531AC155M520DGR

S i 5 3 0 / 5 31 REVISION D C R YS TA L O SCILLATOR (XO) (10 M H Z T O 1 . 4 G H Z ) Features Internal fixed crystal frequency ensures high reliability and low aging Available CMOS, LVPECL, LVDS, and CML outputs 3.3, 2.5, and 1.8 V supply options Industry-standard 5 x 7 mm package and pinout  Pb-free/RoHS-compliant Si5602 Available with any-rate output  frequencies from 10 MHz to 945 MHz and select frequencies to 1.4 GHz  3rd generation DSPLL® with superior  jitter performance   3x better frequency stability than  SAW-based oscillators  Ordering Information: Applications See page 7. SONET/SDH Networking  SD/HD video Test and measurement Clock and data recovery  FPGA/ASIC clock generation     Pin Assignments: See page 6. Description The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL® circuitry to provide a low jitter clock at high frequencies. The Si530/531 is available with any-rate output frequency from 10 to 945 MHz and select frequencies to 1400 MHz. Unlike a traditional XO, where a different crystal is required for each output frequency, the Si530/531 uses one fixed crystal to provide a wide range of output frequencies. This IC based approach allows the crystal resonator to provide exceptional frequency stability and reliability. In addition, DSPLL clock synthesis provides superior supply noise rejection, simplifying the task of generating low jitter clocks in noisy environments typically found in communication systems. The Si530/531 IC based XO is factory configurable for a wide variety of user specifications including frequency, supply voltage, output format, and temperature stability. Specific configurations are factory programmed at time of shipment, thereby eliminating long lead times associated with custom oscillators. Functional Block Diagram V DD CLK– CLK+ (Top View) NC 1 6 VDD OE 2 5 CLK– GND 3 4 CLK+ Si530 (LVDS/LVPECL/CML) OE 1 6 VDD NC 2 5 NC GND 3 4 CLK Si530 (CMOS) Fixed Frequency XO Any-rate 10–1400 MHz DSPLL® Clock Synthesis OE 1 6 VDD NC 2 5 CLK– GND 3 4 CLK+ Si531 (LVDS/LVPECL/CML) OE Rev. 1.5 6/18 GND Copyright © 2018 by Silicon Laboratories Si530/531 Si530/531 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Supply Voltage1 Supply Current Symbol Test Condition Min Typ Max Unit VDD 3.3 V option 2.97 3.3 3.63 V 2.5 V option 2.25 2.5 2.75 V 1.8 V option 1.71 1.8 1.89 V Output enabled LVPECL CML LVDS CMOS — — — — 111 99 90 81 121 108 98 88 Tristate mode — 60 75 mA VIH 0.75 x VDD — — V VIL — — 0.5 V –40 — 85 ºC IDD Output Enable (OE)2 Operating Temperature Range TA mA Notes: 1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 7 for further details. 2. OE pin includes a 17 k pullup resistor to VDD. Table 2. CLK± Output Frequency Characteristics Parameter Nominal Frequency1,2 Initial Accuracy Symbol Test Condition Min Typ Max Unit fO LVPECL/LVDS/CML 10 — 945 MHz CMOS 10 — 160 MHz Measured at +25 °C at time of shipping — ±1.5 — ppm –7 –20 –50 — — — +7 +20 +50 ppm Frequency drift over first year — — ±3 ppm Frequency drift over 20 year life — — ±10 ppm fi Temperature Stability1,3 Aging fa Notes: 1. See Section 3. "Ordering Information" on page 7 for further details. 2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz. 3. Selectable parameter specified by part number. 4. Time from powerup or tristate mode to fO. 2 Rev. 1.5 Si530/531 Table 2. CLK± Output Frequency Characteristics (Continued) Parameter Symbol Total Stability Powerup Time4 Test Condition Min Typ Max Unit Temp stability = ±7 ppm — — ±20 ppm Temp stability = ±20 ppm — — ±31.5 ppm Temp stability = ±50 ppm — — ±61.5 ppm — — 10 ms tOSC Notes: 1. See Section 3. "Ordering Information" on page 7 for further details. 2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz. 3. Selectable parameter specified by part number. 4. Time from powerup or tristate mode to fO. Table 3. CLK± Output Levels and Symmetry Parameter LVPECL Output Symbol Test Condition Min Typ Max Unit VO mid-level VDD – 1.42 — VDD – 1.25 V VOD swing (diff) 1.1 — 1.9 VPP VSE swing (single-ended) 0.55 — 0.95 VPP VO mid-level 1.125 1.20 1.275 V VOD swing (diff) 0.5 0.7 0.9 VPP 2.5/3.3 V option mid-level — VDD – 1.30 — V 1.8 V option mid-level — VDD – 0.36 — V 2.5/3.3 V option swing (diff) 1.10 1.50 1.90 VPP 1.8 V option swing (diff) 0.35 0.425 0.50 VPP VOH IOH = 32 mA 0.8 x VDD — VDD V VOL IOL = 32 mA — — 0.4 V tR, tF LVPECL/LVDS/CML — — 350 ps CMOS with CL = 15 pF — 1 — ns 45 — 55 % Option1 LVDS Output Option2 CML Output Option2 VO VOD CMOS Output Option 3 Rise/Fall time (20/80%) Symmetry (duty cycle) SYM LVPECL: (diff) LVDS: CMOS: VDD – 1.3 V 1.25 V (diff) VDD/2 Notes: 1. 50  to VDD – 2.0 V. 2. Rterm = 100  (differential). 3. CL = 15 pF Rev. 1.5 3 Si530/531 Table 4. CLK± Output Phase Jitter Parameter Symbol Test Condition Min Typ Max Unit Phase Jitter (RMS)1 for FOUT > 500 MHz J 12 kHz to 20 MHz (OC-48) — 0.25 0.40 ps 50 kHz to 80 MHz (OC-192) — 0.26 0.37 ps Phase Jitter (RMS)1 for FOUT of 125 to 500 MHz J 12 kHz to 20 MHz (OC-48) — 0.36 0.50 ps 50 kHz to 80 MHz (OC-192) — 0.34 0.42 ps Phase Jitter (RMS) for FOUT of 10 to 160 MHz CMOS Output Only J 12 kHz to 20 MHz (OC-48)2 — 0.62 — ps 50 kHz to 20 MHz2 — 0.61 — ps 2 Notes: 1. Refer to AN256 for further information. 2. Max offset frequencies: 80 MHz for FOUT > 250 MHz, 20 MHz for 50 MHz < FOUT