534GA622M080BG

Si 5 50 P R E L I M I N A R Y D A TA S H E E T VO L TA G E - C O N T R O L L E D C R Y S TA L O S C I L L A T O R ( V CX O) 10 MH Z T O 1 .4 G H Z Features Available with any-rate output frequencies from 10 MHz to 945 MHz and selected frequencies to 1.4 GHz 3rd generation DSPLL® with superior jitter performance 3x better frequency stability than SAW based oscillators Internal fixed crystal frequency ensures high reliability and low aging Available CMOS, LVPECL, LVDS, & CML outputs 3.3, 2.5, and 1.8 V supply options Industry-standard 5 x 7 mm package and pinout Lead-free/RoHS-compliant Si5602 Ordering Information: See page 8. Applications SONET / SDH xDSL 10 GbE LAN / WAN Low-jitter clock generation Optical modules Clock and data recovery Pin Assignments: See page 7. (Top View) VC 1 2 3 6 5 4 VDD Description The Si550 VCXO utilizes Silicon Laboratories’ advanced DSPLL® circuitry to provide a low-jitter clock at high frequencies. The Si550 is available with any-rate output frequency from 10 to 945 MHz and selected frequencies to 1400 MHz. Unlike traditional VCXO’s where a different crystal is required for each output frequency, the Si550 uses one fixed crystal to provide a wide range of output frequencies. This IC based approach allows the crystal resonator to provide exceptional frequency stability and reliability. In addition, DSPLL clock synthesis provides superior supply noise rejection, simplifying the task of generating low-jitter clocks in noisy environments typically found in communication systems. The Si550 IC-based VCXO is factory configurable for a wide variety of user specifications, including frequency, supply voltage, output format, tuning slope, and temperature stability. Specific configurations are factory programmed at time of shipment, thereby eliminating long lead times associated with custom oscillators. OE GND CLK– CLK+ Functional Block Diagram V DD CLK– CLK+ Fixed Frequency XO A ny-rate 10-1400 MHz DSPLL ® Clock Synthesis A DC Vc OE GND Preliminary Rev. 0.3 4/06 Copyright © 2006 by Silicon Laboratories Si550 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. S i5 50 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Supply Voltage1 Symbol VDD Test Condition 3.3 V option 2.5 V option 1.8 V option Supply Current IDD Output enabled TriState mode Output Enable (OE)2 VIH VIL Operating Temperature Range TA Min 2.97 2.25 1.71 — — 0.75 x VDD — –40 Typ 3.3 2.5 1.8 90 60 — — — Max 3.63 2.75 1.89 — — — 0.5 85 mA V Units V ºC Notes: 1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 8 for further details. 2. OE pin includes a 17 kΩ pullup resistor to VDD. Pulling OE to ground causes outputs to tristate. Table 2. VC Control Voltage Input Parameter Control Voltage Tuning Slope1,2,3 Symbol KV Test Condition 10 to 90% of VDD Min — Typ 45 90 135 180 ±1 ±5 10.0 — 3/8 x VDD Max — Units ppm/V Control Voltage Linearity4 LVC BSL Incremental –5 –10 9.3 500 +5 +10 10.7 — — VDD % kHz kΩ V V Modulation Bandwidth VC Input Impedance Nominal Control Voltage Control Voltage Tuning Range BW ZVC VCNOM VC @ fO — 0 Notes: 1. Positive slope; selectable option by part number. See Section 3. "Ordering Information" on page 8. 2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information. 3. KV variation is ±28% of typical values. 4. BSL determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. Incremental slope determined with VC ranging from 10 to 90% of VDD. 2 Preliminary Rev. 0.3 S i550 Table 3. CLK± Output Frequency Characteristics Parameter Nominal Frequency1,2,3 Symbol fO Test Condition LVDS/CML/LVPECL CMOS Temperature Stability1,4 ∆f/fO TA = –40 to +85 ºC Min 10 10 –20 –50 –100 ±25 Frequency drift over 15 year life. tOSC Typ — — — — — — — — Max 945 160 +20 +50 +100 ±150 ±10 10 Units MHz ppm ppm ppm ms Absolute Pull Range1,4 Aging Power up Time5 APR — — Notes: 1. See Section 3. "Ordering Information" on page 8 for further details. 2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz. 3. Nominal output frequency set by VCNOM = 3/8 x VDD. 4. Selectable parameter specified by part number. 5. Time from power up or tristate mode to fO. Table 4. CLK± Output Levels and Symmetry Parameter LVPECL Output Option1 Symbol VO VOD VSE Test Condition mid-level swing (diff) swing (single-ended) mid-level swing (diff) Min VDD – 1.42 1.1 0.5 1.125 0.32 Typ — Max VDD – 1.25 1.9 0.93 1.275 0.50 Units V VPP VPP V VPP — — 1.20 0.40 LVDS Output Option2 VO VOD CML Output Option2 VO VOD mid-level swing (diff) IOH = 32 mA IOL = 32 mA — 0.70 0.8 x VDD VDD – 0.75 0.95 — — — 1 — 1.20 VDD V VPP V CMOS Output Option3 VOH VOL — — — 0.4 350 — Rise/Fall time (20/80%) tR, tF LVPECL/LVDS/CML CMOS with CL = 15 pF ps ns Preliminary Rev. 0.3 3 S i5 50 Table 4. CLK± Output Levels and Symmetry (Continued) Parameter Symmetry (duty cycle) Symbol SYM Test Condition LVPECL: LVDS: CMOS: VDD – 1.3 V (diff) 1.25 V (diff) VDD/2 Min 45 Typ — Max 55 Units % Notes: 1. 50 Ω to VDD – 2.0 V. 2. Rterm = 100 Ω (differential). 3. CL = 15 pF Table 5. CLK± Output Phase Jitter Parameter Phase Jitter (RMS)1,2,3 for FOUT > 500 MHz Symbol Test Condition Kv = 45 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Kv = 90 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Kv = 135 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Kv = 180 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Phase Jitter (RMS)1,2,3 for FOUT of 125 to 500 MHz Min — — — — — — — — — — — — — — — — Typ 0.35 0.38 0.43 0.41 0.52 0.46 0.64 0.52 0.42 0.58 0.48 0.60 0.57 0.64 0.67 0.68 Max — — — — — — — — ps — — — — — — — — Units ps φJ φJ Kv = 45 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Kv = 90 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Kv = 135 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Kv = 180 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Notes: 1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information. 2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information. 3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply rejection (PSR) advantage of Si55x versus SAW-based solutions. 4 Preliminary Rev. 0.3 S i550 Table 6. CLK± Output Period Jitter Parameter Period Jitter* for FOUT < 160 MHz Symbol JPER Test Condition RMS Peak-to-Peak Min — — Typ 2 14 Max — — Units ps *Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Table 7. CLK± Output Phase Noise (Typical) Configuration fC KV Output Offest Frequency (f) 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 100 MHz –94 –117 –128 –135 –138 –143 n/a 74.25 MHz 45 ppm/V CMOS L (f) –74 –98 –112 –122 –134 –144 –147 –77 –101 –114 –118 –128 –144 –147 300 MHz 90 ppm/V LVPECL 622.08 MHz 45 ppm/V LVPECL Units dBc/Hz Preliminary Rev. 0.3 5 S i5 50 Table 8. Absolute Maximum Ratings Parameter Supply Voltage Input Voltage Storage Temperature ESD Sensitivity (HBM, per JESD22-A114) Soldering Temperature (lead-free profile) Soldering Temperature Time @ TPEAK (lead-free profile) Symbol VDD VI TS ESD TPEAK tP Rating –0.5 to +3.8 –0.5 to VDD + 0.3 –55 to +125 >2500 260 10 Units Volts Volts ºC Volts ºC seconds Note: Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional operation or specification compliance is not implied at these conditions. Table 9. Environmental Compliance The Si550 meets the following qualification test requirements. Parameter Mechanical Shock Mechanical Vibration Solderability Gross & Fine Leak Resistance to Solvents Conditions/ Test Method MIL-STD-883F, Method 2002.3 B MIL-STD-883F, Method 2007.3 A MIL-STD-883F, Method 203.8 MIL-STD-883F, Method 1014.7 MIL-STD-883F, Method 2016 6 Preliminary Rev. 0.3 S i550 2. Pin Descriptions (Top View) VC 1 2 3 6 5 4 VDD OE GND CLK– CLK+ Table 10. Si550 Pin Descriptions Pin 1 2 3 4 5 6 Name VC OE* GND CLK+ CLK– (N/A for CMOS) VDD Type Analog Input Input Ground Output Output Power Control Voltage Output Enable: 0 = clock output disabled (outputs tri-stated) 1 = clock output enabled Electrical and Case Ground Oscillator Output Complementary Output (N/C for CMOS) Power Supply Voltage Function *Note: OE includes 17 kΩ pullup resistor to VDD. Preliminary Rev. 0.3 7 S i5 50 3. Ordering Information The Si550 was designed to support a variety of options including frequency, temperature stability, tuning slope, output format, and VDD. Specific device configurations are programmed into the Si550 at time of shipment. Configurations are specified using the Part Number Configuration chart shown below. Silicon Labs provides a web browser-based part number configuration utility to simplify this process. Refer to www.silabs.com/ VCXOPartNumber to access this tool and for further ordering instructions. The Si550 VCXO series is supplied in an industry-standard, RoHS compliant, lead-free, 6-pad, 5 x 7 mm package. Tape and reel packaging is an ordering option. 550 X X XXXMXXX B G R R = Tape & Reel Blank = Trays Operating Temp Range (°C) G –40 to +85 °C Device Revision Letter 550 VCXO Product Family 1st Option Code Code A B C D E F G H J K VDD 3.3 3.3 DD 3.3 3.3 2.5 2.5 2.5 2.5 1.8 1.8 Output Format LVPECL LVDS CMOS CML LVPECL LVDS CMOS CML CMOS CML Frequency (e.g. 622M080 is 622.080 MHz) Available frequency range is 10 to 945 MHz, 970 to 1134, and 1213 to 1417 MHz. The position of “M” shifts to denote higher or lower frequencies. 2nd Option Code Temperature Stability ± ppm (max) 100 100 50 50 20 50 Tuning Slope Kv ppm/V (typ) 180 90 180 90 45 135 Minimum APR (±ppm) @ 3.3 V @ 2.5 V @ 1.8 V 100 75 25 30 Note 6 Note 6 150 125 75 80 30 25 25 Note 6 Note 6 100 75 50 Code A B C D E F Notes: CMOS available to 160 MHz. Notes: 1. For best jitter and phase noise performance, always choose the smallest Kv that meets the application’s minimum APR requirements. Unlike SAW-based solutions which require higher higher Kv values to account for their higher temperature dependence, the Si55x series provides lower Kv options to minimize noise coupling and jitter in real-world PLL designs. See AN255 and AN266 for more information. 2. APR is the ability of a VCXO to track a signal over the product lifetime. A VCXO with an APR of ±25 ppm is able to lock to a clock with a ±25 ppm stability, over 15 years. 3. Nominal Pull range (±) = 0.5 x VDD x tuning slope. 4. Nominal Absolute Pull Range (±APR) = Pull range – stability – lifetime aging = 0.5 x VDD x tuning slope – stability – 10 ppm 5. Minimum APR values noted above include worst case values for all parameters. 6. Combination not available. Example Part Number: 550AF622M080BGR is a 5 x 7 mm VCXO in a 6 pad package. The nominal frequency is 622.080 MHz, with a 3.3 V supply and LVPECL output. Temperature stability is specified as ±50 ppm and the tuning slope is 135 ppm/V. The part is specified for a –40 to +85 C° ambient temperature range operation and is shipped in tape and reel format. 8 Preliminary Rev. 0.3 S i550 4. Outline Diagram and Suggested Pad Layout Figure 1 illustrates the package details for the Si550. Table 11 lists the values for the dimensions shown in the illustration. Figure 1. Si550 Outline Diagram Table 11. Package Diagram Dimensions (mm) Dimension A b c D D1 e E E1 L S R aaa bbb ccc ddd — — — — 4.30 1.07 6.10 Min 1.45 1.2 Nom 1.65 1.4 0.60 TYP. 7.00 BSC. 6.2 2.54 BSC. 5.00 BSC. 4.40 1.27 1.815 BSC. 0.7 REF. — — — — 0.15 0.15 0.10 0.10 4.50 1.47 6.30 Max 1.85 1.6 Preliminary Rev. 0.3 9 S i5 50 5. 6-Pin PCB Land Pattern Figure 2 illustrates the 6-pin PCB land pattern for the Si550. Table 12 lists the values for the dimensions shown in the illustration. Figure 2. Si550 PCB Land Pattern Table 12. PCB Land Pattern Dimensions (mm) Dimension D2 e E2 GD GE VD VE X Y ZD ZE — — 0.84 2.00 8.20 REF 7.30 REF 1.70 TYP 2.15 REF 6.78 6.30 Min 5.08 REF 2.54 BSC 4.15 REF — — Max Notes: 1. Dimensioning and tolerancing per the ANSI Y14.5M-1994 specification. 2. Land pattern design based on IPC-7351 guidelines. 3. All dimensions shown are at maximum material condition (MMC). 4. Controlling dimension is in millimeters (mm). 10 Preliminary Rev. 0.3 S i550 DOCUMENT CHANGE LIST Revision 0.2 to Revision 0.3 Updated 1. "Electrical Specifications" on page 2. Updated ordering and format of Table 1 through Table 9. Updated LVDS and CML in Table 4, “CLK± Output Levels and Symmetry,” on page 3. Updated RMS jitter values in Table 5, “CLK± Output Phase Jitter,” on page 4. Added Typical Phase Noise performance data in Table 5, “CLK± Output Phase Jitter,” on page 4. Updated 3. "Ordering Information" on page 8. Removed ordering option E at VDD = 2.5 V in table for the 2nd Option Code. Typical APRs replaced with minimum APR values. New 135 ppm/V KV option included. Preliminary Rev. 0.3 11 S i5 50 CONTACT INFORMATION Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: VCXOinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. 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Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 12 Preliminary Rev. 0.3