550AE700M000DGR

Si 5 50 REVISION D VO L TAG E - C ONTR OLLED C RYSTAL O S C I L L A T O R (VCXO) 10 MH Z TO 1 . 4 G H Z Features Available with any frequency from  10 to 945 MHz and select frequencies to 1.4 GHz   3rd generation DSPLL® with superior jitter performance (0.5 ps)  3x better temperature stability than   SAW-based oscillators  Excellent PSRR performance Internal fixed crystal frequency ensures high reliability and low aging Available CMOS, LVPECL, LVDS, and CML outputs 3.3, 2.5, and 1.8 V supply options Industry-standard 5 x 7 mm package and pinout  Pb-free/RoHS-compliant  Si5602 Ordering Information: Applications    See page 10. SONET/SDH xDSL 10 GbE LAN/WAN    Low-jitter clock generation Optical modules Clock and data recovery Pin Assignments: See page 9. Description The Si550 VCXO utilizes Silicon Laboratories’ advanced DSPLL® circuitry to provide a low-jitter clock at high frequencies. The Si550 supports any frequency from 10 to 945 MHz and select frequencies to 1417 MHz. Unlike traditional VCXOs, where a different crystal is required for each output frequency, the Si550 uses one fixed crystal to provide a wide range of output frequencies. This IC-based approach allows the crystal resonator to provide exceptional frequency stability and reliability. In addition, DSPLL clock synthesis provides superior supply noise rejection, simplifying the task of generating low-jitter clocks in noisy environments typically found in communication systems. The Si550 IC-based VCXO is factory-configurable for a wide variety of user specifications, including frequency, supply voltage, output format, tuning slope, and temperature stability. Specific configurations are factory programmed at time of shipment, thereby eliminating the long lead times associated with custom oscillators. (Top View) VC 1 6 VDD OE 2 5 CLK– GND 3 4 CLK+ Functional Block Diagram V DD Any-Frequency 10 MHz–1.4 GHz DSPLL ® Clock Synthesis Fixed Frequency XO Vc CLK– ADC OE Rev. 1.2 6/18 CLK+ GND Copyright © 2018 by Silicon Laboratories Si550 Si5 50 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Supply Voltage1 Symbol Test Condition Min Typ Max Units VDD 3.3 V option 2.97 3.3 3.63 V 2.5 V option 2.25 2.5 2.75 V 1.8 V option 1.71 1.8 1.89 V Output enabled LVPECL CML LVDS CMOS — — — — 120 108 99 90 130 117 108 98 tristate mode — 60 75 mA VIH 0.75 x VDD — — V VIL — — 0.5 V –40 — 85 °C Supply Current Output Enable IDD (OE)2 Operating Temperature Range TA mA Notes: 1. Selectable parameter specified by part number. See 3. "Ordering Information" on page 10 for further details. 2. OE pin includes a 17 k resistor to VDD. Table 2. VC Control Voltage Input Parameter Control Voltage Tuning Slope 1,2,3 Control Voltage Linearity4 Symbol Test Condition Min Typ Max Units KV 10 to 90% of VDD — — — — — — 33 45 90 135 180 356 — — — — — — ppm/V BSL –5 ±1 +5 % Incremental –10 ±5 +10 % LVC Modulation Bandwidth BW 9.3 10.0 10.7 kHz VC Input Impedance ZVC 500 — — k — VDD/2 — V VDD V Nominal Control Voltage Control Voltage Tuning Range VCNOM @ fO 0 VC Notes: 1. Positive slope; selectable option by part number. See 3. "Ordering Information" on page 10. 2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information. 3. KV variation is ±10% of typical values. 4. BSL determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. Incremental slope determined with VC ranging from 10 to 90% of VDD. 2 Rev. 1.2 Si550 Table 3. CLK± Output Frequency Characteristics Parameter Symbol Test Condition Min Typ Max Units fO LVDS/CML/LVPECL 10 — 945 MHz CMOS 10 — 160 MHz TA = –40 to +85 ºC –20 –50 –100 — — — +20 +50 +100 ppm ±12 — ±375 ppm Frequency drift over first year. — — ±3 Frequency drift over 15 year life. — — ±10 — — 10 Nominal Frequency1,2,3 Temperature Stability1,4 Absolute Pull Range1,4 APR Aging Power up Time5 tOSC ppm ms Notes: 1. See Section 3. "Ordering Information" on page 10 for further details. 2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz. 3. Nominal output frequency set by VCNOM = VDD/2. 4. Selectable parameter specified by part number. 5. Time from power up or tristate mode to fO. Table 4. CLK± Output Levels and Symmetry Parameter Symbol Test Condition Min Typ Max Units VO mid-level VDD – 1.42 — VDD – 1.25 V VOD swing (diff) 1.1 — 1.9 VPP VSE swing (single-ended) 0.55 — 0.95 VPP VO mid-level 1.125 1.20 1.275 V VOD swing (diff) 0.5 0.7 0.9 VPP 2.5/3.3 V option mid-level — VDD – 1.30 — V 1.8 V option mid-level — VDD – 0.36 — V 2.5/3.3 V option swing (diff) 1.10 1.50 1.90 VPP 1.8 V option swing (diff) 0.35 0.425 0.50 VPP VOH IOH = 32 mA 0.8 x VDD — VDD V VOL IOL = 32 mA — — 0.4 V tR, tF LVPECL/LVDS/CML — — 350 ps CMOS with CL = 15 pF — 1 — ns 45 — 55 % LVPECL Output Option1 LVDS Output Option 2 VO CML Output Option2 VOD CMOS Output Option 3 Rise/Fall time (20/80%) Symmetry (duty cycle) SYM LVPECL: LVDS: CMOS: VDD – 1.3 V (diff) 1.25 V (diff) VDD/2 Notes: 1. 50  to VDD – 2.0 V. 2. Rterm = 100  (differential). 3. CL = 15 pF Rev. 1.2 3 Si5 50 Table 5. CLK± Output Phase Jitter Parameter 1,2,3 Phase Jitter (RMS) for FOUT > 500 MHz Symbol Test Condition Min Typ Max Units J Kv = 33 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) — — 0.26 0.26 — — ps Kv = 45 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) — — 0.27 0.26 — — ps Kv = 90 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) — — 0.32 0.26 — — ps Kv = 135 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) — — 0.40 0.27 — — ps Kv = 180 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) — — 0.49 0.28 — — ps Kv = 356 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) — — 0.87 0.33 — — ps Notes: 1. Refer to AN255, AN256, and AN266 for further information. 2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information. 3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply rejection (PSR) advantage of Si55x versus SAW-based solutions. 4. Max jitter for LVPECL output with VC=1.65V, VDD=3.3V, 155.52 MHz. 5. Max offset frequencies: 80 MHz for FOUT > 250 MHz, 20 MHz for 50 MHz < FOUT