552GD622M080BGR

Si 5 52 P R E L I M I N A R Y D A TA S H E E T D U A L F R E Q U E N C Y V CXO (10 M H Z T O 1 .4 GH Z ) Features Available with any-rate output frequencies from 10 to 945 MHz and selected frequencies to 1.4 GHz Two selectable output frequencies Industry-standard 7x5 mm package Available CMOS, LVPECL, LVDS & CML outputs 3x better frequency stability than SAW-based oscillators 3rd generation DSPLL® with superior jitter performance Internal fixed crystal frequency ensures high reliability and low aging Lead-free/RoHS-compliant Si5602 Applications SONET / SDH xDSL 10 GbE LAN / WAN Low jitter clock generation Optical Modules Test and Measurement Ordering Information: See page 7. Description The Si552 dual frequency VCXO utilizes Silicon Laboratories advanced DSPLL® circuitry to provide a very low jitter clock for all output frequencies. The Si552 is available with any-rate output frequency from 10 to 945 MHz and selected frequencies to 1400 MHz. Unlike traditional VCXO’s where a different crystal is required for each output frequency, the Si552 uses one fixed crystal frequency to provide a wide range of output frequencies. This IC based approach allows the crystal resonator to be optimized for superior frequency stability and reliability. In addition, DSPLL clock synthesis provides superior supply noise rejection, simplifying the task of generating low jitter clocks in noisy environments often found in communication systems. The Si552 IC based VCXO is factory configurable for a wide variety of user specifications including frequency, supply voltage and output format. Specific configurations are factory programmed into the Si552 at time of shipment, thereby eliminating the long lead times associated with custom oscillators. Functional Block Diagram VDD CLK- CLK+ Fixed Frequency XO Any-rate 10–1400 MHz DSPLL™ Clock Synthesis ADC VC FS GND Preliminary Rev. 0.2 8/05 Copyright © 2005 by Silicon Laboratories Si552 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. S i5 52 1. Electrical Specifications Table 1. Si552 Electrical Specifications Parameter Min Typ Max Units Notes Frequency Nominal Frequency LVDS/CML/LVPECL CMOS Initial Accuracy Temperature Stability 10 10 –1.5 –20 –50 –100 –5 –10 — — — — — — ±1 ±5 945 160 1.5 +20 +50 +100 +5 +10 Specified at time of order by P/N. Also available in bands from 970 to 1134 MHz and 1213 to 1417 MHz. Measured at +25 °C at time of shipping and at VC = VDD/2. Selectable option by P/N. See Section 4. "Ordering Information" on page 7. Measured at VC = VDD/2. BSL determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. Incremental slope determined with VC ranging from 10 to 90% of VDD. Positive slope; selectable option by P/N. See Section 4. "Ordering Information" on page 7. MHz ppm ppm Linearity BSL Incremental % Tuning Slope (kV) from 10 to 90% of VDD Modulation Bandwidth VC Input Impedance Absolute Pull Range (APR) Aging — — — — 500 — — 180 90 45 10 — See Notes — — — — — — — ±10 Outputs ppm/V kHz kΩ — ppm See Section 4. "Ordering Information" on page 7. Projected frequency drift over 15 year life. Symmetry RMS Jitter for FOUT > 500 MHz Kv = 180 ppm/V 12 kHz to 20 MHz 50 kHz to 80 MHz Kv = 45, 90 ppm/V 12 kHz to 20 MHz 50 kHz to 80 MHz 45 — 55 % LVPECL: LVDS: CMOS: VDD – 1.3 V (differential) 1.25 V (differential) VDD/2 — — 0.42 0.34 — — ps FOUT > 500 MHz Differential Modes: LVPECL/LVDS/CML — — 0.28 0.31 — — 2 Preliminary Rev. 0.2 S i552 Table 1. Si552 Electrical Specifications (Continued) Parameter RMS Jitter for FOUT of 125 to 500 MHz 12 kHz to 20 MHz 50 kHz to 80 MHz Period Jitter for FOUT < 160 MHz Peak-to-Peak RMS LVPECL Output Option mid-level swing (diff) swing (single-ended) LVDS Output Option mid-level swing (diff) Min Typ Max Units Notes 125 < FOUT < 500 MHz Differential Modes: LVPECL/LVDS/CML Any output N = 1000 cycles — — — — VDD – 1.42 1.1 0.5 1.125 0.5 0.61 0.52 7 2 — — — 1.2 0.7 — — — — VDD – 1.25 1.9 0.93 1.275 0.9 ps ps V VPP VPP V VPP V VPP V ps ns 50 Ω to VDD – 2.0 V Rterm = 100 Ω (differential) CML Output Option mid-level swing CMOS Output Option VOH VOL — 0.35 0.8xVDD — VDD – 0.36 0.425 — — — 0.5 VDD 0.4 Rterm = 100 Ω (differential) CL = 15 pF Rise/Fall time — 1 Inputs 350 — CML/LVPECL/LVDS at 20% / 80% CMOS Voltage 3.3 V option 2.5 V option 1.8 V option Supply Current Control Voltage (VC) Frequency Select VIL VIH 2.97 2.25 1.71 — 0 0 0.75 x VDD 3.3 2.5 1.8 90 — — — 3.63 2.75 1.89 — VDD 0.5 VDD V Optional parameter specified by P/N mA V V Tuning range for control voltage “0” selects F1 “1” selects F2 Table 2. Absolute Maximum Ratings Parameter Supply Voltage Storage Temperature Symbol VDD TS Rating –0.5 to +3.8 –55 to +125 Units V °C Preliminary Rev. 0.2 3 S i5 52 Table 3. Environmental Conditions Parameter Operating Temperature Mechanical Shock Mechanical Vibration Solderability Gross & Fine Leak Resistance to Solvents Conditions/ Test Method –40 to +85 °C MIL-STD-883F, Method 2002.3 B MIL-STD-883F, Method 2007.3 A MIL-STD-883F, Method 203.8 MIL-STD-883F, Method 1014.7 MIL-STD-883F, Method 2016 Table 4. Pinout Pin 1 2 3 4 5 6 Symbol Vc FS Gnd Output Coutput (N/A for CMOS) VDD Function Control Voltage Frequency Select Ground Oscillator Output Complementary Output (N/C for CMOS) Power Suppy Voltage 4 Preliminary Rev. 0.2 S i552 2. Outline Diagram and Suggested Pad Layout Figure 1 illustrates the package details for the Si552. Table 5 lists the values for the dimensions shown in the illustration. Figure 1. Si550 Outline Diagram Table 5. Package Diagram Dimensions (mm) Dimension A b c D D1 e E E1 L S R aaa bbb ccc ddd — — — — 4.30 1.07 6.10 Min 1.45 1.2 Nom 1.65 1.4 0.60 TYP. 7.00 BSC. 6.2 2.54 BSC. 5.00 BSC. 4.40 1.27 1.815 BSC. 0.7 REF. — — — — 0.15 0.15 0.10 0.10 4.50 1.47 6.30 Max 1.85 1.6 Preliminary Rev. 0.2 5 S i5 52 3. 6-Pin PCB Land Pattern Figure 2 illustrates the 6-pin PCB land pattern for the Si552. Table 6 lists the values for the dimensions shown in the illustration. Figure 2. Si530 PCB Land Pattern Table 6. PCB Land Pattern Dimensions (mm) Dimension D2 e E2 GD GE VD VE X Y ZD ZE — — 0.84 2.00 8.20 REF 7.30 REF 1.70 TYP 2.15 REF 6.78 6.30 Min 5.08 REF 2.54 BSC 4.15 REF — — Max Notes: 1. Dimensioning and tolerancing per the ANSI Y14.5M-1994 specification. 2. Land pattern design based on IPC-7351 guidelines. 3. All dimensions shown are at maximum material condition (MMC). 4. Controlling dimension is in millimeters (mm). 6 Preliminary Rev. 0.2 S i552 4. Ordering Information The Si552 was designed to support a variety of options including frequency, tuning slope, output format, and VDD. Specific device configurations are programmed into the Si552 at time of shipment. A unique part number associated with these options and frequencies will be assigned. The Si552 Dual Frequency VCXO is provided in an industry-standard, 7x5 package. Part numbers for the Si552 Dual Frequency VCXO are determined by following configuration tables. Silicon Labs provides a Windows-based part number configuration tool to simplify this process. Refer to www.silabs.com/VCXO to access this tool and for further ordering instructions. 5 52 X X XXXXXX B X R Tape & Reel Packaging 552 VCXO Product Family Operating Temp Range (°C) G -40 to +85°C Part Revision Letter Frequency Designator Code Two unique frequencies can be specified within the following bands of frequencies: 10 to 945 MHz 970 to 1134 MHz 1213 to 1417 MHz A six digit code will be assigned by SiLabs for the specified combination of frequencies . 1st Option Code A B C D E F G H J K VDD 3.3 3.3 3.3 3.3 2.5 2.5 2.5 2.5 1.8 1.8 Output Format LVPECL LVDS CMOS CML LVPECL LVDS CMOS CML CMOS CML 2nd Option Code (VCXO) T emp Stability Tuning Slope (ppm, max, ±) (Kv,ppm/V , typ ,) APR(typ)@3.3V APR(typ )@2.5V APR(typ )@1.8V A 100 180 185 115 50 B 100 90 38 Note 3 Note 3 C 50 180 235 165 100 D 50 90 85 50 20 E 20 45 40 25 Note 3 Notes: 1. Pull range (±) = 0.5 x VDD x tuning slope . 2. Absolute Pull Range (± APR) = Pull range – stability – lifetime aging = 0.5xV DD x tuning slope – stability – 10 ppm 3. Combination not available . APR is the ability of a VCXO to track a signal over the product lifetime . Thus, a VCXO with an APR of 50 ppm is able to lock to a clock with 50 ppm stability, for a 15 year life. Notes: CMOS available to 160 MHz. Preliminary Rev. 0.2 7 S i5 52 CONTACT INFORMATION Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: VCXOinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 8 Preliminary Rev. 0.2