590AB70M6560DG

S i 5 9 0 / 5 91 1 ps M AX J I T T E R C RYSTAL O SC ILLA TOR (XO) (10 M H Z TO 810 MH Z ) Features  Available with any-frequency output  frequencies from 10 to 810 MHz  3rd generation DSPLL® with superior   jitter performance: 1 ps max jitter  Better frequency stability than SAW based oscillators   Internal fundamental mode crystal ensures high reliability Si5602 Available CMOS, LVPECL, LVDS, and CML outputs 3.3, 2.5, and 1.8 V supply options Industry Standard 5x7 and 3.2x5 mm packages Pb-free/RoHS-compliant –40 to +85 ºC operating temperature range Ordering Information: Applications See page 8.     SONET/SDH (OC-3/12/48) Networking  SD/HD SDI/3G SDI video Test and measurement Storage  FPGA/ASIC clock generation Description The Si590/591 XO utilizes Silicon Laboratories’ advanced DSPLL® circuitry to provide a low jitter clock at high frequencies. The Si590/591 supports any frequency from 10 to 810 MHz. Unlike a traditional XO, where a unique crystal is required for each output frequency, the Si590/591 uses one fixed crystal to provide a wide range of output frequencies. This IC based approach allows the crystal resonator to provide exceptional frequency stability and reliability. In addition, DSPLL clock synthesis provides superior supply noise rejection, simplifying the task of generating low jitter clocks in noisy environments typically found in communication systems. The Si590/591 IC based XO is factory configurable for a wide variety of user specifications including frequency, supply voltage, output format, and stability. Specific configurations are factory programmed at time of shipment, thereby eliminating long lead times associated with custom oscillators. Pin Assignments: See page 7. (Top View) NC 1 6 VDD OE 2 5 CLK– GND 3 4 CLK+ Si590 (LVDS/LVPECL/CML) OE 1 6 VDD NC 2 5 NC GND 3 4 CLK Functional Block Diagram VDD CLK– CLK+ Si590 (CMOS) 17 k * Fixed Frequency XO OE Any-rate 10–810 MHz DSPLL® Clock Synthesis 17 k * GND Rev. 1.2 6/18 *Note: Output Enable High/Low Options Available – See Ordering Information Copyright © 2018 by Silicon Laboratories OE 1 6 VDD NC 2 5 CLK– GND 3 4 CLK+ Si591 (LVDS/LVPECL/CML) Si590/591 Si590/591 TABLE O F C ONTENTS 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4. Package Outline Drawing: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 5. PCB Land Pattern: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 6. Package Outline Drawing: 3.2 x 5 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7. PCB Land Pattern: 3.2 x 5 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8. Si590/Si591 Top Marking: 5 x 7 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 9. Si590/Si591 Top Marking: 3.2 x 5 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2 Rev. 1.2 Si590/591 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Supply Voltage1 Symbol Test Condition Min Typ Max VDD 3.3 V option 2.97 3.3 3.63 2.5 V option 2.25 2.5 2.75 1.8 V option 1.71 1.8 1.89 Output enabled LVPECL CML LVDS CMOS — — — — 110 100 90 80 125 110 100 90 Tristate mode — 60 75 VIH 0.75 x VDD — — VIL — — 0.5 –40 — 85 Supply Current Output Enable (OE) IDD 2 Operating Temperature Range TA Units V mA V ºC Notes: 1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 8 for further details. 2. OE pin includes an internal 17 k pullup resistor to VDD for output enable active high or a 17 k pull-down resistor to GND for output enable active low. See 3. "Ordering Information" on page 8. Table 2. CLK± Output Frequency Characteristics Parameter Nominal Frequency1,2 Initial Accuracy Symbol Test Condition Min Typ Max fO LVPECL/LVDS/CML 10 — 810 CMOS Measured at +25 °C at time of shipping Note 3, second option code “D” Note 3, second option code “C” Note 4, second option code “B” Note 4, second option code “A” second option code “D” second option code “C” second option code “B” second option code “A” 10 — 160 — ±1.5 — ppm — — ±20 ppm — — ±30 ppm — — ±50 ppm — — ±100 ppm — — ±7 ppm fi Total Stability Temperature Stability Powerup Time5 tOSC Units MHz — — ±20 ppm — — ±25 ppm — — ±50 ppm — — 10 ms Notes: 1. See Section 3. "Ordering Information" on page 8 for further details. 2. Specified at time of order by part number. 3. Includes initial accuracy, temperature, shock, vibration, power supply and load drift, and 10 years aging at 40 °C. See 3. "Ordering Information" on page 8. 4. Includes initial accuracy, temperature, shock, vibration, power supply and load drift, and 15 years aging at 70 °C. See 3. "Ordering Information" on page 8. 5. Time from powerup or tristate mode to fO. Rev. 1.2 3 Si590/591 Table 3. CLK± Output Levels and Symmetry Parameter LVPECL Output Option LVDS Output Option Symbol Test Condition Min Typ Max Units VO mid-level VDD – 1.42 — VDD – 1.25 V VOD swing (diff) 1.1 — 1.9 VPP VSE swing (single-ended) 0.55 — 0.95 VPP VO mid-level 1.125 1.20 1.275 V VOD swing (diff) 0.5 0.7 0.9 VPP 2.5/3.3 V option mid-level — VDD – 1.30 — 1.8 V option mid-level — VDD – 0.36 — 2.5/3.3 V option swing (diff) 1.10 1.50 1.90 1.8 V option swing (diff) 0.35 0.425 0.50 VOH 0.8 x VDD — VDD VOL — — 0.4 LVPECL/LVDS/CML — — 350 ps CMOS with CL = 15 pF — 2 — ns 45 — 55 % 1 2 VO CML Output Option2 VOD CMOS Output Option3 Rise/Fall time (20/80%) Symmetry (duty cycle) tR, tF SYM LVPECL: LVDS: CMOS: VDD – 1.3 V (diff) 1.25 V (diff) VDD/2 V VPP V Notes: 1. 50  to VDD – 2.0 V. 2. Rterm = 100  (differential). 3. CL = 15 pF. Sinking or sourcing 12 mA for VDD = 3.3 V, 6 mA for VDD = 2.5 V, 3 mA for VDD = 1.8 V. Table 4. CLK± Output Phase Jitter Parameter Symbol Test Condition Min Typ Max Units Phase Jitter (RMS) for 50 MHz < FOUT < 810 MHz (LVPECL/LVDS/CML) J 12 kHz to 20 MHz — 0.5 1.0 ps Phase Jitter (RMS)1 (LVPECL/LVDS/CML) J 12 kHz to 20 MHz, 155.52 MHz output frequency — 0.4 0.7 ps Phase Jitter (RMS)2 for 50 MHz < FOUT < 160 MHz (CMOS) J 12 kHz to 20 MHz — 0.6 1.0 ps 1 Notes: 1. Refer to AN256 for further information. 2. Single-ended CMOS output phase jitter measured using 33  series termination into 50  phase noise test equipment. 3.3 V supply voltage option only. 4 Rev. 1.2 Si590/591 Table 5. CLK± Output Period Jitter Parameter Symbol Test Condition Min Typ Max Units JPER RMS — — 3 ps Peak-to-Peak — — 35 Period Jitter* *Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information. \ Table 6. Environmental Compliance and Package Information Parameter Conditions/Test Method Mechanical Shock MIL-STD-883, Method 2002 Mechanical Vibration MIL-STD-883, Method 2007 Solderability MIL-STD-883, Method 2003 Gross and Fine Leak MIL-STD-883, Method 1014 Resistance to Solder Heat MIL-STD-883, Method 2036 Contact Pads Gold over Nickel Table 7. Thermal Characteristics (Typical values TA = 25 ºC, VDD = 3.3 V) Parameter Symbol Test Condition Min Typ Max Unit 5x7mm, Thermal Resistance Junction to Ambient JA Still Air — 84.6 — °C/W 5x7mm, Thermal Resistance Junction to Case JC Still Air — 38.8 — °C/W 3.2x5mm, Thermal Resistance Junction to Ambient JA Still Air — 31.1 — °C/W 3.2x5mm, Thermal Resistance Junction to Case JC Still Air — 13.3 — °C/W Ambient Temperature TA –40 — 85 °C Junction Temperature TJ — — 125 °C Rev. 1.2 5 Si590/591 Table 8. Absolute Maximum Ratings1 Symbol Rating Units TAMAX 85 ºC Supply Voltage, 1.8 V Option VDD –0.5 to +1.9 V Supply Voltage, 2.5/3.3 V Option VDD –0.5 to +3.8 V Input Voltage (any input pin) VI –0.5 to VDD + 0.3 V Storage Temperature TS –55 to +125 ºC ESD 2500 V TPEAK 260 ºC tP 20–40 seconds Parameter Maximum Operating Temperature ESD Sensitivity (HBM, per JESD22-A114) Soldering Temperature (Pb-free profile) 2 Soldering Temperature Time @ TPEAK (Pb-free profile)2 Notes: 1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device reliability. 2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download at www.silabs.com/VCXO for further information, including soldering profiles. 6 Rev. 1.2 Si590/591 2. Pin Descriptions (Top View) NC 1 6 VDD OE 1 6 VDD OE 1 6 VDD OE 2 5 CLK– NC 2 5 NC NC 2 5 CLK– GND 3 4 CLK+ GND 3 4 CLK GND 3 4 CLK+ Si590 LVDS/LVPECL/CML Si590 Si591 CMOS LVDS/LVPECL/CML Table 9. Pinout for Si590 Series Pin Symbol LVDS/LVPECL/CML Function CMOS Function 1 OE* No connection Make no external connection to this pin Output enable 2 OE* Output enable No connection Make no external connection to this pin 3 GND Electrical and Case Ground Electrical and Case Ground 4 CLK+ Oscillator Output Oscillator Output 5 CLK– Complementary Output No connection Make no external connection to this pin 6 VDD Power Supply Voltage Power Supply Voltage *Note: OE pin includes an internal 17 k pullup resistor to VDD for output enable active high or a 17 k pulldown resistor to GND for output enable active low. See 3. "Ordering Information" on page 8. Table 10. Pinout for Si591 Series Pin Symbol LVDS/LVPECL/CML Function 1 OE* Output enable 2 No connection Make no external connection to this pin No connection Make no external connection to this pin 3 GND Electrical and Case Ground 4 CLK+ Oscillator Output 5 CLK– Complementary output 6 VDD Power Supply Voltage *Note: OE pin includes an internal 17 k pullup resistor to VDD for output enable active high or a 17 k pulldown resistor to GND for output enable active low. See 3. "Ordering Information" on page 8. Rev. 1.2 7 Si590/591 3. Ordering Information The Si590/591 XO supports a variety of options including frequency, temperature stability, output format, and VDD. Specific device configurations are programmed into the Si590/591 at time of shipment. Configurations can be specified using the Part Number Configuration chart below. Silicon Laboratories provides a web browser-based part number configuration utility to simplify this process. To access this tool refer to www.silabs.com/oscillators and click “Customize” in the product table. The Si590 and Si591 XO series are supplied in an industry-standard, RoHS compliant, 6-pad, 5 x 7 mm and 3.2 x 5 mm packages. The Si591 Series supports an alternate OE pinout (pin #1) for LVPECL, LVDS, and CML output formats. See Tables 9 and 10 for the pinout differences between the Si590 and Si591 series. 59x X X XXXMXXX D G R Tape and Reel Packaging Blank = Coil Tape 590 or 591 XO Product Family Operating Temp Range (°C) G –40 to +85°C Part Revision Letter 1st Option Code A B C D E F G H J K M N P Q R S T U V W VDD 3.3 3.3 3.3 3.3 2.5 2.5 2.5 2.5 1.8 1.8 3.3 3.3 3.3 3.3 2.5 2.5 2.5 2.5 1.8 1.8 Output Format Output Enable Polarity LVPECL High LVDS High CMOS High CML High LVPECL High LVDS High CMOS High CML High CMOS High CML High LVPECL Low LVDS Low CMOS Low CML Low LVPECL Low LVDS Low CMOS Low CML Low CMOS Low CML Low Frequency (e.g., 148M352 is 148.352 MHz) Available frequency range is 10 to 810 MHz. The position of “M” shifts to denote higher or lower frequencies. If the frequency of interest requires greater than 6 digit resolution, a six digit code will be assigned for the specific frequency . 2 Code A B C D E F G nd Option Code Package Total Stablility (ppm, max, ±) 5x7 mm 100 5x7 mm 50 5x7 mm 30 5x7 mm 20 3.2x5 mm 100 3.2x5 mm 50 3.2x5 mm 30 Temperature Stablility (ppm, max, ±) 50 25 20 7 50 25 20 Note: CMOS available to 160 MHz. Example P/N: 590BB148M352DGR is a 5 x 7 XO in a 6 pad package. The frequency is 148.352 MHz, with a 3.3 V supply, LVDS output, and Output Enable active high polarity . Overall stability is specifed as ± 50 ppm. The device is specified for –40 to +85 °C ambient temperature range operation and is shipped in tape and reel format . Figure 1. Part Number Convention 8 Rev. 1.2 Si590/591 4. Package Outline Drawing: 5 x 7 mm, 6-pin Figure 2 illustrates the package details for the 5 x 7 mm Si590/591. Table 11 lists the values for the dimensions shown in the illustration. Figure 2. Si590/591 Outline Diagram Table 11. Package Diagram Dimensions (mm) Dimension Min Nom Max A 1.50 1.65 1.80 b 1.30 1.40 1.50 c 0.50 0.60 0.70 D D1 5.00 BSC 4.30 4.40 e 2.54 BSC E 7.00 BSC 4.50 E1 6.10 6.20 6.30 H 0.55 0.65 0.75 L 1.17 1.27 1.37 L1 0.05 0.10 0.15 p 1.80 — 2.60 R 0.70 REF aaa 0.15 bbb 0.15 ccc 0.10 ddd 0.10 eee 0.05 Rev. 1.2 9 Si590/591 5. PCB Land Pattern: 5 x 7 mm, 6-pin Figure 3 illustrates the 6-pin PCB land pattern for the 5 x 7 mm Si590/591. Table 12 lists the values for the dimensions shown in the illustration. Figure 3. Si590/591 PCB Land Pattern Table 12. PCB Land Pattern Dimensions (mm) Dimension (mm) C1 4.20 E 2.54 X1 1.55 Y1 1.95 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 10 Rev. 1.2 Si590/591 6. Package Outline Drawing: 3.2 x 5 mm, 6-pin Figure illustrates the package details for the 3.2 x 5 mm Si590/591. Table 13 lists the values for the dimensions shown in the illustration. Figure 4. Si590/591 Outline Diagram Table 13. Package Diagram Dimensions (mm) Dimension A A1 A2 A3 b B1 D D1 D2 e E Min 1.02 0.99 0.54 0.35 Nom 1.17 1.10 0.5 BSC 0.30 BSC Max 1.32 1.21 0.64 0.45 5.00 BSC 4.65 BSC 3.38 BSC 1.27 BSC 3.20 BSC 0.74 0.55 Dimension E1 E2 L L2 R1 aaa bbb ccc ddd eee Min 0.35 0.05 Nom 2.85 BSC 1.91 BSC 0.45 0.10 0.10 REF 0.15 0.15 0.08 0.10 0.05 Max 0.55 0.15 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. Rev. 1.2 11 Si590/591 7. PCB Land Pattern: 3.2 x 5 mm, 6-pin Figure 5 illustrates the 6-pin PCB land pattern for the 3.2 x 5 mm Si590/591. Table 14 lists the values for the dimensions shown in the illustration. Figure 5. Si590/591 PCB Land Pattern Table 14. PCB Land Pattern Dimensions (mm) Dimension (mm) C1 2.91 E 1.27 X1 0.80 Y1 1.10 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. 12 Rev. 1.2 Si590/591 8. Si590/Si591 Top Marking: 5 x 7 mm Figure 6 illustrates the mark specification for the 5 x 7 mm Si590/Si591. Table 15 lists the line information.   Figure 6. Top Mark Specification Table 15. Si59x Top Mark Description Line Position Description 1 1–10 “SiLabs”+ Part Family Number, 59x (First 3 characters in part number where x = 0 indicates a 590 device and x = 1 indicates a 591 device) 2 1–10 Si590, Si591: Option1 + Option2 + Freq(7) + Temp Si590/Si591 w/ 8-digit resolution: Option1 + Option2 + ConfigNum(6) + Temp 3 Trace Code Position 1 Pin 1 orientation mark (dot) Position 2 Product Revision (D) Position 3–6 Tiny Trace Code (4 alphanumeric characters per assembly release instructions) Position 7 Year (least significant year digit), to be assigned by assembly site (ex: 2009 = 9) Position 8–9 Calendar Work Week number (1–53), to be assigned by assembly site Position 10 “+” to indicate Pb-Free and RoHS-compliant Rev. 1.2 13 Si590/591 9. Si590/Si591 Top Marking: 3.2 x 5 mm Figure 7 illustrates the mark specification for the 3.2 x 5 mm Si590/Si591. Table 16 lists the line information. Figure 7. Top Mark Specification Table 16. Si59x Top Mark Description Line Position Description 1 1–5 “Si”+ Part Family Number, 59x (First 3 characters in part number where x = 0 indicates a 590 device and x = 1 indicates a 591 device) 6–8 Crystal trace code (3 alphanumeric characters assigned by assembly site) 1–9 Si590, Si591: Option1 + Option2 + Freq(7) Si590/Si591 w/ 8-digit resolution: Option1 + Option2 + ConfigNum(6) 2 3 14 Trace Code Position 1 Pin 1 orientation mark (dot) Position 2 Product Revision (D) Position 3–5 Tiny Trace Code (3 alphanumeric characters per assembly release instructions) Position 6–7 Year (last two digits of year), to be assigned by assembly site (ex: 20017 = 17) Position 8–9 Calendar Work Week number (1–53), to be assigned by assembly site Rev. 1.2 Si590/591 REVISION HISTORY Revision 1.2 June, 2018  Changed “Trays” to “Coil Tape” in 3. "Ordering Information" on page 8. Revision 1.1 December, 2017  Added 3.2 x 5 mm package. Revision 1.0      Updated 2.5 V/3.3 V and 1.8 V CML output level specifications in Table 3 on page 4. Updated Si590/591 devices to support frequencies up to 810 MHz for LVPECL, LVDS, and CML outputs. Separated 1.8 V, 2.5 V/3.3 V supply voltage. specifications for CML output in Table 3 on page 4. Updated Note 1 of Table 4 on page 4 to refer to AN256. Updated Table 4 on page 4. Updated phase jitter specification.  Updated Table 6 on page 5 to include the "Moisture Sensitivity Level" and "Contact Pads" rows.  Updated Figure 3 and Table 15 on page 13 to reflect specific marking information.  Added Table 7, “Thermal Characteristics,” on page 5.  Rearranged sections to conform to new quality standard. Revision 0.4  Added ±7 ppm temperature stability ordering option in Table 4 on page 4 and Figure 1 on page 8. Revision 0.3  Updated Table 4 on page 4 by adding the 155.51 MHz “Phase Jitter (RMS) (LVPECL/LVDS/CML)” row.  Updated and clarified Table 6 on page 5 to correct typos and include the “Moisture Sensitivity Level” and “Contact Pads” rows.  Corrected BSC value in rows D and E in Table 11 on page 9. Revision 0.25  Total Stability Maximum changed to ±30 in Table 2 on page 3.  Total Stability Maximum changed to ±30 in Figure 1 on page 8. Rev. 1.2 15 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. 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