C8051F121

C8051F121 100 MIPS, 128 kB Flash, 12-Bit ADC, 64-Pin Mixed-Signal MCU Analog Peripherals 12-Bit ADC High-Speed 8051 µC Core - - ±1 LSB INL; no missing codes Programmable throughput up to 100 ksps 8 external inputs; programmable as single-ended or differential Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5 Data-dependent windowed interrupt generator Built-in temperature sensor (±3 °C) ±1 LSB INL; no missing codes Programmable throughput up to 500 ksps 8 external inputs Programmable amplifier gain: 4, 2, 1, 0.5 Can synchronize outputs to timers for jitter-free waveform generation Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks Up to 100 MIPS throughput with 100 MHz system clock 16 x 16 multiply/accumulate engine (2-cycle) 8448 bytes data RAM 128 kB Flash; in-system programmable in 1024-byte sectors (1024 bytes are reserved) External parallel data memory interface 32 port I/O; all are 5 V tolerant Hardware SMBus™ (I2C™ Compatible), SPI™, and two UART serial ports available concurrently Programmable 16-bit counter/timer array with six capture/compare modules 5 general-purpose 16-bit counter/timers Dedicated watchdog timer; bidirectional reset Real-time clock mode using Timer 3 or PCA Internal oscillator: 24.5 MHz, 2% accuracy supports UART operation On-chip programmable PLL: up to 100 MHz External oscillator: Crystal, RC, C, or Clock Typical operating current: 50 mA at 100 MHz Typical stop mode current: 0.4 uA Memory 8-Bit ADC Digital Peripherals Two 12-Bit DACs Two Comparators Internal Voltage Reference VDD Monitor/Brown-out Detector On-Chip JTAG Debug & Boundary Scan - On-chip debug circuitry facilitates full speed, non-intrusive in-system debug (no emulator required) Provides breakpoints, single stepping, watchpoints, stack monitor Inspect/modify memory and registers Superior performance to emulation systems using ICE-chips, target pods, and sockets IEEE1149.1 compliant boundary scan Clock Sources Supply Voltage: 3.0 to 3.6 V 64-Pin TQFP Temperature Range: –40 to +85 °C VDD VDD VDD DGND DGND DGND AV+ AGND Digital Power Analog Power TCK TMS TDI TDO RST JTAG Logic Boundary Scan Debug HW Reset 8 0 5 1 C o r e SFR Bus 256 Byte Branch Target Buffer Prefetch HW 32 UART0 UART1 SMBus SPI Bus PCA Timers 0, 1, 2, 4 Timer 3 P0, P1, P2, P3 Latches REFADC VDD P0 Drv P0.0 P0.7 8 MONEN VDD Monitor External Oscillator Circuit Internal 2% Oscillator WDT 128 kB FLASH 256 B RAM 8 kB XRAM External Data Memory Bus 16 x 16 Mult/Acc (2-cycle) C R O S S B A R P1 Drv P1.0/AIN1.0 P1.7/AIN1.7 P2 Drv P2.0 P2.7 P3 Drv P3.0 P3.7 XTAL1 XTAL2 System Clock N/M PLL VREF DAC1 (12-Bit) DAC0 (12-Bit) ADC 500 ksps (8-Bit) Prog Gain VREF A M U X 8:1 DAC1 Bus Control DAC0 VREFA AIN0.0 AIN0.1 AIN0.2 AIN0.3 AIN0.4 AIN0.5 AIN0.6 AIN0.7 CP0+ CP0CP1+ CP1- C T L P4 Latch P4 DRV REFADC A M U X Prog Gain ADC 100 ksps (12-Bit) Address Bus A d d r D a t a P5 Latch P6 Latch P5 DRV P6 DRV TEMP SENSOR Data Bus P7 Latch CP0 P7 DRV CP1 Precision Mixed Signal Copyright © 2004 by Silicon Laboratories 6.15.2004 C8051F121 100 MIPS, 128 kB Flash, 12-Bit ADC, 64-Pin Mixed-Signal MCU Selected Electrical Specifications (TA = –40 to +85 C°, VDD = 3.0 V unless otherwise specified) PARAMETER CONDITIONS GLOBAL CHARACTERISTICS Supply Voltage Supply Current Clock = 100 MHz (CPU active) Clock = 1 MHz Clock = 32 kHz Supply Current Oscillator off; VDD Monitor Enabled (shutdown) Oscillator off; VDD Monitor Disabled Clock Frequency Range INTERNAL CLOCKS Oscillator Frequency PLL Frequency A/D CONVERTER Resolution Integral Nonlinearity Differential Nonlinearity Guaranteed Monotonic Signal-to-Noise Plus Distortion Throughput Rate D/A CONVERTERS Resolution Differential Nonlinearity Guaranteed Monotonic Output Settling Time MIN 3.0 TYP MAX 3.6 UNITS V mA mA µA µA µA MHz MHz MHz bits LSB LSB dB ksps bits LSB µS 50 0.6 16 10 0.4 DC 24.0 96 24.5 98 12 ±1 ±1 66 69 100 12 ±1 10 100 25.0 100 Package Information D D1 C8051F120DK Development Kit MIN NOM MAX (mm) (mm) (mm) A - - 1.20 0.15 1.05 A1 0.05 E1 E A2 0.95 b 0.17 0.22 0.27 12.00 10.00 0.50 12.00 10.00 - 64 PIN 1 DESIGNATOR 1 A2 e A b A1 D D1 e E E1 Precision Mixed Signal Copyright © 2004 by Silicon Laboratories 6.15.2004 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders