C8051F231

C8051F231 25 MIPS, 8 kB Flash, 32-Pin Mixed-Signal MCU Analog Peripherals Two comparators High-Speed 8051 µC Core - - Programmable hysteresis Configurable to generate interrupts or reset VDD Monitor and Brown-out Detector Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks Up to 25 MIPS throughput with 25 MHz system clock Expanded interrupt handler; up to 21 interrupt sources 256 bytes data RAM 8 kB Flash; in-system programmable in 512 byte sectors (512 bytes are reserved) 22 port I/O; all are 5 V tolerant Hardware SPI™ and UART serial ports available concurrently 3 general-purpose 16-bit counter/timers Dedicated watchdog timer; bidirectional reset Internal programmable oscillator: 2–16 MHz External oscillator: Crystal, RC, C, or Clock Can switch between clock sources on-the-fly 32-pin LQFP (standard lead and lead-free packages) Lead-free package: C8051F231-GQ Standard package: C8051F231 On-Chip JTAG Debug Memory On-chip emulation circuitry facilitates full-speed, non-intrusive, in-circuit emulation Supports breakpoints, single stepping, watchpoints, inspect/modify memory, and registers Superior performance to emulation systems using ICE-chips, target pods, and sockets Fully compliant with IEEE 1149.1 specification Typical operating current: 9 mA at 25 MHz Typical stop mode current: