C8051F300-GDI

C8051F300-GDI 8 kB Flash, 8-Bit ADC MCU Die in Wafer Form Analog Peripherals - 8-Bit ADC High Speed 8051 µc Core - Pipelined instruction architecture; executes 70% of Up to 500 ksps Up to 8 external inputs • Programmable amplifier gains of 4, 2, 1, & 0.5 • VREF from external pin or VDD • Built-in temperature sensor • External conversion start input Comparator • Programmable hysteresis and response time • Configurable as interrupt or reset source • Low current (0.5 µA) - Up to 25 MIPS throughput with 25 MHz clock - Expanded interrupt handler Memory - 256 bytes internal data RAM - 8 kB Flash; 512 bytes are reserved in the 8 kB devices Digital Peripherals - 8 Port I/O; All 5 V tolerant with high sink current - Hardware enhanced UART and SMBus™ serial - Supply Voltage 2.7 to 3.6 V - Typical operating current: 6.6 mA @ 25 MHz; ports Three general-purpose 16-bit counter/timers 16-bit programmable counter array (PCA) with three capture/compare modules Real time clock mode using PCA or timer and external clock source Clock Sources - Internal oscillator: 24.5 MHz with ±2% accuracy 14 µA @ 32 kHz Typical stop mode current: 0.1 µA Temperature range: –40 to +85 °C supports UART operation External oscillator: Crystal, RC, C, or clock (1 or 2 pin modes) Can switch between clock sources on-the-fly; Useful in power saving modes fo r Full Technical Data Sheet - C8051F300/1/2/3/4/5 - m en de d - ANALOG PERIPHERALS N ot R ec om A M U X Rev. 1.1 4/12 PGA 8-bit 500 ksps ADC C8051F300/2 only + TEMP SENSOR - VOLTAGE COMPARATOR DIGITAL I/O UART SMBus PCA Timer 0 Timer 1 I/O Port - intrusive in-system debug (no emulator required) Provides breakpoints, single stepping, inspect/modify memory and registers Superior performance to emulation systems using ICE-chips, target pods, and sockets N ew - D On-chip Debug - On-chip debug circuitry facilitates full speed, non- CROSSBAR - es ig ns instructions in 1 or 2 system clocks • • Timer 2 PROGRAMMABLE PRECISION INTERNAL OSCILLATOR HIGH-SPEED CONTROLLER CORE 8/4/2 kBytes ISP Flash 12 INTERRUPTS 8051 CPU (25MIPS) DEBUG CIRCUITRY 256 B SRAM POR Copyright © 2012 by Silicon Laboratories WDT C8051F300-GDI N ot m en de d om ec R 2 *Note: 512 bytes reserved for factory use. fo r MIPS (Peak) Flash Memory (kB)* RAM (Bytes) SMBus/I2C UART Timers (16-bit) Programmable Counter Array C8051F300-GDI 25 8 256 1 1 3  Rev. 1.1 8-bit 500 ksps ADC Programmable Current Reference 8   Analog Comparators Lead-free (RoHS Compliant)  1  Package Table 1.1. Product Selection Guide es ig ns Temperature Sensor D Digital Port I/Os N ew Ordering Part Number C8051F300-GDI 1. Ordering Information Tested Die in Wafer Form C8051F300-GDI 2. Pin Definitions Physical Pad Number Type VREF / 3 A In D I/O or A In P0.1 4 VDD 5 XTAL1 / 6 P0.2 External Voltage Reference Input. Port 0.0. D I/O or A Port 0.1. In Power Supply Voltage. A In Crystal Input. This pin is the external oscillator circuit return for a crystal or ceramic resonator. D I/O or A In Port 0.2. 7 A Out Crystal Input/Output. For an external crystal or resonator, this pin is the excitation driver. This pin is the external clock input for CMOS, capacitor, or RC network configurations. D I/O Port 0.3. P0.3 P0.4 P0.5 RST ec P0.6 / 13 D I/O or A Port 0.4. In 14 D I/O or A Port 0.5. In 15 om C2CK / m en de d fo r XTAL2 / N ew P0.0 Description D Name es ig ns Table 2.1. Pin Definitions for the C8051F300-GDI 16 R CNVSTR C2D / 17 N ot P0.7 GND D I/O Clock signal for the C2 Development Interface. D I/O Device Reset. Open-drain output of internal POR or VDD monitor. An external source can initiate a system reset by driving this pin low for at least 10 µs. D I/O or A In D I/O ADC External Convert Start Input Strobe. D I/O Data signal for the C2 Development Interface. D I/O or A In 18 Port 0.6. Port 0.7. Ground. Rev. 1.1 3 C8051F300-GDI 3. Bonding Instructions Example Package Pin Number (11-QFN) 1 Reserved* –1001.5 2 Reserved* –926.5 3 1 VREF/P0.0 –795.5 4 2 P0.1 –615.5 5 3 VDD 346.17 6 4 XTAL1/P0.2 615.5 –575 7 5 XTAL2/P0.3 795.5 –575 8 Reserved* 926.5 –575 9 Reserved* N ew –575 1001.5 –575 10 Reserved* 1000 –429.57 11 Reserved* 1001.5 575 12 Reserved* 926.5 575 15 16 17 18 19 –575 –575 D –575 –575 P0.4 790.5 575 7 P0.5 620.5 575 8 /RST/C2CK 440.5 575 9 P0.6/CNVSTR –523.5 575 10 C2D/P0.7 –703.5 575 11 GND –834.5 575 Reserved* –926.5 575 Reserved* –1001.5 575 N ot R ec *Note: Pins marked “Reserved” should not be connected. 4 Physical Pad Y (µm) 6 om 20 m en de d 14 Physical Pad X (µm) fo r Physical Pad Number 13 Package Pin Name es ig ns Table 3.1. C8051F300-GDI Pad Connections Rev. 1.1 m en de d fo r N ew D es ig ns C8051F300-GDI N ot R ec om Figure 3.1. Example Die Bonding (QFN-11) Rev. 1.1 5 C8051F300-GDI Table 3.2. Wafer and Die Information 8 in Wafer Dimensions es ig ns C8051F300 Wafer ID 1.40 mm x 2.2 mm Wafer Thickness 12 mil ±1 mil Wafer Identification Notch Scribe Line Width 80 µm Standard Passivation Wafer Jar Wafer Packaging Detail 60 µm x 60 µm Bond Pad Dimensions m en de d fo r Maximum Processing Temperature Bond Pad Pitch Minimum N ew Contact Sales for info Die Per Wafer* Electronic Die Map Format D Die Dimensions 250 °C .txt 75 µm N ot R ec om *Note: This is the Expected Known Good Die yielded per wafer and represents the batch order quantity (one wafer). 6 Rev. 1.1 C8051F300-GDI 4. Wafer Storage Guidelines es ig ns It is necessary to conform to appropriate wafer storage practices to avoid product degradation or contamination.  Wafers may be stored for up to 18 months in the original packaging supplied by Silicon Labs. Wafers must be stored at a temperature of 18–24 °C.  Wafers must be stored in a humidity-controlled environment with a relative humidity of