C8051F317
25 MIPS, 16 kB Flash, 24-Pin Mixed-Signal MCU Analog Peripherals
Two Comparators
High-Speed 8051 µC Core
Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks Up to 25 MIPS throughput with 25 MHz system clock Expanded interrupt handler
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Programmable hysteresis and response time Configurable to generate interrupts or reset Low current (
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