C8051F342-GQR

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Full Speed USB Flash MCU Family Analog Peripherals - 10-Bit ADC (C8051F340/1/2/3/4/5/6/7/A/B only) • • - Instructions in 1 or 2 system clocks - 48 MIPS and 25 MIPS versions available. - Expanded interrupt handler Memory - 4352 or 2304 Bytes RAM - 64 or 32 kB Flash; In-system programmable in 512-byte Two comparators Internal voltage reference (C8051F340/1/2/3/4/5/6/7/A/B only) Brown-out detector and POR Circuitry sectors USB Function Controller - USB specification 2.0 compliant - Full speed (12 Mbps) or low speed (1.5 Mbps) operation - Integrated clock recovery; no external crystal required for full speed or low speed - Supports eight flexible endpoints - 1 kB USB buffer memory - Integrated transceiver; no external resistors required On-Chip Debug - On-chip debug circuitry facilitates full speed, non-intru- sive in-system debug (No emulator required) Provides breakpoints, single stepping, inspect/modify memory and registers Superior performance to emulation systems using ICE-chips, target pods, and sockets Voltage Regulator ANALOG PERIPHERALS 10-bit 200 ksps ADC TEMP SENSOR - + - + - VREG VREF enhanced UART serial ports Four general purpose 16-bit counter/timers 16-bit programmable counter array (PCA) with five capture/compare modules External Memory Interface (EMIF) Clock Sources - Internal Oscillator: ±0.25% accuracy with clock recovery - Voltage Supply Input: 2.7 to 5.25 V - Voltages from 3.6 to 5.25 V supported using On-Chip A M U X Digital Peripherals - 40/25 Port I/O; All 5 V tolerant with high sink current - Hardware enhanced SPI™, SMBus™, and one or two enabled. Supports all USB and UART modes External Oscillator: Crystal, RC, C, or clock (1 or 2 Pin modes) Low Frequency (80 kHz) Internal Oscillator Can switch between clock sources on-the-fly Packages - 48-pin TQFP (C8051F340/1/4/5/8/C) - 32-pin LQFP (C8051F342/3/6/7/9/A/B/D) - 5x5 mm 32-pin QFN (C8051F342/3/6/7/9/A/B) Temperature Range: –40 to +85 °C DIGITAL I/O UART0 UART1* SPI SMBus PCA Port 0 4 Timers 48 Pin Only C8051F340/1/2/34/5/6/7/A/B Only Ext. Memory I/F • Up to 200 ksps Built-in analog multiplexer with single-ended and differential mode VREF from external pin, internal reference, or VDD Built-in temperature sensor External conversion start input option CROSSBAR • • HIgh Speed 8051 µC Core - Pipelined instruction architecture; executes 70% of Port 1 Port 2 Port 3 Port 4 * C8051F340/1/4/5/8/A/B/C Only PRECISION INTERNAL OSCILLATORS USB Controller / Transceiver HIGH-SPEED CONTROLLER CORE 64/32 kB ISP FLASH FLEXIBLE INTERRUPTS Rev. 1.5 3/19 8051 CPU (48/25 MIPS) DEBUG CIRCUITRY 4/2 kB RAM POR Copyright © 2019 by Silicon Laboratories WDT C8051F34x C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 2 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table of Contents 1. 2. 3. 4. 5. System Overview.................................................................................................... 17 Absolute Maximum Ratings .................................................................................. 24 Global DC Electrical Characteristics .................................................................... 25 Pinout and Package Definitions............................................................................ 28 10-Bit ADC (ADC0, C8051F340/1/2/3/4/5/6/7/A/B Only)........................................ 41 5.1. Analog Multiplexer ............................................................................................ 42 5.2. Temperature Sensor ......................................................................................... 43 5.3. Modes of Operation .......................................................................................... 45 5.3.1. Starting a Conversion............................................................................... 45 5.3.2. Tracking Modes........................................................................................ 46 5.3.3. Settling Time Requirements ..................................................................... 47 5.4. Programmable Window Detector ...................................................................... 52 5.4.1. Window Detector In Single-Ended Mode ................................................. 54 5.4.2. Window Detector In Differential Mode...................................................... 55 6. Voltage Reference (C8051F340/1/2/3/4/5/6/7/A/B Only)....................................... 57 7. Comparators ........................................................................................................... 59 8. Voltage Regulator (REG0)...................................................................................... 69 8.1. Regulator Mode Selection................................................................................. 69 8.2. VBUS Detection ................................................................................................ 69 9. CIP-51 Microcontroller ........................................................................................... 73 9.1. Instruction Set ................................................................................................... 74 9.1.1. Instruction and CPU Timing ..................................................................... 74 9.1.2. MOVX Instruction and Program Memory ................................................. 75 9.2. Memory Organization........................................................................................ 79 9.2.1. Program Memory...................................................................................... 80 9.2.2. Data Memory............................................................................................ 81 9.2.3. General Purpose Registers ...................................................................... 81 9.2.4. Bit Addressable Locations........................................................................ 81 9.2.5. Stack ....................................................................................................... 81 9.2.6. Special Function Registers....................................................................... 82 9.2.7. Register Descriptions ............................................................................... 86 9.3. Interrupt Handler ............................................................................................... 88 9.3.1. MCU Interrupt Sources and Vectors ........................................................ 88 9.3.2. External Interrupts .................................................................................... 88 9.3.3. Interrupt Priorities ..................................................................................... 89 9.3.4. Interrupt Latency ...................................................................................... 89 9.3.5. Interrupt Register Descriptions................................................................. 90 9.4. Power Management Modes .............................................................................. 97 9.4.1. Idle Mode.................................................................................................. 97 9.4.2. Stop Mode ................................................................................................ 97 10. Prefetch Engine ...................................................................................................... 99 11. Reset Sources....................................................................................................... 100 11.1.Power-On Reset ............................................................................................. 101 Rev. 1.5 3 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 11.2.Power-Fail Reset / VDD Monitor .................................................................... 102 11.3.External Reset ................................................................................................ 103 11.4.Missing Clock Detector Reset ........................................................................ 103 11.5.Comparator0 Reset ........................................................................................ 103 11.6.PCA Watchdog Timer Reset .......................................................................... 103 11.7.Flash Error Reset ........................................................................................... 103 11.8.Software Reset ............................................................................................... 104 11.9.USB Reset...................................................................................................... 104 12. Flash Memory ....................................................................................................... 107 12.1.Programming The Flash Memory ................................................................... 107 12.1.1.Flash Lock and Key Functions ............................................................... 107 12.1.2.Flash Erase Procedure .......................................................................... 107 12.1.3.Flash Write Procedure ........................................................................... 108 12.2.Non-Volatile Data Storage.............................................................................. 109 12.3.Security Options ............................................................................................. 109 13. External Data Memory Interface and On-Chip XRAM........................................ 114 13.1.Accessing XRAM............................................................................................ 114 13.1.1.16-Bit MOVX Example ........................................................................... 114 13.1.2.8-Bit MOVX Example ............................................................................. 114 13.2.Accessing USB FIFO Space .......................................................................... 115 13.3.Configuring the External Memory Interface .................................................... 116 13.4.Port Configuration........................................................................................... 116 13.5.Multiplexed and Non-multiplexed Selection.................................................... 119 13.5.1.Multiplexed Configuration....................................................................... 119 13.5.2.Non-multiplexed Configuration............................................................... 120 13.6.Memory Mode Selection................................................................................. 120 13.6.1.Internal XRAM Only ............................................................................... 121 13.6.2.Split Mode without Bank Select.............................................................. 121 13.6.3.Split Mode with Bank Select................................................................... 122 13.6.4.External Only.......................................................................................... 122 13.7.Timing .......................................................................................................... 122 13.7.1.Non-multiplexed Mode ........................................................................... 124 13.7.2.Multiplexed Mode ................................................................................... 127 14. Oscillators ............................................................................................................. 131 14.1.Programmable Internal High-Frequency (H-F) Oscillator ............................... 132 14.1.1.Internal H-F Oscillator Suspend Mode ................................................... 132 14.2.Programmable Internal Low-Frequency (L-F) Oscillator ................................ 133 14.2.1.Calibrating the Internal L-F Oscillator..................................................... 133 14.3.External Oscillator Drive Circuit...................................................................... 135 14.3.1.Clocking Timers Directly Through the External Oscillator...................... 135 14.3.2.External Crystal Example....................................................................... 135 14.3.3.External RC Example............................................................................. 136 14.3.4.External Capacitor Example................................................................... 136 14.4.4x Clock Multiplier .......................................................................................... 138 14.5.System and USB Clock Selection .................................................................. 139 4 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 14.5.1.System Clock Selection ......................................................................... 139 14.5.2.USB Clock Selection .............................................................................. 139 15. Port Input/Output.................................................................................................. 142 15.1.Priority Crossbar Decoder .............................................................................. 144 15.2.Port I/O Initialization ....................................................................................... 147 15.3.General Purpose Port I/O ............................................................................... 150 16. Universal Serial Bus Controller (USB0).............................................................. 159 16.1.Endpoint Addressing ...................................................................................... 160 16.2.USB Transceiver ............................................................................................ 160 16.3.USB Register Access ..................................................................................... 162 16.4.USB Clock Configuration................................................................................ 166 16.5.FIFO Management ......................................................................................... 167 16.5.1.FIFO Split Mode ..................................................................................... 167 16.5.2.FIFO Double Buffering ........................................................................... 168 16.5.3.FIFO Access .......................................................................................... 168 16.6.Function Addressing....................................................................................... 169 16.7.Function Configuration and Control................................................................ 169 16.8.Interrupts ........................................................................................................ 172 16.9.The Serial Interface Engine ............................................................................ 176 16.10.Endpoint0 ..................................................................................................... 176 16.10.1.Endpoint0 SETUP Transactions .......................................................... 177 16.10.2.Endpoint0 IN Transactions................................................................... 177 16.10.3.Endpoint0 OUT Transactions............................................................... 178 16.11.Configuring Endpoints1-3 ............................................................................. 180 16.12.Controlling Endpoints1-3 IN.......................................................................... 180 16.12.1.Endpoints1-3 IN Interrupt or Bulk Mode............................................... 180 16.12.2.Endpoints1-3 IN Isochronous Mode..................................................... 181 16.13.Controlling Endpoints1-3 OUT...................................................................... 183 16.13.1.Endpoints1-3 OUT Interrupt or Bulk Mode........................................... 183 16.13.2.Endpoints1-3 OUT Isochronous Mode................................................. 184 17. SMBus ................................................................................................................... 188 17.1.Supporting Documents ................................................................................... 189 17.2.SMBus Configuration...................................................................................... 189 17.3.SMBus Operation ........................................................................................... 189 17.3.1.Arbitration............................................................................................... 190 17.3.2.Clock Low Extension.............................................................................. 191 17.3.3.SCL Low Timeout................................................................................... 191 17.3.4.SCL High (SMBus Free) Timeout .......................................................... 191 17.4.Using the SMBus............................................................................................ 191 17.4.1.SMBus Configuration Register............................................................... 192 17.4.2.SMB0CN Control Register ..................................................................... 195 17.4.3.Data Register ......................................................................................... 198 17.5.SMBus Transfer Modes.................................................................................. 198 17.5.1.Master Transmitter Mode ....................................................................... 198 17.5.2.Master Receiver Mode ........................................................................... 200 Rev. 1.5 5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 17.5.3.Slave Receiver Mode ............................................................................. 201 17.5.4.Slave Transmitter Mode ......................................................................... 202 17.6.SMBus Status Decoding................................................................................. 202 18. UART0.................................................................................................................... 205 18.1.Enhanced Baud Rate Generation................................................................... 206 18.2.Operational Modes ......................................................................................... 206 18.2.1.8-Bit UART ............................................................................................. 207 18.2.2.9-Bit UART ............................................................................................. 208 18.3.Multiprocessor Communications .................................................................... 208 19. UART1 (C8051F340/1/4/5/8/A/B/C Only).............................................................. 213 19.1.Baud Rate Generator ..................................................................................... 214 19.2.Data Format.................................................................................................... 215 19.3.Configuration and Operation .......................................................................... 216 19.3.1.Data Transmission ................................................................................. 216 19.3.2.Data Reception ...................................................................................... 216 19.3.3.Multiprocessor Communications ............................................................ 217 20. Enhanced Serial Peripheral Interface (SPI0)...................................................... 222 20.1.Signal Descriptions......................................................................................... 223 20.1.1.Master Out, Slave In (MOSI).................................................................. 223 20.1.2.Master In, Slave Out (MISO).................................................................. 223 20.1.3.Serial Clock (SCK) ................................................................................. 223 20.1.4.Slave Select (NSS) ................................................................................ 223 20.2.SPI0 Master Mode Operation ......................................................................... 224 20.3.SPI0 Slave Mode Operation ........................................................................... 226 20.4.SPI0 Interrupt Sources ................................................................................... 226 20.5.Serial Clock Timing......................................................................................... 227 20.6.SPI Special Function Registers ...................................................................... 229 21. Timers.................................................................................................................... 235 21.1.Timer 0 and Timer 1 ....................................................................................... 235 21.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 235 21.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 236 21.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 237 21.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 238 21.2.Timer 2 .......................................................................................................... 243 21.2.1.16-bit Timer with Auto-Reload................................................................ 243 21.2.2.8-bit Timers with Auto-Reload................................................................ 244 21.2.3.Timer 2 Capture Modes: USB Start-of-Frame or LFO Falling Edge ...... 245 21.3.Timer 3 .......................................................................................................... 249 21.3.1.16-bit Timer with Auto-Reload................................................................ 249 21.3.2.8-bit Timers with Auto-Reload................................................................ 250 21.3.3.USB Start-of-Frame Capture.................................................................. 251 22. Programmable Counter Array (PCA0) ................................................................ 255 22.1.PCA Counter/Timer ........................................................................................ 256 22.2.Capture/Compare Modules ............................................................................ 257 22.2.1.Edge-triggered Capture Mode................................................................ 258 6 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 22.2.2.Software Timer (Compare) Mode........................................................... 259 22.2.3.High Speed Output Mode....................................................................... 260 22.2.4.Frequency Output Mode ........................................................................ 261 22.2.5.8-Bit Pulse Width Modulator Mode......................................................... 262 22.2.6.16-Bit Pulse Width Modulator Mode....................................................... 263 22.3.Watchdog Timer Mode ................................................................................... 264 22.3.1.Watchdog Timer Operation .................................................................... 264 22.3.2.Watchdog Timer Usage ......................................................................... 265 22.4.Register Descriptions for PCA........................................................................ 266 23. C2 Interface ........................................................................................................... 271 23.1.C2 Interface Registers.................................................................................... 271 23.2.C2 Pin Sharing ............................................................................................... 273 Document Change List............................................................................................. 274 Contact Information.................................................................................................. 276 Rev. 1.5 7 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D List of Figures 1. System Overview Figure 1.1. C8051F340/1/4/5 Block Diagram ........................................................... 19 Figure 1.2. C8051F342/3/6/7 Block Diagram ........................................................... 20 Figure 1.3. C8051F348/C Block Diagram................................................................. 21 Figure 1.4. C8051F349/D Block Diagram................................................................. 22 Figure 1.5. C8051F34A/B Block Diagram ................................................................ 23 4. Pinout and Package Definitions Figure 4.1. TQFP-48 Pinout Diagram (Top View) .................................................... 31 Figure 4.2. TQFP-48 Package Diagram ................................................................... 32 Figure 4.3. TQFP-48 Recommended PCB Land Pattern ......................................... 33 Figure 4.4. LQFP-32 Pinout Diagram (Top View)..................................................... 34 Figure 4.5. LQFP-32 Package Diagram ................................................................... 35 Figure 4.6. LQFP-32 Recommended PCB Land Pattern ......................................... 36 Figure 4.7. QFN-32 Pinout Diagram (Top View) ...................................................... 37 5. 10-Bit ADC (ADC0, C8051F340/1/2/3/4/5/6/7/A/B Only) Figure 5.1. ADC0 Functional Block Diagram............................................................ 41 Figure 5.2. Temperature Sensor Transfer Function ................................................. 43 Figure 5.3. Temperature Sensor Error with 1-Point Calibration (VREF = 2.40 V) .... 44 Figure 5.4. 10-Bit ADC Track and Conversion Example Timing .............................. 46 Figure 5.5. ADC0 Equivalent Input Circuits .............................................................. 47 Figure 5.6. ADC Window Compare Example: Right-Justified Single-Ended Data ... 54 Figure 5.7. ADC Window Compare Example: Left-Justified Single-Ended Data...... 54 Figure 5.8. ADC Window Compare Example: Right-Justified Differential Data........ 55 Figure 5.9. ADC Window Compare Example: Left-Justified Differential Data .......... 55 6. Voltage Reference (C8051F340/1/2/3/4/5/6/7/A/B Only) Figure 6.1. Voltage Reference Functional Block Diagram........................................ 57 7. Comparators Figure 7.1. Comparator Functional Block Diagram .................................................. 60 Figure 7.2. Comparator Hysteresis Plot ................................................................... 61 8. Voltage Regulator (REG0) Figure 8.1. REG0 Configuration: USB Bus-Powered ............................................... 70 Figure 8.2. REG0 Configuration: USB Self-Powered ............................................... 70 Figure 8.3. REG0 Configuration: USB Self-Powered, Regulator Disabled............... 71 Figure 8.4. REG0 Configuration: No USB Connection ............................................. 71 9. CIP-51 Microcontroller Figure 9.1. CIP-51 Block Diagram............................................................................ 73 Figure 9.2. On-Chip Memory Map for 64 kB Devices............................................... 79 Figure 9.3. On-Chip Memory Map for 32 kB Devices............................................... 80 11. Reset Sources Figure 11.1. Reset Sources.................................................................................... 100 Figure 11.2. Power-On and VDD Monitor Reset Timing ........................................ 101 Rev. 1.5 8 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 12. Flash Memory Figure 12.1. Flash Program Memory Map and Security Byte................................. 110 13. External Data Memory Interface and On-Chip XRAM Figure 13.1. USB FIFO Space and XRAM Memory Map with USBFAE set to ‘1’ ...................................................................................... 115 Figure 13.2. Multiplexed Configuration Example.................................................... 119 Figure 13.3. Non-multiplexed Configuration Example ............................................ 120 Figure 13.4. EMIF Operating Modes ...................................................................... 120 Figure 13.5. Non-multiplexed 16-bit MOVX Timing ................................................ 124 Figure 13.6. Non-multiplexed 8-bit MOVX without Bank Select Timing ................. 125 Figure 13.7. Non-multiplexed 8-bit MOVX with Bank Select Timing ...................... 126 Figure 13.8. Multiplexed 16-bit MOVX Timing........................................................ 127 Figure 13.9. Multiplexed 8-bit MOVX without Bank Select Timing ......................... 128 Figure 13.10. Multiplexed 8-bit MOVX with Bank Select Timing ............................ 129 14. Oscillators Figure 14.1. Oscillator Diagram.............................................................................. 131 15. Port Input/Output Figure 15.1. Port I/O Functional Block Diagram (Port 0 through Port 3) ................ 142 Figure 15.2. Port I/O Cell Block Diagram ............................................................... 143 Figure 15.3. Peripheral Availability on Port I/O Pins............................................... 144 Figure 15.4. Crossbar Priority Decoder in Example Configuration (No Pins Skipped) ............................................................................................. 145 Figure 15.5. Crossbar Priority Decoder in Example Configuration (3 Pins Skipped) .......................................................... 146 16. Universal Serial Bus Controller (USB0) Figure 16.1. USB0 Block Diagram.......................................................................... 159 Figure 16.2. USB0 Register Access Scheme......................................................... 162 Figure 16.3. USB FIFO Allocation .......................................................................... 167 17. SMBus Figure 17.1. SMBus Block Diagram ....................................................................... 188 Figure 17.2. Typical SMBus Configuration ............................................................. 189 Figure 17.3. SMBus Transaction ............................................................................ 190 Figure 17.4. Typical SMBus SCL Generation......................................................... 193 Figure 17.5. Typical Master Transmitter Sequence................................................ 199 Figure 17.6. Typical Master Receiver Sequence.................................................... 200 Figure 17.7. Typical Slave Receiver Sequence...................................................... 201 Figure 17.8. Typical Slave Transmitter Sequence.................................................. 202 18. UART0 Figure 18.1. UART0 Block Diagram ....................................................................... 205 Figure 18.2. UART0 Baud Rate Logic .................................................................... 206 Figure 18.3. UART Interconnect Diagram .............................................................. 207 Figure 18.4. 8-Bit UART Timing Diagram............................................................... 207 Figure 18.5. 9-Bit UART Timing Diagram............................................................... 208 Figure 18.6. UART Multi-Processor Mode Interconnect Diagram .......................... 209 19. UART1 (C8051F340/1/4/5/8/A/B/C Only) 9 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Figure 19.1. UART1 Block Diagram ....................................................................... 213 Figure 19.2. UART1 Timing Without Parity or Extra Bit.......................................... 215 Figure 19.3. UART1 Timing With Parity ................................................................. 215 Figure 19.4. UART1 Timing With Extra Bit ............................................................. 215 Figure 19.5. Typical UART Interconnect Diagram.................................................. 216 Figure 19.6. UART Multi-Processor Mode Interconnect Diagram .......................... 218 20. Enhanced Serial Peripheral Interface (SPI0) Figure 20.1. SPI Block Diagram ............................................................................. 222 Figure 20.2. Multiple-Master Mode Connection Diagram ....................................... 225 Figure 20.3. 3-Wire Single Master and Slave Mode Connection Diagram ............. 225 Figure 20.4. 4-Wire Single Master Mode and Slave Mode Connection Diagram ... 225 Figure 20.5. Master Mode Data/Clock Timing ........................................................ 227 Figure 20.6. Slave Mode Data/Clock Timing (CKPHA = 0) .................................... 228 Figure 20.7. Slave Mode Data/Clock Timing (CKPHA = 1) .................................... 228 Figure 20.8. SPI Master Timing (CKPHA = 0)........................................................ 232 Figure 20.9. SPI Master Timing (CKPHA = 1)........................................................ 232 Figure 20.10. SPI Slave Timing (CKPHA = 0)........................................................ 233 Figure 20.11. SPI Slave Timing (CKPHA = 1)........................................................ 233 21. Timers Figure 21.1. T0 Mode 0 Block Diagram.................................................................. 236 Figure 21.2. T0 Mode 2 Block Diagram.................................................................. 237 Figure 21.3. T0 Mode 3 Block Diagram.................................................................. 238 Figure 21.4. Timer 2 16-Bit Mode Block Diagram .................................................. 243 Figure 21.5. Timer 2 8-Bit Mode Block Diagram .................................................... 244 Figure 21.6. Timer 2 Capture Mode (T2SPLIT = ‘0’) .............................................. 245 Figure 21.7. Timer 2 Capture Mode (T2SPLIT = ‘1’) .............................................. 246 Figure 21.8. Timer 3 16-Bit Mode Block Diagram .................................................. 249 Figure 21.9. Timer 3 8-Bit Mode Block Diagram .................................................... 250 Figure 21.10. Timer 3 Capture Mode (T3SPLIT = ‘0’) ............................................ 251 Figure 21.11. Timer 3 Capture Mode (T3SPLIT = ‘1’) ............................................ 252 22. Programmable Counter Array (PCA0) Figure 22.1. PCA Block Diagram............................................................................ 255 Figure 22.2. PCA Counter/Timer Block Diagram.................................................... 256 Figure 22.3. PCA Interrupt Block Diagram ............................................................. 257 Figure 22.4. PCA Capture Mode Diagram.............................................................. 258 Figure 22.5. PCA Software Timer Mode Diagram .................................................. 259 Figure 22.6. PCA High Speed Output Mode Diagram............................................ 260 Figure 22.7. PCA Frequency Output Mode ............................................................ 261 Figure 22.8. PCA 8-Bit PWM Mode Diagram ......................................................... 262 Figure 22.9. PCA 16-Bit PWM Mode...................................................................... 263 Figure 22.10. PCA Module 4 with Watchdog Timer Enabled ................................. 264 23. C2 Interface Figure 23.1. Typical C2 Pin Sharing....................................................................... 273 Rev. 1.5 10 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D List of Tables 1. System Overview Table 1.1. Product Selection Guide ......................................................................... 18 2. Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings* .................................................................. 24 3. Global DC Electrical Characteristics Table 3.1. Global DC Electrical Characteristics ....................................................... 25 Table 3.2. Index to Electrical Characteristics Tables ............................................... 27 4. Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D ................. 28 Table 4.2. TQFP-48 Package Dimensions .............................................................. 32 Table 4.3. TQFP-48 PCB Land Pattern Dimensions ............................................... 33 Table 4.4. LQFP-32 Package Dimensions .............................................................. 35 Table 4.5. LQFP-32 PCB Land Pattern Dimensions ............................................... 36 5. 10-Bit ADC (ADC0, C8051F340/1/2/3/4/5/6/7/A/B Only) Table 5.1. ADC0 Electrical Characteristics .............................................................. 56 6. Voltage Reference (C8051F340/1/2/3/4/5/6/7/A/B Only) Table 6.1. Voltage Reference Electrical Characteristics ......................................... 58 7. Comparators Table 7.1. Comparator Electrical Characteristics .................................................... 68 8. Voltage Regulator (REG0) Table 8.1. Voltage Regulator Electrical Specifications ............................................ 69 9. CIP-51 Microcontroller Table 9.1. CIP-51 Instruction Set Summary ............................................................ 75 Table 9.2. Special Function Register (SFR) Memory Map ...................................... 82 Table 9.3. Special Function Registers ..................................................................... 83 Table 9.4. Interrupt Summary .................................................................................. 90 11. Reset Sources Table 11.1. Reset Electrical Characteristics .......................................................... 106 12. Flash Memory Table 12.1. Flash Electrical Characteristics .......................................................... 109 13. External Data Memory Interface and On-Chip XRAM Table 13.1. AC Parameters for External Memory Interface ................................... 130 14. Oscillators Table 14.1. Oscillator Electrical Characteristics .................................................... 141 15. Port Input/Output Table 15.1. Port I/O DC Electrical Characteristics ................................................. 158 16. Universal Serial Bus Controller (USB0) Table 16.1. Endpoint Addressing Scheme ............................................................ 160 Table 16.2. USB0 Controller Registers ................................................................. 165 Table 16.3. FIFO Configurations ........................................................................... 168 Table 16.4. USB Transceiver Electrical Characteristics ........................................ 187 17. SMBus Table 17.1. SMBus Clock Source Selection .......................................................... 192 Rev. 1.5 11 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 17.2. Minimum SDA Setup and Hold Times ................................................ 193 Table 17.3. Sources for Hardware Changes to SMB0CN ..................................... 197 Table 17.4. SMBus Status Decoding ..................................................................... 203 18. UART0 Table 18.1. Timer Settings for Standard Baud Rates Using the Internal Oscillator ............................................................... 212 19. UART1 (C8051F340/1/4/5/8/A/B/C Only) Table 19.1. Baud Rate Generator Settings for Standard Baud Rates ................... 214 20. Enhanced Serial Peripheral Interface (SPI0) Table 20.1. SPI Slave Timing Parameters ............................................................ 234 22. Programmable Counter Array (PCA0) Table 22.1. PCA Timebase Input Options ............................................................. 256 Table 22.2. PCA0CPM Register Settings for PCA Capture/Compare Modules .... 257 Table 22.3. Watchdog Timer Timeout Intervals1 ................................................... 265 12 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D List of Registers SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select . . . . . . . . . . . . . . . . . . . 48 SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select . . . . . . . . . . . . . . . . . . 49 SFR Definition 5.3. ADC0CF: ADC0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 SFR Definition 5.4. ADC0H: ADC0 Data Word MSB . . . . . . . . . . . . . . . . . . . . . . . . . . 50 SFR Definition 5.5. ADC0L: ADC0 Data Word LSB . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 SFR Definition 5.6. ADC0CN: ADC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 SFR Definition 5.7. ADC0GTH: ADC0 Greater-Than Data High Byte . . . . . . . . . . . . . 52 SFR Definition 5.8. ADC0GTL: ADC0 Greater-Than Data Low Byte . . . . . . . . . . . . . . 52 SFR Definition 5.9. ADC0LTH: ADC0 Less-Than Data High Byte . . . . . . . . . . . . . . . . 53 SFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte . . . . . . . . . . . . . . . 53 SFR Definition 6.1. REF0CN: Reference Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 SFR Definition 7.1. CPT0CN: Comparator0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 SFR Definition 7.2. CPT0MX: Comparator0 MUX Selection . . . . . . . . . . . . . . . . . . . . 63 SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection . . . . . . . . . . . . . . . . . . . . 64 SFR Definition 7.4. CPT1CN: Comparator1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 SFR Definition 7.5. CPT1MX: Comparator1 MUX Selection . . . . . . . . . . . . . . . . . . . . 66 SFR Definition 7.6. CPT1MD: Comparator1 Mode Selection . . . . . . . . . . . . . . . . . . . . 67 SFR Definition 8.1. REG0CN: Voltage Regulator Control . . . . . . . . . . . . . . . . . . . . . . 72 SFR Definition 9.1. DPL: Data Pointer Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 SFR Definition 9.2. DPH: Data Pointer High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 SFR Definition 9.3. SP: Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 SFR Definition 9.4. PSW: Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 SFR Definition 9.5. ACC: Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 SFR Definition 9.6. B: B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 SFR Definition 9.7. IE: Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 SFR Definition 9.8. IP: Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 SFR Definition 9.9. EIE1: Extended Interrupt Enable 1 . . . . . . . . . . . . . . . . . . . . . . . . 93 SFR Definition 9.10. EIP1: Extended Interrupt Priority 1 . . . . . . . . . . . . . . . . . . . . . . . 94 SFR Definition 9.11. EIE2: Extended Interrupt Enable 2 . . . . . . . . . . . . . . . . . . . . . . . 95 SFR Definition 9.12. EIP2: Extended Interrupt Priority 2 . . . . . . . . . . . . . . . . . . . . . . . 95 SFR Definition 9.13. IT01CF: INT0/INT1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . 96 SFR Definition 9.14. PCON: Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 SFR Definition 10.1. PFE0CN: Prefetch Engine Control . . . . . . . . . . . . . . . . . . . . . . . 99 SFR Definition 11.1. VDM0CN: VDD Monitor Control . . . . . . . . . . . . . . . . . . . . . . . . . 102 SFR Definition 11.2. RSTSRC: Reset Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 SFR Definition 12.1. PSCTL: Program Store R/W Control . . . . . . . . . . . . . . . . . . . . . 112 SFR Definition 12.2. FLKEY: Flash Lock and Key . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 SFR Definition 12.3. FLSCL: Flash Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 SFR Definition 13.1. EMI0CN: External Memory Interface Control . . . . . . . . . . . . . . 117 SFR Definition 13.2. EMI0CF: External Memory Configuration . . . . . . . . . . . . . . . . . 118 SFR Definition 13.3. EMI0TC: External Memory Timing Control . . . . . . . . . . . . . . . . 123 SFR Definition 14.1. OSCICN: Internal H-F Oscillator Control . . . . . . . . . . . . . . . . . . 132 SFR Definition 14.2. OSCICL: Internal H-F Oscillator Calibration . . . . . . . . . . . . . . . 133 Rev. 1.5 13 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 14.3. OSCLCN: Internal L-F Oscillator Control . . . . . . . . . . . . . . . . . . 134 SFR Definition 14.4. OSCXCN: External Oscillator Control . . . . . . . . . . . . . . . . . . . . 137 SFR Definition 14.5. CLKMUL: Clock Multiplier Control . . . . . . . . . . . . . . . . . . . . . . . 138 SFR Definition 14.6. CLKSEL: Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 SFR Definition 15.1. XBR0: Port I/O Crossbar Register 0 . . . . . . . . . . . . . . . . . . . . . 148 SFR Definition 15.2. XBR1: Port I/O Crossbar Register 1 . . . . . . . . . . . . . . . . . . . . . 149 SFR Definition 15.3. XBR2: Port I/O Crossbar Register 2 . . . . . . . . . . . . . . . . . . . . . 149 SFR Definition 15.4. P0: Port0 Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 SFR Definition 15.5. P0MDIN: Port0 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 SFR Definition 15.6. P0MDOUT: Port0 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 151 SFR Definition 15.7. P0SKIP: Port0 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 SFR Definition 15.8. P1: Port1 Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 SFR Definition 15.9. P1MDIN: Port1 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 SFR Definition 15.10. P1MDOUT: Port1 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 152 SFR Definition 15.11. P1SKIP: Port1 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 SFR Definition 15.12. P2: Port2 Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 SFR Definition 15.13. P2MDIN: Port2 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 SFR Definition 15.14. P2MDOUT: Port2 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 154 SFR Definition 15.15. P2SKIP: Port2 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 SFR Definition 15.16. P3: Port3 Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 SFR Definition 15.17. P3MDIN: Port3 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 SFR Definition 15.18. P3MDOUT: Port3 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 155 SFR Definition 15.19. P3SKIP: Port3 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 SFR Definition 15.20. P4: Port4 Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 SFR Definition 15.21. P4MDIN: Port4 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 SFR Definition 15.22. P4MDOUT: Port4 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 157 SFR Definition 16.1. USB0XCN: USB0 Transceiver Control . . . . . . . . . . . . . . . . . . . 161 SFR Definition 16.2. USB0ADR: USB0 Indirect Address . . . . . . . . . . . . . . . . . . . . . . 163 SFR Definition 16.3. USB0DAT: USB0 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 USB Register Definition 16.4. INDEX: USB0 Endpoint Index . . . . . . . . . . . . . . . . . . . 165 USB Register Definition 16.5. CLKREC: Clock Recovery Control . . . . . . . . . . . . . . . 166 USB Register Definition 16.6. FIFOn: USB0 Endpoint FIFO Access . . . . . . . . . . . . . 168 USB Register Definition 16.7. FADDR: USB0 Function Address . . . . . . . . . . . . . . . . 169 USB Register Definition 16.8. POWER: USB0 Power . . . . . . . . . . . . . . . . . . . . . . . . 171 USB Register Definition 16.9. FRAMEL: USB0 Frame Number Low . . . . . . . . . . . . . 172 USB Register Definition 16.10. FRAMEH: USB0 Frame Number High . . . . . . . . . . . 172 USB Register Definition 16.11. IN1INT: USB0 IN Endpoint Interrupt . . . . . . . . . . . . . 173 USB Register Definition 16.12. OUT1INT: USB0 Out Endpoint Interrupt . . . . . . . . . . 173 USB Register Definition 16.13. CMINT: USB0 Common Interrupt . . . . . . . . . . . . . . . 174 USB Register Definition 16.14. IN1IE: USB0 IN Endpoint Interrupt Enable . . . . . . . . 175 USB Register Definition 16.15. OUT1IE: USB0 Out Endpoint Interrupt Enable . . . . . 175 USB Register Definition 16.16. CMIE: USB0 Common Interrupt Enable . . . . . . . . . . 176 USB Register Definition 16.17. E0CSR: USB0 Endpoint0 Control . . . . . . . . . . . . . . . 179 USB Register Definition 16.18. E0CNT: USB0 Endpoint 0 Data Count . . . . . . . . . . . 180 14 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D USB Register Definition 16.19. EINCSRL: USB0 IN Endpoint Control Low Byte . . . . 182 USB Register Definition 16.20. EINCSRH: USB0 IN Endpoint Control High Byte . . . 183 USB Register Definition 16.21. EOUTCSRL: USB0 OUT Endpoint Control Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 USB Register Definition 16.22. EOUTCSRH: USB0 OUT Endpoint Control High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 USB Register Definition 16.23. EOUTCNTL: USB0 OUT Endpoint Count Low . . . . . 186 USB Register Definition 16.24. EOUTCNTH: USB0 OUT Endpoint Count High . . . . 186 SFR Definition 17.1. SMB0CF: SMBus Clock/Configuration . . . . . . . . . . . . . . . . . . . 194 SFR Definition 17.2. SMB0CN: SMBus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 SFR Definition 17.3. SMB0DAT: SMBus Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 SFR Definition 18.1. SCON0: Serial Port 0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 210 SFR Definition 18.2. SBUF0: Serial (UART0) Port Data Buffer . . . . . . . . . . . . . . . . . 211 SFR Definition 19.1. SCON1: UART1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 SFR Definition 19.2. SMOD1: UART1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 SFR Definition 19.3. SBUF1: UART1 Data Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 SFR Definition 19.4. SBCON1: UART1 Baud Rate Generator Control . . . . . . . . . . . 220 SFR Definition 19.5. SBRLH1: UART1 Baud Rate Generator High Byte . . . . . . . . . . 221 SFR Definition 19.6. SBRLL1: UART1 Baud Rate Generator Low Byte . . . . . . . . . . . 221 SFR Definition 20.1. SPI0CFG: SPI0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 229 SFR Definition 20.2. SPI0CN: SPI0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 SFR Definition 20.3. SPI0CKR: SPI0 Clock Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 SFR Definition 20.4. SPI0DAT: SPI0 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 SFR Definition 21.1. TCON: Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 SFR Definition 21.2. TMOD: Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 SFR Definition 21.3. CKCON: Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 SFR Definition 21.4. TL0: Timer 0 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 SFR Definition 21.5. TL1: Timer 1 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 SFR Definition 21.6. TH0: Timer 0 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 SFR Definition 21.7. TH1: Timer 1 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 SFR Definition 21.8. TMR2CN: Timer 2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 SFR Definition 21.9. TMR2RLL: Timer 2 Reload Register Low Byte . . . . . . . . . . . . . 248 SFR Definition 21.10. TMR2RLH: Timer 2 Reload Register High Byte . . . . . . . . . . . 248 SFR Definition 21.11. TMR2L: Timer 2 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 SFR Definition 21.12. TMR2H Timer 2 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 SFR Definition 21.13. TMR3CN: Timer 3 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 SFR Definition 21.14. TMR3RLL: Timer 3 Reload Register Low Byte . . . . . . . . . . . . 254 SFR Definition 21.15. TMR3RLH: Timer 3 Reload Register High Byte . . . . . . . . . . . 254 SFR Definition 21.16. TMR3L: Timer 3 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 SFR Definition 21.17. TMR3H Timer 3 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 SFR Definition 22.1. PCA0CN: PCA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 SFR Definition 22.2. PCA0MD: PCA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 SFR Definition 22.3. PCA0CPMn: PCA Capture/Compare Mode . . . . . . . . . . . . . . . 268 SFR Definition 22.4. PCA0L: PCA Counter/Timer Low Byte . . . . . . . . . . . . . . . . . . . 269 SFR Definition 22.5. PCA0H: PCA Counter/Timer High Byte . . . . . . . . . . . . . . . . . . . 269 Rev. 1.5 15 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 22.6. PCA0CPLn: PCA Capture Module Low Byte . . . . . . . . . . . . . . . 269 SFR Definition 22.7. PCA0CPHn: PCA Capture Module High Byte . . . . . . . . . . . . . . 270 C2 Register Definition 23.1. C2ADD: C2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 C2 Register Definition 23.2. DEVICEID: C2 Device ID . . . . . . . . . . . . . . . . . . . . . . . . 271 C2 Register Definition 23.3. REVID: C2 Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . 272 C2 Register Definition 23.4. FPCTL: C2 Flash Programming Control . . . . . . . . . . . . 272 C2 Register Definition 23.5. FPDAT: C2 Flash Programming Data . . . . . . . . . . . . . . 272 16 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 1. System Overview C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are listed below. Refer to Table 1.1 for specific product feature selection. • • • • • • • • • • • • • • • • • High-speed pipelined 8051-compatible microcontroller core (up to 48 MIPS) In-system, full-speed, non-intrusive debug interface (on-chip) Universal Serial Bus (USB) Function Controller with eight flexible endpoint pipes, integrated transceiver, and 1 kB FIFO RAM Supply Voltage Regulator True 10-bit 200 ksps differential / single-ended ADC with analog multiplexer On-chip Voltage Reference and Temperature Sensor On-chip Voltage Comparators (2) Precision internal calibrated 12 MHz internal oscillator and 4x clock multiplier Internal low-frequency oscillator for additional power savings Up to 64 kB of on-chip Flash memory Up to 4352 Bytes of on-chip RAM (256 + 4 kB) External Memory Interface (EMIF) available on 48-pin versions. SMBus/I2C, up to 2 UARTs, and Enhanced SPI serial interfaces implemented in hardware Four general-purpose 16-bit timers Programmable Counter/Timer Array (PCA) with five capture/compare modules and Watchdog Timer function On-chip Power-On Reset, VDD Monitor, and Missing Clock Detector Up to 40 Port I/O (5 V tolerant) With on-chip Power-On Reset, VDD monitor, Voltage Regulator, Watchdog Timer, and clock oscillator, C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D devices are truly stand-alone System-on-a-Chip solutions. The Flash memory can be reprogrammed in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. User software has complete control of all peripherals, and may individually shut down any or all peripherals for power savings. The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging without occupying package pins. Each device is specified for 2.7–5.25 V operation over the industrial temperature range (–40 to +85 °C). For voltages above 3.6 V, the on-chip Voltage Regulator must be used. A minimum of 3.0 V is required for USB communication. The Port I/O and RST pins are tolerant of input signals up to 5 V. C8051F340/1/2/3/ 4/5/6/7/8/9/A/B/C/D devices are available in 48-pin TQFP, 32-pin LQFP, or 32-pin QFN packages. See Table 1.1, “Product Selection Guide,” on page 18 for feature and package choices. Rev. 1.5 17 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Flash Memory (Bytes) RAM Calibrated Internal Oscillator Low Frequency Oscillator USB with 1k Endpoint RAM Supply Voltage Regulator SMBus/I2C Enhanced SPI UARTs Timers (16-bit) Programmable Counter Array Digital Port I/Os External Memory Interface (EMIF) 10-bit 200 ksps ADC Temperature Sensor Voltage Reference Analog Comparators Package C8051F340-GQ 48 64k 4352       2 4  40     2 TQFP48 C8051F341-GQ 48 32k 2304       2 4  40     2 TQFP48 C8051F342-GQ 48 64k 4352       1 4  25 —    2 LQFP32 C8051F342-GM 48 64k 4352       1 4  25 —    2 QFN32 C8051F343-GQ 48 32k 2304       1 4  25 —    2 LQFP32 C8051F343-GM 48 32k 2304       1 4  25 —    2 QFN32 C8051F344-GQ 25 64k 4352       2 4  40     2 TQFP48 C8051F345-GQ 25 32k 2304       2 4  40     2 TQFP48 C8051F346-GQ 25 64k 4352  —     1 4  25 —    2 LQFP32 C8051F346-GM 25 64k 4352  —     1 4  25 —    2 QFN32 C8051F347-GQ 25 32k 2304  —     1 4  25 —    2 LQFP32 C8051F347-GM 25 32k 2304  —     1 4  25 —    2 QFN32 C8051F348-GQ 25 32k 2304       2 4  40  — — — 2 TQFP48 C8051F349-GQ 25 32k 2304       1 4  25 — — — — 2 LQFP32 C8051F349-GM 25 32k 2304       1 4  25 — — — — 2 QFN32 C8051F34A-GQ 48 64k 4352       2 4  25 —    2 LQFP32 C8051F34A-GM 48 64k 4352       2 4  25 —    2 QFN32 C8051F34B-GQ 48 32k 2304       2 4  25 —    2 LQFP32 C8051F34B-GM 48 32k 2304       2 4  25 —    2 QFN32 C8051F34C-GQ 48 64k 4352       2 4  40  — — — 2 TQFP48 C8051F34D-GQ 48 64k 4352       1 4  25 — — — — 2 LQFP32 Ordering Part Number MIPS (Peak) Table 1.1. Product Selection Guide 18 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D C2D Port I/O Configuration Debug / Programming Hardware C2CK/RST UART0 Reset Power-On Reset Supply Monitor VDD Power Net VREG Voltage Regulator Port 0 Drivers P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6/XTAL1 P0.7/XTAL2 Port 1 Drivers P1.0 P1.1 P1.2 P1.3 P1.4/CNVSTR P1.5/VREF P1.6 P1.7 Port 2 Drivers P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 Port 3 Drivers P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Port 4 Drivers P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 Digital Peripherals CIP-51 8051 Controller Core UART1 Timers 0, 1, 2, 3 64/32k Byte ISP FLASH Program Memory Priority Crossbar Decoder PCA/WDT 256 Byte RAM SMBus SPI 4/2k Byte XRAM Crossbar Control GND System Clock Setup XTAL1 XTAL2 External Oscillator Internal Oscillator SFR Bus External Memory Interface P1 Control Clock Multiplier P2 / P3 Address P4 Data Clock Recovery Low Freq. Oscillator Analog Peripherals CP0 VREF USB Peripheral D+ D- VBUS Full / Low Speed Transceiver VDD VREF + + - 2 Comparators Controller 1k Byte RAM CP1 10-bit 200ksps ADC A M U X VDD AIN0 - AIN19 Temp Sensor Figure 1.1. C8051F340/1/4/5 Block Diagram Rev. 1.5 19 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D C2D Port I/O Configuration Debug / Programming Hardware C2CK/RST UART0 Reset Power-On Reset Supply Monitor VDD Power Net VREG Voltage Regulator Port 0 Drivers P0.0 P0.1 P0.2/XTAL1 P0.3/XTAL2 P0.4 P0.5 P0.6/CNVSTR P0.7/VREF Port 1 Drivers P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 Port 2 Drivers P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 Digital Peripherals CIP-51 8051 Controller Core Timers 0, 1, 2, 3 64/32 kB ISP FLASH Program Memory Priority Crossbar Decoder PCA/WDT 256 Byte RAM SMBus SPI 4/2 kB XRAM Crossbar Control GND System Clock Setup XTAL1 XTAL2 External Oscillator Internal Oscillator Clock Recovery SFR Bus P3.0/C2D Port 3 Drivers Clock Multiplier Low Freq. Oscillator* Analog Peripherals CP0 VREF USB Peripheral D+ D- VBUS Full / Low Speed Transceiver VDD VREF CP1 + + - 2 Comparators Controller 10-bit 200 ksps ADC 1 kB RAM A M U X VDD AIN0 - AIN20 Temp Sensor *Low Frequency Oscillator option not available on C8051F346/7 Figure 1.2. C8051F342/3/6/7 Block Diagram 20 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D C2D Port I/O Configuration Debug / Programming Hardware C2CK/RST UART0 Reset Power-On Reset Supply Monitor VDD Power Net VREG Voltage Regulator Port 0 Drivers P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6/XTAL1 P0.7/XTAL2 Port 1 Drivers P1.0 P1.1 P1.2 P1.3 P1.4/CNVSTR P1.5/VREF P1.6 P1.7 Port 2 Drivers P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 Port 3 Drivers P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Port 4 Drivers P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 Digital Peripherals CIP-51 8051 Controller Core UART1 Timers 0, 1, 2, 3 64/32 kB ISP FLASH Program Memory Priority Crossbar Decoder PCA/WDT 256 Byte RAM SMBus SPI 4/2 kB XRAM Crossbar Control GND System Clock Setup XTAL1 XTAL2 External Oscillator Internal Oscillator SFR Bus External Memory Interface P1 Clock Multiplier Control Address P4 Data Clock Recovery P2 / P3 Low Freq. Oscillator Analog Peripherals USB Peripheral D+ D- VBUS Full / Low Speed Transceiver Controller 1k Byte RAM CP0 CP1 + + - 2 Comparators Figure 1.3. C8051F348/C Block Diagram Rev. 1.5 21 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D C2D Port I/O Configuration Debug / Programming Hardware C2CK/RST UART0 Reset Power-On Reset Supply Monitor VDD Power Net VREG Voltage Regulator Port 0 Drivers P0.0 P0.1 P0.2/XTAL1 P0.3/XTAL2 P0.4 P0.5 P0.6/CNVSTR P0.7/VREF Port 1 Drivers P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 Port 2 Drivers P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 Digital Peripherals CIP-51 8051 Controller Core Timers 0, 1, 2, 3 64/32 kB ISP FLASH Program Memory Priority Crossbar Decoder PCA/WDT 256 Byte RAM SMBus SPI 4/2 kB XRAM Crossbar Control GND System Clock Setup XTAL1 XTAL2 External Oscillator Internal Oscillator Clock Recovery SFR Bus P3.0/C2D Port 3 Drivers Clock Multiplier Low Freq. Oscillator Analog Peripherals USB Peripheral D+ D- VBUS Full / Low Speed Transceiver CP0 Controller CP1 + + - 2 Comparators 1 kB RAM Figure 1.4. C8051F349/D Block Diagram 22 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D C2D Port I/O Configuration Debug / Programming Hardware C2CK/RST UART0 Reset Power-On Reset Supply Monitor VDD Power Net VREG Voltage Regulator Port 0 Drivers P0.0 P0.1 P0.2/XTAL1 P0.3/XTAL2 P0.4 P0.5 P0.6/CNVSTR P0.7/VREF Port 1 Drivers P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 Port 2 Drivers P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 Digital Peripherals CIP-51 8051 Controller Core UART1 Timers 0, 1, 2, 3 64/32 kB ISP FLASH Program Memory Priority Crossbar Decoder PCA/WDT 256 Byte RAM SMBus SPI 4/2 kB XRAM Crossbar Control GND System Clock Setup XTAL1 XTAL2 External Oscillator Internal Oscillator Clock Recovery SFR Bus P3.0/C2D Port 3 Drivers Clock Multiplier Low Freq. Oscillator* Analog Peripherals CP0 VREF USB Peripheral D+ D- VBUS Full / Low Speed Transceiver VDD VREF + + - 2 Comparators Controller 1 kB RAM CP1 10-bit 200 ksps ADC A M U X VDD AIN0 - AIN20 Temp Sensor Figure 1.5. C8051F34A/B Block Diagram Rev. 1.5 23 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 2. Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings* Parameter Conditions Min Typ Max Units Ambient temperature under bias –55 125 °C Storage Temperature –65 150 °C Voltage on any Port I/O Pin or RST with respect to GND –0.3 5.8 V Voltage on VDD with respect to GND –0.3 4.2 V Maximum Total current through VDD and GND 500 mA Maximum output current sunk by RST or any Port pin 100 mA *Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 24 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 3. Global DC Electrical Characteristics Table 3.1. Global DC Electrical Characteristics –40 to +85 °C, 25 MHz System Clock unless otherwise specified. Parameter Conditions Digital Supply Voltage1 Min Typ Max Units VRST 3.3 3.6 V Digital Supply RAM Data Retention Voltage SYSCLK (System Clock)2 1.5 C8051F340/1/2/3/A/B/C/D C8051F344/5/6/7/8/9 Specified Operating Temperature Range V 0 0 48 25 MHz –40 +85 °C Digital Supply Current - CPU Active (Normal Mode, accessing Flash) IDD3 IDD Supply Sensitivity3,4 IDD Frequency Sensitivity3,5 VDD = 3.3 V, SYSCLK = 48 MHz VDD = 3.3 V, SYSCLK = 24 MHz VDD = 3.3 V, SYSCLK = 1 MHz VDD = 3.3 V, SYSCLK = 80 kHz 25.9 13.9 0.69 55 28.5 15.7 mA mA mA µA VDD = 3.6 V, SYSCLK = 48 MHz VDD = 3.6 V, SYSCLK = 24 MHz 29.7 15.9 32.3 18 mA mA 47 %/V 46 %/V VDD = 3.3 V, SYSCLK < 30 MHz, T = 25 ºC VDD = 3.3 V, SYSCLK > 30 MHz, T = 25 ºC 0.69 mA/MHz 0.44 mA/MHz VDD = 3.6 V, SYSCLK < 30 MHz, T = 25 ºC VDD = 3.6 V, SYSCLK > 30 MHz, T = 25 ºC 0.80 mA/MHz 0.50 mA/MHz SYSCLK = 1 MHz, relative to VDD = 3.3 V SYSCLK = 24 MHz, relative to VDD = 3.3 V Digital Supply Current - CPU Inactive (Idle Mode, not accessing Flash) IDD3 IDD Supply Sensitivity3,4 VDD = 3.3 V, SYSCLK = 48 MHz VDD = 3.3 V, SYSCLK = 24 MHz VDD = 3.3 V, SYSCLK = 1 MHz VDD = 3.3 V, SYSCLK = 80 kHz 16.6 8.25 0.44 35 18.75 9.34 mA mA mA µA VDD = 3.6 V, SYSCLK = 48 MHz VDD = 3.6 V, SYSCLK = 24 MHz 18.6 9.26 20.9 10.5 mA mA SYSCLK = 1 MHz, relative to VDD = 3.3 V SYSCLK = 24 MHz, relative to VDD = 3.3 V Rev. 1.5 41 %/V 39 %/V 25 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 3.1. Global DC Electrical Characteristics (Continued) –40 to +85 °C, 25 MHz System Clock unless otherwise specified. Parameter IDD Frequency Sensitivity3,6 Digital Supply Current (Stop Mode, shutdown) Conditions Min Typ Max Units VDD = 3.3 V, SYSCLK < 1 MHz, T = 25 ºC VDD = 3.3 V, SYSCLK > 1 MHz, T = 25 ºC 0.44 mA/MHz 0.32 mA/MHz VDD = 3.6 V, SYSCLK < 1 MHz, T = 25 ºC VDD = 3.6 V, SYSCLK > 1 MHz, T = 25 ºC 0.49 mA/MHz 0.36 mA/MHz < 0.1 µA 8.69 mA 9.59 mA < 0.1 µA Oscillator not running, VDD monitor disabled Digital Supply Current for USB VDD = 3.3 V, USB Clock = 48 MHz Module (USB Active Mode) VDD = 3.6 V, USB Clock = 48 MHz Digital Supply Current for USB Oscillator not running Module (USB Suspend Mode) VDD monitor disabled Notes: 1. USB Requires 3.0 V Minimum Supply Voltage. 2. SYSCLK must be at least 32 kHz to enable debugging. 3. Based on device characterization of data; Not production tested. 4. Active and Inactive IDD at voltages and frequencies other than those specified can be calculated using the IDD Supply Sensitivity. For example, if the VDD is 3.0 V instead of 3.3 V at 24 MHz: IDD = 13.9 mA typical at 3.3 V and SYSCLK = 24 MHz. From this, IDD = 13.9 mA + 0.46 x (3.0 V – 3.3 V) = 13.76 mA at 3.0 V and SYSCLK = 24 MHz. 5. IDD can be estimated for frequencies < 30 MHz by multiplying the frequency of interest by the frequency sensitivity number for that range. When using these numbers to estimate IDD for > 30 MHz, the estimate should be the current at 24 MHz (or 48 MHz) minus the difference in current indicated by the frequency sensitivity number. For example: VDD = 3.3 V; SYSCLK = 35 MHz, IDD = 13.9 mA – (24 MHz – 35 MHz) x 0.44 mA/MHz = 18.74 mA. 6. Idle IDD can be estimated for frequencies < 1 MHz by multiplying the frequency of interest by the frequency sensitivity number for that range. When using these numbers to estimate Idle IDD for > 1 MHz, the estimate should be the current at 24 MHz (or 48 MHz) minus the difference in current indicated by the frequency sensitivity number. For example: VDD = 3.3 V; SYSCLK = 5 MHz, Idle IDD = 8.25 mA – (24 MHz – 5 MHz) x 0.32 mA/MHz = 2.17 mA. Other electrical characteristics tables are found in the data sheet section corresponding to the associated peripherals. For more information on electrical characteristics for a specific peripheral, refer to the page indicated in Table 3.2. 26 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 3.2. Index to Electrical Characteristics Tables Table Title ADC0 Electrical Characteristics Voltage Reference Electrical Characteristics Comparator Electrical Characteristics Voltage Regulator Electrical Specifications Reset Electrical Characteristics Flash Electrical Characteristics AC Parameters for External Memory Interface Oscillator Electrical Characteristics Port I/O DC Electrical Characteristics USB Transceiver Electrical Characteristics Page No. 56 58 68 69 106 109 130 141 158 187 Rev. 1.5 27 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 4. Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Name VDD Pin Numbers 48-pin 32-pin 10 6 Type Power In 2.7–3.6 V Power Supply Voltage Input. Power Out GND 7 3 RST/ 13 9 C2CK Description 3.3 V Voltage Regulator Output. See Section 8. Ground. D I/O Device Reset. Open-drain output of internal POR or VDD monitor. An external source can initiate a system reset by driving this pin low for at least 15 µs. See Section 11. D I/O Clock signal for the C2 Debug Interface. C2D 14 — D I/O Bi-directional data signal for the C2 Debug Interface. P3.0 / — 10 D I/O Port 3.0. See Section 15 for a complete description of Port 3. C2D D I/O Bi-directional data signal for the C2 Debug Interface. 28 REGIN 11 7 Power In 5 V Regulator Input. This pin is the input to the on-chip voltage regulator. VBUS 12 8 D In VBUS Sense Input. This pin should be connected to the VBUS signal of a USB network. A 5 V signal on this pin indicates a USB network connection. D+ 8 4 D I/O USB D+. D- 9 5 D I/O USB D–. P0.0 6 2 D I/O or Port 0.0. See Section 15 for a complete description of Port A In 0. P0.1 5 1 D I/O or Port 0.1. A In P0.2 4 32 D I/O or Port 0.2. A In P0.3 3 31 D I/O or Port 0.3. A In P0.4 2 30 D I/O or Port 0.4. A In P0.5 1 29 D I/O or Port 0.5. A In P0.6 48 28 D I/O or Port 0.6. A In P0.7 47 27 D I/O or Port 0.7. A In Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D (Continued) Name Pin Numbers 48-pin 32-pin Type Description P1.0 46 26 D I/O or Port 1.0. See Section 15 for a complete description of Port A In 1. P1.1 45 25 D I/O or Port 1.1. A In P1.2 44 24 D I/O or Port 1.2. A In P1.3 43 23 D I/O or Port 1.3. A In P1.4 42 22 D I/O or Port 1.4. A In P1.5 41 21 D I/O or Port 1.5. A In P1.6 40 20 D I/O or Port 1.6. A In P1.7 39 19 D I/O or Port 1.7. A In P2.0 38 18 D I/O or Port 2.0. See Section 15 for a complete description of Port A In 2. P2.1 37 17 D I/O or Port 2.1. A In P2.2 36 16 D I/O or Port 2.2. A In P2.3 35 15 D I/O or Port 2.3. A In P2.4 34 14 D I/O or Port 2.4. A In P2.5 33 13 D I/O or Port 2.5. A In P2.6 32 12 D I/O or Port 2.6. A In P2.7 31 11 D I/O or Port 2.7. A In P3.0 30 — D I/O or Port 3.0. See Section 15 for a complete description of Port A In 3. P3.1 29 — D I/O or Port 3.1. A In P3.2 28 — D I/O or Port 3.2. A In Rev. 1.5 29 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D (Continued) Name 30 Pin Numbers 48-pin 32-pin Type Description P3.3 27 — D I/O or Port 3.3. A In P3.4 26 — D I/O or Port 3.4. A In P3.5 25 — D I/O or Port 3.5. A In P3.6 24 — D I/O or Port 3.6. A In P3.7 23 — D I/O or Port 3.7. A In P4.0 22 — D I/O or Port 4.0. See Section 15 for a complete description of Port A In 4. P4.1 21 — D I/O or Port 4.1. A In P4.2 20 — D I/O or Port 4.2. A In P4.3 19 — D I/O or Port 4.3. A In P4.4 18 — D I/O or Port 4.4. A In P4.5 17 — D I/O or Port 4.5. A In P4.6 16 — D I/O or Port 4.6. A In P4.7 15 — D I/O or Port 4.7. A In Rev. 1.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 48 47 46 45 44 43 42 41 40 39 38 37 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D P0.5 1 36 P2.2 P0.4 2 35 P2.3 P0.3 3 34 P2.4 P0.2 4 33 P2.5 P0.1 5 32 P2.6 P0.0 6 31 P2.7 GND 7 30 P3.0 D+ 8 29 P3.1 D- 9 28 P3.2 VDD 10 27 P3.3 REGIN 11 26 P3.4 VBUS 12 25 P3.5 21 22 23 24 P4.0 P3.7 P3.6 18 P4.4 P4.1 17 P4.5 20 16 P4.6 P4.2 15 P4.7 19 14 C2D P4.3 13 RST / C2CK C8051F340/1/4/5/8/C-GQ Top View Figure 4.1. TQFP-48 Pinout Diagram (Top View) Rev. 1.5 31 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Figure 4.2. TQFP-48 Package Diagram Table 4.2. TQFP-48 Package Dimensions Dimension A A1 A2 b c D D1 e E E1 L aaa bbb ccc ddd θ Min — 0.05 0.95 0.17 0.09 0.45 0° Nom — — 1.00 0.22 — 9.00 BSC 7.00 BSC 0.50 BSC 9.00 BSC 7.00 BSC 0.60 0.20 0.20 0.08 0.08 3.5° Max 1.20 0.15 1.05 0.27 0.20 0.75 7° Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MS-026, variation ABC. 4. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 32 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Figure 4.3. TQFP-48 Recommended PCB Land Pattern Table 4.3. TQFP-48 PCB Land Pattern Dimensions Dimension Min Max C1 C2 E X1 Y1 8.30 8.30 8.40 8.40 0.50 BSC 0.20 1.40 0.30 1.50 Notes: General: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. Solder Mask Design: 3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design: 4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. The stencil thickness should be 0.125 mm (5 mils). 6. The ratio of stencil aperture to land pad size should be 1:1 for all pads. Card Assembly: 7. A No-Clean, Type-3 solder paste is recommended. 8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.5 33 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 32 31 30 29 28 27 26 25 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D P0.1 1 24 P1.2 P0.0 2 23 P1.3 GND 3 22 P1.4 D+ 4 21 P1.5 D- 5 20 P1.6 VDD 6 19 P1.7 REGIN 7 18 P2.0 VBUS 8 17 P2.1 9 10 11 12 13 14 15 16 RST / C2CK P3.0 / C2D P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 C8051F342/3/6/7/9/A/B/D-GQ Top View Figure 4.4. LQFP-32 Pinout Diagram (Top View) 34 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Figure 4.5. LQFP-32 Package Diagram Table 4.4. LQFP-32 Package Dimensions Dimension A A1 A2 b c D D1 e E E1 L aaa bbb ccc ddd θ Min — 0.05 1.35 0.30 0.09 0.45 0° Nom — — 1.40 0.37 — 9.00 BSC 7.00 BSC 0.80 BSC 9.00 BSC 7.00 BSC 0.60 0.20 0.20 0.10 0.20 3.5° Max 1.60 0.15 1.45 0.45 0.20 0.75 7° Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MS-026, variation BBA. 4. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.5 35 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Figure 4.6. LQFP-32 Recommended PCB Land Pattern Table 4.5. LQFP-32 PCB Land Pattern Dimensions Dimension Min Max C1 C2 E X1 Y1 8.40 8.40 8.50 8.50 0.80 BSC 0.40 1.25 0.50 1.35 Notes: General: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. Solder Mask Design: 3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design: 4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. The stencil thickness should be 0.125 mm (5 mils). 6. The ratio of stencil aperture to land pad size should be 1:1 for all pads. Card Assembly: 7. A No-Clean, Type-3 solder paste is recommended. 8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 36 Rev. 1.5 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 32 31 30 29 28 27 26 25 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D P0.1 1 24 P1.2 P0.0 2 23 P1.3 GND 3 22 P1.4 D+ 4 21 P1.5 D- 5 20 P1.6 VDD 6 19 P1.7 REGIN 7 18 P2.0 17 P2.1 C8051F342/3/6/7/9/A/B-GM Top View GND (optional) 14 15 16 P2.3 P2.2 12 P2.6 P2.4 11 P2.7 13 10 P3.0 / C2D P2.5 9 8 RST / C2CK VBUS Figure 4.7. QFN-32 Pinout Diagram (Top View) Rev. 1.5 37 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Figure 4.8. QFN-32 Package Drawing Table 4.6. QFN-32 Package Dimensions Dimension Min Nom Max A 0.80 0.9 1.00 A1 0.00 0.02 0.05 b 0.18 0.25 0.30 D D2 5.00 BSC 3.20 3.30 e 0.50 BSC E 5.00 BSC 3.40 E2 3.20 3.30 3.40 L 0.30 0.40 0.50 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-220, variation VHHD except for custom features D2, E2, and L which are toleranced per supplier designation. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 38 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 4.6. QFN-32 Package Dimensions (Continued) Dimension Min Nom Max L1 0.00 — 0.15 aaa — — 0.15 bbb — — 0.10 ddd — — 0.05 eee — — 0.08 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-220, variation VHHD except for custom features D2, E2, and L which are toleranced per supplier designation. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.5 39 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Figure 4.9. QFN-32 Recommended PCB Land Pattern Table 4.7. QFN-32 PCB Land Pattern Dimesions Dimension Min Max Dimension Min Max C1 C2 E X1 4.80 4.80 4.90 4.90 X2 Y1 Y2 3.20 0.75 3.20 3.40 0.85 3.40 0.50 BSC 0.20 0.30 Notes: General: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. Solder Mask Design: 3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60μm minimum, all the way around the pad. Stencil Design: 4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. The stencil thickness should be 0.125 mm (5 mils). 6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins. 7. A 3x3 array of 1.0 mm openings on a 1.2mm pitch should be used for the center pad to assure the proper paste volume. Card Assembly: 8. A No-Clean, Type-3 solder paste is recommended. 9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 40 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 5. 10-Bit ADC (ADC0, C8051F340/1/2/3/4/5/6/7/A/B Only) The ADC0 subsystem for the C8051F34x devices consists of two analog multiplexers (referred to collectively as AMUX0), and a 200 ksps, 10-bit successive-approximation-register ADC with integrated track-and-hold and programmable window detector. The AMUX0, data conversion modes, and window detector are all configured under software control via the Special Function Registers shown in Figure 5.1. ADC0 operates in both Single-ended and Differential modes, and may be configured to measure voltages at port pins, the Temperature Sensor output, or VDD with respect to a port pin, VREF, or GND. The connection options for AMUX0 are detailed in SFR Definition 5.1 and SFR Definition 5.2. The ADC0 subsystem is enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1. The ADC0 subsystem is in low power shutdown when this bit is logic 0. AD0CM0 AD0CM1 AD0CM2 AD0WINT AD0INT ADC0L 10-Bit SAR AIN+ ADC AIN- Negative Input (AIN-) AMUX SYSCLK VREF AD0BUSY AD0EN Start Conversion Temp Sensor Port I/O Pins* AD0TM AMX0P0 AMX0P1 AMX0P2 VDD Positive Input (AIN+) AMUX 000 AD0BUSY (W) 001 Timer 0 Overflow 010 Timer 2 Overflow 011 Timer 1 Overflow 100 CNVSTR Input 101 Timer 3 Overflow ADC0H VDD ADC0CN REF Port I/O Pins* AMX0P3 AMX0P4 AMX0P AD0WINT * 21 Selections on 32-pin package 20 Selections on 48-pin package AMX0N AD0SC0 AD0LJST AD0SC1 AD0SC2 AD0SC3 AD0SC4 AMX0N0 AMX0N1 AMX0N2 AMX0N3 AMX0N4 GND ADC0CF 32 ADC0LTH ADC0LTL Window Compare Logic ADC0GTH ADC0GTL Figure 5.1. ADC0 Functional Block Diagram Rev. 1.5 41 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 5.1. Analog Multiplexer AMUX0 selects the positive and negative inputs to the ADC. The positive input (AIN+) can be connected to individual Port pins, the on-chip temperature sensor, or the positive power supply (VDD). The negative input (AIN-) can be connected to individual Port pins, VREF, or GND. When GND is selected as the negative input, ADC0 operates in Single-ended Mode; at all other times, ADC0 operates in Differential Mode. The ADC0 input channels are selected in the AMX0P and AMX0N registers as described in SFR Definition 5.1 and SFR Definition 5.2. The conversion code format differs between Single-ended and Differential modes. The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code from the ADC at the completion of each conversion. Data can be right-justified or left-justified, depending on the setting of the AD0LJST bit (ADC0CN.0). When in Single-ended Mode, conversion codes are represented as 10-bit unsigned integers. Inputs are measured from ‘0’ to VREF x 1023/1024. Example codes are shown below for both right-justified and left-justified data. Unused bits in the ADC0H and ADC0L registers are set to ‘0’. Input Voltage (Single-Ended) VREF x 1023/1024 VREF x 512/1024 VREF x 256/1024 0 Right-Justified ADC0H:ADC0L (AD0LJST = 0) 0x03FF 0x0200 0x0100 0x0000 Left-Justified ADC0H:ADC0L (AD0LJST = 1) 0xFFC0 0x8000 0x4000 0x0000 When in Differential Mode, conversion codes are represented as 10-bit signed 2’s complement numbers. Inputs are measured from –VREF to VREF x 511/512. Example codes are shown below for both right-justified and left-justified data. For right-justified data, the unused MSBs of ADC0H are a sign-extension of the data word. For left-justified data, the unused LSBs in the ADC0L register are set to ‘0’. Input Voltage (Differential) VREF x 511/512 VREF x 256/512 0 –VREF x 256/512 –VREF Right-Justified ADC0H:ADC0L (AD0LJST = 0) 0x01FF 0x0100 0x0000 0xFF00 0xFE00 Left-Justified ADC0H:ADC0L (AD0LJST = 1) 0x7FC0 0x4000 0x0000 0xC000 0x8000 Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be configured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for analog input, set to ‘0’ the corresponding bit in register PnMDIN (for n = 0,1,2,3). To force the Crossbar to skip a Port pin, set to ‘1’ the corresponding bit in register PnSKIP (for n = 0,1,2). See Section “15. Port Input/ Output” on page 142 for more Port I/O configuration details. 42 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 5.2. Temperature Sensor The temperature sensor transfer function is shown in Figure 5.2. The output voltage (VTEMP) is the positive ADC input when the temperature sensor is selected by bits AMX0P4-0 in register AMX0P. Values for the Offset and Slope parameters can be found in Table 5.1. VTEMP = (Gain x TempC) + Offset Voltage TempC = (VTEMP - Offset) / Gain Gain (V / deg C) Offset (V at 0 Celsius) Temperature Figure 5.2. Temperature Sensor Transfer Function The uncalibrated temperature sensor output is extremely linear and suitable for relative temperature measurements (see Table 5.1 for linearity specifications). For absolute temperature measurements, offset and/ or gain calibration is recommended. Typically a 1-point (offset) calibration includes the following steps: Step 1. Control/measure the ambient temperature (this temperature must be known). Step 2. Power the device, and delay for a few seconds to allow for self-heating. Step 3. Perform an ADC conversion with the temperature sensor selected as the positive input and GND selected as the negative input. Step 4. Calculate the offset characteristics, and store this value in non-volatile memory for use with subsequent temperature sensor measurements. Figure 5.3 shows the typical temperature sensor error assuming a 1-point calibration at 25 °C. Note that parameters which affect ADC measurement, in particular the voltage reference value, will also affect temperature measurement. Rev. 1.5 43 Error (degrees C) C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 5.0 0 5.0 0 4.0 0 4.0 0 3.0 0 3.0 0 2.0 0 2.0 0 1.0 0 1.0 0 0.0 0-40.00 -20.00 0.0 0 20.0 0 40.0 0 60.0 0 0.0 0 -1.00 -1.00 -2.00 -2.00 -3.00 -3.00 -4.00 -4.00 -5.00 -5.00 Temperature (degrees C) Figure 5.3. Temperature Sensor Error with 1-Point Calibration (VREF = 2.40 V) 44 80.0 0 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 5.3. Modes of Operation ADC0 has a maximum conversion speed of 200 ksps. The ADC0 conversion clock is a divided version of the system clock, determined by the AD0SC bits in the ADC0CF register (system clock divided by (AD0SC + 1) for 0 ≤ AD0SC ≤ 31). 5.3.1. Starting a Conversion A conversion can be initiated in one of five ways, depending on the programmed states of the ADC0 Start of Conversion Mode bits (AD0CM2–0) in register ADC0CN. Conversions may be initiated by one of the following: 1. 2. 3. 4. 5. 6. Writing a ‘1’ to the AD0BUSY bit of register ADC0CN A Timer 0 overflow (i.e., timed continuous conversions) A Timer 2 overflow A Timer 1 overflow A rising edge on the CNVSTR input signal A Timer 3 overflow Writing a ‘1’ to AD0BUSY provides software control of ADC0 whereby conversions are performed "on-demand". During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conversion is complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt flag (AD0INT). Note: When polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT) should be used. Converted data is available in the ADC0 data registers, ADC0H:ADC0L, when bit AD0INT is logic 1. Note that when Timer 2 or Timer 3 overflows are used as the conversion source, Low Byte overflows are used if Timer 2/3 is in 8-bit mode; High byte overflows are used if Timer 2/3 is in 16-bit mode. See Section “21. Timers” on page 235 for timer configuration. Important Note About Using CNVSTR: The CNVSTR input pin also functions as a Port pin. When the CNVSTR input is used as the ADC0 conversion source, the associated Port pin should be skipped by the Digital Crossbar. To configure the Crossbar to skip a pin, set the corresponding bit in the PnSKIP register to ‘1’. See Section “15. Port Input/Output” on page 142 for details on Port I/O configuration. Rev. 1.5 45 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 5.3.2. Tracking Modes The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0 input is continuously tracked, except when a conversion is in progress. When the AD0TM bit is logic 1, ADC0 operates in low-power track-and-hold mode. In this mode, each conversion is preceded by a tracking period of 3 SAR clocks (after the start-of-conversion signal). When the CNVSTR signal is used to initiate conversions in low-power tracking mode, ADC0 tracks only when CNVSTR is low; conversion begins on the rising edge of CNVSTR (see Figure 5.4). Tracking can also be disabled (shutdown) when the device is in low power standby or sleep modes. Low-power track-and-hold mode is also useful when AMUX settings are frequently changed, due to the settling time requirements described in Section “5.3.3. Settling Time Requirements” on page 47. A. ADC0 Timing for External Trigger Source CNVSTR (AD0CM[2:0]=100) 1 2 3 4 5 6 7 8 9 10 11 SAR Clocks AD0TM=1 AD0TM=0 Write '1' to AD0BUSY, Timer 0, Timer 2, Timer 1, Timer 3 Overflow (AD0CM[2:0]=000, 001,010 011, 101) Low Power or Convert Track Track or Convert Convert Low Power Mode Convert Track B. ADC0 Timing for Internal Trigger Source 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SAR Clocks AD0TM=1 Low Power or Convert Track 1 2 3 Convert 4 5 6 7 8 9 Low Power Mode 10 11 SAR Clocks AD0TM=0 Track or Convert Convert Track Figure 5.4. 10-Bit ADC Track and Conversion Example Timing 46 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 5.3.3. Settling Time Requirements When the ADC0 input configuration is changed (i.e., a different AMUX0 selection is made), a minimum tracking time is required before an accurate conversion can be performed. This tracking time is determined by the AMUX0 resistance, the ADC0 sampling capacitance, any external source resistance, and the accuracy required for the conversion. Note that in low-power tracking mode, three SAR clocks are used for tracking at the start of every conversion. For most applications, these three SAR clocks will meet the minimum tracking time requirements. Figure 5.5 shows the equivalent ADC0 input circuits for both Differential and Single-ended modes. Notice that the equivalent time constant for both input circuits is the same. The required ADC0 settling time for a given settling accuracy (SA) may be approximated by Equation 5.1. When measuring the Temperature Sensor output or VDD with respect to GND, RTOTAL reduces to RMUX. See Table 5.1 for ADC0 minimum settling time requirements. n 2 t = ln  ------- × R TOTAL C SAMPLE SA Equation 5.1. ADC0 Settling Time Requirements Where: SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB) t is the required settling time in seconds RTOTAL is the sum of the AMUX0 resistance and any external source resistance. n is the ADC resolution in bits (10). Differential Mode Single-Ended Mode MUX Select MUX Select Px.x Px.x RMUX = 5k RMUX = 5k CSAMPLE = 5pF CSAMPLE = 5pF RCInput= RMUX * CSAMPLE RCInput= RMUX * CSAMPLE CSAMPLE = 5pF Px.x RMUX = 5k MUX Select Figure 5.5. ADC0 Equivalent Input Circuits Rev. 1.5 47 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select R R R R/W R/W R/W R/W - - - AMX0P4 AMX0P3 AMX0P2 AMX0P1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 R/W Reset Value AMX0P0 00000000 Bit0 SFR Address: 0xBB Bits7–5: UNUSED. Read = 000b; Write = don’t care. Bits4–0: AMX0P4–0: AMUX0 Positive Input Selection AMX0P4-0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 - 11101 11110 11111 48 ADC0 Positive Input (32-pin Package) P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P0.0 P0.1 P0.4 P0.5 RESERVED Temp Sensor VDD Rev. 1.5 ADC0 Positive Input (48-pin Package) P2.0 P2.1 P2.2 P2.3 P2.5 P2.6 P3.0 P3.1 P3.4 P3.5 P3.7 P4.0 P4.3 P4.4 P4.5 P4.6 RESERVED P0.3 P0.4 P1.1 P1.2 RESERVED Temp Sensor VDD C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select R R R R/W R/W R/W R/W - - - AMX0N4 AMX0N3 AMX0N2 AMX0N1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 R/W Reset Value AMX0N0 00000000 Bit0 SFR Address: 0xBA Bits7–5: UNUSED. Read = 000b; Write = don’t care. Bits4–0: AMX0N4–0: AMUX0 Negative Input Selection. Note that when GND is selected as the Negative Input, ADC0 operates in Single-ended mode. For all other Negative Input selections, ADC0 operates in Differential mode. AMX0N4-0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 - 11101 11110 11111 ADC0 Negative Input (32-pin Package) P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P0.0 P0.1 P0.4 P0.5 RESERVED VREF GND (Single-Ended Mode) Rev. 1.5 ADC0 Negative Input (48-pin Package) P2.0 P2.1 P2.2 P2.3 P2.5 P2.6 P3.0 P3.1 P3.4 P3.5 P3.7 P4.0 P4.3 P4.4 P4.5 P4.6 RESERVED P0.3 P0.4 P1.1 P1.2 RESERVED VREF GND (Single-Ended Mode) 49 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 5.3. ADC0CF: ADC0 Configuration R/W R/W R/W R/W AD0SC4 AD0SC3 AD0SC2 AD0SC1 Bit7 Bit6 Bit5 Bit4 R/W R/W AD0SC0 AD0LJST Bit3 Bit2 R/W R/W Reset Value - - 11111000 Bit1 Bit0 SFR Address: 0xBC Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system clock by the following equation, where AD0SC refers to the 5-bit value held in bits AD0SC4-0. SAR Conversion clock requirements are given in Table 5.1. SYSCLK AD0SC = ---------------------- – 1 CLK SAR Bit2: AD0LJST: ADC0 Left Justify Select. 0: Data in ADC0H:ADC0L registers are right-justified. 1: Data in ADC0H:ADC0L registers are left-justified. Bits1–0: UNUSED. Read = 00b; Write = don’t care. SFR Definition 5.4. ADC0H: ADC0 Data Word MSB R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xBE Bits7–0: ADC0 Data Word High-Order Bits. For AD0LJST = 0: Bits 7–2 are the sign extension of Bit1. Bits 1-0 are the upper 2 bits of the 10-bit ADC0 Data Word. For AD0LJST = 1: Bits 7–0 are the most-significant bits of the 10-bit ADC0 Data Word. SFR Definition 5.5. ADC0L: ADC0 Data Word LSB R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xBD Bits7–0: ADC0 Data Word Low-Order Bits. For AD0LJST = 0: Bits 7–0 are the lower 8 bits of the 10-bit Data Word. For AD0LJST = 1: Bits 7–6 are the lower 2 bits of the 10-bit Data Word. Bits 5–0 will always read ‘0’. 50 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 5.6. ADC0CN: ADC0 Control R/W R/W AD0EN AD0TM Bit7 Bit6 R/W R/W R/W R/W AD0INT AD0BUSY AD0WINT AD0CM2 Bit5 Bit4 Bit3 R/W R/W Reset Value AD0CM1 AD0CM0 00000000 Bit2 Bit1 Bit0 (bit addressable) SFR Address: 0xE8 Bit7: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ADC0 Enabled. ADC0 is active and ready for data conversions. Bit6: AD0TM: ADC0 Track Mode Bit. 0: Normal Track Mode: When ADC0 is enabled, tracking is continuous unless a conversion is in progress. 1: Low-power Track Mode: Tracking Defined by AD0CM2-0 bits (see below). Bit5: AD0INT: ADC0 Conversion Complete Interrupt Flag. 0: ADC0 has not completed a data conversion since the last time AD0INT was cleared. 1: ADC0 has completed a data conversion. Bit4: AD0BUSY: ADC0 Busy Bit. Read: 0: ADC0 conversion is complete or a conversion is not currently in progress. AD0INT is set to logic 1 on the falling edge of AD0BUSY. 1: ADC0 conversion is in progress. Write: 0: No Effect. 1: Initiates ADC0 Conversion if AD0CM2-0 = 000b Bit3: AD0WINT: ADC0 Window Compare Interrupt Flag. 0: ADC0 Window Comparison Data match has not occurred since this flag was last cleared. 1: ADC0 Window Comparison Data match has occurred. Bits2–0: AD0CM2–0: ADC0 Start of Conversion Mode Select. When AD0TM = 0: 000: ADC0 conversion initiated on every write of ‘1’ to AD0BUSY. 001: ADC0 conversion initiated on overflow of Timer 0. 010: ADC0 conversion initiated on overflow of Timer 2. 011: ADC0 conversion initiated on overflow of Timer 1. 100: ADC0 conversion initiated on rising edge of external CNVSTR. 101: ADC0 conversion initiated on overflow of Timer 3. 11x: Reserved. When AD0TM = 1: 000: Tracking initiated on write of ‘1’ to AD0BUSY and lasts 3 SAR clocks, followed by conversion. 001: Tracking initiated on overflow of Timer 0 and lasts 3 SAR clocks, followed by conversion. 010: Tracking initiated on overflow of Timer 2 and lasts 3 SAR clocks, followed by conversion. 011: Tracking initiated on overflow of Timer 1 and lasts 3 SAR clocks, followed by conversion. 100: ADC0 tracks only when CNVSTR input is logic low; conversion starts on rising CNVSTR edge. 101: Tracking initiated on overflow of Timer 3 and lasts 3 SAR clocks, followed by conversion. 11x: Reserved. Rev. 1.5 51 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 5.4. Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 conversion results to user-programmed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system response times. The window detector interrupt flag (AD0WINT in register ADC0CN) can also be used in polled mode. The ADC0 Greater-Than (ADC0GTH, ADC0GTL) and Less-Than (ADC0LTH, ADC0LTL) registers hold the comparison values. The window detector flag can be programmed to indicate when measured data is inside or outside of the user-programmed limits, depending on the contents of the ADC0 Less-Than and ADC0 Greater-Than registers. The Window Detector registers must be written with the same format (left/right justified, signed/unsigned) as that of the current ADC configuration (left/right justified, single-ended/differential). SFR Definition 5.7. ADC0GTH: ADC0 Greater-Than Data High Byte R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 11111111 0xC4 Bits7–0: High byte of ADC0 Greater-Than Data Word. SFR Definition 5.8. ADC0GTL: ADC0 Greater-Than Data Low Byte R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 11111111 0xC3 Bits7–0: Low byte of ADC0 Greater-Than Data Word. 52 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 5.9. ADC0LTH: ADC0 Less-Than Data High Byte R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 00000000 0xC6 Bits7–0: High byte of ADC0 Less-Than Data Word. SFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xC5 Bits7–0: Low byte of ADC0 Less-Than Data Word. Rev. 1.5 53 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 5.4.1. Window Detector In Single-Ended Mode Figure 5.6 shows two example window comparisons for right-justified, single-ended data, with ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). In single-ended mode, the input voltage can range from ‘0’ to VREF x (1023/1024) with respect to GND, and is represented by a 10-bit unsigned integer value. In the left example, an AD0WINT interrupt will be generated if the ADC0 conversion word (ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL (if 0x0040 < ADC0H:ADC0L < 0x0080). In the right example, and AD0WINT interrupt will be generated if the ADC0 conversion word is outside of the range defined by the ADC0GT and ADC0LT registers (if ADC0H:ADC0L < 0x0040 or ADC0H:ADC0L > 0x0080). Figure 5.7 shows an example using left-justified data with equivalent ADC0GT and ADC0LT register settings. ADC0H:ADC0L ADC0H:ADC0L Input Voltage (Px.x - GND) VREF x (1023/1024) Input Voltage (Px.x - GND) VREF x (1023/1024) 0x03FF 0x03FF AD0WINT not affected AD0WINT=1 0x0081 VREF x (128/1024) 0x0080 0x0081 ADC0LTH:ADC0LTL VREF x (128/1024) 0x007F 0x0080 0x007F AD0WINT=1 VREF x (64/1024) 0x0041 0x0040 ADC0GTH:ADC0GTL VREF x (64/1024) 0x003F 0x0041 0x0040 ADC0GTH:ADC0GTL AD0WINT not affected ADC0LTH:ADC0LTL 0x003F AD0WINT=1 AD0WINT not affected 0 0x0000 0 0x0000 Figure 5.6. ADC Window Compare Example: Right-Justified Single-Ended Data ADC0H:ADC0L ADC0H:ADC0L Input Voltage (Px.x - GND) VREF x (1023/1024) Input Voltage (Px.x - GND) 0xFFC0 VREF x (1023/1024) 0xFFC0 AD0WINT not affected AD0WINT=1 0x2040 VREF x (128/1024) 0x2000 0x2040 ADC0LTH:ADC0LTL VREF x (128/1024) 0x1FC0 0x2000 0x1FC0 AD0WINT=1 0x1040 VREF x (64/1024) 0x1000 0x1040 ADC0GTH:ADC0GTL VREF x (64/1024) 0x0FC0 0x1000 AD0WINT not affected ADC0LTH:ADC0LTL 0x0FC0 AD0WINT=1 AD0WINT not affected 0 ADC0GTH:ADC0GTL 0x0000 0 0x0000 Figure 5.7. ADC Window Compare Example: Left-Justified Single-Ended Data 54 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 5.4.2. Window Detector In Differential Mode Figure 5.8 shows two example window comparisons for right-justified, differential data, with ADC0LTH:ADC0LTL = 0x0040 (+64d) and ADC0GTH:ADC0GTH = 0xFFFF (-1d). In differential mode, the measurable voltage between the input pins is between -VREF and VREF*(511/512). Output codes are represented as 10-bit 2’s complement signed integers. In the left example, an AD0WINT interrupt will be generated if the ADC0 conversion word (ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL (if 0xFFFF (-1d) < ADC0H:ADC0L < 0x0040 (64d)). In the right example, an AD0WINT interrupt will be generated if the ADC0 conversion word is outside of the range defined by the ADC0GT and ADC0LT registers (if ADC0H:ADC0L < 0xFFFF (-1d) or ADC0H:ADC0L > 0x0040 (+64d)). Figure 5.9 shows an example using left-justified data with equivalent ADC0GT and ADC0LT register settings. ADC0H:ADC0L ADC0H:ADC0L Input Voltage (Px.x - Px.x) VREF x (511/512) Input Voltage (Px.x - Px.x) 0x01FF VREF x (511/512) 0x01FF AD0WINT not affected AD0WINT=1 0x0041 VREF x (64/512) 0x0040 0x0041 ADC0LTH:ADC0LTL VREF x (64/512) 0x003F 0x0040 0x003F AD0WINT=1 0x0000 VREF x (-1/512) 0xFFFF 0x0000 ADC0GTH:ADC0GTL VREF x (-1/512) 0xFFFE 0xFFFF ADC0GTH:ADC0GTL AD0WINT not affected ADC0LTH:ADC0LTL 0xFFFE AD0WINT=1 AD0WINT not affected -VREF 0x0200 -VREF 0x0200 Figure 5.8. ADC Window Compare Example: Right-Justified Differential Data ADC0H:ADC0L ADC0H:ADC0L Input Voltage (Px.x - Px.x) VREF x (511/512) Input Voltage (Px.x - Px.y) 0x7FC0 VREF x (511/512) 0x7FC0 AD0WINT not affected AD0WINT=1 0x1040 VREF x (64/512) 0x1000 0x1040 ADC0LTH:ADC0LTL VREF x (64/512) 0x0FC0 0x1000 0x0FC0 AD0WINT=1 0x0000 VREF x (-1/512) 0xFFC0 0x0000 ADC0GTH:ADC0GTL VREF x (-1/512) 0xFF80 0xFFC0 0x8000 AD0WINT not affected ADC0LTH:ADC0LTL 0xFF80 AD0WINT=1 AD0WINT not affected -VREF ADC0GTH:ADC0GTL -VREF 0x8000 Figure 5.9. ADC Window Compare Example: Left-Justified Differential Data Rev. 1.5 55 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 5.1. ADC0 Electrical Characteristics VDD = 3.0 V, VREF = 2.40 V, –40 to +85 °C unless otherwise specified Parameter Conditions Min Typ Max Units DC Accuracy Resolution 10 Integral Nonlinearity Differential Nonlinearity Guaranteed Monotonic bits ±0.5 ±1 LSB ±0.5 ±1 LSB Offset Error –15 0 +15 LSB Full Scale Error –15 –1 +15 LSB Offset Temperature Coefficient 10 ppm/°C Dynamic Performance (10 kHz sine-wave Single-ended input, 1 dB below Full Scale, 200 ksps) Signal-to-Noise Plus Distortion Total Harmonic Distortion 51 Up to the 5th harmonic Spurious-Free Dynamic Range 52.5 dB –67 dB 78 dB Conversion Rate SAR Conversion Clock 3 MHz Conversion Time in SAR Clocks 10 clocks Track/Hold Acquisition Time 300 ns Throughput Rate 200 ksps 0 –VREF VREF VREF V V 0 VDD V Analog Inputs ADC Input Voltage Range Single Ended (AIN+ – GND) Differential (AIN+ – AIN–) Absolute Pin Voltage with respect Single Ended or Differential to GND Input Capacitance 5 pF ±0.1 °C Gain 2.86 mV/°C Gain Error2 ±33.5 µV/ºC 776 mV ±8.51 mV Temperature Sensor Linearity 1 Offset1 (Temp = 0 °C) Offset Error2 Power Specifications Power Supply Current (VDD supOperating Mode, 200 ksps plied to ADC0) 400 Power Supply Rejection ±0.3 Notes: 1. Includes ADC offset, gain, and linearity variations. 2. Represents one standard deviation from the mean. 56 Rev. 1.5 900 µA mV/V C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 6. Voltage Reference (C8051F340/1/2/3/4/5/6/7/A/B Only) The Voltage reference MUX on C8051F34x devices is configurable to use an externally connected voltage reference, the on-chip reference voltage generator, or the power supply voltage VDD (see Figure 6.1). The REFSL bit in the Reference Control register (REF0CN) selects the reference source. For the internal reference or an external source, REFSL should be set to ‘0’; For VDD as the reference source, REFSL should be set to ‘1’. The BIASE bit enables the internal ADC bias generator, which is used by the ADC and Internal Oscillator. This enable is forced to logic 1 when either of the aforementioned peripherals is enabled. The ADC bias generator may be enabled manually by writing a ‘1’ to the BIASE bit in register REF0CN; see SFR Definition 6.1 for REF0CN register details. The Reference bias generator (see Figure 6.1) is used by the Internal Voltage Reference, Temperature Sensor, and Clock Multiplier. The Reference bias is automatically enabled when any of the aforementioned peripherals are enabled. The electrical specifications for the voltage reference and bias circuits are given in Table 6.1. Important Note About the VREF Pin: The VREF pin, when not using the on-chip voltage reference or an external precision reference, can be configured as a GPIO Port pin. When using an external voltage reference or the on-chip reference, the VREF pin should be configured as analog pin and skipped by the Digital Crossbar. To configure the VREF pin for analog mode, set the corresponding bit in the PnMDIN register to ‘0’. To configure the Crossbar to skip the VREF pin, set the corresponding bit in register PnSKIP to ‘1’. Refer to Section “15. Port Input/Output” on page 142 for complete Port I/O configuration details. The temperature sensor connects to the ADC0 positive input multiplexer (see Section “5.1. Analog Multiplexer” on page 42 for details). The TEMPE bit in register REF0CN enables/disables the temperature sensor. While disabled, the temperature sensor defaults to a high impedance state and any ADC0 measurements performed on the sensor result in meaningless data. REFSL TEMPE BIASE REFBE REF0CN AD0EN EN ADC Bias To ADC, Internal Oscillator IOSCEN VDD R1 External Voltage Reference Circuit EN VREF Temp Sensor To Analog Mux 0 VREF (to ADC) GND VDD 1 CLKMUL Enable EN TEMPE Reference Bias To Clock Multiplier, Temp Sensor REFBE EN Internal Reference Figure 6.1. Voltage Reference Functional Block Diagram Rev. 1.5 57 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 6.1. REF0CN: Reference Control R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - - - - REFSL TEMPE BIASE REFBE 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xD1 Bits7–3: UNUSED. Read = 00000b; Write = don’t care. Bit3: REFSL: Voltage Reference Select. This bit selects the source for the internal voltage reference. 0: VREF pin used as voltage reference. 1: VDD used as voltage reference. Bit2: TEMPE: Temperature Sensor Enable Bit. 0: Internal Temperature Sensor off. 1: Internal Temperature Sensor on. Bit1: BIASE: Internal Analog Bias Generator Enable Bit. 0: Internal Bias Generator off. 1: Internal Bias Generator on. Bit0: REFBE: Internal Reference Buffer Enable Bit. 0: Internal Reference Buffer disabled. 1: Internal Reference Buffer enabled. Internal voltage reference driven on the VREF pin. Table 6.1. Voltage Reference Electrical Characteristics VDD = 3.0 V; –40 to +85 °C Unless Otherwise Specified Parameter Conditions Min Internal Reference (REFBE = 1) 25 °C ambient 2.38 Output Voltage VREF Short-Circuit Current VREF Temperature Coefficient Load Regulation Load = 0 to 200 µA to GND 4.7 µF tantalum, 0.1 µF ceramic VREF Turn-on Time 1 bypass VREF Turn-on Time 2 0.1 µF ceramic bypass VREF Turn-on Time 3 no bypass cap Power Supply Rejection External Reference (REFBE = 0) Input Voltage Range Input Current ADC Bias Generator Reference Bias Generator 58 Typ Max Units 2.44 2.50 10 V mA 15 ppm/°C 1.5 ppm/µA 2 ms 20 10 140 µs µs ppm/V VDD 0 Sample Rate = 200 ksps; VREF = 3.0 V Bias Generators BIASE = ‘1’ Rev. 1.5 V 12 µA 100 40 µA µA C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 7. Comparators C8051F34x devices include two on-chip programmable voltage Comparators. A block diagram of the comparators is shown in Figure 7.1, where “n” is the comparator number (0 or 1). The two Comparators operate identically with the following exceptions: (1) Their input selections differ, and (2) Comparator0 can be used as a reset source. For input selection details, refer to SFR Definition 7.2 and SFR Definition 7.5. Each Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an asynchronous “raw” output (CP0A, CP1A). The asynchronous signal is available even when the system clock is not active. This allows the Comparators to operate and generate an output with the device in STOP mode. When assigned to a Port pin, the Comparator outputs may be configured as open drain or push-pull (see Section “15.2. Port I/O Initialization” on page 147). Comparator0 may also be used as a reset source (see Section “11.5. Comparator0 Reset” on page 103). The Comparator0 inputs are selected in the CPT0MX register (SFR Definition 7.2). The CMX0P1-CMX0P0 bits select the Comparator0 positive input; the CMX0N1-CMX0N0 bits select the Comparator0 negative input. The Comparator1 inputs are selected in the CPT1MX register (SFR Definition 7.5). The CMX1P1-CMX1P0 bits select the Comparator1 positive input; the CMX1N1-CMX1N0 bits select the Comparator1 negative input. Important Note About Comparator Inputs: The Port pins selected as Comparator inputs should be configured as analog inputs in their associated Port configuration register, and configured to be skipped by the Crossbar (for details on Port configuration, see Section “15.3. General Purpose Port I/O” on page 150). Rev. 1.5 59 CMXnN2 CMXnN1 CMXnN0 CPTnCN CPTnMX C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D CPnEN CPnOUT CPnRIF CPnFIF CPnHYP1 VDD CPn Interrupt CPnHYP0 CPnHYN1 CPnHYN0 CMXnP2 CMXnP1 CMXnP0 CPn Rising-edge CPn Falling-edge Interrupt Logic CPn + CPnRIE CPnFIE + D - SET CLR Q Q D SET CLR CPn Q Q Crossbar (SYNCHRONIZER) GND CPnA CPn - Port I/O connection options vary with package (32-pin or 48-pin) CPTnMD Reset Decision Tree (Comprator 0 Only) CPnRIE CPnFIE CPnMD1 CPnMD0 Figure 7.1. Comparator Functional Block Diagram Comparator outputs can be polled in software, used as an interrupt source, and/or routed to a Port pin. When routed to a Port pin, Comparator outputs are available asynchronous or synchronous to the system clock; the asynchronous output is available even in STOP mode (with no system clock active). When disabled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state, and supply current falls to less than 100 nA. See Section “15.1. Priority Crossbar Decoder” on page 144 for details on configuring Comparator outputs via the digital Crossbar. Comparator inputs can be externally driven from –0.25 V to (VDD) + 0.25 V without damage or upset. The complete Comparator electrical specifications are given in Table 7.1. Comparator response time may be configured in software via the CPTnMD registers (see SFR Definition 7.3 and SFR Definition 7.6). Selecting a longer response time reduces the Comparator supply current. See Table 7.1 for complete timing and supply current specifications. 60 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D VIN+ VIN- CP0+ CP0- + CP0 _ OUT CIRCUIT CONFIGURATION Positive Hysteresis Voltage (Programmed with CP0HYP Bits) VIN- INPUTS Negative Hysteresis Voltage (Programmed by CP0HYN Bits) VIN+ VOH OUTPUT VOL Negative Hysteresis Disabled Positive Hysteresis Disabled Maximum Negative Hysteresis Maximum Positive Hysteresis Figure 7.2. Comparator Hysteresis Plot Comparator hysteresis is programmed using Bits3-0 in the Comparator Control Register CPTnCN (shown in SFR Definition 7.1 and SFR Definition 7.4). The amount of negative hysteresis voltage is determined by the settings of the CPnHYN bits. As shown in Figure 7.2, various levels of negative hysteresis can be programmed, or negative hysteresis can be disabled. In a similar way, the amount of positive hysteresis is determined by the setting the CPnHYP bits. Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Interrupt enable and priority control, see Section “9.3. Interrupt Handler” on page 88.) The CPnFIF flag is set to ‘1’ upon a Comparator falling-edge, and the CPnRIF flag is set to ‘1’ upon the Comparator rising-edge. Once set, these bits remain set until cleared by software. The output state of the Comparator can be obtained at any time by reading the CPnOUT bit. The Comparator is enabled by setting the CPnEN bit to ‘1’, and is disabled by clearing this bit to ‘0’. Rev. 1.5 61 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 7.1. CPT0CN: Comparator0 Control R/W R R/W R/W CP0EN CP0OUT CP0RIF CP0FIF Bit7 Bit6 Bit5 Bit4 R/W R/W R/W R/W Reset Value CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 00000000 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x9B Bit7: CP0EN: Comparator0 Enable Bit. 0: Comparator0 Disabled. 1: Comparator0 Enabled. Bit6: CP0OUT: Comparator0 Output State Flag. 0: Voltage on CP0+ < CP0–. 1: Voltage on CP0+ > CP0–. Bit5: CP0RIF: Comparator0 Rising-Edge Flag. 0: No Comparator0 Rising Edge has occurred since this flag was last cleared. 1: Comparator0 Rising Edge has occurred. Bit4: CP0FIF: Comparator0 Falling-Edge Flag. 0: No Comparator0 Falling-Edge has occurred since this flag was last cleared. 1: Comparator0 Falling-Edge Interrupt has occurred. Bits3–2: CP0HYP1–0: Comparator0 Positive Hysteresis Control Bits. 00: Positive Hysteresis Disabled. 01: Positive Hysteresis = 5 mV. 10: Positive Hysteresis = 10 mV. 11: Positive Hysteresis = 20 mV. Bits1–0: CP0HYN1–0: Comparator0 Negative Hysteresis Control Bits. 00: Negative Hysteresis Disabled. 01: Negative Hysteresis = 5 mV. 10: Negative Hysteresis = 10 mV. 11: Negative Hysteresis = 20 mV. 62 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 7.2. CPT0MX: Comparator0 MUX Selection R/W Bit7 R/W R/W R/W CMX0N2 CMX0N1 CMX0N0 Bit6 Bit5 Bit4 R/W R/W R/W - CMX0P2 CMX0P1 Bit3 Bit2 Bit1 R/W Reset Value CMX0P0 00000000 Bit0 SFR Address: 0x9F Bit7: UNUSED. Read = 0b, Write = don’t care. Bits6–4: CMX0N2–CMX0N0: Comparator0 Negative Input MUX Select. These bits select which Port pin is used as the Comparator0 negative input. CMX0N1 CMX0N1 CMX0N0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 Negative Input (32-pin Package) P1.1 P1.5 P2.1 P2.5 P0.1 Negative Input (48-pin Package) P2.1 P2.6 P3.5 P4.4 P0.4 Bit3: UNUSED. Read = 0b, Write = don’t care. Bits2–0: CMX0P2–CMX0P0: Comparator0 Positive Input MUX Select. These bits select which Port pin is used as the Comparator0 positive input. CMX0P1 CMX0P1 CMX0P0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 Positive Input (32-pin Package) P1.0 P1.4 P2.0 P2.4 P0.0 Positive Input (48-pin Package) P2.0 P2.5 P3.4 P4.3 P0.3 Note that the port pins used by the comparator depend on the package type (32-pin or 48-pin). Rev. 1.5 63 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection R/W R/W R/W R/W R/W R/W - - CP0RIE CP0FIE - - Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 R/W R/W Reset Value CP0MD1 CP0MD0 00000010 Bit1 Bit0 SFR Address: 0x9D Bits7–6: UNUSED. Read = 00b. Write = don’t care. Bit5: CP0RIE: Comparator0 Rising-Edge Interrupt Enable. 0: Comparator0 rising-edge interrupt disabled. 1: Comparator0 rising-edge interrupt enabled. Bit4: CP0FIE: Comparator0 Falling-Edge Interrupt Enable. 0: Comparator0 falling-edge interrupt disabled. 1: Comparator0 falling-edge interrupt enabled. Bits3–2: UNUSED. Read = 00b. Write = don’t care. Bits1–0: CP0MD1–CP0MD0: Comparator0 Mode Select These bits select the response time for Comparator0. Mode 0 1 2 3 CP0MD1 0 0 1 1 CP0MD0 0 1 0 1 CP0 Response Time* Fastest Response Lowest Power * See Table 7.1 for response time parameters. 64 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 7.4. CPT1CN: Comparator1 Control R/W R R/W R/W CP1EN CP1OUT CP1RIF CP1FIF Bit7 Bit6 Bit5 Bit4 R/W R/W R/W R/W Reset Value CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0 00000000 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x9A Bit7: CP1EN: Comparator1 Enable Bit. 0: Comparator1 Disabled. 1: Comparator1 Enabled. Bit6: CP1OUT: Comparator1 Output State Flag. 0: Voltage on CP1+ < CP1–. 1: Voltage on CP1+ > CP1–. Bit5: CP1RIF: Comparator1 Rising-Edge Flag. 0: No Comparator1 Rising Edge has occurred since this flag was last cleared. 1: Comparator1 Rising Edge has occurred. Bit4: CP1FIF: Comparator1 Falling-Edge Flag. 0: No Comparator1 Falling-Edge has occurred since this flag was last cleared. 1: Comparator1 Falling-Edge has occurred. Bits3–2: CP1HYP1–0: Comparator1 Positive Hysteresis Control Bits. 00: Positive Hysteresis Disabled. 01: Positive Hysteresis = 5 mV. 10: Positive Hysteresis = 10 mV. 11: Positive Hysteresis = 20 mV. Bits1–0: CP1HYN1–0: Comparator1 Negative Hysteresis Control Bits. 00: Negative Hysteresis Disabled. 01: Negative Hysteresis = 5 mV. 10: Negative Hysteresis = 10 mV. 11: Negative Hysteresis = 20 mV. Rev. 1.5 65 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 7.5. CPT1MX: Comparator1 MUX Selection R/W Bit7 R/W R/W R/W CMX1N2 CMX1N1 CMX1N0 Bit6 Bit5 Bit4 R/W R/W R/W - CMX1P2 CMX1P1 Bit3 Bit2 Bit1 R/W Reset Value CMX1P0 00000000 Bit0 SFR Address: 0x9E Bit7: UNUSED. Read = 0b, Write = don’t care. Bits6–4: CMX1N2–CMX1N0: Comparator1 Negative Input MUX Select. These bits select which Port pin is used as the Comparator1 negative input. CMX1N2 CMX1N1 CMX1N0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 Negative Input (32-pin Package) P1.3 P1.7 P2.3 P2.7 P0.5 Negative Input (48-pin Package) P2.3 P3.1 P4.0 P4.6 P1.2 Bit3: UNUSED. Read = 0b, Write = don’t care. Bits2–0: CMX1P1–CMX1P0: Comparator1 Positive Input MUX Select. These bits select which Port pin is used as the Comparator1 positive input. CMX1P2 CMX1P1 CMX1P0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 Positive Input (32-pin Package) P1.2 P1.6 P2.2 P2.6 P0.4 Positive Input (48-pin Package) P2.2 P3.0 P3.7 P4.5 P1.1 Note that the port pins used by the comparator depend on the package type (32-pin or 48-pin). 66 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 7.6. CPT1MD: Comparator1 Mode Selection R/W R/W R/W R/W R/W R/W - - CP1RIE CP1FIE - - Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 R/W R/W Reset Value CP1MD1 CP1MD0 00000010 Bit1 Bit0 SFR Address: 0x9C Bits7–6: UNUSED. Read = 00b, Write = don’t care. Bit5: CP1RIE: Comparator1 Rising-Edge Interrupt Enable. 0: Comparator1 rising-edge interrupt disabled. 1: Comparator1 rising-edge interrupt enabled. Bit4: CP1FIE: Comparator1 Falling-Edge Interrupt Enable. 0: Comparator1 falling-edge interrupt disabled. 1: Comparator1 falling-edge interrupt enabled. Bits1–0: CP1MD1–CP1MD0: Comparator1 Mode Select. These bits select the response time for Comparator1. Mode 0 1 2 3 CP1MD1 0 0 1 1 CP1MD0 0 1 0 1 CP1 Response Time* Fastest Response Lowest Power * See Table 7.1 for response time parameters. Rev. 1.5 67 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 7.1. Comparator Electrical Characteristics VDD = 3.0 V, –40 to +85 °C unless otherwise noted. All specifications apply to both Comparator0 and Comparator1 unless otherwise noted. Parameter Conditions Min Typ Max Units Response Time: Mode 0, Vcm* = 1.5 V CP0+ – CP0– = 100 mV 100 ns CP0+ – CP0– = –100 mV 250 ns Response Time: Mode 1, Vcm* = 1.5 V CP0+ – CP0– = 100 mV 175 ns CP0+ – CP0– = –100 mV 500 ns Response Time: Mode 2, Vcm* = 1.5 V CP0+ – CP0– = 100 mV 320 ns CP0+ – CP0– = –100 mV 1100 ns Response Time: Mode 3, Vcm* = 1.5 V CP0+ – CP0– = 100 mV 1050 ns CP0+ – CP0– = –100 mV 5200 ns Common-Mode Rejection Ratio 1.5 4 mV/V 0 1 mV Positive Hysteresis 1 CP0HYP1–0 = 00 Positive Hysteresis 2 CP0HYP1–0 = 01 2 5 10 mV Positive Hysteresis 3 CP0HYP1–0 = 10 7 10 20 mV Positive Hysteresis 4 CP0HYP1–0 = 11 15 20 30 mV Negative Hysteresis 1 CP0HYN1–0 = 00 0 1 mV Negative Hysteresis 2 CP0HYN1–0 = 01 2 5 10 mV Negative Hysteresis 3 CP0HYN1–0 = 10 7 10 20 mV Negative Hysteresis 4 CP0HYN1–0 = 11 15 20 30 mV VDD + 0.25 V Inverting or Non-Inverting Input Voltage Range –0.25 Input Capacitance 3 pF Input Bias Current 0.001 nA Input Offset Voltage –5 +5 mV Power Supply Power Supply Rejection 0.1 mV/V Power-up Time 10 µs Mode 0 7.6 µA Mode 1 3.2 µA Mode 2 1.3 µA Mode 3 0.4 µA Supply Current at DC *Note: Vcm is the common-mode voltage on CP0+ and CP0–. 68 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 8. Voltage Regulator (REG0) C8051F34x devices include a voltage regulator (REG0). When enabled, the REG0 output appears on the VDD pin and can be used to power external devices. REG0 can be enabled/disabled by software using bit REGEN in register REG0CN. See Table 8.1 for REG0 electrical characteristics. Note that the VBUS signal must be connected to the VBUS pin when using the device in a USB network. The VBUS signal should only be connected to the REGIN pin when operating the device as a bus-powered function. REG0 configuration options are shown in Figure 8.1–Figure 8.4. 8.1. Regulator Mode Selection REG0 offers a low power mode intended for use when the device is in suspend mode. In this low power mode, the REG0 output remains as specified; however the REG0 dynamic performance (response time) is degraded. See Table 8.1 for normal and low power mode supply current specifications. The REG0 mode selection is controlled via the REGMOD bit in register REG0CN. 8.2. VBUS Detection When the USB Function Controller is used (see section Section “16. Universal Serial Bus Controller (USB0)” on page 159), the VBUS signal should be connected to the VBUS pin. The VBSTAT bit (register REG0CN) indicates the current logic level of the VBUS signal. If enabled, a VBUS interrupt will be generated when the VBUS signal matches the polarity selected by the VBPOL bit in register REG0CN. The VBUS interrupt is level-sensitive, and has no associated interrupt pending flag. The VBUS interrupt will be active as long as the VBUS signal matches the polarity selected by VBPOL. See Table 8.1 for VBUS input parameters. Important Note: When USB is selected as a reset source, a system reset will be generated when the VBUS signal matches the polarity selected by the VBPOL bit. See Section “11. Reset Sources” on page 100 for details on selecting USB as a reset source Table 8.1. Voltage Regulator Electrical Specifications –40 to +85 °C unless otherwise specified. Parameter Conditions Max Units 5.25 V 3.6 V Output Current2 100 mA VBUS Detection Input Low Voltage 1.0 V Input Voltage Range1 Output Voltage (VDD)2 Typ 2.7 Output Current = 1 to 100 mA VBUS Detection Input High Voltage Bias Current Min 3.0 3.3 3.0 Normal Mode (REGMOD = ‘0’) Low Power Mode (REGMOD = ‘1’) Dropout Voltage (VDO)3 V 65 35 111 61 1 µA mV/mA Notes: 1. Input range specified for regulation. When an external regulator is used, should be tied to VDD. 2. Output current is total regulator output, including any current required by the C8051F34x. 3. The minimum input voltage is 2.70 V or VDD + VDO (max load), whichever is greater. Rev. 1.5 69 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D VBUS VBUS Sense From VBUS REGIN 5 V In Voltage Regulator (REG0) 3 V Out To 3 V Power Net Device Power Net VDD Figure 8.1. REG0 Configuration: USB Bus-Powered From VBUS VBUS VBUS Sense From 5 V Power Net REGIN 5 V In Voltage Regulator (REG0) 3 V Out To 3 V Power Net Device Power Net VDD Figure 8.2. REG0 Configuration: USB Self-Powered 70 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D From VBUS VBUS VBUS Sense REGIN 5 V In Voltage Regulator (REG0) 3 V Out From 3 V Power Net Device Power Net VDD Figure 8.3. REG0 Configuration: USB Self-Powered, Regulator Disabled VBUS VBUS Sense From 5 V Power Net REGIN 5 V In Voltage Regulator (REG0) 3 V Out To 3 V Power Net Device Power Net VDD Figure 8.4. REG0 Configuration: No USB Connection Rev. 1.5 71 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 8.1. REG0CN: Voltage Regulator Control R/W R R/W REGDIS VBSTAT VBPOL Bit7 Bit6 Bit5 R/W R/W R/W R/W R/W Reset Value REGMOD Reserved Reserved Reserved Reserved 00000000 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xC9 Bit7: REGDIS: Voltage Regulator Disable. 0: Voltage Regulator Enabled. 1: Voltage Regulator Disabled. Bit6: VBSTAT: VBUS Signal Status. 0: VBUS signal currently absent (device not attached to USB network). 1: VBUS signal currently present (device attached to USB network). Bit5: VBPOL: VBUS Interrupt Polarity Select. This bit selects the VBUS interrupt polarity. 0: VBUS interrupt active when VBUS is low. 1: VBUS interrupt active when VBUS is high. Bit4: REGMOD: Voltage Regulator Mode Select. This bit selects the Voltage Regulator mode. When REGMOD is set to ‘1’, the voltage regulator operates in low power (suspend) mode. 0: USB0 Voltage Regulator in normal mode. 1: USB0 Voltage Regulator in low power mode. Bits3–0: Reserved. Read = 0000b. Must Write = 0000b. 72 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 9. CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has a superset of all the peripherals included with a standard 8051. Included are four 16-bit counter/timers (see description in Section 21), an enhanced full-duplex UART (see description in Section 18), an Enhanced SPI (see description in Section 20), 256 bytes of internal RAM, 128 byte Special Function Register (SFR) address space (Section 9.2.6), and 25 Port I/O (see description in Section 15). The CIP-51 also includes on-chip debug hardware (see description in Section 23), and interfaces directly with the analog and digital subsystems providing a complete data acquisition or control-system solution in a single integrated circuit. The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals and functions to extend its capability (see Figure 9.1 for a block diagram). The CIP-51 includes the following features: - Fully Compatible with MCS-51 Instruction Set - 0 to 48 MHz Clock Frequency - 256 Bytes of Internal RAM - 25 Port I/O - Extended Interrupt Handler Reset Input Power Management Modes On-chip Debug Logic Program and Data Memory Security D8 D8 ACCUMULATOR STACK POINTER TMP1 TMP2 SRAM ADDRESS REGISTER PSW SRAM (256 X 8) D8 D8 D8 ALU D8 DATA BUS B REGISTER D8 D8 D8 DATA BUS DATA BUS SFR_ADDRESS BUFFER D8 DATA POINTER D8 D8 SFR BUS INTERFACE SFR_CONTROL SFR_WRITE_DATA SFR_READ_DATA DATA BUS PC INCREMENTER PROGRAM COUNTER (PC) PRGM. ADDRESS REG. MEM_ADDRESS D8 MEM_CONTROL A16 MEMORY INTERFACE MEM_WRITE_DATA MEM_READ_DATA PIPELINE RESET D8 CONTROL LOGIC SYSTEM_IRQs CLOCK D8 STOP IDLE POWER CONTROL REGISTER INTERRUPT INTERFACE EMULATION_IRQ D8 Figure 9.1. CIP-51 Block Diagram Rev. 1.5 73 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more than eight system clock cycles. With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that for execution time. Clocks to Execute 1 2 2/4 3 3/5 4 5 4/6 6 8 Number of Instructions 26 50 5 10 7 5 2 1 2 1 Programming and Debugging Support In-system programming of the Flash program memory and communication with on-chip debug support logic is accomplished via the Silicon Labs 2-Wire Development Interface (C2). Note that the re-programmable Flash can also be read and changed a single byte at a time by the application software using the MOVC and MOVX instructions. This feature allows program memory to be used for non-volatile data storage as well as updating program code under software control. The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging without occupying package pins. C2 details can be found in Section “23. C2 Interface” on page 271. The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs provides an integrated development environment (IDE) including editor, debugger, and programmer. The IDE's debugger and programmer interface to the CIP-51 via the C2 interface to provide fast and efficient in-system device programming and debugging. An 8051 assembler, linker and evaluation ‘C’ compiler are included in the Development Kit. Many third party macro assemblers and C compilers are also available, which can be used directly with the IDE. 9.1. Instruction Set The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruction set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51 instructions are the binary and functional equivalent of their MCS-51™ counterparts, including opcodes, addressing modes and effect on PSW flags. However, instruction timing is different than that of the standard 8051. 9.1.1. Instruction and CPU Timing In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based solely on clock cycle timing. All instruction timings are specified in terms of clock cycles. Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock cycles as there are program bytes in the instruction. Conditional branch instructions take two fewer clock cycles to complete when the branch is not taken as opposed to when the branch is taken. Table 9.1 is the CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock cycles for each instruction. 74 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 9.1.2. MOVX Instruction and Program Memory In the CIP-51, the MOVX instruction serves three purposes: accessing on-chip XRAM, accessing off-chip data XRAM (only on C8051F340/1/4/5/8 devices), and accessing on-chip program Flash memory. The Flash access feature provides a mechanism for user software to update program code and use the program memory space for non-volatile data storage (see Section “12. Flash Memory” on page 107). The External Memory Interface (only on C8051F340/1/4/5/8 devices) provides a fast access interface to off-chip data XRAM (or memory-mapped peripherals) via the MOVX instruction. Refer to Section “13. External Data Memory Interface and On-Chip XRAM” on page 114. for details. Table 9.1. CIP-51 Instruction Set Summary Mnemonic ADD A, Rn ADD A, direct ADD A, @Ri ADD A, #data ADDC A, Rn ADDC A, direct ADDC A, @Ri ADDC A, #data SUBB A, Rn SUBB A, direct SUBB A, @Ri SUBB A, #data INC A INC Rn INC direct INC @Ri DEC A DEC Rn DEC direct DEC @Ri INC DPTR MUL AB DIV AB DA A ANL A, Rn ANL A, direct ANL A, @Ri ANL A, #data ANL direct, A ANL direct, #data ORL A, Rn ORL A, direct ORL A, @Ri Description Arithmetic Operations Add register to A Add direct byte to A Add indirect RAM to A Add immediate to A Add register to A with carry Add direct byte to A with carry Add indirect RAM to A with carry Add immediate to A with carry Subtract register from A with borrow Subtract direct byte from A with borrow Subtract indirect RAM from A with borrow Subtract immediate from A with borrow Increment A Increment register Increment direct byte Increment indirect RAM Decrement A Decrement register Decrement direct byte Decrement indirect RAM Increment Data Pointer Multiply A and B Divide A by B Decimal adjust A Logical Operations AND Register to A AND direct byte to A AND indirect RAM to A AND immediate to A AND A to direct byte AND immediate to direct byte OR Register to A OR direct byte to A OR indirect RAM to A Rev. 1.5 Bytes Clock Cycles 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 2 1 1 1 1 1 1 2 2 2 1 2 2 2 1 2 2 2 1 1 2 2 1 1 2 2 1 4 8 1 1 2 1 2 2 3 1 2 1 1 2 2 2 2 3 1 2 2 75 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 9.1. CIP-51 Instruction Set Summary (Continued) Mnemonic ORL A, #data ORL direct, A ORL direct, #data XRL A, Rn XRL A, direct XRL A, @Ri XRL A, #data XRL direct, A XRL direct, #data CLR A CPL A RL A RLC A RR A RRC A SWAP A MOV A, Rn MOV A, direct MOV A, @Ri MOV A, #data MOV Rn, A MOV Rn, direct MOV Rn, #data MOV direct, A MOV direct, Rn MOV direct, direct MOV direct, @Ri MOV direct, #data MOV @Ri, A MOV @Ri, direct MOV @Ri, #data MOV DPTR, #data16 MOVC A, @A+DPTR MOVC A, @A+PC MOVX A, @Ri MOVX @Ri, A MOVX A, @DPTR MOVX @DPTR, A PUSH direct POP direct XCH A, Rn XCH A, direct XCH A, @Ri XCHD A, @Ri 76 Description OR immediate to A OR A to direct byte OR immediate to direct byte Exclusive-OR Register to A Exclusive-OR direct byte to A Exclusive-OR indirect RAM to A Exclusive-OR immediate to A Exclusive-OR A to direct byte Exclusive-OR immediate to direct byte Clear A Complement A Rotate A left Rotate A left through Carry Rotate A right Rotate A right through Carry Swap nibbles of A Data Transfer Move Register to A Move direct byte to A Move indirect RAM to A Move immediate to A Move A to Register Move direct byte to Register Move immediate to Register Move A to direct byte Move Register to direct byte Move direct byte to direct byte Move indirect RAM to direct byte Move immediate to direct byte Move A to indirect RAM Move direct byte to indirect RAM Move immediate to indirect RAM Load DPTR with 16-bit constant Move code byte relative DPTR to A Move code byte relative PC to A Move external data (8-bit address) to A Move A to external data (8-bit address) Move external data (16-bit address) to A Move A to external data (16-bit address) Push direct byte onto stack Pop direct byte from stack Exchange Register with A Exchange direct byte with A Exchange indirect RAM with A Exchange low nibble of indirect RAM with A Rev. 1.5 2 2 3 1 2 1 2 2 3 1 1 1 1 1 1 1 Clock Cycles 2 2 3 1 2 2 2 2 3 1 1 1 1 1 1 1 1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1 1 2 2 2 1 2 2 2 2 3 2 3 2 2 2 3 3 3 3 3 3 3 2 2 1 2 2 2 Bytes C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 9.1. CIP-51 Instruction Set Summary (Continued) Mnemonic CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C, bit ANL C, /bit ORL C, bit ORL C, /bit MOV C, bit MOV bit, C JC rel JNC rel JB bit, rel JNB bit, rel JBC bit, rel ACALL addr11 LCALL addr16 RET RETI AJMP addr11 LJMP addr16 SJMP rel JMP @A+DPTR JZ rel JNZ rel CJNE A, direct, rel CJNE A, #data, rel CJNE Rn, #data, rel CJNE @Ri, #data, rel DJNZ Rn, rel DJNZ direct, rel NOP Description Boolean Manipulation Clear Carry Clear direct bit Set Carry Set direct bit Complement Carry Complement direct bit AND direct bit to Carry AND complement of direct bit to Carry OR direct bit to carry OR complement of direct bit to Carry Move direct bit to Carry Move Carry to direct bit Jump if Carry is set Jump if Carry is not set Jump if direct bit is set Jump if direct bit is not set Jump if direct bit is set and clear bit Program Branching Absolute subroutine call Long subroutine call Return from subroutine Return from interrupt Absolute jump Long jump Short jump (relative address) Jump indirect relative to DPTR Jump if A equals zero Jump if A does not equal zero Compare direct byte to A and jump if not equal Compare immediate to A and jump if not equal Compare immediate to Register and jump if not equal Compare immediate to indirect and jump if not equal Decrement Register and jump if not zero Decrement direct byte and jump if not zero No operation Rev. 1.5 Bytes Clock Cycles 1 2 1 2 1 2 2 2 2 2 2 2 2 2 3 3 3 1 2 1 2 1 2 2 2 2 2 2 2 2/4 2/4 3/5 3/5 3/5 2 3 1 1 2 3 2 1 2 2 3 3 3 3 2 3 1 4 5 6 6 4 5 4 4 2/4 2/4 3/5 3/5 3/5 4/6 2/4 3/5 1 77 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Notes on Registers, Operands and Addressing Modes: Rn - Register R0-R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. rel - 8-bit, signed (two’s complement) offset relative to the first byte of the following instruction. Used by SJMP and all conditional jumps. direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location (0x00-0x7F) or an SFR (0x80-0xFF). #data - 8-bit constant #data16 - 16-bit constant bit - Direct-accessed bit in Data RAM or SFR addr11 - 11-bit destination address used by ACALL and AJMP. The destination must be within the same 2K-byte page of program memory as the first byte of the following instruction. addr16 - 16-bit destination address used by LCALL and LJMP. The destination may be anywhere within the 8K-byte program memory space. There is one unused opcode (0xA5) that performs the same function as NOP. All mnemonics copyrighted © Intel Corporation 1980. 78 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 9.2. Memory Organization The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space but are accessed via different instruction types. The CIP-51 memory organization is shown in Figure 9.2 and Figure 9.3. DATA MEMORY (RAM) INTERNAL DATA ADDRESS SPACE PROGRAM/DATA MEMORY (FLASH) 0xFFFF 0xFC00 0xFF RESERVED 0xFBFF 0x80 0x7F Upper 128 RAM (Indirect Addressing Only) (Direct and Indirect Addressing) FLASH (In-System Programmable in 512 Byte Sectors) 0x30 0x2F 0x20 0x1F 0x00 Bit Addressable Special Function Register's (Direct Addressing Only) Lower 128 RAM (Direct and Indirect Addressing) General Purpose Registers EXTERNAL DATA ADDRESS SPACE 0x0000 0xFFFF Off-Chip XRAM (Available only on devices with EMIF) 0x1000 0x0FFF XRAM - 4096 Bytes (Accessable using MOVX instruction) USB FIFOs 1024 Bytes 0x07FF 0x0400 0x0000 Figure 9.2. On-Chip Memory Map for 64 kB Devices Rev. 1.5 79 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D DATA MEMORY (RAM) INTERNAL DATA ADDRESS SPACE PROGRAM/DATA MEMORY (FLASH) 0x7FFF 0xFF FLASH (In-System Programmable in 512 Byte Sectors) 0x0000 0x80 0x7F Upper 128 RAM (Indirect Addressing Only) (Direct and Indirect Addressing) 0x30 0x2F 0x20 0x1F 0x00 Bit Addressable Special Function Register's (Direct Addressing Only) Lower 128 RAM (Direct and Indirect Addressing) General Purpose Registers EXTERNAL DATA ADDRESS SPACE 0xFFFF Off-Chip XRAM (Available only on devices with EMIF) 0x0800 0x07FF XRAM - 2048 Bytes (Accessable using MOVX instruction) USB FIFOs 1024 Bytes 0x07FF 0x0400 0x0000 Figure 9.3. On-Chip Memory Map for 32 kB Devices 9.2.1. Program Memory The CIP-51 core has a 64k-byte program memory space. The C8051F34x implements 64k or 32k bytes of this program memory space as in-system, re-programmable Flash memory. Note that on the 64k versions of the C8051F34x, addresses above 0xFBFF are reserved. Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX instruction. This feature provides a mechanism for the CIP-51 to update program code and use the program memory space for non-volatile data storage. Refer to Section “12. Flash Memory” on page 107 for further details. 80 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 9.2.2. Data Memory The CIP-51 includes 256 of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or as 128 bit locations accessible with the direct addressing mode. The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the same address space as the Special Function Registers (SFR) but is physically separate from the SFR space. The addressing mode used by an instruction when accessing locations above 0x7F determines whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the upper 128 bytes of data memory. Figure 9.2 illustrates the data memory organization of the CIP-51. 9.2.3. General Purpose Registers The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of general-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1 (PSW.4), select the active register bank (see description of the PSW in SFR Definition 9.4). This allows fast context switching when entering subroutines and interrupt service routines. Indirect addressing modes use registers R0 and R1 as index registers. 9.2.4. Bit Addressable Locations In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from 0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address 0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by the type of instruction used (bit source or destination operands as opposed to a byte source or destination). The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where XX is the byte address and B is the bit position within the byte. For example, the instruction: MOV C, 22h.3 moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag. 9.2.5. Stack A programmer's stack can be located anywhere in the 256-byte data memory. The stack area is designated using the Stack Pointer (SP, 0x81) SFR. The SP will point to the last location used. The next value pushed on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to location 0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the first register (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be initialized to a location in the data memory not being used for data storage. The stack depth can extend up to 256 bytes. Rev. 1.5 81 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 9.2.6. Special Function Registers The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The CIP-51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional SFRs used to configure and access the sub-systems unique to the MCU. This allows the addition of new functionality while retaining compatibility with the MCS-51™ instruction set. Table 9.2 lists the SFRs implemented in the CIP-51 System Controller. The SFR registers are accessed anytime the direct addressing mode is used to access memory locations from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are bit-addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate effect and should be avoided. Refer to the corresponding pages of the datasheet, as indicated in Table 9.3, for a detailed description of each register. Table 9.2. Special Function Register (SFR) Memory Map F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 SPI0CN PCA0L PCA0H PCA0CPL0 PCA0CPH0 PCA0CPL4 PCA0CPH4 B P0MDIN P1MDIN P2MDIN P3MDIN P4MDIN EIP1 ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 PCA0CPL3 PCA0CPH3 ACC XBR0 XBR1 XBR2 IT01CF SMOD1 EIE1 PCA0CN PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 PCA0CPM3 PCA0CPM4 PSW REF0CN SCON1 SBUF1 P0SKIP P1SKIP P2SKIP TMR2CN REG0CN TMR2RLL TMR2RLH TMR2L TMR2H SMB0CN SMB0CF SMB0DAT ADC0GTL ADC0GTH ADC0LTL ADC0LTH IP CLKMUL AMX0N AMX0P ADC0CF ADC0L ADC0H P3 OSCXCN OSCICN OSCICL SBRLL1 SBRLH1 FLSCL IE CLKSEL EMI0CN SBCON1 P4MDOUT P2 SPI0CFG SPI0CKR SPI0DAT P0MDOUT P1MDOUT P2MDOUT SCON0 SBUF0 CPT1CN CPT0CN CPT1MD CPT0MD CPT1MX P1 TMR3CN TMR3RLL TMR3RLH TMR3L TMR3H USB0ADR TCON TMOD TL0 TL1 TH0 TH1 CKCON P0 SP DPL DPH EMI0TC EMI0CF OSCLCN 0(8) 1(9) 2(A) 3(B) 4(C) 5(D) 6(E) (bit addressable) 82 Rev. 1.5 VDM0CN EIP2 RSTSRC EIE2 P3SKIP USB0XCN P4 FLKEY PFE0CN P3MDOUT CPT0MX USB0DAT PSCTL PCON 7(F) C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 9.3. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address Description ACC 0xE0 Accumulator ADC0CF 0xBC ADC0 Configuration ADC0CN 0xE8 ADC0 Control ADC0GTH 0xC4 ADC0 Greater-Than Compare High ADC0GTL 0xC3 ADC0 Greater-Than Compare Low ADC0H 0xBE ADC0 High ADC0L 0xBD ADC0 Low ADC0LTH 0xC6 ADC0 Less-Than Compare Word High ADC0LTL 0xC5 ADC0 Less-Than Compare Word Low AMX0N 0xBA AMUX0 Negative Channel Select AMX0P 0xBB AMUX0 Positive Channel Select B 0xF0 B Register CKCON 0x8E Clock Control CLKMUL 0xB9 Clock Multiplier CLKSEL 0xA9 Clock Select CPT0CN 0x9B Comparator0 Control CPT0MD 0x9D Comparator0 Mode Selection CPT0MX 0x9F Comparator0 MUX Selection CPT1CN 0x9A Comparator1 Control CPT1MD 0x9C Comparator1 Mode Selection CPT1MX 0x9E Comparator1 MUX Selection DPH 0x83 Data Pointer High DPL 0x82 Data Pointer Low EIE1 0xE6 Extended Interrupt Enable 1 EIE2 0xE7 Extended Interrupt Enable 2 EIP1 0xF6 Extended Interrupt Priority 1 EIP2 0xF7 Extended Interrupt Priority 2 EMI0CN 0xAA External Memory Interface Control EMI0CF 0x85 External Memory Interface Configuration EMI0TC 0x84 External Memory Interface Timing FLKEY 0xB7 Flash Lock and Key FLSCL 0xB6 Flash Scale IE 0xA8 Interrupt Enable IP 0xB8 Interrupt Priority IT01CF 0xE4 INT0/INT1 Configuration OSCICL 0xB3 Internal Oscillator Calibration OSCICN 0xB2 Internal Oscillator Control OSCLCN 0x86 Internal Low-Frequency Oscillator Control OSCXCN 0xB1 External Oscillator Control P0 0x80 Port 0 Latch P0MDIN 0xF1 Port 0 Input Mode Configuration P0MDOUT 0xA4 Port 0 Output Mode Configuration P0SKIP 0xD4 Port 0 Skip P1 0x90 Port 1 Latch Rev. 1.5 Page 87 50 51 52 52 50 50 53 53 49 48 88 241 138 140 62 64 63 65 67 66 86 86 93 95 94 95 117 118 123 112 113 91 92 96 133 132 134 137 150 150 151 151 152 83 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 9.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address Description P1MDIN 0xF2 Port 1 Input Mode Configuration P1MDOUT 0xA5 Port 1 Output Mode Configuration P1SKIP 0xD5 Port 1 Skip P2 0xA0 Port 2 Latch P2MDIN 0xF3 Port 2 Input Mode Configuration P2MDOUT 0xA6 Port 2 Output Mode Configuration P2SKIP 0xD6 Port 2 Skip P3 0xB0 Port 3 Latch P3MDIN 0xF4 Port 3 Input Mode Configuration P3MDOUT 0xA7 Port 3 Output Mode Configuration P3SKIP 0xDF Port 3Skip P4 0xC7 Port 4 Latch P4MDIN 0xF5 Port 4 Input Mode Configuration P4MDOUT 0xAE Port 4 Output Mode Configuration PCA0CN 0xD8 PCA Control PCA0CPH0 0xFC PCA Capture 0 High PCA0CPH1 0xEA PCA Capture 1 High PCA0CPH2 0xEC PCA Capture 2 High PCA0CPH3 0xEE PCA Capture 3High PCA0CPH4 0xFE PCA Capture 4 High PCA0CPL0 0xFB PCA Capture 0 Low PCA0CPL1 0xE9 PCA Capture 1 Low PCA0CPL2 0xEB PCA Capture 2 Low PCA0CPL3 0xED PCA Capture 3 Low PCA0CPL4 0xFD PCA Capture 4 Low PCA0CPM0 0xDA PCA Module 0 Mode Register PCA0CPM1 0xDB PCA Module 1 Mode Register PCA0CPM2 0xDC PCA Module 2 Mode Register PCA0CPM3 0xDD PCA Module 3 Mode Register PCA0CPM4 0xDE PCA Module 4 Mode Register PCA0H 0xFA PCA Counter High PCA0L 0xF9 PCA Counter Low PCA0MD 0xD9 PCA Mode PCON 0x87 Power Control PFE0CN 0xAF Prefetch Engine Control PSCTL 0x8F Program Store R/W Control PSW 0xD0 Program Status Word REF0CN 0xD1 Voltage Reference Control REG0CN 0xC9 Voltage Regulator Control RSTSRC 0xEF Reset Source Configuration/Status SBCON1 0xAC UART1 Baud Rate Generator Control SBRLH1 0xB5 UART1 Baud Rate Generator High SBRLL1 0xB4 UART1 Baud Rate Generator Low SBUF1 0xD3 UART1 Data Buffer SCON1 0xD2 UART1 Control 84 Rev. 1.5 Page 152 152 153 153 153 154 154 155 155 155 156 156 157 157 266 270 270 270 270 270 269 269 269 269 269 268 268 268 268 268 269 269 267 98 99 112 87 58 72 105 220 221 221 220 218 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 9.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address Description SBUF0 0x99 UART0 Data Buffer SCON0 0x98 UART0 Control SMB0CF 0xC1 SMBus Configuration SMB0CN 0xC0 SMBus Control SMB0DAT 0xC2 SMBus Data SMOD1 0xE5 UART1 Mode SP 0x81 Stack Pointer SPI0CFG 0xA1 SPI Configuration SPI0CKR 0xA2 SPI Clock Rate Control SPI0CN 0xF8 SPI Control SPI0DAT 0xA3 SPI Data TCON 0x88 Timer/Counter Control TH0 0x8C Timer/Counter 0 High TH1 0x8D Timer/Counter 1 High TL0 0x8A Timer/Counter 0 Low TL1 0x8B Timer/Counter 1 Low TMOD 0x89 Timer/Counter Mode TMR2CN 0xC8 Timer/Counter 2 Control TMR2H 0xCD Timer/Counter 2 High TMR2L 0xCC Timer/Counter 2 Low TMR2RLH 0xCB Timer/Counter 2 Reload High TMR2RLL 0xCA Timer/Counter 2 Reload Low TMR3CN 0x91 Timer/Counter 3Control TMR3H 0x95 Timer/Counter 3 High TMR3L 0x94 Timer/Counter 3Low TMR3RLH 0x93 Timer/Counter 3 Reload High TMR3RLL 0x92 Timer/Counter 3 Reload Low VDD Monitor Control VDM0CN 0xFF USB0ADR 0x96 USB0 Indirect Address Register USB0DAT 0x97 USB0 Data Register USB0XCN 0xD7 USB0 Transceiver Control XBR0 0xE1 Port I/O Crossbar Control 0 XBR1 0xE2 Port I/O Crossbar Control 1 XBR2 0xE3 Port I/O Crossbar Control 2 All Other Addresses Reserved Rev. 1.5 Page 211 210 194 196 198 219 86 229 231 230 231 239 242 242 242 242 240 247 248 248 248 248 253 254 254 254 254 102 163 164 161 148 149 149 85 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 9.2.7. Register Descriptions Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should not be set to logic l. Future product versions may use these bits to implement new features in which case the reset value of the bit will be logic 0, selecting the feature's default state. Detailed descriptions of the remaining SFRs are included in the sections of the datasheet associated with their corresponding system function. SFR Definition 9.1. DPL: Data Pointer Low Byte R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x82 Bits7–0: DPL: Data Pointer Low. The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly addressed memory. SFR Definition 9.2. DPH: Data Pointer High Byte R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x83 Bits7–0: DPH: Data Pointer High. The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly addressed memory. SFR Definition 9.3. SP: Stack Pointer R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 00000111 0x81 Bits7–0: SP: Stack Pointer. The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented before every PUSH operation. The SP register defaults to 0x07 after reset. 86 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 9.4. PSW: Program Status Word R/W R/W R/W R/W R/W R/W CY Bit7 R/W R AC F0 RS1 RS0 Bit6 Bit5 Bit4 Bit3 OV F1 PARITY 00000000 Bit2 Bit1 Bit0 SFR Address: (bit addressable) Reset Value 0xD0 Bit7: CY: Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow (subtraction). It is cleared to logic 0 by all other arithmetic operations. Bit6: AC: Auxiliary Carry Flag This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow from (subtraction) the high order nibble. It is cleared to logic 0 by all other arithmetic operations. Bit5: F0: User Flag 0. This is a bit-addressable, general purpose flag for use under software control. Bits4–3: RS1–RS0: Register Bank Select. These bits select which register bank is used during register accesses. RS1 0 0 1 1 Bit2: Bit1: Bit0: RS0 0 1 0 1 Register Bank 0 1 2 3 Address 0x00 - 0x07 0x08 - 0x0F 0x10 - 0x17 0x18 - 0x1F OV: Overflow Flag. This bit is set to 1 under the following circumstances: • An ADD, ADDC, or SUBB instruction causes a sign-change overflow. • A MUL instruction results in an overflow (result is greater than 255). • A DIV instruction causes a divide-by-zero condition. The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other cases. F1: User Flag 1. This is a bit-addressable, general purpose flag for use under software control. PARITY: Parity Flag. This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum is even. SFR Definition 9.5. ACC: Accumulator R/W R/W R/W R/W R/W R/W R/W R/W Reset Value ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: (bit addressable) 0xE0 Bits7–0: ACC: Accumulator. This register is the accumulator for arithmetic operations. Rev. 1.5 87 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 9.6. B: B Register R/W R/W R/W R/W R/W R/W R/W R/W B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: (bit addressable) Reset Value 0xF0 Bits7–0: B: B Register. This register serves as a second accumulator for certain arithmetic operations. 9.3. Interrupt Handler The CIP-51 includes an extended interrupt system supporting multiple interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and external inputs pins varies according to the specific version of the device. Each interrupt source has one or more associated interrupt-pending flag(s) located in an SFR. When a peripheral or external source meets a valid interrupt condition, the associated interrupt-pending flag is set to logic 1. If interrupts are enabled for the source, an interrupt request is generated when the interrupt-pending flag is set. As soon as execution of the current instruction is complete, the CPU generates an LCALL to a predetermined address to begin execution of an interrupt service routine (ISR). Each ISR must end with an RETI instruction, which returns program execution to the next instruction that would have been executed if the interrupt request had not occurred. If interrupts are not enabled, the interrupt-pending flag is ignored by the hardware and program execution continues as normal. (The interrupt-pending flag is set to logic 1 regardless of the interrupt's enable/disable state.) Each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in an SFR (IE-EIE2). However, interrupts must first be globally enabled by setting the EA bit (IE.7) to logic 1 before the individual interrupt enables are recognized. Setting the EA bit to logic 0 disables all interrupt sources regardless of the individual interrupt-enable settings. Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR. However, most are not cleared by the hardware and must be cleared by software before returning from the ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI) instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after the completion of the next instruction. 9.3.1. MCU Interrupt Sources and Vectors The MCU supports multiple interrupt sources. Software can simulate an interrupt by setting any interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated and the CPU will vector to the ISR address associated with the interrupt-pending flag. MCU interrupt sources, associated vector addresses, priority order and control bits are summarized in Table 9.4 on page 90. Refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). 9.3.2. External Interrupts The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level sensitive. The IN0PL (INT0 Polarity) and IN1PL (INT1 Polarity) bits in the IT01CF register select active high or active low; the IT0 and IT1 bits in TCON (Section “21.1. Timer 0 and Timer 1” on page 235) select level or edge sensitive. The following table lists the possible configurations. 88 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D IT0 1 1 0 0 IN0PL 0 1 0 1 INT0 Interrupt Active low, edge sensitive Active high, edge sensitive Active low, level sensitive Active high, level sensitive IT1 1 1 0 0 IN1PL 0 1 0 1 INT1 Interrupt Active low, edge sensitive Active high, edge sensitive Active low, level sensitive Active high, level sensitive INT0 and INT1 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 9.13). Note that INT0 and INT0 Port pin assignments are independent of any Crossbar assignments. INT0 and INT1 will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin via the Crossbar. To assign a Port pin only to INT0 and/or INT1, configure the Crossbar to skip the selected pin(s). This is accomplished by setting the associated bit in register XBR0 (see Section “15.1. Priority Crossbar Decoder” on page 144 for complete details on configuring the Crossbar). In the typical configuration, the external interrupt pin should be skipped in the crossbar and configured as open-drain with the pin latch set to '1'. IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the INT0 and INT1 external interrupts, respectively. If an INT0 or INT1 external interrupt is configured as edge-sensitive, the corresponding interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inactive. The external interrupt source must hold the input active until the interrupt request is recognized. It must then deactivate the interrupt request before execution of the ISR completes or another interrupt request will be generated. 9.3.3. Interrupt Priorities Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP or EIP2) used to configure its priority level. Low priority is the default. If two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is used to arbitrate, given in Table 9.4. 9.3.4. Interrupt Latency Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 6 system clock cycles: 1 clock cycle to detect the interrupt and 5 clock cycles to complete the LCALL to the ISR. If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL is made to service the pending interrupt. Therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is performing an RETI instruction followed by a DIV as the next instruction. In this case, the response time is 20 system clock cycles: 1 clock cycle to detect the interrupt, 6 clock cycles to execute the RETI, 8 clock cycles to complete the DIV instruction and 5 clock cycles to execute the LCALL to the ISR. If the CPU is executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the current ISR completes, including the RETI and following instruction. Note that the CPU is stalled during Flash write/erase operations and USB FIFO MOVX accesses (see Section “13.2. Accessing USB FIFO Space” on page 115). Interrupt service latency will be increased for interrupts occurring while the CPU is stalled. The latency for these situations will be determined by the standard interrupt service procedure (as described above) and the amount of time the CPU is stalled. Rev. 1.5 89 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Bit addressable? Cleared by HW? Table 9.4. Interrupt Summary Enable Flag N/A N/A Always Enabled IE0 (TCON.1) Y Y EX0 (IE.0) PX0 (IP.0) 1 TF0 (TCON.5) Y Y ET0 (IE.1) PT0 (IP.1) 0x0013 2 IE1 (TCON.3) Y Y EX1 (IE.2) PX1 (IP.2) 0x001B 3 Y Y ET1 (IE.3) PT1 (IP.3) UART0 0x0023 4 Y N ES0 (IE.4) PS0 (IP.4) Timer 2 Overflow 0x002B 5 Y N ET2 (IE.5) PT2 (IP.5) SPI0 0x0033 6 TF1 (TCON.7) RI0 (SCON0.0) TI0 (SCON0.1) TF2H (TMR2CN.7) TF2L (TMR2CN.6) SPIF (SPI0CN.7) WCOL (SPI0CN.6) MODF (SPI0CN.5) RXOVRN (SPI0CN.4) Y N ESPI0 (IE.6) SMB0 0x003B 7 SI (SMB0CN.0) Y USB0 0x0043 8 Special N 0x004B 9 AD0WINT (ADC0CN.3) Y 0x0053 10 AD0INT (ADC0CN.5) Y 0x005B 11 Comparator0 0x0063 12 Comparator1 0x006B 13 Timer 3 Overflow 0x0073 14 VBUS Level 0x007B 15 N/A UART1 0x0083 16 RI1 (SCON1.0) TI1 (SCON1.1) Interrupt Source Interrupt Vector Reset 0x0000 Top 0x0003 0 0x000B External Interrupt 0 (INT0) Timer 0 Overflow External Interrupt 1 (INT1) Timer 1 Overflow ADC0 Window Compare ADC0 Conversion Complete Programmable Counter Array Priority Pending Flag Order None CF (PCA0CN.7) CCFn (PCA0CN.n) CP0FIF (CPT0CN.4) CP0RIF (CPT0CN.5) CP1FIF (CPT1CN.4) CP1RIF (CPT1CN.5) TF3H (TMR3CN.7) TF3L (TMR3CN.6) Y N N N N/A N ESMB0 (EIE1.0) EUSB0 N (EIE1.1) EWADC0 N (EIE1.2) EADC0 N (EIE1.3) EPCA0 N (EIE1.4) ECP0 N (EIE1.5) ECP1 N (EIE1.6) ET3 N (EIE1.7) EVBUS N/A (EIE2.0) ES1 N (EIE2.1) N Priority Control Always Highest PSPI0 (IP.6) PSMB0 (EIP1.0) PUSB0 (EIP1.1) PWADC0 (EIP1.2) PADC0 (EIP1.3) PPCA0 (EIP1.4) PCP0 (EIP1.5) PCP1 (EIP1.6) PT3 (EIP1.7) PVBUS (EIP2.0) PS1 (EIP2.1) 9.3.5. Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). 90 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 9.7. IE: Interrupt Enable R/W R/W R/W R/W R/W R/W R/W R/W EA ESPI0 ET2 ES0 ET1 EX1 ET0 EX0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: (bit addressable) Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: Reset Value 0xA8 EA: Enable All Interrupts. This bit globally enables/disables all interrupts. It overrides the individual interrupt mask settings. 0: Disable all interrupt sources. 1: Enable each interrupt according to its individual mask setting. ESPI0: Enable Serial Peripheral Interface (SPI0) Interrupt. This bit sets the masking of the SPI0 interrupts. 0: Disable all SPI0 interrupts. 1: Enable interrupt requests generated by SPI0. ET2: Enable Timer 2 Interrupt. This bit sets the masking of the Timer 2 interrupt. 0: Disable Timer 2 interrupt. 1: Enable interrupt requests generated by the TF2L or TF2H flags. ES0: Enable UART0 Interrupt. This bit sets the masking of the UART0 interrupt. 0: Disable UART0 interrupt. 1: Enable UART0 interrupt. ET1: Enable Timer 1 Interrupt. This bit sets the masking of the Timer 1 interrupt. 0: Disable all Timer 1 interrupt. 1: Enable interrupt requests generated by the TF1 flag. EX1: Enable External Interrupt 1. This bit sets the masking of External Interrupt 1. 0: Disable external interrupt 1. 1: Enable interrupt requests generated by the INT1 input. ET0: Enable Timer 0 Interrupt. This bit sets the masking of the Timer 0 interrupt. 0: Disable all Timer 0 interrupt. 1: Enable interrupt requests generated by the TF0 flag. EX0: Enable External Interrupt 0. This bit sets the masking of External Interrupt 0. 0: Disable external interrupt 0. 1: Enable interrupt requests generated by the INT0 input. Rev. 1.5 91 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 9.8. IP: Interrupt Priority R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - PSPI0 PT2 PS0 PT1 PX1 PT0 PX0 10000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: (bit addressable) Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: 92 UNUSED. Read = 1, Write = don't care. PSPI0: Serial Peripheral Interface (SPI0) Interrupt Priority Control. This bit sets the priority of the SPI0 interrupt. 0: SPI0 interrupt set to low priority level. 1: SPI0 interrupt set to high priority level. PT2: Timer 2 Interrupt Priority Control. This bit sets the priority of the Timer 2 interrupt. 0: Timer 2 interrupt set to low priority level. 1: Timer 2 interrupts set to high priority level. PS0: UART0 Interrupt Priority Control. This bit sets the priority of the UART0 interrupt. 0: UART0 interrupt set to low priority level. 1: UART0 interrupts set to high priority level. PT1: Timer 1 Interrupt Priority Control. This bit sets the priority of the Timer 1 interrupt. 0: Timer 1 interrupt set to low priority level. 1: Timer 1 interrupts set to high priority level. PX1: External Interrupt 1 Priority Control. This bit sets the priority of the External Interrupt 1 interrupt. 0: External Interrupt 1 set to low priority level. 1: External Interrupt 1 set to high priority level. PT0: Timer 0 Interrupt Priority Control. This bit sets the priority of the Timer 0 interrupt. 0: Timer 0 interrupt set to low priority level. 1: Timer 0 interrupt set to high priority level. PX0: External Interrupt 0 Priority Control. This bit sets the priority of the External Interrupt 0 interrupt. 0: External Interrupt 0 set to low priority level. 1: External Interrupt 0 set to high priority level. Rev. 1.5 0xB8 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 9.9. EIE1: Extended Interrupt Enable 1 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value ET3 ECP1 ECP0 EPCA0 EADC0 EWADC0 EUSB0 ESMB0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xE6 Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: ET3: Enable Timer 3 Interrupt. This bit sets the masking of the Timer 3 interrupt. 0: Disable Timer 3 interrupts. 1: Enable interrupt requests generated by the TF3L or TF3H flags. ECP1: Enable Comparator1 (CP1) Interrupt. This bit sets the masking of the CP1 interrupt. 0: Disable CP1 interrupts. 1: Enable interrupt requests generated by the CP1RIF or CP1FIF flags. ECP0: Enable Comparator0 (CP0) Interrupt. This bit sets the masking of the CP0 interrupt. 0: Disable CP0 interrupts. 1: Enable interrupt requests generated by the CP0RIF or CP0FIF flags. EPCA0: Enable Programmable Counter Array (PCA0) Interrupt. This bit sets the masking of the PCA0 interrupts. 0: Disable all PCA0 interrupts. 1: Enable interrupt requests generated by PCA0. EADC0: Enable ADC0 Conversion Complete Interrupt. This bit sets the masking of the ADC0 Conversion Complete interrupt. 0: Disable ADC0 Conversion Complete interrupt. 1: Enable interrupt requests generated by the AD0INT flag. EWADC0: Enable Window Comparison ADC0 Interrupt. This bit sets the masking of ADC0 Window Comparison interrupt. 0: Disable ADC0 Window Comparison interrupt. 1: Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT). EUSB0: Enable USB0 Interrupt. This bit sets the masking of the USB0 interrupt. 0: Disable all USB0 interrupts. 1: Enable interrupt requests generated by USB0. ESMB0: Enable SMBus (SMB0) Interrupt. This bit sets the masking of the SMB0 interrupt. 0: Disable all SMB0 interrupts. 1: Enable interrupt requests generated by SMB0. Rev. 1.5 93 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 9.10. EIP1: Extended Interrupt Priority 1 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value PT3 PCP1 PCP0 PPCA0 PADC0 PWADC0 PUSB0 PSMB0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xF6 Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: 94 PT3: Timer 3 Interrupt Priority Control. This bit sets the priority of the Timer 3 interrupt. 0: Timer 3 interrupts set to low priority level. 1: Timer 3 interrupts set to high priority level. PCP1: Comparator1 (CP1) Interrupt Priority Control. This bit sets the priority of the CP1 interrupt. 0: CP1 interrupt set to low priority level. 1: CP1 interrupt set to high priority level. PCP0: Comparator0 (CP0) Interrupt Priority Control. This bit sets the priority of the CP0 interrupt. 0: CP0 interrupt set to low priority level. 1: CP0 interrupt set to high priority level. PPCA0: Programmable Counter Array (PCA0) Interrupt Priority Control. This bit sets the priority of the PCA0 interrupt. 0: PCA0 interrupt set to low priority level. 1: PCA0 interrupt set to high priority level. PADC0 ADC0 Conversion Complete Interrupt Priority Control. This bit sets the priority of the ADC0 Conversion Complete interrupt. 0: ADC0 Conversion Complete interrupt set to low priority level. 1: ADC0 Conversion Complete interrupt set to high priority level. PWADC0: ADC0 Window Comparator Interrupt Priority Control. This bit sets the priority of the ADC0 Window interrupt. 0: ADC0 Window interrupt set to low priority level. 1: ADC0 Window interrupt set to high priority level. PUSB0: USB0 Interrupt Priority Control. This bit sets the priority of the USB0 interrupt. 0: USB0 interrupt set to low priority level. 1: USB0 interrupt set to high priority level. PSMB0: SMBus (SMB0) Interrupt Priority Control. This bit sets the priority of the SMB0 interrupt. 0: SMB0 interrupt set to low priority level. 1: SMB0 interrupt set to high priority level. Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 9.11. EIE2: Extended Interrupt Enable 2 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - - - - - - ES1 EVBUS 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xE7 Bits7–2: UNUSED. Read = 000000b. Write = don’t care. Bit1: ES1: Enable UART1 Interrupt. This bit sets the masking of the UART1 interrupt. 0: Disable UART1 interrupt. 1: Enable UART1 interrupt. Bit0: EVBUS: Enable VBUS Level Interrupt. This bit sets the masking of the VBUS interrupt. 0: Disable all VBUS interrupts. 1: Enable interrupt requests generated by VBUS level sense. SFR Definition 9.12. EIP2: Extended Interrupt Priority 2 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - - - - - - PS1 PVBUS 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xF7 Bits7–2: UNUSED. Read = 000000b. Write = don’t care. Bit1: PS1: UART1 Interrupt Priority Control. This bit sets the priority of the UART1 interrupt. 0: UART1 interrupt set to low priority level. 1: UART1 interrupts set to high priority level. Bit0: PVBUS: VBUS Level Interrupt Priority Control. This bit sets the priority of the VBUS interrupt. 0: VBUS interrupt set to low priority level. 1: VBUS interrupt set to high priority level. Rev. 1.5 95 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 9.13. IT01CF: INT0/INT1 Configuration R/W R/W R/W R/W R/W R/W R/W R/W Reset Value IN1PL IN1SL2 IN1SL1 IN1SL0 IN0PL IN0SL2 IN0SL1 IN0SL0 00000001 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xE4 Note: Refer to SFR Definition 21.1 for INT0/1 edge- or level-sensitive interrupt selection. Bit7: IN1PL: INT1 Polarity 0: INT1 input is active low. 1: INT1 input is active high. Bits6–4: IN1SL2–0: INT1 Port Pin Selection Bits These bits select which Port pin is assigned to INT1. Note that this pin assignment is independent of the Crossbar; INT1 will monitor the assigned Port pin without disturbing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar will not assign the Port pin to a peripheral if it is configured to skip the selected pin (accomplished by setting to ‘1’ the corresponding bit in register P0SKIP). IN1SL2–0 000 001 010 011 100 101 110 111 INT1 Port Pin P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 IN0PL: INT0 Polarity 0: INT0 interrupt is active low. 1: INT0 interrupt is active high. Bits2–0: INT0SL2–0: INT0 Port Pin Selection Bits These bits select which Port pin is assigned to INT0. Note that this pin assignment is independent of the Crossbar. INT0 will monitor the assigned Port pin without disturbing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar will not assign the Port pin to a peripheral if it is configured to skip the selected pin (accomplished by setting to ‘1’ the corresponding bit in register P0SKIP). Bit3: IN0SL2–0 000 001 010 011 100 101 110 111 96 INT0 Port Pin P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 9.4. Power Management Modes The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU while leaving the peripherals and clocks active. In Stop mode, the CPU is halted, all interrupts, are inactive, and the internal oscillator is stopped (analog peripherals remain in their selected states; the external oscillator is not affected). Since clocks are running in Idle mode, power consumption is dependent upon the system clock frequency and the number of peripherals left in active mode before entering Idle. Stop mode consumes the least power. Figure 1.15 describes the Power Control Register (PCON) used to control the CIP-51's power management modes. Although the CIP-51 has Idle and Stop modes built in (as with any standard 8051 architecture), power management of the entire MCU is better accomplished through system clock and individual peripheral management. Each analog peripheral can be disabled when not in use and placed in low power mode. Digital peripherals, such as timers or serial buses, draw little power when they are not in use. Turning off the oscillators lowers power consumption considerably; however a reset is required to restart the MCU. The internal oscillator can be placed in Suspend mode (see Section “14. Oscillators” on page 131). In Suspend mode, the internal oscillator is stopped until a non-idle USB event is detected, or the VBUS input signal matches the polarity selected by the VBPOL bit in register REG0CN (SFR Definition 8.1). 9.4.1. Idle Mode Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon as the instruction that sets the bit completes execution. All internal registers and memory maintain their original data. All analog and digital peripherals can remain active during Idle mode. Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume operation. The pending interrupt will be serviced and the next instruction to be executed after the return from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit. If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence and begins program execution at address 0x0000. If enabled, the Watchdog Timer (WDT) will eventually cause an internal watchdog reset and thereby terminate the Idle mode. This feature protects the system from an unintended permanent shutdown in the event of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by software prior to entering the Idle mode if the WDT was initially configured to allow this operation. This provides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefinitely, waiting for an external stimulus to wake up the system. Refer to Section “11.6. PCA Watchdog Timer Reset” on page 103 for more information on the use and configuration of the WDT. 9.4.2. Stop Mode Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruction that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital peripherals are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral (including the external oscillator circuit) may be shut down individually prior to entering Stop Mode. Stop mode can only be terminated by an internal or external reset. On reset, the CIP-51 performs the normal reset sequence and begins program execution at address 0x0000. If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode. The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the MCD timeout of 100 µsec. Rev. 1.5 97 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 9.14. PCON: Power Control R/W R/W R/W R/W R/W R/W R/W R/W Reset Value GF5 GF4 GF3 GF2 GF1 GF0 STOP IDLE 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x87 Bits7–2: GF5–GF0: General Purpose Flags 5–0. These are general purpose flags for use under software control. Bit1: STOP: Stop Mode Select. Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0. 1: CPU goes into Stop mode (internal oscillator stopped). Bit0: IDLE: Idle Mode Select. Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0. 1: CPU goes into Idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, Serial Ports, and Analog Peripherals are still active.) 98 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 10. Prefetch Engine The 48 MHz versions of the C8051F34x family of devices incorporate a 2-byte prefetch engine. Because the access time of the FLASH memory is 40 ns, and the minimum instruction time is roughly 20 ns, the prefetch engine is necessary for full-speed code execution. Instructions are read from FLASH memory two bytes at a time by the prefetch engine, and given to the CIP-51 processor core to execute. When running linear code (code without any jumps or branches), the prefetch engine allows instructions to be executed at full speed. When a code branch occurs, the processor may be stalled for up to two clock cycles while the next set of code bytes is retrieved from FLASH memory. The FLRT bit (FLSCL.4) determines how many clock cycles are used to read each set of two code bytes from FLASH. When operating from a system clock of 25 MHz or less, the FLRT bit should be set to ‘0’ so that the prefetch engine takes only one clock cycle for each read. When operating with a system clock of greater than 25 MHz (up to 48 MHz), the prefetch engine must be enabled by setting the PFEN bit to '1', and the FLRT bit should be set to '1' so that each prefetch code read lasts for two clock cycles. SFR Definition 10.1. PFE0CN: Prefetch Engine Control R R R/W R R R R PFEN Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 R/W Reset Value FLBWE 00100000 Bit0 SFR Address: 0xAF Bits 7–6: Unused. Read = 00b; Write = Don’t Care Bit 5: PFEN: Prefetch Enable. This bit enables the prefetch engine. 0: Prefetch engine is disabled. 1: Prefetch engine is enabled. Bits 4–1: Unused. Read = 0000b; Write = Don’t Care Bit 0: FLBWE: FLASH Block Write Enable. This bit allows block writes to FLASH memory from software. 0: Each byte of a software FLASH write is written individually. 1: FLASH bytes are written in groups of two. Rev. 1.5 99 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 11. Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: • • • • CIP-51 halts program execution Special Function Registers (SFRs) are initialized to their defined reset values External Port pins are forced to a known state Interrupts and timers are disabled. All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal data memory are unaffected during a reset; any previously stored data is preserved. However, since the stack pointer SFR is reset, the stack is effectively lost even though the data on the stack is not altered. The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pull-ups are enabled during and after the reset. For VDD Monitor and Power-On Resets, the RST pin is driven low until the device exits the reset state. On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the internal oscillator. Refer to Section “14. Oscillators” on page 131 for information on selecting and configuring the system clock source. The Watchdog Timer is enabled with the system clock divided by 12 as its clock source (Section “22.3. Watchdog Timer Mode” on page 264 details the use of the Watchdog Timer). Program execution begins at location 0x0000. VDD Supply Monitor + - Reset Funnel PCA WDT Software Reset (SWRSF) Errant FLASH Operation MCD Enable System Clock WDT Enable EN Internal LF Oscillator External Oscillator Drive RST CIP-51 Microcontroller Core Enable EN XTAL2 (wired-OR) C0RSEF Missing Clock Detector (oneshot) XTAL1 '0' + - Px.x Clock Multiplier Power On Reset Comparator 0 Px.x Internal HF Oscillator Enable USB Controller VBUS Transition System Reset Clock Select Extended Interrupt Handler Figure 11.1. Reset Sources Rev. 1.3 100 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 11.1. Power-On Reset During power-up, the device is held in a reset state and the RST pin is driven low until VDD settles above VRST. A Power-On Reset delay (TPORDelay) occurs before the device is released from reset; this delay is typically less than 0.3 ms. Figure 11.2. plots the power-on and VDD monitor reset timing. On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other resets). Since all resets cause program execution to begin at the same location (0x0000) software can read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data memory should be assumed to be undefined after a power-on reset. The VDD monitor is enabled following a power-on reset. volts Software can force a power-on reset by writing ‘1’ to the PINRSF bit in register RSTSRC. VDD 2.70 2.4 VRST VD D 2.0 1.0 t Logic HIGH RST TPORDelay Logic LOW VDD Monitor Reset Power-On Reset Figure 11.2. Power-On and VDD Monitor Reset Timing 101 Rev. 1.3 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 11.2. Power-Fail Reset / VDD Monitor When a power-down transition or power irregularity causes VDD to drop below VRST, the power supply monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 11.2). When VDD returns to a level above VRST, the CIP-51 will be released from the reset state. Note that even though internal data memory contents are not altered by the power-fail reset, it is impossible to determine if VDD dropped below the level required for data retention. If the PORSF flag reads ‘1’, the data may no longer be valid. The VDD monitor is enabled after power-on resets; however its defined state (enabled/disabled) is not altered by any other reset source. For example, if the VDD monitor is enabled and a software reset is performed, the VDD monitor will still be enabled after the reset. It is strongly recommended that the VDD monitor be left enabled at all times for any system that contains code to write to Flash memory. Important Note: The VDD monitor must be enabled before it is selected as a reset source. Selecting the VDD monitor as a reset source before it is enabled and stabilized may cause a system reset. In applications where this reset is undesirable, a delay can be implemented between enabling the VDD monitor and selecting it as a reset source. The procedure for configuring the VDD monitor as a reset source is shown below: Step 1. Enable the VDD monitor (VDM0CN.7 = ‘1’). Step 2. If desired, wait for the VDD monitor to stabilize (see Table 11.1 for the VDD Monitor turn-on time). Step 3. Select the VDD monitor as a reset source (RSTSRC.1 = ‘1’). See Figure 11.2 for VDD monitor timing. See Table 11.1 for complete electrical characteristics of the VDD monitor. SFR Definition 11.1. VDM0CN: VDD Monitor Control R/W VDMEN Bit7 R R R R R R R VDDSTAT Reserved Reserved Reserved Reserved Reserved Reserved Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset Value Variable SFR Address: 0xFF Bit7: VDMEN: VDD Monitor Enable. This bit turns the VDD monitor circuit on/off. The VDD Monitor cannot generate system resets until it is also selected as a reset source in register RSTSRC (SFR Definition 11.2). The VDD Monitor must be allowed to stabilize before it is selected as a reset source. Selecting the VDD monitor as a reset source before it has stabilized will generate a system reset. See Table 11.1 for the minimum VDD Monitor turn-on time. The VDD Monitor is enabled following all POR resets. 0: VDD Monitor Disabled. 1: VDD Monitor Enabled. Bit6: VDDSTAT: VDD Status. This bit indicates the current power supply status (VDD Monitor output). 0: VDD is at or below the VDD monitor threshold. 1: VDD is above the VDD monitor threshold. Bits5–0: Reserved. Read = Variable. Write = don’t care. Rev. 1.3 102 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 11.3. External Reset The external RST pin provides a means for external circuitry to force the device into a reset state. Asserting an active-low signal on the RST pin generates a reset; an external pull-up and/or decoupling of the RST pin may be necessary to avoid erroneous noise-induced resets. See Table 11.1 for complete RST pin specifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset. 11.4. Missing Clock Detector Reset The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If more than 100 µs pass between rising edges on the system clock, the one-shot will time out and generate a reset. After a MCD reset, the MCDRSF flag (RSTSRC.2) will read ‘1’, signifying the MCD as the reset source; otherwise, this bit reads ‘0’. Writing a ‘1’ to the MCDRSF bit enables the Missing Clock Detector; writing a ‘0’ disables it. The state of the RST pin is unaffected by this reset. 11.5. Comparator0 Reset Comparator0 can be configured as a reset source by writing a ‘1’ to the C0RSEF flag (RSTSRC.5). Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-inverting input voltage (on CP0+) is less than the inverting input voltage (on CP0-), a system reset is generated. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read ‘1’ signifying Comparator0 as the reset source; otherwise, this bit reads ‘0’. The state of the RST pin is unaffected by this reset. 11.6. PCA Watchdog Timer Reset The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be used to prevent software from running out of control during a system malfunction. The PCA WDT function can be enabled or disabled by software as described in Section “22.3. Watchdog Timer Mode” on page 264; the WDT is enabled and clocked by SYSCLK / 12 following any reset. If a system malfunction prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is set to ‘1’. The state of the RST pin is unaffected by this reset. 11.7. Flash Error Reset If a Flash read/write/erase or program read targets an illegal address, a system reset is generated. This may occur due to any of the following: • • • • • A Flash write or erase is attempted above user code space. This occurs when PSWE is set to “1”, and a MOVX write operation is attempted above address 0x7FFF (32 kB Flash devices) or 0xFBFF (64 kB Flash devices). A Flash read is attempted above user code space. This occurs when a MOVC operation is attempted above address 0x7FFF (32 kB Flash devices) or 0xFBFF (64 kB Flash devices). A Program read is attempted above user code space. This occurs when user code attempts to branch to an address above 0x7FFF (32 kB Flash devices) or 0xFBFF (64 kB Flash devices). A Flash read, write or erase attempt is restricted due to a Flash security setting (see Section “12.3. Security Options” on page 109). A Flash Write or Erase is attempted when the VDD monitor is not enabled. The FERROR bit (RSTSRC.6) is set following a Flash error reset. The state of the RST pin is unaffected by this reset. 103 Rev. 1.3 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 11.8. Software Reset Software may force a reset by writing a ‘1’ to the SWRSF bit (RSTSRC.4). The SWRSF bit will read ‘1’ following a software forced reset. The state of the RST pin is unaffected by this reset. 11.9. USB Reset Writing ‘1’ to the USBRSF bit in register RSTSRC selects USB0 as a reset source. With USB0 selected as a reset source, a system reset will be generated when either of the following occur: 1. RESET signaling is detected on the USB network. The USB Function Controller (USB0) must be enabled for RESET signaling to be detected. See Section “16. Universal Serial Bus Controller (USB0)” on page 159 for information on the USB Function Controller. 2. The voltage on the VBUS pin matches the polarity selected by the VBPOL bit in register REG0CN. See Section “8. Voltage Regulator (REG0)” on page 69 for details on the VBUS detection circuit. The USBRSF bit will read ‘1’ following a USB reset. The state of the RST pin is unaffected by this reset. Rev. 1.3 104 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 11.2. RSTSRC: Reset Source R/W R R/W USBRSF FERROR C0RSEF Bit7 Bit6 Bit5 R/W SWRSF Bit4 R R/W WDTRSF MCDRSF Bit3 Bit2 R/W R Reset Value PORSF PINRSF Variable Bit1 Bit0 SFR Address: 0xEF Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: USBRSF: USB Reset Flag 0: Read: Last reset was not a USB reset; Write: USB resets disabled. 1: Read: Last reset was a USB reset; Write: USB resets enabled. FERROR: Flash Error Indicator. 0: Source of last reset was not a Flash read/write/erase error. 1: Source of last reset was a Flash read/write/erase error. C0RSEF: Comparator0 Reset Enable and Flag. 0: Read: Source of last reset was not Comparator0; Write: Comparator0 is not a reset source. 1: Read: Source of last reset was Comparator0; Write: Comparator0 is a reset source (active-low). SWRSF: Software Reset Force and Flag. 0: Read: Source of last reset was not a write to the SWRSF bit; Write: No Effect. 1: Read: Source of last was a write to the SWRSF bit; Write: Forces a system reset. WDTRSF: Watchdog Timer Reset Flag. 0: Source of last reset was not a WDT timeout. 1: Source of last reset was a WDT timeout. MCDRSF: Missing Clock Detector Flag. 0: Read: Source of last reset was not a Missing Clock Detector timeout; Write: Missing Clock Detector disabled. 1: Read: Source of last reset was a Missing Clock Detector timeout; Write: Missing Clock Detector enabled; triggers a reset if a missing clock condition is detected. PORSF: Power-On / VDD Monitor Reset Flag. This bit is set anytime a power-on reset occurs. Writing this bit selects/deselects the VDD monitor as a reset source. Note: writing ‘1’ to this bit before the VDD monitor is enabled and stabilized can cause a system reset. See register VDM0CN (SFR Definition 11.1). 0: Read: Last reset was not a power-on or VDD monitor reset; Write: VDD monitor is not a reset source. 1: Read: Last reset was a power-on or VDD monitor reset; all other reset flags indeterminate; Write: VDD monitor is a reset source. PINRSF: HW Pin Reset Flag. 0: Source of last reset was not RST pin. 1: Source of last reset was RST pin. Note: For bits that act as both reset source enables (on a write) and reset indicator flags (on a read), read-modify-write instructions read and modify the source enable only. This applies to bits: USBRSF, C0RSEF, SWRSF, MCDRSF, PORSF. 105 Rev. 1.3 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 11.1. Reset Electrical Characteristics –40 to +85 °C unless otherwise specified. Parameter RST Output Low Voltage Conditions Min Typ IOL = 8.5 mA, VDD = 2.7 to 3.6 V Units 0.6 V 0.7 x VDD RST Input High Voltage V 0.3 x VDD RST Input Low Voltage RST Input Pull-Up Current Max RST = 0.0 V VDD POR Threshold (VRST) 25 40 µA 2.40 2.55 2.70 V 220 500 µs Missing Clock Detector Timeout Time from last system clock rising edge to reset initiation 100 Reset Time Delay Delay between release of any reset source and code execution at location 0x0000 5.0 µs Minimum RST Low Time to Generate a System Reset 15 µs VDD Monitor Turn-on Time 100 µs VDD Monitor Supply Current 20 Rev. 1.3 50 µA 106 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 12. Flash Memory On-chip, re-programmable Flash memory is included for program code and non-volatile data storage. The Flash memory can be programmed in-system through the C2 interface or by software using the MOVX instruction. Once cleared to logic 0, a Flash bit must be erased to set it back to logic 1. Flash bytes would typically be erased (set to 0xFF) before being reprogrammed. The write and erase operations are automatically timed by hardware for proper execution; data polling to determine the end of the write/erase operation is not required. Code execution is stalled during a Flash write/erase operation. Refer to Table 12.1 for complete Flash memory electrical characteristics. 12.1. Programming The Flash Memory The simplest means of programming the Flash memory is through the C2 interface using programming tools provided by Silicon Labs or a third party vendor. This is the only means for programming a non-initialized device. For details on the C2 commands to program Flash memory, see Section “23. C2 Interface” on page 271. To ensure the integrity of Flash contents, it is strongly recommended that the VDD monitor be left enabled in any system which writes or erases Flash memory from code. It is also crucial to ensure that the FLRT bit in register FLSCL be set to '1' if a clock speed higher than 25 MHz is being used for the device. 12.1.1. Flash Lock and Key Functions Flash writes and erases by user software are protected with a lock and key function. The Flash Lock and Key Register (FLKEY) must be written with the correct key codes, in sequence, before Flash operations may be performed. The key codes are: 0xA5, 0xF1. The timing does not matter, but the codes must be written in order. If the key codes are written out of order, or the wrong codes are written, Flash writes and erases will be disabled until the next system reset. Flash writes and erases will also be disabled if a Flash write or erase is attempted before the key codes have been written properly. The Flash lock resets after each write or erase; the key codes must be written again before a following Flash operation can be performed. The FLKEY register is detailed in SFR Definition 12.2. 12.1.2. Flash Erase Procedure The Flash memory can be programmed by software using the MOVX write instruction with the address and data byte to be programmed provided as normal operands. Before writing to Flash memory using MOVX, Flash write operations must be enabled by: (1) Writing the Flash key codes in sequence to the Flash Lock register (FLKEY); and (2) Setting the PSWE Program Store Write Enable bit (PSCTL.0) to logic 1 (this directs the MOVX writes to target Flash memory). The PSWE bit remains set until cleared by software. A write to Flash memory can clear bits to logic 0 but cannot set them; only an erase operation can set bits to logic 1 in Flash. A byte location to be programmed must be erased before a new value is written. The Flash memory is organized in 512-byte pages. The erase operation applies to an entire page (setting all bytes in the page to 0xFF). To erase an entire 512-byte page, perform the following steps: Step 1. Step 2. Step 3. Step 4. Step 5. Step 6. Disable interrupts (recommended). Write the first key code to FLKEY: 0xA5. Write the second key code to FLKEY: 0xF1. Set the PSEE bit (register PSCTL). Set the PSWE bit (register PSCTL). Using the MOVX instruction, write a data byte to any location within the 512-byte page to be erased. Step 7. Clear the PSWE bit (register PSCTL). Step 8. Clear the PSEE bit (register PSCTI). Rev. 1.5 107 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 12.1.3. Flash Write Procedure Bytes in Flash memory can be written one byte at a time, or in groups of two. The FLBWE bit in register PFE0CN (SFR Definition 10.1) controls whether a single byte or a block of two bytes is written to Flash during a write operation. When FLBWE is cleared to ‘0’, the Flash will be written one byte at a time. When FLBWE is set to ‘1’, the Flash will be written in two-byte blocks. Block writes are performed in the same amount of time as single-byte writes, which can save time when storing large amounts of data to Flash memory.During a single-byte write to Flash, bytes are written individually, and a Flash write will be performed after each MOVX write instruction. The recommended procedure for writing Flash in single bytes is: Step 1. Step 2. Step 3. Step 4. Step 5. Step 6. Step 7. Disable interrupts. Clear the FLBWE bit (register PFE0CN) to select single-byte write mode. Set the PSWE bit (register PSCTL). Clear the PSEE bit (register PSCTL). Write the first key code to FLKEY: 0xA5. Write the second key code to FLKEY: 0xF1. Using the MOVX instruction, write a single data byte to the desired location within the 512-byte sector. Step 8. Clear the PSWE bit. Step 9. Re-enable interrupts. Steps 5-7 must be repeated for each byte to be written. For block Flash writes, the Flash write procedure is only performed after the last byte of each block is written with the MOVX write instruction. A Flash write block is two bytes long, from even addresses to odd addresses. Writes must be performed sequentially (i.e. addresses ending in 0b and 1b must be written in order). The Flash write will be performed following the MOVX write that targets the address ending in 1b. If a byte in the block does not need to be updated in Flash, it should be written to 0xFF. The recommended procedure for writing Flash in blocks is: Step 1. Step 2. Step 3. Step 4. Step 5. Step 6. Step 7. Disable interrupts. Set the FLBWE bit (register PFE0CN) to select block write mode. Set the PSWE bit (register PSCTL). Clear the PSEE bit (register PSCTL). Write the first key code to FLKEY: 0xA5. Write the second key code to FLKEY: 0xF1. Using the MOVX instruction, write the first data byte to the even block location (ending in 0b). Step 8. Write the first key code to FLKEY: 0xA5. Step 9. Write the second key code to FLKEY: 0xF1. Step 10. Using the MOVX instruction, write the second data byte to the odd block location (ending in 1b). Step 11. Clear the PSWE bit. Step 12. Re-enable interrupts. Steps 5–10 must be repeated for each block to be written. 108 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 12.1. Flash Electrical Characteristics Parameter Flash Size Endurance Erase Cycle Time Write Cycle Time Conditions C8051F340/2/4/6/A/C/D* Min 65536* C8051F341/3/5/7/8/9/B 32768 20k 10 40 25 MHz System Clock 25 MHz System Clock Typ 100k 15 55 Max 20 70 Units Bytes Bytes Erase/Write ms µs *Note: 1024 bytes at location 0xFC00 to 0xFFFF are reserved. 12.2. Non-Volatile Data Storage The Flash memory can be used for non-volatile data storage as well as program code. This allows data such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX write instruction and read using the MOVC instruction. Note: MOVX read instructions always target XRAM. 12.3. Security Options The CIP-51 provides security options to protect the Flash memory from inadvertent modification by software as well as to prevent the viewing of proprietary program code and constants. The Program Store Write Enable (bit PSWE in register PSCTL) and the Program Store Erase Enable (bit PSEE in register PSCTL) bits protect the Flash memory from accidental modification by software. PSWE must be explicitly set to ‘1’ before software can modify the Flash memory; both PSWE and PSEE must be set to ‘1’ before software can erase Flash memory. Additional security features prevent proprietary program code and data constants from being read or altered across the C2 interface. A Security Lock Byte located at the last byte of Flash user space offers protection of the Flash program memory from access (reads, writes, or erases) by unprotected code or the C2 interface. The Flash security mechanism allows the user to lock n 512-byte Flash pages, starting at page 0 (addresses 0x0000 to 0x01FF), where n is the 1’s complement number represented by the Security Lock Byte. Note that the page containing the Flash Security Lock Byte is also locked when any other Flash pages are locked. See example below. Security Lock Byte: 1’s Complement: Flash pages locked: 11111101b 00000010b 3 (2 + Flash Lock Byte Page) First two pages of Flash: 0x0000 to 0x03FF Addresses locked: Flash Lock Byte Page: (0xFA00 to 0xFBFF for 64k devices; 0x7E00 to 0x7FFF for 32k devices) Rev. 1.5 109 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D C8051F340/2/4/6/A/C/D Reserved 0xFC00 Lock Byte 0xFBFF 0xFBFE 0xFA00 FLASH memory organized in 512-byte pages Locked when any other FLASH pages are locked C8051F341/3/5/7/8/9/B Lock Byte 0x7FFE 0x7E00 Unlocked FLASH Pages Access limit set according to the FLASH security lock byte Unlocked FLASH Pages 0x0000 Figure 12.1. Flash Program Memory Map and Security Byte 110 0x7FFF Rev. 1.5 0x0000 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D The level of FLASH security depends on the FLASH access method. The three FLASH access methods that can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on unlocked pages, and user firmware executing on locked pages. Accessing FLASH from the C2 debug interface: 1. 2. 3. 4. 5. 6. Any unlocked page may be read, written, or erased. Locked pages cannot be read, written, or erased. The page containing the Lock Byte may be read, written, or erased if it is unlocked. Reading the contents of the Lock Byte is always permitted. Locking additional pages (changing ‘1’s to ‘0’s in the Lock Byte) is not permitted. Unlocking FLASH pages (changing ‘0’s to ‘1’s in the Lock Byte) requires the C2 Device Erase command, which erases all FLASH pages including the page containing the Lock Byte and the Lock Byte itself. 7. The Reserved Area cannot be read, written, or erased. Accessing FLASH from user firmware executing on an unlocked page: 1. Any unlocked page except the page containing the Lock Byte may be read, written, or erased. 2. Locked pages cannot be read, written, or erased. 3. The page containing the Lock Byte cannot be erased. It may be read or written only if it is unlocked. 4. Reading the contents of the Lock Byte is always permitted. 5. Locking additional pages (changing ‘1’s to ‘0’s in the Lock Byte) is not permitted. 6. Unlocking FLASH pages (changing ‘0’s to ‘1’s in the Lock Byte) is not permitted. 7. The Reserved Area cannot be read, written, or erased. Any attempt to access the reserved area, or any other locked page, will result in a FLASH Error device reset. Accessing FLASH from user firmware executing on a locked page: 1. 2. 3. 4. 5. 6. 7. Any unlocked page except the page containing the Lock Byte may be read, written, or erased. Any locked page except the page containing the Lock Byte may be read, written, or erased. The page containing the Lock Byte cannot be erased. It may only be read or written. Reading the contents of the Lock Byte is always permitted. Locking additional pages (changing ‘1’s to ‘0’s in the Lock Byte) is not permitted. Unlocking FLASH pages (changing ‘0’s to ‘1’s in the Lock Byte) is not permitted. The Reserved Area cannot be read, written, or erased. Any attempt to access the reserved area, or any other locked page, will result in a FLASH Error device reset. Rev. 1.5 111 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 12.1. PSCTL: Program Store R/W Control R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - - - - - Reserved PSEE PSWE 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x8F Bits7–3: Unused: Read = 00000b. Write = don’t care. Bit2: Reserved. Read = 0b. Must Write = 0b. Bit1: PSEE: Program Store Erase Enable Setting this bit (in combination with PSWE) allows an entire page of Flash program memory to be erased. If this bit is logic 1 and Flash writes are enabled (PSWE is logic 1), a write to Flash memory using the MOVX instruction will erase the entire page that contains the location addressed by the MOVX instruction. The value of the data byte written does not matter. 0: Flash program memory erasure disabled. 1: Flash program memory erasure enabled. Bit0: PSWE: Program Store Write Enable Setting this bit allows writing a byte of data to the Flash program memory using the MOVX write instruction. The Flash location should be erased before writing data. 0: Writes to Flash program memory disabled. 1: Writes to Flash program memory enabled; the MOVX write instruction targets Flash memory. SFR Definition 12.2. FLKEY: Flash Lock and Key R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xB7 Bits–0: 112 FLKEY: Flash Lock and Key Register Write: This register must be written to before Flash writes or erases can be performed. Flash remains locked until this register is written to with the following key codes: 0xA5, 0xF1. The timing of the writes does not matter, as long as the codes are written in order. The key codes must be written for each Flash write or erase operation. Flash will be locked until the next system reset if the wrong codes are written or if a Flash operation is attempted before the codes have been written correctly. Read: When read, bits 1-0 indicate the current Flash lock state. 00: Flash is write/erase locked. 01: The first key code has been written (0xA5). 10: Flash is unlocked (writes/erases allowed). 11: Flash writes/erases disabled until the next reset. Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 12.3. FLSCL: Flash Scale R/W FOSE Bit7 R/W R/W Reserved Reserved Bit6 Bit5 R/W FLRT Bit4 R/W R/W R/W R/W Reset Value Reserved Reserved Reserved Reserved 10000000 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xB6 Bits7: FOSE: Flash One-shot Enable This bit enables the Flash read one-shot. When the Flash one-shot disabled, the Flash sense amps are enabled for a full clock cycle during Flash reads. At system clock frequencies below 10 MHz, disabling the Flash one-shot will increase system power consumption. 0: Flash one-shot disabled. 1: Flash one-shot enabled. Bits6–5: RESERVED. Read = 00b. Must Write 00b. Bit 4: FLRT: FLASH Read Time. This bit should be programmed to the smallest allowed value, according to the system clock speed. 0: SYSCLK 2 x SYSCLK) to access this area with MOVX instructions. Bit5: Unused. Read = 0b. Write = don’t care. Bit4: EMD2: EMIF Multiplex Mode Select. 0: EMIF operates in multiplexed address/data mode. 1: EMIF operates in non-multiplexed mode (separate address and data pins). Bits3–2: EMD1–0: EMIF Operating Mode Select. These bits control the operating mode of the External Memory Interface. 00: Internal Only: MOVX accesses on-chip XRAM only. All effective addresses alias to on-chip memory space. 01: Split Mode without Bank Select: Accesses below the on-chip XRAM boundary are directed on-chip. Accesses above the on-chip XRAM boundary are directed off-chip. 8-bit off-chip MOVX operations use the current contents of the Address High port latches to resolve upper address byte. Note that in order to access off-chip space, EMI0CN must be set to a page that is not contained in the on-chip address space. 10: Split Mode with Bank Select: Accesses below the on-chip XRAM boundary are directed on-chip. Accesses above the on-chip XRAM boundary are directed off-chip. 8-bit off-chip MOVX operations use the contents of EMI0CN to determine the high-byte of the address. 11: External Only: MOVX accesses off-chip XRAM only. On-chip XRAM is not visible to the CPU. Bits1–0: EALE1–0: ALE Pulse-Width Select Bits (only has effect when EMD2 = 0). 00: ALE high and ALE low pulse width = 1 SYSCLK cycle. 01: ALE high and ALE low pulse width = 2 SYSCLK cycles. 10: ALE high and ALE low pulse width = 3 SYSCLK cycles. 11: ALE high and ALE low pulse width = 4 SYSCLK cycles. Rev. 1.5 118 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 13.5. Multiplexed and Non-multiplexed Selection The External Memory Interface is capable of acting in a Multiplexed mode or a Non-multiplexed mode, depending on the state of the EMD2 (EMI0CF.4) bit. 13.5.1. Multiplexed Configuration In Multiplexed mode, the Data Bus and the lower 8-bits of the Address Bus share the same Port pins: AD[7:0]. In this mode, an external latch (74HC373 or equivalent logic gate) is used to hold the lower 8-bits of the RAM address. The external latch is controlled by the ALE (Address Latch Enable) signal, which is driven by the External Memory Interface logic. An example of a Multiplexed Configuration is shown in Figure 13.2. In Multiplexed mode, the external MOVX operation can be broken into two phases delineated by the state of the ALE signal. During the first phase, ALE is high and the lower 8-bits of the Address Bus are presented to AD[7:0]. During this phase, the address latch is configured such that the ‘Q’ outputs reflect the states of the ‘D’ inputs. When ALE falls, signaling the beginning of the second phase, the address latch outputs remain fixed and are no longer dependent on the latch inputs. Later in the second phase, the Data Bus controls the state of the AD[7:0] port at the time RD or WR is asserted. See Section “13.7.2. Multiplexed Mode” on page 127 for more information. A[15:8] A[15:8] ADDRESS BUS 74HC373 E M I F ALE AD[7:0] G ADDRESS/DATA BUS D Q A[7:0] VDD 64K X 8 SRAM (Optional) 8 I/O[7:0] CE WE OE WR RD Figure 13.2. Multiplexed Configuration Example 119 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 13.5.2. Non-multiplexed Configuration In Non-multiplexed mode, the Data Bus and the Address Bus pins are not shared. An example of a Non-multiplexed Configuration is shown in Figure 13.3. See Section “13.7.1. Non-multiplexed Mode” on page 124 for more information about Non-multiplexed operation. E M I F A[15:0] A[15:0] ADDRESS BUS VDD (Optional) 64K X 8 SRAM I/O[7:0] 8 D[7:0] DATA BUS CE WE OE WR RD Figure 13.3. Non-multiplexed Configuration Example 13.6. Memory Mode Selection The external data memory space can be configured in one of four modes, shown in Figure 13.4, based on the EMIF Mode bits in the EMI0CF register (SFR Definition 13.2). These modes are summarized below. More information about the different modes can be found in Section “13.7. Timing” on page 122. EMI0CF[3:2] = 00 EMI0CF[3:2] = 01 0xFFFF EMI0CF[3:2] = 11 EMI0CF[3:2] = 10 0xFFFF 0xFFFF 0xFFFF On-Chip XRAM On-Chip XRAM Off-Chip Memory (No Bank Select) Off-Chip Memory (Bank Select) On-Chip XRAM Off-Chip Memory On-Chip XRAM On-Chip XRAM On-Chip XRAM On-Chip XRAM On-Chip XRAM 0x0000 0x0000 0x0000 0x0000 Figure 13.4. EMIF Operating Modes Rev. 1.5 120 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 13.6.1. Internal XRAM Only When EMI0CF.[3:2] are set to ‘00’, all MOVX instructions will target the internal XRAM space on the device. Memory accesses to addresses beyond the populated space will wrap on 2k or 4k boundaries (depending on the RAM available on the device). As an example, the addresses 0x1000 and 0x2000 both evaluate to address 0x0000 in on-chip XRAM space. • • 8-bit MOVX operations use the contents of EMI0CN to determine the high-byte of the effective address and R0 or R1 to determine the low-byte of the effective address. 16-bit MOVX operations use the contents of the 16-bit DPTR to determine the effective address. 13.6.2. Split Mode without Bank Select When EMI0CF.[3:2] are set to ‘01’, the XRAM memory map is split into two areas, on-chip space and off-chip space. • • • • 121 Effective addresses below the internal XRAM size boundary will access on-chip XRAM space. Effective addresses above the internal XRAM size boundary will access off-chip space. 8-bit MOVX operations use the contents of EMI0CN to determine whether the memory access is on-chip or off-chip. However, in the “No Bank Select” mode, an 8-bit MOVX operation will not drive the upper 8-bits A[15:8] of the Address Bus during an off-chip access. This allows the user to manipulate the upper address bits at will by setting the Port state directly via the port latches. This behavior is in contrast with “Split Mode with Bank Select” described below. The lower 8-bits of the Address Bus A[7:0] are driven, determined by R0 or R1. 16-bit MOVX operations use the contents of DPTR to determine whether the memory access is on-chip or off-chip, and unlike 8-bit MOVX operations, the full 16-bits of the Address Bus A[15:0] are driven during the off-chip transaction. Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 13.6.3. Split Mode with Bank Select When EMI0CF.[3:2] are set to ‘10’, the XRAM memory map is split into two areas, on-chip space and off-chip space. • • • • Effective addresses below the internal XRAM size boundary will access on-chip XRAM space. Effective addresses above the internal XRAM size boundary will access off-chip space. 8-bit MOVX operations use the contents of EMI0CN to determine whether the memory access is on-chip or off-chip. The upper 8-bits of the Address Bus A[15:8] are determined by EMI0CN, and the lower 8-bits of the Address Bus A[7:0] are determined by R0 or R1. All 16-bits of the Address Bus A[15:0] are driven in “Bank Select” mode. 16-bit MOVX operations use the contents of DPTR to determine whether the memory access is on-chip or off-chip, and the full 16-bits of the Address Bus A[15:0] are driven during the off-chip transaction. 13.6.4. External Only When EMI0CF[3:2] are set to ‘11’, all MOVX operations are directed to off-chip space. On-chip XRAM is not visible to the CPU. This mode is useful for accessing off-chip memory located between 0x0000 and the internal XRAM size boundary. • • 8-bit MOVX operations ignore the contents of EMI0CN. The upper Address bits A[15:8] are not driven (identical behavior to an off-chip access in “Split Mode without Bank Select” described above). This allows the user to manipulate the upper address bits at will by setting the Port state directly. The lower 8-bits of the effective address A[7:0] are determined by the contents of R0 or R1. 16-bit MOVX operations use the contents of DPTR to determine the effective address A[15:0]. The full 16-bits of the Address Bus A[15:0] are driven during the off-chip transaction. 13.7. Timing The timing parameters of the External Memory Interface can be configured to enable connection to devices having different setup and hold time requirements. The Address Setup time, Address Hold time, RD and WR strobe widths, and in multiplexed mode, the width of the ALE pulse are all programmable in units of SYSCLK periods through EMI0TC, shown in SFR Definition 13.3, and EMI0CF[1:0]. The timing for an off-chip MOVX instruction can be calculated by adding 4 SYSCLK cycles to the timing parameters defined by the EMI0TC register. Assuming non-multiplexed operation, the minimum execution time for an off-chip XRAM operation is 5 SYSCLK cycles (1 SYSCLK for RD or WR pulse + 4 SYSCLKs). For multiplexed operations, the Address Latch Enable signal will require a minimum of 2 additional SYSCLK cycles. Therefore, the minimum execution time for an off-chip XRAM operation in multiplexed mode is 7 SYSCLK cycles (2 for ALE + 1 for RD or WR + 4). The programmable setup and hold times default to the maximum delay settings after a reset. Table 13.1 lists the AC parameters for the External Memory Interface, and Figure 13.5 through Figure 13.10 show the timing diagrams for the different External Memory Interface modes and MOVX operations. Rev. 1.5 122 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 13.3. EMI0TC: External Memory Timing Control R/W R/W R/W R/W R/W R/W R/W R/W Reset Value EAS1 EAS0 EWR3 EWR2 EWR1 EWR0 EAH1 EAH0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x84 Bits7–6: EAS1–0: EMIF Address Setup Time Bits. 00: Address setup time = 0 SYSCLK cycles. 01: Address setup time = 1 SYSCLK cycle. 10: Address setup time = 2 SYSCLK cycles. 11: Address setup time = 3 SYSCLK cycles. Bits5–2: EWR3–0: EMIF WR and RD Pulse-Width Control Bits. 0000: WR and RD pulse width = 1 SYSCLK cycle. 0001: WR and RD pulse width = 2 SYSCLK cycles. 0010: WR and RD pulse width = 3 SYSCLK cycles. 0011: WR and RD pulse width = 4 SYSCLK cycles. 0100: WR and RD pulse width = 5 SYSCLK cycles. 0101: WR and RD pulse width = 6 SYSCLK cycles. 0110: WR and RD pulse width = 7 SYSCLK cycles. 0111: WR and RD pulse width = 8 SYSCLK cycles. 1000: WR and RD pulse width = 9 SYSCLK cycles. 1001: WR and RD pulse width = 10 SYSCLK cycles. 1010: WR and RD pulse width = 11 SYSCLK cycles. 1011: WR and RD pulse width = 12 SYSCLK cycles. 1100: WR and RD pulse width = 13 SYSCLK cycles. 1101: WR and RD pulse width = 14 SYSCLK cycles. 1110: WR and RD pulse width = 15 SYSCLK cycles. 1111:WR and RD pulse width = 16 SYSCLK cycles. Bits1–0: EAH1–0: EMIF Address Hold Time Bits. 00: Address hold time = 0 SYSCLK cycles. 01: Address hold time = 1 SYSCLK cycle. 10: Address hold time = 2 SYSCLK cycles. 11: Address hold time = 3 SYSCLK cycles. 123 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 13.7.1. Non-multiplexed Mode 13.7.1.1.16-bit MOVX: EMI0CF[4:2] = ‘101’, ‘110’, or ‘111’. Nonmuxed 16-bit WRITE ADDR[15:8] P2 EMIF ADDRESS (8 MSBs) from DPH P2 ADDR[7:0] P3 EMIF ADDRESS (8 LSBs) from DPL P3 DATA[7:0] P4 EMIF WRITE DATA P4 T T WDS T ACS WDH T T ACW ACH WR P1.7 P1.7 RD P1.6 P1.6 Nonmuxed 16-bit READ ADDR[15:8] P2 EMIF ADDRESS (8 MSBs) from DPH P2 ADDR[7:0] P3 EMIF ADDRESS (8 LSBs) from DPL P3 DATA[7:0] P4 EMIF READ DATA P4 T RDS T ACS T ACW T RDH T ACH RD P1.6 P1.6 WR P1.7 P1.7 Figure 13.5. Non-multiplexed 16-bit MOVX Timing Rev. 1.5 124 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 13.7.1.2.8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘101’ or ‘111’. Nonmuxed 8-bit WRITE without Bank Select ADDR[15:8] P2 ADDR[7:0] P3 EMIF ADDRESS (8 LSBs) from R0 or R1 P3 DATA[7:0] P4 EMIF WRITE DATA P4 T T WDS T WDH T ACS T ACW ACH WR P1.7 P1.7 RD P1.6 P1.6 Nonmuxed 8-bit READ without Bank Select ADDR[15:8] P2 ADDR[7:0] P3 DATA[7:0] P4 EMIF ADDRESS (8 LSBs) from R0 or R1 EMIF READ DATA T RDS T T ACS ACW P3 P4 T RDH T ACH RD P1.6 P1.6 WR P1.7 P1.7 Figure 13.6. Non-multiplexed 8-bit MOVX without Bank Select Timing 125 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 13.7.1.3.8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘110’. Muxed 8-bit WRITE with Bank Select ADDR[15:8] P3 AD[7:0] P4 EMIF ADDRESS (8 MSBs) from EMI0CN EMIF ADDRESS (8 LSBs) from R0 or R1 T ALEH ALE P3 EMIF WRITE DATA P4 T ALEL P1.3 P1.3 T T WDS T ACS WDH T T ACW ACH WR P1.7 P1.7 RD P1.6 P1.6 Muxed 8-bit READ with Bank Select ADDR[15:8] P3 AD[7:0] P4 EMIF ADDRESS (8 MSBs) from EMI0CN EMIF ADDRESS (8 LSBs) from R0 or R1 T ALEH ALE P3 EMIF READ DATA T T ALEL RDS P4 T RDH P1.3 P1.3 T ACS T ACW T ACH RD P1.6 P1.6 WR P1.7 P1.7 Figure 13.7. Non-multiplexed 8-bit MOVX with Bank Select Timing Rev. 1.5 126 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 13.7.2. Multiplexed Mode 13.7.2.1.16-bit MOVX: EMI0CF[4:2] = ‘001’, ‘010’, or ‘011’. Muxed 16-bit WRITE ADDR[15:8] P3 AD[7:0] P4 EMIF ADDRESS (8 MSBs) from DPH EMIF ADDRESS (8 LSBs) from DPL T ALEH ALE P3 EMIF WRITE DATA P4 T ALEL P1.3 P1.3 T T WDS T ACS WDH T T ACW ACH WR P1.7 P1.7 RD P1.6 P1.6 Muxed 16-bit READ ADDR[15:8] P3 AD[7:0] P4 EMIF ADDRESS (8 MSBs) from DPH EMIF ADDRESS (8 LSBs) from DPL T ALEH ALE P3 EMIF READ DATA T T ALEL RDS T RDH P1.3 P1.3 T ACS T ACW T ACH RD P1.6 P1.6 WR P1.7 P1.7 Figure 13.8. Multiplexed 16-bit MOVX Timing 127 P4 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 13.7.2.2.8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘001’ or ‘011’. Muxed 8-bit WRITE Without Bank Select ADDR[15:8] AD[7:0] P3 P4 EMIF ADDRESS (8 LSBs) from R0 or R1 T ALEH ALE EMIF WRITE DATA P4 T ALEL P1.3 P1.3 T T WDS T ACS WDH T T ACW ACH WR P1.7 P1.7 RD P1.6 P1.6 Muxed 8-bit READ Without Bank Select ADDR[15:8] AD[7:0] P3 P4 EMIF ADDRESS (8 LSBs) from R0 or R1 T ALEH ALE EMIF READ DATA T T ALEL RDS P4 T RDH P1.3 P1.3 T ACS T ACW T ACH RD P1.6 P1.6 WR P1.7 P1.7 Figure 13.9. Multiplexed 8-bit MOVX without Bank Select Timing Rev. 1.5 128 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 13.7.2.3.8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘010’. Muxed 8-bit WRITE with Bank Select ADDR[15:8] P3 AD[7:0] P4 EMIF ADDRESS (8 MSBs) from EMI0CN EMIF ADDRESS (8 LSBs) from R0 or R1 T ALEH ALE P3 EMIF WRITE DATA P4 T ALEL P1.3 P1.3 T T WDS T ACS WDH T T ACW ACH WR P1.7 P1.7 RD P1.6 P1.6 Muxed 8-bit READ with Bank Select ADDR[15:8] P3 AD[7:0] P4 EMIF ADDRESS (8 MSBs) from EMI0CN EMIF ADDRESS (8 LSBs) from R0 or R1 T ALEH ALE P3 EMIF READ DATA T T ALEL RDS T RDH P1.3 P1.3 T ACS T ACW T ACH RD P1.6 P1.6 WR P1.7 P1.7 Figure 13.10. Multiplexed 8-bit MOVX with Bank Select Timing 129 P4 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 13.1. AC Parameters for External Memory Interface Parameter Description Min* Max* Units TACS Address / Control Setup Time 0 3 x TSYSCLK ns TACW Address / Control Pulse Width 1 x TSYSCLK 16 x TSYSCLK ns TACH Address / Control Hold Time 0 3 x TSYSCLK ns TALEH Address Latch Enable High Time 1 x TSYSCLK 4 x TSYSCLK ns TALEL Address Latch Enable Low Time 1 x TSYSCLK 4 x TSYSCLK ns TWDS Write Data Setup Time 1 x TSYSCLK 19 x TSYSCLK ns TWDH Write Data Hold Time 0 3 x TSYSCLK ns TRDS Read Data Setup Time 20 ns TRDH Read Data Hold Time 0 ns *Note: TSYSCLK is equal to one period of the device system clock (SYSCLK). Rev. 1.5 130 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 14. Oscillators C8051F34x devices include a programmable internal high-frequency oscillator, a programmable internal low-frequency oscillator (C8051F340/1/2/3/4/5/8/9/A/B/C/D), an external oscillator drive circuit, and a 4x Clock Multiplier. The internal high-frequency and low-frequency oscillators can be enabled/disabled and adjusted using the special function registers, as shown in Figure 14.1. The system clock (SYSCLK) can be derived from either of the internal oscillators, the external oscillator circuit, or the 4x Clock Multiplier divided by 2. The USB clock (USBCLK) can be derived from the internal oscillator, external oscillator, or 4x Clock Multiplier. Oscillator electrical specifications are given in Table 14.1. CLKSL2 CLKSL1 CLKSL0 IFCN1 IFCN0 CLKSEL USBCLK2 USBCLK1 USBCLK0 Option 2 VDD OSCLCN OSCLEN OSCLRDY OSCLF3 OSCLF2 OSCLF1 OSCLF0 OSCLD1 OSCLD0 OSCICN IOSCEN IFRDY SUSPEND OSCICL Option 3 XTAL2 EN Programmable HighFrequency Oscillator XTAL2 IOSC n OSCLF3-0 EN Programmable LowFrequency Oscillator (C8051F340/1/2/3/4/5/8/9/ A/B/C/D) Input Circuit XTAL2 Option 4 OSC EXOSC IOSC XTLVLD 10MΩ SYSCLK EXOSC x2 x2 IOSC / 2 XTAL2 EXOSC / 2 Clock Multiplier EXOSC XFCN2 XFCN1 XFCN0 XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 USBCLK CLKMUL EXOSC / 2 EXOSC / 3 EXOSC / 4 USBCLK2-0 OSCXCN MULSEL1 MULSEL0 XTAL1 MULEN MULINIT MULRDY Option 1 n Figure 14.1. Oscillator Diagram Rev. 1.5 131 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 14.1. Programmable Internal High-Frequency (H-F) Oscillator All C8051F34x devices include a programmable internal oscillator that defaults as the system clock after a system reset. The internal oscillator period can be programmed via the OSCICL register shown in SFR Definition 14.2. The OSCICL register is factory calibrated to obtain a 12 MHz internal oscillator frequency. Electrical specifications for the precision internal oscillator are given in Table 14.1 on page 141. Note that the system clock may be derived from the programmed internal oscillator divided by 1, 2, 4, or 8, as defined by the IFCN bits in register OSCICN. The divide value defaults to 8 following a reset. 14.1.1. Internal H-F Oscillator Suspend Mode The internal high-frequency oscillator may be placed in Suspend mode by writing ‘1’ to the SUSPEND bit in register OSCICN. In Suspend mode, the internal H-F oscillator is stopped until a non-idle USB event is detected (Section 16) or VBUS matches the polarity selected by the VBPOL bit in register REG0CN (Section 8.2). Note that the USB transceiver can still detect USB events when it is disabled. SFR Definition 14.1. OSCICN: Internal H-F Oscillator Control R/W R R/W R IOSCEN IFRDY SUSPEND - Bit7 Bit6 Bit5 Bit4 R/W R/W R/W R/W Reset Value - - IFCN1 IFCN0 10000000 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xB2 Bit7: IOSCEN: Internal H-F Oscillator Enable Bit. 0: Internal H-F Oscillator Disabled. 1: Internal H-F Oscillator Enabled. Bit6: IFRDY: Internal H-F Oscillator Frequency Ready Flag. 0: Internal H-F Oscillator is not running at programmed frequency. 1: Internal H-F Oscillator is running at programmed frequency. Bit5: SUSPEND: Force Suspend Writing a ‘1’ to this bit will force the internal H-F oscillator to be stopped. The oscillator will be re-started on the next non-idle USB event (i.e., RESUME signaling) or VBUS interrupt event (see SFR Definition 8.1). Bits4–2: UNUSED. Read = 000b, Write = don't care. Bits1–0: IFCN1–0: Internal H-F Oscillator Frequency Control. 00: SYSCLK derived from Internal H-F Oscillator divided by 8. 01: SYSCLK derived from Internal H-F Oscillator divided by 4. 10: SYSCLK derived from Internal H-F Oscillator divided by 2. 11: SYSCLK derived from Internal H-F Oscillator divided by 1. 132 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 14.2. OSCICL: Internal H-F Oscillator Calibration R/W R/W R/W - - - Bit7 Bit6 Bit5 R/W R/W Bit4 Bit3 R/W R/W R/W Reset Value Bit1 Bit0 SFR Address: OSCCAL Bit2 Variable 0xB3 Bits4–0: OSCCAL: Oscillator Calibration Value These bits determine the internal H-F oscillator period. When set to 00000b, the oscillator operates at its fastest setting. When set to 11111b, the oscillator operates at is slowest setting. The contents of this register are factory calibrated to produce a 12 MHz internal oscillator frequency. Note: The contents of this register are undefined when Clock Recovery is enabled. See Section “16.4. USB Clock Configuration” on page 166 for details on Clock Recovery. 14.2. Programmable Internal Low-Frequency (L-F) Oscillator The C8051F340/1/2/3/4/5/8/9/C/D devices include a programmable internal oscillator which operates at a nominal frequency of 80 kHz. The low-frequency oscillator circuit includes a divider that can be changed to divide the clock by 1, 2, 4, or 8, using the OSCLD bits in the OSCLCN register (see SFR Definition 14.3). Additionally, the OSCLF bits (OSCLCN5:2) can be used to adjust the oscillator’s output frequency. 14.2.1. Calibrating the Internal L-F Oscillator Timers 2 and 3 include capture functions that can be used to capture the oscillator frequency, when running from a known time base. When either Timer 2 or Timer 3 is configured for L-F Oscillator Capture Mode, a falling edge (Timer 2) or rising edge (Timer 3) of the low-frequency oscillator’s output will cause a capture event on the corresponding timer. As a capture event occurs, the current timer value (TMRnH:TMRnL) is copied into the timer reload registers (TMRnRLH:TMRnRLL). By recording the difference between two successive timer capture values, the low-frequency oscillator’s period can be calculated. The OSCLF bits can then be adjusted to produce the desired oscillator period. Rev. 1.5 133 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 14.3. OSCLCN: Internal L-F Oscillator Control R/W R R/W OSCLEN OSCLRDY OSCLF3 Bit7 Bit6 Bit5 R R/W R/W R/W R/W Reset Value OSCLF2 OSCLF1 OSCLF0 OSCLD1 OSCLD0 00vvvv00 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x86 Bit7: OSCLEN: Internal L-F Oscillator Enable. 0: Internal L-F Oscillator Disabled. 1: Internal L-F Oscillator Enabled. Bit6: OSCLRDY: Internal L-F Oscillator Ready Flag. 0: Internal L-F Oscillator frequency not stabilized. 1: Internal L-F Oscillator frequency stabilized. Bits5–2: OSCLF[3:0]: Internal L-F Oscillator Frequency Control bits. Fine-tune control bits for the internal L-F Oscillator frequency. When set to 0000b, the L-F oscillator operates at its fastest setting. When set to 1111b, the L-F oscillator operates at its slowest setting. Bits1–0: OSCLD[1:0]: Internal L-F Oscillator Divider Select. 00: Divide by 8 selected. 01: Divide by 4selected. 10: Divide by 2 selected. 11: Divide by 1 selected. 134 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 14.3. External Oscillator Drive Circuit The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor, or RC network. A CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crystal/ resonator must be wired across the XTAL1 and XTAL2 pins as shown in Option 1 of Figure 14.1. A 10 MΩ resistor also must be wired across the XTAL1 and XTAL2 pins for the crystal/resonator configuration. In RC, capacitor, or CMOS clock configuration, the clock source should be wired to the XTAL2 pin as shown in Option 2, 3, or 4 of Figure 14.1. The type of external oscillator must be selected in the OSCXCN register, and the frequency control bits (XFCN) must be selected appropriately (see SFR Definition 14.4) Important Note on External Oscillator Usage: Port pins must be configured when using the external oscillator circuit. When the external oscillator drive circuit is enabled in crystal/resonator mode, Port pins P0.6 and P0.7 (C8051F340/1/4/5/8) or P0.2 and P0.3 (C8051F342/3/6/7/9/A/B) are used as XTAL1 and XTAL2 respectively. When the external oscillator drive circuit is enabled in capacitor, RC, or CMOS clock mode, Port pin P0.7 (C8051F340/1/4/5/8) or P0.3 (C8051F342/3/6/7/9/A/B) is used as XTAL2. The Port I/ O Crossbar should be configured to skip the Port pins used by the oscillator circuit; see Section “15.1. Priority Crossbar Decoder” on page 144 for Crossbar configuration. Additionally, when using the external oscillator circuit in crystal/resonator, capacitor, or RC mode, the associated Port pins should be configured as analog inputs. In CMOS clock mode, the associated pin should be configured as a digital input. See Section “15.2. Port I/O Initialization” on page 147 for details on Port input mode selection. 14.3.1. Clocking Timers Directly Through the External Oscillator The external oscillator source divided by eight is a clock option for the timers (Section “21. Timers” on page 235) and the Programmable Counter Array (PCA) (Section “22. Programmable Counter Array (PCA0)” on page 255). When the external oscillator is used to clock these peripherals, but is not used as the system clock, the external oscillator frequency must be less than or equal to the system clock frequency. In this configuration, the clock supplied to the peripheral (external oscillator / 8) is synchronized with the system clock; the jitter associated with this synchronization is limited to ±0.5 system clock cycles. 14.3.2. External Crystal Example If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 14.1, Option 1. The External Oscillator Frequency Control value (XFCN) should be chosen from the Crystal column of the table in SFR Definition 14.4 (OSCXCN register). For example, a 12 MHz crystal requires an XFCN setting of 111b. When the crystal oscillator is first enabled, the oscillator amplitude detection circuit requires a settling time to achieve proper bias. Introducing a delay of 1 ms between enabling the oscillator and checking the XTLVLD bit will prevent a premature switch to the external oscillator as the system clock. Switching to the external oscillator before the crystal oscillator has stabilized can result in unpredictable behavior. The recommended procedure is: Step 1. Step 2. Step 3. Step 4. Enable the external oscillator. Wait at least 1 ms. Poll for XTLVLD => ‘1’. Switch the system clock to the external oscillator. Important Note on External Crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The crystal should be placed as close as possible to the XTAL pins on the device. The traces should be as short as possible and shielded with ground plane from any other traces which could introduce noise or interference. Rev. 1.5 135 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 14.3.3. External RC Example If an RC network is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 14.1, Option 2. The capacitor should be no greater than 100 pF; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To determine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, first select the RC network value to produce the desired frequency of oscillation. If the frequency desired is 100 kHz, let R = 246 kΩ and C = 50 pF: 3 3 1.23 ( 10 ) 1.23 ( 10 ) f = ------------------------ = -------------------------- = 0.1 MHz = 100 kHz RC [ 246 × 50 ] Referring to the table in SFR Definition 14.4, the required XFCN setting is 010b. Programming XFCN to a higher setting in RC mode will improve frequency accuracy at an increased external oscillator supply current. 14.3.4. External Capacitor Example If a capacitor is used as an external oscillator for the MCU, the circuit should be configured as shown in Figure 14.1, Option 3. The capacitor should be no greater than 100 pF; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To determine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, select the capacitor to be used and find the frequency of oscillation from the equations below. Assume VDD = 3.0 V and C = 50 pF: KF KF f = ------------------------- = -------------------------------( C × VDD ) ( 50 x 3 )MHz KF f = ---------------------150 MHz If a frequency of roughly 150 kHz is desired, select the K Factor from the table in SFR Definition 14.4 as KF = 22: 22 f = --------- = 0.146 MHz, or 146 kHz 150 Therefore, the XFCN value to use in this example is 011b. 136 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 14.4. OSCXCN: External Oscillator Control R R/W R/W R/W XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 Bit7 Bit6 Bit5 Bit4 R R/W R/W R/W Reset Value - XFCN2 XFCN1 XFCN0 00000000 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xB1 Bit7: XTLVLD: Crystal Oscillator Valid Flag. (Read only when XOSCMD = 11x.) 0: Crystal Oscillator is unused or not yet stable. 1: Crystal Oscillator is running and stable. Bits6–4: XOSCMD2–0: External Oscillator Mode Bits. 00x: External Oscillator circuit off. 010: External CMOS Clock Mode. 011: External CMOS Clock Mode with divide by 2 stage. 100: RC Oscillator Mode. 101: Capacitor Oscillator Mode. 110: Crystal Oscillator Mode. 111: Crystal Oscillator Mode with divide by 2 stage. Bit3: RESERVED. Read = 0, Write = don't care. Bits2–0: XFCN2–0: External Oscillator Frequency Control Bits. 000-111: See table below: XFCN Crystal (XOSCMD = 11x) 000 f ≤ 32 kHz 001 32 kHz < f ≤ 84kHz 010 84 kHz < f ≤ 225 kHz 011 225 kHz < f ≤ 590 kHz 100 590 kHz < f ≤ 1.5 MHz 101 1.5 MHz < f ≤ 4 MHz 110 4 MHz < f ≤ 10 MHz 111 10 MHz < f ≤ 30 MHz RC (XOSCMD = 10x) f ≤ 25 kHz 25 kHz < f ≤ 50 kHz 50 kHz < f ≤ 100 kHz 100 kHz < f ≤ 200 kHz 200 kHz < f ≤ 400 kHz 400 kHz < f ≤ 800 kHz 800 kHz < f ≤ 1.6 MHz 1.6 MHz < f ≤ 3.2 MHz C (XOSCMD = 10x) K Factor = 0.87 K Factor = 2.6 K Factor = 7.7 K Factor = 22 K Factor = 65 K Factor = 180 K Factor = 664 K Factor = 1590 CRYSTAL MODE (Circuit from Figure 14.1, Option 1; XOSCMD = 11x) Choose XFCN value to match crystal or resonator frequency. RC MODE (Circuit from Figure 14.1, Option 2; XOSCMD = 10x) Choose XFCN value to match frequency range: f = 1.23(103) / (R x C), where f = frequency of clock in MHz C = capacitor value in pF R = Pull-up resistor value in kΩ C MODE (Circuit from Figure 14.1, Option 3; XOSCMD = 10x) Choose K Factor (KF) for the oscillation frequency desired: f = KF / (C x VDD), where f = frequency of clock in MHz C = capacitor value the XTAL2 pin in pF VDD = Power Supply on MCU in volts Rev. 1.5 137 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 14.4. 4x Clock Multiplier The 4x Clock Multiplier allows a 12 MHz oscillator to generate the 48 MHz clock required for Full Speed USB communication (see Section “16.4. USB Clock Configuration” on page 166). A divided version of the Multiplier output can also be used as the system clock. C8051F340/1/2/3 devices can use the 48 MHz Clock Multiplier output as system clock. See Table 3.1, “Global DC Electrical Characteristics,” on page 25 for system clock frequency specifications. See Section 14.5 for details on system clock and USB clock source selection. The 4x Clock Multiplier is configured via the CLKMUL register. The procedure for configuring and enabling the 4x Clock Multiplier is as follows: 1. 2. 3. 4. 5. 6. Reset the Multiplier by writing 0x00 to register CLKMUL. Select the Multiplier input source via the MULSEL bits. Enable the Multiplier with the MULEN bit (CLKMUL | = 0x80). Delay for >5 µs. Initialize the Multiplier with the MULINIT bit (CLKMUL | = 0xC0). Poll for MULRDY => ‘1’. Important Note: When using an external oscillator as the input to the 4x Clock Multiplier, the external source must be enabled and stable before the Multiplier is initialized. See Section 14.5 for details on selecting an external oscillator source. SFR Definition 14.5. CLKMUL: Clock Multiplier Control R/W MULEN Bit7 R/W R MULINIT MULRDY Bit6 Bit5 R/W R/W R/W - - - Bit4 Bit3 Bit2 R/W R/W MULSEL Bit1 Bit0 Reset Value 00000000 SFR Address 0xB9 Bit7: MULEN: Clock Multiplier Enable 0: Clock Multiplier disabled. 1: Clock Multiplier enabled. Bit6: MULINIT: Clock Multiplier Initialize This bit should be a ‘0’ when the Clock Multiplier is enabled. Once enabled, writing a ‘1’ to this bit will initialize the Clock Multiplier. The MULRDY bit reads ‘1’ when the Clock Multiplier is stabilized. Bit5: MULRDY: Clock Multiplier Ready This read-only bit indicates the status of the Clock Multiplier. 0: Clock Multiplier not ready. 1: Clock Multiplier ready (locked). Bits4–2: Unused. Read = 000b; Write = don’t care. Bits1–0: MULSEL: Clock Multiplier Input Select These bits select the clock supplied to the Clock Multiplier. MULSEL 00 01 10 11 138 Selected Clock Internal Oscillator External Oscillator External Oscillator / 2 RESERVED Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 14.5. System and USB Clock Selection The internal oscillator requires little start-up time and may be selected as the system or USB clock immediately following the OSCICN write that enables the internal oscillator. External crystals and ceramic resonators typically require a start-up time before they are settled and ready for use. The Crystal Valid Flag (XTLVLD in register OSCXCN) is set to ‘1’ by hardware when the external oscillator is settled. To avoid reading a false XTLVLD, in crystal mode software should delay at least 1 ms between enabling the external oscillator and checking XTLVLD. RC and C modes typically require no startup time. 14.5.1. System Clock Selection The CLKSL[1:0] bits in register CLKSEL select which oscillator source is used as the system clock. CLKSL[1:0] must be set to 01b for the system clock to run from the external oscillator; however the external oscillator may still clock certain peripherals (timers, PCA, USB) when the internal oscillator is selected as the system clock. The system clock may be switched on-the-fly between the internal oscillator, external oscillator, and 4x Clock Multiplier so long as the selected oscillator is enabled and has settled. C8051F340/ 1/2/3 devices can use the 48 MHz Clock Multiplier output as system clock. See Table 3.1, “Global DC Electrical Characteristics,” on page 25 for system clock frequency specifications. When operating with a system clock of greater than 25 MHz (up to 48 MHz), the FLRT bit (FLSCL.4) should be set to ‘1’. See Section “10. Prefetch Engine” on page 99 for more details. 14.5.2. USB Clock Selection The USBCLK[2:0] bits in register CLKSEL select which oscillator source is used as the USB clock. The USB clock may be derived from the 4x Clock Multiplier output, a divided version of the internal oscillator, or a divided version of the external oscillator. Note that the USB clock must be 48 MHz when operating USB0 as a Full Speed Function; the USB clock must be 6 MHz when operating USB0 as a Low Speed Function. See SFR Definition 14.6 for USB clock selection options. Some example USB clock configurations for Full and Low Speed mode are given below: Clock Signal USB Clock Clock Multiplier Input Internal Oscillator Clock Signal USB Clock Clock Multiplier Input External Oscillator Internal Oscillator Input Source Selection Clock Multiplier Internal Oscillator* Divide by 1 External Oscillator Input Source Selection Clock Multiplier External Oscillator Crystal Oscillator Mode 12 MHz Crystal Register Bit Settings USBCLK = 000b MULSEL = 00b IFCN = 11b Register Bit Settings USBCLK = 000b MULSEL = 01b XOSCMD = 110b XFCN = 111b *Note: Clock Recovery must be enabled for this configuration. Clock Signal USB Clock Internal Oscillator Clock Signal Internal Oscillator Input Source Selection Internal Oscillator / 2 Divide by 1 External Oscillator Input Source Selection Register Bit Settings USBCLK = 001b IFCN = 11b Register Bit Settings Rev. 1.5 139 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Internal Oscillator Input Source Selection External Oscillator / 4 Crystal Oscillator Mode 24 MHz Crystal Clock Signal USB Clock External Oscillator Register Bit Settings USBCLK = 101b XOSCMD = 110b XFCN = 111b SFR Definition 14.6. CLKSEL: Clock Select R/W R/W Bit7 R/W R/W R/W Bit4 Bit3 USBCLK Bit6 Bit5 R/W - R/W R/W Reset Value Bit0 SFR Address CLKSL Bit2 Bit1 00000000 0xA9 Bit 7: Unused. Read = 0b; Write = don’t care. Bits6–4: USBCLK2–0: USB Clock Select These bits select the clock supplied to USB0. When operating USB0 in full-speed mode, the selected clock should be 48 MHz. When operating USB0 in low-speed mode, the selected clock should be 6 MHz. USBCLK 000 001 010 011 100 101 110 111 Selected Clock 4x Clock Multiplier Internal Oscillator / 2 External Oscillator External Oscillator / 2 External Oscillator / 3 External Oscillator / 4 RESERVED RESERVED Bit3: Unused. Read = 0b; Write = don’t care. Bits2–0: CLKSL2–0: System Clock Select These bits select the system clock source. When operating from a system clock of 25 MHz or less, the FLRT bit should be set to ‘0’. When operating with a system clock of greater than 25 MHz (up to 48 MHz), the FLRT bit (FLSCL.4) should be set to ‘1’. See Section “10. Prefetch Engine” on page 99 for more details. CLKSL 000 001 010 011* 100 101-111 Selected Clock Internal Oscillator (as determined by the IFCN bits in register OSCICN) External Oscillator 4x Clock Multiplier / 2 4x Clock Multiplier* Low-Frequency Oscillator RESERVED *Note: This option is only available on 48 MHz devices. 140 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 14.1. Oscillator Electrical Characteristics VDD = 2.7 to 3.6 V; –40 to +85 °C unless otherwise specified Parameter Conditions Min Typ Max Units 11.82 12.00 12.18 MHz — 685 — µA 72 80 99 kHz — 7.0 — µA Full Speed Mode 47.88 48 48.12 Low Speed Mode 5.91 6 6.09 Internal High-Frequency Oscillator (Using Factory-Calibrated Settings) Oscillator Frequency Oscillator Supply Current (from VDD) IFCN = 11b 24 ºC, VDD = 3.0 V, OSCICN.7 = 1 Internal Low-Frequency Oscillator (Using Factory-Calibrated Settings) Oscillator Frequency Oscillator Supply Current (from VDD) OSCLD = 11b 24 ºC, VDD = 3.0 V, OSCLCN.7 = 1 External USB Clock Requirements USB Clock Frequency* MHz *Note: Applies only to external oscillator sources. Rev. 1.5 141 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 15. Port Input/Output Digital and analog resources are available through 40 I/O pins (48-pin packages) or 25 I/O pins (32-pin packages). Port pins are organized as shown in Figure 15.1. Each of the Port pins can be defined as general-purpose I/O (GPIO) or analog input; Port pins P0.0-P3.7 can be assigned to one of the internal digital resources as shown in Figure 15.3. The designer has complete control over which functions are assigned, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder. Note that the state of a Port I/O pin can always be read in the corresponding Port latch, regardless of the Crossbar settings. The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder (Figure 15.3 and Figure 15.4). The registers XBR0, XBR1, and XBR2 defined in SFR Definition 15.1, SFR Definition 15.2, and SFR Definition 15.3, are used to select internal digital functions. All Port I/Os are 5 V tolerant (refer to Figure 15.2 for the Port cell circuit). The Port I/O cells are configured as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1,2,3,4). Complete Electrical Specifications for Port I/O are given in Table 15.1 on page 158. XBR0, XBR1, XBR2, PnSKIP Registers PnMDOUT, PnMDIN Registers Priority Decoder Highest Priority 2 UART0 4 SPI 8 2 (Internal Digital Signals) SMBus CP0 Outputs 2 CP1 Outputs 2 Digital Crossbar 8 P0.0 P1 I/O Cells P1.0 P2 I/O Cells P2.0 P3 I/O Cells P3.0 P0.7 P1.7 SYSCLK 8 6 PCA P2.7 2 T0, T1 8 Lowest Priority P0 I/O Cells UART1** 2 P3.7* 8 P0 (P0.0-P0.7) (Port Latches) 8 P1 (P1.0-P1.7) 8 P2 *P3.1-P3.7 only available on 48-pin packages **UART1 only available on C8051F340/1/4/5/8/A/B devices (P2.0-P2.7) 8 P3 (P3.0-P3.7*) Figure 15.1. Port I/O Functional Block Diagram (Port 0 through Port 3) Rev. 1.5 142 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D W E A K -P U LLU P VDD P U S H -P U LL VDD P O R T -O U T E N A B LE (W E A K ) PORT PAD P O R T -O U T P U T A nalog S elect GND A N A LO G IN P U T P O R T -IN P U T Figure 15.2. Port I/O Cell Block Diagram 143 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 15.1. Priority Crossbar Decoder The Priority Crossbar Decoder (Figure 15.3) assigns a priority to each I/O function, starting at the top with UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that resource (excluding UART0, which is always at pins 4 and 5). If a Port pin is assigned, the Crossbar skips that pin when assigning the next selected resource. Additionally, the Crossbar will skip Port pins whose associated bits in the PnSKIP registers are set. The PnSKIP registers allow software to skip Port pins that are to be used for analog input, dedicated functions, or GPIO. Important Note on Crossbar Configuration: If a Port pin is claimed by a peripheral without use of the Crossbar, its corresponding PnSKIP bit should be set. This applies to the VREF signal, external oscillator pins (XTAL1, XTAL2), the ADC’s external conversion start signal (CNVSTR), EMIF control signals, and any selected ADC or Comparator inputs. The PnSKIP registers may also be used to skip pins to be used as GPIO. The Crossbar skips selected pins as if they were already assigned, and moves to the next unassigned pin. Figure 15.3 shows all the possible pins available to each peripheral. Figure 15.4 shows the Crossbar Decoder priority with no Port pins skipped. Figure 15.5 shows a Crossbar example with pins P0.2, P0.3, and P1.0 skipped. 7 0 1 2 RD 6 WR 5 VREF 4 P3 P3.1-P3.7 unavailable on the 32-pin packages ALE 1 P2 CNVSTR 0 VREF PIN I/O CNVSTR 3 SF Signals (48-pin Package) XTAL2 2 P1 XTAL1 XTAL2 SF Signals (32-pin Package) XTAL1 P0 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 TX0 RX0 SCK MISO MOSI NSS* SDA SCL CP0 CP0A CP1 CP1A SYSCLK CEX0 CEX1 CEX2 CEX3 CEX4 ECI T0 T1 TX1** RX1** Port pin potentially available to peripheral **UART1 available only on C8051F340/1/4/5/8/A/B devices SF Signals Special Function Signals are not assigned by the Crossbar. When these signals are enabled, the Crossbar must be manually configured to skip their corresponding port pins. *NSS is only pinned out in 4-wire SPI mode Figure 15.3. Peripheral Availability on Port I/O Pins Rev. 1.5 144 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 7 0 1 2 RD 6 WR 5 VREF 4 P3 P3.1-P3.7 unavailable on the 32-pin packages ALE 1 P2 CNVSTR 0 VREF PIN I/O CNVSTR 3 SF Signals (48-pin Package) XTAL2 2 P1 XTAL1 XTAL2 SF Signals (32-pin Package) XTAL1 P0 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 TX0 RX0 SCK MISO MOSI NSS* *NSS is only pinned out in 4-wire SPI mode SDA SCL CP0 CP0A CP1 CP1A SYSCLK CEX0 CEX1 CEX2 CEX3 CEX4 ECI T0 T1 TX1** **UART1 available only on C8051F340/1/4/5/8/A/B devices RX1** 0 0 0 0 0 0 0 0 0 0 0 P0SKIP[0:7] 0 0 0 0 0 P1SKIP[0:7] 0 0 0 0 0 0 0 0 0 0 P2SKIP[0:7] Port pin assigned to peripheral by the Crossbar 0 0 XBR0 = 0x07 XBR1 = 0x43 Figure 15.4. Crossbar Priority Decoder in Example Configuration (No Pins Skipped) 145 Rev. 1.5 0 P3SKIP[0:7] Example: SF Signals Special Function Signals are not assigned by the Crossbar. When these signals are 0 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 7 0 1 2 RD 6 WR 5 VREF 4 P3.1-P3.7 una va ila ble on the 32-pin pa cka ge s CNVSTR 1 P3 P2 ALE 0 VREF P IN I/O CNVSTR 3 S F Signa ls (48-pin P a cka ge ) XTAL2 2 P1 XTAL1 XTAL2 S F Signa ls (32-pin P a cka ge ) XTAL1 P0 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 TX 0 RX0 S CK M ISO M OSI NSS* *NSS is only pinned out in 4-wire S PI m ode S DA S CL CP0 CP0A CP1 CP1A S YSCLK CEX0 CEX1 CEX2 CEX3 CEX4 ECI T0 T1 TX 1** **UA RT1 available only on C8051F340/1/4/5/8/A /B devices RX1** 0 0 1 1 0 0 0 0 1 0 0 P 0SKIP[0:7] 0 0 0 0 0 0 P1S KIP[0:7] 0 0 0 0 0 0 0 0 0 P2SKIP[0:7] Port pin assigned to peripheral by the Crossbar 0 0 0 P3SKIP [0:7] Example: S F Signa ls Special Function Signals are not assigned by the Crossbar. W hen these signals are enabled, the Crossbar must be manually configured to skip their corresponding port pins. 0 XBR0 = 0x07 XBR1 = 0x43 P 0SK IP = 0x0C P 1SK IP = 0x01 Figure 15.5. Crossbar Priority Decoder in Example Configuration (3 Pins Skipped) Registers XBR0, XBR1, and XBR2 are used to assign the digital I/O resources to the physical I/O Port pins. Note that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus (SDA and SCL); when either UART is selected, the Crossbar assigns both pins associated with the UART (TX and RX). UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned to P0.4; UART RX0 is always assigned to P0.5. Standard Port I/Os appear contiguously after the prioritized functions have been assigned. Important Note: The SPI can be operated in either 3-wire or 4-wire modes, depending on the state of the NSSMD1-NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not be routed to a Port pin. Rev. 1.5 146 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 15.2. Port I/O Initialization Port I/O initialization consists of the following steps: Step 1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN). Step 2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port Output Mode register (PnMDOUT). Step 3. Select any pins to be skipped by the I/O Crossbar using the Port Skip registers (PnSKIP). Step 4. Assign Port pins to desired peripherals (XBR0, XBR1). Step 5. Enable the Crossbar (XBARE = ‘1’). All Port pins must be configured as either analog or digital inputs. Any pins to be used as Comparator or ADC inputs should be configured as an analog inputs. When a pin is configured as an analog input, its weak pull-up, digital driver, and digital receiver are disabled. This process saves power and reduces noise on the analog input. Pins configured as digital inputs may still be used by analog peripherals; however this practice is not recommended. To configure a Port pin for digital input, write ‘0’ to the corresponding bit in register PnMDOUT, and write ‘1’ to the corresponding Port latch (register Pn). Additionally, all analog input pins should be configured to be skipped by the Crossbar (accomplished by setting the associated bits in PnSKIP). Port input mode is set in the PnMDIN register, where a ‘1’ indicates a digital input, and a ‘0’ indicates an analog input. All pins default to digital inputs on reset. The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMDOUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is required even for the digital resources selected in the XBRn registers, and is not automatic. The only exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the PnMDOUT settings. When the WEAKPUD bit in XBR1 is ‘0’, a weak pull-up is enabled for all Port I/O configured as open-drain. WEAKPUD does not affect the push-pull Port I/O. Furthermore, the weak pull-up is turned off on an output that is driving a ‘0’ to avoid unnecessary power dissipation. Registers XBR0 and XBR1 must be loaded with the appropriate values to select the digital I/O functions required by the design. Setting the XBARE bit in XBR1 to ‘1’ enables the Crossbar. Until the Crossbar is enabled, the external pins remain as standard Port I/O (in input mode), regardless of the XBRn Register settings. For given XBRn Register settings, one can determine the I/O pin-out using the Priority Decode Table; as an alternative, the Configuration Wizard utility of the Silicon Labs IDE software will determine the Port I/O pin-assignments based on the XBRn Register settings. Important Note: The Crossbar must be enabled to use Ports P0, P1, P2, and P3 as standard Port I/O in output mode. These Port output drivers are disabled while the Crossbar is disabled. Port 4 always functions as standard GPIO. 147 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 15.1. XBR0: Port I/O Crossbar Register 0 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value CP1AE CP1E CP0AE CP0E SYSCKE SMB0E SPI0E URT0E 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xE1 Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: CP1AE: Comparator1 Asynchronous Output Enable 0: Asynchronous CP1 unavailable at Port pin. 1: Asynchronous CP1 routed to Port pin. CP1E: Comparator1 Output Enable 0: CP1 unavailable at Port pin. 1: CP1 routed to Port pin. CP0AE: Comparator0 Asynchronous Output Enable 0: Asynchronous CP0 unavailable at Port pin. 1: Asynchronous CP0 routed to Port pin. CP0E: Comparator0 Output Enable 0: CP0 unavailable at Port pin. 1: CP0 routed to Port pin. SYSCKE: /SYSCLK Output Enable 0: /SYSCLK unavailable at Port pin. 1: /SYSCLK output routed to Port pin. SMB0E: SMBus I/O Enable 0: SMBus I/O unavailable at Port pins. 1: SMBus I/O routed to Port pins. SPI0E: SPI I/O Enable 0: SPI I/O unavailable at Port pins. 1: SPI I/O routed to Port pins. URT0E: UART0 I/O Output Enable 0: UART0 I/O unavailable at Port pins. 1: UART0 TX0, RX0 routed to Port pins P0.4 and P0.5. Rev. 1.5 148 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 15.2. XBR1: Port I/O Crossbar Register 1 R/W R/W R/W R/W R/W WEAKPUD XBARE T1E T0E ECIE Bit7 Bit6 Bit5 Bit4 Bit3 R/W R/W R/W Reset Value Bit0 SFR Address: PCA0ME Bit2 Bit1 00000000 0xE2 Bit7: WEAKPUD: Port I/O Weak Pull-up Disable. 0: Weak Pull-ups enabled (except for Ports whose I/O are configured as analog input or push-pull output). 1: Weak Pull-ups disabled. Bit6: XBARE: Crossbar Enable. 0: Crossbar disabled; all Port drivers disabled. 1: Crossbar enabled. Bit5: T1E: T1 Enable 0: T1 unavailable at Port pin. 1: T1 routed to Port pin. Bit4: T0E: T0 Enable 0: T0 unavailable at Port pin. 1: T0 routed to Port pin. Bit3: ECIE: PCA0 External Counter Input Enable 0: ECI unavailable at Port pin. 1: ECI routed to Port pin. Bits2–0: PCA0ME: PCA Module I/O Enable Bits. 000: All PCA I/O unavailable at Port pins. 001: CEX0 routed to Port pin. 010: CEX0, CEX1 routed to Port pins. 011: CEX0, CEX1, CEX2 routed to Port pins. 100: CEX0, CEX1, CEX2, CEX3 routed to Port pins. 101: CEX0, CEX1, CEX2, CEX3, CEX4 routed to Port pins. 110: Reserved. 111: Reserved. SFR Definition 15.3. XBR2: Port I/O Crossbar Register 2 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Reset Value URT1E 00000000 Bit0 SFR Address: 0xE3 Bits7–1: RESERVED: Always write to 0000000b Bit0: URT1E: UART1 I/O Output Enable (C8051F340/1/4/5/8/A/B Only) 0: UART1 I/O unavailable at Port pins. 1: UART1 TX1, RX1 routed to Port pins. 149 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 15.3. General Purpose Port I/O Port pins that remain unassigned by the Crossbar and are not used by analog peripherals can be used for general purpose I/O. Ports 3-0 are accessed through corresponding special function registers (SFRs) that are both byte addressable and bit addressable. Port 4 (48-pin packages only) uses an SFR which is byte-addressable. When writing to a Port, the value written to the SFR is latched to maintain the output data value at each pin. When reading, the logic levels of the Port's input pins are returned regardless of the XBRn settings (i.e., even when the pin is assigned to another signal by the Crossbar, the Port register can always read its corresponding Port I/O pin). The exception to this is the execution of the read-modify-write instructions. The read-modify-write instructions when operating on a Port SFR are the following: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ and MOV, CLR or SETB, when the destination is an individual bit in a Port SFR. For these instructions, the value of the register (not the pin) is read, modified, and written back to the SFR. SFR Definition 15.4. P0: Port0 Latch R/W R/W R/W R/W R/W R/W R/W R/W P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: (bit addressable) Reset Value 0x80 Bits7–0: P0.[7:0] Write - Output appears on I/O pins per Crossbar Registers (when XBARE = ‘1’). 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P0MDOUT.n bit = 0). Read - Always reads ‘0’ if selected as analog input in register P0MDIN. Directly reads Port pin when configured as digital input. 0: P0.n pin is logic low. 1: P0.n pin is logic high. SFR Definition 15.5. P0MDIN: Port0 Input Mode R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 11111111 0xF1 Bits7–0: Analog Input Configuration Bits for P0.7–P0.0 (respectively). Port pins configured as analog inputs have their weak pull-up, digital driver, and digital receiver disabled. 0: Corresponding P0.n pin is configured as an analog input. 1: Corresponding P0.n pin is not configured as an analog input. Rev. 1.5 150 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 15.6. P0MDOUT: Port0 Output Mode R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xA4 Bits7–0: Output Configuration Bits for P0.7–P0.0 (respectively): ignored if corresponding bit in register P0MDIN is logic 0. 0: Corresponding P0.n Output is open-drain. 1: Corresponding P0.n Output is push-pull. (Note: When SDA and SCL appear on any of the Port I/O, each are open-drain regardless of the value of P0MDOUT). SFR Definition 15.7. P0SKIP: Port0 Skip R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xD4 Bits7–0: P0SKIP[7:0]: Port0 Crossbar Skip Enable Bits. These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as analog inputs (for ADC or Comparator) or used as special functions (VREF input, external oscillator circuit, CNVSTR input) should be skipped by the Crossbar. 0: Corresponding P0.n pin is not skipped by the Crossbar. 1: Corresponding P0.n pin is skipped by the Crossbar. 151 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 15.8. P1: Port1 Latch R/W R/W R/W R/W R/W R/W R/W R/W P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: (bit addressable) Reset Value 0x90 Bits7–0: P1.[7:0] Write - Output appears on I/O pins per Crossbar Registers (when XBARE = ‘1’). 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P1MDOUT.n bit = 0). Read - Always reads ‘0’ if selected as analog input in register P1MDIN. Directly reads Port pin when configured as digital input. 0: P1.n pin is logic low. 1: P1.n pin is logic high. SFR Definition 15.9. P1MDIN: Port1 Input Mode R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 11111111 0xF2 Bits7–0: Analog Input Configuration Bits for P1.7–P1.0 (respectively). Port pins configured as analog inputs have their weak pull-up, digital driver, and digital receiver disabled. 0: Corresponding P1.n pin is configured as an analog input. 1: Corresponding P1.n pin is not configured as an analog input. SFR Definition 15.10. P1MDOUT: Port1 Output Mode R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 00000000 0xA5 Bits7–0: Output Configuration Bits for P1.7–P1.0 (respectively): ignored if corresponding bit in register P1MDIN is logic 0. 0: Corresponding P1.n Output is open-drain. 1: Corresponding P1.n Output is push-pull. Rev. 1.5 152 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 15.11. P1SKIP: Port1 Skip R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xD5 Bits7–0: P1SKIP[7:0]: Port1 Crossbar Skip Enable Bits. These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as analog inputs (for ADC or Comparator) or used as special functions (VREF input, external oscillator circuit, CNVSTR input) should be skipped by the Crossbar. 0: Corresponding P1.n pin is not skipped by the Crossbar. 1: Corresponding P1.n pin is skipped by the Crossbar. SFR Definition 15.12. P2: Port2 Latch R/W R/W R/W R/W R/W R/W R/W R/W P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: (bit addressable) Reset Value 0xA0 Bits7–0: P2.[7:0] Write - Output appears on I/O pins per Crossbar Registers (when XBARE = ‘1’). 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P2MDOUT.n bit = 0). Read - Always reads ‘0’ if selected as analog input in register P2MDIN. Directly reads Port pin when configured as digital input. 0: P2.n pin is logic low. 1: P2.n pin is logic high. SFR Definition 15.13. P2MDIN: Port2 Input Mode R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 11111111 0xF3 Bits7-0: 153 Analog Input Configuration Bits for P2.7-P2.0 (respectively). Port pins configured as analog inputs have their weak pull-up, digital driver, and digital receiver disabled. 0: Corresponding P2.n pin is configured as an analog input. 1: Corresponding P2.n pin is not configured as an analog input. Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 15.14. P2MDOUT: Port2 Output Mode R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xA6 Bits7–0: Output Configuration Bits for P2.7–P2.0 (respectively): ignored if corresponding bit in register P2MDIN is logic 0. 0: Corresponding P2.n Output is open-drain. 1: Corresponding P2.n Output is push-pull. SFR Definition 15.15. P2SKIP: Port2 Skip R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xD6 Bits7–0: P2SKIP[7:0]: Port2 Crossbar Skip Enable Bits. These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as analog inputs (for ADC or Comparator) or used as special functions (VREF input, external oscillator circuit, CNVSTR input) should be skipped by the Crossbar. 0: Corresponding P2.n pin is not skipped by the Crossbar. 1: Corresponding P2.n pin is skipped by the Crossbar. Rev. 1.5 154 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 15.16. P3: Port3 Latch R/W R/W R/W R/W R/W R/W R/W R/W P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: (bit addressable) Reset Value 0xB0 Bits7–0: P3.[7:0] Write - Output appears on I/O pins. 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P3MDOUT.n bit = 0). Read - Always reads ‘0’ if selected as analog input in register P3MDIN. Directly reads Port pin when configured as digital input. 0: P3.n pin is logic low. 1: P3.n pin is logic high. Note: P3.1–3.7 are only available on 48-pin devices. SFR Definition 15.17. P3MDIN: Port3 Input Mode R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 11111111 0xF4 Bits7–0: Analog Input Configuration Bits for P3.7–P3.0 (respectively). Port pins configured as analog inputs have their weak pull-up, digital driver, and digital receiver disabled. 0: Corresponding P3.n pin is configured as an analog input. 1: Corresponding P3.n pin is not configured as an analog input. Note: P3.1–3.7 are only available on 48-pin devices. SFR Definition 15.18. P3MDOUT: Port3 Output Mode R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xA7 Bits7–0: Output Configuration Bits for P3.7–P3.0 (respectively); ignored if corresponding bit in register P3MDIN is logic 0. 0: Corresponding P3.n Output is open-drain. 1: Corresponding P3.n Output is push-pull. Note: P3.1–3.7 are only available on 48-pin devices. 155 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 15.19. P3SKIP: Port3 Skip R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xDF Bits7–0: P3SKIP[3:0]: Port3 Crossbar Skip Enable Bits. These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as analog inputs (for ADC or Comparator) or used as special functions (VREF input, external oscillator circuit, CNVSTR input) should be skipped by the Crossbar. 0: Corresponding P3.n pin is not skipped by the Crossbar. 1: Corresponding P3.n pin is skipped by the Crossbar. Note: P3.1–3.7 are only available on 48-pin devices. SFR Definition 15.20. P4: Port4 Latch R/W R/W R/W R/W R/W R/W R/W R/W P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0 Reset Value 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xC7 Bits7–0: P4.[7:0] Write - Output appears on I/O pins. 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P4MDOUT.n bit = 0). Read - Always reads ‘0’ if selected as analog input in register P4MDIN. Directly reads Port pin when configured as digital input. 0: P4.n pin is logic low. 1: P4.n pin is logic high. Note: P4 is only available on 48-pin devices. Rev. 1.5 156 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 15.21. P4MDIN: Port4 Input Mode R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xF5 Bits7–0: Analog Input Configuration Bits for P4.7–P4.0 (respectively). Port pins configured as analog inputs have their weak pull-up, digital driver, and digital receiver disabled. 0: Corresponding P4.n pin is configured as an analog input. 1: Corresponding P4.n pin is not configured as an analog input. Note: P4 is only available on 48-pin devices. SFR Definition 15.22. P4MDOUT: Port4 Output Mode R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xAE Bits7–0: Output Configuration Bits for P4.7–P4.0 (respectively); ignored if corresponding bit in register P4MDIN is logic 0. 0: Corresponding P4.n Output is open-drain. 1: Corresponding P4.n Output is push-pull. Note: P4 is only available on 48-pin devices. 157 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 15.1. Port I/O DC Electrical Characteristics VDD = 2.7 to 3.6 V, –40 to +85 °C unless otherwise specified Parameters Conditions Min IOH = –3 mA, Port I/O push-pull VDD – 0.7 Output High Voltage IOH = –10 µA, Port I/O push-pull Units V VDD – 0.8 0.6 IOL = 10 µA 0.1 V 1.0 IOL = 25 mA Input High Voltage Input Low Voltage Input Leakage Current Max VDD – 0.1 IOH = –10 mA, Port I/O push-pull IOL = 8.5 mA Output Low Voltage Typ 2.0 0.8 ±1 Weak Pull-up Off Weak Pull-up On, VIN = 0 V Rev. 1.5 25 50 V V µA 158 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 16. Universal Serial Bus Controller (USB0) C8051F34x devices include a complete Full/Low Speed USB function for USB peripheral implementations*. The USB Function Controller (USB0) consists of a Serial Interface Engine (SIE), USB Transceiver (including matching resistors and configurable pull-up resistors), 1k FIFO block, and clock recovery mechanism for crystal-less operation. No external components are required. The USB Function Controller and Transceiver is Universal Serial Bus Specification 2.0 compliant. Transceiver Serial Interface Engine (SIE) Endpoint0 VDD IN/OUT D+ Data Transfer Control D- Endpoint1 Endpoint2 Endpoint3 OUT IN IN USB Control, Status, and Interrupt Registers CIP-51 Core OUT IN OUT USB FIFOs (1k RAM) Figure 16.1. USB0 Block Diagram Important Note: This document assumes a comprehensive understanding of the USB Protocol. Terms and abbreviations used in this document are defined in the USB Specification. We encourage you to review the latest version of the USB Specification before proceeding. *Note: The C8051F34x cannot be used as a USB Host device. Rev. 1.5 159 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 16.1. Endpoint Addressing A total of eight endpoint pipes are available. The control endpoint (Endpoint0) always functions as a bi-directional IN/OUT endpoint. The other endpoints are implemented as three pairs of IN/OUT endpoint pipes: Table 16.1. Endpoint Addressing Scheme Endpoint Endpoint0 Endpoint1 Endpoint2 Endpoint3 Associated Pipes Endpoint0 IN Endpoint0 OUT Endpoint1 IN Endpoint1 OUT Endpoint2 IN Endpoint2 OUT Endpoint3 IN Endpoint3 OUT USB Protocol Address 0x00 0x00 0x81 0x01 0x82 0x02 0x83 0x03 16.2. USB Transceiver The USB Transceiver is configured via the USB0XCN register shown in SFR Definition 16.1. This configuration includes Transceiver enable/disable, pull-up resistor enable/disable, and device speed selection (Full or Low Speed). When bit SPEED = ‘1’, USB0 operates as a Full Speed USB function, and the on-chip pull-up resistor (if enabled) appears on the D+ pin. When bit SPEED = ‘0’, USB0 operates as a Low Speed USB function, and the on-chip pull-up resistor (if enabled) appears on the D- pin. Bits4-0 of register USB0XCN can be used for Transceiver testing as described in SFR Definition 16.1. The pull-up resistor is enabled only when VBUS is present (see Section “8.2. VBUS Detection” on page 69 for details on VBUS detection). Important Note: The USB clock should be active before the Transceiver is enabled. 160 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 16.1. USB0XCN: USB0 Transceiver Control R/W R/W R/W PREN PHYEN SPEED Bit7 Bit6 Bit5 R/W R/W PHYTST1 PHYTST0 Bit4 R R R Reset Value DFREC Dp Dn 00000000 Bit2 Bit1 Bit0 SFR Address: Bit3 0xD7 Bit7: PREN: Internal Pull-up Resistor Enable The location of the pull-up resistor (D+ or D–) is determined by the SPEED bit. 0: Internal pull-up resistor disabled (device effectively detached from the USB network). 1: Internal pull-up resistor enabled when VBUS is present (device attached to the USB network). Bit6: PHYEN: Physical Layer Enable This bit enables/disables the USB0 physical layer transceiver. 0: Transceiver disabled (suspend). 1: Transceiver enabled (normal). Bit5: SPEED: USB0 Speed Select This bit selects the USB0 speed. 0: USB0 operates as a Low Speed device. If enabled, the internal pull-up resistor appears on the D– line. 1: USB0 operates as a Full Speed device. If enabled, the internal pull-up resistor appears on the D+ line. Bits4–3: PHYTST1–0: Physical Layer Test These bits can be used to test the USB0 transceiver. PHYTST[1:0] 00b 01b 10b 11b Bit2: Bit1: Bit0: Mode Mode 0: Normal (non-test mode) Mode 1: Differential ‘1’ Forced Mode 2: Differential ‘0’ Forced Mode 3: Single-Ended ‘0’ Forced D+ X 1 0 0 D– X 0 1 0 DFREC: Differential Receiver The state of this bit indicates the current differential value present on the D+ and D– lines when PHYEN = ‘1’. 0: Differential ‘0’ signaling on the bus. 1: Differential ‘1’ signaling on the bus. Dp: D+ Signal Status This bit indicates the current logic level of the D+ pin. 0: D+ signal currently at logic 0. 1: D+ signal currently at logic 1. Dn: D- Signal Status This bit indicates the current logic level of the D– pin. 0: D– signal currently at logic 0. 1: D– signal currently at logic 1. Rev. 1.5 161 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 16.3. USB Register Access The USB0 controller registers listed in Table 16.2 are accessed through two SFRs: USB0 Address (USB0ADR) and USB0 Data (USB0DAT). The USB0ADR register selects which USB register is targeted by reads/writes of the USB0DAT register. See Figure 16.2. Endpoint control/status registers are accessed by first writing the USB register INDEX with the target endpoint number. Once the target endpoint number is written to the INDEX register, the control/status registers associated with the target endpoint may be accessed. See the “Indexed Registers” section of Table 16.2 for a list of endpoint control/status registers. Important Note: The USB clock must be active when accessing USB registers. 8051 SFRs USB Controller Interrupt Registers FIFO Access Common Registers Index Register USB0DAT Endpoint0 Control/ Status Registers Endpoint1 Control/ Status Registers Endpoint2 Control/ Status Registers USB0ADR Endpoint3 Control/ Status Registers Figure 16.2. USB0 Register Access Scheme 162 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 16.2. USB0ADR: USB0 Indirect Address R/W R/W BUSY AUTORD Bit7 Bit6 R/W R/W R/W Bit5 Bit4 Bit3 R/W R/W R/W Reset Value Bit1 Bit0 SFR Address: USBADDR Bit2 00000000 0x96 Bits7: BUSY: USB0 Register Read Busy Flag This bit is used during indirect USB0 register accesses. Software should write ‘1’ to this bit to initiate a read of the USB0 register targeted by the USBADDR bits (USB0ADR.[5-0]). The target address and BUSY bit may be written in the same write to USB0ADR. After BUSY is set to ‘1’, hardware will clear BUSY when the targeted register data is ready in the USB0DAT register. Software should check BUSY for ‘0’ before writing to USB0DAT. Write: 0: No effect. 1: A USB0 indirect register read is initiated at the address specified by the USBADDR bits. Read: 0: USB0DAT register data is valid. 1: USB0 is busy accessing an indirect register; USB0DAT register data is invalid. Bit6: AUTORD: USB0 Register Auto-read Flag This bit is used for block FIFO reads. 0: BUSY must be written manually for each USB0 indirect register read. 1: The next indirect register read will automatically be initiated when software reads USB0DAT (USBADDR bits will not be changed). Bits5–0: USBADDR: USB0 Indirect Register Address These bits hold a 6-bit address used to indirectly access the USB0 core registers. Table 16.2 lists the USB0 core registers and their indirect addresses. Reads and writes to USB0DAT will target the register indicated by the USBADDR bits. Rev. 1.5 163 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 16.3. USB0DAT: USB0 Data R/W R/W R/W R/W Bit7 Bit6 Bit5 Bit4 R/W R/W R/W R/W Reset Value Bit2 Bit1 Bit0 SFR Address: USB0DAT Bit3 00000000 0x97 This SFR is used to indirectly read and write USB0 registers. Write Procedure: 1. Poll for BUSY (USB 0ADR.7) => ‘0’. 2. Load the target USB0 register address into the USBADDR bits in register USB0ADR. 3. Write data to USB0DAT. 4. Repeat (Step 2 may be skipped when writing to the same USB0 register). Read Procedure: 1. Poll for BUSY (USB 0ADR.7) => ‘0’. 2. Load the target USB0 register address into the USBADDR bits in register USB0ADR. 3. Write ‘1’ to the BUSY bit in register USB0ADR (steps 2 and 3 can be performed in the same write). 4. Poll for BUSY (USB 0ADR.7) => ‘0’. 5. Read data from USB0DAT. 6. Repeat from Step 2 (Step 2 may be skipped when reading the same USB0 register; Step 3 may be skipped when the AUTORD bit (USB0ADR.6) is logic 1). 164 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 16.2. USB0 Controller Registers USB Register Name USB Register Address IN1INT OUT1INT CMINT IN1IE OUT1IE CMIE 0x02 0x04 0x06 0x07 0x09 0x0B FADDR POWER FRAMEL FRAMEH INDEX CLKREC FIFOn 0x00 0x01 0x0C 0x0D 0x0E 0x0F 0x20–0x23 E0CSR EINCSRL EINCSRH EOUTCSRL EOUTCSRH E0CNT EOUTCNTL EOUTCNTH 0x11 0x12 0x14 0x15 0x16 0x17 Description Page Number Interrupt Registers Endpoint0 and Endpoints1-3 IN Interrupt Flags Endpoints1-3 OUT Interrupt Flags Common USB Interrupt Flags Endpoint0 and Endpoints1-3 IN Interrupt Enables Endpoints1-3 OUT Interrupt Enables Common USB Interrupt Enables Common Registers Function Address Power Management Frame Number Low Byte Frame Number High Byte Endpoint Index Selection Clock Recovery Control Endpoints0-3 FIFOs Indexed Registers Endpoint0 Control / Status Endpoint IN Control / Status Low Byte Endpoint IN Control / Status High Byte Endpoint OUT Control / Status Low Byte Endpoint OUT Control / Status High Byte Number of Received Bytes in Endpoint0 FIFO Endpoint OUT Packet Count Low Byte Endpoint OUT Packet Count High Byte 173 173 174 175 175 176 169 171 172 172 165 166 168 179 182 183 185 186 180 186 186 USB Register Definition 16.4. INDEX: USB0 Endpoint Index R R R R - - - - Bit7 Bit6 Bit5 Bit4 R/W R/W R/W R/W EPSEL Bit3 Bit2 Reset Value 00000000 Bit1 Bit0 USB Address: 0x0E Bits7–4: Unused. Read = 0000b; Write = don’t care. Bits3–0: EPSEL: Endpoint Select These bits select which endpoint is targeted when indexed USB0 registers are accessed. INDEX 0x0 0x1 0x2 0x3 0x4–0xF Target Endpoint 0 1 2 3 Reserved Rev. 1.5 165 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 16.4. USB Clock Configuration USB0 is capable of communication as a Full or Low Speed USB function. Communication speed is selected via the SPEED bit in SFR USB0XCN. When operating as a Low Speed function, the USB0 clock must be 6 MHz. When operating as a Full Speed function, the USB0 clock must be 48 MHz. Clock options are described in Section “14. Oscillators” on page 131. The USB0 clock is selected via SFR CLKSEL (see SFR Definition 14.6). Clock Recovery circuitry uses the incoming USB data stream to adjust the internal oscillator; this allows the internal oscillator (and 4x Clock Multiplier) to meet the requirements for USB clock tolerance. Clock Recovery should be used in the following configurations: Communication Speed Full Speed Low Speed USB Clock 4x Clock Multiplier Internal Oscillator / 2 4x Clock Multiplier Input Internal Oscillator N/A When operating USB0 as a Low Speed function with Clock Recovery, software must write ‘1’ to the CRLOW bit to enable Low Speed Clock Recovery. Clock Recovery is typically not necessary in Low Speed mode. Single Step Mode can be used to help the Clock Recovery circuitry to lock when high noise levels are present on the USB network. This mode is not required (or recommended) in typical USB environments. USB Register Definition 16.5. CLKREC: Clock Recovery Control R/W R/W R/W CRE CRSSEN CRLOW Bit7 Bit6 Bit5 R/W R/W Bit4 Bit3 R/W R/W R/W Reset Value Bit1 Bit0 USB Address: Reserved Bit2 00001001 0x0F Bit7: CRE: Clock Recovery Enable. This bit enables/disables the USB clock recovery feature. 0: Clock recovery disabled. 1: Clock recovery enabled. Bit6: CRSSEN: Clock Recovery Single Step. This bit forces the oscillator calibration into ‘single-step’ mode during clock recovery. 0: Normal calibration mode. 1: Single step mode. Bit5: CRLOW: Low Speed Clock Recovery Mode. This bit must be set to ‘1’ if clock recovery is used when operating as a Low Speed USB device. 0: Full Speed Mode. 1: Low Speed Mode. Bits4–0: Reserved. Read = Variable. Must Write = 01001b. Note: The USB transceiver must be enabled before enabling Clock Recovery. 166 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 16.5. FIFO Management 1024 bytes of on-chip XRAM are used as FIFO space for USB0. This FIFO space is split between Endpoints0-3 as shown in Figure 16.3. FIFO space allocated for Endpoints1-3 is configurable as IN, OUT, or both (Split Mode: half IN, half OUT). 0x07FF Endpoint0 (64 bytes) 0x07C0 0x07BF Endpoint1 (128 bytes) 0x0740 0x073F Configurable as IN, OUT, or both (Split Mode) Endpoint2 (256 bytes) 0x0640 0x063F Endpoint3 (512 bytes) 0x0440 0x043F Free (64 bytes) 0x0400 USB Clock Domain System Clock Domain 0x03FF User XRAM (1024 bytes) 0x0000 Figure 16.3. USB FIFO Allocation 16.5.1. FIFO Split Mode The FIFO space for Endpoints1-3 can be split such that the upper half of the FIFO space is used by the IN endpoint, and the lower half is used by the OUT endpoint. For example: if the Endpoint3 FIFO is configured for Split Mode, the upper 256 bytes (0x0540 to 0x063F) are used by Endpoint3 IN and the lower 256 bytes (0x0440 to 0x053F) are used by Endpoint3 OUT. If an endpoint FIFO is not configured for Split Mode, that endpoint IN/OUT pair’s FIFOs are combined to form a single IN or OUT FIFO. In this case only one direction of the endpoint IN/OUT pair may be used at a time. The endpoint direction (IN/OUT) is determined by the DIRSEL bit in the corresponding endpoint’s EINCSRH register (see SFR Definition 16.20). Rev. 1.5 167 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 16.5.2. FIFO Double Buffering FIFO slots for Endpoints1-3 can be configured for double-buffered mode. In this mode, the maximum packet size is halved and the FIFO may contain two packets at a time. This mode is available for Endpoints1-3. When an endpoint is configured for Split Mode, double buffering may be enabled for the IN Endpoint and/or the OUT endpoint. When Split Mode is not enabled, double-buffering may be enabled for the entire endpoint FIFO. See Table 16.3 for a list of maximum packet sizes for each FIFO configuration. Table 16.3. FIFO Configurations Endpoint Number Split Mode Enabled? 0 N/A N Y N Y N Y 1 2 3 Maximum IN Packet Size (Double Buffer Disabled / Enabled) Maximum OUT Packet Size (Double Buffer Disabled / Enabled) 64 128 / 64 64 / 32 64 / 32 256 / 128 128 / 64 128 / 64 512 / 256 256 / 128 256 / 128 16.5.1. FIFO Access Each endpoint FIFO is accessed through a corresponding FIFOn register. A read of an endpoint FIFOn register unloads one byte from the FIFO; a write of an endpoint FIFOn register loads one byte into the endpoint FIFO. When an endpoint FIFO is configured for Split Mode, a read of the endpoint FIFOn register unloads one byte from the OUT endpoint FIFO; a write of the endpoint FIFOn register loads one byte into the IN endpoint FIFO. USB Register Definition 16.6. FIFOn: USB0 Endpoint FIFO Access R/W R/W R/W R/W R/W R/W R/W R/W FIFODATA Bit7 Bit6 Bit5 Bit4 Bit3 Reset Value 00000000 Bit2 Bit1 Bit0 USB Address: 0x20 - 0x23 USB Addresses 0x20–0x23 provide access to the 4 pairs of endpoint FIFOs: IN/OUT Endpoint FIFO 0 1 2 3 USB Address 0x20 0x21 0x22 0x23 Writing to the FIFO address loads data into the IN FIFO for the corresponding endpoint. Reading from the FIFO address unloads data from the OUT FIFO for the corresponding endpoint. 168 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 16.6. Function Addressing The FADDR register holds the current USB0 function address. Software should write the host-assigned 7-bit function address to the FADDR register when received as part of a SET_ADDRESS command. A new address written to FADDR will not take effect (USB0 will not respond to the new address) until the end of the current transfer (typically following the status phase of the SET_ADDRESS command transfer). The UPDATE bit (FADDR.7) is set to ‘1’ by hardware when software writes a new address to the FADDR register. Hardware clears the UPDATE bit when the new address takes effect as described above. USB Register Definition 16.7. FADDR: USB0 Function Address R R/W R/W R/W Bit6 Bit5 Bit4 Update Bit7 R/W R/W R/W R/W Reset Value Bit2 Bit1 Bit0 USB Address: Function Address Bit3 00000000 0x00 Bit7: Update: Function Address Update Set to ‘1’ when software writes the FADDR register. USB0 clears this bit to ‘0’ when the new address takes effect. 0: The last address written to FADDR is in effect. 1: The last address written to FADDR is not yet in effect. Bits6–0: Function Address Holds the 7-bit function address for USB0. This address should be written by software when the SET_ADDRESS standard device request is received on Endpoint0. The new address takes effect when the device request completes. 16.7. Function Configuration and Control The USB register POWER (SFR Definition 16.8) is used to configure and control USB0 at the device level (enable/disable, Reset/Suspend/Resume handling, etc.). USB Reset: The USBRST bit (POWER.3) is set to ‘1’ by hardware when Reset signaling is detected on the bus. Upon this detection, the following occur: 1. The USB0 Address is reset (FADDR = 0x00). 2. Endpoint FIFOs are flushed. 3. Control/status registers are reset to 0x00 (E0CSR, EINCSRL, EINCSRH, EOUTCSRL, EOUTCSRH). 4. USB register INDEX is reset to 0x00. 5. All USB interrupts (excluding the Suspend interrupt) are enabled and their corresponding flags cleared. 6. A USB Reset interrupt is generated if enabled. Writing a ‘1’ to the USBRST bit will generate an asynchronous USB0 reset. All USB registers are reset to their default values following this asynchronous reset. Suspend Mode: With Suspend Detection enabled (SUSEN = ‘1’), USB0 will enter Suspend Mode when Suspend signaling is detected on the bus. An interrupt will be generated if enabled (SUSINTE = ‘1’). The Suspend Interrupt Service Routine (ISR) should perform application-specific configuration tasks such as disabling appropriate peripherals and/or configuring clock sources for low power modes. See Section Rev. 1.5 169 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D “14. Oscillators” on page 131 for more details on internal oscillator configuration, including the Suspend mode feature of the internal oscillator. USB0 exits Suspend mode when any of the following occur: (1) Resume signaling is detected or generated, (2) Reset signaling is detected, or (3) a device or USB reset occurs. If suspended, the internal oscillator will exit Suspend mode upon any of the above listed events. Resume Signaling: USB0 will exit Suspend mode if Resume signaling is detected on the bus. A Resume interrupt will be generated upon detection if enabled (RESINTE = ‘1’). Software may force a Remote Wakeup by writing ‘1’ to the RESUME bit (POWER.2). When forcing a Remote Wakeup, software should write RESUME = ‘0’ to end Resume signaling 10-15 ms after the Remote Wakeup is initiated (RESUME = ‘1’). ISO Update: When software writes ‘1’ to the ISOUP bit (POWER.7), the ISO Update function is enabled. With ISO Update enabled, new packets written to an ISO IN endpoint will not be transmitted until a new Start-Of-Frame (SOF) is received. If the ISO IN endpoint receives an IN token before a SOF, USB0 will transmit a zero-length packet. When ISOUP = ‘1’, ISO Update is enabled for all ISO endpoints. USB Enable: USB0 is disabled following a Power-On-Reset (POR). USB0 is enabled by clearing the USBINH bit (POWER.4). Once written to ‘0’, the USBINH can only be set to ‘1’ by one of the following: (1) a Power-On-Reset (POR), or (2) an asynchronous USB0 reset generated by writing ‘1’ to the USBRST bit (POWER.3). Software should perform all USB0 configuration before enabling USB0. The configuration sequence should be performed as follows: Step 1. Step 2. Step 3. Step 4. Step 5. 170 Select and enable the USB clock source. Reset USB0 by writing USBRST= ‘1’. Configure and enable the USB Transceiver. Perform any USB0 function configuration (interrupts, Suspend detect). Enable USB0 by writing USBINH = ‘0’. Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D USB Register Definition 16.8. POWER: USB0 Power R/W R/W R/W R/W ISOUD - - USBINH Bit7 Bit6 Bit5 Bit4 R/W R/W USBRST RESUME Bit3 Bit2 R R/W Reset Value SUSMD SUSEN 00010000 Bit1 Bit0 USB Address: 0x01 Bit7: ISOUD: ISO Update This bit affects all IN Isochronous endpoints. 0: When software writes INPRDY = ‘1’, USB0 will send the packet when the next IN token is received. 1: When software writes INPRDY = ‘1’, USB0 will wait for a SOF token before sending the packet. If an IN token is received before a SOF token, USB0 will send a zero-length data packet. Bits6–5: Unused. Read = 00b. Write = don’t care. Bit4: USBINH: USB0 Inhibit This bit is set to ‘1’ following a power-on reset (POR) or an asynchronous USB0 reset (see Bit3: RESET). Software should clear this bit after all USB0 and transceiver initialization is complete. Software cannot set this bit to ‘1’. 0: USB0 enabled. 1: USB0 inhibited. All USB traffic is ignored. Bit3: USBRST: Reset Detect Writing ‘1’ to this bit forces an asynchronous USB0 reset. Reading this bit provides bus reset status information. Read: 0: Reset signaling is not present on the bus. 1: Reset signaling detected on the bus. Bit2: RESUME: Force Resume Software can force resume signaling on the bus to wake USB0 from suspend mode. Writing a ‘1’ to this bit while in Suspend mode (SUSMD = ‘1’) forces USB0 to generate Resume signaling on the bus (a remote Wakeup event). Software should write RESUME = ‘0’ after 10 ms to15 ms to end the Resume signaling. An interrupt is generated, and hardware clears SUSMD, when software writes RESUME = ‘0’. Bit1: SUSMD: Suspend Mode Set to ‘1’ by hardware when USB0 enters suspend mode. Cleared by hardware when software writes RESUME = ‘0’ (following a remote wakeup) or reads the CMINT register after detection of Resume signaling on the bus. 0: USB0 not in suspend mode. 1: USB0 in suspend mode. Bit0: SUSEN: Suspend Detection Enable 0: Suspend detection disabled. USB0 will ignore suspend signaling on the bus. 1: Suspend detection enabled. USB0 will enter suspend mode if it detects suspend signaling on the bus. Rev. 1.5 171 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D USB Register Definition 16.9. FRAMEL: USB0 Frame Number Low R R R R R R R R Frame Number Low Bit7 Bit6 Bit5 Bit4 Bit3 Reset Value 00000000 Bit2 Bit1 Bit0 USB Address: 0x0C Bits7-0: Frame Number Low This register contains bits7-0 of the last received frame number. USB Register Definition 16.10. FRAMEH: USB0 Frame Number High R R R R R - - - - - Bit7 Bit6 Bit5 Bit4 Bit3 R R R Frame Number High Bit2 Bit1 Bit0 Reset Value 00000000 USB Address: 0x0D Bits7-3: Bits2-0: Unused. Read = 0. Write = don’t care. Frame Number High Byte This register contains bits10-8 of the last received frame number. 16.8. Interrupts The read-only USB0 interrupt flags are located in the USB registers shown in USB Register Definition 16.11 through USB Register Definition 16.13. The associated interrupt enable bits are located in the USB registers shown in USB Register Definition 16.14 through USB Register Definition 16.16. A USB0 interrupt is generated when any of the USB interrupt flags is set to ‘1’. The USB0 interrupt is enabled via the EIE1 SFR (see Section “9.3. Interrupt Handler” on page 88). Important Note: Reading a USB interrupt flag register resets all flags in that register to ‘0’. 172 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D USB Register Definition 16.11. IN1INT: USB0 IN Endpoint Interrupt R R R R R R R R Reset Value - - - - IN3 IN2 IN1 EP0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USB Address: 0x02 Bits7–4: Unused. Read = 0000b. Write = don’t care. Bit3: IN3: IN Endpoint 3 Interrupt-pending Flag This bit is cleared when software reads the IN1INT register. 0: IN Endpoint 3 interrupt inactive. 1: IN Endpoint 3 interrupt active. Bit2: IN2: IN Endpoint 2 Interrupt-pending Flag This bit is cleared when software reads the IN1INT register. 0: IN Endpoint 2 interrupt inactive. 1: IN Endpoint 2 interrupt active. Bit1: IN1: IN Endpoint 1 Interrupt-pending Flag This bit is cleared when software reads the IN1INT register. 0: IN Endpoint 1 interrupt inactive. 1: IN Endpoint 1 interrupt active. Bit0: EP0: Endpoint 0 Interrupt-pending Flag This bit is cleared when software reads the IN1INT register. 0: Endpoint 0 interrupt inactive. 1: Endpoint 0 interrupt active. USB Register Definition 16.12. OUT1INT: USB0 Out Endpoint Interrupt R R R R R R R R Reset Value - - - - OUT3 OUT2 OUT1 - 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USB Address: 0x04 Bits7–4: Unused. Read = 0000b. Write = don’t care. Bit3: OUT3: OUT Endpoint 3 Interrupt-pending Flag This bit is cleared when software reads the OUT1INT register. 0: OUT Endpoint 3 interrupt inactive. 1: OUT Endpoint 3 interrupt active. Bit2: OUT2: OUT Endpoint 2 Interrupt-pending Flag This bit is cleared when software reads the OUT1INT register. 0: OUT Endpoint 2 interrupt inactive. 1: OUT Endpoint 2 interrupt active. Bit1: OUT1: OUT Endpoint 1 Interrupt-pending Flag This bit is cleared when software reads the OUT1INT register. 0: OUT Endpoint 1 interrupt inactive. 1: OUT Endpoint 1 interrupt active. Bit0: Unused. Read = 0; Write = don’t care. Rev. 1.5 173 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D USB Register Definition 16.13. CMINT: USB0 Common Interrupt R R R R R R R R Reset Value - - - - SOF RSTINT RSUINT SUSINT 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USB Address: 0x06 Bits7–4: Unused. Read = 0000b; Write = don’t care. Bit3: SOF: Start of Frame Interrupt Set by hardware when a SOF token is received. This interrupt event is synthesized by hardware: an interrupt will be generated when hardware expects to receive a SOF event, even if the actual SOF signal is missed or corrupted. This bit is cleared when software reads the CMINT register. 0: SOF interrupt inactive. 1: SOF interrupt active. Bit2: RSTINT: Reset Interrupt-pending Flag Set by hardware when Reset signaling is detected on the bus. This bit is cleared when software reads the CMINT register. 0: Reset interrupt inactive. 1: Reset interrupt active. Bit1: RSUINT: Resume Interrupt-pending Flag Set by hardware when Resume signaling is detected on the bus while USB0 is in suspend mode. This bit is cleared when software reads the CMINT register. 0: Resume interrupt inactive. 1: Resume interrupt active. Bit0: SUSINT: Suspend Interrupt-pending Flag When Suspend detection is enabled (bit SUSEN in register POWER), this bit is set by hardware when Suspend signaling is detected on the bus. This bit is cleared when software reads the CMINT register. 0: Suspend interrupt inactive. 1: Suspend interrupt active. 174 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D USB Register Definition 16.14. IN1IE: USB0 IN Endpoint Interrupt Enable R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - - - - IN3E IN2E IN1E EP0E 00001111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USB Address: 0x07 Bits7–4: Unused. Read = 0000b. Write = don’t care. Bit3: IN3E: IN Endpoint 3 Interrupt Enable 0: IN Endpoint 3 interrupt disabled. 1: IN Endpoint 3 interrupt enabled. Bit2: IN2E: IN Endpoint 2 Interrupt Enable 0: IN Endpoint 2 interrupt disabled. 1: IN Endpoint 2 interrupt enabled. Bit1: IN1E: IN Endpoint 1 Interrupt Enable 0: IN Endpoint 1 interrupt disabled. 1: IN Endpoint 1 interrupt enabled. Bit0: EP0E: Endpoint 0 Interrupt Enable 0: Endpoint 0 interrupt disabled. 1: Endpoint 0 interrupt enabled. USB Register Definition 16.15. OUT1IE: USB0 Out Endpoint Interrupt Enable R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - - - - OUT3E OUT2E OUT1E - 00001110 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USB Address: 0x09 Bits7–4: Unused. Read = 0000b. Write = don’t care. Bit3: OUT3E: OUT Endpoint 3 Interrupt Enable 0: OUT Endpoint 3 interrupt disabled. 1: OUT Endpoint 3 interrupt enabled. Bit2: OUT2E: OUT Endpoint 2 Interrupt Enable 0: OUT Endpoint 2 interrupt disabled. 1: OUT Endpoint 2 interrupt enabled. Bit1: OUT1E: OUT Endpoint 1 Interrupt Enable 0: OUT Endpoint 1 interrupt disabled. 1: OUT Endpoint 1 interrupt enabled. Bit0: Unused. Read = 0; Write = don’t’ care. Rev. 1.5 175 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D USB Register Definition 16.16. CMIE: USB0 Common Interrupt Enable R/W R/W R/W R/W R/W - - - - SOFE Bit7 Bit6 Bit5 Bit4 Bit3 R/W R/W R/W Reset Value RSTINTE RSUINTE SUSINTE 00000110 Bit2 Bit1 Bit0 USB Address: 0x0B Bits7–4: Unused. Read = 0000b; Write = don’t care. Bit3: SOFE: Start of Frame Interrupt Enable 0: SOF interrupt disabled. 1: SOF interrupt enabled. Bit2: RSTINTE: Reset Interrupt Enable 0: Reset interrupt disabled. 1: Reset interrupt enabled. Bit1: RSUINTE: Resume Interrupt Enable 0: Resume interrupt disabled. 1: Resume interrupt enabled. Bit0: SUSINTE: Suspend Interrupt Enable 0: Suspend interrupt disabled. 1: Suspend interrupt enabled. 16.9. The Serial Interface Engine The Serial Interface Engine (SIE) performs all low level USB protocol tasks, interrupting the processor when data has successfully been transmitted or received. When receiving data, the SIE will interrupt the processor when a complete data packet has been received; appropriate handshaking signals are automatically generated by the SIE. When transmitting data, the SIE will interrupt the processor when a complete data packet has been transmitted and the appropriate handshake signal has been received. The SIE will not interrupt the processor when corrupted/erroneous packets are received. 16.10. Endpoint0 Endpoint0 is managed through the USB register E0CSR (USB Register Definition 16.17). The INDEX register must be loaded with 0x00 to access the E0CSR register. An Endpoint0 interrupt is generated when: 1. A data packet (OUT or SETUP) has been received and loaded into the Endpoint0 FIFO. The OPRDY bit (E0CSR.0) is set to ‘1’ by hardware. 2. An IN data packet has successfully been unloaded from the Endpoint0 FIFO and transmitted to the host; INPRDY is reset to ‘0’ by hardware. 3. An IN transaction is completed (this interrupt generated during the status stage of the transaction). 4. Hardware sets the STSTL bit (E0CSR.2) after a control transaction ended due to a protocol violation. 5. Hardware sets the SUEND bit (E0CSR.4) because a control transfer ended before firmware sets the DATAEND bit (E0CSR.3). 176 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D The E0CNT register (USB Register Definition 16.18) holds the number of received data bytes in the Endpoint0 FIFO. Hardware will automatically detect protocol errors and send a STALL condition in response. Firmware may force a STALL condition to abort the current transfer. When a STALL condition is generated, the STSTL bit will be set to ‘1’ and an interrupt generated. The following conditions will cause hardware to generate a STALL condition: 1. The host sends an OUT token during a OUT data phase after the DATAEND bit has been set to ‘1’. 2. The host sends an IN token during an IN data phase after the DATAEND bit has been set to ‘1’. 3. The host sends a packet that exceeds the maximum packet size for Endpoint0. 4. The host sends a non-zero length DATA1 packet during the status phase of an IN transaction. 5. Firmware sets the SDSTL bit (E0CSR.5) to ‘1’. 16.10.1.Endpoint0 SETUP Transactions All control transfers must begin with a SETUP packet. SETUP packets are similar to OUT packets, containing an 8-byte data field sent by the host. Any SETUP packet containing a command field of anything other than 8 bytes will be automatically rejected by USB0. An Endpoint0 interrupt is generated when the data from a SETUP packet is loaded into the Endpoint0 FIFO. Software should unload the command from the Endpoint0 FIFO, decode the command, perform any necessary tasks, and set the SOPRDY bit to indicate that it has serviced the OUT packet. 16.10.2.Endpoint0 IN Transactions When a SETUP request is received that requires USB0 to transmit data to the host, one or more IN requests will be sent by the host. For the first IN transaction, firmware should load an IN packet into the Endpoint0 FIFO, and set the INPRDY bit (E0CSR.1). An interrupt will be generated when an IN packet is transmitted successfully. Note that no interrupt will be generated if an IN request is received before firmware has loaded a packet into the Endpoint0 FIFO. If the requested data exceeds the maximum packet size for Endpoint0 (as reported to the host), the data should be split into multiple packets; each packet should be of the maximum packet size excluding the last (residual) packet. If the requested data is an integer multiple of the maximum packet size for Endpoint0, the last data packet should be a zero-length packet signaling the end of the transfer. Firmware should set the DATAEND bit to ‘1’ after loading into the Endpoint0 FIFO the last data packet for a transfer. Upon reception of the first IN token for a particular control transfer, Endpoint0 is said to be in Transmit Mode. In this mode, only IN tokens should be sent by the host to Endpoint0. The SUEND bit (E0CSR.4) is set to ‘1’ if a SETUP or OUT token is received while Endpoint0 is in Transmit Mode. Endpoint0 will remain in Transmit Mode until any of the following occur: 1. USB0 receives an Endpoint0 SETUP or OUT token. 2. Firmware sends a packet less than the maximum Endpoint0 packet size. 3. Firmware sends a zero-length packet. Firmware should set the DATAEND bit (E0CSR.3) to ‘1’ when performing (2) and (3) above. The SIE will transmit a NAK in response to an IN token if there is no packet ready in the IN FIFO (INPRDY = ‘0’). Rev. 1.5 177 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 16.10.3.Endpoint0 OUT Transactions When a SETUP request is received that requires the host to transmit data to USB0, one or more OUT requests will be sent by the host. When an OUT packet is successfully received by USB0, hardware will set the OPRDY bit (E0CSR.0) to ‘1’ and generate an Endpoint0 interrupt. Following this interrupt, firmware should unload the OUT packet from the Endpoint0 FIFO and set the SOPRDY bit (E0CSR.6) to ‘1’. If the amount of data required for the transfer exceeds the maximum packet size for Endpoint0, the data will be split into multiple packets. If the requested data is an integer multiple of the maximum packet size for Endpoint0 (as reported to the host), the host will send a zero-length data packet signaling the end of the transfer. Upon reception of the first OUT token for a particular control transfer, Endpoint0 is said to be in Receive Mode. In this mode, only OUT tokens should be sent by the host to Endpoint0. The SUEND bit (E0CSR.4) is set to ‘1’ if a SETUP or IN token is received while Endpoint0 is in Receive Mode. Endpoint0 will remain in Receive mode until: 1. The SIE receives a SETUP or IN token. 2. The host sends a packet less than the maximum Endpoint0 packet size. 3. The host sends a zero-length packet. Firmware should set the DATAEND bit (E0CSR.3) to ‘1’ when the expected amount of data has been received. The SIE will transmit a STALL condition if the host sends an OUT packet after the DATAEND bit has been set by firmware. An interrupt will be generated with the STSTL bit (E0CSR.2) set to ‘1’ after the STALL is transmitted. 178 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D USB Register Definition 16.17. E0CSR: USB0 Endpoint0 Control R/W R/W SSUEND SOPRDY Bit7 Bit6 R/W SDSTL Bit5 R R/W SUEND DATAEND Bit4 R/W R/W R Reset Value STSTL INPRDY OPRDY 00000000 Bit2 Bit1 Bit0 USB Address: Bit3 0x11 Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: SSUEND: Serviced Setup End Write: Software should set this bit to ‘1’ after servicing a Setup End (bit SUEND) event. Hardware clears the SUEND bit when software writes ‘1’ to SSUEND. Read: This bit always reads ‘0’. SOPRDY: Serviced OPRDY Write: Software should write ‘1’ to this bit after servicing a received Endpoint0 packet. The OPRDY bit will be cleared by a write of ‘1’ to SOPRDY. Read: This bit always reads ‘0’. SDSTL: Send Stall Software can write ‘1’ to this bit to terminate the current transfer (due to an error condition, unexpected transfer request, etc.). Hardware will clear this bit to ‘0’ when the STALL handshake is transmitted. SUEND: Setup End Hardware sets this read-only bit to ‘1’ when a control transaction ends before software has written ‘1’ to the DATAEND bit. Hardware clears this bit when software writes ‘1’ to SSUEND. DATAEND: Data End Software should write ‘1’ to this bit: 1. When writing ‘1’ to INPRDY for the last outgoing data packet. 2. When writing ‘1’ to INPRDY for a zero-length data packet. 3. When writing ‘1’ to SOPRDY after servicing the last incoming data packet. This bit is automatically cleared by hardware. STSTL: Sent Stall Hardware sets this bit to ‘1’ after transmitting a STALL handshake signal. This flag must be cleared by software. INPRDY: IN Packet Ready Software should write ‘1’ to this bit after loading a data packet into the Endpoint0 FIFO for transmit. Hardware clears this bit and generates an interrupt under either of the following conditions: 1. The packet is transmitted. 2. The packet is overwritten by an incoming SETUP packet. 3. The packet is overwritten by an incoming OUT packet. OPRDY: OUT Packet Ready Hardware sets this read-only bit and generates an interrupt when a data packet has been received. This bit is cleared only when software writes ‘1’ to the SOPRDY bit. Rev. 1.5 179 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D USB Register Definition 16.18. E0CNT: USB0 Endpoint 0 Data Count R R R R - R R R R E0CNT Bit7 Bit6 Bit5 Bit4 Bit3 Reset Value 00000000 Bit2 Bit1 Bit0 USB Address: 0x16 Bit7: Unused. Read = 0; Write = don’t care. Bits6–0: E0CNT: Endpoint 0 Data Count This 7-bit number indicates the number of received data bytes in the Endpoint 0 FIFO. This number is only valid while bit OPRDY is a ‘1’. 16.11. Configuring Endpoints1-3 Endpoints1-3 are configured and controlled through their own sets of the following control/status registers: IN registers EINCSRL and EINCSRH, and OUT registers EOUTCSRL and EOUTCSRH. Only one set of endpoint control/status registers is mapped into the USB register address space at a time, defined by the contents of the INDEX register (USB Register Definition 16.4). Endpoints1-3 can be configured as IN, OUT, or both IN/OUT (Split Mode) as described in Section 16.5.1. The endpoint mode (Split/Normal) is selected via the SPLIT bit in register EINCSRH. When SPLIT = ‘1’, the corresponding endpoint FIFO is split, and both IN and OUT pipes are available. When SPLIT = ‘0’, the corresponding endpoint functions as either IN or OUT; the endpoint direction is selected by the DIRSEL bit in register EINCSRH. 16.12. Controlling Endpoints1-3 IN Endpoints1-3 IN are managed via USB registers EINCSRL and EINCSRH. All IN endpoints can be used for Interrupt, Bulk, or Isochronous transfers. Isochronous (ISO) mode is enabled by writing ‘1’ to the ISO bit in register EINCSRH. Bulk and Interrupt transfers are handled identically by hardware. An Endpoint1-3 IN interrupt is generated by any of the following conditions: 1. An IN packet is successfully transferred to the host. 2. Software writes ‘1’ to the FLUSH bit (EINCSRL.3) when the target FIFO is not empty. 3. Hardware generates a STALL condition. 16.12.1.Endpoints1-3 IN Interrupt or Bulk Mode When the ISO bit (EINCSRH.6) = ‘0’ the target endpoint operates in Bulk or Interrupt Mode. Once an endpoint has been configured to operate in Bulk/Interrupt IN mode (typically following an Endpoint0 SET_INTERFACE command), firmware should load an IN packet into the endpoint IN FIFO and set the INPRDY bit (EINCSRL.0). Upon reception of an IN token, hardware will transmit the data, clear the INPRDY bit, and generate an interrupt. 180 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Writing ‘1’ to INPRDY without writing any data to the endpoint FIFO will cause a zero-length packet to be transmitted upon reception of the next IN token. A Bulk or Interrupt pipe can be shut down (or Halted) by writing ‘1’ to the SDSTL bit (EINCSRL.4). While SDSTL = ‘1’, hardware will respond to all IN requests with a STALL condition. Each time hardware generates a STALL condition, an interrupt will be generated and the STSTL bit (EINCSRL.5) set to ‘1’. The STSTL bit must be reset to ‘0’ by firmware. Hardware will automatically reset INPRDY to ‘0’ when a packet slot is open in the endpoint FIFO. Note that if double buffering is enabled for the target endpoint, it is possible for firmware to load two packets into the IN FIFO at a time. In this case, hardware will reset INPRDY to ‘0’ immediately after firmware loads the first packet into the FIFO and sets INPRDY to ‘1’. An interrupt will not be generated in this case; an interrupt will only be generated when a data packet is transmitted. When firmware writes ‘1’ to the FCDT bit (EINCSRH.3), the data toggle for each IN packet will be toggled continuously, regardless of the handshake received from the host. This feature is typically used by Interrupt endpoints functioning as rate feedback communication for Isochronous endpoints. When FCDT = ‘0’, the data toggle bit will only be toggled when an ACK is sent from the host in response to an IN packet. 16.12.2.Endpoints1-3 IN Isochronous Mode When the ISO bit (EINCSRH.6) is set to ‘1’, the target endpoint operates in Isochronous (ISO) mode. Once an endpoint has been configured for ISO IN mode, the host will send one IN token (data request) per frame; the location of data within each frame may vary. Because of this, it is recommended that double buffering be enabled for ISO IN endpoints. Hardware will automatically reset INPRDY (EINCSRL.0) to ‘0’ when a packet slot is open in the endpoint FIFO. Note that if double buffering is enabled for the target endpoint, it is possible for firmware to load two packets into the IN FIFO at a time. In this case, hardware will reset INPRDY to ‘0’ immediately after firmware loads the first packet into the FIFO and sets INPRDY to ‘1’. An interrupt will not be generated in this case; an interrupt will only be generated when a data packet is transmitted. If there is not a data packet ready in the endpoint FIFO when USB0 receives an IN token from the host, USB0 will transmit a zero-length data packet and set the UNDRUN bit (EINCSRL.2) to ‘1’. The ISO Update feature (see Section 16.7) can be useful in starting a double buffered ISO IN endpoint. If the host has already set up the ISO IN pipe (has begun transmitting IN tokens) when firmware writes the first data packet to the endpoint FIFO, the next IN token may arrive and the first data packet sent before firmware has written the second (double buffered) data packet to the FIFO. The ISO Update feature ensures that any data packet written to the endpoint FIFO will not be transmitted during the current frame; the packet will only be sent after a SOF signal has been received. Rev. 1.5 181 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D USB Register Definition 16.19. EINCSRL: USB0 IN Endpoint Control Low Byte R W R/W R/W R/W - CLRDT STSTL SDSTL FLUSH Bit7 Bit6 Bit5 Bit4 Bit3 R/W R/W UNDRUN FIFONE Bit2 Bit1 R/W Reset Value INPRDY 00000000 Bit0 USB Address: 0x11 Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: 182 Unused. Read = 0; Write = don’t care. CLRDT: Clear Data Toggle. Write: Software should write ‘1’ to this bit to reset the IN Endpoint data toggle to ‘0’. Read: This bit always reads ‘0’. STSTL: Sent Stall Hardware sets this bit to ‘1’ when a STALL handshake signal is transmitted. The FIFO is flushed, and the INPRDY bit cleared. This flag must be cleared by software. SDSTL: Send Stall. Software should write ‘1’ to this bit to generate a STALL handshake in response to an IN token. Software should write ‘0’ to this bit to terminate the STALL signal. This bit has no effect in ISO mode. FLUSH: FIFO Flush. Writing a ‘1’ to this bit flushes the next packet to be transmitted from the IN Endpoint FIFO. The FIFO pointer is reset and the INPRDY bit is cleared. If the FIFO contains multiple packets, software must write ‘1’ to FLUSH for each packet. Hardware resets the FLUSH bit to ‘0’ when the FIFO flush is complete. UNDRUN: Data Underrun. The function of this bit depends on the IN Endpoint mode: Isochronous: Set when a zero-length packet is sent after an IN token is received while bit INPRDY = ‘0’. Interrupt/Bulk: This bit is not used in these modes and will always read a '0'. This bit must be cleared by software. FIFONE: FIFO Not Empty. 0: The IN Endpoint FIFO is empty. 1. The IN Endpoint FIFO contains one or more packets. INPRDY: In Packet Ready. Software should write ‘1’ to this bit after loading a data packet into the IN Endpoint FIFO. Hardware clears INPRDY due to any of the following: 1. A data packet is transmitted. 2. Double buffering is enabled (DBIEN = ‘1’) and there is an open FIFO packet slot. 3. If the endpoint is in Isochronous Mode (ISO = ‘1’) and ISOUD = ‘1’, INPRDY will read ‘0’ until the next SOF is received. An interrupt (if enabled) will be generated when hardware clears INPRDY as a result of a packet being transmitted. Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D USB Register Definition 16.20. EINCSRH: USB0 IN Endpoint Control High Byte R/W R/W R/W R R/W R/W R R Reset Value DBIEN ISO DIRSEL - FCDT SPLIT - - 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USB Address: 0x12 Bit7: DBIEN: IN Endpoint Double-buffer Enable. 0: Double-buffering disabled for the selected IN endpoint. 1: Double-buffering enabled for the selected IN endpoint. Bit6: ISO: Isochronous Transfer Enable. This bit enables/disables isochronous transfers on the current endpoint. 0: Endpoint configured for bulk/interrupt transfers. 1: Endpoint configured for isochronous transfers. Bit5: DIRSEL: Endpoint Direction Select. This bit is valid only when the selected FIFO is not split (SPLIT = ‘0’). 0: Endpoint direction selected as OUT. 1: Endpoint direction selected as IN. Bit4: Unused. Read = ‘0’. Write = don’t care. Bit3: FCDT: Force Data Toggle. 0: Endpoint data toggle switches only when an ACK is received following a data packet transmission. 1: Endpoint data toggle forced to switch after every data packet is transmitted, regardless of ACK reception. Bit2: SPLIT: FIFO Split Enable. When SPLIT = ‘1’, the selected endpoint FIFO is split. The upper half of the selected FIFO is used by the IN endpoint; the lower half of the selected FIFO is used by the OUT endpoint. Bits1–0: Unused. Read = 00b; Write = don’t care. 16.13. Controlling Endpoints1-3 OUT Endpoints1-3 OUT are managed via USB registers EOUTCSRL and EOUTCSRH. All OUT endpoints can be used for Interrupt, Bulk, or Isochronous transfers. Isochronous (ISO) mode is enabled by writing ‘1’ to the ISO bit in register EOUTCSRH. Bulk and Interrupt transfers are handled identically by hardware. An Endpoint1-3 OUT interrupt may be generated by the following: 1. Hardware sets the OPRDY bit (EINCSRL.0) to ‘1’. 2. Hardware generates a STALL condition. 16.13.1.Endpoints1-3 OUT Interrupt or Bulk Mode When the ISO bit (EOUTCSRH.6) = ‘0’ the target endpoint operates in Bulk or Interrupt mode. Once an endpoint has been configured to operate in Bulk/Interrupt OUT mode (typically following an Endpoint0 SET_INTERFACE command), hardware will set the OPRDY bit (EOUTCSRL.0) to ‘1’ and generate an interrupt upon reception of an OUT token and data packet. The number of bytes in the current OUT data packet (the packet ready to be unloaded from the FIFO) is given in the EOUTCNTH and EOUTCNTL registers. In response to this interrupt, firmware should unload the data packet from the OUT FIFO and reset the OPRDY bit to ‘0’. Rev. 1.5 183 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D A Bulk or Interrupt pipe can be shut down (or Halted) by writing ‘1’ to the SDSTL bit (EOUTCSRL.5). While SDSTL = ‘1’, hardware will respond to all OUT requests with a STALL condition. Each time hardware generates a STALL condition, an interrupt will be generated and the STSTL bit (EOUTCSRL.6) set to ‘1’. The STSTL bit must be reset to ‘0’ by firmware. Hardware will automatically set OPRDY when a packet is ready in the OUT FIFO. Note that if double buffering is enabled for the target endpoint, it is possible for two packets to be ready in the OUT FIFO at a time. In this case, hardware will set OPRDY to ‘1’ immediately after firmware unloads the first packet and resets OPRDY to ‘0’. A second interrupt will be generated in this case. 16.13.2.Endpoints1-3 OUT Isochronous Mode When the ISO bit (EOUTCSRH.6) is set to ‘1’, the target endpoint operates in Isochronous (ISO) mode. Once an endpoint has been configured for ISO OUT mode, the host will send exactly one data per USB frame; the location of the data packet within each frame may vary, however. Because of this, it is recommended that double buffering be enabled for ISO OUT endpoints. Each time a data packet is received, hardware will load the received data packet into the endpoint FIFO, set the OPRDY bit (EOUTCSRL.0) to ‘1’, and generate an interrupt (if enabled). Firmware would typically use this interrupt to unload the data packet from the endpoint FIFO and reset the OPRDY bit to ‘0’. If a data packet is received when there is no room in the endpoint FIFO, an interrupt will be generated and the OVRUN bit (EOUTCSRL.2) set to ‘1’. If USB0 receives an ISO data packet with a CRC error, the data packet will be loaded into the endpoint FIFO, OPRDY will be set to ‘1’, an interrupt (if enabled) will be generated, and the DATAERR bit (EOUTCSRL.3) will be set to ‘1’. Software should check the DATAERR bit each time a data packet is unloaded from an ISO OUT endpoint FIFO. 184 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D USB Register Definition 16.21. EOUTCSRL: USB0 OUT Endpoint Control Low Byte W R/W R/W R/W R R/W R R/W Reset Value CLRDT STSTL SDSTL FLUSH DATERR OVRUN FIFOFUL OPRDY 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USB Address: 0x14 Bit7: Bit6: Bit5: Bit4: CLRDT: Clear Data Toggle Write: Software should write ‘1’ to this bit to reset the OUT endpoint data toggle to ‘0’. Read: This bit always reads ‘0’. STSTL: Sent Stall Hardware sets this bit to ‘1’ when a STALL handshake signal is transmitted. This flag must be cleared by software. SDSTL: Send Stall Software should write ‘1’ to this bit to generate a STALL handshake. Software should write ‘0’ to this bit to terminate the STALL signal. This bit has no effect in ISO mode. FLUSH: FIFO Flush Writing a ‘1’ to this bit flushes the next packet to be read from the OUT endpoint FIFO. The FIFO pointer is reset and the OPRDY bit is cleared. If the FIFO contains multiple packets, software must write ‘1’ to FLUSH for each packet. Hardware resets the FLUSH bit to ‘0’ when the FIFO flush is complete. Note: If data for the current packet has already been read from the FIFO, the FLUSH bit should not be used to flush the packet. Instead, the entire data packet should be read from the FIFO manually. Bit3: Bit2: Bit1: Bit0: DATERR: Data Error In ISO mode, this bit is set by hardware if a received packet has a CRC or bit-stuffing error. It is cleared when software clears OPRDY. This bit is only valid in ISO mode. OVRUN: Data Overrun This bit is set by hardware when an incoming data packet cannot be loaded into the OUT endpoint FIFO. This bit is only valid in ISO mode, and must be cleared by software. 0: No data overrun. 1: A data packet was lost because of a full FIFO since this flag was last cleared. FIFOFUL: OUT FIFO Full This bit indicates the contents of the OUT FIFO. If double buffering is enabled for the endpoint (DBIEN = ‘1’), the FIFO is full when the FIFO contains two packets. If DBIEN = ‘0’, the FIFO is full when the FIFO contains one packet. 0: OUT endpoint FIFO is not full. 1: OUT endpoint FIFO is full. OPRDY: OUT Packet Ready Hardware sets this bit to ‘1’ and generates an interrupt when a data packet is available. Software should clear this bit after each data packet is unloaded from the OUT endpoint FIFO. Rev. 1.5 185 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D USB Register Definition 16.22. EOUTCSRH: USB0 OUT Endpoint Control High Byte R/W R/W R/W R/W R R R R Reset Value DBOEN ISO - - - - - - 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USB Address: 0x15 Bit7: DBOEN: Double-buffer Enable 0: Double-buffering disabled for the selected OUT endpoint. 1: Double-buffering enabled for the selected OUT endpoint. Bit6: ISO: Isochronous Transfer Enable This bit enables/disables isochronous transfers on the current endpoint. 0: Endpoint configured for bulk/interrupt transfers. 1: Endpoint configured for isochronous transfers. Bits5–0: Unused. Read = 000000b; Write = don’t care. USB Register Definition 16.23. EOUTCNTL: USB0 OUT Endpoint Count Low R R R R R R R R EOCL Bit7 Bit6 Bit5 Bit4 Reset Value 00000000 Bit3 Bit2 Bit1 Bit0 USB Address: 0x16 Bits7–0: EOCL: OUT Endpoint Count Low Byte EOCL holds the lower 8-bits of the 10-bit number of data bytes in the last received packet in the current OUT endpoint FIFO. This number is only valid while OPRDY = ‘1’. USB Register Definition 16.24. EOUTCNTH: USB0 OUT Endpoint Count High R R R R R R - - - - - - Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 R R E0CH Bit1 Reset Value 00000000 Bit0 USB Address: 0x17 Bits7–2: Unused. Read = 00000. Write = don’t care. Bits1–0: EOCH: OUT Endpoint Count High Byte EOCH holds the upper 2-bits of the 10-bit number of data bytes in the last received packet in the current OUT endpoint FIFO. This number is only valid while OPRDY = ‘1’. 186 Rev. 1.5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 16.4. USB Transceiver Electrical Characteristics VDD = 3.0 to 3.6 V, –40 to +85 °C unless otherwise specified Parameters Symbol Conditions Transmitter VOH Output High Voltage VOL Output Low Voltage VCRS Output Crossover Point Driving High ZDRV Output Impedance Driving Low Full Speed (D+ Pull-up) RPU Pull-up Resistance Low Speed (D– Pull-up) Low Speed TR Output Rise Time Full Speed Low Speed TF Output Fall Time Full Speed Receiver Differential Input VDI | (D+) – (D–) | Sensitivity Differential Input Common VCM Mode Range IL Pullups Disabled Input Leakage Current Min Typ Max Units 0.8 2.0 V V V 2.8 1.3 38 Ω 38 1.425 1.5 1.575 75 300 4 75 20 300 4 20 0.2 kΩ ns ns V 0.8 2.5