C8051F352-GQR

C8051F350/1/2/3 8 k ISP Flash MCU Family Analog Peripherals - 24 or 16-Bit ADC - No missing codes 0.0015% nonlinearity Programmable conversion rates up to 1 ksps 8-Input multiplexer 1x to 128x PGA Built-in temperature sensor instructions in 1 or 2 system clocks - Up to 50 MIPS throughput - Expanded interrupt handler Memory - 768 Bytes (256 + 512) On-Chip RAM - 8 kB Flash; In-system programmable in 512-byte Two 8-Bit Current Output DACs Comparator • Programmable hysteresis and response time • Configurable as interrupt or reset source • Low current (0.4 µA) Sectors On-chip Debug - On-chip debug circuitry facilitates full speed, non- intrusive in-system debug (No emulator required) Provides breakpoints, single stepping, inspect/modify memory and registers Superior performance to emulation systems using ICE-Chips, target pods, and sockets Low Cost, Complete Development Kit Supply Voltage 2.7 to 3.6 V - Typical operating current: 5.8 mA @ 25 MHz; 11 µA @ 32 kHz 0.1 µA capture/compare modules Real time clock mode using PCA or timer and external clock source Clock Sources - Internal Oscillator: 24.5 MHz with ± 2% accuracy supports UART operation External Oscillator: Crystal, RC, C, or clock (1 or 2 pin modes) Clock multiplier to achieve 50 MHz internal clock Can switch between clock sources on-the-fly 28-Pin QFN or 32-Pin LQFP Package - 5 x 5 mm PCB footprint with 28-QFN ANALOG PERIPHERALS 8-bit IDAC 24/16-bit ADC 8-bit IDAC + TEMP SENSOR - - - Typical stop mode current: Temperature Range: –40 to +85 °C A M U X Digital Peripherals - 17 Port I/O; All 5 V tolerant with high sink current - Enhanced UART, SMBus™, and SPI™ Serial Ports - Four general purpose 16-bit counter/timers - 16-bit programmable counter array (PCA) with three VOLTAGE COMPARATOR DIGITAL I/O UART SMBus SPI PCA Timer 0 Timer 1 Timer 2 Timer 3 CROSSBAR • • • • • • High Speed 8051 µC Core - Pipelined Instruction architecture; executes 70% of Port 0 Port 1 P2.0 24.5 MHz PRECISION INTERNAL OSCILLATOR WITH CLOCK MULTIPLIER HIGH-SPEED CONTROLLER CORE 8 kB ISP FLASH FLEXIBLE INTERRUPTS Rev. 1.1 5/07 8051 CPU (50 MIPS) DEBUG CIRCUITRY 768 B SRAM POR Copyright © 2007 by Silicon Laboratories WDT C8051F35x C8051F350/1/2/3 NOTES: 2 Rev. 1.1 C8051F350/1/2/3 Table of Contents 1. System Overview.................................................................................................... 17 1.1. CIP-51™ Microcontroller................................................................................... 21 1.1.1. Fully 8051 Compatible Instruction Set...................................................... 21 1.1.2. Improved Throughput ............................................................................... 21 1.1.3. Additional Features .................................................................................. 21 1.2. On-Chip Debug Circuitry................................................................................... 22 1.3. On-Chip Memory............................................................................................... 23 1.4. 24 or 16-Bit Analog to Digital Converter (ADC0) .............................................. 24 1.5. Two 8-bit Current-Mode DACs.......................................................................... 25 1.6. Programmable Comparator .............................................................................. 26 1.7. Serial Ports ....................................................................................................... 26 1.8. Port Input/Output............................................................................................... 27 1.9. Programmable Counter Array ........................................................................... 28 2. Absolute Maximum Ratings .................................................................................. 29 3. Global DC Electrical Characteristics .................................................................... 30 4. Pinout and Package Definitions............................................................................ 31 5. 24 or 16-Bit Analog to Digital Converter (ADC0) ................................................. 41 5.1. Configuration..................................................................................................... 42 5.1.1. Voltage Reference Selection.................................................................... 42 5.1.2. Analog Inputs ........................................................................................... 42 5.1.3. Modulator Clock ....................................................................................... 43 5.1.4. Decimation Ratio ...................................................................................... 43 5.2. Calibrating the ADC .......................................................................................... 44 5.2.1. Internal Calibration ................................................................................... 44 5.2.2. System Calibration ................................................................................... 44 5.2.3. Calibration Coefficient Storage................................................................. 44 5.3. Performing Conversions ................................................................................... 46 5.3.1. Single Conversions .................................................................................. 46 5.3.2. Continuous Conversions .......................................................................... 46 5.3.3. ADC Output .............................................................................................. 46 5.3.4. Error Conditions ....................................................................................... 47 5.4. Offset DAC........................................................................................................ 47 5.5. Burnout Current Sources .................................................................................. 47 5.6. Analog Multiplexer ............................................................................................ 59 6. 8-Bit Current Mode DACS (IDA0 and IDA1).......................................................... 67 6.1. IDAC Output Scheduling................................................................................... 68 6.1.1. Update Output On-Demand ..................................................................... 68 6.1.2. Update Output Based on Timer Overflow ................................................ 68 6.1.3. Update Output Based on CNVSTR Edge................................................. 68 6.2. IDAC Output Mapping....................................................................................... 68 6.3. IDAC External Pin Connections ........................................................................ 71 7. Voltage Reference .................................................................................................. 73 8. Temperature Sensor............................................................................................... 77 Rev. 1.1 3 C8051F350/1/2/3 9. Comparator0 ........................................................................................................... 79 9.1. Comparator0 Inputs and Outputs...................................................................... 83 10. CIP-51 Microcontroller ........................................................................................... 87 10.1.Instruction Set................................................................................................... 89 10.1.1.Instruction and CPU Timing ..................................................................... 89 10.1.2.MOVX Instruction and Program Memory ................................................. 89 10.2.Register Descriptions ....................................................................................... 93 10.3.Power Management Modes.............................................................................. 96 10.3.1.Idle Mode ................................................................................................. 96 10.3.2.Stop Mode................................................................................................ 96 11. Memory Organization and SFRs ........................................................................... 99 11.1.Program Memory.............................................................................................. 99 11.2.Data Memory .................................................................................................. 100 11.3.General Purpose Registers ............................................................................ 100 11.4.Bit Addressable Locations .............................................................................. 100 11.5.Stack............................................................................................................... 100 11.6.Special Function Registers............................................................................. 101 12. Interrupt Handler .................................................................................................. 105 12.1.MCU Interrupt Sources and Vectors............................................................... 105 12.2.Interrupt Priorities ........................................................................................... 105 12.3.Interrupt Latency............................................................................................. 105 12.4.Interrupt Register Descriptions ....................................................................... 107 12.5.External Interrupts .......................................................................................... 111 13. Prefetch Engine .................................................................................................... 113 14. Reset Sources....................................................................................................... 115 14.1.Power-On Reset ............................................................................................. 116 14.2.Power-Fail Reset / VDD Monitor .................................................................... 117 14.3.External Reset ................................................................................................ 118 14.4.Missing Clock Detector Reset ........................................................................ 118 14.5.Comparator0 Reset ........................................................................................ 118 14.6.PCA Watchdog Timer Reset .......................................................................... 118 14.7.Flash Error Reset ........................................................................................... 118 14.8.Software Reset ............................................................................................... 118 15. Flash Memory ....................................................................................................... 121 15.1.Programming The Flash Memory ................................................................... 121 15.1.1.Flash Lock and Key Functions ............................................................... 121 15.1.2.Flash Erase Procedure .......................................................................... 121 15.1.3.Flash Write Procedure ........................................................................... 122 15.2.Non-volatile Data Storage .............................................................................. 123 15.3.Security Options ............................................................................................. 123 16. External RAM ........................................................................................................ 127 17. Oscillators ............................................................................................................. 129 17.1.Programmable Internal Oscillator ................................................................... 129 17.2.External Oscillator Drive Circuit...................................................................... 131 17.2.1.Clocking Timers Directly Through the External Oscillator...................... 131 4 Rev. 1.1 C8051F350/1/2/3 17.2.2.External Crystal Example....................................................................... 131 17.2.3.External RC Example............................................................................. 133 17.2.4.External Capacitor Example................................................................... 133 17.3.Clock Multiplier ............................................................................................... 135 17.4.System Clock Selection.................................................................................. 136 18. Port Input/Output.................................................................................................. 137 18.1.Priority Crossbar Decoder .............................................................................. 139 18.2.Port I/O Initialization ....................................................................................... 141 18.3.General Purpose Port I/O ............................................................................... 144 19. SMBus ................................................................................................................... 151 19.1.Supporting Documents ................................................................................... 152 19.2.SMBus Configuration...................................................................................... 152 19.3.SMBus Operation ........................................................................................... 152 19.3.1.Arbitration............................................................................................... 153 19.3.2.Clock Low Extension.............................................................................. 154 19.3.3.SCL Low Timeout................................................................................... 154 19.3.4.SCL High (SMBus Free) Timeout .......................................................... 154 19.4.Using the SMBus............................................................................................ 155 19.4.1.SMBus Configuration Register............................................................... 156 19.4.2.SMB0CN Control Register ..................................................................... 159 19.4.3.Data Register ......................................................................................... 162 19.5.SMBus Transfer Modes.................................................................................. 163 19.5.1.Master Transmitter Mode ....................................................................... 163 19.5.2.Master Receiver Mode ........................................................................... 164 19.5.3.Slave Receiver Mode ............................................................................. 165 19.5.4.Slave Transmitter Mode ......................................................................... 166 19.6.SMBus Status Decoding................................................................................. 167 20. UART0.................................................................................................................... 171 20.1.Enhanced Baud Rate Generation................................................................... 172 20.2.Operational Modes ......................................................................................... 173 20.2.1.8-Bit UART ............................................................................................. 173 20.2.2.9-Bit UART ............................................................................................. 174 20.3.Multiprocessor Communications .................................................................... 174 21. Serial Peripheral Interface (SPI0) ........................................................................ 181 21.1.Signal Descriptions......................................................................................... 182 21.1.1.Master Out, Slave In (MOSI).................................................................. 182 21.1.2.Master In, Slave Out (MISO).................................................................. 182 21.1.3.Serial Clock (SCK) ................................................................................. 182 21.1.4.Slave Select (NSS) ................................................................................ 182 21.2.SPI0 Master Mode Operation ......................................................................... 183 21.3.SPI0 Slave Mode Operation ........................................................................... 185 21.4.SPI0 Interrupt Sources ................................................................................... 185 21.5.Serial Clock Timing......................................................................................... 186 21.6.SPI Special Function Registers ...................................................................... 186 Rev. 1.1 5 C8051F350/1/2/3 22. Timers.................................................................................................................... 195 22.1.Timer 0 and Timer 1 ....................................................................................... 195 22.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 195 22.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 196 22.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 197 22.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 198 22.2.Timer 2 .......................................................................................................... 203 22.2.1.16-bit Timer with Auto-Reload................................................................ 203 22.2.2.8-bit Timers with Auto-Reload................................................................ 204 22.3.Timer 3 .......................................................................................................... 207 22.3.1.16-bit Timer with Auto-Reload................................................................ 207 22.3.2.8-bit Timers with Auto-Reload................................................................ 208 23. Programmable Counter Array ............................................................................. 211 23.1.PCA Counter/Timer ........................................................................................ 212 23.2.Capture/Compare Modules ............................................................................ 213 23.2.1.Edge-triggered Capture Mode................................................................ 214 23.2.2.Software Timer (Compare) Mode........................................................... 215 23.2.3.High Speed Output Mode....................................................................... 216 23.2.4.Frequency Output Mode ........................................................................ 217 23.2.5.8-Bit Pulse Width Modulator Mode......................................................... 218 23.2.6.16-Bit Pulse Width Modulator Mode....................................................... 219 23.3.Watchdog Timer Mode ................................................................................... 220 23.3.1.Watchdog Timer Operation .................................................................... 220 23.3.2.Watchdog Timer Usage ......................................................................... 221 23.4.Register Descriptions for PCA........................................................................ 222 24. Revision Specific Behavior ................................................................................. 227 24.1.Revision Identification..................................................................................... 227 25. C2 Interface ........................................................................................................... 229 25.1.C2 Interface Registers.................................................................................... 229 25.2.C2 Pin Sharing ............................................................................................... 231 Document Change List............................................................................................. 232 Contact Information.................................................................................................. 234 6 Rev. 1.1 C8051F350/1/2/3 List of Figures 1. System Overview Figure 1.1. C8051F350 Block Diagram .................................................................... 19 Figure 1.2. C8051F351 Block Diagram .................................................................... 19 Figure 1.3. C8051F352 Block Diagram .................................................................... 20 Figure 1.4. C8051F353 Block Diagram .................................................................... 20 Figure 1.5. Development/In-System Debug Diagram............................................... 22 Figure 1.6. Memory Map .......................................................................................... 23 Figure 1.7. ADC0 Block Diagram ............................................................................. 24 Figure 1.8. IDAC Block Diagram .............................................................................. 25 Figure 1.9. Comparator0 Block Diagram.................................................................. 26 Figure 1.10. Port I/O Functional Block Diagram ....................................................... 27 Figure 1.11. PCA Block Diagram.............................................................................. 28 2. Absolute Maximum Ratings 3. Global DC Electrical Characteristics 4. Pinout and Package Definitions Figure 4.1. LQFP-32 Pinout Diagram (Top View) .................................................... 34 Figure 4.2. QFN-28 Pinout Diagram (Top View) ...................................................... 35 Figure 4.3. LQFP-32 Package Diagram ................................................................... 36 Figure 4.4. QFN-28 Package Drawing ..................................................................... 37 Figure 4.5. Typical QFN-28 Landing Diagram.......................................................... 38 Figure 4.6. Typical QFN-28 Solder Paste Diagram.................................................. 39 5. 24 or 16-Bit Analog to Digital Converter (ADC0) Figure 5.1. ADC0 Block Diagram ............................................................................. 41 Figure 5.2. ADC0 Buffer Control .............................................................................. 43 Figure 5.3. ADC0 Offset Calibration Register Coding .............................................. 45 Figure 5.4. ADC0 Gain Calibration Register Coding ................................................ 45 Figure 5.5. ADC0 Multiplexer Connections .............................................................. 59 6. 8-Bit Current Mode DACS (IDA0 and IDA1) Figure 6.1. IDAC Functional Block Diagram............................................................. 67 Figure 6.2. IDAC Data Word Mapping...................................................................... 68 Figure 6.3. IDAC Pin Connections ........................................................................... 71 7. Voltage Reference Figure 7.1. Reference Circuitry Block Diagram ........................................................ 73 8. Temperature Sensor Figure 8.1. Temperature Sensor Block Diagram...................................................... 77 Figure 8.2. Single Channel Transfer Function.......................................................... 78 Figure 8.3. Differential Transfer Function................................................................. 78 9. Comparator0 Figure 9.1. Comparator0 Functional Block Diagram ................................................ 79 Figure 9.2. Comparator Hysteresis Plot ................................................................... 80 Figure 9.3. Comparator Pin Connections ................................................................. 83 10. CIP-51 Microcontroller Figure 10.1. CIP-51 Block Diagram.......................................................................... 87 Rev. 1.1 7 C8051F350/1/2/3 11. Memory Organization and SFRs Figure 11.1. Memory Map ........................................................................................ 99 12. Interrupt Handler 13. Prefetch Engine 14. Reset Sources Figure 14.1. Reset Sources.................................................................................... 115 Figure 14.2. Power-On and VDD Monitor Reset Timing ........................................ 116 15. Flash Memory Figure 15.1. Flash Memory Map............................................................................. 123 16. External RAM 17. Oscillators Figure 17.1. Oscillator Diagram.............................................................................. 129 Figure 17.2. 32.768 kHz External Crystal Example................................................ 132 18. Port Input/Output Figure 18.1. Port I/O Functional Block Diagram ..................................................... 137 Figure 18.2. Port I/O Cell Block Diagram ............................................................... 138 Figure 18.3. Crossbar Priority Decoder with No Pins Skipped ............................... 139 Figure 18.4. Crossbar Priority Decoder with Crystal Pins Skipped ........................ 140 19. SMBus Figure 19.1. SMBus Block Diagram ....................................................................... 151 Figure 19.2. Typical SMBus Configuration ............................................................. 152 Figure 19.3. SMBus Transaction ............................................................................ 153 Figure 19.4. Typical SMBus SCL Generation......................................................... 157 Figure 19.5. Typical Master Transmitter Sequence................................................ 163 Figure 19.6. Typical Master Receiver Sequence.................................................... 164 Figure 19.7. Typical Slave Receiver Sequence...................................................... 165 Figure 19.8. Typical Slave Transmitter Sequence.................................................. 166 20. UART0 Figure 20.1. UART0 Block Diagram ....................................................................... 171 Figure 20.2. UART0 Baud Rate Logic .................................................................... 172 Figure 20.3. UART Interconnect Diagram .............................................................. 173 Figure 20.4. 8-Bit UART Timing Diagram............................................................... 173 Figure 20.5. 9-Bit UART Timing Diagram............................................................... 174 Figure 20.6. UART Multi-Processor Mode Interconnect Diagram .......................... 175 21. Serial Peripheral Interface (SPI0) Figure 21.1. SPI Block Diagram ............................................................................. 181 Figure 21.2. Multiple-Master Mode Connection Diagram ....................................... 184 Figure 21.3. 3-Wire Single Master and Slave Mode Connection Diagram ............. 184 Figure 21.4. 4-Wire Single Master and Slave Mode Connection Diagram ............. 184 Figure 21.5. Data/Clock Timing Relationship ......................................................... 186 Figure 21.6. SPI Master Timing (CKPHA = 0)........................................................ 191 Figure 21.7. SPI Master Timing (CKPHA = 1)........................................................ 191 Figure 21.8. SPI Slave Timing (CKPHA = 0).......................................................... 192 Figure 21.9. SPI Slave Timing (CKPHA = 1).......................................................... 192 8 Rev. 1.1 C8051F350/1/2/3 22. Timers Figure 22.1. T0 Mode 0 Block Diagram.................................................................. 196 Figure 22.2. T0 Mode 2 Block Diagram.................................................................. 197 Figure 22.3. T0 Mode 3 Block Diagram.................................................................. 198 Figure 22.4. Timer 2 16-Bit Mode Block Diagram .................................................. 203 Figure 22.5. Timer 2 8-Bit Mode Block Diagram .................................................... 204 Figure 22.6. Timer 3 16-Bit Mode Block Diagram .................................................. 207 Figure 22.7. Timer 3 8-Bit Mode Block Diagram .................................................... 208 23. Programmable Counter Array Figure 23.1. PCA Block Diagram............................................................................ 211 Figure 23.2. PCA Counter/Timer Block Diagram.................................................... 212 Figure 23.3. PCA Interrupt Block Diagram ............................................................. 213 Figure 23.4. PCA Capture Mode Diagram.............................................................. 214 Figure 23.5. PCA Software Timer Mode Diagram .................................................. 215 Figure 23.6. PCA High Speed Output Mode Diagram............................................ 216 Figure 23.7. PCA Frequency Output Mode ............................................................ 217 Figure 23.8. PCA 8-Bit PWM Mode Diagram ......................................................... 218 Figure 23.9. PCA 16-Bit PWM Mode...................................................................... 219 Figure 23.10. PCA Module 2 with Watchdog Timer Enabled ................................. 220 24. Revision Specific Behavior Figure 24.1. Reading Package Marking ................................................................. 227 25. C2 Interface Figure 25.1. Typical C2 Pin Sharing....................................................................... 231 Rev. 1.1 9 C8051F350/1/2/3 NOTES: 10 Rev. 1.1 C8051F350/1/2/3 List of Tables 1. System Overview Table 1.1. Product Selection Guide ......................................................................... 18 2. Absolute Maximum Ratings 3. Global DC Electrical Characteristics 4. Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F350/1/2/3 ................................................. 31 Table 4.2. LQFP-32 Package Dimensions .............................................................. 36 Table 4.3. QFN-28 Package Dimensions ................................................................ 37 5. 24 or 16-Bit Analog to Digital Converter (ADC0) Table 5.1. ADC0 Unipolar Output Word Coding (AD0POL = 0) .............................. 47 Table 5.2. ADC0 Bipolar Output Word Coding (AD0POL = 1) ................................ 47 Table 5.3. ADC0 SINC3 Filter Typical RMS Noise (µV) .......................................... 62 Table 5.4. ADC0 SINC3 Filter Effective Resolution in Unipolar Mode (bits) ......................................................................... 63 Table 5.5. ADC0 SINC3 Filter Flicker-Free (Noise-Free) Resolution in Unipolar Mode (bits) ......................................................................... 63 Table 5.6. ADC0 Fast Filter Typical RMS Noise (µV) ............................................. 64 Table 5.7. ADC0 Fast Filter Effective Resolution1 in Unipolar Mode (bits) ............. 64 Table 5.8. ADC0 Fast Filter Flicker-Free (Noise-Free) Resolution in Unipolar Mode (bits) ......................................................................... 65 6. 8-Bit Current Mode DACS (IDA0 and IDA1) 7. Voltage Reference 8. Temperature Sensor 9. Comparator0 10. CIP-51 Microcontroller Table 10.1. CIP-51 Instruction Set Summary .......................................................... 89 11. Memory Organization and SFRs Table 11.1. Special Function Register (SFR) Memory Map .................................. 101 Table 11.2. Special Function Registers ................................................................. 102 12. Interrupt Handler Table 12.1. Interrupt Summary .............................................................................. 106 13. Prefetch Engine 14. Reset Sources 15. Flash Memory 16. External RAM 17. Oscillators 18. Port Input/Output 19. SMBus Table 19.1. SMBus Clock Source Selection .......................................................... 156 Table 19.2. Minimum SDA Setup and Hold Times ................................................ 157 Table 19.3. Sources for Hardware Changes to SMB0CN ..................................... 161 Table 19.4. SMBus Status Decoding ..................................................................... 167 20. UART0 Rev. 1.1 11 C8051F350/1/2/3 Table 20.1. Timer Settings for Standard Baud Rates Using the Internal Oscillator ............................................................... 178 Table 20.2. Timer Settings for Standard Baud Rates Using an External 25.0 MHz Oscillator ............................................... 178 Table 20.3. Timer Settings for Standard Baud Rates Using an External 22.1184 MHz Oscillator ......................................... 179 Table 20.4. Timer Settings for Standard Baud Rates Using an External 18.432 MHz Oscillator ........................................... 179 Table 20.5. Timer Settings for Standard Baud Rates Using an External 11.0592 MHz Oscillator ......................................... 180 Table 20.6. Timer Settings for Standard Baud Rates Using an External 3.6864 MHz Oscillator ........................................... 180 21. Serial Peripheral Interface (SPI0) Table 21.1. SPI Slave Timing Parameters ............................................................ 193 22. Timers 23. Programmable Counter Array Table 23.1. PCA Timebase Input Options ............................................................. 212 Table 23.2. PCA0CPM Register Settings for PCA Capture/Compare Modules .... 213 Table 23.3. Watchdog Timer Timeout Intervals...................................................... 221 24. Revision Specific Behavior 25. C2 Interface 12 Rev. 1.1 C8051F350/1/2/3 List of Registers SFR Definition 5.1. ADC0CN: ADC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 SFR Definition 5.2. ADC0CF: ADC0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 SFR Definition 5.3. ADC0MD: ADC0 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 SFR Definition 5.4. ADC0CLK: ADC0 Modulator Clock Divisor . . . . . . . . . . . . . . . . . . 51 SFR Definition 5.5. ADC0DECH: ADC0 Decimation Ratio Register High Byte . . . . . . 51 SFR Definition 5.6. ADC0DECL: ADC0 Decimation Ratio Register Low Byte . . . . . . . 52 SFR Definition 5.7. ADC0DAC: ADC0 Offset DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 SFR Definition 5.8. ADC0BUF: ADC0 Input Buffer Control . . . . . . . . . . . . . . . . . . . . . 53 SFR Definition 5.9. ADC0STA: ADC0 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 SFR Definition 5.10. ADC0COH: ADC0 Offset Calibration Register High Byte . . . . . . 55 SFR Definition 5.11. ADC0COM: ADC0 Offset Calibration Register Middle Byte . . . . 55 SFR Definition 5.12. ADC0COL: ADC0 Offset Calibration Register Low Byte . . . . . . . 55 SFR Definition 5.13. ADC0CGH: ADC0 Gain Calibration Register High Byte . . . . . . . 56 SFR Definition 5.14. ADC0CGM: ADC0 Gain Calibration Register Middle Byte . . . . . 56 SFR Definition 5.15. ADC0CGL: ADC0 Gain Calibration Register Low Byte . . . . . . . . 56 SFR Definition 5.16. ADC0H: ADC0 Conversion Register (SINC3 Filter) High Byte . . 57 SFR Definition 5.17. ADC0M: ADC0 Conversion Register (SINC3 Filter) Middle Byte 57 SFR Definition 5.18. ADC0L: ADC0 Conversion Register (SINC3 Filter) Low Byte . . . 57 SFR Definition 5.19. ADC0FH: ADC0 Conversion Register (Fast Filter) High Byte . . . 58 SFR Definition 5.20. ADC0FM: ADC0 Conversion Register (Fast Filter) Middle Byte . 58 SFR Definition 5.21. ADC0FL: ADC0 Conversion Register (Fast Filter) Low Byte . . . . 58 SFR Definition 5.22. ADC0MUX: ADC0 Analog Multiplexer Control . . . . . . . . . . . . . . 60 SFR Definition 6.1. IDA0CN: IDA0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 SFR Definition 6.2. IDA0: IDA0 Data Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 SFR Definition 6.3. IDA1CN: IDA1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 SFR Definition 6.4. IDA1: IDA1 Data Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 SFR Definition 7.1. REF0CN: Reference Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 SFR Definition 9.1. CPT0CN: Comparator0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 SFR Definition 9.2. CPT0MD: Comparator0 Mode Selection . . . . . . . . . . . . . . . . . . . . 82 SFR Definition 9.3. CPT0MX: Comparator0 MUX Selection . . . . . . . . . . . . . . . . . . . . 84 SFR Definition 10.1. SP: Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 SFR Definition 10.2. DPL: Data Pointer Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 SFR Definition 10.3. DPH: Data Pointer High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 SFR Definition 10.4. PSW: Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 SFR Definition 10.5. ACC: Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 SFR Definition 10.6. B: B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 SFR Definition 10.7. PCON: Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 SFR Definition 12.1. IE: Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 SFR Definition 12.2. IP: Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 SFR Definition 12.3. EIE1: Extended Interrupt Enable 1 . . . . . . . . . . . . . . . . . . . . . . 109 SFR Definition 12.4. EIP1: Extended Interrupt Priority 1 . . . . . . . . . . . . . . . . . . . . . . 110 SFR Definition 12.5. IT01CF: INT0/INT1 Configuration . . . . . . . . . . . . . . . . . . . . . . . 112 SFR Definition 13.1. PFE0CN: Prefetch Engine Control . . . . . . . . . . . . . . . . . . . . . . 113 Rev. 1.1 13 C8051F350/1/2/3 SFR Definition 14.1. VDM0CN: VDD Monitor Control . . . . . . . . . . . . . . . . . . . . . . . . 117 SFR Definition 14.2. RSTSRC: Reset Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 SFR Definition 15.1. PSCTL: Program Store R/W Control . . . . . . . . . . . . . . . . . . . . . 125 SFR Definition 15.2. FLKEY: Flash Lock and Key . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 SFR Definition 15.3. FLSCL: Flash Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 SFR Definition 16.1. EMI0CN: External Memory Interface Control . . . . . . . . . . . . . . 127 SFR Definition 17.1. OSCICN: Internal Oscillator Control . . . . . . . . . . . . . . . . . . . . . 130 SFR Definition 17.2. OSCICL: Internal Oscillator Calibration . . . . . . . . . . . . . . . . . . . 130 SFR Definition 17.3. OSCXCN: External Oscillator Control . . . . . . . . . . . . . . . . . . . . 134 SFR Definition 17.4. CLKMUL: Clock Multiplier Control . . . . . . . . . . . . . . . . . . . . . . . 135 SFR Definition 17.5. CLKSEL: Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 SFR Definition 18.1. XBR0: Port I/O Crossbar Register 0 . . . . . . . . . . . . . . . . . . . . . 142 SFR Definition 18.2. XBR1: Port I/O Crossbar Register 1 . . . . . . . . . . . . . . . . . . . . . 143 SFR Definition 18.3. P0: Port0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 SFR Definition 18.4. P0MDIN: Port0 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 SFR Definition 18.5. P0MDOUT: Port0 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . 146 SFR Definition 18.6. P0SKIP: Port0 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 SFR Definition 18.7. P1: Port1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 SFR Definition 18.8. P1MDIN: Port1 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 SFR Definition 18.9. P1MDOUT: Port1 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . 148 SFR Definition 18.10. P1SKIP: Port1 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 SFR Definition 18.11. P2: Port2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 SFR Definition 18.12. P2MDOUT: Port2 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 149 SFR Definition 19.1. SMB0CF: SMBus Clock/Configuration . . . . . . . . . . . . . . . . . . . 158 SFR Definition 19.2. SMB0CN: SMBus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 SFR Definition 19.3. SMB0DAT: SMBus Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 SFR Definition 20.1. SCON0: Serial Port 0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 176 SFR Definition 20.2. SBUF0: Serial (UART0) Port Data Buffer . . . . . . . . . . . . . . . . . 177 SFR Definition 21.1. SPI0CFG: SPI0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 187 SFR Definition 21.2. SPI0CN: SPI0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 SFR Definition 21.3. SPI0CKR: SPI0 Clock Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 SFR Definition 21.4. SPI0DAT: SPI0 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 SFR Definition 22.1. TCON: Timer Contro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 SFR Definition 22.2. TMOD: Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 SFR Definition 22.3. CKCON: Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 SFR Definition 22.4. TL0: Timer 0 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 SFR Definition 22.5. TL1: Timer 1 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 SFR Definition 22.6. TH0: Timer 0 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 SFR Definition 22.7. TH1: Timer 1 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 SFR Definition 22.8. TMR2CN: Timer 2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 SFR Definition 22.9. TMR2RLL: Timer 2 Reload Register Low Byte . . . . . . . . . . . . . 206 SFR Definition 22.10. TMR2RLH: Timer 2 Reload Register High Byte . . . . . . . . . . . 206 SFR Definition 22.11. TMR2L: Timer 2 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 SFR Definition 22.12. TMR2H Timer 2 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 SFR Definition 22.13. TMR3CN: Timer 3 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 14 Rev. 1.1 C8051F350/1/2/3 SFR Definition 22.14. TMR3RLL: Timer 3 Reload Register Low Byte . . . . . . . . . . . . 210 SFR Definition 22.15. TMR3RLH: Timer 3 Reload Register High Byte . . . . . . . . . . . 210 SFR Definition 22.16. TMR3L: Timer 3 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 SFR Definition 22.17. TMR3H Timer 3 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 SFR Definition 23.1. PCA0CN: PCA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 SFR Definition 23.2. PCA0MD: PCA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 SFR Definition 23.3. PCA0CPMn: PCA Capture/Compare Mode . . . . . . . . . . . . . . . 224 SFR Definition 23.4. PCA0L: PCA Counter/Timer Low Byte . . . . . . . . . . . . . . . . . . . 225 SFR Definition 23.5. PCA0H: PCA Counter/Timer High Byte . . . . . . . . . . . . . . . . . . . 225 SFR Definition 23.6. PCA0CPLn: PCA Capture Module Low Byte . . . . . . . . . . . . . . . 226 SFR Definition 23.7. PCA0CPHn: PCA Capture Module High Byte . . . . . . . . . . . . . . 226 C2 Register Definition 25.1. C2ADD: C2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 C2 Register Definition 25.2. DEVICEID: C2 Device ID . . . . . . . . . . . . . . . . . . . . . . . . 229 C2 Register Definition 25.3. REVID: C2 Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . 230 C2 Register Definition 25.4. FPCTL: C2 Flash Programming Control . . . . . . . . . . . . 230 C2 Register Definition 25.5. FPDAT: C2 Flash Programming Data . . . . . . . . . . . . . . 230 Rev. 1.1 15 C8051F350/1/2/3 NOTES: 16 Rev. 1.1 C8051F350/1/2/3 1. System Overview C8051F350/1/2/3 devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are listed below. Refer to Table 1.1 for specific product feature selection. • • • • • • • • • • • • • High-speed pipelined 8051-compatible microcontroller core (up to 50 MIPS) In-system, full-speed, non-intrusive debug interface (on-chip) 24 or 16-bit single-ended/differential ADC with analog multiplexer Two 8-bit Current Output DACs Precision programmable 24.5 MHz internal oscillator 8 kB of on-chip Flash memory 768 bytes of on-chip RAM SMBus/I2C, Enhanced UART, and SPI serial interfaces implemented in hardware Four general-purpose 16-bit timers Programmable counter/timer array (PCA) with three capture/compare modules and watchdog timer function On-chip power-on reset, VDD monitor, and temperature sensor On-chip voltage comparator 17 Port I/O (5 V tolerant) With on-chip power-on reset, VDD monitor, watchdog timer, and clock oscillator, the C8051F350/1/2/3 devices are truly stand-alone System-on-a-Chip solutions. The Flash memory can be reprogrammed even in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. User software has complete control of all peripherals, and may individually shut down any or all peripherals for power savings. The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging without occupying package pins. Each device is specified for 2.7 to 3.6 V operation over the industrial temperature range (–45 to +85 °C). The Port I/O and /RST pins are tolerant of input signals up to 5 V. The C8051F350/1/2/3 are available in 28-pin QFN (also referred to as MLP or MLF) or 32-pin LQFP packaging, as shown in Figure 1.1 through Figure 1.4. Rev. 1.1 17 Clock Multiplier SMBus/I2C SPI UART Timers (16-bit) Programmable Counter Array Digital Port I/Os 24-bit ADC 16-bit ADC Two 8-bit Current Output DACs Internal Voltage Reference Temperature Sensor Analog Comparator Lead-free (RoHS Compliant) Package C8051F350-GQ 50 8 kB 768      4  17  —      LQFP-32 C8051F351-GM 50 8 kB 768      4  17  —      QFN-28 C8051F352-GQ 50 8 kB 768      4  17 —       LQFP-32 C8051F353-GM 50 8 kB 768      4  17 —       QFN-28 18 RAM Flash Memory MIPS (Peak) Calibrated Internal 24.5 MHz Oscillator Ordering Part Number C8051F350/1/2/3 Table 1.1. Product Selection Guide Rev. 1.1 C8051F350/1/2/3 VDD Digital Power GND AV+ Analog Power AGND C2D Debug HW Reset /RST/C2CK BrownOut POR XTAL1 XTAL2 External Oscillator Circuit System Clock 24.5 MHz 2% Internal Oscillator Clock Multiplier P0.0 8 kB FLASH 8 0 5 1 256 byte SRAM Timer 0, 1, 2, 3 C o SFR Bus r e P0.3/XTAL2 D r v UART 512 byte XRAM P0.1 P0.2/XTAL1 P 0 Port 0 Latch X B A R 3-Chnl PCA/ WDT SMBus P0.4/TX P0.5/RX P0.6/CNVSTR P0.7 CP0 + CP0A - CP0+ CP0- SPI Bus VREF+ P1.0 VREF– Port 1 Latch VREF P1.1 P1.2 P 1 AIN0 AIN1 AIN2 AIN3 A M U X AIN4 AIN5 + Buffer P1.5/CP0 P1.6/IDAC0 8-bit IDAC0 24-bit ADC0 PGA + P1.3 P1.4/CP0A D r v Offset DAC P1.7/IDAC1 8-bit IDAC1 AIN6 AIN7 C2D Temp Sensor Port 2 Latch P2.0/C2D Figure 1.1. C8051F350 Block Diagram VDD GND AV+ Digital Power Analog Power AGND C2D Debug HW Reset /RST/C2CK POR BrownOut External Oscillator Circuit XTAL1 XTAL2 System Clock 24.5 MHz 2% Internal Oscillator Clock Multiplier P0.0 P0.1 8 kB FLASH 8 0 5 1 256 byte SRAM D r v UART 512 byte XRAM Timer 0, 1, 2, 3 C o SFR Bus r e X B A R 3-Chnl PCA/ WDT SMBus SPI Bus Offset DAC AIN4 AIN5 AIN6 AIN7 A M U X Buffer + + PGA + CP0A - CP0- P 1 P1.2/AIN6 P1.3/AIN7 D r v P1.4/CP0A P1.5/CP0 8-bit IDAC0 24-bit ADC0 CP0+ P1.0/AIN4 P1.1/AIN5 AIN0 AIN3 P0.7 CP0 Port 1 Latch VREF AIN1 AIN2 P0.5/RX P0.6/CNVSTR AIN4-7 VREF+ VREF– P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P 0 Port 0 Latch P1.6/IDAC0 P1.7/IDAC1 8-bit IDAC1 C2D Temp Sensor Port 2 Latch P2.0/C2D Figure 1.2. C8051F351 Block Diagram Rev. 1.1 19 C8051F350/1/2/3 VDD GND AV+ AGND Digital Power Analog Power C2D Debug HW Reset /RST/C2CK POR BrownOut External Oscillator Circuit XTAL1 XTAL2 System Clock 24.5 MHz 2% Internal Oscillator Clock Multiplier P0.0 8 kB FLASH 8 0 5 1 256 byte SRAM 512 byte XRAM C o SFR Bus r e P0.1 P0.2/XTAL1 P0.3/XTAL2 P 0 Port 0 Latch D r v UART Timer 0, 1, 2, 3 X B A R 3-Chnl PCA/ WDT SMBus P0.4/TX P0.5/RX P0.6/CNVSTR P0.7 CP0 + CP0A - CP0+ CP0- SPI Bus VREF+ VREF– P1.0 VREF Port 1 Latch P1.1 P1.2 P1.3 P1.4/CP0A P 1 AIN0 AIN1 D r v Offset DAC AIN2 AIN3 AIN4 A M U X AIN5 AIN6 AIN7 + Buffer P1.5/CP0 P1.6/IDAC0 P1.7/IDAC1 8-bit IDAC0 16-bit ADC0 PGA + 8-bit IDAC1 C2D Temp Sensor Port 2 Latch P2.0/C2D Figure 1.3. C8051F352 Block Diagram VDD Digital Power GND AV+ AGND Analog Power C2D Debug HW Reset /RST/C2CK POR BrownOut External Oscillator Circuit XTAL1 XTAL2 System Clock x2 24.5 MHz 2% Internal Oscillator P0.0 8 kB FLASH 8 0 5 1 256 byte SRAM 512 byte XRAM C o SFR Bus r e P0.1 P0.3/XTAL2 P0.4/TX D r v UART Timer 0, 1, 2, 3 P0.5/RX P0.6/CNVSTR X B A R 3-Chnl PCA/ WDT SMBus SPI Bus P0.7 CP0 + CP0A - CP0+ CP0- AIN4-7 VREF+ P1.0/AIN4 VREF– VREF Port 1 Latch P1.1/AIN5 AIN0 AIN1 Offset DAC AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 A M U X Buffer + + PGA P 1 P1.2/AIN6 D r v P1.4/CP0A 8-bit IDAC0 16-bit ADC0 P1.3/AIN7 P1.5/CP0 P1.6/IDAC0 P1.7/IDAC1 8-bit IDAC1 C2D Temp Sensor Port 2 Latch Figure 1.4. C8051F353 Block Diagram 20 P0.2/XTAL1 P 0 Port 0 Latch Rev. 1.1 P2.0/C2D C8051F350/1/2/3 1.1. CIP-51™ Microcontroller 1.1.1. Fully 8051 Compatible Instruction Set The C8051F35x devices use Silicon Labs’ proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51™ instruction set. Standard 803x/805x assemblers and compilers can be used to develop software. The C8051F35x family has a superset of all the peripherals included with a standard 8052. 1.1.2. Improved Throughput The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute, and usually have a maximum system clock of 12 to 24 MHz. By contrast, the CIP51 core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more than eight system clock cycles. With the CIP-51's system clock running at 50 MHz, it has a peak throughput of 50 MIPS. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execution time. Clocks to Execute 1 2 2/3 3 3/4 4 4/5 5 8 Number of Instructions 26 50 5 14 7 3 1 2 1 1.1.3. Additional Features The C8051F350/1/2/3 SoC family includes several key enhancements to the CIP-51 core and peripherals to improve performance and ease of use in end applications. An extended interrupt handler allows the numerous analog and digital peripherals to operate independently of the controller core and interrupt the controller only when necessary. By requiring less intervention from the microcontroller core, an interrupt-driven system is more efficient and allows for easier implementation of multi-tasking, real-time systems. Eight reset sources are available: power-on reset circuitry (POR), an on-chip VDD monitor, a Watchdog Timer, a Missing Clock Detector, a voltage level detection from Comparator0, a forced software reset, an external reset pin, and an illegal Flash access protection circuit. Each reset source except for the POR, Reset Input Pin, or Flash error may be disabled by the user in software. The WDT may be permanently enabled in software after a power-on reset during MCU initialization. The internal oscillator is factory calibrated to 24.5 MHz ±2%. An external oscillator drive circuit is also included, allowing an external crystal, ceramic resonator, capacitor, RC, or CMOS clock source to generate the system clock. A clock multiplier allows for operation at up to 50 MHz. An external oscillator can also be extremely useful in low power applications, allowing the MCU to run from a slow (power saving) source, while periodically switching to the fast internal oscillator as needed. Rev. 1.1 21 C8051F350/1/2/3 1.2. On-Chip Debug Circuitry The C8051F350/1/2/3 devices include on-chip Silicon Labs 2-Wire (C2) debug circuitry that provides nonintrusive, full speed, in-circuit debugging of the production part installed in the end application. Silicon Labs' debugging system supports inspection and modification of memory and registers, breakpoints, and single stepping. No additional target RAM, program memory, timers, or communications channels are required. All the digital and analog peripherals are functional and work correctly while debugging. All the peripherals (except for the ADC and SMBus) are stalled when the MCU is halted, during single stepping, or at a breakpoint in order to keep them synchronized. The C8051F350DK development kit provides all the hardware and software necessary to develop application code and perform in-circuit debugging with the C8051F35x MCUs. The kit includes software with a developer's studio and debugger, a C2 debug adapter, a target application board with the associated MCU installed, and the required cables and wall-mount power supply. The development kit requires a computer with Windows 98 SE or later installed. The Silicon Labs IDE interface is a vastly superior developing and debugging configuration, compared to standard MCU emulators that use on-board "ICE Chips" and require the MCU in the application board to be socketed. Silicon Labs' debug paradigm increases ease of use and preserves the performance of the precision analog peripherals. Silicon Labs Integrated Development Environment WINDOWS 98 SE or later Debug Adapter C2 (x2), VDD, GND VDD TARGET PCB GND C8051F350 Figure 1.5. Development/In-System Debug Diagram 22 Rev. 1.1 C8051F350/1/2/3 1.3. On-Chip Memory The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as four banks of general purpose registers, and the next 16 bytes can be byte addressable or bit addressable. Program memory consists of 8 kB bytes of Flash. This memory may be reprogrammed in-system in 512 byte sectors, and requires no special off-chip programming voltage. DATA MEMORY (RAM) INTERNAL DATA ADDRESS SPACE PROGRAM/DATA MEMORY (Flash) 0x1FFF 0x1E00 0xFF RESERVED 0x1DFF 0x80 0x7F Upper 128 RAM (Indirect Addressing Only) (Direct and Indirect Addressing) 8 kB Flash (In-System Programmable in 512 Byte Sectors) 0x30 0x2F 0x20 0x1F 0x00 Bit Addressable Special Function Register's (Direct Addressing Only) Lower 128 RAM (Direct and Indirect Addressing) General Purpose Registers EXTERNAL DATA ADDRESS SPACE 0x0000 0xFFFF Same 512 bytes as from 0x0000 to 0x01FF, wrapped on 512-byte boundaries 0x0200 0x01FF 0x0000 XRAM - 512 Bytes (accessable using MOVX instruction) Figure 1.6. Memory Map Rev. 1.1 23 C8051F350/1/2/3 1.4. 24 or 16-Bit Analog to Digital Converter (ADC0) The C8051F350/1/2/3 include a fully-differential, 24-bit (C8051F350/1) or 16-bit (C8051F352/3) SigmaDelta Analog to Digital Converter (ADC) with on-chip calibration capabiliites. Two separate decimation filters can be programmed for throughputs of up to 1 kHz. An internal 2.5 V reference is available, or a differential external reference can be used for ratiometric measurements. A Programmable Gain Amplifier (PGA) is included, with eight gain settings up to 128x. An analog front-end multiplexer connects the differential inputs to eight external pins, the internal temperature sensor, or AGND. The on-chip input buffers can be used to provide a high input impedance for direct connection to sensitive transducers. An 8-bit offset DAC allows for correction of large input offset voltages. AV+ Internal 2.5V or External VREF Burnout Current Sources Eight External Inputs Temperature Sensor AIN+ Σ SINC3 Filter PGA AIN- Modulator Σ Input Buffers AGND Fast Filter 1x to 128x 8-Bit Offset DAC Figure 1.7. ADC0 Block Diagram 24 Rev. 1.1 C8051F350/1/2/3 1.5. Two 8-bit Current-Mode DACs The C8051F350/1/2/3 devices include two 8-bit current-mode Digital-to-Analog Converters (IDACs). The maximum current output of the IDACs can be adjusted for four different current settings; 0.25 mA, 0.5 mA, 1 mA, and 2 mA. A flexible output update mechanism allows for seamless full-scale changes, and supports jitter-free updates for waveform generation. IDAC updates can be performed on-demand, scheduled on a Timer overflow, or synchronized with an external signal. Figure 1.8 shows a block diagram of the IDAC circuitry. 8-bit Digital Input 8 Latch 8 8-bit Digital Input 8 Latch Data Write Timer 0 Timer 1 Timer 2 Timer 3 CNVSTR 8 IDA0 Current Output IDA1 Current Output Data Write Timer 0 Timer 1 Timer 2 Timer 3 CNVSTR Figure 1.8. IDAC Block Diagram Rev. 1.1 25 C8051F350/1/2/3 1.6. Programmable Comparator C8051F350/1/2/3 devices include a software-configurable voltage comparator with an input multiplexer. The Comparator offers programmable response time and hysteresis and two outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0), or an asynchronous “raw” output (CP0A). Comparator interrupts may be generated on rising, falling, or both edges. When in IDLE mode, these interrupts may be used as a “wake-up” source for the processor. Comparator0 may also be configured as a reset source. A block diagram of the Comparator is shown in Figure 1.9. VDD Port I/O Pins Multiplexer Interrupt Logic + D - SET CLR Q Q D SET CLR Q CP0 (synchronous output) Q (SYNCHRONIZER) CP0A (asynchronous output) GND Reset Decision Tree Figure 1.9. Comparator0 Block Diagram 1.7. Serial Ports The C8051F350/1/2/3 Family includes an SMBus/I2C interface, a full-duplex UART with enhanced baud rate configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention. 26 Rev. 1.1 C8051F350/1/2/3 1.8. Port Input/Output C8051F350/1/2/3 devices include 17 I/O pins. Port pins are organized as two byte-wide ports and one 1-bit port. The port pins behave like typical 8051 ports with a few enhancements. Each port pin can be configured as a digital or analog I/O pin. Pins selected as digital I/O can be configured for push-pull or open-drain operation. The “weak pull-ups” that are fixed on typical 8051 devices may be globally disabled to save power. The Digital Crossbar allows mapping of internal digital system resources to port I/O pins. On-chip conter/timers, serial buses, hardware interrupts, and other digital signals can be configured to appear on the port pins using the Crossbar control resgiters. This allows the user to select the exact mix of general-purpose port I/O, digital, and analog resources needed for the application. XBR0, XBR1, PnSKIP Registers PnMDOUT, PnMDIN Registers Priority Decoder (Internal Digital Signals) Highest Priority CP0 Outputs 2 Digital Crossbar 4 SPI SMBus 8 4 T0, T1 8 2 SYSCLK PCA Lowest Priority 2 UART P0 I/O Cells P0.0 P1 I/O Cells P1.0 P0.7 P1.7 2 (Port Latches) 8 P0 (P0.0-P0.7) P1 (P1.0-P1.7) 8 P2 P2 I/O Cell (P2.0) P2.0 Figure 1.10. Port I/O Functional Block Diagram Rev. 1.1 27 C8051F350/1/2/3 1.9. Programmable Counter Array The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer and three 16-bit capture/compare modules. The counter/timer is driven by a programmable timebase that can select between six sources: system clock, system clock divided by four, system clock divided by twelve, the external oscillator clock source divided by 8, Timer 0 overflow, or an external clock signal on the External Clock nput (ECI) input pin. Each capture/compare module may be configured to operate independently in one of six modes: EdgeTriggered Capture, Software Timer, High-Speed Output, Frequency Output, 8-Bit PWM, or 16-Bit PWM. Additionally, PCA Module 2 may be used as a watchdog timer (WDT), and is enabled in this mode following a system reset. The PCA Capture/Compare Module I/O and the External Clock Input may be routed to Port I/O using the digital crossbar. SYSCLK/12 SYSCLK/4 Timer 0 Overflow ECI PCA CLOCK MUX 16-Bit Counter/Timer SYSCLK External Clock/8 Capture/Compare Module 0 Capture/Compare Module 1 Capture/Compare Module 2 / WDT Port I/O Figure 1.11. PCA Block Diagram 28 Rev. 1.1 CEX2 CEX1 CEX0 ECI Crossbar C8051F350/1/2/3 2. Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings Parameter Min Typ Max Units Ambient temperature under bias –55 — 125 °C Storage Temperature –65 — 150 °C Voltage on AIN0.0–AIN0.7, VREF+, and VREF– with respect to DGND –0.3 — VDD + 0.3 V Voltage on any Port 0, 1, or 2 Pin or /RST with respect to DGND –0.3 — 5.8 V Voltage on VDD with respect to DGND –0.3 — 4.2 V Voltage on AV+ with respect to AGND –0.3 — 4.2 V Maximum output current sunk by any Port 0, 1, or 2 pin — — 100 mA Maximum output current sunk by any other I/O pin — — 50 mA Maximum output current sourced by any Port 0, 1, or 2 pin — — 100 mA Maximum output current sourced by any other I/O pin — — 50 mA Maximum Total current through VDD, AV+, DGND, and AGND — — 500 mA Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Rev. 1.1 29 C8051F350/1/2/3 3. Global DC Electrical Characteristics Table 3.1. Global DC Electrical Characteristics –40 to +85 °C, 25 MHz System Clock unless otherwise specified. Parameter Analog Supply Voltage Conditions 1 Min Typ Max Units 2.7 3.0 3.6 V Analog Supply Current Internal REF, ADC, IDACs, Comparators all active — 0.75 1.3 mA Analog Supply Current with analog sub-systems inactive Internal REF, ADC, IDACs, Comparators all disabled, oscillator disabled — 5 µs. Initialize the Multiplier with the MULINIT bit (CLKMUL | = 0xC0). Poll for MULRDY => ‘1’. Important Note: When using an external oscillator as the input to the Clock Multiplier, the external source must be enabled and stable before the Multiplier is initialized. See Section “17.4. System Clock Selection’ on page 136 for details on selecting an external oscillator source. SFR Definition 17.4. CLKMUL: Clock Multiplier Control R/W MULEN Bit7 R/W R MULINIT MULRDY Bit6 Bit5 R/W R/W R/W — — — Bit4 Bit3 Bit2 R/W R/W MULSEL Bit1 Reset Value 00000000 Bit0 SFR Address: 0xBE Bit7: MULEN: Clock Multiplier Enable 0: Clock Multiplier disabled. 1: Clock Multiplier enabled. Bit6: MULINIT: Clock Multiplier Initialize This bit should be a ‘0’ when the Clock Multiplier is enabled. Once enabled, writing a ‘1’ to this bit will initialize the Clock Multiplier. The MULRDY bit reads ‘1’ when the Clock Multiplier is stabilized. Bit5: MULRDY: Clock Multiplier Ready This read-only bit indicates the status of the Clock Multiplier. 0: Clock Multiplier not ready. 1: Clock Multiplier ready (locked). Bits4–2: Unused. Read = 000b; Write = don’t care. Bits1–0: MULSEL: Clock Multiplier Input Select These bits select the clock supplied to the Clock Multiplier. MULSEL 00 01 10 11 Selected Input Clock Internal Oscillator / 2 External Oscillator External Oscillator / 2 RESERVED Rev. 1.1 Clock Multipler Output Internal Oscillator x 2 External Oscillator x 4 External Oscillator x 2 RESERVED 135 C8051F350/1/2/3 17.4. System Clock Selection The internal oscillator requires little start-up time and may be selected as the system clock immediately following the OSCICN write that enables the internal oscillator. External crystals and ceramic resonators typically require a start-up time before they are settled and ready for use. The Crystal Valid Flag (XTLVLD in register OSCXCN) is set to ‘1’ by hardware when the external oscillator is settled. To avoid reading a false XTLVLD, in crystal mode software should delay at least 1 ms between enabling the external oscillator and checking XTLVLD. RC and C modes typically require no startup time. The CLKSL[1:0] bits in register CLKSEL select which oscillator source is used as the system clock. CLKSL[1:0] must be set to 01b for the system clock to run from the external oscillator; however the external oscillator may still clock certain peripherals (timers, PCA) when the internal oscillator is selected as the system clock. The system clock may be switched on-the-fly between the internal oscillator, external oscillator, and Clock Multiplier so long as the selected clock source is enabled and has settled. SFR Definition 17.5. CLKSEL: Clock Select R R R R R R — — — — — — Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 R/W R/W CLKSL Bit1 Reset Value 00000000 Bit0 SFR Address: 0xA9 Bits7–2: Unused. Read = 000000b; Write = don’t care. Bits1–0: CLKSL1–0: System Clock Select These bits select the system clock source. CLKSL 00 01 10 11 Selected Clock Internal Oscillator (as determined by the IFCN bits in register OSCICN) External Oscillator Clock Multiplier RESERVED Table 17.1. Oscillator Electrical Characteristics –40 to +85 °C unless otherwise specified. Parameter Internal Oscillator Frequency Internal Oscillator Supply Current (from VDD) 136 Conditions Reset Frequency OSCICN.7 = 1 Rev. 1.1 Min 24 — Typ 24.5 450 Max 25 — Units MHz µA C8051F350/1/2/3 18. Port Input/Output Digital and analog resources are available through 17 I/O pins. Port pins are organized as two byte-wide Ports and one 1-bit Port. Each of the Port pins can be defined as general-purpose I/O (GPIO) or analog input/output; Port pins P0.0 - P1.7 can be assigned to one of the internal digital resources as shown in Figure 18.3. The designer has complete control over which functions are assigned, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder. Note that the state of a Port I/O pin can always be read in the corresponding Port latch, regardless of the Crossbar settings. The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder (Figure 18.3 and Figure 18.4). The registers XBR0 and XBR1, defined in SFR Definition 18.1 and SFR Definition 18.2, are used to select internal digital functions. All Port I/Os are 5 V tolerant (refer to Figure 18.2 for the Port cell circuit). The Port I/O cells are configured as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1,2). Complete Electrical Specifications for Port I/O are given in Table 18.1 on page 150. XBR0, XBR1, PnSKIP Registers PnMDOUT, PnMDIN Registers Priority Decoder (Internal Digital Signals) Highest Priority 2 UART CP0 Outputs Digital Crossbar 4 SPI SMBus 8 4 T0, T1 8 2 SYSCLK PCA Lowest Priority 2 P0 I/O Cells P0.0 P1 I/O Cells P1.0 P0.7 P1.7 2 8 (Port Latches) P0 (P0.0-P0.7) 8 P1 P2 (P1.0-P1.7) P2 I/O Cell (P2.0) P2.0 Figure 18.1. Port I/O Functional Block Diagram Rev. 1.1 137 C8051F350/1/2/3 /WEAK-PULLUP VDD PUSH-PULL /PORT-OUTENABLE VDD (WEAK) PORT PAD PORT-OUTPUT GND Analog Select ANALOG INPUT PORT-INPUT Figure 18.2. Port I/O Cell Block Diagram 138 Rev. 1.1 C8051F350/1/2/3 18.1. Priority Crossbar Decoder The Priority Crossbar Decoder (Figure 18.3) assigns a priority to each I/O function, starting at the top with UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that resource (excluding UART0, which will be assigned to pins P0.4 and P0.5, and the Comparator0 outputs, which will be assigned to P1.4 and P1.5). If a Port pin is assigned, the Crossbar skips that pin when assigning the next selected resource. Additionally, the Crossbar will skip Port pins whose associated bits in the PnSKIP registers are set. The PnSKIP registers allow software to skip Port pins that are to be used for analog input, dedicated functions, or GPIO. Important Note on Crossbar Configuration: If a Port pin is claimed by a peripheral without use of the Crossbar, its corresponding PnSKIP bit should be set. This applies to P0.3 and/or P0.2 for the external oscillator, P0.6 for the external CNVSTR signal, P1.6 for IDA0, P1.7 for IDA1, and any selected ADC or comparator inputs. The Crossbar skips selected pins as if they were already assigned, and moves to the next unassigned pin. Figure 18.3 shows the Crossbar Decoder priority with no Port pins skipped (P0SKIP, P1SKIP = 0x00); Figure 18.4 shows the Crossbar Decoder priority with the XTAL1 (P0.2) and XTAL2 (P0.3) pins skipped (P0SKIP = 0x0C). P0 SF Signals PIN I/O 0 1 x1 2 x2 3 P1 4 CNVSTR 5 6 7 0 1 2 0 0 0 P2 3 4 5 0 0 0 IDA0 IDA1 6 7 0 TX0 RX0 CP0A CP0 SCK MISO MOSI (*4-Wire SPI Only) NSS* SDA SCL /SYSCLK CEX0 CEX1 CEX2 ECI T0 T1 0 0 0 0 0 0 0 0 0 0 P1SKIP[0:7] P0SKIP[0:7] Port pin potentially assignable to peripheral SF Signals Special Function Signals are not assigned by the crossbar. When these signals are enabled, the CrossBar must be manually configured to skip their corresponding port pins. Figure 18.3. Crossbar Priority Decoder with No Pins Skipped Rev. 1.1 139 C8051F350/1/2/3 P0 SF Signals PIN I/O 0 1 x1 2 x2 3 P1 4 5 CNVSTR 6 7 0 1 2 P2 3 4 5 0 0 0 IDA0 IDA1 6 7 0 TX0 RX0 CP0A CP0 SCK MISO MOSI (*4-Wire SPI Only) NSS* SDA SCL /SYSCLK CEX0 CEX1 CEX2 ECI T0 T1 0 0 1 1 0 0 0 0 0 0 0 P0SKIP[0:7] 0 0 P1SKIP[0:7] Port pin potentially assignable to peripheral SF Signals Special Function Signals are not assigned by the crossbar. When these signals are enabled, the CrossBar must be manually configured to skip their corresponding port pins. Figure 18.4. Crossbar Priority Decoder with Crystal Pins Skipped Registers XBR0 and XBR1 are used to assign the digital I/O resources to the physical I/O Port pins. Note that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus (SDA and SCL); when the UART is selected, the Crossbar assigns both pins associated with the UART (TX and RX). UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned to P0.4; UART RX0 is always assigned to P0.5. Comparator outputs are also fixed: CP0A will appear only on P1.4, CP0 will appear only on P1.5. Standard Port I/Os appear contiguously after the prioritized functions have been assigned. Important Note: The SPI can be operated in either 3-wire or 4-wire modes, pending the state of the NSSMD1–NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not be routed to a Port pin. 140 Rev. 1.1 C8051F350/1/2/3 18.2. Port I/O Initialization Port I/O initialization consists of the following steps: Step 1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN). Step 2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port Output Mode register (PnMDOUT). Step 3. Select any pins to be skipped by the I/O Crossbar using the Port Skip registers (PnSKIP). Step 4. Assign Port pins to desired peripherals. Step 5. Enable the Crossbar (XBARE = ‘1’). All Port pins must be configured as either analog or digital inputs. Any pins to be used as Comparator or ADC inputs should be configured as an analog inputs. When a pin is configured as an analog input, its weak pull-up, digital driver, and digital receiver are disabled. This process saves power and reduces noise on the analog input. Pins configured as digital inputs may still be used by analog peripherals; however this practice is not recommended. Additionally, all analog input pins should be configured to be skipped by the Crossbar (accomplished by setting the associated bits in PnSKIP). Port input mode is set in the PnMDIN register, where a ‘1’ indicates a digital input, and a ‘0’ indicates an analog input. All pins default to digital inputs on reset. See SFR Definition 18.4 for the PnMDIN register details. The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMDOUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is required even for the digital resources selected in the XBRn registers, and is not automatic. The only exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the PnMDOUT settings. When the WEAKPUD bit in XBR1 is ‘0’, a weak pull-up is enabled for all Port I/O configured as open-drain. WEAKPUD does not affect the push-pull Port I/O. Furthermore, the weak pull-up is turned off on an output that is driving a ‘0’ to avoid unnecessary power dissipation. Registers XBR0 and XBR1 must be loaded with the appropriate values to select the digital I/O functions required by the design. Setting the XBARE bit in XBR1 to ‘1’ enables the Crossbar. Until the Crossbar is enabled, the external pins remain as standard Port I/O (in input mode), regardless of the XBRn Register settings. For given XBRn Register settings, one can determine the I/O pin-out using the Priority Decode Table. The Crossbar must be enabled to use Port pins as standard Port I/O in output mode. Port output drivers are disabled while the Crossbar is disabled. Rev. 1.1 141 C8051F350/1/2/3 SFR Definition 18.1. XBR0: Port I/O Crossbar Register 0 R R R/W R/W R/W R/W R/W R/W Reset Value — — CP0AE CP0E SYSCKE SMB0E SPI0E URT0E 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xE1 Bits7–6: UNUSED. Read = 00b, Write = don’t care. Bit5: CP0AE: Comparator0 Asynchronous Output Enable 0: Asynchronous CP0 unavailable at Port pin. 1: Asynchronous CP0 routed to Port pin P1.4. Bit4: CP0E: Comparator0 Output Enable 0: CP0 unavailable at Port pin. 1: CP0 routed to Port pin P1.5. Bit3: SYSCKE: /SYSCLK Output Enable 0: /SYSCLK unavailable at Port pin. 1: /SYSCLK output routed to Port pin. Bit2: SMB0E: SMBus I/O Enable 0: SMBus I/O unavailable at Port pins. 1: SMBus I/O routed to Port pins. Bit1: SPI0E: SPI I/O Enable 0: SPI I/O unavailable at Port pins. 1: SPI I/O routed to Port pins. Note that the SPI can be assigned either 3 or 4 GPIO pins. Bit0: URT0E: UART I/O Output Enable 0: UART I/O unavailable at Port pin. 1: UART TX0, RX0 routed to Port pins P0.4 and P0.5. 142 Rev. 1.1 C8051F350/1/2/3 SFR Definition 18.2. XBR1: Port I/O Crossbar Register 1 R/W R/W R/W R/W R/W R WEAKPUD XBARE T1E T0E ECIE — Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 R/W R/W PCA0ME Bit1 Reset Value 00000000 Bit0 SFR Address: 0xE2 Bit7: WEAKPUD: Port I/O Weak Pull-up Disable. 0: Weak Pull-ups enabled (except for Ports whose I/O are configured as analog input). 1: Weak Pull-ups disabled. Bit6: XBARE: Crossbar Enable. 0: Crossbar disabled. 1: Crossbar enabled. Bit5: T1E: T1 Enable 0: T1 unavailable at Port pin. 1: T1 routed to Port pin. Bit4: T0E: T0 Enable 0: T0 unavailable at Port pin. 1: T0 routed to Port pin. Bit3: ECIE: PCA0 External Counter Input Enable 0: ECI unavailable at Port pin. 1: ECI routed to Port pin. Bit2: Unused. Read = 0b. Write = don’t care. Bits1–0: PCA0ME: PCA Module I/O Enable Bits. 00: All PCA I/O unavailable at Port pins. 01: CEX0 routed to Port pin. 10: CEX0, CEX1 routed to Port pins. 11: CEX0, CEX1, CEX2 routed to Port pins. Rev. 1.1 143 C8051F350/1/2/3 18.3. General Purpose Port I/O Port pins that remain unassigned by the Crossbar and are not used by analog peripherals can be used for general purpose I/O. Ports P0–P2 are accessed through corresponding special function registers (SFRs) that are both byte addressable and bit addressable. When writing to a Port, the value written to the SFR is latched to maintain the output data value at each pin. When reading, the logic levels of the Port's input pins are returned regardless of the XBRn settings (i.e., even when the pin is assigned to another signal by the Crossbar, the Port register can always read its corresponding Port I/O pin). The exception to this is the execution of the read-modify-write instructions that target a Port Latch register as the destination. The read-modify-write instructions when operating on a Port SFR are the following: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ and MOV, CLR or SETB, when the destination is an individual bit in a Port SFR. For these instructions, the value of the register (not the pin) is read, modified, and written back to the SFR. 144 Rev. 1.1 C8051F350/1/2/3 SFR Definition 18.3. P0: Port0 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit Addressable SFR Address: 0x80 Bits7–0: P0.[7:0] Write - Output appears on I/O pins per Crossbar Registers. 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P0MDOUT.n bit = 0). Read - Always reads ‘0’ if selected as analog input in register P0MDIN. Directly reads Port pin when configured as digital input. 0: P0.n pin is logic low. 1: P0.n pin is logic high. SFR Definition 18.4. P0MDIN: Port0 Input Mode R/W R/W R/W R/W R/W R/W R/W R/W Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset Value 11111111 SFR Address: 0xF1 Bits7–0: Analog Input Configuration Bits for P0.7–P0.0 (respectively). Port pins configured as analog inputs have their weak pull-up, digital driver, and digital receiver disabled. 0: Corresponding P0.n pin is configured as an analog input. 1: Corresponding P0.n pin is not configured as an analog input. Rev. 1.1 145 C8051F350/1/2/3 SFR Definition 18.5. P0MDOUT: Port0 Output Mode R/W R/W R/W R/W R/W R/W R/W R/W Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset Value 00000000 SFR Address: 0xA4 Bits7–0: Output Configuration Bits for P0.7–P0.0 (respectively): ignored if corresponding bit in register P0MDIN is logic 0. 0: Corresponding P0.n Output is open-drain. 1: Corresponding P0.n Output is push-pull. (Note: When SDA and SCL appear on any of the Port I/O, each are open-drain regardless of the value of P0MDOUT). SFR Definition 18.6. P0SKIP: Port0 Skip R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xD4 Bits7–0: P0SKIP[7:0]: Port0 Crossbar Skip Enable Bits. These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as analog inputs (for ADC or Comparator) or used as special functions (VREF input, external oscillator circuit, CNVSTR input) should be skipped by the Crossbar. 0: Corresponding P0.n pin is not skipped by the Crossbar. 1: Corresponding P0.n pin is skipped by the Crossbar. 146 Rev. 1.1 C8051F350/1/2/3 SFR Definition 18.7. P1: Port1 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit Addressable SFR Address: 0x90 Bits7–0: P1.[7:0] Write - Output appears on I/O pins per Crossbar Registers. 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P1MDOUT.n bit = 0). Read - Always reads ‘0’ if selected as analog input in register P1MDIN. Directly reads Port pin when configured as digital input. 0: P1.n pin is logic low. 1: P1.n pin is logic high. SFR Definition 18.8. P1MDIN: Port1 Input Mode R/W R/W R/W R/W R/W R/W R/W R/W Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset Value 11111111 SFR Address: 0xF2 Bits7–0: Analog Input Configuration Bits for P1.7–P1.0 (respectively). Port pins configured as analog inputs have their weak pull-up, digital driver, and digital receiver disabled. 0: Corresponding P1.n pin is configured as an analog input. 1: Corresponding P1.n pin is not configured as an analog input. Rev. 1.1 147 C8051F350/1/2/3 SFR Definition 18.9. P1MDOUT: Port1 Output Mode R/W R/W R/W R/W R/W R/W R/W R/W Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset Value 00000000 SFR Address: 0xA5 Bits7–0: Output Configuration Bits for P1.7–P1.0 (respectively): ignored if corresponding bit in register P1MDIN is logic 0. 0: Corresponding P1.n Output is open-drain. 1: Corresponding P1.n Output is push-pull. SFR Definition 18.10. P1SKIP: Port1 Skip R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xD5 Bits7–0: P1SKIP[7:0]: Port1 Crossbar Skip Enable Bits. These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as analog inputs (for ADC or Comparator) or used as special functions (VREF input, external oscillator circuit, CNVSTR input) should be skipped by the Crossbar. 0: Corresponding P1.n pin is not skipped by the Crossbar. 1: Corresponding P1.n pin is skipped by the Crossbar. 148 Rev. 1.1 C8051F350/1/2/3 SFR Definition 18.11. P2: Port2 R R R R R R R R/W Reset Value — — — — — — — P2.0 00000001 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit Addressable SFR Address: 0xA0 Bits7–1: Unused. Read = 0000000b. Write = don’t care. Bit0: P2.0 Write - Output appears on I/O pins per Crossbar Registers. 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P2MDOUT.n bit = 0). Read - Directly reads Port pin. 0: P2.n pin is logic low. 1: P2.n pin is logic high. SFR Definition 18.12. P2MDOUT: Port2 Output Mode R R R R R R R — — — — — — — Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 R/W Reset Value 00000000 Bit0 SFR Address: 0xA6 Bits7–1: Unused. Read = 0000000b. Write = don’t care. Bit0: Output Configuration Bit for P2.0. 0: P2.0 Output is open-drain. 1: P2.0 Output is push-pull. Rev. 1.1 149 C8051F350/1/2/3 Table 18.1. Port I/O DC Electrical Characteristics VDD = 2.7 to 3.6 V, –40 to +85 °C unless otherwise specified. Parameters Conditions Min Typ Max Units IOH = –3 mA, Port I/O push-pull IOH = –10 µA, Port I/O push-pull IOH = –10 mA, Port I/O push-pull VDD – 0.7 VDD – 0.1 — — — VDD – 0.8 — — — V Output High Voltage Output Low Voltage IOL = 8.5 mA IOL = 10 µA IOL = 25 mA — — — — — 1.0 0.6 0.1 — V Input High Voltage 2.0 — — V Input Low Voltage — — 0.8 V — — ±1 50 µA 25 Input Leakage Current 150 Weak Pull-up Off Weak Pull-up On, VIN = 0 V Rev. 1.1 C8051F350/1/2/3 19. SMBus The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specification, version 1.1, and compatible with the I2C serial bus. Reads and writes to the interface by the system controller are byte oriented with the SMBus interface autonomously controlling the serial transfer of the data. Data can be transferred at up to 1/20th of the system clock as a master or slave (this can be faster than allowed by the SMBus specification, depending on the system clock used). A method of extending the clock-low duration is available to accommodate devices with different speed capabilities on the same bus. The SMBus interface may operate as a master and/or slave, and may function on a bus with multiple masters. The SMBus provides control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration logic, and START/STOP control and generation. Three SFRs are associated with the SMBus: SMB0CF configures the SMBus; SMB0CN controls the status of the SMBus; and SMB0DAT is the data register, used for both transmitting and receiving SMBus data and slave addresses. SMB0CN MT S S A A A S A X T T CRC I SMAOK B K T O R L E D QO R E S T SMB0CF E I B E S S S S N N U XMMMM S H S T B B B B M Y H T F CC B OOT S S L E E 1 0 D 00 T0 Overflow 01 T1 Overflow 10 TMR2H Overflow 11 TMR2L Overflow SMBUS CONTROL LOGIC Interrupt Request Arbitration SCL Synchronization SCL Generation (Master Mode) SDA Control Data Path IRQ Generation Control SCL FILTER SCL Control C R O S S B A R N SDA Control SMB0DAT 7 6 5 4 3 2 1 0 Port I/O SDA FILTER N Figure 19.1. SMBus Block Diagram Rev. 1.1 151 C8051F350/1/2/3 19.1. Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents: 1. The I2C-Bus and How to Use It (including specifications), Philips Semiconductor. 2. The I2C-Bus Specification -- Version 2.0, Philips Semiconductor. 3. System Management Bus Specification -- Version 1.1, SBS Implementers Forum. 19.2. SMBus Configuration Figure 19.2 shows a typical SMBus configuration. The SMBus specification allows any recessive voltage between 3.0 V and 5.0 V; different devices on the bus may operate at different voltage levels. The bi-directional SCL (serial clock) and SDA (serial data) lines must be connected to a positive power supply voltage through a pull-up resistor or similar circuit. Every device connected to the bus must have an open-drain or open-collector output for both the SCL and SDA lines, so that both are pulled high (recessive state) when the bus is free. The maximum number of devices on the bus is limited only by the requirement that the rise and fall times on the bus not exceed 300 ns and 1000 ns, respectively. VDD = 5V VDD = 3V VDD = 5V VDD = 3V Master Device Slave Device 1 Slave Device 2 SDA SCL Figure 19.2. Typical SMBus Configuration 19.3. SMBus Operation Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver (WRITE), and data transfers from an addressed slave transmitter to a master receiver (READ). The master device initiates both types of data transfers and provides the serial clock pulses on SCL. The SMBus interface may operate as a master or a slave, and multiple master devices on the same bus are supported. If two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme is employed with a single master always winning the arbitration. Note that it is not necessary to specify one device as the Master in a system; any device who transmits a START and a slave address becomes the master for the duration of that transfer. A typical SMBus transaction consists of a START condition followed by an address byte (Bits7–1: 7-bit slave address; Bit0: R/W direction bit), one or more bytes of data, and a STOP condition. Each byte that is received (by a master or slave) must be acknowledged (ACK) with a low SDA during a high SCL (see Figure 19.3). If the receiving device does not ACK, the transmitting device will read a NACK (not acknowledge), which is a high SDA during a high SCL. 152 Rev. 1.1 C8051F350/1/2/3 The direction bit (R/W) occupies the least-significant bit position of the address byte. The direction bit is set to logic 1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation. All transactions are initiated by a master, with one or more addressed slave devices as the target. The master generates the START condition and then transmits the slave address and direction bit. If the transaction is a WRITE operation from the master to the slave, the master transmits the data a byte at a time waiting for an ACK from the slave at the end of each byte. For READ operations, the slave transmits the data waiting for an ACK from the master at the end of each byte. At the end of the data transfer, the master generates a STOP condition to terminate the transaction and free the bus. Figure 19.3 illustrates a typical SMBus transaction. SCL SDA SLA6 START SLA5-0 Slave Address + R/W R/W D7 ACK D6-0 Data Byte NACK STOP Figure 19.3. SMBus Transaction 19.3.1. Arbitration A master may start a transfer only if the bus is free. The bus is free after a STOP condition or after the SCL and SDA lines remain high for a specified time (see Section “19.3.4. SCL High (SMBus Free) Timeout’ on page 154). In the event that two or more devices attempt to begin a transfer at the same time, an arbitration scheme is employed to force one master to give up the bus. The master devices continue transmitting until one attempts a HIGH while the other transmits a LOW. Since the bus is open-drain, the bus will be pulled LOW. The master attempting the HIGH will detect a LOW SDA and lose the arbitration. The winning master continues its transmission without interruption; the losing master becomes a slave and receives the rest of the transfer if addressed. This arbitration scheme is non-destructive: one device always wins, and no data is lost. Rev. 1.1 153 C8051F350/1/2/3 19.3.2. Clock Low Extension SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line LOW to extend the clock low period, effectively decreasing the serial clock frequency. 19.3.3. SCL Low Timeout If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore, the master cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than 25 ms as a “timeout” condition. Devices that have detected the timeout condition must reset the communication no later than 10 ms after detecting the timeout condition. When the SMBTOE bit in SMB0CF is set, Timer 3 is used to detect SCL low timeouts. Timer 3 is forced to reload when SCL is high, and allowed to count when SCL is low. With Timer 3 enabled and configured to overflow after 25 ms (and SMBTOE set), the Timer 3 interrupt service routine can be used to reset (disable and re-enable) the SMBus in the event of an SCL low timeout. 19.3.4. SCL High (SMBus Free) Timeout The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 µs, the bus is designated as free. When the SMBFTE bit in SMB0CF is set, the bus will be considered free if SCL and SDA remain high for more than 10 SMBus clock source periods. If the SMBus is waiting to generate a Master START, the START will be generated following this timeout. Note that a clock source is required for free timeout detection, even in a slave-only implementation. 154 Rev. 1.1 C8051F350/1/2/3 19.4. Using the SMBus The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting control for serial transfers; higher level protocol is determined by user software. The SMBus interface provides the following application-independent features: • • • • • • • Byte-wise serial data transfers Clock signal generation on SCL (Master Mode only) and SDA data synchronization Timeout/bus error recognition, as defined by the SMB0CF configuration register START/STOP timing, detection, and generation Bus arbitration Interrupt generation Status information SMBus interrupts are generated for each data byte or slave address that is transferred. When transmitting, this interrupt is generated after the ACK cycle so that software may read the received ACK value; when receiving data, this interrupt is generated before the ACK cycle so that software may define the outgoing ACK value. See Section “19.5. SMBus Transfer Modes’ on page 163 for more details on transmission sequences. Interrupts are also generated to indicate the beginning of a transfer when a master (START generated), or the end of a transfer when a slave (STOP detected). Software should read the SMB0CN (SMBus Control register) to find the cause of the SMBus interrupt. The SMB0CN register is described in Section “19.4.2. SMB0CN Control Register’ on page 159; Table 19.4 provides a quick SMB0CN decoding reference. SMBus configuration options include: • • • • Timeout detection (SCL Low Timeout and/or Bus Free Timeout) SDA setup and hold time extensions Slave event enable/disable Clock source selection These options are selected in the SMB0CF register, as described in Section “19.4.1. SMBus Configuration Register’ on page 156. Rev. 1.1 155 C8051F350/1/2/3 19.4.1. SMBus Configuration Register The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes, select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the INH bit. With slave events inhibited, the SMBus interface will still monitor the SCL and SDA pins; however, the interface will NACK all received addresses and will not generate any slave interrupts. When the INH bit is set, all slave events will be inhibited following the next START (interrupts will continue for the duration of the current transfer). Table 19.1. SMBus Clock Source Selection SMBCS1 0 0 1 1 SMBCS0 0 1 0 1 SMBus Clock Source Timer 0 Overflow Timer 1 Overflow Timer 2 High Byte Overflow Timer 2 Low Byte Overflow The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or when the Free Timeout detection is enabled. When operating as a master, overflows from the selected source determine the absolute minimum SCL low and high times as defined in Equation 19.1. Note that the selected clock source may be shared by other peripherals so long as the timer is left running at all times. For example, Timer 1 overflows may generate the SMBus and UART baud rates simultaneously. Timer configuration is covered in Section “22. Timers’ on page 195. 1 T HighMin = T LowMin = ---------------------------------------------f ClockSourceOverflow Equation 19.1. Minimum SCL High and Low Times The selected clock source should be configured to establish the minimum SCL High and Low times as per Equation 19.1. When the interface is operating as a master (and SCL is not driven or extended by any other devices on the bus), the typical SMBus bit rate is approximated by Equation 19.2. f ClockSourceOverflow BitRate = ---------------------------------------------3 Equation 19.2. Typical SMBus Bit Rate 156 Rev. 1.1 C8051F350/1/2/3 Figure 19.4 shows the typical SCL generation described by Equation 19.2. Notice that THIGH is typically twice as large as TLOW. The actual SCL output may vary due to other devices on the bus (SCL may be extended low by slower slave devices, or driven low by contending master devices). The bit rate when operating as a master will never exceed the limits defined by equation Equation 19.1. Timer Source Overflows SCL TLow SCL High Timeout THigh Figure 19.4. Typical SMBus SCL Generation Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA setup time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high. The minimum SDA hold time defines the absolute minimum time that the current SDA value remains stable after SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 19.2 shows the minimum setup and hold times for the two EXTHOLD settings. Setup and hold time extensions are typically necessary when SYSCLK is above 10 MHz. Table 19.2. Minimum SDA Setup and Hold Times EXTHOLD Minimum SDA Setup Time Tlow – 4 system clocks Minimum SDA Hold Time 0 OR 3 system clocks 1 1 system clock + s/w delay* 11 system clocks 12 system clocks *Note: Setup Time for ACK bit transmissions and the MSB of all data transfers. The s/w delay occurs between the time SMB0DAT or ACK is written and when SI is cleared. Note that if SI is cleared in the same write that defines the outgoing ACK value, s/w delay is zero. With the SMBTOE bit set, Timer 3 should be configured to overflow after 25 ms in order to detect SCL low timeouts (see Section “19.3.3. SCL Low Timeout’ on page 154). The SMBus interface will force Timer 3 to reload while SCL is high, and allow Timer 3 to count when SCL is low. The Timer 3 interrupt service routine should be used to reset SMBus communication by disabling and re-enabling the SMBus. SMBus Free Timeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see Figure 19.4). When a Free Timeout is detected, the interface will respond as if a STOP was detected (an interrupt will be generated, and STO will be set). Rev. 1.1 157 C8051F350/1/2/3 SFR Definition 19.1. SMB0CF: SMBus Clock/Configuration R/W R/W R ENSMB INH BUSY Bit7 Bit6 Bit5 R/W R/W R/W R/W EXTHOLD SMBTOE SMBFTE SMBCS1 Bit4 Bit3 Bit2 Bit1 R/W Reset Value SMBCS0 00000000 Bit0 SFR Address: 0xC1 Bit7: ENSMB: SMBus Enable. This bit enables/disables the SMBus interface. When enabled, the interface constantly monitors the SDA and SCL pins. 0: SMBus interface disabled. 1: SMBus interface enabled. Bit6: INH: SMBus Slave Inhibit. When this bit is set to logic 1, the SMBus does not generate an interrupt when slave events occur. This effectively removes the SMBus slave from the bus. Master Mode interrupts are not affected. 0: SMBus Slave Mode enabled. 1: SMBus Slave Mode inhibited. Bit5: BUSY: SMBus Busy Indicator. This bit is set to logic 1 by hardware when a transfer is in progress. It is cleared to logic 0 when a STOP or free-timeout is sensed. Bit4: EXTHOLD: SMBus Setup and Hold Time Extension Enable. This bit controls the SDA setup and hold times according to Table 19.2. 0: SDA Extended Setup and Hold Times disabled. 1: SDA Extended Setup and Hold Times enabled. Bit3: SMBTOE: SMBus SCL Timeout Detection Enable. This bit enables SCL low timeout detection. If set to logic 1, the SMBus forces Timer 3 to reload while SCL is high and allows Timer 3 to count when SCL goes low. If Timer 3 is configured in split mode (T3SPLIT is set), only the high byte of Timer 3 is held in reload while SCL is high. Timer 3 should be programmed to generate interrupts at 25 ms, and the Timer 3 interrupt service routine should reset SMBus communication. Bit2: SMBFTE: SMBus Free Timeout Detection Enable. When this bit is set to logic 1, the bus will be considered free if SCL and SDA remain high for more than 10 SMBus clock source periods. Bits1–0: SMBCS1–SMBCS0: SMBus Clock Source Selection. These two bits select the SMBus clock source, which is used to generate the SMBus bit rate. The selected device should be configured according to Equation 19.1. SMBCS1 0 0 1 1 158 SMBCS0 0 1 0 1 SMBus Clock Source Timer 0 Overflow Timer 1 Overflow Timer 2 High Byte Overflow Timer 2 Low Byte Overflow Rev. 1.1 C8051F350/1/2/3 19.4.2. SMB0CN Control Register SMB0CN is used to control the interface and to provide status information (see SFR Definition 19.2). The higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to jump to service routines. MASTER and TXMODE indicate the master/slave state and transmit/receive modes, respectively. STA and STO indicate that a START and/or STOP has been detected or generated since the last SMBus interrupt. STA and STO are also used to generate START and STOP conditions when operating as a master. Writing a ‘1’ to STA will cause the SMBus interface to enter Master Mode and generate a START when the bus becomes free (STA is not cleared by hardware after the START is generated). Writing a ‘1’ to STO while in Master Mode will cause the interface to generate a STOP and end the current transfer after the next ACK cycle. If STO and STA are both set (while in Master Mode), a STOP followed by a START will be generated. As a receiver, writing the ACK bit defines the outgoing ACK value; as a transmitter, reading the ACK bit indicates the value received on the last ACK cycle. ACKRQ is set each time a byte is received, indicating that an outgoing ACK value is needed. When ACKRQ is set, software should write the desired outgoing value to the ACK bit before clearing SI. A NACK will be generated if software does not write the ACK bit before clearing SI. SDA will reflect the defined ACK value immediately following a write to the ACK bit; however SCL will remain low until SI is cleared. If a received slave address is not acknowledged, further slave events will be ignored until the next START is detected. The ARBLOST bit indicates that the interface has lost an arbitration. This may occur anytime the interface is transmitting (master or slave). A lost arbitration while operating as a slave indicates a bus error condition. ARBLOST is cleared by hardware each time SI is cleared. The SI bit (SMBus Interrupt Flag) is set at the beginning and end of each transfer, after each byte frame, or when an arbitration is lost; see Table 19.3 for more details. Important note about the SI bit: The SMBus interface is stalled while SI is set; thus SCL is held low, and the bus is stalled until software clears SI. Table 19.3 lists all sources for hardware changes to the SMB0CN bits. Refer to Table 19.4 for SMBus status decoding using the SMB0CN register. Rev. 1.1 159 C8051F350/1/2/3 SFR Definition 19.2. SMB0CN: SMBus Control R R MASTER TXMODE Bit7 Bit6 R/W R/W STA STO Bit5 Bit4 R R ACKRQ ARBLOST Bit3 Bit2 R/W R/W Reset Value ACK SI 00000000 Bit1 Bit0 Bit Addressable SFR Address: 0xC0 Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: 160 MASTER: SMBus Master/Slave Indicator. This read-only bit indicates when the SMBus is operating as a master. 0: SMBus operating in Slave Mode. 1: SMBus operating in Master Mode. TXMODE: SMBus Transmit Mode Indicator. This read-only bit indicates when the SMBus is operating as a transmitter. 0: SMBus in Receiver Mode. 1: SMBus in Transmitter Mode. STA: SMBus Start Flag. Write: 0: No Start generated. 1: When operating as a master, a START condition is transmitted if the bus is free (If the bus is not free, the START is transmitted after a STOP is received or a timeout is detected). If STA is set by software as an active Master, a repeated START will be generated after the next ACK cycle. Read: 0: No Start or repeated Start detected. 1: Start or repeated Start detected. STO: SMBus Stop Flag. Write: 0: No STOP condition is transmitted. 1: Setting STO to logic 1 causes a STOP condition to be transmitted after the next ACK cycle. When the STOP condition is generated, hardware clears STO to logic 0. If both STA and STO are set, a STOP condition is transmitted followed by a START condition. Read: 0: No Stop condition detected. 1: Stop condition detected (if in Slave Mode) or pending (if in Master Mode). ACKRQ: SMBus Acknowledge Request This read-only bit is set to logic 1 when the SMBus has received a byte and needs the ACK bit to be written with the correct ACK response value. ARBLOST: SMBus Arbitration Lost Indicator. This read-only bit is set to logic 1 when the SMBus loses arbitration while operating as a transmitter. A lost arbitration while a slave indicates a bus error condition. ACK: SMBus Acknowledge Flag. This bit defines the out-going ACK level and records incoming ACK levels. It should be written each time a byte is received (when ACKRQ=1), or read after each byte is transmitted. 0: A "not acknowledge" has been received (if in Transmitter Mode) OR will be transmitted (if in Receiver Mode). 1: An "acknowledge" has been received (if in Transmitter Mode) OR will be transmitted (if in Receiver Mode). SI: SMBus Interrupt Flag. This bit is set by hardware under the conditions listed in Table 19.3. SI must be cleared by software. While SI is set, SCL is held low and the SMBus is stalled. Rev. 1.1 C8051F350/1/2/3 Table 19.3. Sources for Hardware Changes to SMB0CN Bit MASTER TXMODE STA STO ACKRQ ARBLOST ACK SI Set by Hardware When: • A START is generated. • START is generated. • SMB0DAT is written before the start of an SMBus frame. • A START followed by an address byte is received. • A STOP is detected while addressed as a slave. • Arbitration is lost due to a detected STOP. • A byte has been received and an ACK response value is needed. • A repeated START is detected as a MASTER when STA is low (unwanted repeated START). • SCL is sensed low while attempting to generate a STOP or repeated START condition. • SDA is sensed low while transmitting a ‘1’ (excluding ACK bits). • The incoming ACK value is low (ACKNOWLEDGE). • A START has been generated. • Lost arbitration. • A byte has been transmitted and an ACK/NACK received. • A byte has been received. • A START or repeated START followed by a slave address + R/W has been received. • A STOP has been received. Rev. 1.1 Cleared by Hardware When: • A STOP is generated. • Arbitration is lost. • A START is detected. • Arbitration is lost. • SMB0DAT is not written before the start of an SMBus frame. • Must be cleared by software. • A pending STOP is generated. • After each ACK cycle. • Each time SI is cleared. • The incoming ACK value is high (NOT ACKNOWLEDGE). • Must be cleared by software. 161 C8051F350/1/2/3 19.4.3. Data Register The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software may safely read or write to the data register when the SI flag is set. Software should not attempt to access the SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic 0, as the interface may be in the process of shifting a byte of data into or out of the register. Data in SMB0DAT is always shifted out MSB first. After a byte has been received, the first bit of received data is located at the MSB of SMB0DAT. While data is being shifted out, data on the bus is simultaneously being shifted in. SMB0DAT always contains the last data byte present on the bus. In the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data or address in SMB0DAT. SFR Definition 19.3. SMB0DAT: SMBus Data R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xC2 Bits7–0: SMB0DAT: SMBus Data. The SMB0DAT register contains a byte of data to be transmitted on the SMBus serial interface or a byte that has just been received on the SMBus serial interface. The CPU can read from or write to this register whenever the SI serial interrupt flag (SMB0CN.0) is set to logic 1. The serial data in the register remains stable as long as the SI flag is set. When the SI flag is not set, the system may be in the process of shifting data in/out and the CPU should not attempt to access this register. 162 Rev. 1.1 C8051F350/1/2/3 19.5. SMBus Transfer Modes The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or Slave Receiver. The SMBus interface enters Master Mode any time a START is generated, and remains in Master Mode until it loses an arbitration or generates a STOP. An SMBus interrupt is generated at the end of all SMBus byte frames; however, note that the interrupt is generated before the ACK cycle when operating as a receiver, and after the ACK cycle when operating as a transmitter. 19.5.1. Master Transmitter Mode Serial data is transmitted on SDA while the serial clock is output on SCL. The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the data direction bit. In this case the data direction bit (R/W) will be logic 0 (WRITE). The master then transmits one or more bytes of serial data. After each byte is transmitted, an acknowledge bit is generated by the slave. The transfer is ended when the STO bit is set and a STOP is generated. Note that the interface will switch to Master Receiver Mode if SMB0DAT is not written following a Master Transmitter interrupt. Figure 19.5 shows a typical Master Transmitter sequence. Two transmit data bytes are shown, though any number of bytes may be transmitted. Notice that the ‘data byte transferred’ interrupts occur after the ACK cycle in this mode. S SLA W Interrupt A Interrupt Data Byte A Data Byte Interrupt A P Interrupt S = START P = STOP A = ACK W = WRITE SLA = Slave Address Received by SMBus Interface Transmitted by SMBus Interface Figure 19.5. Typical Master Transmitter Sequence Rev. 1.1 163 C8051F350/1/2/3 19.5.2. Master Receiver Mode Serial data is received on SDA while the serial clock is output on SCL. The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the data direction bit. In this case the data direction bit (R/W) will be logic 1 (READ). Serial data is then received from the slave on SDA while the SMBus outputs the serial clock. The slave transmits one or more bytes of serial data. After each byte is received, ACKRQ is set to ‘1’ and an interrupt is generated. Software must write the ACK bit (SMB0CN.1) to define the outgoing acknowledge value (Note: writing a ‘1’ to the ACK bit generates an ACK; writing a ‘0’ generates a NACK). Software should write a ‘0’ to the ACK bit after the last byte is received, to transmit a NACK. The interface exits Master Receiver Mode after the STO bit is set and a STOP is generated. Note that the interface will switch to Master Transmitter Mode if SMB0DAT is written while an active Master Receiver. Figure 19.6 shows a typical Master Receiver sequence. Two received data bytes are shown, though any number of bytes may be received. Notice that the ‘data byte transferred’ interrupts occur before the ACK cycle in this mode. S SLA R Interrupt A Interrupt Data Byte A Interrupt Data Byte N Interrupt S = START P = STOP A = ACK N = NACK R = READ SLA = Slave Address Received by SMBus Interface Transmitted by SMBus Interface Figure 19.6. Typical Master Receiver Sequence 164 Rev. 1.1 P C8051F350/1/2/3 19.5.3. Slave Receiver Mode Serial data is received on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode when a START followed by a slave address and direction bit (WRITE in this case) is received. Upon entering Slave Receiver Mode, an interrupt is generated and the ACKRQ bit is set. Software responds to the received slave address with an ACK, or ignores the received slave address with a NACK. If the received slave address is ignored, slave interrupts will be inhibited until the next START is detected. If the received slave address is acknowledged, zero or more data bytes are received. Software must write the ACK bit after each received byte to ACK or NACK the received byte. The interface exits Slave Receiver Mode after receiving a STOP. Note that the interface will switch to Slave Transmitter Mode if SMB0DAT is written while an active Slave Receiver. Figure 19.7 shows a typical Slave Receiver sequence. Two received data bytes are shown, though any number of bytes may be received. Notice that the ‘data byte transferred’ interrupts occur before the ACK cycle in this mode. Interrupt S SLA W A Interrupt Data Byte A Interrupt Data Byte A P Interrupt S = START P = STOP A = ACK W = WRITE SLA = Slave Address Received by SMBus Interface Transmitted by SMBus Interface Figure 19.7. Typical Slave Receiver Sequence Rev. 1.1 165 C8051F350/1/2/3 19.5.4. Slave Transmitter Mode Serial data is transmitted on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START followed by a slave address and direction bit (READ in this case) is received. Upon entering Slave Transmitter Mode, an interrupt is generated and the ACKRQ bit is set. Software responds to the received slave address with an ACK, or ignores the received slave address with a NACK. If the received slave address is ignored, slave interrupts will be inhibited until a START is detected. If the received slave address is acknowledged, data should be written to SMB0DAT to be transmitted. The interface enters Slave Transmitter Mode, and transmits one or more bytes of data. After each byte is transmitted, the master sends an acknowledge bit; if the acknowledge bit is an ACK, SMB0DAT should be written with the next data byte. If the acknowledge bit is a NACK, SMB0DAT should not be written to before SI is cleared (Note: an error condition may be generated if SMB0DAT is written following a received NACK while in Slave Transmitter Mode). The interface exits Slave Transmitter Mode after receiving a STOP. Note that the interface will switch to Slave Receiver Mode if SMB0DAT is not written following a Slave Transmitter interrupt. Figure 19.8 shows a typical Slave Transmitter sequence. Two transmitted data bytes are shown, though any number of bytes may be transmitted. Notice that the ‘data byte transferred’ interrupts occur after the ACK cycle in this mode. Interrupt S SLA R A Interrupt Data Byte A Data Byte Interrupt N P Interrupt S = START P = STOP N = NACK R = READ SLA = Slave Address Received by SMBus Interface Transmitted by SMBus Interface Figure 19.8. Typical Slave Transmitter Sequence 166 Rev. 1.1 C8051F350/1/2/3 19.6. SMBus Status Decoding The current SMBus status can be easily decoded using the SMB0CN register. In the table below, STATUS VECTOR refers to the four upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. Note that the shown response options are only the typical responses; application-specific procedures are allowed as long as they conform to the SMBus specification. Highlighted responses are allowed but do not conform to the SMBus specification. Table 19.4. SMBus Status Decoding Values Written Status Vector ACKRQ ARBLOST ACK 1110 0 0 X A master START was generated. 0 0 0 0 1 0 0 X 1 0 X 0 1 X Load next data byte into SMB0DAT. 0 0 X End transfer with STOP. 0 1 X End transfer with STOP and start another transfer. 1 1 X Send repeated START. 1 0 X Switch to Master Receiver Mode (clear SI without writing new data to SMB0DAT). 0 0 X Load slave address + R/W into SMB0DAT. Set STA to restart transfer. A master data or address byte was transmitted; NACK received. Abort transfer. 1100 0 ACK Typical Response Options STO Current SMbus State STA Master Transmitter Mode Values Read A master data or address byte was transmitted; ACK received. Rev. 1.1 167 C8051F350/1/2/3 Table 19.4. SMBus Status Decoding (Continued) Values Written Slave Transmitter 168 0100 0101 ACK X ACK 0 Typical Response Options STO 1 ARBLOST ACKRQ Status Vector 1000 Current SMbus State STA Master Receiver Mode Values Read Acknowledge received byte; Read SMB0DAT. 0 0 1 Send NACK to indicate last byte, and send STOP. 0 1 0 Send NACK to indicate last byte, and send STOP followed by START. 1 1 0 Send ACK followed by repeated START. 1 0 1 1 0 0 Send ACK and switch to Master Transmitter Mode (write to SMB0DAT before clearing SI). 0 0 1 Send NACK and switch to Master Transmitter Mode (write to SMB0DAT before clearing SI). 0 0 0 A master data byte was received; Send NACK to indicate last ACK requested. byte, and send repeated START. 0 0 0 A slave byte was transmitted; NACK received. No action required (expecting STOP condition). 0 0 X 0 0 1 A slave byte was transmitted; ACK received. Load SMB0DAT with next data byte to transmit. 0 0 X 0 1 X A Slave byte was transmitted; error detected. No action required (expecting Master to end transfer). 0 0 X 0 X A illegal STOP or bus error was X detected while a Slave Transmis- Clear STO. sion was in progress. 0 0 X Rev. 1.1 C8051F350/1/2/3 Table 19.4. SMBus Status Decoding (Continued) Values Written A slave address was received; ACK requested. 0010 Slave Receiver 1 0010 0001 1 Lost arbitration as master; slave X address received; ACK requested. ACK ACK X Typical Response Options STO 0 Current SMbus State STA 1 ARBLOST ACKRQ Status Vector Mode Values Read Acknowledge received address. 0 0 1 Do not acknowledge received address. 0 0 0 Acknowledge received address. 0 0 1 Do not acknowledge received address. 0 0 0 Reschedule failed transfer; do not acknowledge received address. 1 0 0 0 0 X 1 0 X 0 0 0 0 0 X 0 0 X 1 0 X Acknowledge received byte; Read SMB0DAT. 0 0 1 Do not acknowledge received byte. 0 0 0 0 0 0 1 0 0 0 1 X Lost arbitration while attempting a Abort failed transfer. repeated START. Reschedule failed transfer. 1 1 X Lost arbitration while attempting a No action required (transfer STOP. complete/aborted). 0 0 A STOP was detected while X addressed as a Slave Transmitter Clear STO. or Slave Receiver. 0 1 X 1 0 X Lost arbitration due to a detected Abort transfer. STOP. Reschedule failed transfer. A slave byte was received; ACK requested. 0000 1 1 X Lost arbitration while transmitting Abort failed transfer. a data byte as master. Reschedule failed transfer. Rev. 1.1 169 C8051F350/1/2/3 NOTES: 170 Rev. 1.1 C8051F350/1/2/3 20. UART0 UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in Section “20.1. Enhanced Baud Rate Generation’ on page 172). Received data buffering allows UART0 to start reception of a second incoming data byte before software has finished reading the previous data byte. UART0 has two associated SFRs: Serial Control Register 0 (SCON0) and Serial Data Buffer 0 (SBUF0). The single SBUF0 location provides access to both transmit and receive registers. Writes to SBUF0 always access the Transmit register. Reads of SBUF0 always access the buffered Receive register; it is not possible to read data from the Transmit register. With UART0 interrupts enabled, an interrupt is generated each time a transmit is completed (TI0 is set in SCON0), or a data byte has been received (RI0 is set in SCON0). The UART0 interrupt flags are not cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually by software, allowing software to determine the cause of the UART0 interrupt (transmit complete or receive complete). SFR Bus Write to SBUF TB8 SBUF (TX Shift) SET D Q TX CLR Crossbar Zero Detector Stop Bit Shift Start Data Tx Control Tx Clock Send Tx IRQ SCON TI Serial Port Interrupt MCE REN TB8 RB8 TI RI SMODE UART Baud Rate Generator Port I/O RI Rx IRQ Rx Clock Rx Control Start Shift 0x1FF Load SBUF RB8 Input Shift Register (9 bits) Load SBUF SBUF (RX Latch) Read SBUF SFR Bus RX Crossbar Figure 20.1. UART0 Block Diagram Rev. 1.1 171 C8051F350/1/2/3 20.1. Enhanced Baud Rate Generation The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 20.2), which is not useraccessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates. The RX Timer runs when Timer 1 is enabled, and uses the same reload value (TH1). However, an RX Timer reload is forced when a START condition is detected on the RX pin. This allows a receive to begin any time a START is detected, independent of the TX Timer state. Timer 1 TL1 UART Overflow 2 TX Clock Overflow 2 RX Clock TH1 Start Detected RX Timer Figure 20.2. UART0 Baud Rate Logic Timer 1 should be configured for Mode 2, 8-bit auto-reload (see Section “22.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload’ on page 197). The Timer 1 reload value should be set so that overflows will occur at two times the desired UART baud rate frequency. Note that Timer 1 may be clocked by one of six sources: SYSCLK, SYSCLK / 4, SYSCLK / 12, SYSCLK / 48, the external oscillator clock / 8, or an external input T1. The UART0 baud rate is determined by Equation 20.1-A and Equation 20.1-B. A) 1 UartBaudRate = --- × T1_Overflow_Rate 2 B) T1 CLK T1_Overflow_Rate = -------------------------256 – TH1 Equation 20.1. UART0 Baud Rate Where T1CLK is the frequency of the clock supplied to Timer 1, and T1H is the high byte of Timer 1 (reload value). Timer 1 clock frequency is selected as described in Section “22. Timers’ on page 195. A quick reference for typical baud rates and system clock frequencies is given in Table 20.1 through Table 20.6. Note that the internal oscillator may still generate the system clock when the external oscillator is driving Timer 1. 172 Rev. 1.1 C8051F350/1/2/3 20.2. Operational Modes UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown below. TX RS-232 LEVEL XLTR RS-232 RX C8051Fxxx OR TX TX RX RX MCU C8051Fxxx Figure 20.3. UART Interconnect Diagram 20.2.1. 8-Bit UART 8-Bit UART mode uses a total of 10 bits per data byte: one start bit, eight data bits (LSB first), and one stop bit. Data are transmitted LSB first from the TX0 pin and received at the RX0 pin. On receive, the eight data bits are stored in SBUF0 and the stop bit goes into RB80 (SCON0.2). Data transmission begins when software writes a data byte to the SBUF0 register. The TI0 Transmit Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to logic 1. After the stop bit is received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met: RI0 must be logic 0, and if MCE0 is logic 1, the stop bit must be logic 1. In the event of a receive data overrun, the first received 8 bits are latched into the SBUF0 receive register and the following overrun data bits are lost. If these conditions are met, the eight bits of data is stored in SBUF0, the stop bit is stored in RB80 and the RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not be set. An interrupt will occur if enabled when either TI0 or RI0 is set. MARK SPACE START BIT D0 D1 D2 D3 D4 D5 D6 D7 STOP BIT BIT TIMES BIT SAMPLING Figure 20.4. 8-Bit UART Timing Diagram Rev. 1.1 173 C8051F350/1/2/3 20.2.2. 9-Bit UART 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programmable ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80 (SCON0.3), which is assigned by user software. It can be assigned the value of the parity flag (bit P in register PSW) for error detection, or used in multiprocessor communications. On receive, the ninth data bit goes into RB80 (SCON0.2) and the stop bit is ignored. Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI0 Transmit Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to ‘1’. After the stop bit is received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met: (1) RI0 must be logic 0, and (2) if MCE0 is logic 1, the 9th bit must be logic 1 (when MCE0 is logic 0, the state of the ninth data bit is unimportant). If these conditions are met, the eight bits of data are stored in SBUF0, the ninth bit is stored in RB80, and the RI0 flag is set to ‘1’. If the above conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not be set to ‘1’. A UART0 interrupt will occur if enabled when either TI0 or RI0 is set to ‘1’. MARK SPACE START BIT D0 D1 D2 D3 D4 D5 D6 D7 D8 STOP BIT BIT TIMES BIT SAMPLING Figure 20.5. 9-Bit UART Timing Diagram 20.3. Multiprocessor Communications 9-Bit UART mode supports multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or more slaves, it first sends an address byte to select the target(s). An address byte differs from a data byte in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0. Setting the MCE0 bit (SCON0.5) of a slave processor configures its UART such that when a stop bit is received, the UART will generate an interrupt only if the ninth bit is logic 1 (RB80 = 1) signifying an address byte has been received. In the UART interrupt handler, software will compare the received address with the slave's own assigned 8-bit address. If the addresses match, the slave will clear its MCE0 bit to enable interrupts on the reception of the following data byte(s). Slaves that weren't addressed leave their MCE0 bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the data. Once the entire message is received, the addressed slave resets its MCE0 bit to ignore all transmissions until it receives the next address byte. Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. The master processor can be configured to receive all transmissions or a protocol can be implemented such that the master/slave role is temporarily reversed to enable half-duplex transmission between the original master and slave(s). 174 Rev. 1.1 C8051F350/1/2/3 Master Device Slave Device Slave Device Slave Device V+ RX TX RX TX RX TX RX TX Figure 20.6. UART Multi-Processor Mode Interconnect Diagram Rev. 1.1 175 C8051F350/1/2/3 SFR Definition 20.1. SCON0: Serial Port 0 Control R/W R R/W R/W R/W R/W R/W R/W Reset Value S0MODE — MCE0 REN0 TB80 RB80 TI0 RI0 01000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit Addressable SFR Address: 0x98 Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: 176 S0MODE: Serial Port 0 Operation Mode. This bit selects the UART0 Operation Mode. 0: 8-bit UART with Variable Baud Rate. 1: 9-bit UART with Variable Baud Rate. UNUSED. Read = 1b. Write = don’t care. MCE0: Multiprocessor Communication Enable. The function of this bit is dependent on the Serial Port 0 Operation Mode. S0MODE = 0: Checks for valid stop bit. 0: Logic level of stop bit is ignored. 1: RI0 will only be activated if stop bit is logic level 1. S0MODE = 1: Multiprocessor Communications Enable. 0: Logic level of ninth bit is ignored. 1: RI0 is set and an interrupt is generated only when the ninth bit is logic 1. REN0: Receive Enable. This bit enables/disables the UART receiver. 0: UART0 reception disabled. 1: UART0 reception enabled. TB80: Ninth Transmission Bit. The logic level of this bit will be assigned to the ninth transmission bit in 9-bit UART Mode. It is not used in 8-bit UART Mode. Set or cleared by software as required. RB80: Ninth Receive Bit. RB80 is assigned the value of the STOP bit in Mode 0; it is assigned the value of the 9th data bit in Mode 1. TI0: Transmit Interrupt Flag. Set by hardware when a byte of data has been transmitted by UART0 (after the 8th bit in 8bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When the UART0 interrupt is enabled, setting this bit causes the CPU to vector to the UART0 interrupt service routine. This bit must be cleared manually by software. RI0: Receive Interrupt Flag. Set to ‘1’ by hardware when a byte of data has been received by UART0 (set at the STOP bit sampling time). When the UART0 interrupt is enabled, setting this bit to ‘1’ causes the CPU to vector to the UART0 interrupt service routine. This bit must be cleared manually by software. Rev. 1.1 C8051F350/1/2/3 SFR Definition 20.2. SBUF0: Serial (UART0) Port Data Buffer R/W R/W R/W R/W R/W R/W R/W R/W Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset Value 00000000 SFR Address: 0x99 Bits7–0: SBUF0[7:0]: Serial Data Buffer Bits 7–0 (MSB–LSB) This SFR accesses two registers; a transmit shift register and a receive latch register. When data is written to SBUF0, it goes to the transmit shift register and is held for serial transmission. Writing a byte to SBUF0 initiates the transmission. A read of SBUF0 returns the contents of the receive latch. Rev. 1.1 177 C8051F350/1/2/3 SYSCLK from Internal Osc. Table 20.1. Timer Settings for Standard Baud Rates Using the Internal Oscillator Target Baud Rate (bps) 230400 115200 57600 28800 14400 9600 2400 1200 Baud Rate % Error –0.32% –0.32% 0.15% –0.32% 0.15% –0.32% –0.32% 0.15% Frequency: 24.5 MHz Oscilla- Timer Clock SCA1–SCA0 tor Divide Source (pre-scale Factor select)* 106 SYSCLK XX 212 SYSCLK XX 426 SYSCLK XX 848 SYSCLK / 4 01 1704 SYSCLK / 12 00 2544 SYSCLK / 12 00 10176 SYSCLK / 48 10 20448 SYSCLK / 48 10 X = Don’t care T1M* 1 1 1 0 0 0 0 0 Timer 1 Reload Value (hex) 0xCB 0x96 0x2B 0x96 0xB9 0x96 0x96 0x2B *Note: SCA1–SCA0 and T1M bit definitions can be found in Section 22.1. SYSCLK from SYSCLK from Internal Osc. External Osc. Table 20.2. Timer Settings for Standard Baud Rates Using an External 25.0 MHz Oscillator Target Baud Rate (bps) 230400 115200 57600 28800 14400 9600 2400 1200 57600 28800 14400 Baud Rate % Error 9600 0.15% –0.47% 0.45% –0.01% 0.45% –0.01% 0.15% 0.45% –0.01% –0.47% –0.47% 0.45% Frequency: 25.0 MHz Oscilla- Timer Clock SCA1–SCA0 tor Divide Source (pre-scale Factor select)* 108 SYSCLK XX 218 SYSCLK XX 434 SYSCLK XX 872 SYSCLK / 4 01 1736 SYSCLK / 4 01 2608 EXTCLK / 8 11 10464 SYSCLK / 48 10 20832 SYSCLK / 48 10 432 EXTCLK / 8 11 864 EXTCLK / 8 11 1744 EXTCLK / 8 11 2608 EXTCLK / 8 11 T1M* 1 1 1 0 0 0 0 0 0 0 0 Timer 1 Reload Value (hex) 0xCA 0x93 0x27 0x93 0x27 0x5D 0x93 0x27 0xE5 0xCA 0x93 0 0x5D X = Don’t care *Note: SCA1–SCA0 and T1M bit definitions can be found in Section 22.1. 178 Rev. 1.1 C8051F350/1/2/3 SYSCLK from Internal Osc. SYSCLK from External Osc. Table 20.3. Timer Settings for Standard Baud Rates Using an External 22.1184 MHz Oscillator Target Baud Rate (bps) 230400 115200 57600 28800 14400 9600 2400 1200 230400 115200 57600 28800 14400 9600 Baud Rate % Error 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% Frequency: 22.1184 MHz Oscilla- Timer Clock SCA1–SCA0 tor Divide Source (pre-scale Factor select)* 96 SYSCLK XX 192 SYSCLK XX 384 SYSCLK XX 768 SYSCLK / 12 00 1536 SYSCLK / 12 00 2304 SYSCLK / 12 00 9216 SYSCLK / 48 10 18432 SYSCLK / 48 10 96 EXTCLK / 8 11 192 EXTCLK / 8 11 384 EXTCLK / 8 11 768 EXTCLK / 8 11 1536 EXTCLK / 8 11 2304 EXTCLK / 8 11 X = Don’t care T1M* 1 1 1 0 0 0 0 0 0 0 0 0 0 0 Timer 1 Reload Value (hex) 0xD0 0xA0 0x40 0xE0 0xC0 0xA0 0xA0 0x40 0xFA 0xF4 0xE8 0xD0 0xA0 0x70 *Note: SCA1–SCA0 and T1M bit definitions can be found in Section 22.1. SYSCLK from Internal Osc. SYSCLK from External Osc. Table 20.4. Timer Settings for Standard Baud Rates Using an External 18.432 MHz Oscillator Target Baud Rate (bps) 230400 115200 57600 28800 14400 9600 2400 1200 230400 115200 57600 28800 14400 9600 Baud Rate % Error 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% Frequency: 18.432 MHz Oscilla- Timer Clock SCA1–SCA0 tor Divide Source (pre-scale Factor select)* 80 SYSCLK XX 160 SYSCLK XX 320 SYSCLK XX 640 SYSCLK / 4 01 1280 SYSCLK / 4 01 1920 SYSCLK / 12 00 7680 SYSCLK / 48 10 15360 SYSCLK / 48 10 80 EXTCLK / 8 11 160 EXTCLK / 8 11 320 EXTCLK / 8 11 640 EXTCLK / 8 11 1280 EXTCLK / 8 11 1920 EXTCLK / 8 11 X = Don’t care T1M* 1 1 1 0 0 0 0 0 0 0 0 0 0 0 Timer 1 Reload Value (hex) 0xD8 0xB0 0x60 0xB0 0x60 0xB0 0xB0 0x60 0xFB 0xF6 0xEC 0xD8 0xB0 0x88 *Note: SCA1–SCA0 and T1M bit definitions can be found in Section 22.1. Rev. 1.1 179 C8051F350/1/2/3 SYSCLK from Internal Osc. SYSCLK from External Osc. Table 20.5. Timer Settings for Standard Baud Rates Using an External 11.0592 MHz Oscillator Target Baud Rate (bps) 230400 115200 57600 28800 14400 9600 2400 1200 230400 115200 57600 28800 14400 9600 Baud Rate % Error 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% Frequency: 11.0592 MHz Oscilla- Timer Clock SCA1–SCA0 tor Divide Source (pre-scale Factor select)* 48 SYSCLK XX 96 SYSCLK XX 192 SYSCLK XX 384 SYSCLK XX 768 SYSCLK / 12 00 1152 SYSCLK / 12 00 4608 SYSCLK / 12 00 9216 SYSCLK / 48 10 48 EXTCLK / 8 11 96 EXTCLK / 8 11 192 EXTCLK / 8 11 384 EXTCLK / 8 11 768 EXTCLK / 8 11 1152 EXTCLK / 8 11 X = Don’t care T1M* 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Timer 1 Reload Value (hex) 0xE8 0xD0 0xA0 0x40 0xE0 0xD0 0x40 0xA0 0xFD 0xFA 0xF4 0xE8 0xD0 0xB8 *Note: SCA1–SCA0 and T1M bit definitions can be found in Section 22.1. SYSCLK from Internal Osc. SYSCLK from External Osc. Table 20.6. Timer Settings for Standard Baud Rates Using an External 3.6864 MHz Oscillator Target Baud Rate (bps) 230400 115200 57600 28800 14400 9600 2400 1200 230400 115200 57600 28800 14400 9600 Baud Rate% Error 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% Frequency: 3.6864 MHz Oscilla- Timer Clock SCA1–SCA0 tor Divide Source (pre-scale Factor select)* 16 SYSCLK XX 32 SYSCLK XX 64 SYSCLK XX 128 SYSCLK XX 256 SYSCLK XX 384 SYSCLK XX 1536 SYSCLK / 12 00 3072 SYSCLK / 12 00 16 EXTCLK / 8 11 32 EXTCLK / 8 11 64 EXTCLK / 8 11 128 EXTCLK / 8 11 256 EXTCLK / 8 11 384 EXTCLK / 8 11 X = Don’t care T1M* 1 1 1 1 1 1 0 0 0 0 0 0 0 0 *Note: SCA1–SCA0 and T1M bit definitions can be found in Section 22.1. 180 Rev. 1.1 Timer 1 Reload Value (hex) 0xF8 0xF0 0xE0 0xC0 0x80 0x40 0xC0 0x80 0xFF 0xFE 0xFC 0xF8 0xF0 0xE8 C8051F350/1/2/3 21. Serial Peripheral Interface (SPI0) The Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input to select SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can also be configured as a chip-select output in master mode, or disabled for 3-wire operation. Additional general purpose port I/O pins can be used to select multiple slave devices in master mode. SFR Bus SYSCLK SPI0CN SPIBSY MSTEN CKPHA CKPOL SLVSEL NSSIN SRMT RXBMT SPIF WCOL MODF RXOVRN NSSMD1 NSSMD0 TXBMT SPIEN SPI0CFG SCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCR1 SCR0 SPI0CKR Clock Divide Logic SPI CONTROL LOGIC Data Path Control SPI IRQ Pin Interface Control MOSI Tx Data SPI0DAT SCK Transmit Data Buffer Shift Register 7 6 5 4 3 2 1 0 Rx Data Pin Control Logic Receive Data Buffer MISO C R O S S B A R Port I/O NSS Read SPI0DAT Write SPI0DAT SFR Bus Figure 21.1. SPI Block Diagram Rev. 1.1 181 C8051F350/1/2/3 21.1. Signal Descriptions The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below. 21.1.1. Master Out, Slave In (MOSI) The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It is used to serially transfer data from the master to the slave. This signal is an output when SPI0 is operating as a master and an input when SPI0 is operating as a slave. Data is transferred most-significant bit first. When configured as a master, MOSI is driven by the MSB of the shift register in both 3- and 4-wire mode. 21.1.2. Master In, Slave Out (MISO) The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device. It is used to serially transfer data from the slave to the master. This signal is an input when SPI0 is operating as a master and an output when SPI0 is operating as a slave. Data is transferred most-significant bit first. The MISO pin is placed in a high-impedance state when the SPI module is disabled and when the SPI operates in 4-wire mode as a slave that is not selected. When acting as a slave in 3-wire mode, MISO is always driven by the MSB of the shift register. 21.1.3. Serial Clock (SCK) The serial clock (SCK) signal is an output from the master device and an input to slave devices. It is used to synchronize the transfer of data between the master and slave on the MOSI and MISO lines. SPI0 generates this signal when operating as a master. The SCK signal is ignored by a SPI slave when the slave is not selected (NSS = 1) in 4-wire slave mode. 21.1.4. Slave Select (NSS) The function of the slave-select (NSS) signal is dependent on the setting of the NSSMD1 and NSSMD0 bits in the SPI0CN register. There are three possible modes that can be selected with these bits: 1. NSSMD[1:0] = 00: 3-Wire Master or 3-Wire Slave Mode: SPI0 operates in 3-wire mode, and NSS is disabled. When operating as a slave device, SPI0 is always selected in 3-wire mode. Since no select signal is present, SPI0 must be the only slave on the bus in 3-wire mode. This is intended for point-to-point communication between a master and one slave. 2. NSSMD[1:0] = 01: 4-Wire Slave or Multi-Master Mode: SPI0 operates in 4-wire mode, and NSS is enabled as an input. When operating as a slave, NSS selects the SPI0 device. When operating as a master, a 1-to-0 transition of the NSS signal disables the master function of SPI0 so that multiple master devices can be used on the same SPI bus. 3. NSSMD[1:0] = 1x: 4-Wire Master Mode: SPI0 operates in 4-wire mode, and NSS is enabled as an output. The setting of NSSMD0 determines what logic level the NSS pin will output. This configuration should only be used when operating SPI0 as a master device. See Figure 21.2, Figure 21.3, and Figure 21.4 for typical connection diagrams of the various operational modes. Note that the setting of NSSMD bits affects the pinout of the device. When in 3-wire master or 3-wire slave mode, the NSS pin will not be mapped by the crossbar. In all other modes, the NSS signal will be mapped to a pin on the device. See Section “18. Port Input/Output’ on page 137 for general purpose port I/O and crossbar information. 182 Rev. 1.1 C8051F350/1/2/3 21.2. SPI0 Master Mode Operation A SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by setting the Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data register (SPI0DAT) when in master mode writes to the transmit buffer. If the SPI shift register is empty, the byte in the transmit buffer is moved to the shift register, and a data transfer begins. The SPI0 master immediately shifts out the data serially on the MOSI line while providing the serial clock on SCK. The SPIF (SPI0CN.7) flag is set to logic 1 at the end of the transfer. If interrupts are enabled, an interrupt request is generated when the SPIF flag is set. While the SPI0 master transfers data to a slave on the MOSI line, the addressed SPI slave device simultaneously transfers data to the SPI master on the MISO line in a full-duplex operation. Therefore, the SPIF flag serves as both a transmit-complete and receive-data-ready flag. The data byte received from the slave is transferred MSB-first into the master's shift register. When a byte is fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by reading SPI0DAT. When configured as a master, SPI0 can operate in one of three different modes: multi-master mode, 3-wire single-master mode, and 4-wire single-master mode. The default, multi-master mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In this mode, NSS is an input to the device, and is used to disable the master SPI0 when another master is accessing the bus. When NSS is pulled low in this mode, MSTEN (SPI0CN.6) and SPIEN (SPI0CN.0) are set to 0 to disable the SPI master device, and a Mode Fault is generated (MODF, SPI0CN.5 = 1). Mode Fault will generate an interrupt if enabled. SPI0 must be manually re-enabled in software under these circumstances. In multi-master systems, devices will typically default to being slave devices while they are not acting as the system master device. In multi-master mode, slave devices can be addressed individually (if needed) using general-purpose I/O pins. Figure 21.2 shows a connection diagram between two master devices in multiple-master mode. 3-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. In this mode, NSS is not used, and is not mapped to an external port pin through the crossbar. Any slave devices that must be addressed in this mode should be selected using general-purpose I/O pins. Figure 21.3 shows a connection diagram between a master device in 3-wire master mode and a slave device. 4-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 1. In this mode, NSS is configured as an output pin, and can be used as a slave-select signal for a single SPI device. In this mode, the output value of NSS is controlled (in software) with the bit NSSMD0 (SPI0CN.2). Additional slave devices can be addressed using general-purpose I/O pins. Figure 21.4 shows a connection diagram for a master device in 4-wire master mode and two slave devices. Rev. 1.1 183 C8051F350/1/2/3 Master Device 1 NSS GPIO MISO MISO MOSI MOSI SCK SCK GPIO NSS Master Device 2 Figure 21.2. Multiple-Master Mode Connection Diagram Master Device MISO MISO MOSI MOSI SCK SCK Slave Device Figure 21.3. 3-Wire Single Master and Slave Mode Connection Diagram Master Device GPIO MISO MISO MOSI MOSI SCK SCK NSS NSS MISO MOSI Slave Device Slave Device SCK NSS Figure 21.4. 4-Wire Single Master and Slave Mode Connection Diagram 184 Rev. 1.1 C8051F350/1/2/3 21.3. SPI0 Slave Mode Operation When SPI0 is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK signal. A bit counter in the SPI0 logic counts SCK edges. When 8 bits have been shifted into the shift register, the SPIF flag is set to logic 1, and the byte is copied into the receive buffer. Data is read from the receive buffer by reading SPI0DAT. A slave device cannot initiate transfers. Data to be transferred to the master device is pre-loaded into the shift register by writing to SPI0DAT. Writes to SPI0DAT are double-buffered, and are placed in the transmit buffer first. If the shift register is empty, the contents of the transmit buffer will immediately be transferred into the shift register. When the shift register already contains data, the SPI will load the shift register with the transmit buffer’s contents after the last SCK edge of the next (or current) SPI transfer. When configured as a slave, SPI0 can be configured for 4-wire or 3-wire operation. The default, 4-wire slave mode, is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In 4-wire mode, the NSS signal is routed to a port pin and configured as a digital input. SPI0 is enabled when NSS is logic 0, and disabled when NSS is logic 1. The bit counter is reset on a falling edge of NSS. Note that the NSS signal must be driven low at least 2 system clocks before the first active edge of SCK for each byte transfer. Figure 21.4 shows a connection diagram between two slave devices in 4-wire slave mode and a master device. 3-wire slave mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. NSS is not used in this mode, and is not mapped to an external port pin through the crossbar. Since there is not a way of uniquely addressing the device in 3-wire slave mode, SPI0 must be the only slave device present on the bus. It is important to note that in 3-wire slave mode there is no external means of resetting the bit counter that determines when a full byte has been received. The bit counter can only be reset by disabling and reenabling SPI0 with the SPIEN bit. Figure 21.3 shows a connection diagram between a slave device in 3wire slave mode and a master device. 21.4. SPI0 Interrupt Sources When SPI0 interrupts are enabled, the following four flags will generate an interrupt when they are set to logic 1: Note that all of the following bits must be cleared by software. 1. The SPI Interrupt Flag, SPIF (SPI0CN.7) is set to logic 1 at the end of each byte transfer. This flag can occur in all SPI0 modes. 2. The Write Collision Flag, WCOL (SPI0CN.6) is set to logic 1 if a write to SPI0DAT is attempted when the transmit buffer has not been emptied to the SPI shift register. When this occurs, the write to SPI0DAT will be ignored, and the transmit buffer will not be written.This flag can occur in all SPI0 modes. 3. The Mode Fault Flag MODF (SPI0CN.5) is set to logic 1 when SPI0 is configured as a master, and for multi-master mode and the NSS pin is pulled low. When a Mode Fault occurs, the MSTEN and SPIEN bits in SPI0CN are set to logic 0 to disable SPI0 and allow another master device to access the bus. 4. The Receive Overrun Flag RXOVRN (SPI0CN.4) is set to logic 1 when configured as a slave, and a transfer is completed while the receive buffer still holds an unread byte from a previous transfer. The new byte is not transferred to the receive buffer, allowing the previously received data byte to be read. The data byte which caused the overrun is lost. Rev. 1.1 185 C8051F350/1/2/3 21.5. Serial Clock Timing Four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases (edge used to latch the data). The CKPOL bit (SPI0CFG.4) selects between an active-high or active-low clock. Both master and slave devices must be configured to use the same clock phase and polarity. SPI0 should be disabled (by clearing the SPIEN bit, SPI0CN.0) when changing the clock phase or polarity. The clock and data line relationships are shown in Figure 21.5. The SPI0 Clock Rate Register (SPI0CKR) as shown in SFR Definition 21.3 controls the master mode serial clock frequency. This register is ignored when operating in slave mode. When the SPI is configured as a master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency or 12.5 MHz, whichever is slower. When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the system clock frequency, provided that the master issues SCK, NSS (in 4wire slave mode), and the serial input data synchronously with the slave’s system clock. If the master issues SCK, NSS, and the serial input data asynchronously, the maximum data transfer rate (bits/sec) must be less than 1/10 the system clock frequency. In the special case where the master only wants to transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the SPI slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. This is provided that the master issues SCK, NSS, and the serial input data synchronously with the slave’s system clock. SCK (CKPOL=0, CKPHA=0) SCK (CKPOL=0, CKPHA=1) SCK (CKPOL=1, CKPHA=0) SCK (CKPOL=1, CKPHA=1) MISO/MOSI MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Figure 21.5. Data/Clock Timing Relationship 21.6. SPI Special Function Registers SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate Register. The four special function registers related to the operation of the SPI0 Bus are described in the following figures. 186 Rev. 1.1 C8051F350/1/2/3 SFR Definition 21.1. SPI0CFG: SPI0 Configuration R R/W R/W R/W R R R R Reset Value SPIBSY MSTEN CKPHA CKPOL SLVSEL NSSIN SRMT RXBMT 00000111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xA1 Bit 7: Bit 6: Bit 5: Bit 4: Bit 3: Bit 2: Bit 1: Bit 0: SPIBSY: SPI Busy (read only). This bit is set to logic 1 when a SPI transfer is in progress (Master or Slave Mode). MSTEN: Master Mode Enable. 0: Disable master mode. Operate in slave mode. 1: Enable master mode. Operate as a master. CKPHA: SPI0 Clock Phase. This bit controls the SPI0 clock phase. 0: Data centered on first edge of SCK period.* 1: Data centered on second edge of SCK period.* CKPOL: SPI0 Clock Polarity. This bit controls the SPI0 clock polarity. 0: SCK line low in idle state. 1: SCK line high in idle state. SLVSEL: Slave Selected Flag (read only). This bit is set to logic 1 whenever the NSS pin is low indicating SPI0 is the selected slave. It is cleared to logic 0 when NSS is high (slave not selected). This bit does not indicate the instantaneous value at the NSS pin, but rather a de-glitched version of the pin input. NSSIN: NSS Instantaneous Pin Input (read only). This bit mimics the instantaneous value that is present on the NSS port pin at the time that the register is read. This input is not de-glitched. SRMT: Shift Register Empty (Valid in Slave Mode, read only). This bit will be set to logic 1 when all data has been transferred in/out of the shift register, and there is no new information available to read from the transmit buffer or write to the receive buffer. It returns to logic 0 when a data byte is transferred to the shift register from the transmit buffer or by a transition on SCK. NOTE: SRMT = 1 when in Master Mode. RXBMT: Receive Buffer Empty (Valid in Slave Mode, read only). This bit will be set to logic 1 when the receive buffer has been read and contains no new information. If there is new information available in the receive buffer that has not been read, this bit will return to logic 0. NOTE: RXBMT = 1 when in Master Mode. *Note: See Table 21.1 for timing parameters. Rev. 1.1 187 C8051F350/1/2/3 SFR Definition 21.2. SPI0CN: SPI0 Control R/W R/W R/W SPIF WCOL MODF Bit7 Bit6 Bit5 R/W R/W R/W RXOVRN NSSMD1 NSSMD0 Bit4 Bit3 Bit2 R R/W Reset Value TXBMT SPIEN 00000110 Bit1 Bit0 Bit Addressable SFR Address: 0xF8 Bit 7: SPIF: SPI0 Interrupt Flag. This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are enabled, setting this bit causes the CPU to vector to the SPI0 interrupt service routine. This bit is not automatically cleared by hardware. It must be cleared by software. Bit 6: WCOL: Write Collision Flag. This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) to indicate a write to the SPI0 data register was attempted while a data transfer was in progress. This bit is not automatically cleared by hardware. It must be cleared by software. Bit 5: MODF: Mode Fault Flag. This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when a master mode collision is detected (NSS is low, MSTEN = 1, and NSSMD[1:0] = 01). This bit is not automatically cleared by hardware. It must be cleared by software. Bit 4: RXOVRN: Receive Overrun Flag (Slave Mode only). This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when the receive buffer still holds unread data from a previous transfer and the last bit of the current transfer is shifted into the SPI0 shift register. This bit is not automatically cleared by hardware. It must be cleared by software. Bits 3–2: NSSMD1–NSSMD0: Slave Select Mode. Selects between the following NSS operation modes: (See Section “21.2. SPI0 Master Mode Operation’ on page 183 and Section “21.3. SPI0 Slave Mode Operation’ on page 185). 00: 3-Wire Slave or 3-wire Master Mode. NSS signal is not routed to a port pin. 01: 4-Wire Slave or Multi-Master Mode (Default). NSS is always an input to the device. 1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from the device and will assume the value of NSSMD0. Bit 1: TXBMT: Transmit Buffer Empty. This bit will be set to logic 0 when new data has been written to the transmit buffer. When data in the transmit buffer is transferred to the SPI shift register, this bit will be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer. Bit 0: SPIEN: SPI0 Enable. This bit enables/disables the SPI. 0: SPI disabled. 1: SPI enabled. 188 Rev. 1.1 C8051F350/1/2/3 SFR Definition 21.3. SPI0CKR: SPI0 Clock Rate R/W R/W R/W R/W R/W R/W R/W R/W Reset Value SCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCR1 SCR0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xA2 Bits 7–0: SCR7–SCR0: SPI0 Clock Rate. These bits determine the frequency of the SCK output when the SPI0 module is configured for master mode operation. The SCK clock frequency is a divided version of the system clock, and is given in the following equation, where SYSCLK is the system clock frequency and SPI0CKR is the 8-bit value held in the SPI0CKR register. SYSCLK f SCK = ------------------------------------------------2 × ( SPI0CKR + 1 ) for 0