C8051F353-GMR

C8051F350/1/2/3 8 k ISP Flash MCU Family Analog Peripherals - 24 or 16-Bit ADC High Speed 8051 µC Core - Pipelined Instruction architecture; executes 70% of - - Up to 50 MIPS throughput - Expanded interrupt handler Memory - 768 Bytes (256 + 512) On-Chip RAM - 8 kB Flash; In-system programmable in 512-byte No missing codes 0.0015% nonlinearity Programmable conversion rates up to 1 ksps 8-Input multiplexer 1x to 128x PGA Built-in temperature sensor instructions in 1 or 2 system clocks Two 8-Bit Current Output DACs Comparator • Programmable hysteresis and response time • Configurable as interrupt or reset source • Low current (0.4 µA) Sectors On-chip Debug - On-chip debug circuitry facilitates full speed, non- intrusive in-system debug (No emulator required) Provides breakpoints, single stepping,  inspect/modify memory and registers Superior performance to emulation systems using ICE-Chips, target pods, and sockets Low Cost, Complete Development Kit Supply Voltage 2.7 to 3.6 V - Typical operating current: 5.8 mA @ 25 MHz; 11 µA @ 32 kHz 0.1 µA capture/compare modules Real time clock mode using PCA or timer and external clock source Clock Sources - Internal Oscillator: 24.5 MHz with ± 2% accuracy supports UART operation External Oscillator: Crystal, RC, C, or clock  (1 or 2 pin modes) Clock multiplier to achieve 50 MHz internal clock Can switch between clock sources on-the-fly 28-Pin QFN or 32-Pin LQFP Package - 5 x 5 mm PCB footprint with 28-QFN ANALOG PERIPHERALS 8-bit IDAC 24/16-bit ADC 8-bit IDAC + TEMP SENSOR - - - Typical stop mode current: Temperature Range: –40 to +85 °C A M U X Digital Peripherals - 17 Port I/O; All 5 V tolerant with high sink current - Enhanced UART, SMBus™, and SPI™ Serial Ports - Four general purpose 16-bit counter/timers - 16-bit programmable counter array (PCA) with three VOLTAGE COMPARATOR DIGITAL I/O UART SMBus SPI PCA Timer 0 Timer 1 Timer 2 Timer 3 CROSSBAR • • • • • • Port 0 Port 1 P2.0 24.5 MHz PRECISION INTERNAL OSCILLATOR WITH CLOCK MULTIPLIER HIGH-SPEED CONTROLLER CORE 8 kB ISP FLASH FLEXIBLE INTERRUPTS Rev. 1.2 11/22 8051 CPU (50 MIPS) DEBUG CIRCUITRY 768 B SRAM POR Copyright © 2022 by Silicon Laboratories WDT C8051F35x C8051F350/1/2/3 Table of Contents 1. System Overview.................................................................................................... 14 1.1. CIP-51™ Microcontroller................................................................................... 18 1.1.1. Fully 8051 Compatible Instruction Set...................................................... 18 1.1.2. Improved Throughput ............................................................................... 18 1.1.3. Additional Features .................................................................................. 18 1.2. On-Chip Debug Circuitry................................................................................... 19 1.3. On-Chip Memory............................................................................................... 20 1.4. 24 or 16-Bit Analog to Digital Converter (ADC0) .............................................. 21 1.5. Two 8-bit Current-Mode DACs.......................................................................... 22 1.6. Programmable Comparator .............................................................................. 23 1.7. Serial Ports ....................................................................................................... 23 1.8. Port Input/Output............................................................................................... 24 1.9. Programmable Counter Array ........................................................................... 25 2. Absolute Maximum Ratings .................................................................................. 26 3. Global DC Electrical Characteristics .................................................................... 27 4. Pinout and Package Definitions............................................................................ 28 5. 24 or 16-Bit Analog to Digital Converter (ADC0) ................................................. 37 5.1. Configuration..................................................................................................... 38 5.1.1. Voltage Reference Selection.................................................................... 38 5.1.2. Analog Inputs ........................................................................................... 38 5.1.3. Modulator Clock ....................................................................................... 39 5.1.4. Decimation Ratio ...................................................................................... 39 5.2. Calibrating the ADC .......................................................................................... 40 5.2.1. Internal Calibration ................................................................................... 40 5.2.2. System Calibration ................................................................................... 40 5.2.3. Calibration Coefficient Storage................................................................. 40 5.3. Performing Conversions ................................................................................... 42 5.3.1. Single Conversions .................................................................................. 42 5.3.2. Continuous Conversions .......................................................................... 42 5.3.3. ADC Output .............................................................................................. 42 5.3.4. Error Conditions ....................................................................................... 43 5.4. Offset DAC........................................................................................................ 43 5.5. Burnout Current Sources .................................................................................. 43 5.6. Analog Multiplexer ............................................................................................ 55 6. 8-Bit Current Mode DACS (IDA0 and IDA1).......................................................... 62 6.1. IDAC Output Scheduling................................................................................... 63 6.1.1. Update Output On-Demand ..................................................................... 63 6.1.2. Update Output Based on Timer Overflow ................................................ 63 6.1.3. Update Output Based on CNVSTR Edge................................................. 63 6.2. IDAC Output Mapping....................................................................................... 63 6.3. IDAC External Pin Connections ........................................................................ 66 7. Voltage Reference .................................................................................................. 68 8. Temperature Sensor............................................................................................... 71 2 Rev. 1.2 C8051F350/1/2/3 9. Comparator0 ........................................................................................................... 73 9.1. Comparator0 Inputs and Outputs...................................................................... 77 10. CIP-51 Microcontroller ........................................................................................... 80 10.1.Instruction Set................................................................................................... 82 10.1.1.Instruction and CPU Timing ..................................................................... 82 10.1.2.MOVX Instruction and Program Memory ................................................. 82 10.2.Register Descriptions ....................................................................................... 86 10.3.Power Management Modes.............................................................................. 89 10.3.1.Idle Mode ................................................................................................. 89 10.3.2.Stop Mode................................................................................................ 89 11. Memory Organization and SFRs ........................................................................... 91 11.1.Program Memory.............................................................................................. 91 11.2.Data Memory .................................................................................................... 92 11.3.General Purpose Registers .............................................................................. 92 11.4.Bit Addressable Locations ................................................................................ 92 11.5.Stack ............................................................................................................ 92 11.6.Special Function Registers............................................................................... 93 12. Interrupt Handler .................................................................................................... 97 12.1.MCU Interrupt Sources and Vectors................................................................. 97 12.2.Interrupt Priorities ............................................................................................. 97 12.3.Interrupt Latency............................................................................................... 97 12.4.Interrupt Register Descriptions ......................................................................... 99 12.5.External Interrupts .......................................................................................... 103 13. Prefetch Engine .................................................................................................... 105 14. Reset Sources....................................................................................................... 106 14.1.Power-On Reset ............................................................................................. 107 14.2.Power-Fail Reset / VDD Monitor .................................................................... 108 14.3.External Reset ................................................................................................ 109 14.4.Missing Clock Detector Reset ........................................................................ 109 14.5.Comparator0 Reset ........................................................................................ 109 14.6.PCA Watchdog Timer Reset .......................................................................... 109 14.7.Flash Error Reset ........................................................................................... 109 14.8.Software Reset ............................................................................................... 109 15. Flash Memory ....................................................................................................... 112 15.1.Programming The Flash Memory ................................................................... 112 15.1.1.Flash Lock and Key Functions ............................................................... 112 15.1.2.Flash Erase Procedure .......................................................................... 112 15.1.3.Flash Write Procedure ........................................................................... 113 15.2.Non-volatile Data Storage .............................................................................. 114 15.3.Security Options ............................................................................................. 114 16. External RAM ........................................................................................................ 118 17. Oscillators ............................................................................................................. 119 17.1.Programmable Internal Oscillator ................................................................... 119 17.2.External Oscillator Drive Circuit...................................................................... 121 17.2.1.Clocking Timers Directly Through the External Oscillator...................... 121 Rev. 1.2 3 C8051F350/1/2/3 17.2.2.External Crystal Example....................................................................... 121 17.2.3.External RC Example............................................................................. 123 17.2.4.External Capacitor Example................................................................... 123 17.3.Clock Multiplier ............................................................................................... 125 17.4.System Clock Selection.................................................................................. 126 18. Port Input/Output.................................................................................................. 127 18.1.Priority Crossbar Decoder .............................................................................. 129 18.2.Port I/O Initialization ....................................................................................... 131 18.3.General Purpose Port I/O ............................................................................... 134 19. SMBus ................................................................................................................... 141 19.1.Supporting Documents ................................................................................... 142 19.2.SMBus Configuration...................................................................................... 142 19.3.SMBus Operation ........................................................................................... 142 19.3.1.Arbitration............................................................................................... 143 19.3.2.Clock Low Extension.............................................................................. 144 19.3.3.SCL Low Timeout................................................................................... 144 19.3.4.SCL High (SMBus Free) Timeout .......................................................... 144 19.4.Using the SMBus............................................................................................ 145 19.4.1.SMBus Configuration Register............................................................... 146 19.4.2.SMB0CN Control Register ..................................................................... 149 19.4.3.Data Register ......................................................................................... 152 19.5.SMBus Transfer Modes.................................................................................. 153 19.5.1.Master Transmitter Mode ....................................................................... 153 19.5.2.Master Receiver Mode ........................................................................... 154 19.5.3.Slave Receiver Mode ............................................................................. 155 19.5.4.Slave Transmitter Mode ......................................................................... 156 19.6.SMBus Status Decoding................................................................................. 157 20. UART0.................................................................................................................... 160 20.1.Enhanced Baud Rate Generation................................................................... 161 20.2.Operational Modes ......................................................................................... 162 20.2.1.8-Bit UART ............................................................................................. 162 20.2.2.9-Bit UART ............................................................................................. 163 20.3.Multiprocessor Communications .................................................................... 163 21. Serial Peripheral Interface (SPI0) ........................................................................ 170 21.1.Signal Descriptions......................................................................................... 171 21.1.1.Master Out, Slave In (MOSI).................................................................. 171 21.1.2.Master In, Slave Out (MISO).................................................................. 171 21.1.3.Serial Clock (SCK) ................................................................................. 171 21.1.4.Slave Select (NSS) ................................................................................ 171 21.2.SPI0 Master Mode Operation ......................................................................... 172 21.3.SPI0 Slave Mode Operation ........................................................................... 174 21.4.SPI0 Interrupt Sources ................................................................................... 174 21.5.Serial Clock Timing......................................................................................... 175 21.6.SPI Special Function Registers ...................................................................... 175 4 Rev. 1.2 C8051F350/1/2/3 22. Timers.................................................................................................................... 183 22.1.Timer 0 and Timer 1 ....................................................................................... 183 22.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 183 22.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 184 22.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 185 22.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 186 22.2.Timer 2 .......................................................................................................... 191 22.2.1.16-bit Timer with Auto-Reload................................................................ 191 22.2.2.8-bit Timers with Auto-Reload................................................................ 192 22.3.Timer 3 .......................................................................................................... 195 22.3.1.16-bit Timer with Auto-Reload................................................................ 195 22.3.2.8-bit Timers with Auto-Reload................................................................ 196 23. Programmable Counter Array ............................................................................. 199 23.1.PCA Counter/Timer ........................................................................................ 200 23.2.Capture/Compare Modules ............................................................................ 201 23.2.1.Edge-triggered Capture Mode................................................................ 202 23.2.2.Software Timer (Compare) Mode........................................................... 203 23.2.3.High Speed Output Mode....................................................................... 204 23.2.4.Frequency Output Mode ........................................................................ 205 23.2.5.8-Bit Pulse Width Modulator Mode......................................................... 206 23.2.6.16-Bit Pulse Width Modulator Mode....................................................... 207 23.3.Watchdog Timer Mode ................................................................................... 208 23.3.1.Watchdog Timer Operation .................................................................... 208 23.3.2.Watchdog Timer Usage ......................................................................... 209 23.4.Register Descriptions for PCA........................................................................ 210 24. Revision Specific Behavior ................................................................................. 215 24.1.Revision Identification..................................................................................... 215 25. C2 Interface ........................................................................................................... 216 25.1.C2 Interface Registers.................................................................................... 216 25.2.C2 Pin Sharing ............................................................................................... 218 Rev. 1.2 5 C8051F350/1/2/3 List of Figures 1. System Overview Figure 1.1. C8051F350 Block Diagram .................................................................... 16 Figure 1.2. C8051F351 Block Diagram .................................................................... 16 Figure 1.3. C8051F352 Block Diagram .................................................................... 17 Figure 1.4. C8051F353 Block Diagram .................................................................... 17 Figure 1.5. Development/In-System Debug Diagram............................................... 19 Figure 1.6. Memory Map .......................................................................................... 20 Figure 1.7. ADC0 Block Diagram ............................................................................. 21 Figure 1.8. IDAC Block Diagram .............................................................................. 22 Figure 1.9. Comparator0 Block Diagram.................................................................. 23 Figure 1.10. Port I/O Functional Block Diagram ....................................................... 24 Figure 1.11. PCA Block Diagram.............................................................................. 25 4. Pinout and Package Definitions Figure 4.1. LQFP-32 Pinout Diagram (Top View) .................................................... 31 Figure 4.2. QFN-28 Pinout Diagram (Top View) ...................................................... 32 Figure 4.3. LQFP-32 Package Diagram ................................................................... 33 Figure 4.4. QFN-28 Package Drawing ..................................................................... 34 Figure 4.5. Typical QFN-28 Landing Diagram.......................................................... 35 Figure 4.6. Typical QFN-28 Solder Paste Diagram.................................................. 36 5. 24 or 16-Bit Analog to Digital Converter (ADC0) Figure 5.1. ADC0 Block Diagram ............................................................................. 37 Figure 5.2. ADC0 Buffer Control .............................................................................. 39 Figure 5.3. ADC0 Offset Calibration Register Coding .............................................. 41 Figure 5.4. ADC0 Gain Calibration Register Coding ................................................ 41 Figure 5.5. ADC0 Multiplexer Connections .............................................................. 55 6. 8-Bit Current Mode DACS (IDA0 and IDA1) Figure 6.1. IDAC Functional Block Diagram............................................................. 62 Figure 6.2. IDAC Data Word Mapping...................................................................... 63 Figure 6.3. IDAC Pin Connections ........................................................................... 66 7. Voltage Reference Figure 7.1. Reference Circuitry Block Diagram ........................................................ 68 8. Temperature Sensor Figure 8.1. Temperature Sensor Block Diagram...................................................... 71 Figure 8.2. Single Channel Transfer Function.......................................................... 72 Figure 8.3. Differential Transfer Function................................................................. 72 9. Comparator0 Figure 9.1. Comparator0 Functional Block Diagram ................................................ 73 Figure 9.2. Comparator Hysteresis Plot ................................................................... 74 Figure 9.3. Comparator Pin Connections ................................................................. 77 10. CIP-51 Microcontroller Figure 10.1. CIP-51 Block Diagram.......................................................................... 80 11. Memory Organization and SFRs Figure 11.1. Memory Map ........................................................................................ 91 6 Rev. 1.2 C8051F350/1/2/3 14. Reset Sources Figure 14.1. Reset Sources.................................................................................... 106 Figure 14.2. Power-On and VDD Monitor Reset Timing ........................................ 107 15. Flash Memory Figure 15.1. Flash Memory Map............................................................................. 114 17. Oscillators Figure 17.1. Oscillator Diagram.............................................................................. 119 Figure 17.2. 32.768 kHz External Crystal Example................................................ 122 18. Port Input/Output Figure 18.1. Port I/O Functional Block Diagram ..................................................... 127 Figure 18.2. Port I/O Cell Block Diagram ............................................................... 128 Figure 18.3. Crossbar Priority Decoder with No Pins Skipped ............................... 129 Figure 18.4. Crossbar Priority Decoder with Crystal Pins Skipped ........................ 130 19. SMBus Figure 19.1. SMBus Block Diagram ....................................................................... 141 Figure 19.2. Typical SMBus Configuration ............................................................. 142 Figure 19.3. SMBus Transaction ............................................................................ 143 Figure 19.4. Typical SMBus SCL Generation......................................................... 147 Figure 19.5. Typical Master Transmitter Sequence................................................ 153 Figure 19.6. Typical Master Receiver Sequence.................................................... 154 Figure 19.7. Typical Slave Receiver Sequence...................................................... 155 Figure 19.8. Typical Slave Transmitter Sequence.................................................. 156 20. UART0 Figure 20.1. UART0 Block Diagram ....................................................................... 160 Figure 20.2. UART0 Baud Rate Logic .................................................................... 161 Figure 20.3. UART Interconnect Diagram .............................................................. 162 Figure 20.4. 8-Bit UART Timing Diagram............................................................... 162 Figure 20.5. 9-Bit UART Timing Diagram............................................................... 163 Figure 20.6. UART Multi-Processor Mode Interconnect Diagram .......................... 164 21. Serial Peripheral Interface (SPI0) Figure 21.1. SPI Block Diagram ............................................................................. 170 Figure 21.2. Multiple-Master Mode Connection Diagram ....................................... 173 Figure 21.3. 3-Wire Single Master and Slave Mode Connection Diagram ............. 173 Figure 21.4. 4-Wire Single Master and Slave Mode Connection Diagram ............. 173 Figure 21.5. Data/Clock Timing Relationship ......................................................... 175 Figure 21.6. SPI Master Timing (CKPHA = 0)........................................................ 180 Figure 21.7. SPI Master Timing (CKPHA = 1)........................................................ 180 Figure 21.8. SPI Slave Timing (CKPHA = 0).......................................................... 181 Figure 21.9. SPI Slave Timing (CKPHA = 1).......................................................... 181 22. Timers Figure 22.1. T0 Mode 0 Block Diagram.................................................................. 184 Figure 22.2. T0 Mode 2 Block Diagram.................................................................. 185 Figure 22.3. T0 Mode 3 Block Diagram.................................................................. 186 Figure 22.4. Timer 2 16-Bit Mode Block Diagram .................................................. 191 Figure 22.5. Timer 2 8-Bit Mode Block Diagram .................................................... 192 Rev. 1.2 7 C8051F350/1/2/3 Figure 22.6. Timer 3 16-Bit Mode Block Diagram .................................................. 195 Figure 22.7. Timer 3 8-Bit Mode Block Diagram .................................................... 196 23. Programmable Counter Array Figure 23.1. PCA Block Diagram............................................................................ 199 Figure 23.2. PCA Counter/Timer Block Diagram.................................................... 200 Figure 23.3. PCA Interrupt Block Diagram ............................................................. 201 Figure 23.4. PCA Capture Mode Diagram.............................................................. 202 Figure 23.5. PCA Software Timer Mode Diagram .................................................. 203 Figure 23.6. PCA High Speed Output Mode Diagram............................................ 204 Figure 23.7. PCA Frequency Output Mode ............................................................ 205 Figure 23.8. PCA 8-Bit PWM Mode Diagram ......................................................... 206 Figure 23.9. PCA 16-Bit PWM Mode...................................................................... 207 Figure 23.10. PCA Module 2 with Watchdog Timer Enabled ................................. 208 24. Revision Specific Behavior Figure 24.1. Reading Package Marking ................................................................. 215 25. C2 Interface Figure 25.1. Typical C2 Pin Sharing....................................................................... 218 8 Rev. 1.2 C8051F350/1/2/3 List of Tables 1. System Overview Table 1.1. Product Selection Guide ......................................................................... 15 4. Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F350/1/2/3 ................................................. 28 Table 4.2. LQFP-32 Package Dimensions .............................................................. 33 Table 4.3. QFN-28 Package Dimensions ................................................................ 34 5. 24 or 16-Bit Analog to Digital Converter (ADC0) Table 5.1. ADC0 Unipolar Output Word Coding (AD0POL = 0) .............................. 43 Table 5.2. ADC0 Bipolar Output Word Coding (AD0POL = 1) ................................ 43 Table 5.3. ADC0 SINC3 Filter Typical RMS Noise (µV) .......................................... 58 Table 5.4. ADC0 SINC3 Filter Effective Resolution1  in Unipolar Mode (bits) ......................................................................... 59 Table 5.5. ADC0 SINC3 Filter Flicker-Free (Noise-Free) Resolution1  in Unipolar Mode (bits) ......................................................................... 59 Table 5.6. ADC0 Fast Filter Typical RMS Noise (µV) ............................................. 60 Table 5.7. ADC0 Fast Filter Effective Resolution1 in Unipolar Mode (bits) ............. 60 Table 5.8. ADC0 Fast Filter Flicker-Free (Noise-Free) Resolution1  in Unipolar Mode (bits) ......................................................................... 61 10. CIP-51 Microcontroller Table 10.1. CIP-51 Instruction Set Summary .......................................................... 82 11. Memory Organization and SFRs Table 11.1. Special Function Register (SFR) Memory Map .................................... 93 Table 11.2. Special Function Registers ................................................................... 94 12. Interrupt Handler Table 12.1. Interrupt Summary ................................................................................ 98 19. SMBus Table 19.1. SMBus Clock Source Selection .......................................................... 146 Table 19.2. Minimum SDA Setup and Hold Times ................................................ 147 Table 19.3. Sources for Hardware Changes to SMB0CN ..................................... 151 Table 19.4. SMBus Status Decoding ..................................................................... 157 20. UART0 Table 20.1. Timer Settings for Standard Baud Rates Using the Internal Oscillator ............................................................... 167 Table 20.2. Timer Settings for Standard Baud Rates Using an External 25.0 MHz Oscillator ............................................... 167 Table 20.3. Timer Settings for Standard Baud Rates Using an External 22.1184 MHz Oscillator ......................................... 168 Table 20.4. Timer Settings for Standard Baud Rates Using an External 18.432 MHz Oscillator ........................................... 168 Table 20.5. Timer Settings for Standard Baud Rates Using an External 11.0592 MHz Oscillator ......................................... 169 Table 20.6. Timer Settings for Standard Baud Rates Using an External 3.6864 MHz Oscillator ........................................... 169 Rev. 1.1 9 C8051F350/1/2/3 21. Serial Peripheral Interface (SPI0) Table 21.1. SPI Slave Timing Parameters ............................................................ 182 23. Programmable Counter Array Table 23.1. PCA Timebase Input Options ............................................................. 200 Table 23.2. PCA0CPM Register Settings for PCA Capture/Compare Modules .... 201 Table 23.3. Watchdog Timer Timeout Intervals1 ................................................... 209 10 Rev. 1.1 C8051F350/1/2/3 List of Registers SFR Definition 5.1. ADC0CN: ADC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 SFR Definition 5.2. ADC0CF: ADC0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 SFR Definition 5.3. ADC0MD: ADC0 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 SFR Definition 5.4. ADC0CLK: ADC0 Modulator Clock Divisor . . . . . . . . . . . . . . . . . . 47 SFR Definition 5.5. ADC0DECH: ADC0 Decimation Ratio Register High Byte . . . . . . 47 SFR Definition 5.6. ADC0DECL: ADC0 Decimation Ratio Register Low Byte . . . . . . . 48 SFR Definition 5.7. ADC0DAC: ADC0 Offset DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 SFR Definition 5.8. ADC0BUF: ADC0 Input Buffer Control . . . . . . . . . . . . . . . . . . . . . 49 SFR Definition 5.9. ADC0STA: ADC0 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 SFR Definition 5.10. ADC0COH: ADC0 Offset Calibration Register High Byte . . . . . . 51 SFR Definition 5.11. ADC0COM: ADC0 Offset Calibration Register Middle Byte . . . . 51 SFR Definition 5.12. ADC0COL: ADC0 Offset Calibration Register Low Byte . . . . . . . 51 SFR Definition 5.13. ADC0CGH: ADC0 Gain Calibration Register High Byte . . . . . . . 52 SFR Definition 5.14. ADC0CGM: ADC0 Gain Calibration Register Middle Byte . . . . . 52 SFR Definition 5.15. ADC0CGL: ADC0 Gain Calibration Register Low Byte . . . . . . . . 52 SFR Definition 5.16. ADC0H: ADC0 Conversion Register (SINC3 Filter) High Byte . . 53 SFR Definition 5.17. ADC0M: ADC0 Conversion Register (SINC3 Filter) Middle Byte 53 SFR Definition 5.18. ADC0L: ADC0 Conversion Register (SINC3 Filter) Low Byte . . . 53 SFR Definition 5.19. ADC0FH: ADC0 Conversion Register (Fast Filter) High Byte . . . 54 SFR Definition 5.20. ADC0FM: ADC0 Conversion Register (Fast Filter) Middle Byte . 54 SFR Definition 5.21. ADC0FL: ADC0 Conversion Register (Fast Filter) Low Byte . . . . 54 SFR Definition 5.22. ADC0MUX: ADC0 Analog Multiplexer Control . . . . . . . . . . . . . . 56 SFR Definition 6.1. IDA0CN: IDA0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 SFR Definition 6.2. IDA0: IDA0 Data Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 SFR Definition 6.3. IDA1CN: IDA1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 SFR Definition 6.4. IDA1: IDA1 Data Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 SFR Definition 7.1. REF0CN: Reference Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 SFR Definition 9.1. CPT0CN: Comparator0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 SFR Definition 9.2. CPT0MD: Comparator0 Mode Selection . . . . . . . . . . . . . . . . . . . . 76 SFR Definition 9.3. CPT0MX: Comparator0 MUX Selection . . . . . . . . . . . . . . . . . . . . 78 SFR Definition 10.1. SP: Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 SFR Definition 10.2. DPL: Data Pointer Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 SFR Definition 10.3. DPH: Data Pointer High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 SFR Definition 10.4. PSW: Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 SFR Definition 10.5. ACC: Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 SFR Definition 10.6. B: B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 SFR Definition 10.7. PCON: Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SFR Definition 12.1. IE: Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 SFR Definition 12.2. IP: Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 SFR Definition 12.3. EIE1: Extended Interrupt Enable 1 . . . . . . . . . . . . . . . . . . . . . . 101 SFR Definition 12.4. EIP1: Extended Interrupt Priority 1 . . . . . . . . . . . . . . . . . . . . . . 102 SFR Definition 12.5. IT01CF: INT0/INT1 Configuration . . . . . . . . . . . . . . . . . . . . . . . 104 SFR Definition 13.1. PFE0CN: Prefetch Engine Control . . . . . . . . . . . . . . . . . . . . . . 105 Rev. 1.2 11 C8051F350/1/2/3 SFR Definition 14.1. VDM0CN: VDD Monitor Control . . . . . . . . . . . . . . . . . . . . . . . . 108 SFR Definition 14.2. RSTSRC: Reset Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 SFR Definition 15.1. PSCTL: Program Store R/W Control . . . . . . . . . . . . . . . . . . . . . 116 SFR Definition 15.2. FLKEY: Flash Lock and Key . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 SFR Definition 15.3. FLSCL: Flash Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 SFR Definition 16.1. EMI0CN: External Memory Interface Control . . . . . . . . . . . . . . 118 SFR Definition 17.1. OSCICN: Internal Oscillator Control . . . . . . . . . . . . . . . . . . . . . 120 SFR Definition 17.2. OSCICL: Internal Oscillator Calibration . . . . . . . . . . . . . . . . . . . 120 SFR Definition 17.3. OSCXCN: External Oscillator Control . . . . . . . . . . . . . . . . . . . . 124 SFR Definition 17.4. CLKMUL: Clock Multiplier Control . . . . . . . . . . . . . . . . . . . . . . . 125 SFR Definition 17.5. CLKSEL: Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 SFR Definition 18.1. XBR0: Port I/O Crossbar Register 0 . . . . . . . . . . . . . . . . . . . . . 132 SFR Definition 18.2. XBR1: Port I/O Crossbar Register 1 . . . . . . . . . . . . . . . . . . . . . 133 SFR Definition 18.3. P0: Port0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 SFR Definition 18.4. P0MDIN: Port0 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 SFR Definition 18.5. P0MDOUT: Port0 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . 136 SFR Definition 18.6. P0SKIP: Port0 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 SFR Definition 18.7. P1: Port1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 SFR Definition 18.8. P1MDIN: Port1 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 SFR Definition 18.9. P1MDOUT: Port1 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . 138 SFR Definition 18.10. P1SKIP: Port1 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 SFR Definition 18.11. P2: Port2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 SFR Definition 18.12. P2MDOUT: Port2 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 139 SFR Definition 19.1. SMB0CF: SMBus Clock/Configuration . . . . . . . . . . . . . . . . . . . 148 SFR Definition 19.2. SMB0CN: SMBus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 SFR Definition 19.3. SMB0DAT: SMBus Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 SFR Definition 20.1. SCON0: Serial Port 0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 165 SFR Definition 20.2. SBUF0: Serial (UART0) Port Data Buffer . . . . . . . . . . . . . . . . . 166 SFR Definition 21.1. SPI0CFG: SPI0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 176 SFR Definition 21.2. SPI0CN: SPI0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 SFR Definition 21.3. SPI0CKR: SPI0 Clock Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 SFR Definition 21.4. SPI0DAT: SPI0 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 SFR Definition 22.1. TCON: Timer Contro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 SFR Definition 22.2. TMOD: Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 SFR Definition 22.3. CKCON: Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 SFR Definition 22.4. TL0: Timer 0 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 SFR Definition 22.5. TL1: Timer 1 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 SFR Definition 22.6. TH0: Timer 0 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 SFR Definition 22.7. TH1: Timer 1 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 SFR Definition 22.8. TMR2CN: Timer 2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 SFR Definition 22.9. TMR2RLL: Timer 2 Reload Register Low Byte . . . . . . . . . . . . . 194 SFR Definition 22.10. TMR2RLH: Timer 2 Reload Register High Byte . . . . . . . . . . . 194 SFR Definition 22.11. TMR2L: Timer 2 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 SFR Definition 22.12. TMR2H Timer 2 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 SFR Definition 22.13. TMR3CN: Timer 3 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 12 Rev. 1.2 C8051F350/1/2/3 SFR Definition 22.14. TMR3RLL: Timer 3 Reload Register Low Byte . . . . . . . . . . . . 198 SFR Definition 22.15. TMR3RLH: Timer 3 Reload Register High Byte . . . . . . . . . . . 198 SFR Definition 22.16. TMR3L: Timer 3 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 SFR Definition 22.17. TMR3H Timer 3 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 SFR Definition 23.1. PCA0CN: PCA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 SFR Definition 23.2. PCA0MD: PCA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 SFR Definition 23.3. PCA0CPMn: PCA Capture/Compare Mode . . . . . . . . . . . . . . . 212 SFR Definition 23.4. PCA0L: PCA Counter/Timer Low Byte . . . . . . . . . . . . . . . . . . . 213 SFR Definition 23.5. PCA0H: PCA Counter/Timer High Byte . . . . . . . . . . . . . . . . . . . 213 SFR Definition 23.6. PCA0CPLn: PCA Capture Module Low Byte . . . . . . . . . . . . . . . 214 SFR Definition 23.7. PCA0CPHn: PCA Capture Module High Byte . . . . . . . . . . . . . . 214 Rev. 1.2 13 C8051F350/1/2/3 1. System Overview C8051F350/1/2/3 devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are listed below. Refer to Table 1.1 for specific product feature selection. • • • • • • • • • • • • • High-speed pipelined 8051-compatible microcontroller core (up to 50 MIPS) In-system, full-speed, non-intrusive debug interface (on-chip) 24 or 16-bit single-ended/differential ADC with analog multiplexer Two 8-bit Current Output DACs Precision programmable 24.5 MHz internal oscillator 8 kB of on-chip Flash memory 768 bytes of on-chip RAM SMBus/I2C, Enhanced UART, and SPI serial interfaces implemented in hardware Four general-purpose 16-bit timers Programmable counter/timer array (PCA) with three capture/compare modules and watchdog timer function On-chip power-on reset, VDD monitor, and temperature sensor On-chip voltage comparator 17 Port I/O (5 V tolerant) With on-chip power-on reset, VDD monitor, watchdog timer, and clock oscillator, the C8051F350/1/2/3 devices are truly stand-alone System-on-a-Chip solutions. The Flash memory can be reprogrammed even in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. User software has complete control of all peripherals, and may individually shut down any or all peripherals for power savings. The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging without occupying package pins. Each device is specified for 2.7 to 3.6 V operation over the industrial temperature range (–45 to +85 °C). The Port I/O and /RST pins are tolerant of input signals up to 5 V. The C8051F350/1/2/3 are available in 28-pin QFN (also referred to as MLP or MLF) or 32-pin LQFP packaging, as shown in Figure 1.1 through Figure 1.4. 14 Rev. 1.2 Calibrated Internal 24.5 MHz Oscillator Clock Multiplier SMBus/I2C SPI UART Timers (16-bit) Programmable Counter Array Digital Port I/Os 24-bit ADC 16-bit ADC Two 8-bit Current Output DACs Internal Voltage Reference Temperature Sensor Analog Comparator Lead-free (RoHS Compliant) Package C8051F350-GQ 50 8 kB 768      4  17  —      LQFP-32 C8051F351-GM 50 8 kB 768      4  17  —      QFN-28 C8051F352-GQ 50 8 kB 768      4  17 —       LQFP-32 C8051F353-GM 50 8 kB 768      4  17 —       QFN-28 RAM Flash Memory MIPS (Peak) Ordering Part Number C8051F350/1/2/3 Table 1.1. Product Selection Guide Rev. 1.2 15 C8051F350/1/2/3 VDD Digital Power GND AV+ Analog Power AGND C2D Debug HW Reset /RST/C2CK BrownOut POR XTAL1 XTAL2 External Oscillator Circuit System Clock 24.5 MHz 2% Internal Oscillator Clock Multiplier P0.0 8 kB FLASH 8 0 5 1 256 byte SRAM 512 byte XRAM C o SFR Bus r e P0.1 P0.2/XTAL1 P 0 Port 0 Latch P0.3/XTAL2 D r v UART Timer 0, 1, 2, 3 X B A R 3-Chnl PCA/ WDT SMBus P0.4/TX P0.5/RX P0.6/CNVSTR P0.7 CP0 + CP0A - CP0+ CP0- SPI Bus VREF+ P1.0 VREF– VREF Port 1 Latch P1.1 P1.2 P 1 AIN0 AIN1 AIN2 AIN3 A M U X AIN4 AIN5 + Buffer 8-bit IDAC0 24-bit ADC0 PGA + P1.3 P1.4/CP0A D r v Offset DAC P1.5/CP0 P1.6/IDAC0 P1.7/IDAC1 8-bit IDAC1 AIN6 AIN7 C2D Temp Sensor Port 2 Latch P2.0/C2D Figure 1.1. C8051F350 Block Diagram VDD GND AV+ Digital Power Analog Power AGND C2D Debug HW Reset /RST/C2CK POR BrownOut External Oscillator Circuit XTAL1 XTAL2 System Clock 24.5 MHz 2% Internal Oscillator Clock Multiplier P0.0 P0.1 8 kB FLASH 8 0 5 1 256 byte SRAM 512 byte XRAM C o SFR Bus r e D r v UART Timer 0, 1, 2, 3 X B A R 3-Chnl PCA/ WDT SMBus SPI Bus VREF+ VREF– VREF AIN4 AIN5 AIN6 AIN7 A M U X Buffer + + PGA + CP0A - 8-bit IDAC0 24-bit ADC0 CP0+ CP0- P1.0/AIN4 P1.1/AIN5 P 1 P1.2/AIN6 P1.3/AIN7 D r v P1.4/CP0A P1.5/CP0 P1.6/IDAC0 P1.7/IDAC1 8-bit IDAC1 C2D Temp Sensor Port 2 Latch Figure 1.2. C8051F351 Block Diagram 16 P0.7 CP0 Port 1 Latch Offset DAC AIN3 P0.5/RX P0.6/CNVSTR AIN4-7 AIN0 AIN1 AIN2 P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P 0 Port 0 Latch Rev. 1.2 P2.0/C2D C8051F350/1/2/3 VDD GND AV+ AGND Digital Power Analog Power C2D Debug HW Reset /RST/C2CK POR BrownOut External Oscillator Circuit XTAL1 XTAL2 System Clock 24.5 MHz 2% Internal Oscillator Clock Multiplier P0.0 8 kB FLASH 8 0 5 1 256 byte SRAM D r v UART 512 byte XRAM Timer 0, 1, 2, 3 C o SFR Bus r e P0.1 P0.2/XTAL1 P0.3/XTAL2 P 0 Port 0 Latch X B A R 3-Chnl PCA/ WDT SMBus P0.4/TX P0.5/RX P0.6/CNVSTR P0.7 CP0 + CP0A - CP0+ CP0- SPI Bus VREF+ VREF– P1.0 Port 1 Latch VREF P1.1 P1.2 P1.3 P1.4/CP0A P 1 AIN0 AIN1 D r v Offset DAC AIN2 AIN3 AIN4 A M U X AIN5 AIN6 AIN7 + Buffer 8-bit IDAC0 16-bit ADC0 PGA + P1.5/CP0 P1.6/IDAC0 P1.7/IDAC1 8-bit IDAC1 C2D Temp Sensor Port 2 Latch P2.0/C2D Figure 1.3. C8051F352 Block Diagram VDD Digital Power GND AV+ AGND Analog Power C2D Debug HW Reset /RST/C2CK POR BrownOut External Oscillator Circuit XTAL1 XTAL2 System Clock x2 24.5 MHz 2% Internal Oscillator P0.0 8 kB FLASH 8 0 5 1 P0.1 256 byte SRAM Timer 0, 1, 2, 3 C o SFR Bus r e P0.5/RX P0.6/CNVSTR X B A R 3-Chnl PCA/ WDT SMBus SPI Bus VREF+ P0.3/XTAL2 P0.4/TX D r v UART 512 byte XRAM P0.2/XTAL1 P 0 Port 0 Latch P0.7 CP0 + CP0A - CP0+ CP0- AIN4-7 P1.0/AIN4 VREF– Port 1 Latch VREF P1.1/AIN5 AIN0 AIN1 Offset DAC AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 A M U X Buffer + + PGA 8-bit IDAC0 16-bit ADC0 P 1 P1.2/AIN6 D r v P1.4/CP0A P1.3/AIN7 P1.5/CP0 P1.6/IDAC0 P1.7/IDAC1 8-bit IDAC1 C2D Temp Sensor Port 2 Latch P2.0/C2D Figure 1.4. C8051F353 Block Diagram Rev. 1.2 17 C8051F350/1/2/3 1.1. CIP-51™ Microcontroller 1.1.1. Fully 8051 Compatible Instruction Set The C8051F35x devices use Silicon Labs’ proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51™ instruction set. Standard 803x/805x assemblers and compilers can be used to develop software. The C8051F35x family has a superset of all the peripherals included with a standard 8052. 1.1.2. Improved Throughput The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute, and usually have a maximum system clock of 12 to 24 MHz. By contrast, the CIP51 core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more than eight system clock cycles. With the CIP-51's system clock running at 50 MHz, it has a peak throughput of 50 MIPS. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execution time. Clocks to Execute 1 2 2/3 3 3/4 4 4/5 5 8 Number of Instructions 26 50 5 14 7 3 1 2 1 1.1.3. Additional Features The C8051F350/1/2/3 SoC family includes several key enhancements to the CIP-51 core and peripherals to improve performance and ease of use in end applications. An extended interrupt handler allows the numerous analog and digital peripherals to operate independently of the controller core and interrupt the controller only when necessary. By requiring less intervention from the microcontroller core, an interrupt-driven system is more efficient and allows for easier implementation of multi-tasking, real-time systems. Eight reset sources are available: power-on reset circuitry (POR), an on-chip VDD monitor, a Watchdog Timer, a Missing Clock Detector, a voltage level detection from Comparator0, a forced software reset, an external reset pin, and an illegal Flash access protection circuit. Each reset source except for the POR, Reset Input Pin, or Flash error may be disabled by the user in software. The WDT may be permanently enabled in software after a power-on reset during MCU initialization. The internal oscillator is factory calibrated to 24.5 MHz ±2%. An external oscillator drive circuit is also included, allowing an external crystal, ceramic resonator, capacitor, RC, or CMOS clock source to generate the system clock. A clock multiplier allows for operation at up to 50 MHz. An external oscillator can also be extremely useful in low power applications, allowing the MCU to run from a slow (power saving) source, while periodically switching to the fast internal oscillator as needed. 18 Rev. 1.2 C8051F350/1/2/3 1.2. On-Chip Debug Circuitry The C8051F350/1/2/3 devices include on-chip Silicon Labs 2-Wire (C2) debug circuitry that provides nonintrusive, full speed, in-circuit debugging of the production part installed in the end application. Silicon Labs' debugging system supports inspection and modification of memory and registers, breakpoints, and single stepping. No additional target RAM, program memory, timers, or communications channels are required. All the digital and analog peripherals are functional and work correctly while debugging. All the peripherals (except for the ADC and SMBus) are stalled when the MCU is halted, during single stepping, or at a breakpoint in order to keep them synchronized. The C8051F350DK development kit provides all the hardware and software necessary to develop application code and perform in-circuit debugging with the C8051F35x MCUs. The kit includes software with a developer's studio and debugger, a C2 debug adapter, a target application board with the associated MCU installed, and the required cables and wall-mount power supply. The development kit requires a computer with Windows 98 SE or later installed. The Silicon Labs IDE interface is a vastly superior developing and debugging configuration, compared to standard MCU emulators that use on-board "ICE Chips" and require the MCU in the application board to be socketed. Silicon Labs' debug paradigm increases ease of use and preserves the performance of the precision analog peripherals. Silicon Labs Integrated Development Environment WINDOWS 98 SE or later Debug Adapter C2 (x2), VDD, GND VDD TARGET PCB GND C8051F350 Figure 1.5. Development/In-System Debug Diagram Rev. 1.2 19 C8051F350/1/2/3 1.3. On-Chip Memory The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as four banks of general purpose registers, and the next 16 bytes can be byte addressable or bit addressable. Program memory consists of 8 kB bytes of Flash. This memory may be reprogrammed in-system in 512 byte sectors, and requires no special off-chip programming voltage. DATA MEMORY (RAM) INTERNAL DATA ADDRESS SPACE PROGRAM/DATA MEMORY (Flash) 0x1FFF 0x1E00 RESERVED 0x1DFF 0xFF 0x80 0x7F Upper 128 RAM (Indirect Addressing Only) (Direct and Indirect Addressing) 8 kB Flash (In-System Programmable in 512 Byte Sectors) 0x30 0x2F 0x20 0x1F 0x00 Bit Addressable Lower 128 RAM (Direct and Indirect Addressing) General Purpose Registers EXTERNAL DATA ADDRESS SPACE 0x0000 0xFFFF Same 512 bytes as from 0x0000 to 0x01FF, wrapped on 512-byte boundaries 0x0200 0x01FF 0x0000 XRAM - 512 Bytes (accessable using MOVX instruction) Figure 1.6. Memory Map 20 Special Function Register's (Direct Addressing Only) Rev. 1.2 C8051F350/1/2/3 1.4. 24 or 16-Bit Analog to Digital Converter (ADC0) The C8051F350/1/2/3 include a fully-differential, 24-bit (C8051F350/1) or 16-bit (C8051F352/3) SigmaDelta Analog to Digital Converter (ADC) with on-chip calibration capabiliites. Two separate decimation filters can be programmed for throughputs of up to 1 kHz. An internal 2.5 V reference is available, or a differential external reference can be used for ratiometric measurements. A Programmable Gain Amplifier (PGA) is included, with eight gain settings up to 128x. An analog front-end multiplexer connects the differential inputs to eight external pins, the internal temperature sensor, or AGND. The on-chip input buffers can be used to provide a high input impedance for direct connection to sensitive transducers. An 8-bit offset DAC allows for correction of large input offset voltages. AV+ Internal 2.5V or External VREF Burnout Current Sources Eight External Inputs Temperature Sensor AIN+  SINC3 Filter PGA AIN- Modulator  Input Buffers AGND Fast Filter 1x to 128x 8-Bit Offset DAC Figure 1.7. ADC0 Block Diagram Rev. 1.2 21 C8051F350/1/2/3 1.5. Two 8-bit Current-Mode DACs The C8051F350/1/2/3 devices include two 8-bit current-mode Digital-to-Analog Converters (IDACs). The maximum current output of the IDACs can be adjusted for four different current settings; 0.25 mA, 0.5 mA, 1 mA, and 2 mA. A flexible output update mechanism allows for seamless full-scale changes, and supports jitter-free updates for waveform generation. IDAC updates can be performed on-demand, scheduled on a Timer overflow, or synchronized with an external signal. Figure 1.8 shows a block diagram of the IDAC circuitry. 8 8-bit Digital Input 8 Latch 8-bit Digital Input 8 Latch Data Write Timer 0 Timer 1 Timer 2 Timer 3 CNVSTR 8 IDA0 Current Output IDA1 Current Output Data Write Timer 0 Timer 1 Timer 2 Timer 3 CNVSTR Figure 1.8. IDAC Block Diagram 22 Rev. 1.2 C8051F350/1/2/3 1.6. Programmable Comparator C8051F350/1/2/3 devices include a software-configurable voltage comparator with an input multiplexer. The Comparator offers programmable response time and hysteresis and two outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0), or an asynchronous “raw” output (CP0A). Comparator interrupts may be generated on rising, falling, or both edges. When in IDLE mode, these interrupts may be used as a “wake-up” source for the processor. Comparator0 may also be configured as a reset source. A block diagram of the Comparator is shown in Figure 1.9. VDD Port I/O Pins Multiplexer Interrupt Logic + D - SET CLR Q Q D SET CLR Q CP0 (synchronous output) Q (SYNCHRONIZER) CP0A (asynchronous output) GND Reset Decision Tree Figure 1.9. Comparator0 Block Diagram 1.7. Serial Ports The C8051F350/1/2/3 Family includes an SMBus/I2C interface, a full-duplex UART with enhanced baud rate configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention. Rev. 1.2 23 C8051F350/1/2/3 1.8. Port Input/Output C8051F350/1/2/3 devices include 17 I/O pins. Port pins are organized as two byte-wide ports and one 1-bit port. The port pins behave like typical 8051 ports with a few enhancements. Each port pin can be configured as a digital or analog I/O pin. Pins selected as digital I/O can be configured for push-pull or open-drain operation. The “weak pull-ups” that are fixed on typical 8051 devices may be globally disabled to save power. The Digital Crossbar allows mapping of internal digital system resources to port I/O pins. On-chip conter/timers, serial buses, hardware interrupts, and other digital signals can be configured to appear on the port pins using the Crossbar control resgiters. This allows the user to select the exact mix of general-purpose port I/O, digital, and analog resources needed for the application. XBR0, XBR1, PnSKIP Registers PnMDOUT, PnMDIN Registers Priority Decoder (Internal Digital Signals) Highest Priority CP0 Outputs 2 Digital Crossbar 4 SPI SMBus 8 4 T0, T1 8 2 SYSCLK PCA Lowest Priority 2 UART P0 I/O Cells P0.0 P1 I/O Cells P1.0 P0.7 P1.7 2 (Port Latches) 8 P0 (P0.0-P0.7) P1 (P1.0-P1.7) 8 P2 (P2.0) P2 I/O Cell Figure 1.10. Port I/O Functional Block Diagram 24 Rev. 1.2 P2.0 C8051F350/1/2/3 1.9. Programmable Counter Array The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer and three 16-bit capture/compare modules. The counter/timer is driven by a programmable timebase that can select between six sources: system clock, system clock divided by four, system clock divided by twelve, the external oscillator clock source divided by 8, Timer 0 overflow, or an external clock signal on the External Clock nput (ECI) input pin. Each capture/compare module may be configured to operate independently in one of six modes: EdgeTriggered Capture, Software Timer, High-Speed Output, Frequency Output, 8-Bit PWM, or 16-Bit PWM. Additionally, PCA Module 2 may be used as a watchdog timer (WDT), and is enabled in this mode following a system reset. The PCA Capture/Compare Module I/O and the External Clock Input may be routed to Port I/O using the digital crossbar. SYSCLK/12 SYSCLK/4 Timer 0 Overflow ECI SYSCLK PCA CLOCK MUX 16-Bit Counter/Timer External Clock/8 Capture/Compare Module 0 Capture/Compare Module 1 Capture/Compare Module 2 / WDT CEX2 CEX1 CEX0 ECI Crossbar Port I/O Figure 1.11. PCA Block Diagram Rev. 1.2 25 C8051F350/1/2/3 2. Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings Parameter Min Typ Max Units Ambient temperature under bias –55 — 125 °C Storage Temperature –65 — 150 °C Voltage on AIN0.0–AIN0.7, VREF+, and VREF– with respect to DGND –0.3 — VDD + 0.3 V Voltage on any Port 0, 1, or 2 Pin or /RST with respect to DGND –0.3 — 5.8 V Voltage on VDD with respect to DGND –0.3 — 4.2 V Voltage on AV+ with respect to AGND –0.3 — 4.2 V Maximum output current sunk by any Port 0, 1, or 2 pin — — 100 mA Maximum output current sunk by any other I/O pin — — 50 mA Maximum output current sourced by any Port 0, 1, or 2 pin — — 100 mA Maximum output current sourced by any other I/O pin — — 50 mA Maximum Total current through VDD, AV+, DGND, and AGND — — 500 mA Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 26 Rev. 1.2 C8051F350/1/2/3 3. Global DC Electrical Characteristics Table 3.1. Global DC Electrical Characteristics –40 to +85 °C, 25 MHz System Clock unless otherwise specified. Parameter Analog Supply Voltage Conditions 1 Min Typ Max Units 2.7 3.0 3.6 V Analog Supply Current Internal REF, ADC, IDACs, Comparators all active — 0.75 1.3 mA Analog Supply Current with analog sub-systems inactive Internal REF, ADC, IDACs, Comparators all disabled, oscillator disabled —