C8051F396-A-GM

C8051F39x/37x 50 MIPS 16 kB Flash, 512B EEPROM Mixed-Signal MCU Analog Peripherals (‘F390/2/4/6/8 and ‘F370/4) - 10-Bit ADC • Programmable throughput up to 500 ksps • Up to 16 external inputs, programmable as single- • - Two 10-Bit Current Output DACs • - Supports output through resets for continuous operation - Comparator • • - ended or differential Reference from on-chip voltage reference, VDD or external VREF pin Internal or external start of conversion sources Programmable hysteresis and response time Configurable as interrupt or reset source Precision Temperature Sensor • Accurate to ±2 °C across temperature range with no user calibration On-Chip Debug - On-chip debug circuitry facilitates full speed, non- intrusive in-system debug (no emulator required) Provides breakpoints, single stepping, inspect/modify memory and registers Low Power - 160 µA/MHz Active mode with 49 MHz internal precision oscillator - 200 nA Stop mode current Temperature Range - –40 to +85 °C (‘F37x) - –40 to +105 °C (‘F39x) Package - 24-Pin QFN (‘F390/1/4/5 and ‘F37x) - 20-Pin QFN (‘F392/3/6/7/8/9) VREF 10-bit 10-bit Current Current DAC DAC Temp Sensor Precision Temp Sensor – VOLTAGE COMPARATOR Digital Peripherals - 21 or 17 Port I/O - UART, 2 SMBus (I2C compatible), and SPI serial - ports Six general purpose 16-bit counter/timers 16-Bit programmable counter array (PCA) with three capture/compare modules and PWM functionality Clock Sources - 49 MHz ±2% precision internal oscillator • Supports crystal-less UART operation • Low-power suspend mode with fast wake time - 80 kHz low-frequency, low-power oscillator - External oscillator: Crystal, RC, C, or CMOS clock - Can switch between clock sources on-the-fly; useful in power saving modes 10-bit 500 ksps ADC + byte Sectors 512 bytes of byte-programmable EEPROM; 1 million write/erase cycles (‘F37x) Supply Voltage 1.8 to 3.6 V - Built-in voltage supply monitor ANALOG PERIPHERALS A M U X instructions in 1 or 2 system clocks - Up to 50 MIPS throughput with 50 MHz clock - Expanded interrupt handler Memory - Up to 1 kB internal data RAM (256 + 768) - Up to 16 kB Flash; In-system programmable in 512- ‘F390/2/4/6/8 & ‘F370/4 Only 49 MHz PRECISION INTERNAL OSCILLATOR DIGITAL I/O UART SMBus0 SMBus1 SPI PCA0 PCA1 PCA2 Timer 0 Timer 1 Timer 2 Timer 3 Timer 4 Timer 5 80 KHz LOW FREQUENCY INTERNAL OSCILLATOR Port 0 CROSSBAR • High-Speed 8051 µC Core - Pipelined instruction architecture; executes 70% of Port 1 P2.0 P2.1– P2.4* *P2.1–2.4 QFN24 Only 512 B EEPROM HIGH-SPEED CONTROLLER CORE 16/8 kB 8051 CPU 1024 B ISP FLASH (50 MIPS) SRAM FLEXIBLE DEBUG POR WDT INTERRUPTS CIRCUITRY Rev. 1.2 2/19 Copyright © 2019 by Silicon Laboratories C8051F39x/37x C8051F39x/37x 2 Rev. 1.2 C8051F39x/37x 1. System Overview ..................................................................................................... 17 2. Ordering Information ............................................................................................... 20 3. C8051F33x Compatibility ........................................................................................ 21 3.1. Hardware Incompatibilities ................................................................................ 21 4. Pin Definitions.......................................................................................................... 22 5. QFN-20 Package Specifications ............................................................................. 28 6. QFN-24 Package Specifications ............................................................................. 30 7. Electrical Characteristics ........................................................................................ 32 7.1. Absolute Maximum Specifications..................................................................... 32 7.2. Electrical Characteristics ................................................................................... 33 7.3. Typical Performance Curves ............................................................................. 45 8. Precision Temperature Sensor (C8051F390/2/4/6/8 and C8051F370/4 Only)............................................................... 47 8.1. Temperature in Two’s Complement .................................................................. 47 9. 10-Bit ADC (ADC0, C8051F390/2/4/6/8 and C8051F370/4 Only) ........................... 50 9.1. Output Code Formatting .................................................................................... 51 9.2. Modes of Operation ........................................................................................... 52 9.2.1. Starting a Conversion................................................................................ 52 9.2.2. Tracking Modes......................................................................................... 53 9.2.3. Settling Time Requirements...................................................................... 54 9.3. Programmable Window Detector....................................................................... 58 9.3.1. Window Detector Example........................................................................ 60 9.4. ADC0 Analog Multiplexer (C8051F390/2/4/6/8 and C8051F370/4 Only) .......... 61 10. Temperature Sensor (C8051F390/2/4/6/8 and C8051F370/4 Only)..................... 64 10.1. Calibration ....................................................................................................... 65 11. 10-Bit Current Mode DACs (IDA0, IDA1, C8051F390/2/4/6/8 and C8051F370/4 Only) ............................................................................................................................ 66 11.1. IDAC Output Scheduling ................................................................................. 66 11.1.1. Update Output On-Demand .................................................................... 66 11.1.2. Update Output Based on Timer Overflow ............................................... 68 11.1.3. Update Output Based on CNVSTR Edge ............................................... 68 11.2. IDAC Reset Behavior ...................................................................................... 68 11.3. IDAC Output Mapping ..................................................................................... 68 12. Voltage Reference Options ................................................................................... 73 13. Voltage Regulator .................................................................................................. 75 13.1. Power Modes................................................................................................... 75 14. Comparator0........................................................................................................... 76 14.1. Comparator Multiplexer ................................................................................... 80 15. CIP-51 Microcontroller........................................................................................... 82 15.1. Instruction Set.................................................................................................. 83 15.1.1. Instruction and CPU Timing .................................................................... 83 15.2. CIP-51 Register Descriptions .......................................................................... 87 16. Prefetch Engine...................................................................................................... 92 17. Memory Organization ............................................................................................ 93 17.1. Program Memory............................................................................................. 94 Rev. 1.2 3 C8051F39x/37x 17.1.1. MOVX Instruction and Program Memory ................................................ 94 17.2. Data Memory ................................................................................................... 94 17.2.1. Internal RAM ........................................................................................... 94 17.2.1.1. General Purpose Registers ............................................................ 95 17.2.1.2. Bit Addressable Locations .............................................................. 95 17.2.1.3. Stack ............................................................................................ 95 17.2.2. External RAM .......................................................................................... 95 18. Device ID Registers ............................................................................................... 97 19. Special Function Registers................................................................................. 101 19.1. SFR Paging ................................................................................................... 101 19.2. Interrupts and Automatic SFR Paging ........................................................... 101 19.3. SFR Page Stack Example ............................................................................. 103 20. Interrupts .............................................................................................................. 117 20.1. MCU Interrupt Sources and Vectors.............................................................. 118 20.1.1. Interrupt Priorities.................................................................................. 118 20.1.2. Interrupt Latency ................................................................................... 118 20.2. Interrupt Register Descriptions ...................................................................... 120 20.3. External Interrupts INT0 and INT1................................................................. 128 21. Flash Memory....................................................................................................... 131 21.1. Programming The Flash Memory .................................................................. 131 21.1.1. Flash Lock and Key Functions .............................................................. 131 21.1.2. Flash Erase Procedure ......................................................................... 131 21.1.3. Flash Write Procedure .......................................................................... 132 21.2. Non-volatile Data Storage ............................................................................. 132 21.3. Security Options ............................................................................................ 133 21.4. Flash Write and Erase Guidelines ................................................................. 135 21.4.1. VDD Maintenance and the VDD Monitor ................................................ 135 21.4.2. PSWE Maintenance .............................................................................. 135 21.4.3. System Clock ........................................................................................ 136 22. EEPROM (C8051F37x) ......................................................................................... 140 22.1. EEPROM Communication Protocol.............................................................. 140 22.1.1. Slave Address Byte............................................................................... 141 22.1.2. Acknowledgement (ACK) ...................................................................... 141 22.1.3. Not-Acknowledgement (NACK)............................................................. 141 22.1.4. Reset..................................................................................................... 141 22.2. Write Operation ............................................................................................. 142 22.3. Read Operation ............................................................................................. 143 22.3.1. Current Address Read .......................................................................... 143 22.3.2. Selective Address Read........................................................................ 145 23. Cyclic Redundancy Check Unit (CRC0)............................................................. 147 23.1. CRC Algorithm............................................................................................... 147 23.2. Preparing for a CRC Calculation ................................................................... 149 23.3. Performing a CRC Calculation ...................................................................... 149 23.4. Accessing the CRC0 Result .......................................................................... 149 23.5. CRC0 Bit Reverse Feature............................................................................ 149 4 Rev. 1.2 C8051F39x/37x 24. Reset Sources ...................................................................................................... 155 24.1. Power-On Reset ............................................................................................ 156 24.2. Power-Fail Reset / VDD Monitor ................................................................... 157 24.3. External Reset ............................................................................................... 159 24.4. Missing Clock Detector Reset ....................................................................... 159 24.5. Comparator0 Reset ....................................................................................... 159 24.6. PCA Watchdog Timer Reset ......................................................................... 159 24.7. Flash Error Reset .......................................................................................... 159 24.8. Software Reset .............................................................................................. 159 25. Power Management Modes................................................................................. 161 25.1. Idle Mode....................................................................................................... 161 25.2. Stop Mode ..................................................................................................... 162 25.3. Suspend Mode .............................................................................................. 162 26. Oscillators and Clock Selection ......................................................................... 164 26.1. System Clock Selection................................................................................. 165 26.2. Programmable Internal High-Frequency (H-F) Oscillator .............................. 166 26.2.1. Internal Oscillator Suspend Mode ......................................................... 166 26.3. Programmable Internal Low-Frequency (L-F) Oscillator ............................... 168 26.3.1. Calibrating the Internal L-F Oscillator.................................................... 168 26.4. Internal Low-Power Oscillator........................................................................ 169 26.5. External Oscillator Drive Circuit..................................................................... 169 26.5.1. External Crystal Mode........................................................................... 169 26.5.2. External RC Example............................................................................ 171 26.5.3. External Capacitor Example.................................................................. 171 27. Port Input/Output ................................................................................................. 173 27.1. Port I/O Modes of Operation.......................................................................... 174 27.1.1. Port Pins Configured for Analog I/O...................................................... 174 27.1.2. Port Pins Configured For Digital I/O...................................................... 174 27.2. Assigning Port I/O Pins to Analog and Digital Functions............................... 175 27.2.1. Assigning Port I/O Pins to Analog Functions ........................................ 175 27.2.2. Assigning Port I/O Pins to Digital Functions.......................................... 176 27.2.3. Assigning Port I/O Pins to External Event Trigger Functions................ 177 27.3. Priority Crossbar Decoder ............................................................................. 178 27.4. Port I/O Initialization ...................................................................................... 180 27.5. Port Match ..................................................................................................... 183 27.6. Special Function Registers for Accessing and Configuring Port I/O ............. 185 28. SMBus0 and SMBus1 (I2C Compatible)............................................................. 192 28.1. Supporting Documents .................................................................................. 193 28.2. SMBus Configuration..................................................................................... 193 28.3. SMBus Operation .......................................................................................... 193 28.3.1. Transmitter vs. Receiver ....................................................................... 194 28.3.2. Arbitration.............................................................................................. 194 28.3.3. Clock Low Extension............................................................................. 194 28.3.4. SCL Low Timeout.................................................................................. 194 28.3.5. SCL High (SMBus Free) Timeout ......................................................... 195 Rev. 1.2 5 C8051F39x/37x 28.4. Using the SMBus........................................................................................... 195 28.4.1. SMBus Configuration Register.............................................................. 195 28.4.2. SMBus Pin Swap .................................................................................. 197 28.4.3. SMBus Timing Control .......................................................................... 197 28.4.4. SMBnCN Control Register .................................................................... 201 28.4.4.1. Software ACK Generation ............................................................ 201 28.4.4.2. Hardware ACK Generation ........................................................... 201 28.4.5. Hardware Slave Address Recognition .................................................. 204 28.4.6. Data Register ........................................................................................ 209 28.5. SMBus Transfer Modes................................................................................. 211 28.5.1. Write Sequence (Master) ...................................................................... 211 28.5.2. Read Sequence (Master) ...................................................................... 212 28.5.3. Write Sequence (Slave) ........................................................................ 213 28.5.4. Read Sequence (Slave) ........................................................................ 214 28.6. SMBus Status Decoding................................................................................ 214 29. UART0 ................................................................................................................... 220 29.1. Enhanced Baud Rate Generation.................................................................. 221 29.2. Operational Modes ........................................................................................ 222 29.2.1. 8-Bit UART ............................................................................................ 222 29.2.2. 9-Bit UART ............................................................................................ 223 29.3. Multiprocessor Communications ................................................................... 224 30. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 228 30.1. Signal Descriptions........................................................................................ 229 30.1.1. Master Out, Slave In (MOSI)................................................................. 229 30.1.2. Master In, Slave Out (MISO)................................................................. 229 30.1.3. Serial Clock (SCK) ................................................................................ 229 30.1.4. Slave Select (NSS) ............................................................................... 229 30.2. SPI0 Master Mode Operation ........................................................................ 230 30.3. SPI0 Slave Mode Operation .......................................................................... 231 30.4. SPI0 Interrupt Sources .................................................................................. 232 30.5. Serial Clock Phase and Polarity .................................................................... 232 30.6. SPI Special Function Registers ..................................................................... 234 31. Timers ................................................................................................................... 242 31.1. Timer 0 and Timer 1 ...................................................................................... 245 31.1.1. Mode 0: 13-bit Counter/Timer ............................................................... 245 31.1.2. Mode 1: 16-bit Counter/Timer ............................................................... 246 31.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload..................................... 247 31.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................ 248 31.2. Timer 2 .......................................................................................................... 253 31.2.1. 16-bit Timer with Auto-Reload............................................................... 253 31.2.2. 8-bit Timers with Auto-Reload............................................................... 254 31.2.3. Low-Frequency Oscillator (LFO) Capture Mode ................................... 255 31.3. Timer 3 .......................................................................................................... 259 31.3.1. 16-bit Timer with Auto-Reload............................................................... 259 31.3.2. 8-bit Timers with Auto-Reload............................................................... 260 6 Rev. 1.2 C8051F39x/37x 31.3.3. Low-Frequency Oscillator (LFO) Capture Mode ................................... 261 31.4. Timer 4 .......................................................................................................... 265 31.4.1. 16-bit Timer with Auto-Reload............................................................... 265 31.4.2. 8-bit Timers with Auto-Reload............................................................... 266 31.5. Timer 5 .......................................................................................................... 270 31.5.1. 16-bit Timer with Auto-Reload............................................................... 270 31.5.2. 8-bit Timers with Auto-Reload............................................................... 271 32. Programmable Counter Array............................................................................. 275 32.1. PCA Counter/Timer ....................................................................................... 276 32.2. PCA0 Interrupt Sources................................................................................. 277 32.3. Capture/Compare Modules ........................................................................... 278 32.3.1. Edge-triggered Capture Mode............................................................... 279 32.3.2. Software Timer (Compare) Mode.......................................................... 280 32.3.3. High-Speed Output Mode ..................................................................... 281 32.3.4. Frequency Output Mode ....................................................................... 282 32.3.5. 8-bit, 9-bit, 10-bit and 11-bit Pulse Width Modulator Modes ................ 282 32.3.5.1. 8-bit Pulse Width Modulator Mode............................................... 283 32.3.5.2. 9/10/11-bit Pulse Width Modulator Mode..................................... 284 32.3.6. 16-Bit Pulse Width Modulator Mode..................................................... 285 32.4. Watchdog Timer Mode .................................................................................. 286 32.4.1. Watchdog Timer Operation ................................................................... 286 32.4.2. Watchdog Timer Usage ........................................................................ 287 32.5. Comparator Clear Function ........................................................................... 288 32.6. Register Descriptions for PCA0..................................................................... 290 33. C2 Interface .......................................................................................................... 297 33.1. C2 Interface Registers................................................................................... 297 33.2. C2 Pin Sharing .............................................................................................. 300 Document Change List.............................................................................................. 301 Contact Information................................................................................................... 303 Rev. 1.2 7 C8051F39x/37x Figure 1.1. C8051F392/3/6/7/8/9 Block Diagram .................................................... 18 Figure 1.2. C8051F390/1/4/5 Block Diagram .......................................................... 18 Figure 1.3. C8051F370/1/4/5 Block Diagram .......................................................... 19 Figure 4.1. C8051F392/3/6/7/8/9 QFN-20 Pinout Diagram (Top View) ................... 25 Figure 4.2. C8051F390/1/4/5 Pinout Diagram (Top View) ...................................... 26 Figure 4.3. C8051F370/1/4/5 Pinout Diagram (Top View) ...................................... 27 Figure 5.1. QFN-20 Package Drawing .................................................................... 28 Figure 5.2. QFN-20 Recommended PCB Land Pattern .......................................... 29 Figure 6.1. QFN-24 Package Drawing .................................................................... 30 Figure 6.2. QFN-24 Recommended PCB Land Pattern .......................................... 31 Figure 7.1. Normal Mode Digital Supply Current vs. Frequency ............................. 45 Figure 7.2. Idle Mode Digital Supply Current vs. Frequency ................................... 45 Figure 7.3. Precision Temperature Sensor Error vs. Temperature ......................... 46 Figure 9.1. ADC0 Functional Block Diagram ........................................................... 50 Figure 9.2. 10-Bit ADC Track and Conversion Example Timing ............................. 53 Figure 9.3. ADC0 Equivalent Input Circuits ............................................................. 54 Figure 9.4. ADC Window Compare Example: Right-Justified, Single-Ended Data . 60 Figure 9.5. ADC Window Compare Example: Left-Justified, Single-Ended Data .... 60 Figure 9.6. ADC0 Multiplexer Block Diagram .......................................................... 61 Figure 10.1. Temperature Sensor Transfer Function .............................................. 64 Figure 10.2. Temperature Sensor Error with 1-Point Calibration at 0 °C ................ 65 Figure 11.1. IDA0 Functional Block Diagram .......................................................... 66 Figure 11.2. IDA1 Functional Block Diagram .......................................................... 67 Figure 11.3. IDA0 Data Word Mapping ................................................................... 68 Figure 12.1. Voltage Reference Functional Block Diagram ..................................... 73 Figure 14.1. Comparator0 Functional Block Diagram ............................................. 76 Figure 14.2. Comparator Hysteresis Plot ................................................................ 77 Figure 14.3. Comparator Input Multiplexer Block Diagram ...................................... 80 Figure 15.1. CIP-51 Block Diagram ......................................................................... 82 Figure 17.1. C8051F39x/37x Memory Map ............................................................. 93 Figure 17.2. Flash Program Memory Map ............................................................... 94 Figure 19.1. SFR Page Stack ................................................................................ 102 Figure 19.2. SFR Page Stack While Using SFR Page 0x0F To Access TS0CN .. 103 Figure 19.3. SFR Page Stack After SPI0 Interrupt Occurs .................................... 104 Figure 19.4. SFR Page Stack Upon PCA Interrupt Occurring During a SPI0 ISR 105 Figure 19.5. SFR Page Stack Upon Return from PCA0 Interrupt ......................... 106 Figure 19.6. SFR Page Stack Upon Return From SPI0 Interrupt .......................... 107 Figure 21.1. Security Byte Decoding ..................................................................... 133 Figure 22.1. Slave Address Byte Definition ........................................................... 141 Figure 22.2. Write Operation (Single Byte) ............................................................ 142 Figure 22.3. Write Operation (Multiple Bytes) ....................................................... 142 Figure 22.4. Current Address Read Operation (Single Byte) ................................ 143 Figure 22.5. Current Address Read Operation (Multiple Bytes) ............................ 144 Figure 22.6. Selective Address Read (Single Byte) .............................................. 145 Figure 22.7. Selective Address Read (Multiple Bytes) .......................................... 146 8 Rev. 1.2 C8051F39x/37x Figure 23.1. CRC0 Block Diagram ........................................................................ 147 Figure 23.2. Bit Reverse Register ......................................................................... 149 Figure 24.1. Reset Sources ................................................................................... 155 Figure 24.2. Power-On and VDD Monitor Reset Timing ....................................... 156 Figure 26.1. Oscillator Options .............................................................................. 164 Figure 26.2. External Crystal Example .................................................................. 170 Figure 27.1. Port I/O Functional Block Diagram .................................................... 173 Figure 27.2. Port I/O Cell Block Diagram .............................................................. 174 Figure 27.3. Crossbar Priority Decoder - Possible Pin Assignments .................... 178 Figure 27.4. Crossbar Priority Decoder Example .................................................. 179 Figure 28.1. SMBus0 Block Diagram .................................................................... 192 Figure 28.2. Typical SMBus Configuration ............................................................ 193 Figure 28.3. SMBus Transaction ........................................................................... 194 Figure 28.4. Typical SMBus SCL Generation ........................................................ 196 Figure 28.5. Typical Master Write Sequence ........................................................ 211 Figure 28.6. Typical Master Read Sequence ........................................................ 212 Figure 28.7. Typical Slave Write Sequence .......................................................... 213 Figure 28.8. Typical Slave Read Sequence .......................................................... 214 Figure 29.1. UART0 Block Diagram ...................................................................... 220 Figure 29.2. UART0 Baud Rate Logic ................................................................... 221 Figure 29.3. UART Interconnect Diagram ............................................................. 222 Figure 29.4. 8-Bit UART Timing Diagram .............................................................. 222 Figure 29.5. 9-Bit UART Timing Diagram .............................................................. 223 Figure 29.6. UART Multi-Processor Mode Interconnect Diagram ......................... 224 Figure 30.1. SPI Block Diagram ............................................................................ 228 Figure 30.2. Multiple-Master Mode Connection Diagram ...................................... 230 Figure 30.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram 231 Figure 30.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram 231 Figure 30.5. Master Mode Data/Clock Timing ....................................................... 233 Figure 30.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 233 Figure 30.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 234 Figure 30.8. SPI Master Timing (CKPHA = 0) ....................................................... 238 Figure 30.9. SPI Master Timing (CKPHA = 1) ....................................................... 239 Figure 30.10. SPI Slave Timing (CKPHA = 0) ....................................................... 239 Figure 30.11. SPI Slave Timing (CKPHA = 1) ....................................................... 240 Figure 31.1. T0 Mode 0 Block Diagram ................................................................. 246 Figure 31.2. T0 Mode 2 Block Diagram ................................................................. 247 Figure 31.3. T0 Mode 3 Block Diagram ................................................................. 248 Figure 31.4. Timer 2 16-Bit Mode Block Diagram ................................................. 253 Figure 31.5. Timer 2 8-Bit Mode Block Diagram ................................................... 254 Figure 31.6. Timer 2 Low-Frequency Oscillation Capture Mode Block Diagram ... 255 Figure 31.7. Timer 3 16-Bit Mode Block Diagram ................................................. 259 Figure 31.8. Timer 3 8-Bit Mode Block Diagram ................................................... 260 Rev. 1.2 9 C8051F39x/37x Figure 31.9. Timer 3 Low-Frequency Oscillation Capture Mode Block Diagram ... 261 Figure 31.10. Timer 4 16-Bit Mode Block Diagram ............................................... 265 Figure 31.11. Timer 4 8-Bit Mode Block Diagram ................................................. 266 Figure 31.12. Timer 5 16-Bit Mode Block Diagram ............................................... 270 Figure 31.13. Timer 5 8-Bit Mode Block Diagram ................................................. 271 Figure 32.1. PCA Block Diagram ........................................................................... 275 Figure 32.2. PCA Counter/Timer Block Diagram ................................................... 276 Figure 32.3. PCA Interrupt Block Diagram ............................................................ 277 Figure 32.4. PCA Capture Mode Diagram ............................................................. 279 Figure 32.5. PCA Software Timer Mode Diagram ................................................. 280 Figure 32.6. PCA High-Speed Output Mode Diagram ........................................... 281 Figure 32.7. PCA Frequency Output Mode ........................................................... 282 Figure 32.8. PCA 8-Bit PWM Mode Diagram ........................................................ 283 Figure 32.9. PCA 9, 10 and 11-Bit PWM Mode Diagram ...................................... 284 Figure 32.10. PCA 16-Bit PWM Mode ................................................................... 285 Figure 32.11. PCA Module 2 with Watchdog Timer Enabled ................................ 286 Figure 32.12. Comparator Clear Function Diagram .............................................. 288 Figure 32.13. CEXn with CPCEn = 1, CPCPOL = 0 .............................................. 288 Figure 32.14. CEXn with CPCEn = 1, CPCPOL = 1 .............................................. 289 Figure 32.15. CEXn with CPCEn = 1, CPCPOL = 0 .............................................. 289 Figure 32.16. CEXn with CPCEn = 1, CPCPOL = 1 .............................................. 289 Figure 33.1. Typical C2 Pin Sharing ...................................................................... 300 10 Rev. 1.2 C8051F39x/37x Table 2.1. Product Selection Guide ......................................................................... 20 Table 3.1. C8051F33x Replacement Part Numbers ................................................ 21 Table 4.1. Pin Definitions for the C8051F39x/37x ................................................... 22 Table 5.1. QFN-20 Package Dimensions ................................................................ 28 Table 5.2. QFN-20 PCB Land Pattern Dimensions ................................................. 29 Table 6.1. QFN-24 Package Dimensions ................................................................ 30 Table 6.2. QFN-24 PCB Land Pattern Dimensions ................................................. 31 Table 7.1. Absolute Maximum Ratings .................................................................... 32 Table 7.2. Global Electrical Characteristics ............................................................. 33 Table 7.3. Port I/O DC Electrical Characteristics ..................................................... 35 Table 7.4. Reset Electrical Characteristics .............................................................. 36 Table 7.5. Flash Electrical Characteristics .............................................................. 37 Table 7.6. EEPROM Electrical Characteristics ........................................................ 37 Table 7.7. Internal High-Frequency Oscillator Electrical Characteristics ................. 38 Table 7.8. Internal Low-Frequency Oscillator Electrical Characteristics ................. 38 Table 7.9. Internal Low-Power Oscillator Electrical Characteristics ........................ 38 Table 7.10. ADC0 Electrical Characteristics ............................................................ 39 Table 7.11. ADC Temperature Sensor Electrical Characteristics ............................ 40 Table 7.12. Precision Temperature Sensor Electrical Characteristics .................... 40 Table 7.13. Voltage Reference Electrical Characteristics ....................................... 41 Table 7.14. Voltage Regulator Electrical Characteristics ........................................ 41 Table 7.15. IDAC Electrical Characteristics ............................................................. 42 Table 7.16. Comparator Electrical Characteristics .................................................. 43 Table 8.1. Example Temperature Values in TS0DATH:TS0DATL .......................... 47 Table 15.1. CIP-51 Instruction Set Summary .......................................................... 84 Table 19.1. SFR Page Stack ................................................................................. 101 Table 19.2. Special Function Register (SFR) Memory Map .................................. 111 Table 19.3. Special Function Registers ................................................................. 112 Table 20.1. Configurable Interrupt Priority Decoding ............................................ 118 Table 20.2. Interrupt Summary .............................................................................. 119 Table 21.1. Flash Security Summary .................................................................... 133 Table 23.1. Example 16-bit CRC Outputs ............................................................. 148 Table 27.1. Port I/O Assignment for Analog Functions ......................................... 175 Table 27.2. Port I/O Assignment for Digital Functions ........................................... 176 Table 27.3. Port I/O Assignment for External Event Trigger Functions ................. 177 Table 28.1. SMBus Clock Source Selection .......................................................... 196 Table 28.2. Minimum SDA Setup and Hold Times ................................................ 197 Table 28.3. Sources for Hardware Changes to SMBnCN ..................................... 204 Table 28.4. Hardware Address Recognition Examples (EHACK = 1) ................... 205 Table 28.5. SMBus Status Decoding: Hardware ACK Disabled (EHACK = 0) ...... 215 Table 28.6. SMBus Status Decoding: Hardware ACK Enabled (EHACK = 1) ...... 217 Table 29.1. Timer Settings for Standard Baud Rates Using The Internal 49 MHz Oscillator ................................................. 227 Table 29.2. Timer Settings for Standard Baud Rates Using an External 22.1184 MHz Oscillator ......................................... 227 Rev. 1.2 11 C8051F39x/37x Table 30.1. SPI Slave Timing Parameters ............................................................ 241 Table 32.1. PCA Timebase Input Options ............................................................. 276 Table 32.2. PCA0CPM and PCA0PWM Bit Settings for PCA Capture/Compare Modules ..................................................................................................... 278 Table 32.3. Watchdog Timer Timeout Intervals1 ................................................... 287 12 Rev. 1.2 C8051F39x/37x SFR Definition 8.1. TS0CN: Temperature Sensor Control ........................................... 48 SFR Definition 8.2. TS0DATH: Temperature Sensor Output High Byte ....................... 49 SFR Definition 8.3. TS0DATL: Temperature Sensor Output Low Byte ........................ 49 SFR Definition 9.1. ADC0CF: ADC0 Configuration ...................................................... 55 SFR Definition 9.2. ADC0H: ADC0 Data Word MSB .................................................... 56 SFR Definition 9.3. ADC0L: ADC0 Data Word LSB ...................................................... 56 SFR Definition 9.4. ADC0CN: ADC0 Control ................................................................ 57 SFR Definition 9.5. ADC0GTH: ADC0 Greater Than Data High Byte .......................... 58 SFR Definition 9.6. ADC0GTL: ADC0 Greater-Than Data Low Byte ............................ 58 SFR Definition 9.7. ADC0LTH: ADC0 Less-Than Data High Byte ................................ 59 SFR Definition 9.8. ADC0LTL: ADC0 Less-Than Data Low Byte ................................. 59 SFR Definition 9.9. AMX0P: AMUX0 Positive Channel Select ..................................... 62 SFR Definition 9.10. AMX0N: AMUX0 Negative Channel Select ................................. 63 SFR Definition 11.1. IDA0CN: IDA0 Control ................................................................. 69 SFR Definition 11.2. IDA0H: IDA0 Data Word MSB ..................................................... 70 SFR Definition 11.3. IDA0L: IDA0 Data Word LSB ....................................................... 70 SFR Definition 11.4. IDA1CN: IDA1 Control ................................................................. 71 SFR Definition 11.5. IDA1H: IDA1 Data Word MSB ..................................................... 72 SFR Definition 11.6. IDA1L: IDA1 Data Word LSB ....................................................... 72 SFR Definition 12.1. REF0CN: Reference Control ....................................................... 74 SFR Definition 13.1. REG0CN: Voltage Regulator Control .......................................... 75 SFR Definition 14.1. CPT0CN: Comparator0 Control ................................................... 78 SFR Definition 14.2. CPT0MD: Comparator0 Mode Selection ..................................... 79 SFR Definition 14.3. CPT0MX: Comparator0 MUX Selection ...................................... 81 SFR Definition 15.1. DPL: Data Pointer Low Byte ........................................................ 88 SFR Definition 15.2. DPH: Data Pointer High Byte ....................................................... 88 SFR Definition 15.3. SP: Stack Pointer ......................................................................... 89 SFR Definition 15.4. ACC: Accumulator ....................................................................... 89 SFR Definition 15.5. B: B Register ................................................................................ 90 SFR Definition 15.6. PSW: Program Status Word ........................................................ 91 SFR Definition 16.1. PFE0CN: Prefetch Engine Control .............................................. 92 SFR Definition 17.1. EMI0CN: External Memory Interface Control .............................. 96 SFR Definition 18.1. DERIVID: Device Derivative ID .................................................... 97 SFR Definition 18.2. REVISION: Device Revision ID ................................................... 98 SFR Definition 18.3. SN3: Serial Number Byte 3 .......................................................... 98 SFR Definition 18.4. SN2: Serial Number Byte 2 .......................................................... 99 SFR Definition 18.5. SN1: Serial Number Byte 1 .......................................................... 99 SFR Definition 18.6. SN0: Serial Number Byte 0 ........................................................ 100 SFR Definition 19.1. SFRPAGE: SFR Page ............................................................... 108 SFR Definition 19.2. SFRPGCN: SFR Page Control .................................................. 109 SFR Definition 19.3. SFRSTACK: SFR Page Stack ................................................... 110 SFR Definition 20.1. IE: Interrupt Enable .................................................................... 120 SFR Definition 20.2. IP: Interrupt Priority .................................................................... 121 SFR Definition 20.3. IPH: Interrupt Priority High ......................................................... 122 SFR Definition 20.4. EIE1: Extended Interrupt Enable 1 ............................................ 123 Rev. 1.2 13 C8051F39x/37x SFR Definition 20.5. EIP1: Extended Interrupt Priority 1 ............................................ 124 SFR Definition 20.6. EIP1H: Extended Interrupt Priority 1 High ................................. 125 SFR Definition 20.7. EIE2: Extended Interrupt Enable 2 ............................................ 126 SFR Definition 20.8. EIP2: Extended Interrupt Priority 2 ............................................ 127 SFR Definition 20.9. EIP2H: Extended Interrupt Priority 2 High ................................. 127 SFR Definition 20.10. IT01CF: INT0/INT1 Configuration ............................................ 129 SFR Definition 21.1. PSCTL: Program Store R/W Control ......................................... 137 SFR Definition 21.2. FLKEY: Flash Lock and Key ...................................................... 138 SFR Definition 21.3. FLSCL: Flash Scale ................................................................... 139 SFR Definition 23.1. CRC0CN: CRC0 Control ........................................................... 150 SFR Definition 23.2. CRC0IN: CRC0 Data Input ........................................................ 151 SFR Definition 23.3. CRC0DAT: CRC0 Data Output .................................................. 151 SFR Definition 23.4. CRC0AUTO: CRC0 Automatic Control ...................................... 152 SFR Definition 23.5. CRC0CNT: CRC0 Automatic Flash Sector Count ..................... 153 SFR Definition 23.6. CRC0FLIP: CRC0 Bit Flip .......................................................... 154 SFR Definition 24.1. VDM0CN: VDD Monitor Control ................................................ 158 SFR Definition 24.2. RSTSRC: Reset Source ............................................................ 160 SFR Definition 25.1. PCON: Power Control ................................................................ 163 SFR Definition 26.1. CLKSEL: Clock Select ............................................................... 165 SFR Definition 26.2. OSCICL: Internal H-F Oscillator Calibration .............................. 166 SFR Definition 26.3. OSCICN: Internal H-F Oscillator Control ................................... 167 SFR Definition 26.4. OSCLCN: Internal L-F Oscillator Control ................................... 168 SFR Definition 26.5. OSCXCN: External Oscillator Control ........................................ 172 SFR Definition 27.1. XBR0: Port I/O Crossbar Register 0 .......................................... 181 SFR Definition 27.2. XBR1: Port I/O Crossbar Register 1 .......................................... 182 SFR Definition 27.3. P0MASK: Port 0 Mask Register ................................................. 183 SFR Definition 27.4. P0MAT: Port 0 Match Register .................................................. 184 SFR Definition 27.5. P1MASK: Port 1 Mask Register ................................................. 184 SFR Definition 27.6. P1MAT: Port 1 Match Register .................................................. 185 SFR Definition 27.7. P0: Port 0 ................................................................................... 186 SFR Definition 27.8. P0MDIN: Port 0 Input Mode ....................................................... 186 SFR Definition 27.9. P0MDOUT: Port 0 Output Mode ................................................ 187 SFR Definition 27.10. P0SKIP: Port 0 Skip ................................................................. 187 SFR Definition 27.11. P1: Port 1 ................................................................................. 188 SFR Definition 27.12. P1MDIN: Port 1 Input Mode ..................................................... 188 SFR Definition 27.13. P1MDOUT: Port 1 Output Mode .............................................. 189 SFR Definition 27.14. P1SKIP: Port 1 Skip ................................................................. 189 SFR Definition 27.15. P2: Port 2 ................................................................................. 190 SFR Definition 27.16. P2MDIN: Port 2 Input Mode ..................................................... 190 SFR Definition 27.17. P2MDOUT: Port 2 Output Mode .............................................. 191 SFR Definition 27.18. P2SKIP: Port 2 Skip ................................................................. 191 SFR Definition 28.1. SMB0CF: SMBus Clock/Configuration ...................................... 198 SFR Definition 28.2. SMB1CF: SMBus Clock/Configuration ...................................... 199 SFR Definition 28.3. SMBTC: SMBus Timing and Pin Control ................................... 200 SFR Definition 28.4. SMB0CN: SMBus Control .......................................................... 202 14 Rev. 1.2 C8051F39x/37x SFR Definition 28.5. SMB1CN: SMBus Control .......................................................... 203 SFR Definition 28.6. SMB0ADR: SMBus0 Slave Address .......................................... 205 SFR Definition 28.7. SMB0ADM: SMBus0 Slave Address Mask ................................ 206 SFR Definition 28.8. SMB1ADR: SMBus1 Slave Address .......................................... 207 SFR Definition 28.9. SMB1ADM: SMBus1 Slave Address Mask ................................ 208 SFR Definition 28.10. SMB0DAT: SMBus Data .......................................................... 209 SFR Definition 28.11. SMB1DAT: SMBus Data .......................................................... 210 SFR Definition 29.1. SCON0: Serial Port 0 Control .................................................... 225 SFR Definition 29.2. SBUF0: Serial (UART0) Port Data Buffer .................................. 226 SFR Definition 30.1. SPI0CFG: SPI0 Configuration ................................................... 235 SFR Definition 30.2. SPI0CN: SPI0 Control ............................................................... 236 SFR Definition 30.3. SPI0CKR: SPI0 Clock Rate ....................................................... 237 SFR Definition 30.4. SPI0DAT: SPI0 Data ................................................................. 238 SFR Definition 31.1. CKCON: Clock Control .............................................................. 243 SFR Definition 31.2. CKCON1: Clock Control 1 ......................................................... 244 SFR Definition 31.3. TCON: Timer Control ................................................................. 249 SFR Definition 31.4. TMOD: Timer Mode ................................................................... 250 SFR Definition 31.5. TL0: Timer 0 Low Byte ............................................................... 251 SFR Definition 31.6. TL1: Timer 1 Low Byte ............................................................... 251 SFR Definition 31.7. TH0: Timer 0 High Byte ............................................................. 252 SFR Definition 31.8. TH1: Timer 1 High Byte ............................................................. 252 SFR Definition 31.9. TMR2CN: Timer 2 Control ......................................................... 256 SFR Definition 31.10. TMR2RLL: Timer 2 Reload Register Low Byte ........................ 257 SFR Definition 31.11. TMR2RLH: Timer 2 Reload Register High Byte ...................... 257 SFR Definition 31.12. TMR2L: Timer 2 Low Byte ....................................................... 257 SFR Definition 31.13. TMR2H Timer 2 High Byte ....................................................... 258 SFR Definition 31.14. TMR3CN: Timer 3 Control ....................................................... 262 SFR Definition 31.15. TMR3RLL: Timer 3 Reload Register Low Byte ........................ 263 SFR Definition 31.16. TMR3RLH: Timer 3 Reload Register High Byte ...................... 263 SFR Definition 31.17. TMR3L: Timer 3 Low Byte ....................................................... 263 SFR Definition 31.18. TMR3H Timer 3 High Byte ....................................................... 264 SFR Definition 31.19. TMR4CN: Timer 4 Control ....................................................... 267 SFR Definition 31.20. TMR4RLL: Timer 4 Reload Register Low Byte ........................ 268 SFR Definition 31.21. TMR4RLH: Timer 4 Reload Register High Byte ...................... 268 SFR Definition 31.22. TMR4L: Timer 4 Low Byte ....................................................... 268 SFR Definition 31.23. TMR4H Timer 4 High Byte ....................................................... 269 SFR Definition 31.24. TMR5CN: Timer 5 Control ....................................................... 272 SFR Definition 31.25. TMR5RLL: Timer 5 Reload Register Low Byte ........................ 273 SFR Definition 31.26. TMR5RLH: Timer 5 Reload Register High Byte ...................... 273 SFR Definition 31.27. TMR5L: Timer 5 Low Byte ....................................................... 273 SFR Definition 31.28. TMR5H Timer 5 High Byte ....................................................... 274 SFR Definition 32.1. PCA0CN: PCA Control .............................................................. 290 SFR Definition 32.2. PCA0MD: PCA Mode ................................................................ 291 SFR Definition 32.3. PCA0PWM: PCA PWM Configuration ....................................... 292 SFR Definition 32.4. PCA0CLR: PCA Comparator Clear Control ............................... 293 Rev. 1.2 15 C8051F39x/37x SFR Definition 32.5. PCA0CPMn: PCA Capture/Compare Mode .............................. 294 SFR Definition 32.6. PCA0L: PCA Counter/Timer Low Byte ...................................... 295 SFR Definition 32.7. PCA0H: PCA Counter/Timer High Byte ..................................... 295 SFR Definition 32.8. PCA0CPLn: PCA Capture Module Low Byte ............................. 296 SFR Definition 32.9. PCA0CPHn: PCA Capture Module High Byte ........................... 296 C2 Register Definition 33.1. C2ADD: C2 Address ...................................................... 297 C2 Register Definition 33.2. DEVICEID: C2 Device ID ............................................... 298 C2 Register Definition 33.3. REVID: C2 Revision ID .................................................. 298 C2 Register Definition 33.4. FPCTL: C2 Flash Programming Control ........................ 299 C2 Register Definition 33.5. FPDAT: C2 Flash Programming Data ............................ 299 16 Rev. 1.2 C8051F39x/37x 1. System Overview C8051F39x/37x devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are listed below. Refer to Section “2. Ordering Information” on page 20 for specific product feature selection and part ordering numbers.  High-speed pipelined 8051-compatible microcontroller core (up to 50 MIPS) In-system, full-speed, non-intrusive debug interface (on-chip) True 10-bit 500 ksps 20 or 16-channel single-ended/differential ADC with analog multiplexer Two 10-bit Current Output DACs Precision temperature sensor with ±2 °C absolute accuracy Precision programmable 49 MHz internal oscillator Low-power, low-frequency oscillator 16 kB of on-chip Flash memory 1024 bytes of on-chip RAM  Co-packaged with 512 bytes of EEPROM memory, accessible via I2C (C8051F37x)         Two SMBus/I2C, UART, and SPI serial interfaces implemented in hardware  Six general-purpose 16-bit timers  Programmable Counter/Timer Array (PCA) with three capture/compare modules and Watchdog Timer function  On-chip Power-On Reset, VDD Monitor, and Temperature Sensor  On-chip Voltage Comparator 21 or 17 Port I/O  Low-power suspend mode with fast wake-up time With on-chip Power-On Reset, VDD monitor, Watchdog Timer, and clock oscillator, the C8051F39x/37x devices are truly stand-alone System-on-a-Chip solutions. The Flash memory can be reprogrammed even in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. User software has complete control of all peripherals, and may individually shut down any or all peripherals for power savings.   The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging without occupying package pins. The C8051F37x devices are specified for 1.8 to 3.6 V operation over the industrial temperature range (–40 to +85 °C), while the C8051F39x devices operate over an extended temperature range (-40 to +105 °C). The C8051F392/3/6/7/8/9 are available in a 20-pin QFN package and the C8051F390/1/4/5 and C8051F37x are available in a 24-pin QFN package. Both package options are lead-free and RoHS compliant. See Section “2. Ordering Information” on page 20 for ordering information. Block diagrams are included in Figure 1.1, Figure 1.2 and Figure 1.3. Rev. 1.2 17 C8051F39x/37x Power On Reset Reset C2CK/RST Port I/O Configuration CIP-51 8051 Controller Core Debug / Programming Hardware UART Timers 0 through 5 256 Byte SRAM 768 Byte XRAM 2xI2C / SMBus SPI Internal LDO Crossbar Control Power Net SFR Bus GND XTAL2 P2.0/C2D IDA0 IDA1 Port 2 Drivers Precision Temperature Sensor SYSCLK A M U X 10-bit 500 ksps ADC External Oscillator Circuit XTAL1 Analog Peripherals 2 x 10-bit IDACs Precision 49 MHz Oscillator Low-Freq. Oscillator Port 1 Drivers P1.0/IDA1 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 Priority Crossbar Decoder PCA/ WDT C2D VDD Port 0 Drivers P0.0/VREF P0.1/IDA0 P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6/CNVSTR P0.7 Digital Peripherals 16/8/4 kB ISP Flash Program Memory C8051F392/6/8 Only System Clock Configuration CP0, CP0A + - Comparator Figure 1.1. C8051F392/3/6/7/8/9 Block Diagram Power On Reset Reset C2CK/RST Port I/O Configuration CIP-51 8051 Controller Core 16/8 kB ISP Flash Program Memory Debug / Programming Hardware UART Timers 0 through 5 256 Byte SRAM 768 Byte XRAM Crossbar Control Power Net SFR Bus GND XTAL1 XTAL2 External Oscillator Circuit IDA0 IDA1 2 x 10-bit IDACs Precision Temperature Sensor SYSCLK A M U X 10-bit 500 ksps ADC C8051F390/4 Only System Clock Configuration CP0, CP0A + - Comparator Figure 1.2. C8051F390/1/4/5 Block Diagram 18 P2.0 P2.1 P2.2 P2.3 P2.4/C2D Analog Peripherals Precision 49 MHz Oscillator Low-Freq. Oscillator Port 2 Drivers 2xI2C / SMBus SPI Internal LDO Port 1 Drivers P1.0 P1.1 P1.2/IDA1 P1.3 P1.4 P1.5 P1.6 P1.7 Priority Crossbar Decoder PCA/ WDT C2D VDD Port 0 Drivers P0.0/VREF P0.1/IDA0 P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6/CNVSTR P0.7 Digital Peripherals Rev. 1.2 C8051F39x/37x Power On Reset Reset C2CK/RST Port I/O Configuration CIP-51 8051 Controller Core 16 kB ISP Flash Program Memory Debug / Programming Hardware UART Timers 0 through 5 256 Byte SRAM 768 Byte XRAM EESCL VDD Internal LDO SPI Crossbar Control SFR Bus Low-Freq. Oscillator XTAL1 XTAL2 External Oscillator Circuit System Clock Configuration IDA0 IDA1 2 x 10-bit IDACs SYSCLK P2.0 P2.1 P2.2/EESCL P2.3/EESDA P2.4/C2D Analog Peripherals GND Precision 49 MHz Oscillator Port 2 Drivers 2xI2C / SMBus 512 Byte I2C EEPROM Power Net Port 1 Drivers P1.0 P1.1 P1.2/IDA1 P1.3 P1.4 P1.5 P1.6 P1.7 Priority Crossbar Decoder PCA/ WDT C2D EESDA Port 0 Drivers P0.0/VREF P0.1/IDA0 P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6/CNVSTR P0.7 Digital Peripherals Precision Temperature Sensor A M U X 10-bit 500 ksps ADC C8051F370/4 Only CP0, CP0A + - Comparator Figure 1.3. C8051F370/1/4/5 Block Diagram Rev. 1.2 19 C8051F39x/37x 2. Ordering Information The following features are common to all device in this family: 50 MIPS throughput (peak)  1 kB of RAM (256 internal bytes and 768 XRAM bytes)  Calibrated internal 49 MHz oscillator  Internal 80 kHz oscillator        Two SMBus/I2C Enhanced SPI, Enhanced UART Six Timers Three Programmable Counter Array channels Analog Comparator Lead-free / RoHS Compliant Table 2.1 shows the features that differentiate the devices in this family. Table 2.1. Product Selection Guide Ordering Part Number Flash EEPROM Digital 10-bit 10-bit On-Chip Precision Package Memory (Bytes) Port I/Os ADC DAC Voltage Temperature 4x4 mm (Bytes) Channels Channels Reference Sensor C8051F390-A-GM 16k — 21 20 2 Y Y QFN-24 C8051F391-A-GM 16k — 21 — — — — QFN-24 C8051F392-A-GM 16k — 17 16 2 Y Y QFN-20 C8051F393-A-GM 16k — 17 — — — — QFN-20 C8051F394-A-GM 8k — 21 20 2 Y Y QFN-24 C8051F395-A-GM 8k — 21 — — — — QFN-24 C8051F396-A-GM 8k — 17 16 2 Y Y QFN-20 C8051F397-A-GM 8k — 17 — — — — QFN-20 C8051F398-A-GM 4k — 17 16 2 Y Y QFN-20 C8051F399-A-GM 4k — 17 — — — — QFN-20 C8051F370-A-GM1 16k 512 21 20 2 Y Y QFN-24 C8051F371-A-GM1 16k 512 21 — — — — QFN-24 C8051F374-A-GM1 8k 512 21 20 2 Y Y QFN-24 C8051F375-A-GM1 8k 512 21 — — — — QFN-24 Notes: 1. These devices are not recommended for new designs. 20 Rev. 1.2 C8051F39x/37x 3. C8051F33x Compatibility The C8051F39x/37x family is designed to be a pin and code compatible replacement for the C8051F33x device family, with an enhanced feature set. The C8051F39x/37x device should function as a drop-in replacement for the C8051F33x devices in most applications. Table 3.1 lists recommended replacement part numbers for C8051F33x devices. See “3.1. Hardware Incompatibilities” to determine if any changes are necessary when upgrading an existing C8051F33x design to the C8051F39x/37x. Table 3.1. C8051F33x Replacement Part Numbers C8051F33x Part Number C8051F39x/37x Part Number C8051F330-GM C8051F396-A-GM C8051F331-GM C8051F397-A-GM C8051F332-GM C8051F398-A-GM C8051F333-GM C8051F399-A-GM C8051F334-GM C8051F398-A-GM C8051F335-GM C8051F399-A-GM C8051F336-GM C8051F392-A-GM C8051F337-GM C8051F393-A-GM C8051F338-GM C8051F390-A-GM C8051F339-GM C8051F391-A-GM 3.1. Hardware Incompatibilities While the C8051F39x/37x family includes a number of new features not found on the C8051F33x family, there are some differences that should be considered for any design port. Internal High-Frequency Oscillator: The undivided high-frequency oscillator on the C8051F39x/37x is 49 MHz, whereas the undivided high-frequency oscillator on the C8051F33x is 24.5 MHz. Correspondingly, the internal high frequency divide ratios (IFCN) have doubled. Thus, firmware written for the C8051F33x where the CLKSL[1:0] = 00b will result in the same SYSCLK frequency on the C8051F39x/37x.  Fabrication Technology: The C8051F39x/37x is manufactured using a different technology process than the C8051F33x. As a result, many of the electrical performance parameters will have subtle differences. These differences should not affect most systems but it is nonetheless important to review the electrical parameters for any blocks that are used in the design, and ensure they are compatible with the existing hardware.  5 V Tolerance: The port I/O pins on the C8501F39x/37x are not 5 V tolerant, whereas the port I/O pins on the C8051F33x are 5 V tolerant.  Lock Byte Address: The lock byte for C8051F39x/7x devices with 16 kB of Flash resides at address 0x3FFF, whereas the lock byte for C8051F33x devices with 16 kB of Flash resides at address 0x3DFF. The lock byte for C8051F39x/7x devices with 8 kB of Flash resides at address 0x1FFF, whereas the lock byte for C8051F33x devices with 8 kB of Flash resides at address 0x1DFF.  Rev. 1.2 21 C8051F39x/37x 4. Pin Definitions Table 4.1. Pin Definitions for the C8051F39x/37x Name Pin ‘F392/3/6/ 7/8/9 Pin ’F390/1/ 4/5 Pin ’F370/1/ 4/5 VDD 3 4 4 Power Supply Voltage. GND 2 3 3 Ground. This ground connection is required. The center pad may optionally be connected to ground also. RST/ 4 5 5 C2CK C2D 5 6 6 P0.0/ 1 2 2 VREF P0.1 20 1 1 19 24 24 Device Reset. Open-drain output of internal POR or VDD monitor. An external source can initiate a system reset by driving this pin low for at least 10 µs. D I/O Clock signal for the C2 Debug Interface. D I/O Bi-directional data signal for the C2 Debug Interface. Shared with P2.0 on 20-pin packaging and P2.4 on 24-pin packaging. D I/O or Port 0.0. A In External VREF input. D I/O or Port 0.1. A In 18 23 23 IDA0 Output. D I/O or Port 0.2. A In A In XTAL2 22 D I/O A Out XTAL1 P0.3/ Description A In IDA0 P0.2/ Type External Clock Input. This pin is the external oscillator return for a crystal or resonator. D I/O or Port 0.3. A In A I/O or External Clock Output. For an external crystal or resonator, this pin is the excitation driver. This D In pin is the external clock input for CMOS, capacitor, or RC oscillator configurations. P0.4 17 22 22 D I/O or Port 0.4. A In P0.5 16 21 21 D I/O or Port 0.5. A In Rev. 1.2 C8051F39x/37x Table 4.1. Pin Definitions for the C8051F39x/37x (Continued) Name Pin ‘F392/3/6/ 7/8/9 Pin ’F390/1/ 4/5 Pin ’F370/1/ 4/5 P0.6/ 15 20 20 CNVSTR Type Description D I/O or Port 0.6. A In D In ADC0 External Convert Start or IDA0 Update Source Input. P0.7 14 19 19 D I/O or Port 0.7. A In P1.0 13 — — D I/O or Port 1.0. A In IDA1 A Out P1.0 IDA1 Output. 18 18 D I/O or Port 1.0. A In P1.1 12 17 17 D I/O or Port 1.1. A In P1.2 - 16 16 D I/O or Port 1.2. A In IDA1 A Out IDA1 Output. P1.2 11 — — D I/O or Port 1.2. A In P1.3 10 15 15 D I/O or Port 1.3. A In P1.4 9 14 14 D I/O or Port 1.4. A In P1.5 8 13 13 D I/O or Port 1.5. A In P1.6 7 12 12 D I/O or Port 1.6. A In P1.7 6 11 11 D I/O or Port 1.7. A In P2.0 5 10 10 D I/O or Port 2.0. (Also C2D on 20-pin Packaging) A In P2.1 — 9 9 D I/O or Port 2.1. A In Rev. 1.2 23 C8051F39x/37x Table 4.1. Pin Definitions for the C8051F39x/37x (Continued) Name Pin ‘F392/3/6/ 7/8/9 Pin ’F390/1/ 4/5 Pin ’F370/1/ 4/5 P2.2 — 8 — D I/O or Port 2.2. A In P2.2 - — 8 D I/O or Port 2.2. A In EESCL D I/O Description EEPROM SCL Connection. P2.3 — 7 — D I/O or Port 2.3. A In P2.3 - — 7 D I/O or Port 2.3. A In EESDA P2.4 24 Type — 6 6 D I/O EEPROM SDA Connection. D I/O Port 2.4. (Also C2D on 24-pin Packaging) Rev. 1.2 P0.1 P0.2 P0.3 P0.4 P0.5 20 19 18 17 16 C8051F39x/37x P0.0 1 15 P0.6 GND 2 14 P0.7 VDD 3 13 P1.0 /RST/C2CK 4 12 P1.1 P2.0/C2D 5 11 P1.2 QFN-20 Top View 8 9 10 P1.4 P1.3 7 P1.6 P1.5 6 P1.7 GND (optional) Figure 4.1. C8051F392/3/6/7/8/9 QFN-20 Pinout Diagram (Top View) Rev. 1.2 25 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 24 23 22 21 20 19 C8051F39x/37x P0.1 1 18 P1.0 P0.0 2 17 P1.1 GND 3 16 P1.2 VDD 4 15 P1.3 /RST/C2CK 5 14 P1.4 P2.4/C2D 6 13 P1.5 QFN-24 Top View 9 10 11 12 P2.0 P1.7 P1.6 8 P2.2 P2.1 7 P2.3 GND (optional) Figure 4.2. C8051F390/1/4/5 Pinout Diagram (Top View) 26 Rev. 1.2 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 24 23 22 21 20 19 C8051F39x/37x P0.1 1 18 P1.0 P0.0 2 17 P1.1 GND 3 16 P1.2 VDD 4 15 P1.3 /RST/C2CK 5 14 P1.4 13 P1.5 QFN-24 Top View GND (optional) 7 8 9 10 11 12 P2.2/EESCL P2.1 P2.0 P1.7 P1.6 6 P2.3/EESDA P2.4/C2D Figure 4.3. C8051F370/1/4/5 Pinout Diagram (Top View) Rev. 1.2 27 C8051F39x/37x 5. QFN-20 Package Specifications Figure 5.1. QFN-20 Package Drawing Table 5.1. QFN-20 Package Dimensions Dimension Min Typ Max Dimension Min Typ Max A A1 b D D2 e E E2 0.80 0.00 0.20 0.85 0.035 0.25 4.00 BSC. 2.10 0.50 BSC. 4.00 BSC. 2.10 0.90 0.05 0.30 L aaa bbb ccc ddd eee ggg 0.50 — — — — — 0.55 — — — — — 0.60 0.10 0.10 0.08 0.10 0.10 0.05 2.00 2.00 2.20 2.20 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-220, variation VGGD except for custom features D2, E2, Z, Y, and L which are toleranced per supplier designation. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. 28 Rev. 1.2 C8051F39x/37x Figure 5.2. QFN-20 Recommended PCB Land Pattern Table 5.2. QFN-20 PCB Land Pattern Dimensions Dimension Max Dimension Max C1 C2 E X1 3.80 3.80 0.50 0.30 X2 Y1 Y2 2.20 1.00 2.20 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. Solder Mask Design 4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 6. The stencil thickness should be 0.125 mm (5 mils). 7. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins. 8. A 2x2 array of 0.95mm openings on a 1.1 mm pitch should be used for the center pad to assure the proper paste volume (71% Paste Coverage). Card Assembly 9. A No-Clean, Type-3 solder paste is recommended. 10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. Rev. 1.2 29 C8051F39x/37x 6. QFN-24 Package Specifications Figure 6.1. QFN-24 Package Drawing Table 6.1. QFN-24 Package Dimensions Dimension Min Typ Max Dimension Min Typ Max A A1 b D D2 e E E2 0.70 0.00 0.18 0.75 0.02 0.25 4.00 BSC. 2.70 0.50 BSC. 4.00 BSC. 2.70 0.80 0.05 0.30 L L1 aaa bbb ddd eee Z Y 0.30 0.00 — — — — — — 0.40 — — — — — 0.24 0.18 0.50 0.15 0.15 0.10 0.05 0.08 — — 2.55 2.55 2.80 2.80 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC Solid State Outline MO-220, variation WGGD except for custom features D2, E2, Z, Y, and L which are toleranced per supplier designation. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. 30 Rev. 1.2 C8051F39x/37x Figure 6.2. QFN-24 Recommended PCB Land Pattern Table 6.2. QFN-24 PCB Land Pattern Dimensions Dimension Min Max Dimension Min Max C1 C2 E X1 3.90 3.90 4.00 4.00 X2 Y1 Y2 2.70 0.65 2.70 2.80 0.75 2.80 0.50 BSC 0.20 0.30 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. Solder Mask Design 3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. The stencil thickness should be 0.125 mm (5 mils). 6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 7. A 2 x 2 array of 1.10 mm x 1.10 mm openings on a 1.30 mm pitch should be used for the center pad. Card Assembly 8. A No-Clean, Type-3 solder paste is recommended. 9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. Rev. 1.2 31 C8051F39x/37x 7. Electrical Characteristics 7.1. Absolute Maximum Specifications Table 7.1. Absolute Maximum Ratings Parameter Test Condition Min Typ Max Unit Ambient Temperature under Bias –55 — 125 °C Storage Temperature –65 — 150 °C Voltage on any Port I/O Pin or RST with respect to GND –0.3 — VDD + 0.3 V Voltage on VDD with Respect to GND –0.3 — 4.2 V Maximum Total Current through VDD or GND — — 100 mA Maximum Output Current Sunk by RST or any Port Pin — — 100 mA Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 32 Rev. 1.2 C8051F39x/37x 7.2. Electrical Characteristics Table 7.2. Global Electrical Characteristics –40 to +105 °C (C8051F39x), –40 to +85 °C (C8051F37x), 50 MHz system clock, unless otherwise specified. Parameter Typ Max Unit 3.0 3.6 V 1.8 3.0 3.6 V Digital Supply RAM Data Retention Voltage — 1.5 — V SYSCLK (System Clock) 2 0 — 50 MHz TSYSH (SYSCLK High Time) 9.5 — — ns TSYSL (SYSCLK Low Time) 9.5 — — ns C8051F39x –40 — +105 °C C8051F37x –40 — +85 °C Supply Voltage (VDD) Test Condition Normal Operation Writing or Erasing Flash Memory Specified Operating Temperature Range Min VRST 1 Digital Supply Current—CPU Active (Normal Mode, Fetching Instructions from Flash) IDD 3, 4 VDD = 3.6 V, F = 50 MHz — 7.1 7.8 mA VDD = 3.0 V, F = 50 MHz — 7.0 7.7 mA VDD = 3.6 V, F = 25 MHz — 4.6 5.2 mA VDD = 3.0 V, F = 25 MHz — 4.5 5.1 mA VDD = 3.6 V, F = 1 MHz — 0.35 — mA VDD = 3.0 V, F = 1 MHz — 0.35 — mA VDD = 3.0 V, F = 80 kHz — 0.25 — mA Notes: 1. Given in Table 7.4 on page 36. 2. SYSCLK must be at least 32 kHz to enable debugging. 3. Based on device characterization data; Not production tested. 4. Digital Supply Current depends on the particular code being executed. The values in this table are obtained with the CPU executing an “sjmp $” loop, which is the compiled form of a while(1) loop in C. One iteration requires 3 CPU clock cycles, and the Flash memory is read on each cycle. The supply current will vary slightly based on the physical location of the sjmp instruction and the number of Flash address lines that toggle as a result. In the worst case, current can increase by up to 30% if the sjmp loop straddles a 64-byte Flash address boundary (e.g., 0x007F to 0x0080). Real-world code with larger loops and longer linear sequences will have few transitions across the 64-byte boundary. Rev. 1.2 33 C8051F39x/37x Table 7.2. Global Electrical Characteristics (Continued) –40 to +105 °C (C8051F39x), –40 to +85 °C (C8051F37x), 50 MHz system clock, unless otherwise specified. Parameter Test Condition Min Typ Max Unit Digital Supply Current—CPU Inactive (Idle Mode, Not Fetching Instructions from Flash) IDD 3 VDD = 3.6 V, F = 50 MHz — 3.9 4.5 mA VDD = 3.0 V, F = 50 MHz — 3.8 4.4 mA VDD = 3.6 V, F = 25 MHz — 2.1 2.5 mA VDD = 3.0 V, F = 25 MHz — 2.0 2.4 mA VDD = 3.6 V, F = 1 MHz — 0.15 — mA VDD = 3.0 V, F = 1 MHz — 0.15 — mA VDD = 3.0 V, F = 80 kHz — 0.1 — mA Digital Supply Current (Suspend Mode) Oscillator not running, VDD Monitor Disabled, Regulator running (STOPCF = 0) — 73 — µA Digital Supply Current (Stop Mode) Oscillator not running, VDD Monitor Disabled, Regulator running (STOPCF = 0) — 75 — µA Digital Supply Current (Stop Mode, Regulator Shutdown) Oscillator not running, VDD Monitor Disabled, Regulator Shutdown (STOPCF = 1) — 0.2 — µA Notes: 1. Given in Table 7.4 on page 36. 2. SYSCLK must be at least 32 kHz to enable debugging. 3. Based on device characterization data; Not production tested. 4. Digital Supply Current depends on the particular code being executed. The values in this table are obtained with the CPU executing an “sjmp $” loop, which is the compiled form of a while(1) loop in C. One iteration requires 3 CPU clock cycles, and the Flash memory is read on each cycle. The supply current will vary slightly based on the physical location of the sjmp instruction and the number of Flash address lines that toggle as a result. In the worst case, current can increase by up to 30% if the sjmp loop straddles a 64-byte Flash address boundary (e.g., 0x007F to 0x0080). Real-world code with larger loops and longer linear sequences will have few transitions across the 64-byte boundary. 34 Rev. 1.2 C8051F39x/37x Table 7.3. Port I/O DC Electrical Characteristics VDD = 1.8 to 3.6 V, –40 to +105 °C (C8051F39x), –40 to +85 °C (C8051F37x), unless otherwise specified. Parameters Test Condition Min Typ Max Unit VDD – 0.7 — — V IOH = –10 µA, Port I/O push-pull VDD – 0.1 — — V IOH = –10 mA, Port I/O push-pull — VDD – 0.8 — V IOL = 8.5 mA — — 0.6 V IOL = 10 µA — — 0.1 V IOL = 10 mA, 1.8 V ≤ VDD < 2.7 V — 0.8 — V IOL = 25 mA, 2.7 V ≤ VDD ≤ 3.6 V — 1.0 — V 1.8 V ≤ VDD < 2.7 V VDD – 0.4 — — V 2.7 V ≤ VDD ≤ 3.6 V VDD – 0.5 — — V 1.8 V ≤ VDD < 2.7 V — — 0.5 V 2.7 V ≤ VDD ≤ 3.6 V — — 0.6 V Weak Pullup Off — — ±1 µA Weak Pullup On, VIN = 0 V — 20 100 µA Standard Port I/O Output High Voltage IOH = –3 mA, Port I/O push-pull Output Low Voltage Input High Voltage Input Low Voltage Input Leakage Current EESDA and EESCL (C8051F37x Only)* Output Low Voltage (EESDA) IOL = 0.15 mA, VDD = 1.8 V — — 0.2 V Output Low Voltage (EESDA) IOL = 2.1 mA, VDD = 3 V — — 0.4 V Output Leakage Current (EESDA) EEPUE = 0, VDD = 3.6 V, 0 V ≤ VOUT ≤ VDD — — 2 µA Input High Voltage VDD x 0.7 — — V Input Low Voltage — — VDD x 0.3 V — — ±3 µA Input Leakage Current EEPUE = 0, Standby, VDD = 3.6 V, 0 V ≤ VIN ≤ VDD Note: Applicable when interfacing to the C8051F37x EEPROM. Otherwise, standard port I/O characteristics apply. Rev. 1.2 35 C8051F39x/37x Table 7.4. Reset Electrical Characteristics –40 to +105 °C (C8051F39x), –40 to +85 °C (C8051F37x), unless otherwise specified. Parameter RST Output Low Voltage Test Condition IOL = 4 mA, VDD = 1.8 to 3.6 V RST Input Low Voltage Min Typ Max Unit — — 0.6 V — — 0.6 V RST Input Pullup Current RST = 0.0 V — 20 100 µA VDD POR Threshold (VRST) VRST_LOW 1.7 1.75 1.8 V VRST_HIGH 2.4 2.55 2.7 V Missing Clock Detector Timeout Time from last system clock rising edge to reset initiation 80 580 800 µs Reset Time Delay Delay between release of any reset source and code execution at location 0x0000 — — 40 µs Minimum RST Low Time to Generate a System Reset 15 — — µs VDD Monitor Turn-on Time 100 — — µs — 20 50 µA VDD Monitor Supply Current 36 Rev. 1.2 C8051F39x/37x Table 7.5. Flash Electrical Characteristics VDD = 1.8 to 3.6 V, –40 to +105 °C (C8051F39x), –40 to +85 °C (C8051F37x), unless otherwise specified. Parameter Flash Size Test Condition Min Typ Max Unit C8051F390/1/2/3, C8051F370/1 16384 Bytes C8051F394/5/6/7, C8051F374/5 8192 Bytes C8051F398/9 4096 Bytes Endurance 20000 100000 — Erase/Write Erase Cycle Time 23 25 27 ms Write Cycle Time 58 61 64 µs Max Unit Table 7.6. EEPROM Electrical Characteristics VDD = 1.8 to 3.6 V, –40 to +85 °C (C8051F37x), unless otherwise specified. Parameter Test Condition Min EEPROM Size Typ 512 Endurance Bytes 1000000 — — Write Cycles — — 3.5 ms EESCL Clock Frequency — — 400 kHz Supply Current — — 3 µA — — 2 mA — — 3 mA Write Cycle Time 16-byte page VDD = 3.6 V, Write Rev. 1.2 37 C8051F39x/37x Table 7.7. Internal High-Frequency Oscillator Electrical Characteristics VDD = 1.8 to 3.6 V, –40 to +105 °C (C8051F39x), –40 to +85 °C (C8051F37x), using factory-calibrated settings, unless otherwise specified. Parameter Test Condition Min Typ Max Unit Oscillator Frequency C8051F390/1/2/3, C8051F370/1 48 49 50 MHz Oscillator Supply Current (from VDD) C8051F394/5/6/7, C8051F374/5 — 840 880 µA Power Supply Sensitivity C8051F398/9 — 0.12 — %/V — 90 — ppm/°C Temperature Sensitivity Table 7.8. Internal Low-Frequency Oscillator Electrical Characteristics VDD = 1.8 to 3.6 V, –40 to +105 °C (C8051F39x), –40 to +85 °C (C8051F37x), using factory-calibrated settings, unless otherwise specified. Parameter Test Condition Min Typ Max Unit Oscillator Frequency C8051F390/1/2/3, C8051F370/1 75 80 85 kHz Oscillator Supply Current (from VDD) C8051F394/5/6/7, C8051F374/5 — 5.5 12 µA Power Supply Sensitivity C8051F398/9 — 0.05 — %/V — 160 — ppm/°C Temperature Sensitivity Table 7.9. Internal Low-Power Oscillator Electrical Characteristics VDD = 1.8 to 3.6 V, –40 to +105 °C (C8051F39x), –40 to +85 °C (C8051F37x), using factory-calibrated settings, unless otherwise specified. Parameter Test Condition Min Typ Max Unit Oscillator Frequency C8051F390/1/2/3, C8051F370/1 18.5 20 21.5 MHz Power Supply Sensitivity C8051F394/5/6/7, C8051F374/5 — 0.1 — %/V Temperature Sensitivity C8051F398/9 — 60 — ppm/°C 38 Rev. 1.2 C8051F39x/37x Table 7.10. ADC0 Electrical Characteristics VDD = 3.0 V, VREF = 2.40 V (REFSL = 0), –40 to +105 °C (C8051F39x), –40 to +85 °C (C8051F37x), unless otherwise specified. Parameter Test Condition Min Typ Max Unit DC Accuracy Resolution C8051F394/5/6/7, C8051F374/5 Integral Nonlinearity C8051F398/9 10 bits —