C8051F410-GQ

C8051F410/1/2/3 2.0 V, 32/16 kB Flash, smaRTClock, 12-bit ADC Analog Peripherals - 12-Bit ADC • • • • • - Two 12-Bit Current Mode DACs Two Comparators • • ±1 LSB INL; no missing codes Programmable throughput up to 200 ksps Up to 24 external inputs Data dependent windowed interrupt generator Built-in temperature sensor (±3 °C) Programmable hysteresis and response time Configurable as wake-up or reset source Memory - 2304 bytes internal data RAM (256 + 2048) - 32/16 kB Flash; In-system programmable in 512 byte sectors - 64 bytes battery-backed RAM (smaRTClock) Digital Peripherals - 24 port I/O; push-pull or open-drain, up to 5.25 V tolerance Hardware SMBus™ (I2C™ Compatible), SPI™, and UART serial ports available concurrently Four general purpose 16-bit counter/timers Programmable 16-bit counter/timer array with six capture/compare modules, WDT Hardware smaRTClock operates down to 1 V with 64 bytes battery-backed RAM and backup voltage regulator - POR/Brownout Detector - Voltage Reference—1.5, 2.2 V (programmable) On-Chip Debug - On-chip debug circuitry facilitates full-speed, nonintrusive in-system debug (No emulator required) - Provides breakpoints, single stepping - Inspect/modify memory and registers - Complete development kit Supply Voltage 2.0 to 5.25 V - Built-in LDO regulator: 2.1 or 2.5 V High Speed 8051 µC Core - Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks Up to 50 MIPS throughput with 50 MHz system clock Expanded interrupt handler Clock Sources - Internal oscillators: 24.5 MHz 2% accuracy supports UART operation; clock multiplier up to 50 MHz External oscillator: Crystal, RC, C, or Clock (1 or 2 pin modes) smaRTClock oscillator: 32 kHz Crystal or self-resonant oscillator Can switch between clock sources on-the-fly 32-PIN LQFP or 28-PIN 5x5 QFN Temperature Range: –40 to +85 °C CROSSBAR ANALOG PERIPHERALS A M U X DIGITAL I/O UART SMBus SPI PCA Timer 0 Timer 1 Timer 2 Timer 3 CRC 12-bit 200 ksps ADC + 12-bit IDAC Port 0 12-bit IDAC + - Port 1 TEMP SENSOR V REF VREG - Port 2 VOLTAGE COMPARATORS 24.5 MHz PRECISION INTERNAL OSCILLATOR WITH CLOCK MULTIPLIER LOW FREQUENCY INTERNAL OSCILLATOR HARDWARE smaRTClock HIGH-SPEED CONTROLLER CORE 32/16 kB ISP FLASH FLEXIBLE INTERRUPTS 8051 CPU (50 MIPS) D EBUG CIRCUITRY 2368 B SRAM POR W DT Rev. 1.0 2/07 Copyright © 2007 by Silicon Laboratories C8051F41x C8051F410/1/2/3 NOTES: 2 Rev. 1.0 C8051F410/1/2/3 Table of Contents 1. System Overview.................................................................................................... 19 1.1. CIP-51™ Microcontroller................................................................................... 25 1.1.1. Fully 8051 Compatible Instruction Set...................................................... 25 1.1.2. Improved Throughput ............................................................................... 25 1.1.3. Additional Features .................................................................................. 25 1.2. On-Chip Debug Circuitry................................................................................... 26 1.3. On-Chip Memory............................................................................................... 27 1.4. Operating Modes .............................................................................................. 28 1.5. 12-Bit Analog to Digital Converter..................................................................... 29 1.6. Two 12-bit Current-Mode DACs........................................................................ 29 1.7. Programmable Comparators............................................................................. 30 1.8. Cyclic Redundancy Check Unit......................................................................... 31 1.9. Voltage Regulator ............................................................................................. 31 1.10.Serial Ports ....................................................................................................... 31 1.11.smaRTClock (Real Time Clock) ....................................................................... 32 1.12.Port Input/Output .............................................................................................. 33 1.13.Programmable Counter Array........................................................................... 34 2. Absolute Maximum Ratings .................................................................................. 35 3. Global DC Electrical Characteristics .................................................................... 36 4. Pinout and Package Definitions............................................................................ 41 5. 12-Bit ADC (ADC0).................................................................................................. 51 5.1. Analog Multiplexer ............................................................................................ 51 5.2. Temperature Sensor ......................................................................................... 52 5.3. ADC0 Operation................................................................................................ 52 5.3.1. Starting a Conversion............................................................................... 53 5.3.2. Tracking Modes........................................................................................ 53 5.3.3. Timing....................................................................................................... 54 5.3.4. Burst Mode ............................................................................................... 56 5.3.5. Output Conversion Code.......................................................................... 57 5.3.6. Settling Time Requirements ..................................................................... 58 5.4. Programmable Window Detector ...................................................................... 63 5.4.1. Window Detector In Single-Ended Mode ................................................. 66 6. 12-Bit Current Mode DACs (IDA0 and IDA1) ........................................................ 69 6.1. IDAC Output Scheduling................................................................................... 69 6.1.1. Update Output On-Demand ..................................................................... 69 6.1.2. Update Output Based on Timer Overflow ................................................ 70 6.1.3. Update Output Based on CNVSTR Edge................................................. 70 6.2. IDAC Output Mapping....................................................................................... 70 6.3. IDAC External Pin Connections ........................................................................ 73 7. Voltage Reference .................................................................................................. 77 8. Voltage Regulator (REG0)...................................................................................... 81 9. Comparators ......................................................................................................... 83 Rev. 1.0 3 C8051F410/1/2/3 10. CIP-51 Microcontroller ........................................................................................... 93 10.1.Instruction Set................................................................................................... 94 10.1.1.Instruction and CPU Timing ..................................................................... 94 10.1.2.MOVX Instruction and Program Memory ................................................. 95 10.2.Register Descriptions ....................................................................................... 98 10.3.Power Management Modes............................................................................ 101 10.3.1.Idle Mode ............................................................................................... 102 10.3.2.Stop Mode.............................................................................................. 102 10.3.3.Suspend Mode ....................................................................................... 102 11. Memory Organization and SFRs ......................................................................... 103 11.1.Program Memory............................................................................................ 103 11.2.Data Memory .................................................................................................. 104 11.3.General Purpose Registers ............................................................................ 104 11.4.Bit Addressable Locations .............................................................................. 104 11.5.Stack............................................................................................................... 104 11.6.Special Function Registers............................................................................. 105 12. Interrupt Handler .................................................................................................. 110 12.1.MCU Interrupt Sources and Vectors............................................................... 110 12.2.Interrupt Priorities ........................................................................................... 110 12.3.Interrupt Latency............................................................................................. 110 12.4.Interrupt Register Descriptions ....................................................................... 112 12.5.External Interrupts .......................................................................................... 117 13. Prefetch Engine .................................................................................................... 119 14. Cyclic Redundancy Check Unit (CRC0) ............................................................. 121 14.1.CRC Algorithm................................................................................................ 121 14.2.Preparing for a CRC Calculation .................................................................... 123 14.3.Performing a CRC Calculation ....................................................................... 123 14.4.Accessing the CRC0 Result ........................................................................... 123 14.5.CRC0 Bit Reverse Feature............................................................................. 123 15. Reset Sources....................................................................................................... 127 15.1.Power-On Reset ............................................................................................. 128 15.2.Power-Fail Reset / VDD Monitor .................................................................... 129 15.3.External Reset ................................................................................................ 130 15.4.Missing Clock Detector Reset ........................................................................ 130 15.5.Comparator0 Reset ........................................................................................ 130 15.6.PCA Watchdog Timer Reset .......................................................................... 131 15.7.Flash Error Reset ........................................................................................... 131 15.8.smaRTClock (Real Time Clock) Reset........................................................... 132 15.9.Software Reset ............................................................................................... 132 16. Flash Memory ....................................................................................................... 135 16.1.Programming The Flash Memory ................................................................... 135 16.1.1.Flash Lock and Key Functions ............................................................... 135 16.1.2.Flash Erase Procedure .......................................................................... 135 16.1.3.Flash Write Procedure ........................................................................... 136 16.2.Non-volatile Data Storage .............................................................................. 137 4 Rev. 1.0 C8051F410/1/2/3 16.3.Security Options ............................................................................................. 137 16.4.Flash Write and Erase Guidelines .................................................................. 139 16.4.1.VDD Maintenance and the VDD Monitor ............................................... 139 16.4.2.16.4.2 PSWE Maintenance .................................................................... 140 16.4.3.System Clock ......................................................................................... 140 16.5.Flash Read Timing ......................................................................................... 142 17. External RAM ........................................................................................................ 145 18. Port Input/Output.................................................................................................. 147 18.1.Priority Crossbar Decoder .............................................................................. 149 18.2.Port I/O Initialization ....................................................................................... 151 18.3.General Purpose Port I/O ............................................................................... 154 19. Oscillators ............................................................................................................. 165 19.1.Programmable Internal Oscillator ................................................................... 165 19.1.1.Internal Oscillator Suspend Mode .......................................................... 166 19.2.External Oscillator Drive Circuit...................................................................... 168 19.2.1.Clocking Timers Directly Through the External Oscillator...................... 168 19.2.2.External Crystal Example....................................................................... 168 19.2.3.External RC Example............................................................................. 170 19.2.4.External Capacitor Example................................................................... 170 19.3.Clock Multiplier ............................................................................................... 172 19.4.System Clock Selection.................................................................................. 174 20. smaRTClock (Real Time Clock)........................................................................... 177 20.1.smaRTClock Interface .................................................................................... 178 20.1.1.smaRTClock Lock and Key Functions ................................................... 178 20.1.2.Using RTC0ADR and RTC0DAT to Access smaRTClock Internal Registers.............................................................. 178 20.1.3.smaRTClock Interface Autoread Feature............................................... 178 20.1.4.RTC0ADR Autoincrement Feature......................................................... 179 20.2.smaRTClock Clocking Sources ...................................................................... 182 20.2.1.Using the smaRTClock Oscillator in Crystal Mode ................................ 182 20.2.2.Using the smaRTClock Oscillator in Self-Oscillate Mode ...................... 182 20.2.3.Automatic Gain Control (Crystal Mode Only) ......................................... 183 20.2.4.smaRTClock Bias Doubling ................................................................... 183 20.2.5.smaRTClock Missing Clock Detector..................................................... 183 20.3.smaRTClock Timer and Alarm Function......................................................... 185 20.3.1.Setting and Reading the smaRTClock Timer Value............................... 185 20.3.2.Setting a smaRTClock Alarm ................................................................. 186 20.4.Backup Regulator and RAM ........................................................................... 187 21. SMBus ................................................................................................................... 191 21.1.Supporting Documents ................................................................................... 192 21.2.SMBus Configuration...................................................................................... 192 21.3.SMBus Operation ........................................................................................... 192 21.3.1.Arbitration............................................................................................... 193 21.3.2.Clock Low Extension.............................................................................. 193 21.3.3.SCL Low Timeout................................................................................... 194 Rev. 1.0 5 C8051F410/1/2/3 21.3.4.SCL High (SMBus Free) Timeout .......................................................... 194 21.4.Using the SMBus............................................................................................ 194 21.4.1.SMBus Configuration Register............................................................... 195 21.4.2.SMB0CN Control Register ..................................................................... 198 21.4.3.Data Register ......................................................................................... 201 21.5.SMBus Transfer Modes.................................................................................. 201 21.5.1.Master Transmitter Mode ....................................................................... 201 21.5.2.Master Receiver Mode ........................................................................... 202 21.5.3.Slave Receiver Mode ............................................................................. 203 21.5.4.Slave Transmitter Mode ......................................................................... 204 21.6.SMBus Status Decoding................................................................................. 204 22. UART0.................................................................................................................... 207 22.1.Enhanced Baud Rate Generation................................................................... 208 22.2.Operational Modes ......................................................................................... 209 22.2.1.8-Bit UART ............................................................................................. 209 22.2.2.9-Bit UART ............................................................................................. 210 22.3.Multiprocessor Communications .................................................................... 210 23. Enhanced Serial Peripheral Interface (SPI0)...................................................... 217 23.1.Signal Descriptions......................................................................................... 218 23.1.1.Master Out, Slave In (MOSI).................................................................. 218 23.1.2.Master In, Slave Out (MISO).................................................................. 218 23.1.3.Serial Clock (SCK) ................................................................................. 218 23.1.4.Slave Select (NSS) ................................................................................ 218 23.2.SPI0 Master Mode Operation ......................................................................... 219 23.3.SPI0 Slave Mode Operation ........................................................................... 220 23.4.SPI0 Interrupt Sources ................................................................................... 221 23.5.Serial Clock Timing......................................................................................... 221 23.6.SPI Special Function Registers ...................................................................... 222 24. Timers.................................................................................................................... 231 24.1.Timer 0 and Timer 1 ....................................................................................... 231 24.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 231 24.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 233 24.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 233 24.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 234 24.2.Timer 2 .......................................................................................................... 239 24.2.1.16-bit Timer with Auto-Reload................................................................ 239 24.2.2.8-bit Timers with Auto-Reload................................................................ 240 24.2.3.External/smaRTClock Capture Mode..................................................... 241 24.3.Timer 3 .......................................................................................................... 244 24.3.1.16-bit Timer with Auto-Reload................................................................ 244 24.3.2.8-bit Timers with Auto-Reload................................................................ 245 24.3.3.External/smaRTClock Capture Mode..................................................... 246 25. Programmable Counter Array (PCA0) ................................................................ 249 25.1.PCA Counter/Timer ........................................................................................ 250 25.2.Capture/Compare Modules ............................................................................ 251 6 Rev. 1.0 C8051F410/1/2/3 25.2.1.Edge-triggered Capture Mode................................................................ 252 25.2.2.Software Timer (Compare) Mode........................................................... 253 25.2.3.High Speed Output Mode....................................................................... 254 25.2.4.Frequency Output Mode ........................................................................ 255 25.2.5.8-Bit Pulse Width Modulator Mode......................................................... 256 25.2.6.16-Bit Pulse Width Modulator Mode....................................................... 257 25.3.Watchdog Timer Mode ................................................................................... 257 25.3.1.Watchdog Timer Operation .................................................................... 258 25.3.2.Watchdog Timer Usage ......................................................................... 259 25.4.Register Descriptions for PCA........................................................................ 261 26. C2 Interface ........................................................................................................... 265 26.1.C2 Interface Registers.................................................................................... 265 26.2.C2 Pin Sharing ............................................................................................... 267 Document Change List............................................................................................. 268 Contact Information.................................................................................................. 270 Rev. 1.0 7 C8051F410/1/2/3 NOTES: 8 Rev. 1.0 C8051F410/1/2/3 List of Figures 1. System Overview Figure 1.1. C8051F410 Block Diagram .................................................................... 21 Figure 1.2. C8051F411 Block Diagram .................................................................... 22 Figure 1.3. C8051F412 Block Diagram .................................................................... 23 Figure 1.4. C8051F413 Block Diagram .................................................................... 24 Figure 1.5. Development/In-System Debug Diagram............................................... 26 Figure 1.6. Memory Map .......................................................................................... 27 Figure 1.7. 12-Bit ADC Block Diagram..................................................................... 29 Figure 1.8. IDAC Block Diagram .............................................................................. 30 Figure 1.9. Comparators Block Diagram .................................................................. 31 Figure 1.10. smaRTClock Block Diagram ................................................................ 32 Figure 1.11. Port I/O Functional Block Diagram ....................................................... 33 Figure 1.12. PCA Block Diagram.............................................................................. 34 2. Absolute Maximum Ratings 3. Global DC Electrical Characteristics 4. Pinout and Package Definitions Figure 4.1. LQFP-32 Pinout Diagram (Top View) .................................................... 44 Figure 4.2. QFN-28 Pinout Diagram (Top View) ...................................................... 45 Figure 4.3. LQFP-32 Package Diagram ................................................................... 46 Figure 4.4. QFN-28 Package Drawing ..................................................................... 47 Figure 4.5. Typical QFN-28 Landing Diagram.......................................................... 48 Figure 4.6. Typical QFN-28 Solder Paste Mask....................................................... 49 5. 12-Bit ADC (ADC0) Figure 5.1. ADC0 Functional Block Diagram............................................................ 51 Figure 5.2. Typical Temperature Sensor Transfer Function..................................... 52 Figure 5.3. ADC0 Tracking Modes ........................................................................... 54 Figure 5.4. 12-Bit ADC Tracking Mode Example ..................................................... 55 Figure 5.5. 12-Bit ADC Burst Mode Example with Repeat Count Set to 4............... 56 Figure 5.6. ADC0 Equivalent Input Circuits.............................................................. 58 Figure 5.7. ADC Window Compare Example: Right-Justified Single-Ended Data ... 66 Figure 5.8. ADC Window Compare Example: Left-Justified Single-Ended Data ..... 66 6. 12-Bit Current Mode DACs (IDA0 and IDA1) Figure 6.1. IDAC Functional Block Diagram............................................................. 69 Figure 6.2. IDAC Data Word Mapping...................................................................... 70 Figure 6.3. IDAC Pin Connections ........................................................................... 74 7. Voltage Reference Figure 7.1. Voltage Reference Functional Block Diagram ....................................... 77 8. Voltage Regulator (REG0) Figure 8.1. External Capacitors for Voltage Regulator Input/Output ........................ 81 Figure 8.2. External Capacitors for Voltage Regulator Input/Output ........................ 81 9. Comparators Figure 9.1. Comparator0 Functional Block Diagram ................................................ 83 Figure 9.2. Comparator1 Functional Block Diagram ................................................ 84 Rev. 1.0 9 C8051F410/1/2/3 Figure 9.3. Comparator Hysteresis Plot ................................................................... 85 10. CIP-51 Microcontroller Figure 10.1. CIP-51 Block Diagram.......................................................................... 93 11. Memory Organization and SFRs Figure 11.1. Memory Map ...................................................................................... 103 12. Interrupt Handler 13. Prefetch Engine 14. Cyclic Redundancy Check Unit (CRC0) Figure 14.1. CRC0 Block Diagram ......................................................................... 121 Figure 14.2. Bit Reverse Register .......................................................................... 123 15. Reset Sources Figure 15.1. Reset Sources.................................................................................... 127 Figure 15.2. Power-On and VDD Monitor Reset Timing ........................................ 128 16. Flash Memory Figure 16.1. Flash Program Memory Map.............................................................. 137 17. External RAM 18. Port Input/Output Figure 18.1. Port I/O Functional Block Diagram ..................................................... 147 Figure 18.2. Port I/O Cell Block Diagram ............................................................... 148 Figure 18.3. Crossbar Priority Decoder with No Pins Skipped ............................... 149 Figure 18.4. Crossbar Priority Decoder with Crystal Pins Skipped ........................ 150 Figure 18.5. Port 0 Input Overdrive Current Range................................................ 152 19. Oscillators Figure 19.1. Oscillator Diagram.............................................................................. 165 Figure 19.2. 32.768 kHz External Crystal Example................................................ 169 Figure 19.3. Example Clock Multiplier Output ........................................................ 172 20. smaRTClock (Real Time Clock) Figure 20.1. smaRTClock Block Diagram .............................................................. 177 21. SMBus Figure 21.1. SMBus Block Diagram ....................................................................... 191 Figure 21.2. Typical SMBus Configuration ............................................................. 192 Figure 21.3. SMBus Transaction ............................................................................ 193 Figure 21.4. Typical SMBus SCL Generation......................................................... 196 Figure 21.5. Typical Master Transmitter Sequence................................................ 202 Figure 21.6. Typical Master Receiver Sequence.................................................... 202 Figure 21.7. Typical Slave Receiver Sequence...................................................... 203 Figure 21.8. Typical Slave Transmitter Sequence.................................................. 204 22. UART0 Figure 22.1. UART0 Block Diagram ....................................................................... 207 Figure 22.2. UART0 Baud Rate Logic .................................................................... 208 Figure 22.3. UART Interconnect Diagram .............................................................. 209 Figure 22.4. 8-Bit UART Timing Diagram............................................................... 209 Figure 22.5. 9-Bit UART Timing Diagram............................................................... 210 Figure 22.6. UART Multi-Processor Mode Interconnect Diagram .......................... 211 10 Rev. 1.0 C8051F410/1/2/3 23. Enhanced Serial Peripheral Interface (SPI0) Figure 23.1. SPI Block Diagram ............................................................................. 217 Figure 23.2. Multiple-Master Mode Connection Diagram ....................................... 220 Figure 23.3. 3-Wire Single Master and Slave Mode Connection Diagram ............. 220 Figure 23.4. 4-Wire Single Master and Slave Mode Connection Diagram ............. 220 Figure 23.5. Data/Clock Timing Relationship ......................................................... 222 Figure 23.6. SPI Master Timing (CKPHA = 0)........................................................ 227 Figure 23.7. SPI Master Timing (CKPHA = 1)........................................................ 227 Figure 23.8. SPI Slave Timing (CKPHA = 0).......................................................... 228 Figure 23.9. SPI Slave Timing (CKPHA = 1).......................................................... 228 24. Timers Figure 24.1. T0 Mode 0 Block Diagram.................................................................. 232 Figure 24.2. T0 Mode 2 Block Diagram.................................................................. 233 Figure 24.3. T0 Mode 3 Block Diagram.................................................................. 234 Figure 24.4. Timer 2 16-Bit Mode Block Diagram .................................................. 239 Figure 24.5. Timer 2 8-Bit Mode Block Diagram .................................................... 240 Figure 24.6. Timer 2 Capture Mode Block Diagram ............................................... 241 Figure 24.7. Timer 3 16-Bit Mode Block Diagram .................................................. 244 Figure 24.8. Timer 3 8-Bit Mode Block Diagram .................................................... 245 Figure 24.9. Timer 3 Capture Mode Block Diagram ............................................... 246 25. Programmable Counter Array (PCA0) Figure 25.1. PCA Block Diagram............................................................................ 249 Figure 25.2. PCA Counter/Timer Block Diagram.................................................... 250 Figure 25.3. PCA Interrupt Block Diagram ............................................................. 251 Figure 25.4. PCA Capture Mode Diagram.............................................................. 252 Figure 25.5. PCA Software Timer Mode Diagram .................................................. 253 Figure 25.6. PCA High-Speed Output Mode Diagram............................................ 254 Figure 25.7. PCA Frequency Output Mode ............................................................ 255 Figure 25.8. PCA 8-Bit PWM Mode Diagram ......................................................... 256 Figure 25.9. PCA 16-Bit PWM Mode...................................................................... 257 Figure 25.10. PCA Module 5 with Watchdog Timer Enabled ................................. 258 26. C2 Interface Figure 26.1. Typical C2 Pin Sharing....................................................................... 267 Rev. 1.0 11 C8051F410/1/2/3 NOTES: 12 Rev. 1.0 C8051F410/1/2/3 List of Tables 1. System Overview Table 1.1. Product Selection Guide ......................................................................... 20 Table 1.2. Operating Modes Summary .................................................................... 28 2. Absolute Maximum Ratings Table 2.1.Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3. Global DC Electrical Characteristics Table 3.1.Global DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 3.2. Index to Electrical Characteristics Tables ............................................... 39 4. Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F41x .......................................................... 41 Table 4.2. LQFP-32 Package Dimensions .............................................................. 46 Table 4.3. QFN-28 Package Dimensions ................................................................ 47 5. 12-Bit ADC (ADC0) Table 5.1. ADC0 Examples of Right- and Left-Justified Samples ........................... 57 Table 5.2. ADC0 Repeat Count Examples at Various Input Voltages ..................... 57 Table 5.3.ADC0 Electrical Characteristics (VDD = 2.5 V, VREF = 2.2 V) . . . . . . . . 67 Table 5.4.ADC0 Electrical Characteristics (VDD = 2.1 V, VREF = 1.5 V) . . . . . . . . 68 6. 12-Bit Current Mode DACs (IDA0 and IDA1) Table 6.1.IDAC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7. Voltage Reference Table 7.1.Voltage Reference Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 79 8. Voltage Regulator (REG0) Table 8.1.Voltage Regulator Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . 82 9. Comparators Table 9.1.Comparator Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 92 10. CIP-51 Microcontroller Table 10.1. CIP-51 Instruction Set Summary .......................................................... 95 11. Memory Organization and SFRs Table 11.1. Special Function Register (SFR) Memory Map .................................. 105 Table 11.2. Special Function Registers ................................................................. 106 12. Interrupt Handler Table 12.1. Interrupt Summary .............................................................................. 111 13. Prefetch Engine 14. Cyclic Redundancy Check Unit (CRC0) Table 14.1. Example 16-bit CRC Outputs ............................................................. 122 15. Reset Sources Table 15.1.Reset Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 16. Flash Memory Table 16.1. Flash Security Summary .................................................................... 138 Table 16.2.Flash Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 17. External RAM Rev. 1.0 13 C8051F410/1/2/3 18. Port Input/Output Table 18.1.Port I/O DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 163 19. Oscillators Table 19.1.Oscillator Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 175 20. smaRTClock (Real Time Clock) Table 20.1. smaRTClock Internal Registers .......................................................... 179 21. SMBus Table 21.1. SMBus Clock Source Selection .......................................................... 195 Table 21.2. Minimum SDA Setup and Hold Times ................................................ 196 Table 21.3. Sources for Hardware Changes to SMB0CN ..................................... 200 Table 21.4. SMBus Status Decoding ..................................................................... 205 22. UART0 Table 22.1. Timer Settings for Standard Baud Rates Using the Internal Oscillator ............................................................... 214 Table 22.2. Timer Settings for Standard Baud Rates Using an External 25.0 MHz Oscillator ............................................... 214 Table 22.3. Timer Settings for Standard Baud Rates Using an External 22.1184 MHz Oscillator ......................................... 215 Table 22.4. Timer Settings for Standard Baud Rates Using an External 18.432 MHz Oscillator ........................................... 215 Table 22.5. Timer Settings for Standard Baud Rates Using an External 11.0592 MHz Oscillator ......................................... 216 Table 22.6. Timer Settings for Standard Baud Rates Using an External 3.6864 MHz Oscillator ........................................... 216 23. Enhanced Serial Peripheral Interface (SPI0) Table 23.1.SPI Slave Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 24. Timers 25. Programmable Counter Array (PCA0) Table 25.1. PCA Timebase Input Options ............................................................. 250 Table 25.2. PCA0CPM Register Settings for PCA Capture/Compare Modules .... 251 Table 25.3. Watchdog Timer Timeout Intervals ..................................................... 260 26. C2 Interface 14 Rev. 1.0 C8051F410/1/2/3 List of Registers SFR Definition 5.1. ADC0MX: ADC0 Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . 59 SFR Definition 5.2. ADC0CF: ADC0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 SFR Definition 5.3. ADC0H: ADC0 Data Word MSB . . . . . . . . . . . . . . . . . . . . . . . . . . 61 SFR Definition 5.4. ADC0L: ADC0 Data Word LSB . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 SFR Definition 5.5. ADC0CN: ADC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 SFR Definition 5.6. ADC0TK: ADC0 Tracking Mode Select . . . . . . . . . . . . . . . . . . . . 63 SFR Definition 5.7. ADC0GTH: ADC0 Greater-Than Data High Byte . . . . . . . . . . . . . 64 SFR Definition 5.8. ADC0GTL: ADC0 Greater-Than Data Low Byte . . . . . . . . . . . . . . 64 SFR Definition 5.9. ADC0LTH: ADC0 Less-Than Data High Byte . . . . . . . . . . . . . . . . 65 SFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte . . . . . . . . . . . . . . . . 65 SFR Definition 6.1. IDA0CN: IDA0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 SFR Definition 6.2. IDA0H: IDA0 Data High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 SFR Definition 6.3. IDA0L: IDA0 Data Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 SFR Definition 6.4. IDA1CN: IDA1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 SFR Definition 6.5. IDA1H: IDA0 Data High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 SFR Definition 6.6. IDA1L: IDA1 Data Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 SFR Definition 7.1. REF0CN: Reference Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 SFR Definition 8.1. REG0CN: Regulator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 SFR Definition 9.1. CPT0CN: Comparator0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 SFR Definition 9.2. CPT0MX: Comparator0 MUX Selection . . . . . . . . . . . . . . . . . . . . 87 SFR Definition 9.3. CPT0MD: Comparator0 Mode Selection . . . . . . . . . . . . . . . . . . . . 88 SFR Definition 9.4. CPT1MX: Comparator1 MUX Selection . . . . . . . . . . . . . . . . . . . . 89 SFR Definition 9.5. CPT1MD: Comparator1 Mode Selection . . . . . . . . . . . . . . . . . . . . 90 SFR Definition 9.6. CPT1CN: Comparator1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 SFR Definition 10.1. SP: Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 SFR Definition 10.2. DPL: Data Pointer Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 SFR Definition 10.3. DPH: Data Pointer High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 SFR Definition 10.4. PSW: Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 SFR Definition 10.5. ACC: Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 SFR Definition 10.6. B: B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 SFR Definition 10.7. PCON: Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 SFR Definition 12.1. IE: Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 SFR Definition 12.2. IP: Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 SFR Definition 12.3. EIE1: Extended Interrupt Enable 1 . . . . . . . . . . . . . . . . . . . . . . 114 SFR Definition 12.4. EIP1: Extended Interrupt Priority 1 . . . . . . . . . . . . . . . . . . . . . . 115 SFR Definition 12.5. EIE2: Extended Interrupt Enable 2 . . . . . . . . . . . . . . . . . . . . . . 116 SFR Definition 12.6. EIP2: Extended Interrupt Priority 2 . . . . . . . . . . . . . . . . . . . . . . 116 SFR Definition 12.7. IT01CF: INT0/INT1 Configuration . . . . . . . . . . . . . . . . . . . . . . . 118 SFR Definition 13.1. PFE0CN: Prefetch Engine Control . . . . . . . . . . . . . . . . . . . . . . 119 SFR Definition 14.1. CRC0CN: CRC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 SFR Definition 14.2. CRC0IN: CRC0 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 SFR Definition 14.3. CRC0DAT: CRC0 Data Output . . . . . . . . . . . . . . . . . . . . . . . . . 125 SFR Definition 14.4. CRC0FLIP: CRC0 Bit Flip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Rev. 1.0 15 C8051F410/1/2/3 SFR Definition 15.1. VDM0CN: VDD Monitor Control . . . . . . . . . . . . . . . . . . . . . . . . 130 SFR Definition 15.2. RSTSRC: Reset Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 SFR Definition 16.1. PSCTL: Program Store R/W Control . . . . . . . . . . . . . . . . . . . . . 141 SFR Definition 16.2. FLKEY: Flash Lock and Key . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 SFR Definition 16.3. FLSCL: Flash Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 SFR Definition 16.4. ONESHOT: Flash Oneshot Period . . . . . . . . . . . . . . . . . . . . . . 143 SFR Definition 17.1. EMI0CN: External Memory Interface Control . . . . . . . . . . . . . . 145 SFR Definition 18.1. XBR0: Port I/O Crossbar Register 0 . . . . . . . . . . . . . . . . . . . . . 153 SFR Definition 18.2. XBR1: Port I/O Crossbar Register 1 . . . . . . . . . . . . . . . . . . . . . 154 SFR Definition 18.3. P0: Port0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 SFR Definition 18.4. P0MDIN: Port0 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 SFR Definition 18.5. P0MDOUT: Port0 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . 156 SFR Definition 18.6. P0SKIP: Port0 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 SFR Definition 18.7. P0MAT: Port0 Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 SFR Definition 18.8. P0MASK: Port0 Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 SFR Definition 18.9. P0ODEN: Port0 Overdrive Mode . . . . . . . . . . . . . . . . . . . . . . . . 157 SFR Definition 18.10. P1: Port1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 SFR Definition 18.11. P1MDIN: Port1 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 SFR Definition 18.12. P1MDOUT: Port1 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 159 SFR Definition 18.13. P1SKIP: Port1 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 SFR Definition 18.14. P1MAT: Port1 Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 SFR Definition 18.15. P1MASK: Port1 Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 SFR Definition 18.16. P2: Port2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 SFR Definition 18.17. P2MDIN: Port2 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 SFR Definition 18.18. P2MDOUT: Port2 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 162 SFR Definition 18.19. P2SKIP: Port2 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 SFR Definition 19.1. OSCICN: Internal Oscillator Control . . . . . . . . . . . . . . . . . . . . . 167 SFR Definition 19.2. OSCICL: Internal Oscillator Calibration . . . . . . . . . . . . . . . . . . . 167 SFR Definition 19.3. OSCXCN: External Oscillator Control . . . . . . . . . . . . . . . . . . . . 171 SFR Definition 19.4. CLKMUL: Clock Multiplier Control . . . . . . . . . . . . . . . . . . . . . . . 173 SFR Definition 19.5. CLKSEL: Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 SFR Definition 20.1. RTC0KEY: smaRTClock Lock and Key . . . . . . . . . . . . . . . . . . . 180 SFR Definition 20.2. RTC0ADR: smaRTClock Address . . . . . . . . . . . . . . . . . . . . . . 181 SFR Definition 20.3. RTC0DAT: smaRTClock Data . . . . . . . . . . . . . . . . . . . . . . . . . 182 Internal Register Definition 20.4. RTC0CN: smaRTClock Control . . . . . . . . . . . . . . . 184 Internal Register Definition 20.5. RTC0XCN: smaRTClock Oscillator Control . . . . . . 185 Internal Register Definition 20.6. CAPTUREn: smaRTClock Timer Capture . . . . . . . 186 Internal Register Definition 20.7. ALARMn: smaRTClock Alarm . . . . . . . . . . . . . . . . 187 Internal Register Definition 20.8. RAMADDR: smaRTClock Backup RAM Address . . 187 Internal Register Definition 20.9. RAMDATA: smaRTClock Backup RAM Data . . . . . 188 SFR Definition 21.1. SMB0CF: SMBus Clock/Configuration . . . . . . . . . . . . . . . . . . . 197 SFR Definition 21.2. SMB0CN: SMBus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 SFR Definition 21.3. SMB0DAT: SMBus Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 SFR Definition 22.1. SCON0: Serial Port 0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 212 SFR Definition 22.2. SBUF0: Serial (UART0) Port Data Buffer . . . . . . . . . . . . . . . . . 213 16 Rev. 1.0 C8051F410/1/2/3 SFR Definition 23.1. SPI0CFG: SPI0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 223 SFR Definition 23.2. SPI0CN: SPI0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 SFR Definition 23.3. SPI0CKR: SPI0 Clock Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 SFR Definition 23.4. SPI0DAT: SPI0 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 SFR Definition 24.1. TCON: Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 SFR Definition 24.2. TMOD: Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 SFR Definition 24.3. CKCON: Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 SFR Definition 24.4. TL0: Timer 0 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 SFR Definition 24.5. TL1: Timer 1 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 SFR Definition 24.6. TH0: Timer 0 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 SFR Definition 24.7. TH1: Timer 1 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 SFR Definition 24.8. TMR2CN: Timer 2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 SFR Definition 24.9. TMR2RLL: Timer 2 Reload Register Low Byte . . . . . . . . . . . . . 243 SFR Definition 24.10. TMR2RLH: Timer 2 Reload Register High Byte . . . . . . . . . . . 243 SFR Definition 24.11. TMR2L: Timer 2 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 SFR Definition 24.12. TMR2H Timer 2 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 SFR Definition 24.13. TMR3CN: Timer 3 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 SFR Definition 24.14. TMR3RLL: Timer 3 Reload Register Low Byte . . . . . . . . . . . . 248 SFR Definition 24.15. TMR3RLH: Timer 3 Reload Register High Byte . . . . . . . . . . . 248 SFR Definition 24.16. TMR3L: Timer 3 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 SFR Definition 24.17. TMR3H Timer 3 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 SFR Definition 25.1. PCA0CN: PCA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 SFR Definition 25.2. PCA0MD: PCA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 SFR Definition 25.3. PCA0CPMn: PCA Capture/Compare Mode . . . . . . . . . . . . . . . 263 SFR Definition 25.4. PCA0L: PCA Counter/Timer Low Byte . . . . . . . . . . . . . . . . . . . 264 SFR Definition 25.5. PCA0H: PCA Counter/Timer High Byte . . . . . . . . . . . . . . . . . . . 264 SFR Definition 25.6. PCA0CPLn: PCA Capture Module Low Byte . . . . . . . . . . . . . . . 264 SFR Definition 25.7. PCA0CPHn: PCA Capture Module High Byte . . . . . . . . . . . . . . 264 C2 Register Definition 26.1. C2ADD: C2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 C2 Register Definition 26.2. DEVICEID: C2 Device ID . . . . . . . . . . . . . . . . . . . . . . . . 265 C2 Register Definition 26.3. REVID: C2 Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . 266 C2 Register Definition 26.4. FPCTL: C2 Flash Programming Control . . . . . . . . . . . . 266 C2 Register Definition 26.5. FPDAT: C2 Flash Programming Data . . . . . . . . . . . . . . 266 Rev. 1.0 17 C8051F410/1/2/3 NOTES: 18 Rev. 1.0 C8051F410/1/2/3 1. System Overview C8051F41x devices are fully integrated, low power, mixed-signal system-on-a-chip MCUs. Highlighted features are listed below. Refer to Table 1.1 for specific product feature selection. • • • • • • • • • • • • • • • High-speed pipelined 8051-compatible microcontroller core (up to 50 MIPS) In-system, full-speed, non-intrusive debug interface (on-chip) True 12-bit 200 ksps ADC with analog multiplexer and 24 analog inputs Two 12-bit Current Output DACs Precision programmable 24.5 MHz internal oscillator Up to 32 kB bytes of on-chip Flash memory 2304 bytes of on-chip RAM SMBus/I2C, Enhanced UART, and SPI serial interfaces implemented in hardware Four general-purpose 16-bit timers Programmable Counter/Timer Array (PCA) with six capture/compare modules and Watchdog Timer function Hardware smaRTClock (Real Time Clock) operates down to 1 V with 64 bytes of Backup RAM and a Backup Voltage Regulator Hardware CRC Engine On-chip Power-On Reset, VDD Monitor, and Temperature Sensor On-chip Voltage Comparators Up to 24 Port I/O With on-chip Power-On Reset, VDD monitor, Watchdog Timer, and clock oscillator, the C8051F41x devices are truly standalone system-on-a-chip solutions. The Flash memory can be reprogrammed even in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. User software has complete control of all peripherals, and may individually shut down any or all peripherals for power savings. The on-chip Silicon Laboratories 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging using C2. The two C2 interface pins can be shared with user functions, allowing in-system programming and debugging without occupying package pins. Each device is specified for 2.0-to-2.75 V operation (supply voltage can be up to 5.25 V using on-chip regulator) over the industrial temperature range (–45 to +85 °C). The C8051F41x are available in 28-pin QFN (also referred to as MLP or MLF) or 32-pin LQFP packages. Rev. 1.0 19 20 Ordering Part Number MIPS (Peak) Flash Memory RAM Calibrated Internal 24.5 MHz Oscillator Clock Multiplier SMBus/I2C SPI UART 4 4 4 4 Timers (16-bit) Programmable Counter Array 20 24 20 24 Port I/Os 12-bit ADC ±1 LSB INL smaRTClock (Real Time Clock) Two 12-bit Current Output DACs Internal Voltage Reference Temperature Sensor Analog Comparators Lead-Free (RoHS compliant) C8051F413-GM 50 16 kB 2368 C8051F412-GQ 50 16 kB 2368 C8051F411-GM 50 32 kB 2368 C8051F410-GQ 50 32 kB 2368 C8051F410/1/2/3 Table 1.1. Product Selection Guide Rev. 1.0 LQFP-32 QFN-28 QFN-28 LQFP-32 Package C8051F410/1/2/3 VREGIN VREG (to rest of chip) VIO VDD VRTC-BACKUP GND (to smarRTClock Block) Port 0 Latch Port 1 Latch UART C R O S S B A R P 0 D r v P 1 D r v P 2 D r v IDAC0 Battery Switch-Over Circuit (VDD >= VRTC-BACKUP) C2D P0.0/IDAC0 P0.1/IDAC1 P0.2 P0.3 P0.4/TX P0.5/RX P0.6/CNVST P0.7 P1.0/XTAL1 P1.1/XTAL2 P1.2/VREF P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7/C2D Debug HW Reset /RST/C2CK POR BrownOut 8 0 5 1 x16 32 kB FLASH 256 B SRAM 2 kB XRAM Timer 0,1,2,3 PCA x6 / WDT SMBus SPI Port 2 Latch 12-bit IDAC0 12-bit IDAC1 XTAL1 XTAL2 External Oscillator Circuit 24.5 MHz 2% Oscillator Clock Mult. C o SFR Bus r CRC e Engine IDAC1 CP1 CP0 + + - XTAL3 XTAL4 32 KHz Oscillator 64B RAM VREF VDD Temp smaRTClock State Machine smaRTClock Block smaRTClock Alarm 12-bit 200 ksps ADC A M U X AIN0-AIN23 Figure 1.1. C8051F410 Block Diagram Rev. 1.0 21 C8051F410/1/2/3 VREGIN VREG (to rest of chip) VIO VDD VRTC-BACKUP GND (to smaRTClock Block) Port 0 Latch Port 1 Latch UART C R O S S B A R P 0 D r v P 1 D r v P 2 D r v IDAC0 Battery Switch-Over Circuit (VDD >= VRTC-BACKUP) C2D P0.0/IDAC0 P0.1/IDAC1 P0.2 P0.3 P0.4/TX P0.5/RX P0.6/CNVST P0.7 P1.0/XTAL1 P1.1/XTAL2 P1.2/VREF P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 Debug HW Reset /RST/C2CK POR BrownOut 8 0 5 1 x16 32 kB FLASH 256 B SRAM 2 kB XRAM Timer 0,1,2,3 PCA x6 / WDT SMBus SPI Port 2 Latch 12-bit IDAC0 12-bit IDAC1 XTAL1 XTAL2 External Oscillator Circuit 24.5 MHz 2% Oscillator Clock Mult. C o SFR Bus r CRC e P2.7/C2D Engine IDAC1 CP1 CP0 + + - XTAL3 XTAL4 32 KHz Oscillator 64B RAM VREF VDD Temp smaRTClock State Machine smaRTClock Block smaRTClock Alarm 12-bit 200 ksps ADC A M U X AIN0-AIN20 Figure 1.2. C8051F411 Block Diagram 22 Rev. 1.0 C8051F410/1/2/3 VREGIN VREG (to rest of chip) VIO VDD VRTC-BACKUP GND (to smaRTClocl Block) Port 0 Latch Port 1 Latch UART C R O S S B A R P 0 D r v P 1 D r v P 2 D r v IDAC0 Battery Switch-Over Circuit (VDD >= VRTC-BACKUP) C2D P0.0/IDAC0 P0.1/IDAC1 P0.2 P0.3 P0.4/TX P0.5/RX P0.6/CNVST P0.7 P1.0/XTAL1 P1.1/XTAL2 P1.2/VREF P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7/C2D Debug HW Reset /RST/C2CK POR BrownOut 8 0 5 1 x16 16 kB FLASH 256 B SRAM 2 kB XRAM Timer 0,1,2,3 PCA x6 / WDT SMBus SPI Port 2 Latch 12-bit IDAC0 12-bit IDAC1 XTAL1 XTAL2 External Oscillator Circuit 24.5 MHz 2% Oscillator Clock Mult. C o SFR Bus r CRC e Engine IDAC1 CP1 CP0 + + - XTAL3 XTAL4 32 KHz Oscillator 64B RAM VREF VDD Temp smaRTClock State Machine smaRTClock Block smaRTClock Alarm 12-bit 200 ksps ADC A M U X AIN0-AIN23 Figure 1.3. C8051F412 Block Diagram Rev. 1.0 23 C8051F410/1/2/3 VIO VREGIN VDD VRTC-BACKUP GND VREG (to rest of chip) (to smaRTClock Block) Port 0 Latch Port 1 Latch UART C R O S S B A R P 0 D r v P 1 D r v P 2 D r v IDAC0 Battery Switch-Over Circuit (VDD >= VRTC-BACKUP) C2D P0.0/IDAC0 P0.1/IDAC1 P0.2 P0.3 P0.4/TX P0.5/RX P0.6/CNVST P0.7 P1.0/XTAL1 P1.1/XTAL2 P1.2/VREF P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 Debug HW Reset /RST/C2CK POR BrownOut 8 0 5 1 x16 16 kB FLASH 256 B SRAM 2 kB XRAM Timer 0,1,2,3 PCA x6 / WDT SMBus SPI Port 2 Latch 12-bit IDAC0 12-bit IDAC1 XTAL1 XTAL2 External Oscillator Circuit 24.5 MHz 2% Oscillator Clock Mult. C o SFR Bus r CRC e P2.7/C2D Engine IDAC1 CP1 CP0 + + - XTAL3 XTAL4 32 KHz Oscillator 64B RAM VREF VDD Temp smaRTClock State Machine smaRTClock Block smaRTClock Alarm 12-bit 200 ksps ADC A M U X AIN0-AIN20 Figure 1.4. C8051F413 Block Diagram 24 Rev. 1.0 C8051F410/1/2/3 1.1. CIP-51™ Microcontroller 1.1.1. Fully 8051 Compatible Instruction Set The C8051F41x devices use Silicon Laboratories’ proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51™ instruction set. Standard 803x/805x assemblers and compilers can be used to develop software. The C8051F41x family has a superset of all the peripherals included with a standard 8052. 1.1.2. Improved Throughput The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute, and usually have a maximum system clock of 12-to-24 MHz. By contrast, the CIP51 core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more than eight system clock cycles. With the CIP-51's system clock running at 50 MHz, it has a peak throughput of 50 MIPS. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execution time. Clocks to Execute Number of Instructions 1 26 2 50 2/4 5 3 10 3/5 7 4 5 5 2 4/6 1 6 2 8 1 1.1.3. Additional Features The C8051F41x SoC family includes several key enhancements to the CIP-51 core and peripherals to improve performance and ease of use in end applications. An extended interrupt handler allows the numerous analog and digital peripherals to operate independently of the controller core and interrupt the controller only when necessary. By requiring less intervention from the microcontroller core, an interrupt-driven system is more efficient and allows for easier implementation of multi-tasking, real-time systems. Eight reset sources are available: power-on reset circuitry (POR), an on-chip VDD monitor, a Watchdog Timer, a Missing Clock Detector, a voltage level detection from Comparator0, a smaRTClock alarm or missing smaRTClock clock detector reset, a forced software reset, an external reset pin, and an illegal Flash access protection circuit. Each reset source except for the POR, Reset Input Pin, or Flash error may be disabled by the user in software. The WDT may be permanently enabled in software after a power-on reset during MCU initialization. The internal oscillator is factory calibrated to 24.5 MHz ±2%. An external oscillator drive circuit is also included, allowing an external crystal, ceramic resonator, capacitor, RC, or CMOS clock source to generate the system clock. A clock multiplier allows for operation at up to 50 MHz. The dedicated smaRTClock oscillator can be extremely useful in low power applications, allowing the system to maintain accurate time while the MCU is not powered, or its internal oscillator is suspended. The MCU can be reset or have its oscillator awakened using the smaRTClock alarm function. Rev. 1.0 25 C8051F410/1/2/3 1.2. On-Chip Debug Circuitry The C8051F41x devices include on-chip Silicon Laboratories 2-Wire (C2) debug circuitry that provides non-intrusive, full speed, in-circuit debugging of the production part installed in the end application. Silicon Laboratories’ debugging system supports inspection and modification of memory and registers, breakpoints, and single stepping. No additional target RAM, program memory, timers, or communications channels are required. All the digital and analog peripherals are functional and work correctly while debugging. All the peripherals (except for the ADC and SMBus) are stalled when the MCU is halted, during single stepping, or at a breakpoint in order to keep them synchronized. The C8051F410DK development kit provides all the hardware and software necessary to develop application code and perform in-circuit debugging with the C8051F41x MCUs. The kit includes software with a developer's studio and debugger, a USB debug adapter, a target application board with the associated MCU installed, and the required cables and wall-mount power supply. The development kit requires a computer with Windows®98 SE or later installed. As shown in Figure 1.5, the PC is connected to the USB debug adapter. A six-inch ribbon cable connects the USB debug adapter to the user's application board, picking up the two C2 pins and GND. The Silicon Laboratories IDE interface is a vastly superior developing and debugging configuration, compared to standard MCU emulators that use on-board "ICE Chips" and require the MCU in the application board to be socketed. Silicon Laboratories’ debug paradigm increases ease of use and preserves the performance of the precision analog peripherals. Silicon Laboratories Integrated Development Environment WINDOWS 98 SE or later USB Debug Adapter C2 (x2), GND VDD GND TARGET PCB C8051F41x Figure 1.5. Development/In-System Debug Diagram 26 Rev. 1.0 C8051F410/1/2/3 1.3. On-Chip Memory The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and direct addressing accesses the 128-byte SFR address space. The lower 128 bytes of RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as four banks of general purpose registers, and the next 16 bytes can be byte addressable or bit addressable. Program memory consists of 32 kB (‘F410/1) or 16 kB (‘F412/3) of Flash. This memory may be reprogrammed in-system in 512 byte sectors and requires no special off-chip programming voltage. PROGRAM/DATA MEMORY (Flash) ‘F410/1 0xFF 0x7E00 0x7DFF RESERVED 0x80 0x7F DATA MEMORY (RAM) INTERNAL DATA ADDRESS SPACE Upper 128 RAM (Indirect Addressing Only) (Direct and Indirect Addressing) Special Function Register's (Direct Addressing Only) 32 kB Flash (In-System Programmable in 512 Byte Sectors) 0x30 0x2F 0x20 0x1F 0x00 Bit Addressable General Purpose Registers L ower 128 RAM (Direct and Indirect Addressing) 0x0000 EXTERNAL DATA ADDRESS SPACE ‘F412/3 0xFFFF 0x4000 0x3FFF RESERVED Same 2048 bytes as from 0x0000 to 0x07FF, wrapped on 2048-byte boundaries 16 kB Flash (In-System Programmable in 512 Byte Sectors) 0x0800 0x07FF XRAM - 2048 Bytes (accessible using MOVX instruction) 0x0000 0x0000 Figure 1.6. Memory Map Rev. 1.0 27 C8051F410/1/2/3 1.4. Operating Modes The C8051F41x devices have four operating modes: Active (Normal), Idle, Suspend, and Stop. Active mode occurs during normal operation when the oscillator and peripherals are active. Idle mode halts the CPU while leaving the peripherals and internal clocks active. Suspend mode halts SYSCLK until a wakening event occurs, which also halts all peripherals using SYSCLK. In Stop mode, the CPU is halted, all interrupts and timers are inactive, and the internal oscillator is stopped. The various operating modes are described in Table 1.2 below: Table 1.2. Operating Modes Summary Properties • • • • • • Idle • • • • Suspend • SYSCLK active CPU active (accessing Flash) Peripherals active or inactive depending on user settings smaRTClock active or inactive SYSCLK active CPU inactive (not accessing Flash) Peripherals active or inactive depending on user settings smaRTClock active or inactive SYSCLK inactive CPU inactive (not accessing Flash) Peripherals enabled (but not operating) or disabled depending on user settings smaRTClock active or inactive SYSCLK inactive CPU inactive (not accessing Flash) Digital peripherals inactive; analog peripherals enabled (but not operating) or disabled depending on user settings smaRTClock inactive Power Consumption Full How Entered? — How Exited? — Active Less than Full IDLE (PCON.0) Any enabled interrupt or device reset Low SUSPEND (OSCICN.5) Wakening event or external/MCD reset • • • Stop • Very low STOP (PCON.1) External or MCD reset • See Section “10.3. Power Management Modes” on page 101 for Idle and Stop mode details. See Section “19.1.1. Internal Oscillator Suspend Mode” on page 166 for more information on Suspend mode. 28 Rev. 1.0 C8051F410/1/2/3 1.5. 12-Bit Analog to Digital Converter The C8051F41x devices include an on-chip 12-bit SAR ADC with a 27-channel single-ended input multiplexer and a maximum throughput of 200 ksps. The ADC system includes a configurable analog multiplexer that selects the positive ADC input, which is measured with respect to GND. Ports 0–2 are available as ADC inputs; additionally, the on-chip Temperature Sensor output and the core supply voltage (VDD) are available as ADC inputs. User firmware may shut down the ADC or use it in Burst Mode to save power. Conversions can be started in four ways: a software command, an overflow of Timer 2 or 3, or an external convert start signal. This flexibility allows the start of conversion to be triggered by software events, a periodic signal (timer overflows), or external HW signals. Conversion completions are indicated by a status bit and an interrupt (if enabled) and occur after 1, 4, 8, or 16 samples have been accumulated by a hardware accumulator. The resulting data word is latched into the ADC data SFRs upon completion of a conversion. When the system clock is slow, Burst Mode allows ADC0 to automatically wake from a low power shutdown state, acquire and accumulate samples, then re-enter the low power shutdown state without CPU intervention. Window compare registers for the ADC data can be configured to interrupt the controller when ADC data is either within or outside of a specified range. The ADC can monitor a key voltage continuously in background mode, but not interrupt the controller unless the converted data is within/outside the specified range. A nalog Multiplexer Configuration, Control, and Data Registers P0.0 Start Conversion AD0BUSY (W) Timer 3 Overflow CNVSTR Rising Edge Timer 2 Overflow P0.7 P1.0 Burst Mode Logic P1.7 P2.0 P2.3-2.6 available on C8051F410/2 19-to-1 AMUX 12-Bit SAR P2.7 ADC End of Conversion Interrupt 16 ADC Data Registers Accumulator Temp Sensor VDD GND Window Compare Logic Window Compare Interrupt Figure 1.7. 12-Bit ADC Block Diagram 1.6. Two 12-bit Current-Mode DACs The C8051F41x devices include two 12-bit current-mode Digital-to-Analog Converters (IDACs). The maximum current output of the IDACs can be adjusted for four different current settings; 0.25 mA, 0.5 mA, 1 mA, and 2 mA. A flexible output update mechanism allows for seamless full-scale changes, and supports jitter-free updates for waveform generation. The IDAC outputs can be merged onto a single port I/O pin for increased full-scale current output or increased resolution. IDAC updates can be performed on-demand, scheduled on a Timer overflow, or synchronized with an external signal. Figure 1.8 shows a block diagram of the IDAC circuitry. Rev. 1.0 29 C8051F410/1/2/3 Data Write Timer 0 Timer 1 Timer 2 Timer 3 CNVSTR 12-bit Digital 12 Input Latch 12 IDA0 Current Output 12-bit Digital 12 Input Data Write Timer 0 Timer 1 Timer 2 Timer 3 CNVSTR Latch 12 IDA1 Current Output Figure 1.8. IDAC Block Diagram 1.7. Programmable Comparators C8051F41x devices include two software-configurable voltage comparators with an input multiplexer. Each comparator offers programmable response time and hysteresis and two outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0 and CP1), or an asynchronous “raw” output (CP0A and CP1A). Comparator interrupts may be generated on rising, falling, or both edges. When in IDLE or SUSPEND mode, these interrupts may be used as a “wake-up” source for the processor. Comparator0 may also be configured as a reset source. A block diagram of the comparator is shown in Figure 1.9. 30 Rev. 1.0 C8051F410/1/2/3 VDD Interrupt Logic Multiplexer Port I/O Pins + D SET Q D SET Q GND Reset Decision Tree VDD CP0 (synchronous output) CLR Q CLR Q (SYNCHRONIZER) CP0A (asynchronous output) Interrupt Logic Multiplexer Port I/O Pins + D SET Q D SET Q GND CP1 (synchronous output) CLR Q CLR Q (SYNCHRONIZER) CP1A (asynchronous output) Figure 1.9. Comparators Block Diagram 1.8. Cyclic Redundancy Check Unit C8051F41x devices include a cyclic redundancy check unit (CRC0) that can perform a CRC using a 16-bit or 32-bit polynomial. CRC0 accepts a stream of 8-bit data and outputs a 16-bit or 32-bit result. CRC0 also has a hardware bit reverse feature for quick data manipulation. 1.9. Voltage Regulator C8051F41x devices include an on-chip low dropout voltage regulator (REG0). The input to REG0 at the VREGIN pin can be as high as 5.25 V. The output can be selected by software to 2.0 V or 2.5 V. When enabled, the output of REG0 powers the device and drives the VDD pin. The voltage regulator can be used to power external devices connected to VDD. 1.10. Serial Ports The C8051F41x Family includes an SMBus/I2C interface, a full-duplex UART with enhanced baud rate configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention. Rev. 1.0 31 C8051F410/1/2/3 1.11. smaRTClock (Real Time Clock) C8051F41x devices include a smaRTClock Peripheral (Real Time Clock). The smaRTClock has a dedicated 32 kHz oscillator that can be configured for use with or without a crystal, a 47-bit smaRTClock timer with alarm, a backup supply regulator, and 64 bytes of backup SRAM. When the backup supply voltage (VRTC-BACKUP) is powered, the smaRTClock peripheral remains fully functional even if the core supply voltage (VDD) is lost. The smaRTClock allows a maximum of 137 year 47-bit independent time-keeping when used with a 32.768 kHz Watch Crystal and backup supply voltage of at least 1 V. The switchover logic powers smaRTClock from the backup supply when the voltage at VRTC-BACKUP is greater than VDD. The smaRTClock alarm and missing clock detector can interrupt the CIP-51, wake the internal oscillator from SUSPEND mode, or generate a device reset if the smaRTClock timer reaches a pre-set value or the oscillator stops. XTAL4 XTAL3 smaRTClock smaRTClock Oscillator 47-Bit smaRTClock Timer CIP-51 CPU VDD smaRTClock State Machine Interrupt 64B Backup RAM Internal Registers CAPTUREn RTC0CN RTC0XCN ALARMn RAMADDR RAMDATA Interface Registers RTC0KEY RTC0ADR RTC0DAT Backup Regulator Switchover Logic VRTC-BACKUP Figure 1.10. smaRTClock Block Diagram 32 Rev. 1.0 C8051F410/1/2/3 1.12. Port Input/Output C8051F41x devices include up to 24 I/O pins. Port pins are organized as three byte-wide ports. The port pins behave like typical 8051 ports with a few enhancements. Each port pin can be configured as a digital or analog I/O pin. Pins selected as digital I/O can be configured for push-pull or open-drain operation. The “weak pullups” that are fixed on typical 8051 devices may be individually or globally disabled to save power. The Digital Crossbar allows mapping of internal digital system resources to port I/O pins. On-chip counter/timers, serial buses, hardware interrupts, and other digital signals can be configured to appear on the port pins using the Crossbar control registers. This allows the user to select the exact mix of generalpurpose port I/O, digital, and analog resources needed for the application. XBR0, XBR1, PnSKIP Registers P0MASK, P0MATCH P1MASK, P1MATCH Registers Priority Decoder UART SPI (Internal Digital Signals) SMBus CP0 CP1 Outputs SYSCLK PCA Lowest Priority 7 2 8 P0 (Port Latches) (P0.0-P0.7) 8 P1 (P1.0-P1.7) 8 P2 (P2.0-P2.7) 4 2 4 2 PnMDOUT, PnMDIN Registers Highest Priority Digital Crossbar 8 P0 I/O Cells P0.0 P0.7 P1.0 P1.7 P2.0 P2.7 8 P1 I/O Cells T0, T1 8 P2 I/O Cell P2.3–2.6 available on C8051F410/2 Figure 1.11. Port I/O Functional Block Diagram Rev. 1.0 33 C8051F410/1/2/3 1.13. Programmable Counter Array The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer and six 16-bit capture/compare modules. The counter/timer is driven by a programmable timebase that can select between seven sources: system clock, system clock divided by four, system clock divided by twelve, the external oscillator clock source divided by 8, real-time clock source divided by 8, Timer 0 overflow, or an external clock signal on the External Clock Input (ECI) pin. Each capture/compare module may be configured to operate independently in one of six modes: EdgeTriggered Capture, Software Timer, High-Speed Output, Frequency Output, 8-Bit PWM, or 16-Bit PWM. Additionally, PCA Module 5 may be used as a watchdog timer (WDT), and is enabled in this mode following a system reset. The PCA Capture/Compare Module I/O and the External Clock Input may be routed to Port I/O using the digital crossbar. SYSCLK/12 SYSCLK/4 Timer 0 Overflow ECI SYSCLK External Clock/8 smaRTClock/8 PCA CLOCK MUX 16-Bit Counter/Timer Capture/Compare Module 0 Capture/Compare Module 1 Capture/Compare Module 2 Capture/Compare Module 3 Capture/Compare Module 4 Capture/Compare Module 5 CEX0 CEX1 CEX2 CEX3 CEX4 CEX5 ECI Crossbar Port I/O Figure 1.12. PCA Block Diagram 34 Rev. 1.0 C8051F410/1/2/3 2. Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings* Parameter Ambient temperature under bias Storage Temperature Voltage on VREGIN with respect to GND Voltage on VDD with respect to GND Voltage on VRTC-BACKUP with respect to GND Voltage on XTAL1 with respect to GND Voltage on XTAL3 with respect to GND Voltage on any Port I/O Pin (except Port 0 pins) or RST with respect to GND Voltage on any Port 0 Pin with respect to GND Maximum output current sunk by any Port pin Maximum output current sourced by any Port pin Maximum Total current through VDD, VIO, VRTC-BACKUP, VREGIN, and GND Conditions Min –55 –65 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 0.3 — — — Typ — — — — — — — — — — — — Max 125 150 5.5 3.0 5.5 VDD+ 0.3 5.5 VIO + 0.3 5.5 100 100 500 Units °C °C V V V V V V V mA mA mA *Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Rev. 1.0 35 C8051F410/1/2/3 3. Global DC Electrical Characteristics Table 3.1. Global DC Electrical Characteristics –40 to +85 °C, 50 MHz System Clock unless otherwise specified. Typical values are given at 25 °C Parameter Supply Input Voltage (VREGIN)1 Core Supply Voltage (VDD) I/O Supply Voltage (VIO) Backup Supply Voltage (VRTC-BACKUP)2 Backup Supply Current (IRTC-BACKUP) (VDD = 0 V, smaRTClock clock = 32 kHz) Conditions Output Current = 1 mA Min 2.15 2.0 2.0 1.0 Typ — — — — 0.65 0.9 1.4 0.7 0.92 1.45 0.72 0.95 1.5 1.5 — — Max 5.25 2.75 5.25 5.25 1.5 1.8 2.5 — — — 1.6 1.85 2.6 — 50 +85 Units V V V V µA µA µA µA µA µA µA µA µA V MHz °C VRTC-BACKUP = 1.0 V: at –40 ºC at 25 ºC at 85 ºC VRTC-BACKUP = 1.8 V: at –40 ºC at 25 ºC at 85 ºC VRTC-BACKUP = 2.5 V: at –40 ºC at 25 ºC at 85 ºC — — — — — — — — — — 0 –40 Core Supply RAM Data Retention Voltage SYSCLK (System Clock)3,4 Specified Operating Temperature Range Notes: 1. For more information on VREGIN characteristics, see Table 8.1 on page 82. 2. The Backup Supply Voltage (VRTC-BACKUP) is used to power the smaRTClock peripheral only. 3. SYSCLK is the internal device clock. For operational speeds in excess of 25 MHz, SYSCLK must be derived from the internal clock multiplier. 4. SYSCLK must be at least 32 kHz to enable debugging. 5. Based on device characterization data, not production tested. 6. Active and Inactive IDD at voltages and frequencies other than those specified can be calculated using the IDD Supply Sensitivity. For example, if the VDD is 2.2 V instead of 2.0 V at 25 MHz: IDD = 5.5 mA typical at 2.0 V and f = 25 MHz. From this, IDD = 5.5 mA + 1.14 x (2.2 V – 2.0 V) = 5.73 mA at 2.2 V and f = 25 MHz. 7. IDD can be estimated for frequencies < 15 MHz by simply multiplying the frequency of interest by the frequency sensitivity number for that range. When using these numbers to estimate IDD for > 15 MHz, the estimate should be the current at 25 MHz minus the difference in current indicated by the frequency sensitivity number. For example: VDD = 2.0 V; F = 20 MHz, IDD = 5.5 mA – (25 MHz – 20 MHz) x 0.16 mA/MHz = 4.7 mA. 8. Idle IDD can be estimated for frequencies < 1 MHz by simply multiplying the frequency of interest by the frequency sensitivity number for that range. When using these numbers to estimate Idle for > 1 MHz, the estimate should be the current at 25 MHz minus the difference in current indicated by the frequency sensitivity number. For example: VDD = 2.0 V; F = 5 MHz, Idle IDD = 2.8 mA – (25 MHz – 5 MHz) x 0.1 mA/MHz = 0.8 mA. 36 Rev. 1.0 C8051F410/1/2/3 Table 3.1. Global DC Electrical Characteristics (Continued) –40 to +85 °C, 50 MHz System Clock unless otherwise specified. Typical values are given at 25 °C Parameter Conditions Min Typ Max Units Digital Supply Current—CPU Active (Normal Mode, fetching instructions from Flash) Core Supply Current (IDD)5 VDD = 2.0 V: F = 32 kHz F = 1 MHz F = 25 MHz F = 50 MHz VDD = 2.5 V: F = 32 kHz F = 1 MHz F = 25 MHz F = 50 MHz F = 25 MHz F = 1 MHz — — — — — — — — — — — — — — 13 0.30 5.5 9.5 17 0.43 8.3 13.5 114 100 0.27 0.16 0.39 0.2 30 0.5 6.5 12 40 0.65 9.5 15 — — — — — — µA mA mA mA µA mA mA mA %/V %/V mA/MHz mA/MHz mA/MHz mA/MHz Supply Sensitivity (IDD)5,6 Frequency Sensitivity (IDD)5,7 VDD = 2.0 V: F < 15 MHz, T = 25 ºC F > 15 MHz, T = 25 ºC VDD = 2.5 V: F < 15 MHz, T = 25 ºC F > 15 MHz, T = 25 ºC Notes: 1. For more information on VREGIN characteristics, see Table 8.1 on page 82. 2. The Backup Supply Voltage (VRTC-BACKUP) is used to power the smaRTClock peripheral only. 3. SYSCLK is the internal device clock. For operational speeds in excess of 25 MHz, SYSCLK must be derived from the internal clock multiplier. 4. SYSCLK must be at least 32 kHz to enable debugging. 5. Based on device characterization data, not production tested. 6. Active and Inactive IDD at voltages and frequencies other than those specified can be calculated using the IDD Supply Sensitivity. For example, if the VDD is 2.2 V instead of 2.0 V at 25 MHz: IDD = 5.5 mA typical at 2.0 V and f = 25 MHz. From this, IDD = 5.5 mA + 1.14 x (2.2 V – 2.0 V) = 5.73 mA at 2.2 V and f = 25 MHz. 7. IDD can be estimated for frequencies < 15 MHz by simply multiplying the frequency of interest by the frequency sensitivity number for that range. When using these numbers to estimate IDD for > 15 MHz, the estimate should be the current at 25 MHz minus the difference in current indicated by the frequency sensitivity number. For example: VDD = 2.0 V; F = 20 MHz, IDD = 5.5 mA – (25 MHz – 20 MHz) x 0.16 mA/MHz = 4.7 mA. 8. Idle IDD can be estimated for frequencies < 1 MHz by simply multiplying the frequency of interest by the frequency sensitivity number for that range. When using these numbers to estimate Idle for > 1 MHz, the estimate should be the current at 25 MHz minus the difference in current indicated by the frequency sensitivity number. For example: VDD = 2.0 V; F = 5 MHz, Idle IDD = 2.8 mA – (25 MHz – 5 MHz) x 0.1 mA/MHz = 0.8 mA. Rev. 1.0 37 C8051F410/1/2/3 Table 3.1. Global DC Electrical Characteristics (Continued) –40 to +85 °C, 50 MHz System Clock unless otherwise specified. Typical values are given at 25 °C Parameter Conditions Min Typ Max Units Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from Flash) Core Supply Current (IDD)5 VDD = 2.0 V: F = 32 kHz F = 1 MHz F = 25 MHz F = 50 MHz VDD = 2.5 V: F = 32 kHz F = 1 MHz F = 25 MHz F = 50 MHz F = 25 MHz F = 1 MHz — — — — — — — — — — — — — — — — 10 0.15 2.8 5 11 0.21 3.8 7.5 75 68 0.14 0.1 0.19 0.13 0.15 0.15 25 0.25 3.3 11 30 0.37 4.3 8.0 — — — — — — 50 50 µA mA mA mA µA mA mA mA %/V %/V mA/MHz mA/MHz mA/MHz mA/MHz µA µA Supply Sensitivity (IDD)5,6 Frequency Sensitivity (IDD)5,8 VDD = 2.0 V: F < 1 MHz, T = 25 ºC F > 1 MHz, T = 25 ºC VDD = 2.5 V: F < 1 MHz, T = 25 ºC F > 1 MHz, T = 25 ºC Oscillator not running, VDD = 2.5 V Oscillator not running, VDD = 2.5 V Digital Supply Current (Suspend Mode) Digital Supply Current (Stop Mode, shutdown) Notes: 1. For more information on VREGIN characteristics, see Table 8.1 on page 82. 2. The Backup Supply Voltage (VRTC-BACKUP) is used to power the smaRTClock peripheral only. 3. SYSCLK is the internal device clock. For operational speeds in excess of 25 MHz, SYSCLK must be derived from the internal clock multiplier. 4. SYSCLK must be at least 32 kHz to enable debugging. 5. Based on device characterization data, not production tested. 6. Active and Inactive IDD at voltages and frequencies other than those specified can be calculated using the IDD Supply Sensitivity. For example, if the VDD is 2.2 V instead of 2.0 V at 25 MHz: IDD = 5.5 mA typical at 2.0 V and f = 25 MHz. From this, IDD = 5.5 mA + 1.14 x (2.2 V – 2.0 V) = 5.73 mA at 2.2 V and f = 25 MHz. 7. IDD can be estimated for frequencies < 15 MHz by simply multiplying the frequency of interest by the frequency sensitivity number for that range. When using these numbers to estimate IDD for > 15 MHz, the estimate should be the current at 25 MHz minus the difference in current indicated by the frequency sensitivity number. For example: VDD = 2.0 V; F = 20 MHz, IDD = 5.5 mA – (25 MHz – 20 MHz) x 0.16 mA/MHz = 4.7 mA. 8. Idle IDD can be estimated for frequencies < 1 MHz by simply multiplying the frequency of interest by the frequency sensitivity number for that range. When using these numbers to estimate Idle for > 1 MHz, the estimate should be the current at 25 MHz minus the difference in current indicated by the frequency sensitivity number. For example: VDD = 2.0 V; F = 5 MHz, Idle IDD = 2.8 mA – (25 MHz – 5 MHz) x 0.1 mA/MHz = 0.8 mA. 38 Rev. 1.0 C8051F410/1/2/3 Table 3.2. Index to Electrical Characteristics Tables Table Title ADC0 Electrical Characteristics (VDD = 2.5 V, VREF = 2.2 V) ADC0 Electrical Characteristics (VDD = 2.1 V, VREF = 1.5 V) IDAC Electrical Characteristics Voltage Reference Electrical Characteristics Voltage Regulator Electrical Specifications Comparator Electrical Characteristics Reset Electrical Characteristics Flash Electrical Characteristics Port I/O DC Electrical Characteristics Oscillator Electrical Characteristics Page # 67 68 75 79 82 92 134 143 163 175 Rev. 1.0 39 C8051F410/1/2/3 NOTES: 40 Rev. 1.0 C8051F410/1/2/3 4. Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F41x Name VDD VIO GND VRTC-BACKUP VREGIN RST/ Pin Numbers ‘F410/2 7 1 6 3 8 ‘F411/3 6 28 5 2 7 Type Description Core Supply Voltage. I/O Supply Voltage. Ground. smaRTClock Backup Supply Voltage. On-Chip Voltage Regulator Input. D I/O 2 1 D I/O D I/O Device Reset. Open-drain output of internal POR or VDD monitor. An external source can initiate a system reset by driving this pin low for at least 15 µs. A 1 kΩ pullup to VIO is recommended. See Reset Sources Section for a complete description. Clock signal for the C2 Debug Interface. Port 2.7. See Port I/O Section for a complete description. Bi-directional data signal for the C2 Debug Interface. smaRTClock Oscillator Crystal Input. See Section 20. "smaRTClock (Real Time Clock)" for a complete description. smaRTClock Oscillator Crystal Input. See Section 20. "smaRTClock (Real Time Clock)" for a complete description. C2CK P2.7/ 32 C2D 27 D I/O XTAL3 5 4 A In XTAL4 P0.0/ 4 3 A Out 17 IDAC0 P0.1/ 18 IDAC1 P0.2 P0.3 19 20 16 D I/O or Port 0.0. See Port I/O Section for a complete description. A In A Out IDAC0 Output. See IDAC Section for complete description. D I/O or Port 0.1. See Port I/O Section for a complete description. A In 17 A Out 18 19 IDAC1 Output. See IDAC Section for complete description. D I/O or Port 0.2. See Port I/O Section for a complete description. A In D I/O or Port 0.3. See Port I/O Section for a complete description. A In Rev. 1.0 41 C8051F410/1/2/3 Table 4.1. Pin Definitions for the C8051F41x (Continued) Name P0.4/ 21 TX P0.5/ 22 RX P0.6/ 23 CNVSTR P0.7 P1.0/ 9 XTAL1 8 24 23 22 D In External Convert Start Input for ADC0, IDA0, and IDA1. See ADC0 or IDACs section for a complete description. 21 D In UART RX Pin. See Port I/O Section for a complete description. 20 D Out UART TX Pin. See Port I/O Section for a complete description. Pin Numbers ‘F410/2 ‘F411/3 Type Description D I/O or Port 0.4. See Port I/O Section for a complete description. A In D I/O or Port 0.5. See Port I/O Section for a complete description. A In D I/O or Port 0.6. See Port I/O Section for a complete description. A In D I/O or Port 0.7. See Port I/O Section for a complete description. A In D I/O or Port 1.0. See Port I/O Section for a complete description. A In External Clock Input. This pin is the external oscillator A In return for a crystal or resonator. See Oscillator Section. Port 1.1. See Port I/O Section for a complete description. D I/O or A In P1.1/ 10 XTAL2 9 A O or D In External Clock Output. This pin is the excitation driver for an external crystal or resonator, or an external clock input for CMOS, capacitor, or RC oscillator configurations. See Oscillator Section. P1.2 11 VREF P1.3 P1.4 P1.5 P1.6 12 13 14 15 11 12 13 14 10 D I/O or Port 1.2. See Port I/O Section for a complete description. A In A In External VREF Input. See VREF Section. D I/O or Port 1.3. See Port I/O Section for a complete description. A In D I/O or Port 1.4. See Port I/O Section for a complete description. A In D I/O or Port 1.5. See Port I/O Section for a complete description. A In D I/O or Port 1.6. See Port I/O Section for a complete description. A In 42 Rev. 1.0 C8051F410/1/2/3 Table 4.1. Pin Definitions for the C8051F41x (Continued) Name P1.7 P2.0 P2.1 P2.2 P2.3* P2.4* P2.5* P2.6* Pin Numbers ‘F410/2 16 25 26 27 28 29 30 31 ‘F411/3 15 24 25 26 Type Description D I/O or Port 1.7. See Port I/O Section for a complete description. A In D I/O or Port 2.0. See Port I/O Section for a complete description. A In D I/O or Port 2.1. See Port I/O Section for a complete description. A In D I/O or Port 2.2. See Port I/O Section for a complete description. A In D I/O or Port 2.3. See Port I/O Section for a complete description. A In D I/O or Port 2.4. See Port I/O Section for a complete description. A In D I/O or Port 2.5. See Port I/O Section for a complete description. A In D I/O or Port 2.6. See Port I/O Section for a complete description. A In *Note: Available only on the C8051F410/2. Rev. 1.0 43 C8051F410/1/2/3 P2.7 / C2D P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 32 31 30 29 28 27 26 V IO RST/C2CK V RTC-BACKUP XTAL4 XTAL3 GND V DD V REGIN 1 2 3 4 5 6 7 8 25 P2.0 24 23 22 P0.7 P0.6 / CNVSTR P0.5 / RX P0.4 / TX P0.3 P0.2 P0.1 / IDAC1 P0.0 / IDAC0 C8051F410/2 Top View 21 20 19 18 17 10 11 12 13 14 15 P1.6 P1.0 / XTAL1 P1.1 / XTAL2 P1.2 / VREF P1.3 P1.4 P1.5 Figure 4.1. LQFP-32 Pinout Diagram (Top View) 44 Rev. 1.0 P1.7 16 9 C8051F410/1/2/3 28 27 26 25 24 23 GND RST / C2CK V RTC-BACKUP XTAL4 XTAL3 GND V DD V REGIN 1 2 3 4 5 6 22 P0.6 / CNVSTR P2.7 / C2D P2.2 P2.1 P2.0 P0.7 VIO 21 20 19 P0.5 / RX P0.4 / TX P0.3 P0.2 P0.1 / IDAC1 P0.0 / IDAC0 P1.7 C8051F411/3 Top View 18 17 16 GND 7 15 10 11 12 13 P1.5 P1.3 P1.4 P1.0 / XTAL1 P1.1 / XTAL2 Figure 4.2. QFN-28 Pinout Diagram (Top View) P1.2 / VREF Rev. 1.0 P1.6 14 8 9 45 C8051F410/1/2/3 D D1 Table 4.2. LQFP-32 Package Dimensions MIN 0.05 1.35 0.30 0.45 MM TYP 1.40 0.37 9.00 7.00 0.80 9.00 7.00 0.60 MAX 1.60 0.15 1.45 0.45 0.75 E1 E 32 A A1 A2 b D D1 e E E1 L PIN 1 IDENTIFIER 1 A2 A L b A1 e Figure 4.3. LQFP-32 Package Diagram 46 Rev. 1.0 C8051F410/1/2/3 Bottom View 10 12 13 11 14 8 9 L 7 Table 4.3. QFN-28 Package Dimensions Min 0.80 0 0 0.18 2.90 2.90 0.45 0.09 MM Typ 0.90 0.02 0.65 0.25 0.23 5.00 3.15 5.00 3.15 0.5 0.55 28 7 7 0.435 0.435 0.18 0.18 Max 1.00 0.05 1.00 0.30 3.35 3.35 0.65 - 15 D2 D2 2 E2 R 19 20 DETAIL 1 28 27 26 25 24 23 22 21 16 17 18 6xe E A1 A 6 5 4 e b 2 1 6xe D Side View A2 A3 e DETAIL 1 AA BB Figure 4.4. QFN-28 Package Drawing DD CC E2 2 3 A A1 A2 A3 b D D2 E E2 e L N ND NE R AA BB CC DD Rev. 1.0 47 C8051F410/1/2/3 Top View 0.50 mm 0.20 mm 0.20 mm 0.30 mm 0.85 mm 0.50 mm D2 0.35 mm 0.50 mm 0.20 mm b 0.10 mm L E2 0.20 mm 0.30 mm e 0.50 mm 0.35 mm 0.85 mm 0.10 mm E Figure 4.5. Typical QFN-28 Landing Diagram 48 Rev. 1.0 D C8051F410/1/2/3 Top View 0.20 mm 0.50 mm 0.20 mm 0.30 mm 0.85 mm 0.50 mm 0.60 mm 0.60 mm 0.70 mm 0.30 mm 0.20 mm 0.40 mm D2 0.35 mm 0.50 mm 0.20 mm b 0.10 mm L e E2 0.20 mm 0.30 mm 0.50 mm 0.35 mm 0.85 mm 0.10 mm E Figure 4.6. Typical QFN-28 Solder Paste Mask Rev. 1.0 D 49 C8051F410/1/2/3 NOTES: 50 Rev. 1.0 C8051F410/1/2/3 5. 12-Bit ADC (ADC0) The ADC0 subsystem for the C8051F41x consists of an analog multiplexer (AMUX0) with 27 total input selections, and a 200 ksps, 12-bit successive-approximation-register ADC with integrated track-and-hold, programmable window detector, and hardware accumulator. The ADC0 subsystem has a special Burst Mode which can automatically enable ADC0, capture and accumulate samples, then place ADC0 in a low power shutdown mode without CPU intervention. The AMUX0, data conversion modes, and window detector are all configurable under software control via the Special Function Registers shown in Figure 5.1. ADC0 inputs are single-ended and may be configured to measure P0.0-P2.7, the Temperature Sensor output, VDD, or GND with respect to GND. ADC0 is enabled when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1, or when performing conversions in Burst Mode. ADC0 is in low power shutdown when AD0EN is logic 0 and no Burst Mode conversions are taking place. ADC0MX AD0PWR3 AD0PWR2 ADC0MX4 ADC0MX3 ADC0MX2 ADC0MX1 ADC0MX0 ADC0TK AD0PWR1 AD0PWR0 AD0TM1 AD0TM0 AD0TK1 AD0TK0 AD0EN ADC0CN BURSTEN AD0INT AD0BUSY AD0WINT AD0LJST AD0CM1 AD0CM0 00 01 10 11 P0.0 Start Conversion SYSCLK Burst Mode Logic FCLK VDD Start Conversion AD0BUSY (W) Timer 3 Overflow CNVSTR Input Timer 2 Overflow AD0POST P2.7 VDD Temp Sensor AD0TM1:0 AD0PRE FCLK REF P2.3-P2.6 available on ‘F410/2 ADC0H P1.7 P2.0 12-Bit SAR ADC0L P0.7 P1.0 Burst Mode Oscillator 25 MHz Max 27-to-1 AMUX ADC Accumulator AD0WINT Window Compare Logic AD0SC0 AD0RPT1 AD0RPT0 AD0SC4 AD0SC3 AD0SC2 AD0SC1 GND 32 ADC0LTH ADC0LTL ADC0GTH ADC0GTL ADC0CF Figure 5.1. ADC0 Functional Block Diagram 5.1. Analog Multiplexer AMUX0 selects the input channel to the ADC. Any of the following may be selected as an input: P0.0-P2.7, the on-chip temperature sensor, the core power supply (VDD), or ground (GND). ADC0 is single-ended and all signals measured are with respect to GND. The ADC0 input channels are selected using the ADC0MX register as described in SFR Definition 5.1. Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be configured as analog inputs and should be skipped by the Digital Crossbar. To configure a Port pin for analog input, set to ‘0’ the corresponding bit in register PnMDIN (for n = 0,1,2) and write a ‘1’ in the corresponding Port Latch register Pn (for n = 0,1,2). To force the Crossbar to skip a Port pin, set to ‘1’ the corresponding bit in register PnSKIP (for n = 0,1,2). See Section “18. Port Input/Output” on page 147 for more Port I/O configuration details. Rev. 1.0 51 C8051F410/1/2/3 5.2. Temperature Sensor The typical temperature sensor transfer function is shown in Figure 5.2. The output voltage (VTEMP) is the positive ADC input when the temperature sensor is selected by bits AD0MX4-0 in register ADC0MX. (Volts) 1.000 0.900 0.800 VTEMP = SLOPE(TEMPC) + Offset 0.700 0.600 0.500 -50 0 50 100 (Celsius) Figure 5.2. Typical Temperature Sensor Transfer Function 5.3. ADC0 Operation In a typical system, ADC0 is configured using the following steps: Step 1. Step 2. Step 3. Step 4. Step 5. Step 6. Step 7. Step 8. Choose the start of conversion source. Choose Normal Mode or Burst Mode operation. If Burst Mode, choose the ADC0 Idle Power State and set the Power-Up Time. Choose the tracking mode. Note that Pre-Tracking Mode can only be used with Normal Mode. Calculate required settling time and set the post convert-start tracking time using the AD0TK bits. Choose the repeat count. Choose the output word justification (Right-Justified or Left-Justified). Enable or disable the End of Conversion and Window Comparator Interrupts. 52 Rev. 1.0 C8051F410/1/2/3 5.3.1. Starting a Conversion A conversion can be initiated in one of four ways, depending on the programmed states of the ADC0 Start of Conversion Mode bits (AD0CM1-0) in register ADC0CN. Conversions may be initiated by one of the following: • • • • Writing a ‘1’ to the AD0BUSY bit of register ADC0CN A Timer 3 overflow (i.e., timed continuous conversions) A rising edge on the CNVSTR input signal (pin P0.6) A Timer 2 overflow (i.e., timed continuous conversions) Writing a ‘1’ to AD0BUSY provides software control of ADC0 whereby conversions are performed "ondemand.” During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conversion is complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt flag (AD0INT). Note: When polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT) should be used. Converted data is available in the ADC0 data registers, ADC0H:ADC0L, when bit AD0INT is logic 1. Note that when Timer 2 or Timer 3 overflows are used as the conversion source, Low Byte overflows are used if Timer 2/3 is in 8-bit mode; High byte overflows are used if Timer 2/3 is in 16-bit mode. See Section “24. Timers” on page 231 for timer configuration. Important Note About Using CNVSTR: The CNVSTR input pin also functions as Port Pin P0.6. When the CNVSTR input is used as the ADC0 conversion source, Port Pin P0.6 should be skipped by the Digital Crossbar. To configure the Crossbar to skip P0.6, set bit 6 in the P0SKIP register to logic 1. See Section “18. Port Input/Output” on page 147 for details on Port I/O configuration. 5.3.2. Tracking Modes According to Table 5.3 and Table 5.4, each ADC0 conversion must be preceded by a minimum tracking time for the converted result to be accurate. ADC0 has three tracking modes: Pre-Tracking, Post-Tracking, and Dual-Tracking. Pre-Tracking Mode provides the minimum delay between the convert start signal and end of conversion by tracking continuously before the convert start signal. This mode requires software management in order to meet minimum tracking requirements. In Post-Tracking Mode, a programmable tracking time starts after the convert start signal and is managed by hardware. Dual-Tracking Mode maximizes tracking time by tracking before and after the convert start signal. Figure 5.3 shows examples of the three tracking modes. Pre-Tracking Mode is selected when AD0TM is set to 10b. Conversions are started immediately following the convert start signal. ADC0 is tracking continuously when not performing a conversion. Software must allow at least the minimum tracking time between each end of conversion and the next convert start signal. The minimum tracking time must also be met prior to the first convert start signal after ADC0 is enabled. Post-Tracking Mode is selected when AD0TM is set to 01b. A programmable tracking time based on AD0TK is started immediately following the convert start signal. Conversions are started after the programmed tracking time ends. After a conversion is complete, ADC0 does not track the input. Rather, the sampling capacitor remains disconnected from the input making the input pin high-impedance until the next convert start signal. Dual-Tracking Mode is selected when AD0TM is set to 11b. A programmable tracking time based on AD0TK is started immediately following the convert start signal. Conversions are started after the programmed tracking time ends. After a conversion is complete, ADC0 tracks continuously until the next conversion is started. Rev. 1.0 53 C8051F410/1/2/3 Depending on the output connected to the ADC input, additional tracking time, more than is specified in Table 5.3 and Table 5.4, may be required after changing MUX settings. See the settling time requirements described in Section “5.3.6. Settling Time Requirements” on page 58. Convert Start Pre-Tracking AD0TM = 10 Post-Tracking AD0TM= 01 Dual-Tracking AD0TM = 11 Track Convert Track Convert ... Idle Track Convert Idle Track Convert.. Track Track Convert Track Track Convert.. Figure 5.3. ADC0 Tracking Modes 5.3.3. Timing ADC0 has a maximum conversion speed specified in Table 5.3 and Table 5.4. ADC0 is clocked from the ADC0 Subsystem Clock (FCLK). The source of FCLK is selected based on the BURSTEN bit. When BURSTEN is logic 0, FCLK is derived from the current system clock. When BURSTEN is logic 1, FCLK is derived from the Burst Mode Oscillator, an independent clock source with a maximum frequency of 25 MHz. When ADC0 is performing a conversion, it requires a clock source that is typically slower than FCLK. The ADC0 SAR conversion clock (SAR clock) is a divided version of FCLK. The divide ratio can be configured using the AD0SC bits in the ADC0CF register. The maximum SAR clock frequency is listed in Table 5.3 and Table 5.4. ADC0 can be in one of three states at any given time: tracking, converting, or idle. Tracking time depends on the tracking mode selected. For Pre-Tracking Mode, tracking is managed by software and ADC0 starts conversions immediately following the convert start signal. For Post-Tracking and Dual-Tracking Modes, the tracking time after the convert start signal is equal to the value determined by the AD0TK bits plus 2 FCLK cycles. Tracking is immediately followed by a conversion. The ADC0 conversion time is always 13 SAR clock cycles plus an additional 2 FCLK cycles to start and complete a conversion. Figure 5.4 shows timing diagrams for a conversion in Pre-Tracking Mode and tracking plus conversion in Post-Tracking or Dual-Tracking Mode. In this example, repeat count is set to one. 54 Rev. 1.0 C8051F410/1/2/3 Convert Start Pre-Tracking Mode Time ADC0 State AD0INT Flag F S1 S2 ... Convert S12 S13 F Post-Tracking or Dual-Tracking Modes (AD0TK = ‘00') Time ADC0 State AD0INT Flag Key F Sn Equal to one period of FCLK. Each Sn is equal to one period of the SAR clock. F S1 S2 FF S1 S2 ... Convert S12 S13 F Track Figure 5.4. 12-Bit ADC Tracking Mode Example Rev. 1.0 55 C8051F410/1/2/3 5.3.4. Burst Mode Burst Mode is a power saving feature that allows ADC0 to remain in a low power state between conversions. When Burst Mode is enabled, ADC0 wakes from a low power state, accumulates 1, 4, 8, or 16 samples using an internal Burst Mode clock (approximately 25 MHz), then re-enters a low power state. Since the Burst Mode clock is independent of the system clock, ADC0 can perform multiple conversions then enter a low power state within a single system clock cycle, even if the system clock is slow (e.g. 32.768 kHz), or suspended. Burst Mode is enabled by setting BURSTEN to logic 1. When in Burst Mode, AD0EN controls the ADC0 idle power state (i.e. the state ADC0 enters when not tracking or performing conversions). If AD0EN is set to logic 0, ADC0 is powered down after each burst. If AD0EN is set to logic 1, ADC0 remains enabled after each burst. On each convert start signal, ADC0 is awakened from its Idle Power State. If ADC0 is powered down, it will automatically power up and wait the programmable Power-Up Time controlled by the AD0PWR bits. Otherwise, ADC0 will start tracking and converting immediately. Figure 5.5 shows an example of Burst Mode Operation with a slow system clock and a repeat count of 4. Important Note: When Burst Mode is enabled, only Post-Tracking and Dual-Tracking modes can be used. When Burst Mode is enabled, a single convert start will initiate a number of conversions equal to the repeat count. When Burst Mode is disabled, a convert start is required to initiate each conversion. In both modes, the ADC0 End of Conversion Interrupt Flag (AD0INT) will be set after “repeat count” conversions have been accumulated. Similarly, the Window Comparator will not compare the result to the greater-than and less-than registers until “repeat count” conversions have been accumulated. Note: When using Burst Mode, care must be taken to issue a convert start signal no faster than once every four SYSCLK periods. This includes external convert start signals. S y stem C loc k C on v ert S ta rt P o st-T ra ckin g AD 0TM = 01 AD0EN = 0 D u a l-T ra ckin g AD 0TM = 11 AD0EN = 0 P o w e re d D ow n P o w e re d D ow n P o w e r-U p a nd Idle P o w e r-U p a n d T ra c k AD 0PW R T C T C T C T C P o w e re d D ow n P o w e re d D ow n P ow e r-U p a n d Id le P ow e r-U p an d T ra ck T C .. T C T C T C T C T C .. P o st-T ra ckin g AD 0TM = 01 AD0EN = 1 D u a l-T ra ckin g AD 0TM = 11 AD0EN = 1 Id le T C T C T C T C Id le T C T C T C .. T ra ck T C T C T C T C T ra ck T C T C T C .. T = T ra ck in g C = C o n ve rtin g Figure 5.5. 12-Bit ADC Burst Mode Example with Repeat Count Set to 4 56 Rev. 1.0 C8051F410/1/2/3 5.3.5. Output Conversion Code The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code. When the repeat count is set to 1, conversion codes are represented in 12-bit unsigned integer format and the output conversion code is updated after each conversion. Inputs are measured from ‘0’ to VREF x 4095/4096. Data can be right-justified or left-justified, depending on the setting of the AD0LJST bit (ADC0CN.2). Unused bits in the ADC0H and ADC0L registers are set to ‘0’. Example codes are shown in Table 5.1 for both right-justified and left-justified data. Table 5.1. ADC0 Examples of Right- and Left-Justified Samples Input Voltage VREF x 4095/4096 VREF x 2048/4096 VREF x 2047/4096 0 Right-Justified ADC0H:ADC0L (AD0LJST = 0) 0x0FFF 0x0800 0x07FF 0x0000 Left-Justified ADC0H:ADC0L (AD0LJST = 1) 0xFFF0 0x8000 0x7FF0 0x0000 When the ADC0 Repeat Count is greater than 1, the output conversion code represents the accumulated result of the conversions performed and is updated after the last conversion in the series is finished. Sets of 4, 8, or 16 consecutive samples can be accumulated and represented in unsigned integer format. The repeat count can be selected using the AD0RPT bits in the ADC0CF register. The value must be rightjustified (AD0LJST = “0”), and unused bits in the ADC0H and ADC0L registers are set to '0'. The example in Table 5.2 shows the right-justified result for various input voltages and repeat counts. Notice that accumulating 2n samples is equivalent to left-shifting by n bit positions when all samples returned from the ADC have the same value. Table 5.2. ADC0 Repeat Count Examples at Various Input Voltages Input Voltage VREF x 4095/4096 VREF x 2048/4096 VREF x 2047/4096 0 Repeat Count = 4 0x3FFC 0x2000 0x1FFC 0x0000 Repeat Count = 8 0x7FF8 0x4000 0x3FF8 0x0000 Repeat Count = 16 0xFFF0 0x8000 0x7FF0 0x0000 Rev. 1.0 57 C8051F410/1/2/3 5.3.6. Settling Time Requirements A minimum tracking time is required before an accurate conversion can be performed. This tracking time is determined by the AMUX0 resistance, the ADC0 sampling capacitance, any external source resistance, and the accuracy required for the conversion. Figure 5.6 shows the equivalent ADC0 input circuit. The required ADC0 settling time for a given settling accuracy (SA) may be approximated by Equation 5.1. When measuring the Temperature Sensor output or VDD with respect to GND, RTOTAL reduces to RMUX. See Table 5.3 and Table 5.4 for ADC0 minimum settling time requirements. 2 t = ln ⎛ ------⎞ × R TOTAL C SAMPLE ⎝ SA⎠ Equation 5.1. ADC0 Settling Time Requirements Where: SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB) t is the required settling time in seconds RTOTAL is the sum of the AMUX0 resistance and any external source resistance. n is the ADC resolution in bits (12). MUX Select n Px.x RMUX = 5 kΩ CSAMPLE = 12 pF RCInput= RMUX * CSAMPLE Figure 5.6. ADC0 Equivalent Input Circuits 58 Rev. 1.0 C8051F410/1/2/3 SFR Definition 5.1. ADC0MX: ADC0 Channel Select R R R R/W Bit4 R/W Bit3 R/W R/W Bit1 R/W Bit0 Reset Value Bit7 Bit6 Bit5 AD0MX Bit2 00011111 SFR Address: 0xBB Bits7-5: Bits4-0: UNUSED. Read = 000b; Write = don’t care. AD0MX4-0: AMUX0 Positive Input Selection AD0MX4-0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 - 11111 ADC0 Input Channel P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3* P2.4* P2.5* P2.6* P2.7 Temp Sensor VDD GND *Note: Only applies to C8051F410/2; selection RESERVED on C8051F411/3 devices. Rev. 1.0 59 C8051F410/1/2/3 SFR Definition 5.2. ADC0CF: ADC0 Configuration R/W Bit7 R/W Bit6 R/W R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Reset Value AD0SC Bit5 AD0RPT Reserved Bit0 11111000 SFR Address: 0xBC Bits7-3: AD0SC4-0: ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from FCLK by the following equation, where AD0SC refers to the 5-bit value held in bits AD0SC4-0. SAR Conversion clock requirements are given in Table 5.3. BURSTEN = 0: FCLK is the current system clock. BURSTEN = 1: FCLK is a maximum of 25 MHz, independent of the current system clock. FCLK AD0SC = ------------------- – 1 * CLK SAR *Note: Round the result up. or FCLK CLK SAR = ---------------------------AD 0 SC + 1 Bits2-1: AD0RPT1-0: ADC0 Repeat Count. Controls the number of conversions taken and accumulated between ADC0 End of Conversion (ADCINT) and ADC0 Window Comparator (ADCWINT) interrupts. A convert start is required for each conversion unless Burst Mode is enabled. In Burst Mode, a single convert start can initiate multiple self-timed conversions. Results in both modes are accumulated in the ADC0H:ADC0L register. When AD0RPT1-0 are set to a value other than '00', the AD0LJST bit in the ADC0CN register must be set to '0' (right justified). 00: 1 conversion is performed. 01: 4 conversions are performed and accumulated. 10: 8 conversions are performed and accumulated. 11: 16 conversions are performed and accumulated. RESERVED. Read = 0b; Must write 0b. Bit0: 60 Rev. 1.0 C8051F410/1/2/3 SFR Definition 5.3. ADC0H: ADC0 Data Word MSB R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 00000000 SFR Address: 0xBE Bits7-0: ADC0 Data Word High-Order Bits. For AD0LJST = 0 and AD0RPT as follows: 00: Bits 3–0 are the upper 4 bits of the accumulated result. Bits 7–4 are 0000b. 01: Bits 5–0 are the upper 6 bits of the accumulated result. Bits 7–6 are 00b. 10: Bits 6–0 are the upper 7 bits of the accumulated result. Bit 7 is 0b. 11: Bits 7–0 are the upper 8 bits of the accumulated result. For AD0LJST = 1 (AD0RPT must be '00'): Bits 7–0 are the most-significant bits of the ADC0 12-bit result. SFR Definition 5.4. ADC0L: ADC0 Data Word LSB R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 00000000 SFR Address: 0xBD Bits7-0: ADC0 Data Word Low-Order Bits. For AD0LJST = 0: Bits 7-0 are the lower 8 bits of the ADC0 accumulated result. For AD0LJST = 1 (AD0RPT must be '00'): Bits 7-4 are the lower 4 bits of the 12-bit result. Bits 3-0 are 0000b. Rev. 1.0 61 C8051F410/1/2/3 SFR Definition 5.5. ADC0CN: ADC0 Control R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 (bit addressable) Reset Value SFR Address: AD0EN BURSTEN AD0INT AD0BUSY AD0WINT AD0LJST AD0CM1 AD0CM0 00000000 0xE8 Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bits1-0: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ADC0 Enabled. ADC0 is active and ready for data conversions. BURSTEN: ADC0 Burst Mode Enable Bit. 0: ADC0 Burst Mode Disabled. 1: ADC0 Burst Mode Enabled. AD0INT: ADC0 Conversion Complete Interrupt Flag. 0: ADC0 has not completed a data conversion since the last time AD0INT was cleared. 1: ADC0 has completed a data conversion. AD0BUSY: ADC0 Busy Bit. Read: 0: ADC0 conversion is complete or a conversion is not currently in progress. AD0INT is set to logic 1 on the falling edge of AD0BUSY. 1: ADC0 conversion is in progress. Write: 0: No Effect. 1: Initiates ADC0 Conversion if AD0CM1-0 = 00b AD0WINT: ADC0 Window Compare Interrupt Flag. This bit must be cleared by software. 0: ADC0 Window Comparison Data match has not occurred since this flag was last cleared. 1: ADC0 Window Comparison Data match has occurred. AD0LJST: ADC0 Left Justify Select 0: Data in ADC0H:ADC0L registers is right justified. 1: Data in ADC0H:ADC0L registers is left justified. This option should not be used with a repeat count greater than 1 (when AD0RPT1-0 is 01b, 10b, or 11b). AD0CM1-0: ADC0 Start of Conversion Mode Select. 00: ADC0 conversion initiated on every write of ‘1’ to AD0BUSY. 01: ADC0 conversion initiated on overflow of Timer 3. 10: ADC0 conversion initiated on rising edge of external CNVSTR. 11: ADC0 conversion initiated on overflow of Timer 2. 62 Rev. 1.0 C8051F410/1/2/3 SFR Definition 5.6. ADC0TK: ADC0 Tracking Mode Select R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W R/W R/W R/W Reset Value AD0PWR Bit3 AD0TM Bit2 Bit1 AD0TK Bit0 (bit addressable) 11111111 SFR Address: 0xBA Bits7-4: AD0PWR3-0: ADC0 Burst Power-Up Time. For BURSTEN = 0: ADC0 power state controlled by AD0EN. For BURSTEN = 1 and AD0EN = 1; ADC0 remains enabled and does not enter the low power state. For BURSTEN = 1 and AD0EN = 0: ADC0 enters the low power state as specified in Table 5.3 and Table 5.4 and is enabled after each convert start signal. The Power Up time is programmed according to the following equation: Tstartup AD0PWR = ---------------------- – 1 200 ns Bits3-2: or Tstartup = ( AD0PWR + 1 ) 200 n s Bits1-0: AD0TM1-0: ADC0 Tracking Mode Select Bits. 00: Reserved. 01: ADC0 is configured to Post-Tracking Mode. 10: ADC0 is configured to Pre-Tracking Mode. 11: ADC0 is configured to Dual-Tracking Mode (default). AD0TK1-0: ADC0 Post-Track Time. Post-Tracking time is controlled by AD0TK as follows: 00: Post-Tracking time is equal to 2 SAR clock cycles + 2 FCLK cycles. 01: Post-Tracking time is equal to 4 SAR clock cycles + 2 FCLK cycles. 10: Post-Tracking time is equal to 8 SAR clock cycles + 2 FCLK cycles. 11: Post-Tracking time is equal to 16 SAR clock cycles + 2 FCLK cycles. 5.4. Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-programmed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system response times. The window detector interrupt flag (AD0WINT in register ADC0CN) can also be used in polled mode. The ADC0 Greater-Than (ADC0GTH, ADC0GTL) and Less-Than (ADC0LTH, ADC0LTL) registers hold the comparison values. The window detector flag can be programmed to indicate when measured data is inside or outside of the user-programmed limits, depending on the contents of the ADC0 Less-Than and ADC0 Greater-Than registers. Rev. 1.0 63 C8051F410/1/2/3 SFR Definition 5.7. ADC0GTH: ADC0 Greater-Than Data High Byte R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 11111111 SFR Address: 0xC4 Bits7-0: High byte of ADC0 Greater-Than Data Word. SFR Definition 5.8. ADC0GTL: ADC0 Greater-Than Data Low Byte R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 11111111 SFR Address: 0xC3 Bits7-0: Low byte of ADC0 Greater-Than Data Word. 64 Rev. 1.0 C8051F410/1/2/3 SFR Definition 5.9. ADC0LTH: ADC0 Less-Than Data High Byte R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 00000000 SFR Address: 0xC6 Bits7-0: High byte of ADC0 Less-Than Data Word. SFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 00000000 SFR Address: 0xC5 Bits7-0: Low byte of ADC0 Less-Than Data Word. Rev. 1.0 65 C8051F410/1/2/3 5.4.1. Window Detector In Single-Ended Mode Figure 5.7 shows two example window comparisons for right-justified data with ADC0LTH:ADC0LTL = 0x0200 (512d) and ADC0GTH:ADC0GTL = 0x0100 (256d). The input voltage can range from ‘0’ to VREF x (4095/4096) with respect to GND, and is represented by a 12-bit unsigned integer value. The repeat count is set to one. In the left example, an AD0WINT interrupt will be generated if the ADC0 conversion word (ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL (if 0x0100 < ADC0H:ADC0L < 0x0200). In the right example, and AD0WINT interrupt will be generated if the ADC0 conversion word is outside of the range defined by the ADC0GT and ADC0LT registers (if ADC0H:ADC0L < 0x0100 or ADC0H:ADC0L > 0x0200). Figure 5.8 shows an example using left-justified data with the same comparison values. ADC0H:ADC0L Input Voltage (Px.x - GND) VREF x (4095/4096) 0x0FFF AD0WINT not affected 0x0201 VREF x (512/4096) 0x0200 0x01FF 0x0101 0x0100 0x00FF ADC0LTH:ADC0LTL AD0WINT=1 VREF x (256/4096) ADC0GTH:ADC0GTL VREF x (256/4096) VREF x (512/4096) Input Voltage (Px.x - GND) VREF x (4095/ 4096) ADC0H:ADC0L 0x0FFF AD0WINT=1 0x0201 0x0200 0x01FF 0x0101 0x0100 0x00FF ADC0GTH:ADC0GTL AD0WINT not affected ADC0LTH:ADC0LTL AD0WINT not affected 0 0x0000 0 0x0000 AD0WINT=1 Figure 5.7. ADC Window Compare Example: Right-Justified Single-Ended Data ADC0H:ADC0L Input Voltage (Px.x - GND) VREF x (4095/4096) 0xFFF0 AD0WINT not affected 0x2010 VREF x (512/4096) 0x2000 0x1FF0 0x1010 0x1000 0x0FF0 ADC0LTH:ADC0LTL AD0WINT=1 VREF x (256/4096) ADC0GTH:ADC0GTL VREF x (256/4096) VREF x (512/4096) Input Voltage (Px.x - GND) VREF x (4095/4096) ADC0H:ADC0L 0xFFF0 AD0WINT=1 0x2010 0x2000 0x1FF0 0x1010 0x1000 0x0FF0 ADC0GTH:ADC0GTL AD0WINT not affected ADC0LTH:ADC0LTL AD0WINT not affected 0 0x0000 0 0x0000 AD0WINT=1 Figure 5.8. ADC Window Compare Example: Left-Justified Single-Ended Data 66 Rev. 1.0 C8051F410/1/2/3 Table 5.3. ADC0 Electrical Characteristics (VDD = 2.5 V, VREF = 2.2 V) VDD = 2.5 V, VREF = 2.2 V (REFSL=0), –40 to +85 °C unless otherwise specified. Typical values are given at 25 ºC. Parameter DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale Error Conditions Min Typ 12 Max Units bits — Guaranteed Monotonic — — — Regular Mode (BURSTEN = '0') Burst Mode (BURSTEN = '0') Up to the 5th harmonic 66 60 — — Regular Mode (BURSTEN = '0') — — 1 — 0 — — — — (Temp = 0 °C) — — — — ±3 ±3 69 63 –77 –94 — 13 — — — 12 ±0.2 2.95 ±73 900 ±17 ±1 ±1 ±10 ±10 — — — — 3 — — 200 VREF — — — — — — LSB LSB LSB LSB Dynamic Performance (10 kHz sine-wave Single-ended input, 0 to 1 dB below Full Scale, 200 ksps) Signal-to-Noise Plus Distortion Total Harmonic Distortion Spurious-Free Dynamic Range dB dB dB MHz clocks µs ksps V pF °C mV/°C µV/°C mV mV Conversion Rate SAR Conversion Clock Conversion Time in SAR Clocks1 Track/Hold Acquisition Time2 Throughput Rate Analog Inputs Input Voltage Range Input Capacitance Temperature Sensor Linearity3,4 Slope4 Slope Error3 Offset4 Offset Error 3 Power Specifications Power Supply Current (VDD supplied to ADC0) Burst Mode (Idle) Power Supply Rejection Operating Mode, 200 ksps — — — 680 100 1 1000 — — µA µA mV/V Notes: 1. An additional 2 FCLK cycles are required to start and complete a conversion. 2. Additional tracking time may be required depending on the output impedance connected to the ADC input. See Section “5.3.6. Settling Time Requirements” on page 58. 3. Represents one standard deviation from the mean. 4. Includes ADC offset, gain, and linearity variations. Rev. 1.0 67 C8051F410/1/2/3 Table 5.4. ADC0 Electrical Characteristics (VDD = 2.1 V, VREF = 1.5 V) VDD = 2.1 V, VREF = 1.5 V (REFSL = 0), –40 to +85 °C unless otherwise specified. Typical values are given at 25 ºC. Parameter DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale Error Conditions Min Typ 12 Max Units bits — Guaranteed Monotonic — — — Regular Mode (BURSTEN = '0') Burst Mode (BURSTEN = '0') Up to the 5th harmonic 66 60 — — Regular Mode (BURSTEN = '0') — — 1 — 0 — — — — — ±3 ±3 68 62 –75 –90 — 13 — — — 12 ±0.2 2.95 ±73 900 ±17 ±1 ±1 ±10 ±10 — — — — 3 — — 200 VREF — — — — — — LSB LSB LSB LSB Dynamic Performance (10 kHz sine-wave Single-ended input, 0 to 1 dB below Full Scale, 200 ksps) Signal-to-Noise Plus Distortion Total Harmonic Distortion Spurious-Free Dynamic Range dB dB dB MHz clocks µs ksps V pF °C mV/°C µV/°C mV mV Conversion Rate SAR Conversion Clock Conversion Time in SAR Clocks1 Track/Hold Acquisition Time2 Throughput Rate Analog Inputs Input Voltage Range Input Capacitance Temperature Sensor Linearity3,4 Slope4 Slope Error Offset Offset Error3 3 — (Temp = 0 °C) — — Power Specifications Power Supply Current (VDD supOperating Mode, 200 ksps plied to ADC0) Burst Mode (Idle) Power Supply Rejection — — — 650 100 1 1000 — — µA µA mV/V Notes: 1. An additional 2 FCLK cycles are required to start and complete a conversion. 2. Additional tracking time may be required depending on the output impedance connected to the ADC input. See Section “5.3.6. Settling Time Requirements” on page 58. 3. Represents one standard deviation from the mean. 4. Includes ADC offset, gain, and linearity variations. 68 Rev. 1.0 C8051F410/1/2/3 6. 12-Bit Current Mode DACs (IDA0 and IDA1) The C8051F41x devices include two 12-bit current-mode Digital-to-Analog Converters (IDACs). The maximum current output of the IDACs can be adjusted for four different current settings; 0.25 mA, 0.5 mA, 1 mA, and 2 mA. The IDACs can be individually enabled or disabled using the enable bits in the corresponding IDAC Control Register (IDA0CN or IDA1CN). When both IDACs are enabled, their outputs may be routed to individual pins or merged onto a single pin. An internal bandgap bias generator is used to generate a reference current for the IDACs whenever they are enabled. IDAC updates can be performed ondemand, scheduled on a Timer overflow, or synchronized with an external pin edge. Figure 6.1 shows a block diagram of the IDAC circuitry. Timer 0 Timer 1 Timer 2 Timer 3 IDAnH IDAnCN IDAnEN IDAnCM2 IDAnCM1 IDAnCM0 IDAnRJST IDAnOMD1 IDAnOMD0 IDAnH 8 Latch 12 CNVSTR IDAn IDAn Output IDAnL 4 Figure 6.1. IDAC Functional Block Diagram 6.1. IDAC Output Scheduling A flexible output update mechanism allows for seamless full-scale changes and supports jitter-free updates for waveform generation. Three update modes are provided, allowing IDAC output updates on a write to the IDAC’s data register, on a Timer overflow, or on an external pin edge. 6.1.1. Update Output On-Demand In its default mode (IDAnCN.[6:4] = ‘111’) the IDAC output is updated “on-demand” with a write to the data register high byte (IDAnH). It is important to note that in this mode, writes to the data register low byte (IDAnL) are held and have no effect on the IDAn output until a write to IDAnH takes place. Since data from both the high and low bytes of the data register are immediately latched to IDAn after a write to IDAnH, the write sequence when writing a full 12-bit word to the IDAC data registers should be IDAnL followed by IDAnH. When the data word is left justified, the IDAC can be used in 8-bit mode by initializing IDAnL to the desired value (typically 0x00), and writing data only to IDA0H. Rev. 1.0 69 C8051F410/1/2/3 6.1.2. Update Output Based on Timer Overflow The IDAC output update can be scheduled on a Timer overflow. This feature is useful in systems where the IDAC is used to generate a waveform of a defined sampling rate, by eliminating the effects of variable interrupt latency and instruction execution on the timing of the IDAC output. When the IDAnCM bits (IDAnCN.[6:4]) are set to ‘000’, ‘001’, ‘010’ or ‘011’, writes to both IDAC data registers (IDAnL and IDAnH) are held until an associated Timer overflow event (Timer 0, Timer 1, Timer 2 or Timer 3, respectively) occurs, at which time the IDAnH:IDAnL contents are copied to the IDAC input latch, allowing the IDAC output to change to the new value. When updates are scheduled based on Timer 2 or 3, updates occur on low-byte overflows if Timer 2 or 3 is in 8-bit mode and high-byte overflows if Timer 2 or 3 is in 16-bit mode. 6.1.3. Update Output Based on CNVSTR Edge The IDAC output can also be configured to update on a rising edge, falling edge, or both edges of the external CNVSTR signal. When the IDAnCM bits (IDAnCN.[6:4]) are set to ‘100’, ‘101’, or ‘110’, writes to the IDAC data registers (IDAnL and IDAnH) are held until an edge occurs on the CNVSTR input pin. The particular setting of the IDAnCM bits determines whether the IDAC output is updated on rising, falling, or both edges of CNVSTR. When a corresponding edge occurs, the IDAnH:IDAnL contents are copied to the IDAC input latch, allowing the IDAC output to change to the new value. 6.2. IDAC Output Mapping The IDAC data word can be Left Justified or Right Justified as shown in Figure 6.2. When Left Justified, the 8 MSBs of the data word (D11-D4) are mapped to bits 7-0 of the IDAnH register and the 4 LSBs of the data word (D3-D0) are mapped to bits 7-4 of the IDAnL register. When Right Justified, the 4 MSBs of the data word (D11-D8) are mapped to bits 3-0 of the IDAnH register and the 8 LSBs of the data word (D7-D0) are mapped to bits 7-0 of the IDAnL register. The IDAC data word justification is selected using the IDAnRJST bit (IDAnCN.2). The full-scale output current of the IDAC is selected using the IDAnOMD bits (IDAnCN[1:0]). By default, the IDAC is set to a full-scale output current of 2 mA. The IDAnOMD bits can also be configured to provide full-scale output currents of 0.25 mA, 0.5 mA, or 1 mA. Left Justified Data (IDAnRJST = 0): IDAnH D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 IDAnL D0 Right Justified Data (IDAnRJST = 1): IDAnH D11 D10 D9 D8 D7 D6 D5 IDAnL D4 D3 D2 D1 D0 IDAn Data Word Output Current vs IDAnOMD bit setting (D11 - D0) ‘11’ (2 mA) ‘10’ (1 mA) ‘01’ (0.5 mA) ‘00’ (0.25 mA) 0x000 0 mA 0 mA 0 mA 0 mA 0x001 1/4096 x 2 mA 1/4096 x 1 mA 1/4096 x 0.5 mA 1/4096 x 0.25 mA 0x800 2048/4096 x 2 mA 2048/4096 x 1 mA 2048/4096 x 0.5 mA 2048/4096 x 0.25 mA 0xFFF 4095/4096 x 2 mA 4095/4096 x 1 mA 4095/4096 x 0.5 mA 4095/4096 x 0.25 mA Figure 6.2. IDAC Data Word Mapping 70 Rev. 1.0 C8051F410/1/2/3 SFR Definition 6.1. IDA0CN: IDA0 Control R/W R/W Bit6 R/W R/W Bit4 R/W R R/W Bit1 R/W Bit0 SFR Address: 0xB9 Reset Value IDA0EN Bit7 IDA0CM Bit5 Bit3 IDA0RJST Bit2 IDA0OMD 01110011 Bit 7: IDA0EN: IDA0 Enable Bit. 0: IDA0 Disabled. 1: IDA0 Enabled. Bits 6–4: IDA0CM[2:0]: IDA0 Update Source Select Bits. 000: DAC output updates on Timer 0 overflow. 001: DAC output updates on Timer 1 overflow. 010: DAC output updates on Timer 2 overflow. 011: DAC output updates on Timer 3 overflow. 100: DAC output updates on rising edge of CNVSTR. 101: DAC output updates on falling edge of CNVSTR. 110: DAC output updates on any edge of CNVSTR. 111: DAC output updates on write to IDA0H. Bit 3: Reserved. Read = 0b, Write = 0b. Bit 2: IDA0RJST: IDA0 Right Justify Select Bit. 0: IDA0 data in IDA0H:IDA0L is left justified. 1: IDA0 data in IDA0H:IDA0L is right justified. Bits 1:0: IDA0OMD[1:0]: IDA0 Output Mode Select Bits. 00: 0.25 mA full-scale output current. 01: 0.5 mA full-scale output current. 10: 1.0 mA full-scale output current. 11: 2.0 mA full-scale output current. SFR Definition 6.2. IDA0H: IDA0 Data High Byte R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 SFR Address: 0x97 Reset Value 00000000 Bits 7–0: IDA0 Data Word High-Order Bits. For IDA0RJST = 0: Bits 7-0 hold the most significant 8-bits of the 12-bit IDA0 Data Word. For IDA0RJST = 1: Bits 3-0 hold the most significant 4-bits of the 12-bit IDA0 Data Word. Bits 7-4 are 0000b. Rev. 1.0 71 C8051F410/1/2/3 SFR Definition 6.3. IDA0L: IDA0 Data Low Byte R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 SFR Address: 0x96 Reset Value 00000000 Bits 7–0: IDA0 Data Word Low-Order Bits. For IDA0RJST = 0: Bits 7-4 hold the least significant 4-bits of the 12-bit IDA0 Data Word. Bits 3–0 are 0000b. For IDA0RJST = 1: Bits 7–0 hold the least significant 8-bits of the 12-bit IDA0 Data Word. SFR Definition 6.4. IDA1CN: IDA1 Control R/W R/W Bit6 R/W R/W Bit4 R/W R R/W Bit1 R/W Bit0 SFR Address: 0xB5 Reset Value IDA1EN Bit7 IDA1CM Bit5 Bit3 IDA1RJST Bit2 IDA1OMD 01110011 Bit 7: IDA1EN: IDA0 Enable Bit. 0: IDA1 Disabled. 1: IDA1 Enabled. Bits 6–4: IDA1CM[2:0]: IDA1 Update Source Select Bits. 000: DAC output updates on Timer 0 overflow. 001: DAC output updates on Timer 1 overflow. 010: DAC output updates on Timer 2 overflow. 011: DAC output updates on Timer 3 overflow. 100: DAC output updates on rising edge of CNVSTR. 101: DAC output updates on falling edge of CNVSTR. 110: DAC output updates on any edge of CNVSTR. 111: DAC output updates on write to IDA1H. Bit 3: Reserved. Read = 0b, Write = 0b. Bit 2: IDA1RJST: IDA1 Right Justify Select Bit. 0: IDA1 data in IDA1H:IDA1L is left justified. 1: IDA1 data in IDA1H:IDA1L is right justified. Bits 1–0: IDA1OMD[1:0]: IDA1 Output Mode Select Bits. 00: 0.25 mA full-scale output current. 01: 0.5 mA full-scale output current. 10: 1.0 mA full-scale output current. 11: 2.0 mA full-scale output current. 72 Rev. 1.0 C8051F410/1/2/3 SFR Definition 6.5. IDA1H: IDA0 Data High Byte R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 SFR Address: 0xF5 Reset Value 00000000 Bits 7–0: IDA1 Data Word High-Order Bits. For IDA0RJST = 0: Bits 7-0 hold the most significant 8-bits of the 12-bit IDA1 Data Word. For IDA0RJST = 1: Bits 3-0 hold the most significant 4-bits of the 12-bit IDA1 Data Word. Bits 7–4 are 0000b. SFR Definition 6.6. IDA1L: IDA1 Data Low Byte R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 SFR Address: 0xF4 Reset Value 00000000 Bits 7–0: IDA1 Data Word Low-Order Bits. For IDA0RJST = 0: Bits 7-4 hold the least significant 4-bits of the 12-bit IDA1 Data Word. Bits 3–0 are 0000b. For IDA0RJST = 1: Bits 7–0 hold the least significant 8-bits of the 12-bit IDA1 Data Word. 6.3. IDAC External Pin Connections The IDA0 output is connected to P0.0, and the IDA1 output can be connected to P0.0 or P0.1. The output pin for IDA1 is selected using IDAMRG (REF0CN.7). When the enable bits for both IDACs (IDAnEN) are set to ‘0’, the IDAC outputs behave as a normal GPIO pins. When either IDAC’s enable bit is set to ‘1’, the digital output drivers and weak pullup for the selected IDAC pin are automatically disabled, and the pin is connected to the IDAC output. When using the IDACs, the selected IDAC pin(s) should be skipped in the Crossbar by setting the corresponding PnSKIP bits to a ‘1’. Figure 6.3 shows the pin connections for IDA0 and IDA1. When both IDACs are enabled and IDAMRG is set to logic 1, the output of both IDACs is merged onto P0.0. Rev. 1.0 73 C8051F410/1/2/3 IDA0EN IDA0 0 1 P0.0 IDA1EN 1 0 IDA1 0 1 P0.1 IDAMRG Figure 6.3. IDAC Pin Connections 74 Rev. 1.0 C8051F410/1/2/3 Table 6.1. IDAC Electrical Characteristics –40 to +85 °C, VDD = 2.0 V Full-scale output current set to 2 mA unless otherwise specified. Typical values are given at 25 ºC. Parameter Static Performance Resolution Integral Nonlinearity Differential Nonlinearity Output Compliance Range Offset Error Gain Error Gain-Error Tempco VDD Power Supply Rejection Ratio Output Capacitance Conditions Min Typ 12 Max Units bits — Guaranteed Monotonic Guaranteed by Design 2 mA Full Scale Output Current — — — — — — — — 1 mA Full Scale Output Current 0.5 mA Full Scale Output Current 0.25 mA Full Scale Output Current 2 mA Full Scale Output Current 1 mA Full Scale Output Current 0.5 mA Full Scale Output Current 0.25 mA Full Scale Output Current — — — — 0 0.05 320 2 2 10 0.5 0.5 0.5 2.1 1.1 0.6 0.35 ±10 ±1 VDD – 1.2 — 2 — — — — — LSB LSB V LSB % nA/°C µA/V pF µs % % % mA mA mA mA Dynamic Performance Startup Time Gain Variation From 2 mA range Power Consumption Power Supply Current — — Rev. 1.0 75 C8051F410/1/2/3 NOTES: 76 Rev. 1.0 C8051F410/1/2/3 7. Voltage Reference The Voltage reference MUX on C8051F41x devices is configurable to use an externally connected voltage reference, the internal reference voltage generator, or the VDD power supply voltage (see Figure 7.1). The REFSL bit in the Reference Control register (REF0CN) selects the reference source. For an external source or the internal reference, REFSL should be set to ‘0’. To use VDD as the reference source, REFSL should be set to ‘1’. The internal voltage reference circuit consists of a temperature stable bandgap voltage reference generator and a gain-of-two output buffer amplifier. The output voltage is selected between 1.5 V and 2.2 V. The internal voltage reference can be driven out on the VREF pin by setting the REFBE bit in register REF0CN to a ‘1’ (see Figure 7.1). The load seen by the VREF pin must draw less than 200 µA to GND. When using the internal voltage reference, bypass capacitors of 0.1 µF and 4.7 µF are recommended from the VREF pin to GND. If the internal reference is not used, the REFBE bit should be cleared to ‘0’. The BIASE bit enables the internal voltage bias generator, which is used by the ADC, Temperature Sensor, internal oscillators, and IDACs. This bit is forced to logic 1 when any of the aforementioned peripherals are enabled. The bias generator may be enabled manually by writing a ‘1’ to the BIASE bit in register REF0CN; see SFR Definition 7.1 for REF0CN register details. The electrical specifications for the voltage reference circuit are given in Table 7.1. REFLV REFLV Figure 7.1. Voltage Reference Functional Block Diagram Rev. 1.0 77 C8051F410/1/2/3 Important Note About the VREF Pin: Port pin P1.2 is used as the external VREF input and as an output for the internal VREF. When using either an external voltage reference or the internal reference circuitry, P1.2 should be configured as an analog pin, and skipped by the Digital Crossbar. To configure P1.2 as an analog pin, clear Bit 2 in register P1MDIN to ‘0’ and set Bit 2 in register P1 to '1'. To configure the Crossbar to skip P1.2, set Bit 2 in register P1SKIP to ‘1’. Refer to Section “18. Port Input/Output” on page 147 for complete Port I/O configuration details. The TEMPE bit in register REF0CN enables/disables the temperature sensor. While disabled, the temperature sensor defaults to a high impedance state and any ADC0 measurements performed on the sensor result in meaningless data. SFR Definition 7.1. REF0CN: Reference Control R/W R/W R/W R/W R/W R/W R/W R/W Reset Value IDAMRG Bit7 GF Bit6 ZTCEN Bit5 REFLV Bit4 REFSL Bit3 TEMPE Bit2 BIASE Bit1 REFBE Bit0 00000000 SFR Address: 0xD1 Bit7: IDAMRG: IDAC Output Merge Select. 0: IDA1 Output is P0.1. 1: IDA1 Output is P0.0 (Merged with IDA0 Output). GF. General Purpose Flag. This bit is a general purpose flag for use under software control. ZTCEN: Zero-TempCo Bias Enable Bit. 0: ZeroTC Bias Generator automatically enabled when needed. 1: ZeroTC Bias Generator forced on. REFLV: Voltage Reference Output Level Select. This bit selects the output voltage level for the internal voltage reference. 0: Internal voltage reference set to 1.5 V. 1: Internal voltage reference set to 2.2 V. REFSL: Voltage Reference Select. This bit selects the source for the internal voltage reference. 0: VREF pin used as voltage reference. 1: VDD used as voltage reference. TEMPE: Temperature Sensor Enable Bit. 0: Internal Temperature Sensor off. 1: Internal Temperature Sensor on. BIASE: Internal Analog Bias Generator Enable Bit. 0: Internal Analog Bias Generator automatically enabled when needed. 1: Internal Analog Bias Generator on. REFBE: Internal Reference Buffer Enable Bit. 0: Internal Reference Buffer disabled. 1: Internal Reference Buffer enabled. Internal voltage reference driven on the VREF pin. Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: 78 Rev. 1.0 C8051F410/1/2/3 Table 7.1. Voltage Reference Electrical Characteristics VDD = 2.0 V; –40 to +85 °C unless otherwise specified. Parameter Internal Reference (REFBE = 1) Output Voltage VREF Short-Circuit Current VREF Temperature Coefficient Load Regulation VREF Turn-on Time Conditions 25 °C ambient (REFLV = 0) 25 °C ambient (REFLV = 1), VDD = 2.5 V Min 1.47 2.16 — — Typ 1.5 2.2 3.0 35 10 2.5 55 6.8 144 2 — 5 22 50 Max 1.53 2.24 — — — — — — — — VDD — — — Units V mA ppm/°C ppm/µA ms µs ms µs mV/V V µA µA µA Load = 0 to 200 µA to GND VDD = 2.5 V, VREF = 1.5 V: 4.7 µF tantalum, 0.1 µF ceramic bypass 0.1 µF ceramic bypass VDD = 2.5 V, VREF = 2.2 V: 4.7 µF tantalum, 0.1 µF ceramic bypass 0.1 µF ceramic bypass — — — — — — 0 Power Supply Rejection External Reference (REFBE = 0) Input Voltage Range Input Current Sample Rate = 200 ksps; VREF = 2 V BIASE = ‘1’ — — — Bias Generators ADC Bias Generator Power Consumption (Internal) Rev. 1.0 79 C8051F410/1/2/3 NOTES: 80 Rev. 1.0 C8051F410/1/2/3 8. Voltage Regulator (REG0) C8051F41x devices include an on-chip low dropout voltage regulator (REG0). The input to REG0 at the VREGIN pin can be as high as 5.25 V. The output can be selected by software to 2.1 V or 2.5 V. When enabled, the output of REG0 appears on the VDD pin, powers the microcontroller core, and can be used to power external devices. On reset, REG0 is enabled and can be disabled by software. The input (VREGIN) and output (VDD) of the voltage regulator should both be protected with a large capacitor (4.7 µF + 0.1 µF) to ground. This capacitor will eliminate power spikes and provide any immediate power required by the microcontroller. A settling time associated with the voltage regulator is shown in Table 8.1. REG0 4.7 µF .1 µF VREGIN VDD 4.7 µF .1 µF VDD Figure 8.1. External Capacitors for Voltage Regulator Input/Output If the internal voltage regulator is not used, the VREGIN input should be tied to VDD, as shown in Figure 8.2. VREGIN VDD 4.7 µF .1 µF VDD Figure 8.2. External Capacitors for Voltage Regulator Input/Output Rev. 1.0 81 C8051F410/1/2/3 SFR Definition 8.1. REG0CN: Regulator Control R/W Bit7 R/W Bit6 R R/W R R R R Bit0 SFR Address: 0xC9 Reset Value REGDIS Reserved — Bit5 REG0MD Bit4 — Bit3 — Bit2 — Bit1 DROPOUT 00010000 Bit 7: REGDIS: Voltage Regulator Disable Bit. This bit disables/enables the Voltage Regulator. 0: Voltage Regulator Enabled. 1: Voltage Regulator Disabled. Bit 6: RESERVED. Read = 0b. Must write 0b. Bit 5: UNUSED. Read = 0b. Write = don’t care. Bit 4: REG0MD: Voltage Regulator Mode Select Bit. This bit selects the Voltage Regulator output voltage. 0: Voltage Regulator output is 2.1 V. 1: Voltage Regulator output is 2.5 V (default). Bits 3–1: UNUSED. Read = 0b. Write = don’t care. Bit 0: DROPOUT: Voltage Regulator Dropout Indicator Bit. 0: Voltage Regulator is not in dropout. 1: Voltage Regulator is in or near dropout. Table 8.1. Voltage Regulator Electrical Specifications VDD = 2.1 or 2.5 V; –40 to +85 °C unless otherwise specified. Typical values are given at 25 ºC. Parameter Input Voltage Range (VREGIN)* Dropout Voltage (VDO) Output Voltage (VDD) Bias Current Dropout Indicator Detection Threshold Output Voltage Tempco VREG Settling Time Conditions Min (See Note) — Typ — 7 2.1 2.5 1 1 65 600 250 Max 5.25 15 2.25 2.55 1.5 1.5 — — — Units V mV/mA V Output Current = 1 mA REG0MD = ‘0’ REG0MD = ‘1’ REG0MD = ‘0’ REG0MD = ‘1’ 2.0 2.35 — — — — µA mV µV/ºC µs 50 mA load with VREGIN = 2.5 V and VDD load capacitor of 4.8 µF — *Note: Actual Output Voltage (VDD) = Nominal Output Voltage (VDD) – Dropout Voltage (VDO)(max load). 82 Rev. 1.0 C8051F410/1/2/3 9. Comparators C8051F41x devices include two on-chip programmable voltage comparators: Comparator0 is shown in Figure 9.1; Comparator1 is shown in Figure 9.2. The two comparators operate identically, but only Comparator0 can be used as a reset source. The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an asynchronous “raw” output (CP0A, CP1A). The asynchronous CP0A signal is available even when the system clock is not active. This allows the Comparator to operate and generate an output with the device in STOP or SUSPEND mode. When assigned to a Port pin, the Comparator output may be configured as open drain or push-pull (see Section “18.2. Port I/O Initialization” on page 151). Comparator0 may also be used as a reset source (see Section “15.5. Comparator0 Reset” on page 130). The Comparator0 inputs are selected in the CPT0MX register (SFR Definition 9.2). The CMX0P3-CMX0P0 bits select the Comparator0 positive input; the CMX0N3-CMX0N0 bits select the Comparator0 negative input. The Comparator1 inputs are selected in the CPT1MX register (SFR Definition 9.4). The CMX1P3CMX1P0 bits select the Comparator1 positive input; the CMX1N3-CMX1N0 bits select the Comparator1 negative input. Important Note About Comparator Inputs: The Port pins selected as Comparator inputs should be configured as analog inputs in their associated Port configuration register (with a ‘1’ written to the corresponding Port Latch register), and configured to be skipped by the Crossbar (for details on Port configuration, see Section “18.3. General Purpose Port I/O” on page 154) CP0EN CP0OUT CP0RIF CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 CPT0MX CMX0N3 CMX0N2 CMX0N1 CMX0N0 CMX0P3 CMX0P2 CMX0P1 CMX0P0 P0.0 P0.2 CPT0CN VDD C P0 Interrupt CP0 Rising-edge C P0 Falling-edge P 0.1 P0.4 P 0.3 P0.6 P 0.5 P1.0 P 0.7 P1.2 P 1.1 P1.4 P 1.3 P1.6 P 1.5 P2.0 P 1.7 P2.2 P 2.1 P2.4 P 2.3 P2.6 P 2.5 P 2.7 CP0 CP0MD0 CP0MD1 Reset Decision Tree GND (SYNCHRONIZER) CP0 + Interrupt Logic + D SET CP0 Q D SET Q - CL R Q CLR Q Crossbar CP0A CPT0MD CP0RIE CP0FIE Figure 9.1. Comparator0 Functional Block Diagram Rev. 1.0 83 C8051F410/1/2/3 The Comparator output can be polled in software, used as an interrupt source, internal oscillator suspend awakening source and/or routed to a Port pin. When routed to a Port pin, the Comparator output is available asynchronous or synchronous to the system clock; the asynchronous output is available even in STOP or SUSPEND mode (with no system clock active). When disabled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state, and its supply current falls to less than 100 nA. See Section “18.1. Priority Crossbar Decoder” on page 149 for details on configuring Comparator outputs via the digital Crossbar. Comparator inputs can be externally driven from -0.25 V to (VDD) + 0.25 V without damage or upset. The complete Comparator electrical specifications are given in Table 9.1. The Comparator response time may be configured in software via the CPTnMD registers (see SFR Definition 9.3 and SFR Definition 9.5). Selecting a longer response time reduces the Comparator supply current. See Table 9.1 for complete timing and current consumption specifications. CP1EN CP1OUT CP1RIF CP1FIF CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0 CMX1N3 CMX1N2 CMX1N1 CMX1N0 CMX1P3 CMX1P2 CMX1P1 CMX1P0 P0.0 P0.2 P 0.1 P0.4 P 0.3 P0.6 P 0.5 P 1.0 P 0.7 P1.2 P 1.1 P1.4 P 1.3 P1.6 P 1.5 P2.0 P 1.7 P2.2 P 2.1 P2.4 P 2.3 P2.6 P 2.5 P 2.7 CPT1CN VDD CPT1MX C P1 Interrupt CP1 Rising-edge C P1 Falling-edge CP1 + Interrupt Logic + D SET CP1 Q D SET Q GND CLR Q CLR Q Crossbar (SYNCHRONIZER) CP1A CPT1MD CP1MD0 CP1MD1 CP1RIE CP1FIE CP1 - Figure 9.2. Comparator1 Functional Block Diagram 84 Rev. 1.0 C8051F410/1/2/3 VIN+ VIN- CP0+ CP0- + CP0 _ OUT CIRCUIT CONFIGURATION Positive Hysteresis Voltage (Programmed with CP0HYP Bits) VIN- INPUTS VIN+ Negative Hysteresis Voltage (Programmed by CP0HYN Bits) VOH OUTPUT VOL Negative Hysteresis Disabled Positive Hysteresis Disabled Maximum Positive Hysteresis Maximum Negative Hysteresis Figure 9.3. Comparator Hysteresis Plot The Comparator hysteresis is software-programmable via its Comparator Control register CPTnCN (for n = 0 or 1). The user can program both the amount of hysteresis voltage (referred to the input voltage) and the positive and negative-going symmetry of this hysteresis around the threshold voltage. The Comparator hysteresis is programmed using Bits3-0 in the Comparator Control Register CPTnCN (shown in SFR Definition 9.1 and SFR Definition 9.6). The amount of negative hysteresis voltage is determined by the settings of the CPnHYN bits. As shown in Table 9.1, settings of 20, 10 or 5 mV of negative hysteresis can be programmed, or negative hysteresis can be disabled. In a similar way, the amount of positive hysteresis is determined by setting the CPnHYP bits. Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Interrupt enable and priority control, see Section “12. Interrupt Handler” on page 110). The CPnFIF flag is set to logic 1 upon a Comparator falling-edge detect, and the CPnRIF flag is set to logic 1 upon the Comparator rising-edge detect. Once set, these bits remain set until cleared by software. The output state of the Comparator can be obtained at any time by reading the CPnOUT bit. The Comparator is enabled by setting the CPnEN bit to logic 1, and is disabled by clearing this bit to logic 0. The output state of the Comparator can be obtained at any time by reading the CPnOUT bit. The Comparator is enabled by setting the CPnEN bit to logic 1, and is disabled by clearing this bit to logic 0. When the Comparator is enabled, the internal oscillator is awakened from SUSPEND mode if the Comparator output is logic 0. Note that false rising edges and falling edges can be detected when the comparator is first powered-on or if changes are made to the hysteresis or response time control bits. Therefore, it is recommended that the rising-edge and falling-edge flags be explicitly cleared to logic 0 a short time after the comparator is enabled or its mode bits have been changed. This Power Up Time is specified in Table 9.1 on page 92. Rev. 1.0 85 C8051F410/1/2/3 SFR Definition 9.1. CPT0CN: Comparator0 Control R/W R R/W R/W R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value SFR Address: CP0EN Bit7 CP0OUT Bit6 CP0RIF Bit5 CP0FIF Bit4 CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 00000000 0x9B Bit7: CP0EN: Comparator0 Enable Bit. 0: Comparator0 Disabled. 1: Comparator0 Enabled. Bit6: CP0OUT: Comparator0 Output State Flag. 0: Voltage on CP0+ < CP0–. 1: Voltage on CP0+ > CP0–. Bit5: CP0RIF: Comparator0 Rising-Edge Flag. 0: No Comparator0 Rising Edge has occurred since this flag was last cleared. 1: Comparator0 Rising Edge has occurred. Bit4: CP0FIF: Comparator0 Falling-Edge Flag. 0: No Comparator0 Falling-Edge has occurred since this flag was last cleared. 1: Comparator0 Falling-Edge has occurred. Bits3–2: CP0HYP1–0: Comparator0 Positive Hysteresis Control Bits. 00: Positive Hysteresis Disabled. 01: Positive Hysteresis = 5 mV. 10: Positive Hysteresis = 10 mV. 11: Positive Hysteresis = 20 mV. Bits1–0: CP0HYN1–0: Comparator0 Negative Hysteresis Control Bits. 00: Negative Hysteresis Disabled. 01: Negative Hysteresis = 5 mV. 10: Negative Hysteresis = 10 mV. 11: Negative Hysteresis = 20 mV. 86 Rev. 1.0 C8051F410/1/2/3 SFR Definition 9.2. CPT0MX: Comparator0 MUX Selection R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W R/W Bit1 R/W Bit0 Reset Value CMX0N3 CMX0N2 CMX0N1 CMX0N0 CMX0P3 CMX0P2 Bit2 CMX0P1 CMX0P0 11111111 SFR Address: 0x9F Bits7–4: CMX0N3–CMX0N0: Comparator0 Negative Input MUX Select. These bits select which Port pin is used as the Comparator0 negative input. CMX0N3 CMX0N2 CMX0N1 CMX0N0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 x x *Note: Available only on the C8051F410/2. Negative Input P0.1 P0.3 P0.5 P0.7 P1.1 P1.3 P1.5 P1.7 P2.1 P2.3* P2.5* P2.7 Reserved Bits1–0: CMX0P3–CMX0P0: Comparator0 Positive Input MUX Select. These bits select which Port pin is used as the Comparator0 positive input. CMX0P3 CMX0P2 CMX0P1 CMX0P0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 x x *Note: Available only on the C8051F410/2. Positive Input P0.0 P0.2 P0.4 P0.6 P1.0 P1.2 P1.4 P1.6 P2.0 P2.2 P2.4* P2.6* Reserved Rev. 1.0 87 C8051F410/1/2/3 SFR Definition 9.3. CPT0MD: Comparator0 Mode Selection R/W R/W R/W R/W R/W R/W R/W Bit1 R/W Bit0 Reset Value SFR Address: RESERVED Bit7 Bit6 CP0RIE Bit5 CP0FIE Bit4 Bit3 Bit2 CP0MD1 CP0MD0 00000010 0x9D Bit7: Bit6: Bit5: RESERVED. Read = 0b. Must Write 0b. UNUSED. Read = 0b. Write = don’t care. CP0RIE: Comparator Rising-Edge Interrupt Enable. 0: Comparator rising-edge interrupt disabled. 1: Comparator rising-edge interrupt enabled. Bit4: CP0FIE: Comparator Falling-Edge Interrupt Enable. 0: Comparator falling-edge interrupt disabled. 1: Comparator falling-edge interrupt enabled. Bits3–2: UNUSED. Read = 00b. Write = don’t care. Bits1–0: CP0MD1–CP0MD0: Comparator0 Mode Select These bits select the response time for Comparator0. Mode 0 1 2 3 CP0MD1 0 0 1 1 CP0MD0 0 1 0 1 CP0 Falling Edge Response Time (TYP) Fastest Response Time — — Lowest Power Consumption Note: Rising Edge response times are approximately double the Falling Edge response times. 88 Rev. 1.0 C8051F410/1/2/3 SFR Definition 9.4. CPT1MX: Comparator1 MUX Selection R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W R/W Bit1 R/W Bit0 Reset Value CMX1N3 CMX1N2 CMX1N1 CMX1N0 CMX1P3 CMX1P2 Bit2 CMX1P1 CMX1P0 11111111 SFR Address: 0x9E Bits7–4: CMX1N3–CMX1N0: Comparator1 Negative Input MUX Select. These bits select which Port pin is used as the Comparator1 negative input. CMX1N3 CMX1N2 CMX1N1 CMX1N0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 x x *Note: Available only on the C8051F410/2. Negative Input P0.1 P0.3 P0.5 P0.7 P1.1 P1.3 P1.5 P1.7 P2.1 P2.3* P2.5* P2.7 Reserved Bits3–0: CMX1P3–CMX1P0: Comparator1 Positive Input MUX Select. These bits select which Port pin is used as the Comparator1 positive input. CMX1P3 CMX1P2 CMX1P1 CMX1P0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 x x *Note: Available only on the C8051F410/2. Positive Input P0.0 P0.2 P0.4 P0.6 P1.0 P1.2 P1.4 P1.6 P2.0 P2.2 P2.4* P2.6* Reserved Rev. 1.0 89 C8051F410/1/2/3 SFR Definition 9.5. CPT1MD: Comparator1 Mode Selection R/W R/W R/W R/W R/W R/W R/W Bit1 R/W Bit0 Reset Value SFR Address: RESERVED Bit7 Bit6 CP1RIE Bit5 CP1FIE Bit4 Bit3 Bit2 CP1MD1 CP1MD0 00000010 0x9C Bit7: Bit6: Bit5: RESERVED. Read = 0b. Must Write 0b. UNUSED. Read = 0b. Write = don’t care. CP1RIE: Comparator Rising-Edge Interrupt Enable. 0: Comparator rising-edge interrupt disabled. 1: Comparator rising-edge interrupt enabled. Bit4: CP1FIE: Comparator Falling-Edge Interrupt Enable. 0: Comparator falling-edge interrupt disabled. 1: Comparator falling-edge interrupt enabled. Bits3–2: UNUSED. Read = 00b. Write = don’t care. Bits1–0: CP1MD1–CP1MD0: Comparator1 Mode Select. These bits select the response time for Comparator1. Mode 0 1 2 3 CP1MD1 0 0 1 1 CP1MD0 0 1 0 1 CP1 Falling Edge Response Time (TYP) Fastest Response Time — — Lowest Power Consumption Note: Rising Edge response times are approximately double the Falling Edge response times. 90 Rev. 1.0 C8051F410/1/2/3 SFR Definition 9.6. CPT1CN: Comparator1 Control R/W R R/W R/W R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value SFR Address: CP1EN Bit7 CP1OUT Bit6 CP1RIF Bit5 CP1FIF Bit4 CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0 00000000 0x9A Bit7: CP1EN: Comparator1 Enable Bit. 0: Comparator1 Disabled. 1: Comparator1 Enabled. Bit6: CP1OUT: Comparator1 Output State Flag. 0: Voltage on CP1+ < CP1-. 1: Voltage on CP1+ > CP1-. Bit5: CP1RIF: Comparator1 Rising-Edge Flag. 0: No Comparator1 Rising Edge has occurred since this flag was last cleared. 1: Comparator1 Rising Edge has occurred. Bit4: CP1FIF: Comparator1 Falling-Edge Flag. 0: No Comparator1 Falling-Edge has occurred since this flag was last cleared. 1: Comparator1 Falling-Edge has occurred. Bits3–2: CP1HYP1–0: Comparator1 Positive Hysteresis Control Bits. 00: Positive Hysteresis Disabled. 01: Positive Hysteresis = 5 mV. 10: Positive Hysteresis = 10 mV. 11: Positive Hysteresis = 20 mV. Bits1–0: CP1HYN1–0: Comparator1 Negative Hysteresis Control Bits. 00: Negative Hysteresis Disabled. 01: Negative Hysteresis = 5 mV. 10: Negative Hysteresis = 10 mV. 11: Negative Hysteresis = 20 mV. Rev. 1.0 91 C8051F410/1/2/3 Table 9.1. Comparator Electrical Characteristics VDD = 2.0 V, –40 to +85 °C unless otherwise noted. All specifications apply to both Comparator0 and Comparator1 unless otherwise noted. Typical values are given at 25 ºC. Parameter Response Time: Mode 0, Vcm1 = 1.5 V Response Time: Mode 1, Vcm1 = 1.5 V Response Time: Mode 2, Vcm1 = 1.5 V Response Time: Mode 3, Vcm1 = 1.5 V Common-Mode Rejection Ratio2 Positive Hysteresis 1 Positive Hysteresis 2 Positive Hysteresis 3 Positive Hysteresis 4 Negative Hysteresis 1 Negative Hysteresis 2 Negative Hysteresis 3 Negative Hysteresis 4 Inverting or Non-Inverting Input Voltage Range Input Capacitance Input Bias Current Input Offset Voltage Conditions CP0+ – CP0– = 100 mV CP0+ – CP0– = –100 mV CP0+ – CP0– = 100 mV CP0+ – CP0– = –100 mV CP0+ – CP0– = 100 mV CP0+ – CP0– = –100 mV CP0+ – CP0– = 100 mV CP0+ – CP0– = –100 mV Min — — — — — — — — — Typ 120 160 200 340 360 720 2.2 7.2 1.5 0.5 4.5 9.0 18.0 –0.5 –4.5 –9.0 –18.0 — 4 0.5 — 0.2 2.3 13 6.0 3.0 1.0 Max — — — — — — — — 14 2.0 10 20 40 –2.0 –10 –20 –40 VDD + 0.25 — — 10 4 — 30 20 10 5 Units ns ns ns ns ns ns µs µs mV/V mV mV mV mV mV mV mV mV V pF nA mV mV/V µs µA µA µA µA CP0HYP1-0 = 00 CP0HYP1-0 = 01 CP0HYP1-0 = 10 CP0HYP1-0 = 11 CP0HYN1-0 = 00 CP0HYN1-0 = 01 CP0HYN1-0 = 10 CP0HYN1-0 = 11 — 2 5 13 — –2 –5 –13 –0.25 — — –10 — — Power Supply Power Supply Rejection2 Power-up Time Mode 0 Mode 1 Supply Current at DC Mode 2 Mode 3 Notes: 1. Vcm is the common-mode voltage on CP0+ and CP0–. 2. Guaranteed by design and/or characterization. — — — — 92 Rev. 1.0 C8051F410/1/2/3 10. CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set. Standard 803x/805x assemblers and compilers can be used to develop software. The C8051F41x family has a superset of all the peripherals included with a standard 8051. See Section “1. System Overview” on page 19 for more information about the available peripherals. The CIP-51 includes on-chip debug hardware which interfaces directly with the analog and digital subsystems, providing a complete data acquisition or control-system solution in a single integrated circuit. The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals and functions to extend its capability (see Figure 10.1 for a block diagram). The CIP-51 core includes the following features: - Fully Compatible with MCS-51 Instruction Set - 50 MIPS Peak Throughput - 256 Bytes of Internal RAM - Extended Interrupt Handler Reset Input Power Management Modes Integrated Debug Logic DATA BUS D8 D8 D8 D8 D8 ACCUMULATOR B REGISTER STACK POINTER DATA BUS TMP1 TMP2 PSW ALU D8 D8 SRAM ADDRESS REGISTER D8 SRAM (256 X 8) D8 DATA BUS SFR_ADDRESS BUFFER D8 DATA POINTER D8 D8 SFR BUS INTERFACE SFR_CONTROL SFR_WRITE_DATA SFR_READ_DATA PC INCREMENTER DATA BUS PROGRAM COUNTER (PC) D8 MEM_ADDRESS MEM_CONTROL PRGM. ADDRESS REG. A16 MEMORY INTERFACE MEM_WRITE_DATA MEM_READ_DATA PIPELINE RESET CLOCK STOP IDLE POWER CONTROL REGISTER D8 D8 CONTROL LOGIC INTERRUPT INTERFACE SYSTEM_IRQs EMULATION_IRQ D8 Figure 10.1. CIP-51 Block Diagram Rev. 1.0 93 C8051F410/1/2/3 Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more than eight system clock cycles. With the CIP-51's system clock running at 50 MHz, it has a peak throughput of 50 MIPS. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execution time. Clocks to Execute Number of Instructions 1 26 2 50 2/4 5 3 10 3/5 7 4 5 5 2 4/6 1 6 2 8 1 Programming and Debugging Support In-system programming of the Flash program memory and communication with on-chip debug support logic is accomplished via the Silicon Labs 2-Wire (C2) interface. Note that the re-programmable Flash can also be read and written a single byte at a time by the application software using the MOVC and MOVX instructions. This feature allows program memory to be used for non-volatile data storage as well as updating program code under software control. The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware breakpoints, starting, stopping and single stepping through program execution (including interrupt service routines), examination of the program's call stack, and reading/writing the contents of registers and memory. This method of on-chip debugging is completely non-intrusive, requiring no RAM, Stack, timers, or other on-chip resources. The CIP-51 is supported by development tools from Silicon Laboratories, Inc. and third party vendors. Silicon Laboratories provides an integrated development environment (IDE) including editor, evaluation compiler, assembler, debugger and programmer. The IDE's debugger and programmer interface to the CIP-51 via the on-chip debug logic to provide fast and efficient in-system device programming and debugging. Third party macro assemblers and C compilers are also available. 10.1. Instruction Set The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruction set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51 instructions are the binary and functional equivalent of their MCS-51™ counterparts, including opcodes, addressing modes and effect on PSW flags. However, instruction timing is different than that of the standard 8051. 10.1.1. Instruction and CPU Timing In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based solely on clock cycle timing. All instruction timings are specified in terms of clock cycles. Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock cycles as there are program bytes in the instruction. Conditional branch instructions take two less clock cycles to complete when the branch is not taken as opposed to when the branch is taken. Table 10.1 is the CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock cycles for each instruction. 94 Rev. 1.0 C8051F410/1/2/3 10.1.2. MOVX Instruction and Program Memory The MOVX instruction is typically used to access data stored in XDATA memory space. In the CIP-51, the MOVX instruction can also be used to write or erase on-chip program memory space implemented as reprogrammable Flash memory. The Flash access feature provides a mechanism for the CIP-51 to update program code and use the program memory space for non-volatile data storage. Refer to Section “16. Flash Memory” on page 135 for further details. Table 10.1. CIP-51 Instruction Set Summary1 Mnemonic ADD A, Rn ADD A, direct ADD A, @Ri ADD A, #data ADDC A, Rn ADDC A, direct ADDC A, @Ri ADDC A, #data SUBB A, Rn SUBB A, direct SUBB A, @Ri SUBB A, #data INC A INC Rn INC direct INC @Ri DEC A DEC Rn DEC direct DEC @Ri INC DPTR MUL AB DIV AB DA A ANL A, Rn ANL A, direct ANL A, @Ri ANL A, #data ANL direct, A ANL direct, #data ORL A, Rn ORL A, direct Description Arithmetic Operations Add register to A Add direct byte to A Add indirect RAM to A Add immediate to A Add register to A with carry Add direct byte to A with carry Add indirect RAM to A with carry Add immediate to A with carry Subtract register from A with borrow Subtract direct byte from A with borrow Subtract indirect RAM from A with borrow Subtract immediate from A with borrow Increment A Increment register Increment direct byte Increment indirect RAM Decrement A Decrement register Decrement direct byte Decrement indirect RAM Increment Data Pointer Multiply A and B Divide A by B Decimal adjust A Logical Operations AND Register to A AND direct byte to A AND indirect RAM to A AND immediate to A AND A to direct byte AND immediate to direct byte OR Register to A OR direct byte to A Bytes 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 2 1 1 1 1 1 1 2 1 2 2 3 1 2 Clock Cycles 1 2 2 2 1 2 2 2 1 2 2 2 1 1 2 2 1 1 2 2 1 4 8 1 1 2 2 2 2 3 1 2 Notes: 1. Assumes PFEN = 1 for all instruction timing. 2. MOVC instructions take 4 to 7 clock cycles depending on instruction alignment and the FLRT setting (SFR Definition 16.3. FLSCL: Flash Scale). Rev. 1.0 95 C8051F410/1/2/3 Table 10.1. CIP-51 Instruction Set Summary1 (Continued) Mnemonic ORL A, @Ri ORL A, #data ORL direct, A ORL direct, #data XRL A, Rn XRL A, direct XRL A, @Ri XRL A, #data XRL direct, A XRL direct, #data CLR A CPL A RL A RLC A RR A RRC A SWAP A MOV A, Rn MOV A, direct MOV A, @Ri MOV A, #data MOV Rn, A MOV Rn, direct MOV Rn, #data MOV direct, A MOV direct, Rn MOV direct, direct MOV direct, @Ri MOV direct, #data MOV @Ri, A MOV @Ri, direct MOV @Ri, #data MOV DPTR, #data16 MOVC A, @A+DPTR MOVC A, @A+PC MOVX A, @Ri MOVX @Ri, A MOVX A, @DPTR MOVX @DPTR, A PUSH direct Description OR indirect RAM to A OR immediate to A OR A to direct byte OR immediate to direct byte Exclusive-OR Register to A Exclusive-OR direct byte to A Exclusive-OR indirect RAM to A Exclusive-OR immediate to A Exclusive-OR A to direct byte Exclusive-OR immediate to direct byte Clear A Complement A Rotate A left Rotate A left through Carry Rotate A right Rotate A right through Carry Swap nibbles of A Data Transfer Move Register to A Move direct byte to A Move indirect RAM to A Move immediate to A Move A to Register Move direct byte to Register Move immediate to Register Move A to direct byte Move Register to direct byte Move direct byte to direct byte Move indirect RAM to direct byte Move immediate to direct byte Move A to indirect RAM Move direct byte to indirect RAM Move immediate to indirect RAM Load DPTR with 16-bit constant Move code byte relative DPTR to A Move code byte relative PC to A Move external data (8-bit address) to A Move A to external data (8-bit address) Move external data (16-bit address) to A Move A to external data (16-bit address) Push direct byte onto stack Bytes 1 2 2 3 1 2 1 2 2 3 1 1 1 1 1 1 1 1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 1 1 1 2 Clock Cycles 2 2 2 3 1 2 2 2 2 3 1 1 1 1 1 1 1 1 2 2 2 1 2 2 2 2 3 2 3 2 2 2 3 4 to 72 4 to 72 3 3 3 3 2 Notes: 1. Assumes PFEN = 1 for all instruction timing. 2. MOVC instructions take 4 to 7 clock cycles depending on instruction alignment and the FLRT setting (SFR Definition 16.3. FLSCL: Flash Scale). 96 Rev. 1.0 C8051F410/1/2/3 Table 10.1. CIP-51 Instruction Set Summary1 (Continued) Mnemonic POP direct XCH A, Rn XCH A, direct XCH A, @Ri XCHD A, @Ri CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C, bit ANL C, /bit ORL C, bit ORL C, /bit MOV C, bit MOV bit, C JC rel JNC rel JB bit, rel JNB bit, rel JBC bit, rel ACALL addr11 LCALL addr16 RET RETI AJMP addr11 LJMP addr16 SJMP rel JMP @A+DPTR JZ rel JNZ rel CJNE A, direct, rel CJNE A, #data, rel CJNE Rn, #data, rel CJNE @Ri, #data, rel DJNZ Rn, rel DJNZ direct, rel NOP Description Pop direct byte from stack Exchange Register with A Exchange direct byte with A Exchange indirect RAM with A Exchange low nibble of indirect RAM with A Boolean Manipulation Clear Carry Clear direct bit Set Carry Set direct bit Complement Carry Complement direct bit AND direct bit to Carry AND complement of direct bit to Carry OR direct bit to carry OR complement of direct bit to Carry Move direct bit to Carry Move Carry to direct bit Jump if Carry is set Jump if Carry is not set Jump if direct bit is set Jump if direct bit is not set Jump if direct bit is set and clear bit Program Branching Absolute subroutine call Long subroutine call Return from subroutine Return from interrupt Absolute jump Long jump Short jump (relative address) Jump indirect relative to DPTR Jump if A equals zero Jump if A does not equal zero Compare direct byte to A and jump if not equal Compare immediate to A and jump if not equal Compare immediate to Register and jump if not equal Compare immediate to indirect and jump if not equal Decrement Register and jump if not zero Decrement direct byte and jump if not zero No operation Bytes 2 1 2 1 1 1 2 1 2 1 2 2 2 2 2 2 2 2 2 3 3 3 2 3 1 1 2 3 2 1 2 2 3 3 3 3 2 3 1 Clock Cycles 2 1 2 2 2 1 2 1 2 1 2 2 2 2 2 2 2 2/4 2/4 3/5 3/5 3/5 4 5 6 6 4 5 4 4 2/4 2/4 3/5 3/5 3/5 4/6 2/4 3/5 1 Notes: 1. Assumes PFEN = 1 for all instruction timing. 2. MOVC instructions take 4 to 7 clock cycles depending on instruction alignment and the FLRT setting (SFR Definition 16.3. FLSCL: Flash Scale). Rev. 1.0 97 C8051F410/1/2/3 Notes on Registers, Operands and Addressing Modes: Rn - Register R0-R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. rel - 8-bit, signed (two’s complement) offset relative to the first byte of the following instruction. Used by SJMP and all conditional jumps. direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location (0x000x7F) or an SFR (0x80-0xFF). #data - 8-bit constant #data16 - 16-bit constant bit - Direct-accessed bit in Data RAM or SFR addr11 - 11-bit destination address used by ACALL and AJMP. The destination must be within the same 2K-byte page of program memory as the first byte of the following instruction. addr16 - 16-bit destination address used by LCALL and LJMP. The destination may be anywhere within the 8K-byte program memory space. There is one unused opcode (0xA5) that performs the same function as NOP. All mnemonics copyrighted © Intel Corporation 1980. 10.2. Register Descriptions Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should not be set to logic 1. Future product versions may use these bits to implement new features in which case the reset value of the bit will be logic 0, selecting the feature's default state. Detailed descriptions of the remaining SFRs are included in the sections of the datasheet associated with their corresponding system function. SFR Definition 10.1. SP: Stack Pointer R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 SFR Address: 0x81 Reset Value 00000111 Bits7–0: SP: Stack Pointer. The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented before every PUSH operation. The SP register defaults to 0x07 after reset. 98 Rev. 1.0 C8051F410/1/2/3 SFR Definition 10.2. DPL: Data Pointer Low Byte R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 00000000 SFR Address: 0x82 Bits7–0: DPL: Data Pointer Low. The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly addressed XRAM and Flash memory. SFR Definition 10.3. DPH: Data Pointer High Byte R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 00000000 SFR Address: 0x83 Bits7–0: DPH: Data Pointer High. The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly addressed XRAM and Flash memory. Rev. 1.0 99 C8051F410/1/2/3 SFR Definition 10.4. PSW: Program Status Word R/W R/W R/W R/W R/W R/W R/W R Reset Value CY Bit7 AC Bit6 F0 Bit5 RS1 Bit4 RS0 Bit3 OV Bit2 F1 Bit1 PARITY Bit0 00000000 Bit Addressable SFR Address: 0xD0 Bit7: CY: Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow (subtraction). It is cleared to 0 by all other arithmetic operations. Bit6: AC: Auxiliary Carry Flag This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow from (subtraction) the high order nibble. It is cleared to 0 by all other arithmetic operations. Bit5: F0: User Flag 0. This is a bit-addressable, general purpose flag for use under software control. Bits4–3: RS1–RS0: Register Bank Select. These bits select which register bank is used during register accesses. RS1 0 0 1 1 Bit2: RS0 0 1 0 1 Register Bank 0 1 2 3 Address 0x00–0x07 0x08–0x0F 0x10–0x17 0x18–0x1F Bit1: Bit0: OV: Overflow Flag. This bit is set to 1 under the following circumstances: • An ADD, ADDC, or SUBB instruction causes a sign-change overflow. • A MUL instruction results in an overflow (result is greater than 255). • A DIV instruction causes a divide-by-zero condition. The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other cases. F1: User Flag 1. This is a bit-addressable, general purpose flag for use under software control. PARITY: Parity Flag. This bit is set to 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum is even. 100 Rev. 1.0 C8051F410/1/2/3 SFR Definition 10.5. ACC: Accumulator R/W R/W R/W R/W R/W R/W R/W R/W Reset Value ACC.7 Bit7 ACC.6 Bit6 ACC.5 Bit5 ACC.4 Bit4 ACC.3 Bit3 ACC.2 Bit2 ACC.1 Bit1 ACC.0 Bit0 00000000 Bit Addressable SFR Address: 0xE0 Bits7–0: ACC: Accumulator. This register is the accumulator for arithmetic operations. SFR Definition 10.6. B: B Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value B.7 Bit7 B.6 Bit6 B.5 Bit5 B.4 Bit4 B.3 Bit3 B.2 Bit2 B.1 Bit1 B.0 Bit0 00000000 Bit Addressable SFR Address: 0xF0 Bits7–0: B: B Register. This register serves as a second accumulator for certain arithmetic operations. 10.3. Power Management Modes The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU while leaving the peripherals and internal clocks active. In Stop mode, the CPU is halted, all interrupts and timers (except the Missing Clock Detector) are inactive, and the internal oscillator is stopped (analog peripherals remain in their selected states; the external oscillator is not affected). Since clocks are running in Idle mode, power consumption is dependent upon the system clock frequency and the number of peripherals left in active mode before entering Idle. Stop mode consumes the least power. SFR Definition 10.7 describes the Power Control Register (PCON) used to control the CIP-51's power management modes. Although the CIP-51 has Idle and Stop modes built in (as with any standard 8051 architecture), power management of the entire MCU is better accomplished by enabling/disabling individual peripherals as needed. Each analog peripheral can be disabled when not in use and placed in low power mode. Digital peripherals, such as timers or serial buses, draw little power when they are not in use. Turning off the oscillators lowers power consumption considerably; however a reset is required to restart the MCU. The C8051F41x devices feature a low-power SUSPEND mode, which stops the internal oscillator until a wakening event occurs. See Section “19.1.1. Internal Oscillator Suspend Mode” on page 166. Rev. 1.0 101 C8051F410/1/2/3 10.3.1. Idle Mode Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon as the instruction that sets the bit completes execution. All internal registers and memory maintain their original data. All analog and digital peripherals can remain active during Idle mode. Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume operation. The pending interrupt will be serviced and the next instruction to be executed after the return from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit. If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence and begins program execution at address 0x0000. If enabled, the Watchdog Timer (WDT) will eventually cause an internal watchdog reset and thereby terminate the Idle mode. This feature protects the system from an unintended permanent shutdown in the event of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by software prior to entering the Idle mode if the WDT was initially configured to allow this operation. This provides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefinitely, waiting for an external stimulus to wake up the system. 10.3.2. Stop Mode Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruction that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital peripherals are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral (including the external oscillator circuit) may be shut down individually prior to entering Stop Mode. Stop mode can only be terminated by an internal or external reset. On reset, the CIP-51 performs the normal reset sequence and begins program execution at address 0x0000. If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode. The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the MCD timeout period of 100 µs. 10.3.3. Suspend Mode The C8051F41x devices feature a low-power SUSPEND mode, which stops the internal oscillator until a wakening event occurs. See Section “19.1.1. Internal Oscillator Suspend Mode” on page 166. SFR Definition 10.7. PCON: Power Control R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W R/W Reset Value Reserved Reserved Reserved Reserved Reserved Reserved STOP Bit1 IDLE Bit0 00000000 SFR Address: 0x87 Bits7–2: Reserved. Bit1: STOP: STOP Mode Select. Writing a ‘1’ to this bit will place the CIP-51 into STOP mode. This bit will always read ‘0’. 1: CIP-51 forced into power-down mode. (Turns off internal oscillator). Bit0: IDLE: IDLE Mode Select. Writing a ‘1’ to this bit will place the CIP-51 into IDLE mode. This bit will always read ‘0’. 1: CIP-51 forced into IDLE mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, and all peripherals remain active.) 102 Rev. 1.0 C8051F410/1/2/3 11. Memory Organization and SFRs The memory organization of the C8051F41x is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space but are accessed via different instruction types. The memory map is shown in Figure 11.1. PROGRAM/DATA MEMORY (Flash) ‘F410/1 0xFF 0x7E00 0x7DFF RESERVED 0x80 0x7F DATA MEMORY (RAM) INTERNAL DATA ADDRESS SPACE Upper 128 RAM (Indirect Addressing Only) (Direct and Indirect Addressing) Special Function Register's (Direct Addressing Only) 32 kB Flash (In-System Programmable in 512 Byte Sectors) 0x30 0x2F 0x20 0x1F 0x00 Bit Addressable General Purpose Registers L ower 128 RAM (Direct and Indirect Addressing) EXTERNAL DATA ADDRESS SPACE 0x0000 0xFFFF ‘F412/3 0x4000 0x3FFF RESERVED Same 2048 bytes as from 0x0000 to 0x07FF, wrapped on 2048-byte boundaries 16 kB Flash (In-System Programmable in 512 Byte Sectors) 0x0800 0x07FF XRAM - 2048 Bytes (accessible using MOVX instruction) 0x0000 0x0000 Figure 11.1. Memory Map 11.1. Program Memory The CIP-51 core has a 64k-byte program memory space. The C8051F410/1 implement 32k of this program memory space as in-system, re-programmable Flash memory, organized in a contiguous block from addresses 0x0000 to 0x7DFF. Addresses above 0x7DFF are reserved on the 32 kB devices. The C8051F412/3 implement 16 kB of Flash from addresses 0x0000 to 0x3FFF. Program memory is normally assumed to be read-only. However, the C8051F41x can write to program memory by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX write instruction. This feature provides a mechanism for updates to program code and use of the program memory space for non-volatile data storage. Refer to Section “16. Flash Memory” on page 135 for further details. Rev. 1.0 103 C8051F410/1/2/3 11.2. Data Memory The C8051F41x includes 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or as 128 bit locations accessible with the direct addressing mode. The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the same address space as the Special Function Registers (SFRs) but is physically separate from the SFR space. The addressing mode used by an instruction when accessing locations above 0x7F determines whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the upper 128 bytes of data memory. Figure 11.1 illustrates the data memory organization of the C8051F41x. The C8051F41x family also includes 2048 bytes of on-chip RAM mapped into the external memory (XDATA) space. This RAM can be accessed using the CIP-51 core’s MOVX instruction. More information on the XRAM memory can be found in Section “17. External RAM” on page 145. 11.3. General Purpose Registers The lower 32 bytes of data memory (locations 0x00 through 0x1F) may be addressed as four banks of general-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1 (PSW.4), select the active register bank (see description of the PSW in SFR Definition 10.4. PSW: Program Status Word). This allows fast context switching when entering subroutines and interrupt service routines. Indirect addressing modes use registers R0 and R1 as index registers. 11.4. Bit Addressable Locations In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from 0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address 0x00 while bit 7 of the byte at 0x20 has bit address 0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by the type of instruction used (bit source or destination operands as opposed to a byte source or destination). The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where XX is the byte address and B is the bit position within the byte. For example, the instruction: MOV C, 22.3h moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag. 11.5. Stack A programmer's stack can be located anywhere in the 256-byte data memory. The stack area is designated using the Stack Pointer (SP, 0x81) SFR. The SP will point to the last location used. The next value pushed on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to location 0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the first register (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be initialized to a location in the data memory not being used for data storage. The stack depth can extend up to 256 bytes. 104 Rev. 1.0 C8051F410/1/2/3 11.6. Special Function Registers The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The CIP-51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional SFRs used to configure and access the sub-systems unique to the MCU. This allows the addition of new functionality while retaining compatibility with the MCS-51™ instruction set. Table 11.1 lists the SFRs implemented in the CIP-51 System Controller. The SFR registers are accessed anytime the direct addressing mode is used to access memory locations from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, IE, etc.) are bit-addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate effect and should be avoided. Refer to the corresponding pages of the data sheet, as indicated in Table 11.2, for a detailed description of each register. Table 11.1. Special Function Register (SFR) Memory Map F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 SPI0CN B ADC0CN ACC PCA0CN PSW TMR2CN SMB0CN IP P0ODEN IE P2 SCON0 P1 TCON P0 0(8) (bit addressable) PCA0L P0MDIN PCA0CPL1 XBR0 PCA0MD REF0CN REG0CN SMB0CF IDA0CN OSCXCN CLKSEL SPI0CFG SBUF0 TMR3CN TMOD SP 1(9) PCA0H PCA0CPL0 PCA0CPH0 PCA0CPL4 PCA0CPH4 P1MDIN P2MDIN IDA1L IDA1H EIP1 PCA0CPH1 PCA0CPL2 PCA0CPH2 PCA0CPL3 PCA0CPH3 XBR1 PFE0CN IT01CF EIE1 PCA0CPM0 PCA0CPM1 PCA0CPM2 PCA0CPM3 PCA0CPM4 PCA0CPL5 PCA0CPH5 P0SKIP P1SKIP P2SKIP TMR2RLL TMR2RLH TMR2L TMR2H PCA0CPM5 SMB0DAT ADC0GTL ADC0GTH ADC0LTL ADC0LTH ADC0TK ADC0MX ADC0CF ADC0L ADC0H OSCICN OSCICL IDA1CN FLSCL EMI0CN CLKMUL RTC0ADR RTC0DAT RTC0KEY SPI0CKR SPI0DAT P0MDOUT P1MDOUT P2MDOUT CPT1CN CPT0CN CPT1MD CPT0MD CPT1MX TMR3RLL TMR3RLH TMR3L TMR3H IDA0L TL0 TL1 TH0 TH1 CKCON DPL DPH CRC0CN CRC0IN CRC0DAT 2(A) 3(B) 4(C) 5(D) 6(E) VDM0CN EIP2 RSTSRC EIE2 CRC0FLIP P0MAT P1MAT P0MASK P1MASK FLKEY ONESHOT CPT0MX IDA0H PSCTL PCON 7(F) Rev. 1.0 105 C8051F410/1/2/3 Table 11.2. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register ACC ADC0CF ADC0CN ADC0H ADC0L ADC0GTH ADC0GTL ADC0LTH ADC0LTL ADC0MX ADC0TK B CKCON CLKMUL CLKSEL CPT0CN CPT0MD CPT0MX CPT1CN CPT1MD CPT1MX CRC0CN CRC0IN CRC0DAT CRC0FLIP DPH DPL EIE1 EIE2 EIP1 EIP2 EMI0CN FLKEY FLSCL IDA0H IDA0L IDA0CN IDA1H Address 0xE0 0xBC 0xE8 0xBE 0xBD 0xC4 0xC3 0xC6 0xC5 0xC6 0xBA 0xF0 0x8E 0xAB 0xA9 0x9B 0x9D 0x9F 0x9A 0x9C 0x9E 0x84 0x85 0x86 0xDF 0x83 0x82 0xE6 0xE7 0xF6 0xF7 0xAA 0xB7 0xB6 0x97 0x96 0xB9 0xF5 Accumulator ADC0 Configuration ADC0 Control ADC0 ADC0 Description Page 101 60 62 61 61 64 64 65 65 59 63 101 237 173 174 86 88 87 91 90 89 124 124 125 125 99 99 114 116 115 116 145 141 142 71 72 71 73 ADC0 Greater-Than Data High Byte ADC0 Greater-Than Data Low Byte ADC0 Less-Than Data High Byte ADC0 Less-Than Data Low Byte ADC0 Channel Select ADC0 Tracking Mode Select B Register Clock Control Clock Multiplier Clock Select Comparator0 Control Comparator0 Mode Selection Comparator0 MUX Selection Comparator1 Control Comparator1 Mode Selection Comparator1 MUX Selection CRC0 Control CRC0 Data Input CRC0 Data Output CRC0 Bit Flip Data Pointer High Data Pointer Low Extended Interrupt Enable 1 Extended Interrupt Enable 2 Extended Interrupt Priority 1 Extended Interrupt Priority 2 External Memory Interface Control Flash Lock and Key Flash Scale Current Mode DAC0 High Byte Current Mode DAC0 Low Byte Current Mode DAC0 Control Current Mode DAC1 High Byte 106 Rev. 1.0 C8051F410/1/2/3 Table 11.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register IDA1L IDA1CN IE IP IT01CF ONESHOT OSCICL OSCICN OSCXCN P0 P0MASK P0MAT P0MDIN P0MDOUT P0ODEN P0SKIP P1 P1MASK P1MAT P1MDIN P1MDOUT P1SKIP P2 P2MDIN P2MDOUT P2SKIP PCA0CN PCA0CPH0 PCA0CPH1 PCA0CPH2 PCA0CPH3 PCA0CPH4 PCA0CPH5 PCA0CPL0 PCA0CPL1 PCA0CPL2 PCA0CPL3 PCA0CPL4 Address 0xF4 0xB5 0xA8 0xB8 0xE4 0xAF 0xB3 0xB2 0xB1 0x80 0xC7 0xD7 0xF1 0xA4 0xB0 0xD4 0x90 0xBF 0xCF 0xF2 0xA5 0xD5 0xA0 0xF3 0xA6 0xD6 0xD8 0xFC 0xEA 0xEC 0xEE 0xFE 0xD3 0xFB 0xE9 0xEB 0xED 0xFD Description Current Mode DAC1 Low Byte Current Mode DAC1 Control Interrupt Enable Interrupt Priority INT0/INT1 Configuration Flash Oneshot Period Internal Oscillator Calibration Internal Oscillator Control External Oscillator Control Port 0 Latch Port 0 Mask Port 0 Match Port 0 Input Mode Configuration Port 0 Output Mode Configuration Port 0 Overdrive Port 0 Skip Port 1 Latch Port 1 Mask Port 1 Match Port 1 Input Mode Configuration Port 1 Output Mode Configuration Port 1 Skip Port 2 Latch Port 2 Input Mode Configuration Port 2 Output Mode Configuration Port 2 Skip PCA Control PCA Capture 0 High PCA Capture 1 High PCA Capture 2 High PCA Capture 3 High PCA Capture 4 High PCA Capture 5 High PCA Capture 0 Low PCA Capture 1 Low PCA Capture 2 Low PCA Capture 3 Low PCA Capture 4 Low Page 73 72 112 113 118 143 167 167 171 155 157 157 155 156 157 156 158 160 160 158 159 159 161 161 162 162 261 264 264 264 264 264 264 264 264 264 264 264 Rev. 1.0 107 C8051F410/1/2/3 Table 11.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register PCA0CPL5 PCA0CPM0 PCA0CPM1 PCA0CPM2 PCA0CPM3 PCA0CPM4 PCA0CPM5 PCA0H PCA0L PCA0MD PCON PFE0CN PSCTL PSW REF0CN REG0CN RTC0ADR RTC0DAT RTC0KEY RSTSRC SBUF0 SCON0 SMB0CF SMB0CN SMB0DAT SP SPI0CFG SPI0CKR SPI0CN SPI0DAT TCON TH0 TH1 TL0 TL1 TMOD TMR2CN TMR2H Address 0xD2 0xDA 0xDB 0xDC 0xDD 0xDE 0xCE 0xFA 0xF9 0xD9 0x87 0xE3 0x8F 0xD0 0xD1 0xC9 0xAC 0xAD 0xAE 0xEF 0x99 0x98 0xC1 0xC0 0xC2 0x81 0xA1 0xA2 0xF8 0xA3 0x88 0x8C 0x8D 0x8A 0x8B 0x89 0xC8 0xCD PCA Capture 5 Low PCA Module 0 Mode PCA Module 1 Mode PCA Module 2 Mode PCA Module 3 Mode PCA Module 4 Mode PCA Module 5 Mode PCA Counter High PCA Counter Low PCA Mode Power Control Prefetch Engine Control Description Page 264 263 263 263 263 263 263 264 264 262 102 119 141 100 78 82 181 182 180 133 213 212 197 199 201 98 223 225 224 226 235 238 238 238 238 236 242 243 Program Store R/W Control Program Status Word Voltage Reference Control Voltage Regulator Control smaRTClock Address smaRTClock Data smaRTClock Lock and Key Reset Source Configuration/Status UART0 Data Buffer UART0 Control SMBus Configuration SMBus Control SMBus Data Stack Pointer SPI Configuration SPI Clock Rate Control SPI Control SPI Data Timer/Counter Control Timer/Counter 0 High Timer/Counter 1 High Timer/Counter 0 Low Timer/Counter 1 Low Timer/Counter Mode Timer/Counter 2 Control Timer/Counter 2 High 108 Rev. 1.0 C8051F410/1/2/3 Table 11.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register TMR2L TMR2RLH TMR2RLL TMR3CN TMR3H TMR3L TMR3RLH TMR3RLL VDM0CN XBR0 XBR1 Address 0xCC 0xCB 0xCA 0x91 0x95 0x94 0x93 0x92 0xFF 0xE1 0xE2 Timer/Counter 2 Low Description Timer/Counter 2 Reload High Timer/Counter 2 Reload Low Timer/Counter 3Control Timer/Counter 3 High Timer/Counter 3 Low Timer/Counter 3 Reload High Timer/Counter 3 Reload Low VDD Monitor Control Port I/O Crossbar Control 0 Port I/O Crossbar Control 1 Page 243 243 243 247 248 248 248 248 130 153 154 Rev. 1.0 109 C8051F410/1/2/3 12. Interrupt Handler The C8051F41x family includes an extended interrupt system supporting a total of 18 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and external input pins varies according to the specific version of the device. Each interrupt source has one or more associated interrupt-pending flag(s) located in an SFR. When a peripheral or external source meets a valid interrupt condition, the associated interrupt-pending flag is set to logic 1. If interrupts are enabled for the source, an interrupt request is generated when the interrupt-pending flag is set. As soon as execution of the current instruction is complete, the CPU generates an LCALL to a predetermined address to begin execution of an interrupt service routine (ISR). Each ISR must end with an RETI instruction, which returns program execution to the next instruction that would have been executed if the interrupt request had not occurred. If interrupts are not enabled, the interrupt-pending flag is ignored by the hardware and program execution continues as normal. (The interrupt-pending flag is set to logic 1 regardless of the interrupt's enable/disable state.) Each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in the Interrupt Enable and Extended Interrupt Enable SFRs. However, interrupts must first be globally enabled by setting the EA bit (IE.7) to logic 1 before the individual interrupt enables are recognized. Setting the EA bit to logic 0 disables all interrupt sources regardless of the individual interruptenable settings. Note that interrupts which occur when the EA bit is set to logic 0 will be held in a pending state, and will not be serviced until the EA bit is set back to logic 1. Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR. However, most are not cleared by the hardware and must be cleared by software before returning from the ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI) instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after the completion of the next instruction. 12.1. MCU Interrupt Sources and Vectors The MCUs support 18 interrupt sources. Software can simulate an interrupt by setting any interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated and the CPU will vector to the ISR address associated with the interrupt-pending flag. MCU interrupt sources, associated vector addresses, priority order, and control bits are summarized in Table 12.1 on page 111. Refer to the data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). 12.2. Interrupt Priorities Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP or EIP1) used to configure its priority level. Low priority is the default. If two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is used to arbitrate, given in Table 12.1. 12.3. Interrupt Latency Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 7 system clock cycles: 1 clock cycle to detect the interrupt, 1 clock cycle to execute a single instruction, and 5 clock cycles to complete the LCALL to the ISR. If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL is made to service the pending interrupt. Therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is performing an RETI instruction followed by a DIV as the next 110 Rev. 1.0 C8051F410/1/2/3 instruction. In this case, the response time is 19 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the RETI, 8 clock cycles to complete the DIV instruction and 5 clock cycles to execute the LCALL to the ISR. If the CPU is executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the current ISR completes, including the RETI and following instruction. Table 12.1. Interrupt Summary Bit addressable? Cleared by HW? Interrupt Source Interrupt Priority Pending Flag Vector Order Enable Flag Priority Control Reset External Interrupt 0 (/INT0) Timer 0 Overflow External Interrupt 1 (/INT1) Timer 1 Overflow UART0 Timer 2 Overflow 0x0000 0x0003 0x000B 0x0013 0x001B 0x0023 0x002B Top 0 1 2 3 4 5 None IE0 (TCON.1) TF0 (TCON.5) IE1 (TCON.3) TF1 (TCON.7) RI0 (SCON0.0) TI0 (SCON0.1) TF2H (TMR2CN.7) TF2L (TMR2CN.6) SPIF (SPI0CN.7) WCOL (SPI0CN.6) MODF (SPI0CN.5) RXOVRN (SPI0CN.4) SI (SMB0CN.0) ALRM (RTC0CN.2) OSCFAIL (RTC0CN.5) AD0WINT (ADC0CN.3) N/A N/A Y Y Y Y Y Y Y Y Y Y N N Always Enabled EX0 (IE.0) ET0 (IE.1) EX1 (IE.2) ET1 (IE.3) ES0 (IE.4) ET2 (IE.5) ESPI0 (IE.6) ESMB0 (EIE1.0) ERTC0 (EIE1.1) Always Highest PX0 (IP.0) PT0 (IP.1) PX1 (IP.2) PT1 (IP.3) PS0 (IP.4) PT2 (IP.5) PSPI0 (IP.6) PSMB0 (EIP1.0) PRTC0 (EIP1.1) PWADC0 (EIP1.2) PADC0 (EIP1.3) PPCA0 (EIP1.4) PCP0 (EIP1.5) PCP1 (EIP1.6) PT3 (EIP1.7) PREG0 (EIP2.0) PMAT (EIP2.1) SPI0 0x0033 6 Y N SMB0 smaRTClock ADC0 Window Comparator ADC0 End of Conversion Programmable Counter Array Comparator0 Comparator1 Timer 3 Overflow 0x003B 0x0043 0x004B 0x0053 0x005B 0x0063 0x006B 0x0073 7 8 9 10 11 12 13 14 15 16 Y N Y N N N Voltage Regulator Dropout 0x007B Port Match 0x0083 EWADC0 (EIE1.2) EADC0 AD0INT (ADC0STA.5) Y N (EIE1.3) CF (PCA0CN.7) EPCA0 Y N (EIE1.4) CCFn (PCA0CN.n) CP0FIF (CPT0CN.4) ECP0 N N CP0RIF (CPT0CN.5) (EIE1.5) CP1FIF (CPT1CN.4) ECP1 N N (EIE1.6) CP1RIF (CPT1CN.5) TF3H (TMR3CN.7) ET3 N N (EIE1.7) TF3L (TMR3CN.6) EREG0 N/A N/A N/A (EIE2.0) EMAT N/A N/A N/A (EIE2.1) Rev. 1.0 111 C8051F410/1/2/3 12.4. Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). SFR Definition 12.1. IE: Interrupt Enable R/W R/W R/W R/W R/W R/W R/W R/W Reset Value EA Bit7 ESPI0 Bit6 ET2 Bit5 ES0 Bit4 ET1 Bit3 EX1 Bit2 ET0 Bit1 EX0 Bit0 00000000 Bit Addressable SFR Address: 0xA8 Bit 7: Bit 6: Bit 5: Bit 4: Bit 3: Bit 2: Bit 1: Bit 0: EA: Global Interrupt Enable. This bit globally enables/disables all interrupts. It overrides the individual interrupt mask settings. 0: Disable all interrupt sources. 1: Enable each interrupt according to its individual mask setting. ESPI0: Enable Serial Peripheral Interface (SPI0) Interrupt. This bit sets the masking of the SPI0 interrupts. 0: Disable all SPI0 interrupts. 1: Enable interrupt requests generated by SPI0. ET2: Enable Timer 2 Interrupt. This bit sets the masking of the Timer 2 interrupt. 0: Disable Timer 2 interrupt. 1: Enable interrupt requests generated by the TF2L or TF2H flags. ES0: Enable UART0 Interrupt. This bit sets the masking of the UART0 interrupt. 0: Disable UART0 interrupt. 1: Enable UART0 interrupt. ET1: Enable Timer 1 Interrupt. This bit sets the masking of the Timer 1 interrupt. 0: Disable all Timer 1 interrupt. 1: Enable interrupt requests generated by the TF1 flag. EX1: Enable External Interrupt 1. This bit sets the masking of External Interrupt 1. 0: Disable external interrupt 1. 1: Enable interrupt requests generated by the /INT1 input. ET0: Enable Timer 0 Interrupt. This bit sets the masking of the Timer 0 interrupt. 0: Disable all Timer 0 interrupt. 1: Enable interrupt requests generated by the TF0 flag. EX0: Enable External Interrupt 0. This bit sets the masking of External Interrupt 0. 0: Disable external interrupt 0. 1: Enable interrupt requests generated by the /INT0 input. 112 Rev. 1.0 C8051F410/1/2/3 SFR Definition 12.2. IP: Interrupt Priority R R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 PSPI0 Bit6 PT2 Bit5 PS0 Bit4 PT1 Bit3 PX1 Bit2 PT0 Bit1 PX0 Bit0 10000000 Bit Addressable SFR Address: 0xB8 Bit 7: Bit 6: Bit 5: Bit 4: Bit 3: Bit 2: Bit 1: Bit 0: UNUSED. Read = 1, Write = don't care. PSPI0: Serial Peripheral Interface (SPI0) Interrupt Priority Control. This bit sets the priority of the SPI0 interrupt. 0: SPI0 interrupt set to low priority level. 1: SPI0 interrupt set to high priority level. PT2: Timer 2 Interrupt Priority Control. This bit sets the priority of the Timer 2 interrupt. 0: Timer 2 interrupt set to low priority level. 1: Timer 2 interrupt set to high priority level. PS0: UART0 Interrupt Priority Control. This bit sets the priority of the UART0 interrupt. 0: UART0 interrupt set to low priority level. 1: UART0 interrupt set to high priority level. PT1: Timer 1 Interrupt Priority Control. This bit sets the priority of the Timer 1 interrupt. 0: Timer 1 interrupt set to low priority level. 1: Timer 1 interrupt set to high priority level. PX1: External Interrupt 1 Priority Control. This bit sets the priority of the External Interrupt 1 interrupt. 0: External Interrupt 1 set to low priority level. 1: External Interrupt 1 set to high priority level. PT0: Timer 0 Interrupt Priority Control. This bit sets the priority of the Timer 0 interrupt. 0: Timer 0 interrupt set to low priority level. 1: Timer 0 interrupt set to high priority level. PX0: External Interrupt 0 Priority Control. This bit sets the priority of the External Interrupt 0 interrupt. 0: External Interrupt 0 set to low priority level. 1: External Interrupt 0 set to high priority level. Rev. 1.0 113 C8051F410/1/2/3 SFR Definition 12.3. EIE1: Extended Interrupt Enable 1 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value ET3 Bit7 ECP1 Bit6 ECP0 Bit5 EPCA0 Bit4 EADC0 Bit3 EWADC0 Bit2 ERTC0 Bit1 ESMB0 Bit0 00000000 SFR Address: 0xE6 Bit 7: Bit 6: Bit 5: Bit 4: Bit 3: Bit 2: Bit 1: Bit 0: ET3: Enable Timer 3 Interrupt. This bit sets the masking of the Timer 3 interrupt. 0: Disable Timer 3 interrupts. 1: Enable interrupt requests generated by the TF3L or TF3H flags. ECP1: Enable Comparator1 (CP1) Interrupt. This bit sets the masking of the CP1 interrupt. 0: Disable CP1 interrupts. 1: Enable interrupt requests generated by the CP1RIF or CP1FIF flags. ECP0: Enable Comparator0 (CP0) Interrupt. This bit sets the masking of the CP0 interrupt. 0: Disable CP0 interrupts. 1: Enable interrupt requests generated by the CP0RIF or CP0FIF flags. EPCA0: Enable Programmable Counter Array (PCA0) Interrupt. This bit sets the masking of the PCA0 interrupts. 0: Disable all PCA0 interrupts. 1: Enable interrupt requests generated by PCA0. EADC0: Enable ADC0 Conversion Complete Interrupt. This bit sets the masking of the ADC0 Conversion Complete interrupt. 0: Disable ADC0 Conversion Complete interrupt. 1: Enable interrupt requests generated by the AD0INT flag. EWADC0: Enable ADC0 Window Comparison Interrupt. This bit sets the masking of the ADC0 Window Comparison interrupt. 0: Disable ADC0 Window Comparison interrupt. 1: Enable interrupt requests generated by the AD0WINT flag. ERTC0: Enable smaRTClock Interrupt. This bit sets the masking of the smaRTClock interrupt. 0: Disable smaRTClock interrupts. 1: Enable interrupt requests generated by the ALRM and OSCFAIL flag. ESMB0: Enable SMBus (SMB0) Interrupt. This bit sets the masking of the SMB0 interrupt. 0: Disable all SMB0 interrupts. 1: Enable interrupt requests generated by SMB0. 114 Rev. 1.0 C8051F410/1/2/3 SFR Definition 12.4. EIP1: Extended Interrupt Priority 1 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value PT3 Bit7 PCP1 Bit6 PCP0 Bit5 PPCA0 Bit4 PADC0 Bit3 PWADC0 Bit2 PRTC0 Bit1 PSMB0 Bit0 00000000 SFR Address: 0xF6 Bit 7: Bit 6: Bit 5: Bit 4: Bit 3: Bit 2: Bit 1: Bit 0: PT3: Timer 3 Interrupt Priority Control. This bit sets the priority of the Timer 3 interrupt. 0: Timer 3 interrupts set to low priority level. 1: Timer 3 interrupts set to high priority level. PCP1: Comparator1 (CP1) Interrupt Priority Control. This bit sets the priority of the CP1 interrupt. 0: CP1 interrupt set to low priority level. 1: CP1 interrupt set to high priority level. PCP0: Comparator0 (CP0) Interrupt Priority Control. This bit sets the priority of the CP0 interrupt. 0: CP0 interrupt set to low priority level. 1: CP0 interrupt set to high priority level. PPCA0: Programmable Counter Array (PCA0) Interrupt Priority Control. This bit sets the priority of the PCA0 interrupt. 0: PCA0 interrupt set to low priority level. 1: PCA0 interrupt set to high priority level. PADC0: ADC0 Conversion Complete Interrupt Priority Control. This bit sets the priority of the ADC0 Conversion Complete interrupt. 0: ADC0 Conversion Complete interrupt set to low priority level. 1: ADC0 Conversion Complete interrupt set to high priority level. PWADC0: ADC0 Window Comparison Interrupt Priority Control. This bit sets the priority of the ADC0 Window Comparison interrupt. 0: ADC0 Window Comparison interrupt set to low priority level. 1: ADC0 Window Comparison interrupt set to high priority level. PRTC0: smaRTClock Interrupt Priority Control. This bit sets the priority of the smaRTClock interrupt. 0: smaRTClock interrupt set to low priority level. 1: smaRTClock interrupt set to high priority level. PSMB0: SMBus (SMB0) Interrupt Priority Control. This bit sets the priority of the SMB0 interrupt. 0: SMB0 interrupt set to low priority level. 1: SMB0 interrupt set to high priority level. Rev. 1.0 115 C8051F410/1/2/3 SFR Definition 12.5. EIE2: Extended Interrupt Enable 2 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 EMAT Bit1 EREG0 Bit0 00000000 SFR Address: 0xE7 Bits 7–2: UNUSED. Read = 000000b. Write = don’t care. Bit 1: EMAT: Enable Port Match Interrupt. This bit sets the masking of the Port Match interrupt. 0: Disable the Port Match interrupt. 1: Enable the Port Match interrupt. Bit 0: EREG0: Enable Voltage Regulator Interrupt. This bit sets the masking of the Voltage Regulator Dropout interrupt. 0: Disable the Voltage Regulator Dropout interrupt. 1: Enable the Voltage Regulator Dropout interrupt. SFR Definition 12.6. EIP2: Extended Interrupt Priority 2 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 PMAT Bit1 PREG0 Bit0 00000000 SFR Address: 0xF7 Bits 7–2: UNUSED. Read = 000000b. Write = don’t care. Bit 1: EMAT: Port Match Interrupt Priority Control. This bit sets the priority of the Port Match interrupt. 0: Port Match interrupt set to low priority level. 1: Port Match interrupt set to high priority level. Bit 0: PREG0: Voltage Regulator Interrupt Priority Control. This bit sets the priority of the Voltage Regulator interrupt. 0: Voltage Regulator interrupt set to low priority level. 1: Voltage Regulator interrupt set to high priority level. 116 Rev. 1.0 C8051F410/1/2/3 12.5. External Interrupts The /INT0 and /INT1 external interrupt sources are configurable as active high or low, edge or level sensitive. The IN0PL (/INT0 Polarity) and IN1PL (/INT1 Polarity) bits in the IT01CF register select active high or active low; the IT0 and IT1 bits in TCON (Section “24.1. Timer 0 and Timer 1” on page 231) select level or edge sensitive. The table below lists the possible configurations. IT0 1 1 0 0 IN0PL 0 1 0 1 /INT0 Interrupt Active low, edge sensitive Active high, edge sensitive Active low, level sensitive Active high, level sensitive IT1 1 1 0 0 IN1PL 0 1 0 1 /INT1 Interrupt Active low, edge sensitive Active high, edge sensitive Active low, level sensitive Active high, level sensitive /INT0 and /INT1 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 12.7). Note that /INT0 and /INT0 Port pin assignments are independent of any Crossbar assignments. /INT0 and /INT1 will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin via the Crossbar. To assign a Port pin only to /INT0 and/or /INT1, configure the Crossbar to skip the selected pin(s). This is accomplished by setting the associated bit in register XBR0 (see Section “18.1. Priority Crossbar Decoder” on page 149 for complete details on configuring the Crossbar). IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the /INT0 and /INT1 external interrupts, respectively. If an /INT0 or /INT1 external interrupt is configured as edge-sensitive, the corresponding interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inactive. The external interrupt source must hold the input active until the interrupt request is recognized. It must then deactivate the interrupt request before execution of the ISR completes or another interrupt request will be generated. Rev. 1.0 117 C8051F410/1/2/3 SFR Definition 12.7. IT01CF: INT0/INT1 Configuration R/W R/W R/W R/W R/W R/W R/W R/W Reset Value IN1PL Bit7 IN1SL2 Bit6 IN1SL1 Bit5 IN1SL0 Bit4 IN0PL Bit3 IN0SL2 Bit2 IN0SL1 Bit1 IN0SL0 Bit0 00000001 SFR Address: 0xE4 Note: Refer to SFR Definition 24.1. “TCON: Timer Control” on page 235 for INT0/1 edge- or level-sensitive interrupt selection. Bit 7: IN1PL: /INT1 Polarity 0: /INT1 input is active low. 1: /INT1 input is active high. Bits 6–4: IN1SL2–0: /INT1 Port Pin Selection Bits These bits select which Port pin is assigned to /INT1. Note that this pin assignment is independent of the Crossbar; /INT1 will monitor the assigned Port pin without disturbing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar will not assign the Port pin to a peripheral if it is configured to skip the selected pin (accomplished by setting to ‘1’ the corresponding bit in register P0SKIP). IN1SL2–0 000 001 010 011 100 101 110 111 Bit 3: /INT1 Port Pin P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 IN0PL: /INT0 Polarity 0: /INT0 interrupt is active low. 1: /INT0 interrupt is active high. Bits 2–0: INT0SL2–0: /INT0 Port Pin Selection Bits These bits select which Port pin is assigned to /INT0. Note that this pin assignment is independent of the Crossbar. /INT0 will monitor the assigned Port pin without disturbing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar will not assign the Port pin to a peripheral if it is configured to skip the selected pin (accomplished by setting to ‘1’ the corresponding bit in register P0SKIP). IN0SL2–0 000 001 010 011 100 101 110 111 /INT0 Port Pin P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 118 Rev. 1.0 C8051F410/1/2/3 13. Prefetch Engine The C8051F41x family of devices incorporate a 2-byte prefetch engine. Due to Flash access time specifications, the prefetch engine is necessary for full-speed (50 MHz) code execution. Instructions are read from Flash memory two bytes at a time by the prefetch engine, and given to the CIP-51 processor core to execute. When running linear code (code without any jumps or branches), the prefetch engine allows instructions to be executed at full speed. When a code branch occurs, the processor may be stalled for up to two clock cycles while the next set of code bytes is retrieved from Flash memory. The FLRT bit (FLSCL.4) determines how many clock cycles are used to read each set of two code bytes from Flash. When operating from a system clock of 25 MHz or less, the FLRT bit should be set to ‘0’ so that the prefetch engine takes only one clock cycle for each read. When operating with a system clock of greater than 25 MHz (up to 50 MHz), the FLRT bit should be set to ‘1’, so that each prefetch code read lasts for two clock cycles. SFR Definition 13.1. PFE0CN: Prefetch Engine Control R Bit7 R Bit6 R/W R Bit4 R Bit3 R Bit2 R Bit1 R/W Reset Value PFEN Bit5 FLBWE Bit0 00100000 SFR Address: 0xE3 Bits 7–6: Unused. Read = 00b; Write = Don’t Care Bit 5: PFEN: Prefetch Enable. This bit enables the prefetch engine. 0: Prefetch engine is disabled. 1: Prefetch engine is enabled. Bits 4–1: Unused. Read = 0000b; Write = Don’t Care Bit 0: FLBWE: Flash Block Write Enable. This bit allows block writes to Flash memory from software. 0: Each byte of a software Flash write is written individually. 1: Flash bytes are written in groups of two. Note: The prefetch engine should be disabled when changes to FLRT are made. See Section “16. Flash Memory” on page 135. Rev. 1.0 119 C8051F410/1/2/3 NOTES: 120 Rev. 1.0 C8051F410/1/2/3 14. Cyclic Redundancy Check Unit (CRC0) C8051F41x devices include a cyclic redundancy check unit (CRC0) that can perform a CRC using a 16-bit or 32-bit polynomial. CRC0 accepts a stream of 8-bit data written to the CRC0IN register. CRC0 posts the 16-bit or 32-bit result to an internal register. The internal result register may be accessed indirectly using the CRC0PNT bits and CRC0DAT register, as shown in Figure 14.1. CRC0 also has a bit reverse register for quick data manipulation. CRC0IN 8 CRC0CN CRC0SEL CRC0INIT CRC0VAL CRC0PNT1 CRC0PNT0 CRC Engine 32 RESULT 8 8 8 4 to 1 MUX 8 8 CRC0DAT Figure 14.1. CRC0 Block Diagram 14.1. CRC Algorithm The C8051F41x CRC unit generates a CRC result equivalent to the following algorithm: Step 1. XOR the input with the most-significant bytes of the current CRC result. If this is the first iteration of the CRC unit, the current CRC result will be the set initial value (0x00000000 or 0xFFFFFFFF). Step 2a. If the MSB of the CRC result is set, shift the CRC result and XOR the result with the selected polynomial. Step 2b. If the MSB of the CRC result is not set, shift the CRC result. Step 3. Repeat Steps 2a/2b for the number of input bits (8). Rev. 1.0 121 C8051F410/1/2/3 For example, the 16-bit 'F41x CRC algorithm can be described by the following code: unsigned short UpdateCRC (unsigned short CRC_acc, unsigned char CRC_input) { unsigned char i; // loop counter #define POLY 0x1021 // Create the CRC "dividend" for polynomial arithmetic (binary arithmetic // with no carries) CRC_acc = CRC_acc ^ (CRC_input