C8051F80x-83x
Mixed Signal ISP Flash MCU Family
Capacitance to Digital Converter
- Supports buttons, sliders, wheels, and capacitive
High-Speed 8051 μC Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
-
512-byte sectors
ble), and enhanced SPI™ serial ports
Three general purpose 16-bit counter/timers
16-Bit programmable counter array (PCA) with 3
capture/compare modules and enhanced PWM
functionality
Real time clock mode using timer and crystal
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Digital Peripherals
- 17 or 13 Port I/O with high sink current
- Hardware enhanced UART, SMBus™ (I2C compati-
Clock Sources
- 24.5 MHz ±2% Oscillator
• Supports crystal-less UART operation
- External oscillator: Crystal, RC, C, or clock
-
(1 or 2 pin modes)
Can switch between clock sources on-the-fly; useful
in power saving modes
Supply Voltage 1.8 to 3.6 V
- Built-in voltage supply monitor
24-Pin QSOP, 20-Pin QFN, 16-Pin SOIC
Temperature Range: –40 to +85 °C
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intrusive in-system debug (no emulator required)
Provides breakpoints, single stepping,
inspect/modify memory and registers
Superior performance to emulation systems using
ICE-chips, target pods, and sockets
Low cost, complete development kit
- Up to 25 MIPS throughput with 25 MHz clock
- Expanded interrupt handler
Memory
- Up to 512 bytes internal data RAM (256 + 256)
- Up to 16 kB Flash; In-system programmable in
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proximity sensing
- Fast 40 μs per channel conversion time
- 16-bit resolution
- Up to 16 input channels
- Auto-scan and wake-on-touch
- Auto-accumulate 4x, 8x, 16, 32x, and 64x samples
Analog Peripherals
- 10-Bit ADC
• Up to 500 ksps
• Up to 16 external single-ended inputs
• VREF from on-chip VREF, external pin or VDD
• Internal or external start of conversion source
• Built-in temperature sensor
- Comparator
• Programmable hysteresis and response time
• Configurable as interrupt or reset source
On-Chip Debug
- On-chip debug circuitry facilitates full speed, non-
Rev. 1.1 3/22
Copyright © 2022 by Silicon Laboratories
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C8051F80x-83x
2
Rev. 1.1
C8051F80x-83x
Table of Contents
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1. System Overview ..................................................................................................... 15
2. Ordering Information ............................................................................................... 25
3. Pin Definitions.......................................................................................................... 28
4. QFN-20 Package Specifications ............................................................................. 33
5. QSOP-24 Package Specifications .......................................................................... 35
6. SOIC-16 Package Specifications ............................................................................ 37
7. Electrical Characteristics ........................................................................................ 39
7.1. Absolute Maximum Specifications..................................................................... 39
7.2. Electrical Characteristics ................................................................................... 40
8. 10-Bit ADC (ADC0) ................................................................................................... 46
8.1. Output Code Formatting .................................................................................... 47
8.2. 8-Bit Mode ......................................................................................................... 47
8.3. Modes of Operation ........................................................................................... 47
8.3.1. Starting a Conversion................................................................................ 47
8.3.2. Tracking Modes......................................................................................... 48
8.3.3. Settling Time Requirements...................................................................... 49
8.4. Programmable Window Detector....................................................................... 53
8.4.1. Window Detector Example........................................................................ 55
8.5. ADC0 Analog Multiplexer .................................................................................. 56
9. Temperature Sensor ................................................................................................ 58
9.1. Calibration ......................................................................................................... 58
10. Voltage and Ground Reference Options.............................................................. 60
10.1. External Voltage References........................................................................... 61
10.2. Internal Voltage Reference Options ................................................................ 61
10.3. Analog Ground Reference............................................................................... 61
10.4. Temperature Sensor Enable ........................................................................... 61
11. Voltage Regulator (REG0) ..................................................................................... 63
12. Comparator0........................................................................................................... 65
12.1. Comparator Multiplexer ................................................................................... 69
13. Capacitive Sense (CS0) ......................................................................................... 71
13.1. Configuring Port Pins as Capacitive Sense Inputs .......................................... 72
13.2. Capacitive Sense Start-Of-Conversion Sources ............................................. 72
13.3. Automatic Scanning......................................................................................... 72
13.4. CS0 Comparator.............................................................................................. 73
13.5. CS0 Conversion Accumulator ......................................................................... 74
13.6. Capacitive Sense Multiplexer .......................................................................... 80
14. CIP-51 Microcontroller........................................................................................... 82
14.1. Instruction Set.................................................................................................. 83
14.1.1. Instruction and CPU Timing .................................................................... 83
14.2. CIP-51 Register Descriptions .......................................................................... 88
15. Memory Organization ............................................................................................ 92
15.1. Program Memory............................................................................................. 93
15.1.1. MOVX Instruction and Program Memory ................................................ 93
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15.2. Data Memory ................................................................................................... 93
15.2.1. Internal RAM ........................................................................................... 93
15.2.1.1. General Purpose Registers ............................................................ 94
15.2.1.2. Bit Addressable Locations .............................................................. 94
15.2.1.3. Stack ............................................................................................ 94
16. In-System Device Identification............................................................................ 95
17. Special Function Registers................................................................................... 97
18. Interrupts .............................................................................................................. 102
18.1. MCU Interrupt Sources and Vectors.............................................................. 103
18.1.1. Interrupt Priorities.................................................................................. 103
18.1.2. Interrupt Latency ................................................................................... 103
18.2. Interrupt Register Descriptions ...................................................................... 104
18.3. INT0 and INT1 External Interrupts................................................................. 111
19. Flash Memory....................................................................................................... 113
19.1. Programming The Flash Memory .................................................................. 113
19.1.1. Flash Lock and Key Functions .............................................................. 113
19.1.2. Flash Erase Procedure ......................................................................... 113
19.1.3. Flash Write Procedure .......................................................................... 114
19.2. Non-volatile Data Storage ............................................................................. 114
19.3. Security Options ............................................................................................ 114
19.4. Flash Write and Erase Guidelines ................................................................. 115
19.4.1. VDD Maintenance and the VDD Monitor .............................................. 116
19.4.2. PSWE Maintenance .............................................................................. 116
19.4.3. System Clock ........................................................................................ 117
20. Power Management Modes................................................................................. 120
20.1. Idle Mode....................................................................................................... 120
20.2. Stop Mode ..................................................................................................... 121
20.3. Suspend Mode .............................................................................................. 121
21. Reset Sources ...................................................................................................... 123
21.1. Power-On Reset ............................................................................................ 124
21.2. Power-Fail Reset / VDD Monitor ................................................................... 125
21.3. External Reset ............................................................................................... 126
21.4. Missing Clock Detector Reset ....................................................................... 126
21.5. Comparator0 Reset ....................................................................................... 127
21.6. PCA Watchdog Timer Reset ......................................................................... 127
21.7. Flash Error Reset .......................................................................................... 127
21.8. Software Reset .............................................................................................. 127
22. Oscillators and Clock Selection ......................................................................... 129
22.1. System Clock Selection................................................................................. 129
22.2. Programmable Internal High-Frequency (H-F) Oscillator .............................. 131
22.3. External Oscillator Drive Circuit..................................................................... 133
22.3.1. External Crystal Example...................................................................... 135
22.3.2. External RC Example............................................................................ 136
22.3.3. External Capacitor Example.................................................................. 137
23. Port Input/Output ................................................................................................. 138
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23.1. Port I/O Modes of Operation.......................................................................... 139
23.1.1. Port Pins Configured for Analog I/O...................................................... 139
23.1.2. Port Pins Configured For Digital I/O...................................................... 139
23.1.3. Interfacing Port I/O to 5 V Logic ............................................................ 140
23.2. Assigning Port I/O Pins to Analog and Digital Functions............................... 140
23.2.1. Assigning Port I/O Pins to Analog Functions ........................................ 140
23.2.2. Assigning Port I/O Pins to Digital Functions.......................................... 141
23.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions ... 142
23.3. Priority Crossbar Decoder ............................................................................. 143
23.4. Port I/O Initialization ...................................................................................... 147
23.5. Port Match ..................................................................................................... 150
23.6. Special Function Registers for Accessing and Configuring Port I/O ............. 152
24. Cyclic Redundancy Check Unit (CRC0)............................................................. 159
24.1. 16-bit CRC Algorithm..................................................................................... 160
24.2. 32-bit CRC Algorithm..................................................................................... 161
24.3. Preparing for a CRC Calculation ................................................................... 162
24.4. Performing a CRC Calculation ...................................................................... 162
24.5. Accessing the CRC0 Result .......................................................................... 162
24.6. CRC0 Bit Reverse Feature............................................................................ 166
25. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 167
25.1. Signal Descriptions........................................................................................ 168
25.1.1. Master Out, Slave In (MOSI)................................................................. 168
25.1.2. Master In, Slave Out (MISO)................................................................. 168
25.1.3. Serial Clock (SCK) ................................................................................ 168
25.1.4. Slave Select (NSS) ............................................................................... 168
25.2. SPI0 Master Mode Operation ........................................................................ 168
25.3. SPI0 Slave Mode Operation .......................................................................... 170
25.4. SPI0 Interrupt Sources .................................................................................. 171
25.5. Serial Clock Phase and Polarity .................................................................... 171
25.6. SPI Special Function Registers ..................................................................... 173
26. SMBus................................................................................................................... 180
26.1. Supporting Documents .................................................................................. 181
26.2. SMBus Configuration..................................................................................... 181
26.3. SMBus Operation .......................................................................................... 181
26.3.1. Transmitter Vs. Receiver....................................................................... 182
26.3.2. Arbitration.............................................................................................. 182
26.3.3. Clock Low Extension............................................................................. 182
26.3.4. SCL Low Timeout.................................................................................. 182
26.3.5. SCL High (SMBus Free) Timeout ......................................................... 183
26.4. Using the SMBus........................................................................................... 183
26.4.1. SMBus Configuration Register.............................................................. 183
26.4.2. SMB0CN Control Register .................................................................... 187
26.4.2.1. Software ACK Generation ............................................................ 187
26.4.2.2. Hardware ACK Generation ........................................................... 187
26.4.3. Hardware Slave Address Recognition .................................................. 189
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26.4.4. Data Register ........................................................................................ 192
26.5. SMBus Transfer Modes................................................................................. 193
26.5.1. Write Sequence (Master) ...................................................................... 193
26.5.2. Read Sequence (Master) ...................................................................... 194
26.5.3. Write Sequence (Slave) ........................................................................ 195
26.5.4. Read Sequence (Slave) ........................................................................ 196
26.6. SMBus Status Decoding................................................................................ 196
27. UART0 ................................................................................................................... 201
27.1. Enhanced Baud Rate Generation.................................................................. 202
27.2. Operational Modes ........................................................................................ 203
27.2.1. 8-Bit UART ............................................................................................ 203
27.2.2. 9-Bit UART ............................................................................................ 204
27.3. Multiprocessor Communications ................................................................... 205
28. Timers ................................................................................................................... 209
28.1. Timer 0 and Timer 1 ...................................................................................... 211
28.1.1. Mode 0: 13-bit Counter/Timer ............................................................... 211
28.1.2. Mode 1: 16-bit Counter/Timer ............................................................... 212
28.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload..................................... 212
28.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................ 213
28.2. Timer 2 .......................................................................................................... 219
28.2.1. 16-bit Timer with Auto-Reload............................................................... 219
28.2.2. 8-bit Timers with Auto-Reload............................................................... 220
29. Programmable Counter Array............................................................................. 225
29.1. PCA Counter/Timer ....................................................................................... 226
29.2. PCA0 Interrupt Sources................................................................................. 227
29.3. Capture/Compare Modules ........................................................................... 228
29.3.1. Edge-Triggered Capture Mode ............................................................. 229
29.3.2. Software Timer (Compare) Mode.......................................................... 230
29.3.3. High-Speed Output Mode ..................................................................... 231
29.3.4. Frequency Output Mode ....................................................................... 232
29.3.5. 8-bit through 15-bit Pulse Width Modulator Modes .............................. 232
29.3.5.1. 8-bit Pulse Width Modulator Mode............................................... 233
29.3.5.2. 9-bit through 15-bit Pulse Width Modulator Mode ....................... 234
29.3.6. 16-Bit Pulse Width Modulator Mode..................................................... 235
29.4. Watchdog Timer Mode .................................................................................. 236
29.4.1. Watchdog Timer Operation ................................................................... 236
29.4.2. Watchdog Timer Usage ........................................................................ 237
29.5. Register Descriptions for PCA0..................................................................... 237
30. C2 Interface .......................................................................................................... 244
30.1. C2 Interface Registers................................................................................... 244
30.2. C2CK Pin Sharing ......................................................................................... 247
Document Change List.............................................................................................. 248
Contact Information................................................................................................... 250
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List of Tables
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1. System Overview
2. Ordering Information
Table 2.1. Product Selection Guide ......................................................................... 26
3. Pin Definitions
Table 3.1. Pin Definitions for the C8051F80x-83x ................................................... 28
4. QFN-20 Package Specifications
Table 4.1. QFN-20 Package Dimensions ................................................................ 33
Table 4.2. QFN-20 PCB Land Pattern Dimensions ................................................. 34
5. QSOP-24 Package Specifications
Table 5.1. QSOP-24 Package Dimensions ............................................................. 35
Table 5.2. QSOP-24 PCB Land Pattern Dimensions .............................................. 36
6. SOIC-16 Package Specifications
Table 6.1. SOIC-16 Package Dimensions ............................................................... 37
Table 6.2. SOIC-16 PCB Land Pattern Dimensions ................................................ 38
7. Electrical Characteristics
Table 7.1. Absolute Maximum Ratings .................................................................... 39
Table 7.2. Global Electrical Characteristics ............................................................. 40
Table 7.3. Port I/O DC Electrical Characteristics ..................................................... 41
Table 7.4. Reset Electrical Characteristics .............................................................. 41
Table 7.5. Internal Voltage Regulator Electrical Characteristics ............................. 41
Table 7.6. Flash Electrical Characteristics .............................................................. 42
Table 7.7. Internal High-Frequency Oscillator Electrical Characteristics ................. 42
Table 7.8. Capacitive Sense Electrical Characteristics ........................................... 42
Table 7.9. ADC0 Electrical Characteristics .............................................................. 43
Table 7.10. Power Management Electrical Characteristics ..................................... 44
Table 7.11. Temperature Sensor Electrical Characteristics .................................... 44
Table 7.12. Voltage Reference Electrical Characteristics ....................................... 44
Table 7.13. Comparator Electrical Characteristics .................................................. 45
8. 10-Bit ADC (ADC0)
9. Temperature Sensor
10. Voltage and Ground Reference Options
11. Voltage Regulator (REG0)
12. Comparator0
13. Capacitive Sense (CS0)
Table 13.1. Operation with Auto-scan and Accumulate .......................................... 74
14. CIP-51 Microcontroller
Table 14.1. CIP-51 Instruction Set Summary .......................................................... 84
15. Memory Organization
16. In-System Device Identification
17. Special Function Registers
Table 17.1. Special Function Register (SFR) Memory Map .................................... 97
Table 17.2. Special Function Registers ................................................................... 98
18. Interrupts
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Table 18.1. Interrupt Summary .............................................................................. 104
19. Flash Memory
Table 19.1. Flash Security Summary .................................................................... 115
20. Power Management Modes
21. Reset Sources
22. Oscillators and Clock Selection
23. Port Input/Output
Table 23.1. Port I/O Assignment for Analog Functions ......................................... 141
Table 23.2. Port I/O Assignment for Digital Functions ........................................... 142
Table 23.3. Port I/O Assignment for External Digital Event Capture Functions .... 142
24. Cyclic Redundancy Check Unit (CRC0)
Table 24.1. Example 16-bit CRC Outputs ............................................................. 160
Table 24.2. Example 32-bit CRC Outputs ............................................................. 161
25. Enhanced Serial Peripheral Interface (SPI0)
Table 25.1. SPI Slave Timing Parameters ............................................................ 179
26. SMBus
Table 26.1. SMBus Clock Source Selection .......................................................... 184
Table 26.2. Minimum SDA Setup and Hold Times ................................................ 185
Table 26.3. Sources for Hardware Changes to SMB0CN ..................................... 189
Table 26.4. Hardware Address Recognition Examples (EHACK = 1) ................... 190
Table 26.5. SMBus Status Decoding With Hardware ACK Generation Disabled
(EHACK = 0) ....................................................................................... 197
Table 26.6. SMBus Status Decoding With Hardware ACK Generation Enabled
(EHACK = 1) ....................................................................................... 199
27. UART0
Table 27.1. Timer Settings for Standard Baud Rates
Using The Internal 24.5 MHz Oscillator .............................................. 208
Table 27.2. Timer Settings for Standard Baud Rates
Using an External 22.1184 MHz Oscillator ......................................... 208
28. Timers
29. Programmable Counter Array
Table 29.1. PCA Timebase Input Options ............................................................. 226
Table 29.2. PCA0CPM and PCA0PWM Bit Settings for PCA Capture/Compare Modules1,2,3,4,5,6 ........................................................................................ 228
Table 29.3. Watchdog Timer Timeout Intervals1 ................................................... 237
30. C2 Interface
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List of Figures
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1. System Overview
Figure 1.1. C8051F800, C8051F806, C8051F812, C8051F818 Block Diagram ..... 16
Figure 1.2. C8051F801, C8051F807, C8051F813, C8051F819 Block Diagram ..... 17
Figure 1.3. C8051F802, C8051F808, C8051F814, C8051F820 Block Diagram ..... 18
Figure 1.4. C8051F803, C8051F809, C8051F815, C8051F821 Block Diagram ..... 19
Figure 1.5. C8051F804, C8051F810, C8051F816, C8051F822 Block Diagram ..... 20
Figure 1.6. C8051F805, C8051F811, C8051F817, C8051F823 Block Diagram ..... 21
Figure 1.7. C8051F824, C8051F827, C8051F830, C8051F833 Block Diagram ..... 22
Figure 1.8. C8051F825, C8051F828, C8051F831, C8051F834 Block Diagram ..... 23
Figure 1.9. C8051F826, C8051F829, C8051F832, C8051F835 Block Diagram ..... 24
2. Ordering Information
3. Pin Definitions
Figure 3.1. QFN-20 Pinout Diagram (Top View) ..................................................... 30
Figure 3.2. QSOP-24 Pinout Diagram (Top View) ................................................... 31
Figure 3.3. SOIC-16 Pinout Diagram (Top View) .................................................... 32
4. QFN-20 Package Specifications
Figure 4.1. QFN-20 Package Drawing .................................................................... 33
Figure 4.2. QFN-20 Recommended PCB Land Pattern .......................................... 34
5. QSOP-24 Package Specifications
Figure 5.1. QSOP-24 Package Drawing .................................................................. 35
Figure 5.2. QSOP-24 PCB Land Pattern ................................................................. 36
6. SOIC-16 Package Specifications
Figure 6.1. SOIC-16 Package Drawing ................................................................... 37
Figure 6.2. SOIC-16 PCB Land Pattern .................................................................. 38
7. Electrical Characteristics
8. 10-Bit ADC (ADC0)
Figure 8.1. ADC0 Functional Block Diagram ........................................................... 46
Figure 8.2. 10-Bit ADC Track and Conversion Example Timing ............................. 48
Figure 8.3. ADC0 Equivalent Input Circuits ............................................................. 49
Figure 8.4. ADC Window Compare Example: Right-Justified Data ......................... 55
Figure 8.5. ADC Window Compare Example: Left-Justified Data ........................... 55
Figure 8.6. ADC0 Multiplexer Block Diagram .......................................................... 56
9. Temperature Sensor
Figure 9.1. Temperature Sensor Transfer Function ................................................ 58
Figure 9.2. Temperature Sensor Error with 1-Point Calibration at 0 °C .................. 59
10. Voltage and Ground Reference Options
Figure 10.1. Voltage Reference Functional Block Diagram ..................................... 60
11. Voltage Regulator (REG0)
12. Comparator0
Figure 12.1. Comparator0 Functional Block Diagram ............................................. 65
Figure 12.2. Comparator Hysteresis Plot ................................................................ 66
Figure 12.3. Comparator Input Multiplexer Block Diagram ...................................... 69
13. Capacitive Sense (CS0)
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Figure 13.1. CS0 Block Diagram ............................................................................. 71
Figure 13.2. Auto-Scan Example ............................................................................. 73
Figure 13.3. CS0 Multiplexer Block Diagram ........................................................... 80
14. CIP-51 Microcontroller
Figure 14.1. CIP-51 Block Diagram ......................................................................... 82
15. Memory Organization
Figure 15.1. C8051F80x-83x Memory Map ............................................................. 92
Figure 15.2. Flash Program Memory Map ............................................................... 93
16. In-System Device Identification
17. Special Function Registers
18. Interrupts
19. Flash Memory
20. Power Management Modes
21. Reset Sources
Figure 21.1. Reset Sources ................................................................................... 123
Figure 21.2. Power-On and VDD Monitor Reset Timing ....................................... 124
22. Oscillators and Clock Selection
Figure 22.1. Oscillator Options .............................................................................. 129
Figure 22.2. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram 136
23. Port Input/Output
Figure 23.1. Port I/O Functional Block Diagram .................................................... 138
Figure 23.2. Port I/O Cell Block Diagram .............................................................. 139
Figure 23.3. Port I/O Overdrive Current ................................................................ 140
Figure 23.4. Priority Crossbar Decoder Potential Pin Assignments ...................... 144
Figure 23.5. Priority Crossbar Decoder Example 1—No Skipped Pins ................. 145
Figure 23.6. Priority Crossbar Decoder Example 2—Skipping Pins ...................... 146
24. Cyclic Redundancy Check Unit (CRC0)
Figure 24.1. CRC0 Block Diagram ........................................................................ 159
25. Enhanced Serial Peripheral Interface (SPI0)
Figure 25.1. SPI Block Diagram ............................................................................ 167
Figure 25.2. Multiple-Master Mode Connection Diagram ...................................... 169
Figure 25.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram
169
Figure 25.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram
170
Figure 25.5. Master Mode Data/Clock Timing ....................................................... 172
Figure 25.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 172
Figure 25.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 173
Figure 25.8. SPI Master Timing (CKPHA = 0) ....................................................... 177
Figure 25.9. SPI Master Timing (CKPHA = 1) ....................................................... 177
Figure 25.10. SPI Slave Timing (CKPHA = 0) ....................................................... 178
Figure 25.11. SPI Slave Timing (CKPHA = 1) ....................................................... 178
26. SMBus
Figure 26.1. SMBus Block Diagram ...................................................................... 180
Figure 26.2. Typical SMBus Configuration ............................................................ 181
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Figure 26.3. SMBus Transaction ........................................................................... 182
Figure 26.4. Typical SMBus SCL Generation ........................................................ 184
Figure 26.5. Typical Master Write Sequence ........................................................ 193
Figure 26.6. Typical Master Read Sequence ........................................................ 194
Figure 26.7. Typical Slave Write Sequence .......................................................... 195
Figure 26.8. Typical Slave Read Sequence .......................................................... 196
27. UART0
Figure 27.1. UART0 Block Diagram ...................................................................... 201
Figure 27.2. UART0 Baud Rate Logic ................................................................... 202
Figure 27.3. UART Interconnect Diagram ............................................................. 203
Figure 27.4. 8-Bit UART Timing Diagram .............................................................. 203
Figure 27.5. 9-Bit UART Timing Diagram .............................................................. 204
Figure 27.6. UART Multi-Processor Mode Interconnect Diagram ......................... 205
28. Timers
Figure 28.1. T0 Mode 0 Block Diagram ................................................................. 212
Figure 28.2. T0 Mode 2 Block Diagram ................................................................. 213
Figure 28.3. T0 Mode 3 Block Diagram ................................................................. 214
Figure 28.4. Timer 2 16-Bit Mode Block Diagram ................................................. 219
Figure 28.5. Timer 2 8-Bit Mode Block Diagram ................................................... 220
29. Programmable Counter Array
Figure 29.1. PCA Block Diagram ........................................................................... 225
Figure 29.2. PCA Counter/Timer Block Diagram ................................................... 226
Figure 29.3. PCA Interrupt Block Diagram ............................................................ 227
Figure 29.4. PCA Capture Mode Diagram ............................................................. 229
Figure 29.5. PCA Software Timer Mode Diagram ................................................. 230
Figure 29.6. PCA High-Speed Output Mode Diagram ........................................... 231
Figure 29.7. PCA Frequency Output Mode ........................................................... 232
Figure 29.8. PCA 8-Bit PWM Mode Diagram ........................................................ 233
Figure 29.9. PCA 9-bit through 15-Bit PWM Mode Diagram ................................. 234
Figure 29.10. PCA 16-Bit PWM Mode ................................................................... 235
Figure 29.11. PCA Module 2 with Watchdog Timer Enabled ................................ 236
30. C2 Interface
Figure 30.1. Typical C2 Pin Sharing ...................................................................... 247
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List of Registers
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SFR Definition 8.1. ADC0CF: ADC0 Configuration ...................................................... 50
SFR Definition 8.2. ADC0H: ADC0 Data Word MSB .................................................... 51
SFR Definition 8.3. ADC0L: ADC0 Data Word LSB ...................................................... 51
SFR Definition 8.4. ADC0CN: ADC0 Control ................................................................ 52
SFR Definition 8.5. ADC0GTH: ADC0 Greater-Than Data High Byte .......................... 53
SFR Definition 8.6. ADC0GTL: ADC0 Greater-Than Data Low Byte ............................ 53
SFR Definition 8.7. ADC0LTH: ADC0 Less-Than Data High Byte ................................ 54
SFR Definition 8.8. ADC0LTL: ADC0 Less-Than Data Low Byte ................................. 54
SFR Definition 8.9. ADC0MX: AMUX0 Channel Select ................................................ 57
SFR Definition 10.1. REF0CN: Voltage Reference Control .......................................... 62
SFR Definition 11.1. REG0CN: Voltage Regulator Control .......................................... 64
SFR Definition 12.1. CPT0CN: Comparator0 Control ................................................... 67
SFR Definition 12.2. CPT0MD: Comparator0 Mode Selection ..................................... 68
SFR Definition 12.3. CPT0MX: Comparator0 MUX Selection ...................................... 70
SFR Definition 13.1. CS0CN: Capacitive Sense Control .............................................. 75
SFR Definition 13.2. CS0CF: Capacitive Sense Configuration ..................................... 76
SFR Definition 13.3. CS0DH: Capacitive Sense Data High Byte ................................. 77
SFR Definition 13.4. CS0DL: Capacitive Sense Data Low Byte ................................... 77
SFR Definition 13.5. CS0SS: Capacitive Sense Auto-Scan Start Channel .................. 78
SFR Definition 13.6. CS0SE: Capacitive Sense Auto-Scan End Channel ................... 78
SFR Definition 13.7. CS0THH: Capacitive Sense Comparator Threshold High Byte ... 79
SFR Definition 13.8. CS0THL: Capacitive Sense Comparator Threshold Low Byte .... 79
SFR Definition 13.9. CS0MX: Capacitive Sense Mux Channel Select ......................... 81
SFR Definition 14.1. DPL: Data Pointer Low Byte ........................................................ 88
SFR Definition 14.2. DPH: Data Pointer High Byte ....................................................... 88
SFR Definition 14.3. SP: Stack Pointer ......................................................................... 89
SFR Definition 14.4. ACC: Accumulator ....................................................................... 89
SFR Definition 14.5. B: B Register ................................................................................ 90
SFR Definition 14.6. PSW: Program Status Word ........................................................ 91
SFR Definition 16.1. HWID: Hardware Identification Byte ............................................ 95
SFR Definition 16.2. DERIVID: Derivative Identification Byte ....................................... 96
SFR Definition 16.3. REVID: Hardware Revision Identification Byte ............................ 96
SFR Definition 18.1. IE: Interrupt Enable .................................................................... 105
SFR Definition 18.2. IP: Interrupt Priority .................................................................... 106
SFR Definition 18.3. EIE1: Extended Interrupt Enable 1 ............................................ 107
SFR Definition 18.4. EIE2: Extended Interrupt Enable 2 ............................................ 108
SFR Definition 18.5. EIP1: Extended Interrupt Priority 1 ............................................ 109
SFR Definition 18.6. EIP2: Extended Interrupt Priority 2 ............................................ 110
SFR Definition 18.7. IT01CF: INT0/INT1 Configuration .............................................. 112
SFR Definition 19.1. PSCTL: Program Store R/W Control ......................................... 118
SFR Definition 19.2. FLKEY: Flash Lock and Key ...................................................... 119
SFR Definition 20.1. PCON: Power Control ................................................................ 122
SFR Definition 21.1. VDM0CN: VDD Monitor Control ................................................ 126
Rev. 1.1
12
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SFR Definition 21.2. RSTSRC: Reset Source ............................................................ 128
SFR Definition 22.1. CLKSEL: Clock Select ............................................................... 130
SFR Definition 22.2. OSCICL: Internal H-F Oscillator Calibration .............................. 131
SFR Definition 22.3. OSCICN: Internal H-F Oscillator Control ................................... 132
SFR Definition 22.4. OSCXCN: External Oscillator Control ........................................ 134
SFR Definition 23.1. XBR0: Port I/O Crossbar Register 0 .......................................... 148
SFR Definition 23.2. XBR1: Port I/O Crossbar Register 1 .......................................... 149
SFR Definition 23.3. P0MASK: Port 0 Mask Register ................................................. 151
SFR Definition 23.4. P0MAT: Port 0 Match Register .................................................. 151
SFR Definition 23.5. P1MASK: Port 1 Mask Register ................................................. 152
SFR Definition 23.6. P1MAT: Port 1 Match Register .................................................. 152
SFR Definition 23.7. P0: Port 0 ................................................................................... 153
SFR Definition 23.8. P0MDIN: Port 0 Input Mode ....................................................... 154
SFR Definition 23.9. P0MDOUT: Port 0 Output Mode ................................................ 154
SFR Definition 23.10. P0SKIP: Port 0 Skip ................................................................. 155
SFR Definition 23.11. P1: Port 1 ................................................................................. 155
SFR Definition 23.12. P1MDIN: Port 1 Input Mode ..................................................... 156
SFR Definition 23.13. P1MDOUT: Port 1 Output Mode .............................................. 156
SFR Definition 23.14. P1SKIP: Port 1 Skip ................................................................. 157
SFR Definition 23.15. P2: Port 2 ................................................................................. 157
SFR Definition 23.16. P2MDOUT: Port 2 Output Mode .............................................. 158
SFR Definition 24.1. CRC0CN: CRC0 Control ........................................................... 163
SFR Definition 24.2. CRC0IN: CRC Data Input .......................................................... 164
SFR Definition 24.3. CRC0DATA: CRC Data Output ................................................. 164
SFR Definition 24.4. CRC0AUTO: CRC Automatic Control ........................................ 165
SFR Definition 24.5. CRC0CNT: CRC Automatic Flash Sector Count ....................... 165
SFR Definition 24.6. CRC0FLIP: CRC Bit Flip ............................................................ 166
SFR Definition 25.1. SPI0CFG: SPI0 Configuration ................................................... 174
SFR Definition 25.2. SPI0CN: SPI0 Control ............................................................... 175
SFR Definition 25.3. SPI0CKR: SPI0 Clock Rate ....................................................... 176
SFR Definition 25.4. SPI0DAT: SPI0 Data ................................................................. 176
SFR Definition 26.1. SMB0CF: SMBus Clock/Configuration ...................................... 186
SFR Definition 26.2. SMB0CN: SMBus Control .......................................................... 188
SFR Definition 26.3. SMB0ADR: SMBus Slave Address ............................................ 191
SFR Definition 26.4. SMB0ADM: SMBus Slave Address Mask .................................. 191
SFR Definition 26.5. SMB0DAT: SMBus Data ............................................................ 192
SFR Definition 27.1. SCON0: Serial Port 0 Control .................................................... 206
SFR Definition 27.2. SBUF0: Serial (UART0) Port Data Buffer .................................. 207
SFR Definition 28.1. CKCON: Clock Control .............................................................. 210
SFR Definition 28.2. TCON: Timer Control ................................................................. 215
SFR Definition 28.3. TMOD: Timer Mode ................................................................... 216
SFR Definition 28.4. TL0: Timer 0 Low Byte ............................................................... 217
SFR Definition 28.5. TL1: Timer 1 Low Byte ............................................................... 217
SFR Definition 28.6. TH0: Timer 0 High Byte ............................................................. 218
SFR Definition 28.7. TH1: Timer 1 High Byte ............................................................. 218
13
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SFR Definition 28.8. TMR2CN: Timer 2 Control ......................................................... 222
SFR Definition 28.9. TMR2RLL: Timer 2 Reload Register Low Byte .......................... 223
SFR Definition 28.10. TMR2RLH: Timer 2 Reload Register High Byte ...................... 223
SFR Definition 28.11. TMR2L: Timer 2 Low Byte ....................................................... 224
SFR Definition 28.12. TMR2H Timer 2 High Byte ....................................................... 224
SFR Definition 29.1. PCA0CN: PCA0 Control ............................................................ 238
SFR Definition 29.2. PCA0MD: PCA0 Mode .............................................................. 239
SFR Definition 29.3. PCA0PWM: PCA0 PWM Configuration ..................................... 240
SFR Definition 29.4. PCA0CPMn: PCA0 Capture/Compare Mode ............................ 241
SFR Definition 29.5. PCA0L: PCA0 Counter/Timer Low Byte .................................... 242
SFR Definition 29.6. PCA0H: PCA0 Counter/Timer High Byte ................................... 242
SFR Definition 29.7. PCA0CPLn: PCA0 Capture Module Low Byte ........................... 243
SFR Definition 29.8. PCA0CPHn: PCA0 Capture Module High Byte ......................... 243
C2 Register Definition 30.1. C2ADD: C2 Address ...................................................... 244
C2 Register Definition 30.3. REVID: C2 Revision ID .................................................. 245
C2 Register Definition 30.2. DEVICEID: C2 Device ID ............................................... 245
C2 Register Definition 30.4. FPCTL: C2 Flash Programming Control ........................ 246
C2 Register Definition 30.5. FPDAT: C2 Flash Programming Data ............................ 246
Rev. 1.1
14
C8051F80x-83x
1. System Overview
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C8051F80x-83x devices are fully integrated, mixed-signal, system-on-a-chip capacitive sensing MCUs.
Highlighted features are listed below. Refer to Table 2.1 for specific product feature selection and part
ordering numbers.
High-speed
pipelined 8051-compatible microcontroller core (up to 25 MIPS)
full-speed, non-intrusive debug interface (on-chip)
Capacitive sense interface with 16 input channels
10-bit 500 ksps single-ended ADC with 16-channel analog multiplexer and integrated temperature sensor
Precision calibrated 24.5 MHz internal oscillator
16 kb of on-chip Flash memory
512 bytes of on-chip RAM
D
In-system,
2
SMBus/I
C, Enhanced UART, and Enhanced SPI serial interfaces implemented in hardware
general-purpose 16-bit timers
Programmable counter/timer array (PCA) with three capture/compare modules
On-chip internal voltage reference
On-chip Watchdog timer
On-chip power-on reset and supply monitor
On-chip voltage comparator
17 general purpose I/O
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With on-chip power-on reset, VDD monitor, watchdog timer, and clock oscillator, the C8051F80x-83x
devices are truly stand-alone, system-on-a-chip solutions. The Flash memory can be reprogrammed even
in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. User
software has complete control of all peripherals, and may individually shut down any or all peripherals for
power savings.
The C8051F80x-83x processors include Silicon Laboratories’ 2-Wire C2 Debug and Programming interface, which allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production MCU installed in the final application. This debug logic supports inspection of memory, viewing and
modification of special function registers, setting breakpoints, single stepping, and run and halt commands.
All analog and digital peripherals are fully functional while debugging using C2. The two C2 interface pins
can be shared with user functions, allowing in-system debugging without occupying package pins.
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Each device is specified for 1.8–3.6 V operation over the industrial temperature range (–45 to +85 °C). An
internal LDO regulator is used to supply the processor core voltage at 1.8 V. The Port I/O and RST pins are
tolerant of input signals up to 5 V. See Table 2.1 for ordering information. Block diagrams of the devices in
the C8051F80x-83x family are shown in Figure 1.1 through Figure 1.9.
Rev. 1.1
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Figure 1.1. C8051F800, C8051F806, C8051F812, C8051F818 Block Diagram
16
Rev. 1.1
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Figure 1.2. C8051F801, C8051F807, C8051F813, C8051F819 Block Diagram
Rev. 1.1
17
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Figure 1.3. C8051F802, C8051F808, C8051F814, C8051F820 Block Diagram
18
Rev. 1.1
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Figure 1.4. C8051F803, C8051F809, C8051F815, C8051F821 Block Diagram
Rev. 1.1
19
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Figure 1.5. C8051F804, C8051F810, C8051F816, C8051F822 Block Diagram
20
Rev. 1.1
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Figure 1.6. C8051F805, C8051F811, C8051F817, C8051F823 Block Diagram
Rev. 1.1
21
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Figure 1.7. C8051F824, C8051F827, C8051F830, C8051F833 Block Diagram
22
Rev. 1.1
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Figure 1.8. C8051F825, C8051F828, C8051F831, C8051F834 Block Diagram
Rev. 1.1
23
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Figure 1.9. C8051F826, C8051F829, C8051F832, C8051F835 Block Diagram
24
Rev. 1.1
C8051F80x-83x
2. Ordering Information
All C8051F80x-83x devices have the following features:
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25 MIPS (Peak)
Calibrated Internal Oscillator
SMBus/I2C
Enhanced SPI
UART
Programmable counter array (3 channels)
3 Timers (16-bit)
1 Comparator
Pb-Free (RoHS compliant) package
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In addition to the features listed above, each device in the C8051F80x-83x family has a set of features that
vary across the product line. See Table 2.1 for a complete list of the unique feature sets for each device in
the family.
Rev. 1.1
25
C8051F80x-83x
C8051F805-GS
C8051F806-GM
C8051F807-GM
C8051F808-GM
C8051F809-GS
C8051F810-GS
C8051F811-GS
C8051F812-GM
C8051F813-GM
C8051F814-GM
C8051F815-GS
C8051F816-GS
C8051F817-GS
C8051F818-GM
C8051F819-GM
C8051F820-GM
C8051F821-GS
C8051F822-GS
C8051F823-GS
C8051F824-GS
C8051F825-GS
C8051F826-GS
C8051F827-GS
C8051F828-GS
C8051F829-GS
C8051F830-GS
C8051F831-GS
C8051F832-GS
13
17
17
17
13
13
13
17
17
17
13
13
13
17
17
17
13
13
13
13
13
13
13
13
13
13
13
13
—
16
8
—
12
8
—
16
8
—
12
8
—
16
8
—
12
8
—
12
8
—
12
8
—
12
8
—
16
16
16
16
16
16
16
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
4
4
4
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
256
256
256
256
256
256
256
256
256
16
16
16
12
Rev. 1.1
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—
—
—
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—
—
—
—
—
—
—
—
—
Package (RoHS)
512
512
512
512
512
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RAM
(Bytes)
16
16
16
16
16
QFN-20
QFN-20
QFN-20
SOIC-16
D
Flash
Memory
(kB)
16
8
—
12
8
Temperature
Sensor
Capacitive Sense
Channels
17
17
17
13
13
ADC
Channels
Digital
Port I/Os
C8051F800-GM
C8051F801-GM
C8051F802-GM
C8051F803-GS
C8051F804-GS
10-bit
500 ksps
ADC
Part
Number
Table 2.1. Product Selection Guide
12
12
—
—
—
—
—
—
16
16
16
12
12
12
—
—
—
—
—
—
12
12
12
—
—
—
12
12
12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SOIC-16
SOIC-16
QFN-20
QFN-20
QFN-20
SOIC-16
SOIC-16
SOIC-16
QFN-20
QFN-20
QFN-20
SOIC-16
SOIC-16
SOIC-16
QFN-20
QFN-20
QFN-20
SOIC-16
SOIC-16
SOIC-16
SOIC-16
SOIC-16
SOIC-16
SOIC-16
SOIC-16
SOIC-16
SOIC-16
SOIC-16
SOIC-16
C8051F80x-83x
Temperature
Sensor
Package (RoHS)
—
—
—
—
—
—
SOIC-16
SOIC-16
SOIC-16
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ADC
Channels
—
—
—
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13
12
4
256
C8051F834-GS
13
8
4
256
C8051F835-GS
13
—
4
256
Lead finish material on all devices is 100% matte tin (Sn).
10-bit
500 ksps
ADC
RAM
(Bytes)
Flash
Memory
(kB)
Capacitive Sense
Channels
Part
Number
Digital
Port I/Os
Table 2.1. Product Selection Guide (Continued)
—
—
—
—
—
—
—
—
—
—
—
—
Package (RoHS)
16
16
16
—
—
—
16
16
16
—
—
—
Temperature
Sensor
ADC
Channels
QSOP-24
QSOP-24
QSOP-24
QSOP-24
QSOP-24
QSOP-24
QSOP-24
QSOP-24
QSOP-24
QSOP-24
QSOP-24
QSOP-24
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C8051F800-GU
17
16
16
512
C8051F801-GU
17
8
16
512
C8051F802-GU
17
—
16
512
C8051F806-GU
17
16
16
512
C8051F807-GU
17
8
16
512
C8051F808-GU
17
—
16
512
C8051F812-GU
17
16
8
512
C8051F813-GU
17
8
8
512
C8051F814-GU
17
—
8
512
C8051F818-GU
17
16
8
512
C8051F819-GU
17
8
8
512
C8051F820-GU
17
—
8
512
Lead finish material on all devices is 100% matte tin (Sn).
10-bit
500 ksps
ADC
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Flash
Memory
(kB)
Capacitive Sense
Channels
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Digital
Port I/Os
Part
Number
Table 2.2. Product Selection Guide (End of Life)
Rev. 1.1
27
C8051F80x-83x
3. Pin Definitions
Pin
QSOP-24
Pin
QFN-20
Pin
SOIC-16
GND
5
2
4
Ground.
This ground connection is required. The center
pad may optionally be connected to ground as
well on the QFN-20 packages.
VDD
6
3
5
Power Supply Voltage.
RST/
7
4
6
5
7
4
VREF
D I/O
Bi-directional data signal for the C2 Debug Interface. Shared with P2.0 on 20-pin packaging and
P2.4 on 24-pin packaging.
1
3
P0.2/
2
2
D I/O or Port 0.1.
A In
19
1
D I/O or Port 0.2.
A In
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18
A In
16
R
P0.3/
External VREF input.
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3
Bi-directional data signal for the C2 Debug Interface. Shared with P2.0 on 20-pin packaging and
P2.4 on 24-pin packaging.
D I/O or Port 0.0.
A In
A In
P0.1
XTAL2
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Clock signal for the C2 Debug Interface.
D I/O
P0.0/
P0.4
D I/O
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C2D
XTAL1
Device Reset. Open-drain output of internal
POR or VDD monitor. An external source can initiate a system reset by driving this pin low for at
least 10 μs.
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P2.0/
Description
D
Name
C2CK
Type
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Table 3.1. Pin Definitions for the C8051F80x-83x
External Clock Input. This pin is the external
oscillator return for a crystal or resonator.
D I/O or Port 0.3.
A In
A I/O or External Clock Output. For an external crystal or
resonator, this pin is the excitation driver. This
D In
pin is the external clock input for CMOS, capacitor, or RC oscillator configurations.
22
17
15
D I/O or Port 0.4.
A In
Rev. 1.1
28
C8051F80x-83x
Table 3.1. Pin Definitions for the C8051F80x-83x (Continued)
Pin
QSOP-24
Pin
QFN-20
Pin
SOIC-16
P0.5
21
16
14
D I/O or Port 0.5.
A In
P0.6/
20
15
13
D I/O or Port 0.6.
A In
D In
ADC0 External Convert Start or IDA0 Update
Source Input.
19
14
12
D I/O or Port 0.7.
A In
P1.0
18
13
11
D I/O or Port 1.0.
A In
P1.1
17
12
10
D I/O or Port 1.1.
A In
P1.2
16
11
9
D I/O or Port 1.2.
A In
P1.3
15
10
8
D I/O or Port 1.3.
A In
P1.4
14
P1.5
11
P1.6
10
P1.7
9
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P0.7
D I/O or Port 1.4.
A In
8
D I/O or Port 1.5.
A In
7
D I/O or Port 1.6.
A In
6
D I/O or Port 1.7.
A In
om
9
1, 12, 13,
24
No Connection.
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Description
D
CNVSTR
Type
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Name
Rev. 1.1
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Figure 3.1. QFN-20 Pinout Diagram (Top View)
Rev. 1.1
30
Figure 3.2. QSOP-24 Pinout Diagram (Top View)
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C8051F80x-83x
31
Rev. 1.1
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Figure 3.3. SOIC-16 Pinout Diagram (Top View)
Rev. 1.1
32
C8051F80x-83x
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4. QFN-20 Package Specifications
Figure 4.1. QFN-20 Package Drawing
Table 4.1. QFN-20 Package Dimensions
Dimension
Typ
Max
Dimension
Min
Typ
Max
0.80
0.00
0.18
0.90
0.02
0.25
4.00 BSC.
2.15
0.50 BSC.
4.00 BSC.
2.15
1.00
0.05
0.30
L
L1
aaa
bbb
ddd
eee
Z
Y
0.45
0.00
—
—
—
—
—
—
0.55
—
—
—
—
—
0.43
0.18
0.65
0.15
0.15
0.10
0.05
0.08
—
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A
A1
b
D
D2
e
E
E2
Min
2.00
2.00
2.25
2.25
N
ot
R
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, variation VGGD except for
custom features D2, E2, Z, Y, and L which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
Rev. 1.1
33
N
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C8051F80x-83x
fo
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Figure 4.2. QFN-20 Recommended PCB Land Pattern
Table 4.2. QFN-20 PCB Land Pattern Dimensions
C1
C2
E
X1
Min
Max
Dimension
m
en
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Dimension
3.70
3.70
0.50
0.20
X2
Y1
Y2
Min
Max
2.15
0.90
2.15
2.25
1.00
2.25
0.30
om
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
ec
Solder Mask Design
4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 μm minimum, all the way around the pad.
N
ot
R
Stencil Design
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
to assure good solder paste release.
6. The stencil thickness should be 0.125 mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
8. A 2x2 array of 0.95 mm openings on a 1.1 mm pitch should be used for the center pad to
assure the proper paste volume.
34
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.
Rev. 1.1
C8051F80x-83x
m
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5. QSOP-24 Package Specifications
Figure 5.1. QSOP-24 Package Drawing
Table 5.1. QSOP-24 Package Dimensions
Dimension
Nom
Max
Dimension
Min
Nom
Max
—
0.10
0.20
0.10
—
—
—
1.75
0.25
0.30
0.40
0.25
—
0.25 BSC
—
0.20
1.27
—
8.65 BSC
6.00 BSC
3.90 BSC
0.635 BSC
L
L2
aaa
om
A
A1
b
c
Min
ec
D
E
E1
e
bbb
ccc
ddd
0º
8º
0.18
0.10
0.10
N
ot
R
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-137, variation AE.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
Rev. 1.1
35
fo
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C8051F80x-83x
m
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Figure 5.2. QSOP-24 PCB Land Pattern
Table 5.2. QSOP-24 PCB Land Pattern Dimensions
Dimension
Min
Max
C
E
X
Y
5.20
5.30
0.635 BSC
0.30
1.50
0.40
1.60
om
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This land pattern design is based on the IPC-7351 guidelines.
ec
Solder Mask Design
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal
pad is to be 60 μm minimum, all the way around the pad.
N
ot
R
Stencil Design
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good
solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
Card Assembly
7. A No-Clean, Type-3 solder paste is recommended.
8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
36
Rev. 1.1
C8051F80x-83x
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6. SOIC-16 Package Specifications
Figure 6.1. SOIC-16 Package Drawing
Table 6.1. SOIC-16 Package Dimensions
Dimension
R
ec
D
E
E1
e
Nom
—
0.10
1.25
0.31
0.17
om
A
A1
A2
b
c
Min
Max
Dimension
Min
1.75
0.25
—
0.51
L
L2
h
aaa
0.40
0.25
9.90 BSC
6.00 BSC
3.90 BSC
1.27 BSC
bbb
ccc
ddd
Nom
Max
1.27
0.25 BSC
0.25
0º
0.50
8º
0.10
0.20
0.10
0.25
N
ot
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
Rev. 1.1
37
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C8051F80x-83x
m
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Figure 6.2. SOIC-16 PCB Land Pattern
Table 6.2. SOIC-16 PCB Land Pattern Dimensions
Dimension
Feature
(mm)
C1
E
X1
Y1
Pad Column Spacing
Pad Row Pitch
Pad Width
Pad Length
5.40
1.27
0.60
1.55
N
ot
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ec
om
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N for Density Level B (Median
Land Protrusion).
3. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of
0.05 mm is assumed.
38
Rev. 1.1
C8051F80x-83x
7. Electrical Characteristics
Table 7.1. Absolute Maximum Ratings
Min
Typ
Max
Units
Ambient temperature under bias
–55
—
125
°C
Storage Temperature
–65
—
150
°C
Voltage on RST or any Port I/O Pin
with respect to GND
–0.3
—
5.8
V
Voltage on VDD with respect to GND
–0.3
—
4.2
V
—
—
500
mA
—
—
100
mA
D
Conditions
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Parameter
es
ig
ns
7.1. Absolute Maximum Specifications
Maximum Total current through VDD
and GND
Maximum output current sunk by RST
or any Port pin
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Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the devices at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
Rev. 1.1
39
C8051F80x-83x
7.2. Electrical Characteristics
–40 to +85 °C, 25 MHz system clock unless otherwise specified.
Parameter
Conditions
Min
Supply Voltage
1.8
es
ig
ns
Table 7.2. Global Electrical Characteristics
Typ
Max
Units
3.0
3.6
V
4.6
1.2
135
5.5
1.3
150
6.0
—
—
6.5
—
—
mA
mA
μA
mA
mA
μA
VDD = 1.8 V, Clock = 25 MHz
VDD = 1.8 V, Clock = 1 MHz
VDD = 1.8 V, Clock = 32 kHz
VDD = 3.0 V, Clock = 25 MHz
VDD = 3.0 V, Clock = 1 MHz
VDD = 3.0 V, Clock = 32 kHz
—
—
—
—
—
—
Digital Supply Current with
CPU Inactive (Idle Mode1)
VDD = 1.8 V, Clock = 25 MHz
VDD = 1.8 V, Clock = 1 MHz
VDD = 1.8 V, Clock = 32 kHz
VDD = 3.0 V, Clock = 25 MHz
VDD = 3.0 V, Clock = 1 MHz
VDD = 3.0 V, Clock = 32 kHz
—
—
—
—
—
—
2
190
100
2.3
335
115
2.6
—
—
2.8
—
—
mA
μA
μA
mA
μA
μA
Digital Supply Current
(shutdown)
Oscillator not running (stop mode),
Internal Regulator Off, 25 °C
—
0.5
2
μA
—
105
140
μA
—
1.3
—
V
–40
—
+85
°C
0
—
25
MHz
Tsysl (SYSCLK low time)
18
—
—
ns
Tsysh (SYSCLK high time)
18
—
—
ns
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Oscillator not running (stop or suspend
mode), Internal Regulator On, 25 °C
Digital Supply RAM Data
Retention Voltage
Specified Operating Temperature Range
See Note 2
ec
om
SYSCLK (system clock
frequency)
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Notes:
1. Includes bias current for internal voltage regulator.
2. SYSCLK must be at least 32 kHz to enable debugging.
40
D
Digital Supply Current with
CPU Active (Normal Mode1)
Rev. 1.1
C8051F80x-83x
Table 7.3. Port I/O DC Electrical Characteristics
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Max
Units
—
—
—
0.6
0.1
—
—
0.6
1
50
V
V
V
V
V
V
V
V
μA
μA
Typ
Max
Units
—
—
0.6
V
0.75 x VDD
—
—
V
—
—
0.3 x VDD
VDD
—
25
50
μA
VDD POR Ramp Time
—
—
1
ms
VDD Monitor Threshold (VRST)
1.7
1.75
1.8
V
100
500
1000
μs
—
—
30
μs
15
—
—
μs
—
50
—
μs
—
20
30
μA
Table 7.4. Reset Electrical Characteristics
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Conditions
RST Output Low Voltage
IOL = 8.5 mA,
VDD = 1.8 V to 3.6 V
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RST Input High Voltage
RST Input Low Voltage
RST Input Pullup Current
RST = 0.0 V
Time from last system clock
rising edge to reset initiation
Reset Time Delay
Delay between release of any
reset source and code
execution at location 0x0000
om
Missing Clock Detector
Timeout
ec
Minimum RST Low Time to
Generate a System Reset
VDD Monitor Turn-on Time
D
—
—
VDD - 0.8
—
—
1.0
—
—
—
15
Min
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Parameter
Typ
VDD = VRST – 0.1 V
R
VDD Monitor Supply Current
es
ig
ns
Min
VDD – 0.7
VDD - 0.1
—
—
—
—
0.75 x VDD
—
–1
—
N
ew
Parameters
Conditions
Output High Voltage IOH = –3 mA, Port I/O push-pull
IOH = –10 μA, Port I/O push-pull
IOH = –10 mA, Port I/O push-pull
Output Low Voltage IOL = 8.5 mA
IOL = 10 μA
IOL = 25 mA
Input High Voltage
Input Low Voltage
Input Leakage
Weak Pullup Off
Current
Weak Pullup On, VIN = 0 V
N
ot
Table 7.5. Internal Voltage Regulator Electrical Characteristics
VDD = 3.0 V, –40 to +85 °C unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
Input Voltage Range
1.8
—
3.6
V
Bias Current
—
50
65
μA
Rev. 1.1
41
C8051F80x-83x
Table 7.6. Flash Electrical Characteristics
Conditions
C8051F80x and C8051F810/1
C8051F812/3/4/5/6/7/8/9 and C8051F82x
C8051F830/1/2/3/4/5
Endurance (Erase/Write)
Erase Cycle Time
Write Cycle Time
Clock Speed during Flash
Write/Erase Operations
Typ
Max Units
16384
8192
4096
10000
—
15
20
15
20
1
—
25 MHz Clock
25 MHz Clock
bytes
bytes
bytes
cycles
ms
μs
MHz
—
26
26
—
D
Flash Size (Note 1)
Min
es
ig
ns
Parameter
N
ew
Note: Includes Security Lock Byte.
Table 7.7. Internal High-Frequency Oscillator Electrical Characteristics
VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified. Use factory-calibrated settings.
IFCN = 11b
25 °C, VDD = 3.0 V,
OSCICN.7 = 1,
OCSICN.5 = 0
Min
24
—
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Conditions
m
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Parameter
Oscillator Frequency
Oscillator Supply Current
Typ
24.5
350
Max
25
650
Units
MHz
μA
Table 7.8. Capacitive Sense Electrical Characteristics
VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified.
Parameter
Conditions
ec
om
Conversion Time
Single Conversion
Capacitance per Code
External Capacitive Load
Quantization Noise1
RMS
Peak-to-Peak
Supply Current
CS module bias current, 25 °C
CS module alone, maximum code
output, 25 °C
Wake-on-CS Threshold2, 25 °C
Min
Typ
Max
Units
26
—
—
—
—
—
—
38
1
—
3
20
40
75
50
—
45
—
—
60
105
μs
fF
pF
fF
fF
μA
μA
—
150
165
μA
N
ot
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Notes:
1. RMS Noise is equivalent to one standard deviation. Peak-to-peak noise encompasses ±3.3 standard
deviations.
2. Includes only current from regulator, CS module, and MCU in suspend mode.
42
Rev. 1.1
C8051F80x-83x
Table 7.9. ADC0 Electrical Characteristics
VDD = 3.0 V, VREF = 2.40 V (REFSL=0), –40 to +85 °C unless otherwise specified.
Conditions
Min
Typ
—
—
–2
–2
—
10
±0.5
±0.5
0
0
45
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Full Scale Error
Offset Temperature Coefficient
Guaranteed Monotonic
Units
±1
±1
2
2
—
bits
LSB
LSB
LSB
LSB
ppm/°C
D
DC Accuracy
Max
es
ig
ns
Parameter
Signal-to-Noise Plus Distortion
Total Harmonic Distortion
Spurious-Free Dynamic Range
Up to the 5th harmonic
SAR Conversion Clock
Conversion Time in SAR Clocks
Throughput Rate
Analog Inputs
m
en
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Track/Hold Acquisition Time
10-bit Mode
8-bit Mode
VDD >= 2.0 V
VDD < 2.0 V
ADC Input Voltage Range
Sampling Capacitance
54
—
—
60
75
–90
—
—
—
dB
dB
dB
—
13
11
300
2.0
—
—
—
—
—
—
—
8.33
—
—
—
—
500
MHz
clocks
clocks
ns
μs
ksps
0
—
—
—
—
5
3
5
VREF
—
—
—
V
pF
pF
k
—
—
630
–70
1000
—
μA
dB
fo
r
Conversion Rate
N
ew
Dynamic performance (10 kHz sine-wave single-ended input, 1 dB below Full Scale, 200 ksps)
1x Gain
0.5x Gain
Input Multiplexer Impedance
Power Specifications
Operating Mode, 500 ksps
N
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om
Power Supply Current
Power Supply Rejection
Rev. 1.1
43
C8051F80x-83x
Table 7.10. Power Management Electrical Characteristics
VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified. Use factory-calibrated settings.
Conditions
Min
2
—
Typ
—
500
Max
3
—
Table 7.11. Temperature Sensor Electrical Characteristics
VDD = 3.0 V, –40 to +85 °C unless otherwise specified.
Linearity
Slope
Slope Error*
Offset
Offset Error*
Temp = 0 °C
Temp = 0 °C
*Note: Represents one standard deviation from the mean.
Min
Typ
Max
—
—
—
—
—
1
2.43
±45
873
14.5
D
Conditions
N
ew
Parameter
Units
SYSCLKs
ns
es
ig
ns
Parameter
Idle Mode Wake-Up Time
Suspend Mode Wake-up Time
—
—
—
—
—
Units
°C
mV/°C
μV/°C
mV
mV
fo
r
Table 7.12. Voltage Reference Electrical Characteristics
VDD = 1.8 to 3.6 V; –40 to +85 °C unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
1.55
1.65
1.75
V
—
—
1.7
μs
—
180
—
μA
0
—
VDD
—
7
—
Output Voltage
Turn-on Time
Supply Current
m
en
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d
Internal High Speed Reference (REFSL[1:0] = 11)
25 °C ambient
External Reference (REF0E = 0)
Input Voltage Range
Sample Rate = 500 ksps; VREF = 3.0 V
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Input Current
44
Rev. 1.1
μA
C8051F80x-83x
Table 7.13. Comparator Electrical Characteristics
VDD = 3.0 V, –40 to +85 °C unless otherwise noted.
Response Time:
Mode 2, Vcm* = 1.5 V
Response Time:
Mode 3, Vcm* = 1.5 V
Input Offset Voltage
Mode 2, CP0HYP1–0 = 00b
Mode 2, CP0HYP1–0 = 01b
Mode 2, CP0HYP1–0 = 10b
Mode 2, CP0HYP1–0 = 11b
Mode 2, CP0HYN1–0 = 00b
Mode 2, CP0HYN1–0 = 01b
Mode 2, CP0HYN1–0 = 10b
Mode 2, CP0HYN1–0 = 11b
m
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Common-Mode Rejection Ratio
Positive Hysteresis 1
Positive Hysteresis 2
Positive Hysteresis 3
Positive Hysteresis 4
Negative Hysteresis 1
Negative Hysteresis 2
Negative Hysteresis 3
Negative Hysteresis 4
Inverting or Non-Inverting Input
Voltage Range
Max
Units
—
—
—
—
—
—
—
—
—
—
2
7
10
—
2
7
10
–0.25
220
225
340
380
510
945
1500
5000
1
0
5
10
20
0
5
10
20
—
—
—
—
—
—
—
—
—
4
1
10
20
30
1
10
20
30
ns
ns
ns
ns
ns
ns
ns
ns
mV/V
mV
mV
mV
mV
mV
mV
mV
mV
VDD + 0.25
V
–7.5
—
7.5
mV
—
—
—
—
—
—
0.1
10
20
8
3
0.5
—
—
—
—
—
—
mV/V
μs
μA
μA
μA
μA
N
ew
Response Time:
Mode 1, Vcm* = 1.5 V
CP0+ – CP0– = 100 mV
CP0+ – CP0– = –100 mV
CP0+ – CP0– = 100 mV
CP0+ – CP0– = –100 mV
CP0+ – CP0– = 100 mV
CP0+ – CP0– = –100 mV
CP0+ – CP0– = 100 mV
CP0+ – CP0– = –100 mV
Typ
fo
r
Response Time:
Mode 0, Vcm* = 1.5 V
Min
es
ig
ns
Conditions
D
Parameter
Power Specifications
om
Power Supply Rejection
Powerup Time
Supply Current at DC
Mode 0
Mode 1
Mode 2
Mode 3
N
ot
R
ec
Note: Vcm is the common-mode voltage on CP0+ and CP0–.
Rev. 1.1
45
C8051F80x-83x
8. 10-Bit ADC (ADC0)
Figure 8.1. ADC0 Functional Block Diagram
N
ot
R
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om
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D
es
ig
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ADC0 on the C8051F800/1/2/3/4/5, C8051F812/3/4/5/6/7, C8051F824/5/6, and C8051F830/1/2 is a
500 ksps, 10-bit successive-approximation-register (SAR) ADC with integrated track-and-hold, a gain
stage programmable to 1x or 0.5x, and a programmable window detector. The ADC is fully configurable
under software control via Special Function Registers. The ADC may be configured to measure various different signals using the analog multiplexer described in Section “8.5. ADC0 Analog Multiplexer” on
page 56. The voltage reference for the ADC is selected as described in Section “9. Temperature Sensor”
on page 58. The ADC0 subsystem is enabled only when the AD0EN bit in the ADC0 Control register
(ADC0CN) is set to logic 1. The ADC0 subsystem is in low power shutdown when this bit is logic 0.
Rev. 1.1
46
C8051F80x-83x
8.1. Output Code Formatting
VREF x 1023/1024
VREF x 512/1024
VREF x 256/1024
0
8.2. 8-Bit Mode
Left-Justified ADC0H:ADC0L
(AD0LJST = 1)
0xFFC0
0x8000
0x4000
0x0000
D
Right-Justified ADC0H:ADC0L
(AD0LJST = 0)
0x03FF
0x0200
0x0100
0x0000
N
ew
Input Voltage
es
ig
ns
The ADC measures the input voltage with reference to GND. The registers ADC0H and ADC0L contain the
high and low bytes of the output conversion code from the ADC at the completion of each conversion. Data
can be right-justified or left-justified, depending on the setting of the AD0LJST bit. Conversion codes are
represented as 10-bit unsigned integers. Inputs are measured from 0 to VREF x 1023/1024. Example
codes are shown below for both right-justified and left-justified data. Unused bits in the ADC0H and ADC0L
registers are set to 0.
8.3. Modes of Operation
fo
r
Setting the ADC08BE bit in register ADC0CF to 1 will put the ADC in 8-bit mode. In 8-bit mode, only the 8
MSBs of data are converted, and the ADC0H register holds the results. The AD0LJST bit is ignored for 8bit mode. 8-bit conversions take two fewer SAR clock cycles than 10-bit conversions, so the conversion is
completed faster, and a 500 ksps sampling rate can be achieved with a slower SAR clock.
m
en
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d
ADC0 has a maximum conversion speed of 500 ksps. The ADC0 conversion clock is a divided version of
the system clock, determined by the AD0SC bits in the ADC0CF register.
8.3.1. Starting a Conversion
A conversion can be initiated in one of six ways, depending on the programmed states of the ADC0 Start of
Conversion Mode bits (AD0CM2–0) in register ADC0CN. Conversions may be initiated by one of the following:
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ot
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om
1. Writing a 1 to the AD0BUSY bit of register ADC0CN
2. A Timer 0 overflow (i.e., timed continuous conversions)
3. A Timer 2 overflow
4. A Timer 1 overflow
5. A rising edge on the CNVSTR input signal
Writing a 1 to AD0BUSY provides software control of ADC0 whereby conversions are performed "ondemand". During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conversion is
complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt
flag (AD0INT). When polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT) should be
used. Converted data is available in the ADC0 data registers, ADC0H:ADC0L, when bit AD0INT is logic 1.
When Timer 2 overflows are used as the conversion source, Low Byte overflows are used if Timer 2/3 is in
8-bit mode; High byte overflows are used if Timer 2 is in 16-bit mode. See Section “28. Timers” on
page 209 for timer configuration.
Important Note About Using CNVSTR: The CNVSTR input pin also functions as a Port I/O pin. When the
CNVSTR input is used as the ADC0 conversion source, the associated pin should be skipped by the Digital Crossbar. See Section “23. Port Input/Output” on page 138 for details on Port I/O configuration.
47
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8.3.2. Tracking Modes
The AD0TM bit in register ADC0CN enables "delayed conversions", and will delay the actual conversion
start by three SAR clock cycles, during which time the ADC will continue to track the input. If AD0TM is left
at logic 0, a conversion will begin immediately, without the extra tracking time. For internal start-of-conversion sources, the ADC will track anytime it is not performing a conversion. When the CNVSTR signal is
used to initiate conversions, ADC0 will track either when AD0TM is logic 1, or when AD0TM is logic 0 and
CNVSTR is held low. See Figure 8.2 for track and convert timing details. Delayed conversion mode is useful when AMUX settings are frequently changed, due to the settling time requirements described in Section
“8.3.3. Settling Time Requirements” on page 49.
Figure 8.2. 10-Bit ADC Track and Conversion Example Timing
Rev. 1.1
48
C8051F80x-83x
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8.3.3. Settling Time Requirements
A minimum tracking time is required before each conversion to ensure that an accurate conversion is performed. This tracking time is determined by any series impedance, including the AMUX0 resistance, the
the ADC0 sampling capacitance, and the accuracy required for the conversion. In delayed tracking mode,
three SAR clocks are used for tracking at the start of every conversion. For many applications, these three
SAR clocks will meet the minimum tracking time requirements.
n
N
ew
2
t = ln ------- R TOTAL C SAMPLE
SA
D
Figure 8.3 shows the equivalent ADC0 input circuit. The required ADC0 settling time for a given settling
accuracy (SA) may be approximated by Equation 8.1. See Table 7.9 for ADC0 minimum settling time
requirements as well as the mux impedance and sampling capacitor values.
Equation 8.1. ADC0 Settling Time Requirements
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Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
RTOTAL is the sum of the AMUX0 resistance and any external source resistance.
n is the ADC resolution in bits (10).
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Figure 8.3. ADC0 Equivalent Input Circuits
49
Rev. 1.1
C8051F80x-83x
Bit
7
6
5
4
3
2
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SFR Definition 8.1. ADC0CF: ADC0 Configuration
1
0
Name
AD0SC[4:0]
AD0LJST
AD08BE
AMP0GN0
Type
R/W
R/W
R/W
R/W
0
1
1
1
SFR Address = 0xBC
Bit
Name
1
1
0
Function
D
1
Reset
N
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7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Period Bits.
SAR Conversion clock is derived from system clock by the following equation, where
AD0SC refers to the 5-bit value held in bits AD0SC4–0. SAR Conversion clock
requirements are given in the ADC specification table.
AD0LJST
ADC0 Left Justify Select.
0: Data in ADC0H:ADC0L registers are right-justified.
1: Data in ADC0H:ADC0L registers are left-justified.
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AD0SC = SYSCLK
----------------------- – 1
CLK SAR
Note: The AD0LJST bit is only valid for 10-bit mode (AD08BE = 0).
1
AD08BE
8-Bit Mode Enable.
0: ADC operates in 10-bit mode (normal).
1: ADC operates in 8-bit mode.
Note: When AD08BE is set to 1, the AD0LJST bit is ignored.
AMP0GN0 ADC Gain Control Bit.
0: Gain = 0.5
1: Gain = 1
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0
Rev. 1.1
50
C8051F80x-83x
7
6
5
4
3
Name
ADC0H[7:0]
Type
R/W
0
Reset
0
0
0
0
SFR Address = 0xBE
Bit
Name
2
0
1
0
0
0
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Bit
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SFR Definition 8.2. ADC0H: ADC0 Data Word MSB
Function
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7:0 ADC0H[7:0] ADC0 Data Word High-Order Bits.
For AD0LJST = 0: Bits 7–2 will read 000000b. Bits 1–0 are the upper 2 bits of the 10bit ADC0 Data Word.
For AD0LJST = 1: Bits 7–0 are the most-significant bits of the 10-bit ADC0 Data
Word.
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Note: In 8-bit mode AD0LJST is ignored, and ADC0H holds the 8-bit data word.
Bit
7
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SFR Definition 8.3. ADC0L: ADC0 Data Word LSB
6
5
4
3
2
1
0
0
0
0
ADC0L[7:0]
Name
R/W
Type
0
Reset
0
0
0
SFR Address = 0xBD
Bit
Name
0
Function
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7:0 ADC0L[7:0] ADC0 Data Word Low-Order Bits.
For AD0LJST = 0: Bits 7–0 are the lower 8 bits of the 10-bit Data Word.
For AD0LJST = 1: Bits 7–6 are the lower 2 bits of the 10-bit Data Word. Bits 5–0 will
always read 0.
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Note: In 8-bit mode AD0LJST is ignored, and ADC0L will read back 00000000b.
51
Rev. 1.1
C8051F80x-83x
7
6
5
Name
AD0EN
AD0TM
AD0INT
Type
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
SFR Address = 0xE8; Bit-Addressable
Bit
Name
4
3
2
AD0BUSY AD0WINT
1
0
AD0CM[2:0]
R/W
0
Function
0
0
D
Bit
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SFR Definition 8.4. ADC0CN: ADC0 Control
AD0EN
ADC0 Enable Bit.
0: ADC0 Disabled. ADC0 is in low-power shutdown.
1: ADC0 Enabled. ADC0 is active and ready for data conversions.
6
AD0TM
ADC0 Track Mode Bit.
0: Normal Track Mode: When ADC0 is enabled, tracking is continuous unless a conversion is in progress. Conversion begins immediately on start-of-conversion event,
as defined by AD0CM[2:0].
1: Delayed Track Mode: When ADC0 is enabled, input is tracked when a conversion
is not in progress. A start-of-conversion signal initiates three SAR clocks of additional
tracking, and then begins the conversion.
5
AD0INT
ADC0 Conversion Complete Interrupt Flag.
0: ADC0 has not completed a data conversion since AD0INT was last cleared.
1: ADC0 has completed a data conversion.
4
AD0BUSY
ADC0 Busy Bit.
3
AD0WINT
ADC0 Window Compare Interrupt Flag.
0: ADC0 Window Comparison Data match has not occurred since this flag was last
cleared.
1: ADC0 Window Comparison Data match has occurred.
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7
Write:
0: No Effect.
1: Initiates ADC0 Conversion if AD0CM[2:0] =
000b
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Read:
0: ADC0 conversion is not
in progress.
1: ADC0 conversion is in
progress.
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2:0 AD0CM[2:0] ADC0 Start of Conversion Mode Select.
000: ADC0 start-of-conversion source is write of 1 to AD0BUSY.
001: ADC0 start-of-conversion source is overflow of Timer 0.
010: ADC0 start-of-conversion source is overflow of Timer 2.
011: ADC0 start-of-conversion source is overflow of Timer 1.
100: ADC0 start-of-conversion source is rising edge of external CNVSTR.
101–111: Reserved.
Rev. 1.1
52
C8051F80x-83x
8.4. Programmable Window Detector
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The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-programmed limits, and notifies the system when a desired condition is detected. This is especially effective in
an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system
response times. The window detector interrupt flag (AD0WINT in register ADC0CN) can also be used in
polled mode. The ADC0 Greater-Than (ADC0GTH, ADC0GTL) and Less-Than (ADC0LTH, ADC0LTL)
registers hold the comparison values. The window detector flag can be programmed to indicate when measured data is inside or outside of the user-programmed limits, depending on the contents of the ADC0
Less-Than and ADC0 Greater-Than registers.
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SFR Definition 8.5. ADC0GTH: ADC0 Greater-Than Data High Byte
7
6
5
4
3
Name
ADC0GTH[7:0]
Type
R/W
1
Reset
1
1
1
0
1
1
1
1
2
1
0
1
1
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SFR Address = 0xC4
Bit
Name
1
2
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Bit
Function
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7:0 ADC0GTH[7:0] ADC0 Greater-Than Data Word High-Order Bits.
SFR Definition 8.6. ADC0GTL: ADC0 Greater-Than Data Low Byte
Bit
7
6
5
4
ADC0GTL[7:0]
Name
R/W
Type
1
1
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Reset
1
1
SFR Address = 0xC3
Bit
Name
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ADC0GTL[7:0] ADC0 Greater-Than Data Word Low-Order Bits.
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1
Function
R
7:0
3
Rev. 1.1
C8051F80x-83x
7
6
5
4
3
Name
ADC0LTH[7:0]
Type
R/W
0
Reset
0
0
0
0
SFR Address = 0xC6
Bit
Name
0
Function
ADC0LTH[7:0] ADC0 Less-Than Data Word High-Order Bits.
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2
1
0
0
0
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SFR Definition 8.7. ADC0LTH: ADC0 Less-Than Data High Byte
SFR Definition 8.8. ADC0LTL: ADC0 Less-Than Data Low Byte
7
6
5
4
3
Name
ADC0LTL[7:0]
Type
R/W
0
0
0
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0
Reset
SFR Address = 0xC5
Bit
Name
1
0
0
0
0
0
Function
ADC0LTL[7:0] ADC0 Less-Than Data Word Low-Order Bits.
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Bit
Rev. 1.1
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C8051F80x-83x
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8.4.1. Window Detector Example
Figure 8.4
shows
two
example
window
comparisons
for
right-justified
data,
with
ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). The input voltage can
range from 0 to VREF x (1023/1024) with respect to GND, and is represented by a 10-bit unsigned integer
value. In the left example, an AD0WINT interrupt will be generated if the ADC0 conversion word
(ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL
(if 0x0040 < ADC0H:ADC0L < 0x0080). In the right example, and AD0WINT interrupt will be generated if
the ADC0 conversion word is outside of the range defined by the ADC0GT and ADC0LT registers
(if ADC0H:ADC0L < 0x0040 or ADC0H:ADC0L > 0x0080). Figure 8.5 shows an example using left-justified data with the same comparison values.
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Figure 8.4. ADC Window Compare Example: Right-Justified Data
55
Figure 8.5. ADC Window Compare Example: Left-Justified Data
Rev. 1.1
C8051F80x-83x
8.5. ADC0 Analog Multiplexer
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ADC0 on the C8051F800/1/2/3/4/5, C8051F812/3/4/5/6/7, C8051F824/5/6, and C8051F830/1/2 uses an
analog input multiplexer to select the positive input to the ADC. Any of the following may be selected as the
positive input: Port 0 or Port 1 I/O pins, the on-chip temperature sensor, or the positive power supply (VDD).
The ADC0 input channel is selected in the ADC0MX register described in SFR Definition 8.9.
Figure 8.6. ADC0 Multiplexer Block Diagram
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Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be configured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for analog
input, set the corresponding bit in register PnMDIN to 0. To force the Crossbar to skip a Port pin, set the
corresponding bit in register PnSKIP to 1. See Section “23. Port Input/Output” on page 138 for more Port
I/O configuration details.
Rev. 1.1
56
C8051F80x-83x
Bit
7
6
5
4
3
2
AMX0P[3:0]
Name
R
R
R
Reset
0
0
0
R/W
1
SFR Address = 0xBB
Bit
Name
1
1
Unused
Read = 000b; Write = Don’t Care.
4:0
AMX0P[4:0]
AMUX0 Positive Input Selection.
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7:5
1
0
1
1
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SFR Definition 8.9. ADC0MX: AMUX0 Channel Select
20-Pin and 24-Pin Devices 16-Pin Devices
00001:
P0.1
00010:
P0.2
00011:
P0.3
00100:
P0.4
00101:
P0.5
P0.0
P0.1
P0.2
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P0.0
P0.4
P0.5
P0.6
P0.6
00111:
P0.7
P0.7
01000
P1.0
P1.0
01001
P1.1
P1.1
01010
P1.2
P1.2
01011
P1.3
P1.3
01100
P1.4
Reserved.
01101
P1.5
Reserved.
01110
P1.6
Reserved.
01111
P1.7
Reserved.
10000:
Temp Sensor
Temp Sensor
10001:
VREG Output
VREG Output
10010:
VDD
VDD
10011:
GND
GND
10100 – 11111:
no input selected
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00110:
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00000:
Rev. 1.1
C8051F80x-83x
9. Temperature Sensor
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An on-chip temperature sensor is included on the C8051F800/1/2/3/4/5, C8051F812/3/4/5/6/7,
C8051F824/5/6, and C8051F830/1/2 which can be directly accessed via the ADC multiplexer in singleended configuration. To use the ADC to measure the temperature sensor, the ADC mux channel should be
configured to connect to the temperature sensor. The temperature sensor transfer function is shown in
Figure 9.1. The output voltage (VTEMP) is the positive ADC input when the ADC multiplexer is set correctly.
The TEMPE bit in register REF0CN enables/disables the temperature sensor, as described in SFR Definition 10.1. While disabled, the temperature sensor defaults to a high impedance state and any ADC measurements performed on the sensor will result in meaningless data. Refer to Table 7.11 for the slope and
offset parameters of the temperature sensor.
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Figure 9.1. Temperature Sensor Transfer Function
9.1. Calibration
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The uncalibrated temperature sensor output is extremely linear and suitable for relative temperature measurements (see Table 5.1 for linearity specifications). For absolute temperature measurements, offset
and/or gain calibration is recommended. Typically a 1-point (offset) calibration includes the following steps:
Control/measure the ambient temperature (this temperature must be known).
Power the device, and delay for a few seconds to allow for self-heating.
Perform an ADC conversion with the temperature sensor selected as the ADC’s input.
Calculate the offset characteristics, and store this value in non-volatile memory for use with subsequent
temperature sensor measurements.
Figure 5.3 shows the typical temperature sensor error assuming a 1-point calibration at 0 °C.
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2.
3.
4.
Parameters that affect ADC measurement, in particular the voltage reference value, will also affect temperature measurement.
Rev. 1.1
58
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C8051F80x-83x
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Figure 9.2. Temperature Sensor Error with 1-Point Calibration at 0 °C
59
Rev. 1.1
C8051F80x-83x
10. Voltage and Ground Reference Options
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The voltage reference MUX is configurable to use an externally connected voltage reference, the on-chip
voltage reference, or one of two power supply voltages (see Figure 10.1). The ground reference MUX
allows the ground reference for ADC0 to be selected between the ground pin (GND) or a port pin dedicated to analog ground (P0.1/AGND).
The voltage and ground reference options are configured using the REF0CN SFR described on page 62.
Electrical specifications are can be found in the Electrical Specifications Chapter.
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Important Note About the VREF and AGND Inputs: Port pins are used as the external VREF and AGND
inputs. When using an external voltage reference, P0.0/VREF should be configured as an analog input and
skipped by the Digital Crossbar. When using AGND as the ground reference to ADC0, P0.1/AGND should
be configured as an analog input and skipped by the Digital Crossbar. Refer to Section “23. Port Input/Output” on page 138 for complete Port I/O configuration details. The external reference voltage must be within
the range 0 VREF VDD and the external ground reference must be at the same DC voltage potential as
GND.
Figure 10.1. Voltage Reference Functional Block Diagram
Rev. 1.1
60
C8051F80x-83x
10.1. External Voltage References
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To use an external voltage reference, REFSL[1:0] should be set to 00. Bypass capacitors should be added
as recommended by the manufacturer of the external voltage reference.
10.2. Internal Voltage Reference Options
A 1.65 V high-speed reference is included on-chip. The high speed internal reference is selected by setting
REFSL[1:0] to 11. When selected, the high speed internal reference will be automatically enabled on an
as-needed basis by ADC0.
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For applications with a non-varying power supply voltage, using the power supply as the voltage reference
can provide ADC0 with added dynamic range at the cost of reduced power supply noise rejection. To use
the 1.8 to 3.6 V power supply voltage (VDD) or the 1.8 V regulated digital supply voltage as the reference
source, REFSL[1:0] should be set to 01 or 10, respectively.
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10.3. Analog Ground Reference
10.4. Temperature Sensor Enable
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To prevent ground noise generated by switching digital logic from affecting sensitive analog measurements, a separate analog ground reference option is available. When enabled, the ground reference for
ADC0 is taken from the P0.1/AGND pin. Any external sensors sampled by ADC0 should be referenced to
the P0.1/AGND pin. The separate analog ground reference option is enabled by setting REFGND to 1.
Note that when using this option, P0.1/AGND must be connected to the same potential as GND.
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The TEMPE bit in register REF0CN enables the temperature sensor. While disabled, the temperature sensor defaults to a high impedance state and any ADC0 measurements performed on the sensor result in
meaningless data.
61
Rev. 1.1
C8051F80x-83x
7
6
5
4
3
REFGND
Name
REFSL
2
BIASE
R/W
R
0
0
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
1
0
0
5
Unused
Function
Read = 00b; Write = Don’t Care.
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7:6
0
TEMPE
Type
SFR Address = 0xD1
Bit
Name
1
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Bit
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SFR Definition 10.1. REF0CN: Voltage Reference Control
REFGND Analog Ground Reference.
Selects the ADC0 ground reference.
0: The ADC0 ground reference is the GND pin.
1: The ADC0 ground reference is the P0.1/AGND pin.
REFSL
2
TEMPE
1
BIASE
0
Unused
Voltage Reference Select.
Selects the ADC0 voltage reference.
00: The ADC0 voltage reference is the P0.0/VREF pin.
01: The ADC0 voltage reference is the VDD pin.
10: The ADC0 voltage reference is the internal 1.8 V digital supply voltage.
11: The ADC0 voltage reference is the internal 1.65 V high speed voltage reference.
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4:3
Temperature Sensor Enable.
Enables/Disables the internal temperature sensor.
0: Temperature Sensor Disabled.
1: Temperature Sensor Enabled.
Internal Analog Bias Generator Enable Bit.
0: Internal Bias Generator off.
1: Internal Bias Generator on.
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Read = 0b; Write = Don’t Care.
Rev. 1.1
62
C8051F80x-83x
11. Voltage Regulator (REG0)
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C8051F80x-83x devices include an internal voltage regulator (REG0) to regulate the internal core supply
to 1.8 V from a VDD supply of 1.8 to 3.6 V. A power-saving mode is built into the regulator to help reduce
current consumption in low-power applications. This mode is accessed through the REG0CN register
(SFR Definition 11.1). Electrical characteristics for the on-chip regulator are specified in Table 7.5 on
page 41
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Under default conditions, when the device enters STOP mode the internal regulator will remain on. This
allows any enabled reset source to generate a reset for the device and bring the device out of STOP mode.
For additional power savings, the STOPCF bit can be used to shut down the regulator and the internal
power network of the device when the part enters STOP mode. When STOPCF is set to 1, the RST pin or
a full power cycle of the device are the only methods of generating a reset.
Rev. 1.1
63
C8051F80x-83x
7
6
5
4
3
2
Name
STOPCF
Type
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
SFR Address = 0xC9
Bit
Name
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64
R/W
R/W
0
0
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ew
Reserved Must write to 0000000b.
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6:0
0
STOPCF Stop Mode Configuration.
This bit configures the regulator’s behavior when the device enters STOP mode.
0: Regulator is still active in STOP mode. Any enabled reset source will reset the
device.
1: Regulator is shut down in STOP mode. Only the RST pin or power cycle can reset
the device.
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7
Function
1
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Bit
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SFR Definition 11.1. REG0CN: Voltage Regulator Control
Rev. 1.1
C8051F80x-83x
12. Comparator0
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C8051F80x-83x devices include an on-chip programmable voltage comparator, Comparator0, shown in
Figure 12.1.
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The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0), or an asynchronous “raw” output (CP0A). The asynchronous CP0A signal is available even when the system clock is
not active. This allows the Comparator to operate and generate an output with the device in STOP mode.
When assigned to a Port pin, the Comparator output may be configured as open drain or push-pull (see
Section “23.4. Port I/O Initialization” on page 147). Comparator0 may also be used as a reset source (see
Section “21.5. Comparator0 Reset” on page 127).
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The Comparator0 inputs are selected by the comparator input multiplexer, as detailed in Section
“12.1. Comparator Multiplexer” on page 69.
Figure 12.1. Comparator0 Functional Block Diagram
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The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin.
When routed to a Port pin, the Comparator output is available asynchronous or synchronous to the system
clock; the asynchronous output is available even in STOP mode (with no system clock active). When disabled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state,
and the power supply to the comparator is turned off. See Section “23.3. Priority Crossbar Decoder” on
page 143 for details on configuring Comparator outputs via the digital Crossbar. Comparator inputs can be
externally driven from –0.25 V to (VDD) + 0.25 V without damage or upset. The complete Comparator electrical specifications are given in Section “7. Electrical Characteristics” on page 39.
Rev. 1.1
65
C8051F80x-83x
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The Comparator response time may be configured in software via the CPT0MD register (see SFR Definition 12.2). Selecting a longer response time reduces the Comparator supply current.
Figure 12.2. Comparator Hysteresis Plot
The Comparator hysteresis is software-programmable via its Comparator Control register CPT0CN. The
user can program both the amount of hysteresis voltage (referred to the input voltage) and the positive and
negative-going symmetry of this hysteresis around the threshold voltage.
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The Comparator hysteresis is programmed using bits 3:0 in the Comparator Control Register CPT0CN
(shown in SFR Definition 12.1). The amount of negative hysteresis voltage is determined by the settings of
the CP0HYN bits. As shown in Figure 12.2, settings of 20, 10 or 5 mV of negative hysteresis can be programmed, or negative hysteresis can be disabled. In a similar way, the amount of positive hysteresis is
determined by the setting the CP0HYP bits.
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Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Interrupt enable and priority control, see Section “18.1. MCU Interrupt Sources and Vectors” on page 103). The
CP0FIF flag is set to logic 1 upon a Comparator falling-edge occurrence, and the CP0RIF flag is set to
logic 1 upon the Comparator rising-edge occurrence. Once set, these bits remain set until cleared by software. The Comparator rising-edge interrupt mask is enabled by setting CP0RIE to a logic 1. The Comparator0 falling-edge interrupt mask is enabled by setting CP0FIE to a logic 1.
The output state of the Comparator can be obtained at any time by reading the CP0OUT bit. The Comparator is enabled by setting the CP0EN bit to logic 1, and is disabled by clearing this bit to logic 0.
Note that false rising edges and falling edges can be detected when the comparator is first powered on or
if changes are made to the hysteresis or response time control bits. Therefore, it is recommended that the
rising-edge and falling-edge flags be explicitly cleared to logic 0 a short time after the comparator is
enabled or its mode bits have been changed.
66
Rev. 1.1
C8051F80x-83x
Bit
7
6
5
4
2
Name
CP0EN
CP0OUT
CP0RIF
CP0FIF
CP0HYP[1:0]
Type
R/W
R
R/W
R/W
R/W
Reset
0
0
0
0
0
SFR Address = 0x9B
Bit
Name
Function
0
CP0HYN[1:0]
R/W
0
0
0
CP0EN
6
CP0OUT
Comparator0 Output State Flag.
0: Voltage on CP0+ < CP0–.
1: Voltage on CP0+ > CP0–.
5
CP0RIF
Comparator0 Rising-Edge Flag. Must be cleared by software.
0: No Comparator0 Rising Edge has occurred since this flag was last cleared.
1: Comparator0 Rising Edge has occurred.
4
CP0FIF
Comparator0 Falling-Edge Flag. Must be cleared by software.
0: No Comparator0 Falling-Edge has occurred since this flag was last cleared.
1: Comparator0 Falling-Edge has occurred.
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Comparator0 Enable Bit.
0: Comparator0 Disabled.
1: Comparator0 Enabled.
1
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SFR Definition 12.1. CPT0CN: Comparator0 Control
3:2 CP0HYP[1:0] Comparator0 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 mV.
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1:0 CP0HYN[1:0] Comparator0 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 mV.
Rev. 1.1
67
C8051F80x-83x
7
6
Name
5
4
CP0RIE
CP0FIE
3
2
R
R
R/W
R/W
R
R
Reset
0
0
0
0
0
0
Function
Unused
Read = 00b, Write = Don’t Care.
5
CP0RIE
Comparator0 Rising-Edge Interrupt Enable.
0: Comparator0 Rising-edge interrupt disabled.
1: Comparator0 Rising-edge interrupt enabled.
4
CP0FIE
Comparator0 Falling-Edge Interrupt Enable.
0: Comparator0 Falling-edge interrupt disabled.
1: Comparator0 Falling-edge interrupt enabled.
3:2
Unused
Read = 00b, Write = don’t care.
1
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CP0MD[1:0] Comparator0 Mode Select.
These bits affect the response time and power consumption for Comparator0.
00: Mode 0 (Fastest Response Time, Highest Power Consumption)
01: Mode 1
10: Mode 2
11: Mode 3 (Slowest Response Time, Lowest Power Consumption)
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68
R/W
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7:6
1:0
0
CP0MD[1:0]
Type
SFR Address = 0x9D
Bit
Name
1
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Bit
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SFR Definition 12.2. CPT0MD: Comparator0 Mode Selection
Rev. 1.1
0
C8051F80x-83x
12.1. Comparator Multiplexer
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C8051F80x-83x devices include an analog input multiplexer to connect Port I/O pins to the comparator
inputs. The Comparator0 inputs are selected in the CPT0MX register (SFR Definition 12.3). The CMX0P3–
CMX0P0 bits select the Comparator0 positive input; the CMX0N3–CMX0N0 bits select the Comparator0
negative input. Important Note About Comparator Inputs: The Port pins selected as comparator inputs
should be configured as analog inputs in their associated Port configuration register, and configured to be
skipped by the Crossbar (for details on Port configuration, see Section “23.6. Special Function Registers
for Accessing and Configuring Port I/O” on page 152).
Figure 12.3. Comparator Input Multiplexer Block Diagram
Rev. 1.1
69
C8051F80x-83x
Bit
7
6
5
4
3
2
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SFR Definition 12.3. CPT0MX: Comparator0 MUX Selection
1
Name
CMX0N[3:0]
CMX0P[3:0]
Type
R/W
R/W
1
1
1
SFR Address = 0x9F
Bit
Name
Function
20-Pin and 24-Pin Devices
P0.1
P0.3
P0.5
P0.7
P1.1
P1.3
P1.5
P1.7
VREG Output.
No input selected.
16-Pin Devices
P0.1
P0.3
P0.5
P0.7
P1.1
P1.3
Reserved.
Reserved.
VREG Output.
No input selected.
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CMX0P[3:0] Comparator0 Positive Input MUX Selection.
20-Pin and 24-Pin Devices
P0.0
P0.2
P0.4
P0.6
P1.0
P1.2
P1.4
P1.6
VREG Output.
No input selected.
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0000
0001
0010
0011
0100
0101
0110
0111
1000
1001–1111
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1
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CMX0N[3:0] Comparator0 Negative Input MUX Selection.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001–1111
3:0
1
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7:4
1
D
1
Reset
Rev. 1.1
16-Pin Devices
P0.0
P0.2
P0.4
P0.6
P1.0
P1.2
Reserved.
Reserved.
VREG Output.
No input selected.
0
1
C8051F80x-83x
13. Capacitive Sense (CS0)
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The Capacitive Sense subsystem included on the C8051F800/1/3/4/6/7/9, C8051F810/2/3/5/6/8/9,
C8051F821/2/4/5/7/8, C8051F830/1/3/4 uses a capacitance-to-digital circuit to determine the capacitance
on a port pin. The module can take measurements from different port pins using the module’s analog multiplexer. The multiplexer supports up to 16 channels. See SFR Definition 13.9. “CS0MX: Capacitive Sense
Mux Channel Select” on page 81 for channel availability for specific part numbers. The module is enabled
only when the CS0EN bit (CS0CN) is set to 1. Otherwise the module is in a low-power shutdown state. The
module can be configured to take measurements on one port pin or a group of port pins, using auto-scan.
An accumulator can be configured to accumulate multiple conversions on an input channel. Interrupts can
be generated when CS0 completes a conversion or when the measured value crosses a threshold defined
in CS0THH:L.
Figure 13.1. CS0 Block Diagram
Rev. 1.1
71
C8051F80x-83x
13.1. Configuring Port Pins as Capacitive Sense Inputs
13.2. Capacitive Sense Start-Of-Conversion Sources
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In order for a port pin to be measured by CS0, that port pin must be configured as an analog input (see “23.
Port Input/Output” ). Configuring the input multiplexer to a port pin not configured as an analog input will
cause the capacitive sense comparator to output incorrect measurements.
A capacitive sense conversion can be initiated in one of seven ways, depending on the programmed state
of the CS0 start of conversion bits (CS0CF6:4). Conversions may be initiated by one of the following:
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1. Writing a 1 to the CS0BUSY bit of register CS0CN
2. Timer 0 overflow
3. Timer 2 overflow
4. Timer 1 overflow
5. Convert continuously
6. Convert continuously with auto-scan enabled
Conversions can be configured to be initiated continuously through one of two methods. CS0 can be configured to convert at a single channel continuously or it can be configured to convert continuously with
auto-scan enabled. When configured to convert continuously, conversions will begin after the CS0BUSY
bit in CS0CF has been set.
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An interrupt will be generated if CS0 conversion complete interrupts are enabled by setting the ECSCPT
bit (EIE2.0).
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Note: CS0 conversion complete interrupt behavior depends on the settings of the CS0 accumulator. If CS0 is
configured to accumulate multiple conversions on an input channel, a CS0 conversion complete interrupt will
be generated only after the last conversion completes.
13.3. Automatic Scanning
CS0 can be configured to automatically scan a sequence of contiguous CS0 input channels by configuring
and enabling auto-scan. Using auto-scan with the CS0 comparator interrupt enabled allows a system to
detect a change in measured capacitance without requiring any additional dedicated MCU resources.
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Auto-scan is enabled by setting the CS0 start-of-conversion bits (CS0CF6:4) to 111b. After enabling autoscan, the starting and ending channels should be set to appropriate values in CS0SS and CS0SE, respectively. Writing to CS0SS when auto-scan is enabled will cause the value written to CS0SS to be copied into
CS0MX. After being enabled, writing a 1 to CS0BUSY will start auto-scan conversions. When auto-scan
completes the number of conversions defined in the CS0 accumulator bits (CS0CF1:0) (see “13.5. CS0
Conversion Accumulator” ), auto-scan configures CS0MX to the next highest port pin configured as an
analog input and begins a conversion on that channel. This scan sequence continues until CS0MX
reaches the ending input channel value defined in CS0SE. After one or more conversions have been taken
at this channel, auto-scan configures CS0MX back to the starting input channel. For an example system
configured to use auto-scan, please see Figure “13.2 Auto-Scan Example” on page 73.
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Note: Auto-scan attempts one conversion on a CS0MX channel regardless of whether that channel’s port pin has
been configured as an analog input.
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If auto-scan is enabled when the device enters suspend mode, auto-scan will remain enabled and running.
This feature allows the device to wake from suspend through CS0 greater-than comparator event on any
configured capacitive sense input included in the auto-scan sequence of inputs.
72
Rev. 1.1
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C8051F80x-83x
Figure 13.2. Auto-Scan Example
13.4. CS0 Comparator
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The CS0 comparator compares the latest capacitive sense conversion result with the value stored in
CS0THH:CS0THL. If the result is less than or equal to the stored value, the CS0CMPF bit(CS0CN:0) is set
to 0. If the result is greater than the stored value, CS0CMPF is set to 1.
If the CS0 conversion accumulator is configured to accumulate multiple conversions, a comparison will not
be made until the last conversion has been accumulated.
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An interrupt will be generated if CS0 greater-than comparator interrupts are enabled by setting the ECSGRT bit (EIE2.1) when the comparator sets CS0CMPF to 1.
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If auto-scan is running when the comparator sets the CS0CMPF bit, no further auto-scan initiated conversions will start until firmware sets CS0BUSY to 1.
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A CS0 greater-than comparator event can wake a device from suspend mode. This feature is useful in systems configured to continuously sample one or more capacitive sense channels. The device will remain in
the low-power suspend state until the captured value of one of the scanned channels causes a CS0
greater-than comparator event to occur. It is not necessary to have CS0 comparator interrupts enabled in
order to wake a device from suspend with a greater-than event.
Note: On waking from suspend mode due to a CS0 greater-than comparator event, the CS0CN register
should be accessed only after at least two system clock cycles have elapsed.
For a summary of behavior with different CS0 comparator, auto-scan, and auto accumulator settings,
please see Table 13.1.
Rev. 1.1
73
C8051F80x-83x
13.5. CS0 Conversion Accumulator
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CS0 can be configured to accumulate multiple conversions on an input channel. The number of samples to
be accumulated is configured using the CS0ACU2:0 bits (CS0CF2:0). The accumulator can accumulate 1,
4, 8, 16, 32, or 64 samples. After the defined number of samples have been accumulated, the result is converted to a 16-bit value by dividing the 22-bit accumulator by either 1, 4, 8, 16, 32, or 64 (depending on the
CS0ACU[2:0] setting) and copied to the CS0DH:CS0DL SFRs.
Accumulator Enabled
CS0 Conversion
Complete
Interrupt
Behavior
CS0 Greater Than Interrupt
Behavior
Interrupt serviced after 1 conversion completes if value in
CS0DH:CS0DL is greater than
CS0THH:CS0THL
CS0MX Behavior
N
N
CS0INT Interrupt
serviced after 1
conversion completes
N
Y
CS0INT Interrupt Interrupt serviced after M conversions complete if value in
serviced after M
conversions com- 16-bit accumulator is greater
than CS0THH:CS0THL
plete
Y
N
CS0INT Interrupt
serviced after 1
conversion completes
Y
Y
CS0INT Interrupt Interrupt serviced after M con- If greater-than comparator detects converserviced after M
versions complete if value in
sion value is greater than
conversions com- 16-bit accumulator is greater
CS0THH:CS0THL, CS0MX is left
plete
than CS0THH:CS0THL; Auto- unchanged; otherwise, CS0MX updates to
Scan stopped
the next channel (CS0MX + 1) and wraps
back to CS0SS after passing CS0SE
CS0MX unchanged.
CS0MX unchanged.
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Auto-Scan Enabled
Table 13.1. Operation with Auto-scan and Accumulate
M = Accumulator setting (1x, 4x, 8x, 16x, 32x, 64x)
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Interrupt serviced after con- If greater-than comparator detects converversion completes if value in
sion value is greater than
CS0DH:CS0DL is greater than
CS0THH:CS0THL, CMUX0 is left
CS0THH:CS0THL;
unchanged; otherwise, CMUX0 updates to
the next channel (CS0MX + 1) and wraps
Auto-Scan stopped
back to CS0SS after passing CS0SE
74
Rev. 1.1
C8051F80x-83x
Bit
7
5
Name
CS0EN
Type
R/W
R
R/W
R/W
R/W
R
Reset
0
0
0
0
0
0
CS0INT
4
3
CS0BUSY CS0CMPEN
SFR Address = 0xB0; Bit-Addressable
Bit
Name
CS0EN
6
Unused
5
CS0INT
4
CS0BUSY
3
CS0CMPEN
Description
CS0 Enable.
0: CS0 disabled and in low-power mode.
1: CS0 enabled and ready to convert.
Read = 0b; Write = Don’t care
1
0
CS0CMPF
R
R
0
0
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SFR Definition 13.1. CS0CN: Capacitive Sense Control
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CS0 Interrupt Flag.
0: CS0 has not completed a data conversion since the last time CS0INT was
cleared.
1: CS0 has completed a data conversion.
This bit is not automatically cleared by hardware.
CS0CMPF
R
0
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CS0 Digital Comparator Enable Bit.
Enables the digital comparator, which compares accumulated CS0 conversion
output to the value stored in CS0THH:CS0THL.
0: CS0 digital comparator disabled.
1: CS0 digital comparator enabled.
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Unused
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2:1
CS0 Busy.
Read:
0: CS0 conversion is complete or a conversion is not currently in progress.
1: CS0 conversion is in progress.
Write:
0: No effect.
1: Initiates CS0 conversion if CS0CM[2:0] = 000b, 110b, or 111b.
Read = 00b; Write = Don’t care
CS0 Digital Comparator Interrupt Flag.
0: CS0 result is smaller than the value set by CS0THH and CS0THL since the last
time CS0CMPF was cleared.
1: CS0 result is greater than the value set by CS0THH and CS0THL since the last
time CS0CMPF was cleared.
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Note: On waking from suspend mode due to a CS0 greater-than comparator event, the CS0CN register
should be accessed only after at least two system clock cycles have elapsed.
Rev. 1.1
75
C8051F80x-83x
7
6
5
4
3
2
CS0CM[2:0]
Name
R
R/W
R/W
R/W
R
R/W
Reset
0
0
0
0
0
0
SFR Address = 0x9E
Bit
Name
Read = 0b; Write = Don’t care
CS0CM[2:0]
3
Unused
2:0
CS0ACU[2:0]
R/W
0
0
CS0 Start of Conversion Mode Select.
000: Conversion initiated on every write of 1 to CS0BUSY.
001: Conversion initiated on overflow of Timer 0.
010: Conversion initiated on overflow of Timer 2.
011: Conversion initiated on overflow of Timer 1.
100: Reserved.
101: Reserved.
110: Conversion initiated continuously after writing 1 to CS0BUSY.
111: Auto-scan enabled, conversions initiated continuously after writing 1 to
CS0BUSY.
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Read = 0b; Write = Don’t care
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CS0 Accumulator Mode Select.
000: Accumulate 1 sample.
001: Accumulate 4 samples.
010: Accumulate 8 samples.
011: Accumulate 16 samples
100: Accumulate 32 samples.
101: Accumulate 64 samples.
11x: Reserved.
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R/W
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6:4
Description
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Unused
0
CS0ACU[2:0]
Type
7
1
D
Bit
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SFR Definition 13.2. CS0CF: Capacitive Sense Configuration
Rev. 1.1
C8051F80x-83x
Bit
7
6
5
4
3
2
CS0DH[7:0]
Name
R
R
R
R
R
R
Reset
0
0
0
0
0
0
SFR Address = 0xAC
Bit
Name
CS0DH
0
R
R
0
0
Description
CS0 Data High Byte.
Stores the high byte of the last completed 16-bit Capacitive Sense conversion.
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1
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Type
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SFR Definition 13.3. CS0DH: Capacitive Sense Data High Byte
Bit
7
6
5
4
3
2
1
0
CS0DL[7:0]
Name
R
Reset
0
R
R
R
R
R
R
R
0
0
0
0
0
0
0
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Type
SFR Address = 0xAB
Bit
Name
CS0DL
Description
CS0 Data Low Byte.
Stores the low byte of the last completed 16-bit Capacitive Sense conversion.
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7:0
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SFR Definition 13.4. CS0DL: Capacitive Sense Data Low Byte
Rev. 1.1
77
C8051F80x-83x
Bit
7
6
5
4
3
2
CS0SS[4:0]
Name
R
R
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
SFR Address = 0xB9
Bit
Name
Unused
4:0
CS0SS[4:0]
0
R/W
R/W
0
0
Description
Read = 000b; Write = Don’t care
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7:5
1
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Type
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SFR Definition 13.5. CS0SS: Capacitive Sense Auto-Scan Start Channel
Starting Channel for Auto-Scan.
Sets the first CS0 channel to be selected by the mux for Capacitive Sense conversion when auto-scan is enabled and active.
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When auto-scan is enabled, a write to CS0SS will also update CS0MX.
Bit
7
Name
Type
R
Reset
0
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SFR Definition 13.6. CS0SE: Capacitive Sense Auto-Scan End Channel
6
5
4
0
CS0SE[4:0]
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
Description
Read = 000b; Write = Don’t care
R
Ending Channel for Auto-Scan.
Sets the last CS0 channel to be selected by the mux for Capacitive Sense conversion when auto-scan is enabled and active.
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1
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CS0SE[4:0]
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4:0
Unused
2
R
SFR Address = 0xBA
Bit
Name
7:5
3
Rev. 1.1
C8051F80x-83x
Bit
7
6
5
4
3
2
CS0THH[7:0]
Name
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
SFR Address = 0x97
Bit
Name
CS0THH[7:0]
0
R/W
R/W
0
0
Description
CS0 Comparator Threshold High Byte.
High byte of the 16-bit value compared to the Capacitive Sense conversion result.
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7:0
1
D
Type
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SFR Definition 13.7. CS0THH: Capacitive Sense Comparator Threshold High Byte
Bit
7
6
5
4
3
2
1
0
CS0THL[7:0]
Name
R/W
Reset
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
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Type
SFR Address = 0x96
Bit
Name
CS0THL[7:0]
Description
CS0 Comparator Threshold Low Byte.
Low byte of the 16-bit value compared to the Capacitive Sense conversion result.
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7:0
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SFR Definition 13.8. CS0THL: Capacitive Sense Comparator Threshold Low Byte
Rev. 1.1
79
C8051F80x-83x
13.6. Capacitive Sense Multiplexer
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The input multiplexer can be controlled through two methods. The CS0MX register can be written to
through firmware, or the register can be configured automatically using the modules auto-scan functionality
(see “13.3. Automatic Scanning” ).
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Figure 13.3. CS0 Multiplexer Block Diagram
Rev. 1.1
80
C8051F80x-83x
Bit
7
6
5
4
3
Name
CS0UC
Type
R/W
R
R
R
R/W
R/W
Reset
1
0
0
1
1
1
2
CS0UC
6:4
Reserved
3:0
CS0MX[3:0]
R/W
1
1
D
Description
CS0 Unconnected.
Disconnects CS0 from all port pins, regardless of the selected channel.
0: CS0 connected to port pins
1: CS0 disconnected from port pins
Read = 000b; Write = 000b
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CS0 Mux Channel Select.
Selects one of the 16 input channels for Capacitive Sense conversion.
C8051F800/6,
C8051F812/8
C8051F803/9,
C8051F815,
C8051F821/4/7,
C8051F830/3
C8051F801/4/7,
C8051F810/3/6/9,
C8051F822/5/8,
C8051F831/4
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Value
0000
P0.0
P0.0
P0.0
0001
P0.1
P0.1
P0.1
0010
P0.2
P0.2
P0.2
0011
P0.3
P0.3
P0.3
0100
P0.4
P0.4
P0.4
0101
P0.5
P0.5
P0.5
0110
P0.6
P0.6
P0.6
0111
P0.7
P0.7
P0.7
1000
P1.0
P1.0
Reserved.
1001
P1.1
P1.1
Reserved.
1010
P1.2
P1.2
Reserved.
1011
P1.3
P1.3
Reserved.
1100
P1.4
Reserved.
Reserved.
1101
P1.5
Reserved.
Reserved.
1110
P1.6
Reserved.
Reserved.
1111
P1.7
Reserved.
Reserved.
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R
0
R/W
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7
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1
CS0MX[3:0]
SFR Address = 0x9C
Bit
Name
Note: CS0MX is Reserved on all the devices that are not listed in the above table.
81
es
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SFR Definition 13.9. CS0MX: Capacitive Sense Mux Channel Select
Rev. 1.1
C8051F80x-83x
14. CIP-51 Microcontroller
es
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The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has a superset of all the peripherals included with a standard 8051. The CIP-51
also includes on-chip debug hardware (see description in Section 30), and interfaces directly with the analog and digital subsystems providing a complete data acquisition or control-system solution in a single integrated circuit.
Reset
25
Compatible with MCS-51 Instruction Set
MIPS Peak Throughput with 25 MHz Clock
0 to 25 MHz Clock Frequency
Extended Interrupt Handler
Power
Input
Management Modes
On-chip Debug Logic
Program and Data Memory Security
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Fully
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The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 14.1 for a block diagram).
The CIP-51 includes the following features:
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Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51
core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.
Figure 14.1. CIP-51 Block Diagram
Rev. 1.1
82
C8051F80x-83x
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With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has
a total of 109 instructions. The table below shows the total number of instructions that require each execution time.
Clocks to Execute
1
2
2/3
3
3/4
4
4/5
5
8
Number of Instructions
26
50
5
14
6
3
2
2
1
14.1. Instruction Set
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The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruction set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51
instructions are the binary and functional equivalent of their MCS-51™ counterparts, including opcodes,
addressing modes and effect on PSW flags. However, instruction timing is different than that of the standard 8051.
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14.1.1. Instruction and CPU Timing
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with
machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based
solely on clock cycle timing. All instruction timings are specified in terms of clock cycles.
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Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock
cycles as there are program bytes in the instruction. Conditional branch instructions take one less clock
cycle to complete when the branch is not taken as opposed to when the branch is taken. Table 14.1 is the
CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock
cycles for each instruction.
83
Rev. 1.1
C8051F80x-83x
Table 14.1. CIP-51 Instruction Set Summary
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AND Register to A
AND direct byte to A
AND indirect RAM to A
AND immediate to A
AND A to direct byte
AND immediate to direct byte
OR Register to A
OR direct byte to A
OR indirect RAM to A
OR immediate to A
OR A to direct byte
OR immediate to direct byte
Exclusive-OR Register to A
Exclusive-OR direct byte to A
Exclusive-OR indirect RAM to A
Exclusive-OR immediate to A
Exclusive-OR A to direct byte
Rev. 1.1
Clock
Cycles
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Add register to A
Add direct byte to A
Add indirect RAM to A
Add immediate to A
Add register to A with carry
Add direct byte to A with carry
Add indirect RAM to A with carry
Add immediate to A with carry
Subtract register from A with borrow
Subtract direct byte from A with borrow
Subtract indirect RAM from A with borrow
Subtract immediate from A with borrow
Increment A
Increment register
Increment direct byte
Increment indirect RAM
Decrement A
Decrement register
Decrement direct byte
Decrement indirect RAM
Increment Data Pointer
Multiply A and B
Divide A by B
Decimal adjust A
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Arithmetic Operations
ADD A, Rn
ADD A, direct
ADD A, @Ri
ADD A, #data
ADDC A, Rn
ADDC A, direct
ADDC A, @Ri
ADDC A, #data
SUBB A, Rn
SUBB A, direct
SUBB A, @Ri
SUBB A, #data
INC A
INC Rn
INC direct
INC @Ri
DEC A
DEC Rn
DEC direct
DEC @Ri
INC DPTR
MUL AB
DIV AB
DA A
Logical Operations
ANL A, Rn
ANL A, direct
ANL A, @Ri
ANL A, #data
ANL direct, A
ANL direct, #data
ORL A, Rn
ORL A, direct
ORL A, @Ri
ORL A, #data
ORL direct, A
ORL direct, #data
XRL A, Rn
XRL A, direct
XRL A, @Ri
XRL A, #data
XRL direct, A
Bytes
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
1
2
2
2
1
2
2
2
1
2
2
2
1
1
2
2
1
1
2
2
1
4
8
1
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
1
2
2
2
2
3
1
2
2
2
2
3
1
2
2
2
2
D
Description
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Mnemonic
84
C8051F80x-83x
Description
Bytes
3
1
1
1
1
1
1
1
Clock
Cycles
3
1
1
1
1
1
1
1
XRL direct, #data
CLR A
CPL A
RL A
RLC A
RR A
RRC A
SWAP A
Data Transfer
MOV A, Rn
MOV A, direct
MOV A, @Ri
MOV A, #data
MOV Rn, A
MOV Rn, direct
MOV Rn, #data
MOV direct, A
MOV direct, Rn
MOV direct, direct
MOV direct, @Ri
MOV direct, #data
MOV @Ri, A
MOV @Ri, direct
MOV @Ri, #data
MOV DPTR, #data16
MOVC A, @A+DPTR
MOVC A, @A+PC
MOVX A, @Ri
MOVX @Ri, A
MOVX A, @DPTR
MOVX @DPTR, A
PUSH direct
POP direct
XCH A, Rn
XCH A, direct
XCH A, @Ri
XCHD A, @Ri
Boolean Manipulation
CLR C
CLR bit
SETB C
SETB bit
CPL C
CPL bit
Exclusive-OR immediate to direct byte
Clear A
Complement A
Rotate A left
Rotate A left through Carry
Rotate A right
Rotate A right through Carry
Swap nibbles of A
Move Register to A
Move direct byte to A
Move indirect RAM to A
Move immediate to A
Move A to Register
Move direct byte to Register
Move immediate to Register
Move A to direct byte
Move Register to direct byte
Move direct byte to direct byte
Move indirect RAM to direct byte
Move immediate to direct byte
Move A to indirect RAM
Move direct byte to indirect RAM
Move immediate to indirect RAM
Load DPTR with 16-bit constant
Move code byte relative DPTR to A
Move code byte relative PC to A
Move external data (8-bit address) to A
Move A to external data (8-bit address)
Move external data (16-bit address) to A
Move A to external data (16-bit address)
Push direct byte onto stack
Pop direct byte from stack
Exchange Register with A
Exchange direct byte with A
Exchange indirect RAM with A
Exchange low nibble of indirect RAM with A
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
1
1
1
2
2
1
2
1
1
1
2
2
2
1
2
2
2
2
3
2
3
2
2
2
3
3
3
3
3
3
3
2
2
1
2
2
2
Clear Carry
Clear direct bit
Set Carry
Set direct bit
Complement Carry
Complement direct bit
1
2
1
2
1
2
1
2
1
2
1
2
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Mnemonic
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Table 14.1. CIP-51 Instruction Set Summary (Continued)
Rev. 1.1
C8051F80x-83x
Description
Bytes
ANL C, bit
ANL C, /bit
ORL C, bit
ORL C, /bit
MOV C, bit
MOV bit, C
JC rel
JNC rel
JB bit, rel
JNB bit, rel
JBC bit, rel
Program Branching
ACALL addr11
LCALL addr16
RET
RETI
AJMP addr11
LJMP addr16
SJMP rel
JMP @A+DPTR
JZ rel
JNZ rel
CJNE A, direct, rel
CJNE A, #data, rel
CJNE Rn, #data, rel
AND direct bit to Carry
AND complement of direct bit to Carry
OR direct bit to carry
OR complement of direct bit to Carry
Move direct bit to Carry
Move Carry to direct bit
Jump if Carry is set
Jump if Carry is not set
Jump if direct bit is set
Jump if direct bit is not set
Jump if direct bit is set and clear bit
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CJNE @Ri, #data, rel
2
3
1
1
2
3
2
1
2
2
3
3
3
3
4
5
5
3
4
3
3
2/3
2/3
4/5
3/4
3/4
3
4/5
2
3
1
2/3
3/4
1
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DJNZ Rn, rel
DJNZ direct, rel
NOP
Absolute subroutine call
Long subroutine call
Return from subroutine
Return from interrupt
Absolute jump
Long jump
Short jump (relative address)
Jump indirect relative to DPTR
Jump if A equals zero
Jump if A does not equal zero
Compare direct byte to A and jump if not equal
Compare immediate to A and jump if not equal
Compare immediate to Register and jump if not
equal
Compare immediate to indirect and jump if not
equal
Decrement Register and jump if not zero
Decrement direct byte and jump if not zero
No operation
2
2
2
2
2
2
2
2
3
3
3
Clock
Cycles
2
2
2
2
2
2
2/3
2/3
3/4
3/4
3/4
D
Mnemonic
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Table 14.1. CIP-51 Instruction Set Summary (Continued)
Rev. 1.1
86
C8051F80x-83x
Rn—Register R0–R7 of the currently selected register bank.
@Ri—Data RAM location addressed indirectly through R0 or R1.
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Notes on Registers, Operands and Addressing Modes:
rel—8-bit, signed (twos complement) offset relative to the first byte of the following instruction. Used by
SJMP and all conditional jumps.
D
direct—8-bit internal data location’s address. This could be a direct-access Data RAM location (0x00–
0x7F) or an SFR (0x80–0xFF).
#data—8-bit constant
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#data16—16-bit constant
bit—Direct-accessed bit in Data RAM or SFR
addr11—11-bit destination address used by ACALL and AJMP. The destination must be within the
same 2 kB page of program memory as the first byte of the following instruction.
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addr16—16-bit destination address used by LCALL and LJMP. The destination may be anywhere within
the 8 kB program memory space.
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There is one unused opcode (0xA5) that performs the same function as NOP.
All mnemonics copyrighted © Intel Corporation 1980.
87
Rev. 1.1
C8051F80x-83x
14.2. CIP-51 Register Descriptions
SFR Definition 14.1. DPL: Data Pointer Low Byte
7
6
5
4
3
DPL[7:0]
Type
R/W
0
Reset
0
0
0
SFR Address = 0x82
Bit
Name
0
0
0
3
2
1
0
0
0
0
0
Function
Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR.
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DPL[7:0]
0
0
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7:0
1
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Name
2
D
Bit
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Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits
should always be written to the value indicated in the SFR description. Future product versions may use
these bits to implement new features in which case the reset value of the bit will be the indicated value,
selecting the feature's default state. Detailed descriptions of the remaining SFRs are included in the sections of the data sheet associated with their corresponding system function.
SFR Definition 14.2. DPH: Data Pointer High Byte
Bit
7
6
4
DPH[7:0]
Name
R/W
Type
0
Reset
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SFR Address = 0x83
Bit
Name
DPH[7:0]
0
0
Function
Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR.
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7:0
5
Rev. 1.1
88
C8051F80x-83x
7
6
5
4
Name
SP[7:0]
Type
R/W
0
Reset
0
0
0
SFR Address = 0x81
Bit
Name
SP[7:0]
6
5
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7
0
1
1
4
3
2
1
0
0
0
0
0
ACC[7:0]
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R/W
Type
0
Reset
0
0
0
SFR Address = 0xE0; Bit-Addressable
Bit
Name
Accumulator.
This register is the accumulator for arithmetic operations.
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ACC[7:0]
Function
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1
1
Stack Pointer.
The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented before every PUSH operation. The SP register defaults to 0x07 after reset.
Name
7:0
0
Function
SFR Definition 14.4. ACC: Accumulator
Bit
2
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7:0
3
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Bit
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SFR Definition 14.3. SP: Stack Pointer
Rev. 1.1
C8051F80x-83x
7
6
5
4
Name
B[7:0]
Type
R/W
0
Reset
0
0
SFR Address = 0xF0; Bit-Addressable
Bit
Name
B[7:0]
2
0
0
Function
1
0
0
0
B Register.
This register serves as a second accumulator for certain arithmetic operations.
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7:0
0
3
D
Bit
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SFR Definition 14.5. B: B Register
Rev. 1.1
90
C8051F80x-83x
7
6
5
4
3
Name
CY
AC
F0
RS[1:0]
OV
Type
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
SFR Address = 0xD0; Bit-Addressable
Bit
Name
0
Function
2
0
1
0
F1
PARITY
R/W
R
0
0
D
Bit
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SFR Definition 14.6. PSW: Program Status Word
CY
Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow (subtraction). It is cleared to logic 0 by all other arithmetic operations.
6
AC
Auxiliary Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a
borrow from (subtraction) the high order nibble. It is cleared to logic 0 by all other arithmetic operations.
5
F0
User Flag 0.
This is a bit-addressable, general purpose flag for use under software control.
4:3
RS[1:0]
2
OV
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7
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Register Bank Select.
These bits select which register bank is used during register accesses.
00: Bank 0, Addresses 0x00-0x07
01: Bank 1, Addresses 0x08-0x0F
10: Bank 2, Addresses 0x10-0x17
11: Bank 3, Addresses 0x18-0x1F
Overflow Flag.
This bit is set to 1 under the following circumstances:
An
ADD, ADDC, or SUBB instruction causes a sign-change overflow.
MUL instruction results in an overflow (result is greater than 255).
A DIV instruction causes a divide-by-zero condition.
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A
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all
other cases.
F1
User Flag 1.
This is a bit-addressable, general purpose flag for use under software control.
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1
PARITY
Parity Flag.
This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared
if the sum is even.
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0
91
Rev. 1.1
C8051F80x-83x
15. Memory Organization
Figure 15.1. C8051F80x-83x Memory Map
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The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The memory organization of the
C8051F80x-83x device family is shown in Figure 15.1
Rev. 1.1
92
C8051F80x-83x
15.1. Program Memory
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The members of the C8051F80x-83x device family contain 16 kB (C8051F80x and C8051F810/1), 8 kB
(C8051F812/3/4/5/6/7/8/9 and C8051F82x), or 4 kB (C8051F830/1/2/3/4/5) of re-programmable Flash
memory that can be used as non-volatile program or data storage. The last byte of user code space is
used as the security lock byte (0x3FFF on 16 kB devices, 0x1FFF on 8 kB devices and 0x0FFF on 4 kB
devices).
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Figure 15.2. Flash Program Memory Map
15.1.1. MOVX Instruction and Program Memory
The MOVX instruction in an 8051 device is typically used to access external data memory. On the
C8051F80x-83x devices, the MOVX instruction is normally used to read and write on-chip XRAM, but can
be re-configured to write and erase on-chip Flash memory space. MOVC instructions are always used to
read Flash memory, while MOVX write instructions are used to erase and write Flash. This Flash access
feature provides a mechanism for the C8051F80x-83x to update program code and use the program memory space for non-volatile data storage. Refer to Section “19. Flash Memory” on page 113 for further
details.
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15.2. Data Memory
ec
The members of the C8051F80x-83x device family contain 512 bytes (C8051F80x, C8051F81x, and
C8051F820/1/2/3) or 256 bytes (C8051F824/5/6/7/8/9 and C8051F830/1/2/3/4/5) of RAM data memory.
For all C8051F80x-83x devices, 256 bytes of this memory is mapped into the internal RAM space of the
8051. For the devices with 512 bytes of RAM, the remaining 256 bytes of this memory is on-chip “external”
memory. The data memory map is shown in Figure 15.1 for reference.
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15.2.1. Internal RAM
There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The
lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either
direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00
through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight
byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or
as 128 bit locations accessible with the direct addressing mode.
The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the
same address space as the Special Function Registers (SFR) but is physically separate from the SFR
space. The addressing mode used by an instruction when accessing locations above 0x7F determines
93
Rev. 1.1
C8051F80x-83x
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whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use
direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the
upper 128 bytes of data memory. Figure 15.1 illustrates the data memory organization of the C8051F80x83x.
D
15.2.1.1. General Purpose Registers
The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of general-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only
one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1
(PSW.4), select the active register bank (see description of the PSW in SFR Definition 14.6). This allows
fast context switching when entering subroutines and interrupt service routines. Indirect addressing modes
use registers R0 and R1 as index registers.
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15.2.1.2. Bit Addressable Locations
In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20
through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from
0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address
0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by
the type of instruction used (bit source or destination operands as opposed to a byte source or destination).
MOV
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The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where
XX is the byte address and B is the bit position within the byte. For example, the instruction:
C, 22.3h
moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag.
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15.2.1.3. Stack
A programmer's stack can be located anywhere in the 256-byte data memory. The stack area is designated using the Stack Pointer (SP) SFR. The SP will point to the last location used. The next value pushed
on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to location
0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the first register (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be initialized
to a location in the data memory not being used for data storage. The stack depth can extend up to
256 bytes.
Rev. 1.1
94
C8051F80x-83x
16. In-System Device Identification
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The C8051F80x-83x has SFRs that identify the device family and derivative. These SFRs can be read by
firmware at runtime to determine the capabilities of the MCU that is executing code. This allows the same
firmware image to run on MCUs with different memory sizes and peripherals, and dynamically changing
functionality to suit the capabilities of that MCU.
In order for firmware to identify the MCU, it must read three SFRs. HWID describes the MCU’s family,
DERIVID describes the specific derivative within that device family, and REVID describes the hardware
revision of the MCU.
7
6
5
4
3
2
1
0
R
R
R
R
0
0
1
1
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Bit
D
SFR Definition 16.1. HWID: Hardware Identification Byte
HWID[7:0]
Name
R
R
R
R
Reset
0
0
1
0
Description
Hardware Identification Byte.
Describes the MCU family.
0x23: Devices covered in this document (C8051F80x-83x)
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SFR Address = 0xB5
Bit
Name
HWID[7:0]
7:0
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Type
Rev. 1.1
95
C8051F80x-83x
Bit
7
6
5
4
3
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SFR Definition 16.2. DERIVID: Derivative Identification Byte
2
DERIVID[7:0]
Name
R
R
R
R
R
R
Reset
Varies
Varies
Varies
Varies
Varies
Varies
R
R
Varies
Varies
Description
Derivative Identification Byte.
Shows the C8051F80x-83x derivative being used.
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SFR Address = 0xAD
Bit
Name
7:0 DERIVID[7:0]
0
D
Type
1
0xD0: C8051F800; 0xD1: C8051F801; 0xD2: C8051F802; 0xD3: C8051F803
0xD4: C8051F804; 0xD5: C8051F805; 0xD6: C8051F806; 0xD7: C8051F807
0xD8: C8051F808; 0xD9: C8051F809; 0xDA: C8051F810; 0xDB: C8051F811
fo
r
0xDC: C8051F812; 0xDD: C8051F813; 0xDE: C8051F814; 0xDF: C8051F815
0xE0: C8051F816; 0xE1: C8051F817; 0xE2: C8051F818; 0xE3: C8051F819
m
en
de
d
0xE4: C8051F820; 0xE5: C8051F821; 0xE6: C8051F822; 0xE7: C8051F823
0xE8: C8051F824; 0xE9: C8051F825; 0xEA: C8051F826; 0xEB: C8051F827
0xEC: C8051F828; 0xED: C8051F829; 0xEE: C8051F830; 0xEF: C8051F831
0xF0: C8051F832; 0xF1: C8051F833; 0xF2: C8051F834; 0xF3: C8051F835
SFR Definition 16.3. REVID: Hardware Revision Identification Byte
Name
R
ec
Type
7
6
om
Bit
Varies
Reset
5
4
R
N
ot
96
REVID[7:0]
2
1
0
REVID[7:0]
R
R
R
R
R
R
R
Varies
Varies
Varies
Varies
Varies
Varies
Varies
SFR Address = 0xB6
Bit
Name
7:0
3
Description
Hardware Revision Identification Byte.
Shows the C8051F80x-83x hardware revision being used.
For example, 0x00 = Revision A.
Rev. 1.1
C8051F80x-83x
17. Special Function Registers
es
ig
ns
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the C8051F80x-83x's resources and peripherals. The CIP-51 controller core duplicates the SFRs found in a typical 8051 implementation as well as
implementing additional SFRs used to configure and access the sub-systems unique to the C8051F80x83x. This allows the addition of new functionality while retaining compatibility with the MCS-51™ instruction set. Table 17.1 lists the SFRs implemented in the C8051F80x-83x device family.
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The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g., P0, TCON, SCON0, IE, etc.) are bitaddressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the corresponding pages of the data sheet, as indicated in
Table 17.2, for a detailed description of each register.
Table 17.1. Special Function Register (SFR) Memory Map
fo
r
PCA0L
PCA0H PCA0CPL0 PCA0CPH0 P0MAT
P0MASK
VDM0CN
P0MDIN
P1MDIN
EIP1
EIP2
PCA0PWM
PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 P1MAT
P1MASK
RSTSRC
XBR0
XBR1
IT01CF
EIE1
EIE2
PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 CRC0IN CRC0DATA
REF0CN CRC0AUTO CRC0CNT
P0SKIP
P1SKIP
SMB0ADM SMB0ADR
REG0CN TMR2RLL TMR2RLH
TMR2L
TMR2H
CRC0CN CRC0FLIP
SMB0CF SMB0DAT ADC0GTL ADC0GTH ADC0LTL ADC0LTH
CS0SS
CS0SE
ADC0MX
ADC0CF
ADC0L
ADC0H
OSCXCN
OSCICN
OSCICL
HWID
REVID
FLKEY
CLKSEL
CS0DL
CS0DH
DERVID
SPI0CFG SPI0CKR
SPI0DAT P0MDOUT P1MDOUT P2MDOUT
SBUF0
CPT0CN
CS0MX
CPT0MD
CS0CF
CPT0MX
CS0THL
CS0THH
TMOD
TL0
TL1
TH0
TH1
CKCON
PSCTL
SP
DPL
DPH
PCON
1(9)
2(A)
3(B)
4(C)
5(D)
6(E)
7(F)
m
en
de
d
SPI0CN
B
ADC0CN
ACC
PCA0CN
PSW
TMR2CN
SMB0CN
IP
CS0CN
IE
P2
SCON0
P1
TCON
P0
0(8)
om
F8
F0
E8
E0
D8
D0
C8
C0
B8
B0
A8
A0
98
90
88
80
N
ot
R
ec
Note: SFR Addresses ending in 0x0 or 0x8 are bit-addressable locations, and can be used with bitwise instructions.
Rev. 1.1
97
C8051F80x-83x
Table 17.2. Special Function Registers
Register
Address
0xE0
Accumulator
ADC0CF
0xBC
ADC0 Configuration
ADC0CN
0xE8
ADC0 Control
ADC0GTH
0xC4
ADC0 Greater-Than Compare High
ADC0GTL
0xC3
ADC0 Greater-Than Compare Low
ADC0H
0xBE
ADC0 High
ADC0L
0xBD
ADC0 Low
ADC0LTH
0xC6
ADC0 Less-Than Compare Word High
54
ADC0LTL
0xC5
ADC0 Less-Than Compare Word Low
54
ADC0MX
0xBB
AMUX0 Multiplexer Channel Select
57
B
0xF0
B Register
90
CKCON
0x8E
Clock Control
210
0xA9
Clock Select
210
0x9B
Comparator0 Control
67
0x9D
Comparator0 Mode Selection
68
0x9F
Comparator0 MUX Selection
70
0xD2
CRC0 Automatic Control Register
165
CRC0CN
0xCE
CRC0 Control
163
CRC0CNT
0xD3
CRC0 Automatic Flash Sector Count
165
CRC0DATA
0xDE
CRC0 Data Output
164
CRC0FLIP
0xCF
CRC0 Bit Flip
166
CRC0IN
0xDD
CRC Data Input
164
CS0THH
0x97
CS0 Digital Compare Threshold High
79
CS0THL
0x96
CS0 Digital Compare Threshold High
79
CS0CN
0xB0
CS0 Control
75
CS0DH
0xAC
CS0 Data High
77
CS0DL
0xAB
CS0 Data Low
77
CPT0MD
CPT0MX
R
ec
om
CRC0AUTO
89
50
52
D
53
N
ew
fo
r
m
en
de
d
CPT0CN
N
ot
Page
ACC
CLKSEL
98
Description
es
ig
ns
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Rev. 1.1
53
51
51
C8051F80x-83x
Table 17.2. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Address
Description
Page
es
ig
ns
Register
CS0CF
0x9E
CS0 Configuration
76
CS0MX
0x9C
CS0 Mux
CS0SE
0xBA
Auto Scan End Channel
CS0SS
0xB9
Auto Scan Start Channel
DERIVID
0xAD
Derivative Identification
DPH
0x83
Data Pointer High
DPL
0x82
Data Pointer Low
EIE1
0xE6
Extended Interrupt Enable 1
107
EIE2
0xE7
Extended Interrupt Enable 2
108
EIP1
0xF3
Extended Interrupt Priority 1
109
EIP2
0xF4
Extended Interrupt Priority 2
110
FLKEY
0xB7
Flash Lock And Key
119
81
78
D
78
96
88
0xB5
Hardware Identification
95
0xA8
Interrupt Enable
105
0xB8
Interrupt Priority
106
0xE4
INT0/INT1 Configuration
112
0xB3
Internal Oscillator Calibration
131
0xB2
Internal Oscillator Control
132
OSCXCN
0xB1
External Oscillator Control
134
P0
0x80
Port 0 Latch
153
ec
m
en
de
d
fo
r
N
ew
88
P0MASK
0xFE
Port 0 Mask
151
P0MAT
0xFD
Port 0 Match
151
P0MDIN
0xF1
Port 0 Input Mode Configuration
154
P0MDOUT
0xA4
Port 0 Output Mode Configuration
154
P0SKIP
0xD4
Port 0 Skip
155
P1
0x90
Port 1 Latch
155
P1MASK
0xEE
P0 Mask
152
HWID
IE
IP
IT01CF
OSCICL
N
ot
R
om
OSCICN
Rev. 1.1
99
C8051F80x-83x
Table 17.2. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Address
0xED
P1 Match
P1MDIN
0xF2
Port 1 Input Mode Configuration
P1MDOUT
0xA5
Port 1 Output Mode Configuration
P1SKIP
0xD5
Port 1 Skip
P2
0xA0
Port 2 Latch
P2MDOUT
0xA6
Port 2 Output Mode Configuration
PCA0CN
0xD8
PCA Control
PCA0CPH0
0xFC
PCA Capture 0 High
PCA0CPH1
0xEA
PCA Capture 1 High
PCA0CPH2
0xEC
PCA Capture 2 High
243
PCA0CPL0
0xFB
PCA Capture 0 Low
243
PCA0CPL1
0xE9
PCA Capture 1 Low
243
152
156
156
D
157
m
en
de
d
fo
r
N
ew
157
158
238
243
243
0xEB
PCA Capture 2 Low
243
0xDA
PCA Module 0 Mode Register
241
0xDB
PCA Module 1 Mode Register
241
0xDC
PCA Module 2 Mode Register
241
0xFA
PCA Counter High
242
0xF9
PCA Counter Low
242
PCA0MD
0xD9
PCA Mode
239
PCA0PWM
0xF7
PCA PWM Configuration
240
PCON
0x87
Power Control
122
PSCTL
0x8F
Program Store R/W Control
118
PSW
0xD0
Program Status Word
91
REF0CN
0xD1
Voltage Reference Control
62
REG0CN
0xC9
Voltage Regulator Control
64
REVID
0xB6
Revision ID
96
RSTSRC
0xEF
Reset Source Configuration/Status
128
PCA0CPM0
PCA0CPM1
PCA0CPM2
PCA0H
R
ec
om
PCA0L
N
ot
Page
P1MAT
PCA0CPL2
100
Description
es
ig
ns
Register
Rev. 1.1
C8051F80x-83x
Table 17.2. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Address
Page
SBUF0
0x99
UART0 Data Buffer
SCON0
0x98
UART0 Control
SMB0ADM
0xD6
SMBus Slave Address mask
SMB0ADR
0xD7
SMBus Slave Address
SMB0CF
0xC1
SMBus Configuration
SMB0CN
0xC0
SMBus Control
SMB0DAT
0xC2
SMBus Data
SP
0x81
Stack Pointer
SPI0CFG
0xA1
SPI0 Configuration
SPI0CKR
0xA2
SPI0 Clock Rate Control
176
SPI0CN
0xF8
SPI0 Control
175
SPI0DAT
0xA3
SPI0 Data
176
207
206
191
D
191
186
m
en
de
d
fo
r
N
ew
188
192
89
174
0x88
Timer/Counter Control
215
0x8C
Timer/Counter 0 High
218
0x8D
Timer/Counter 1 High
218
0x8A
Timer/Counter 0 Low
217
0x8B
Timer/Counter 1 Low
217
0x89
Timer/Counter Mode
216
TMR2CN
0xC8
Timer/Counter 2 Control
222
TMR2H
0xCD
Timer/Counter 2 High
224
TMR2L
0xCC
Timer/Counter 2 Low
224
TMR2RLH
0xCB
Timer/Counter 2 Reload High
223
TMR2RLL
0xCA
Timer/Counter 2 Reload Low
223
VDM0CN
0xFF
VDD Monitor Control
126
XBR0
0xE1
Port I/O Crossbar Control 0
148
XBR1
0xE2
Port I/O Crossbar Control 1
149
TCON
TH0
TH1
TL0
TL1
R
ec
om
TMOD
N
ot
Description
es
ig
ns
Register
All other SFR Locations
Reserved
Rev. 1.1
101
C8051F80x-83x
18. Interrupts
es
ig
ns
The C8051F80x-83x includes an extended interrupt system supporting a total of 15 interrupt sources with
two priority levels. The allocation of interrupt sources between on-chip peripherals and external input pins
varies according to the specific version of the device. Each interrupt source has one or more associated
interrupt-pending flag(s) located in an SFR. When a peripheral or external source meets a valid interrupt
condition, the associated interrupt-pending flag is set to logic 1.
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ew
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If interrupts are enabled for the source, an interrupt request is generated when the interrupt-pending flag is
set. As soon as execution of the current instruction is complete, the CPU generates an LCALL to a predetermined address to begin execution of an interrupt service routine (ISR). Each ISR must end with an RETI
instruction, which returns program execution to the next instruction that would have been executed if the
interrupt request had not occurred. If interrupts are not enabled, the interrupt-pending flag is ignored by the
hardware and program execution continues as normal. (The interrupt-pending flag is set to logic 1 regardless of the interrupt's enable/disable state.)
Each interrupt source can be individually enabled or disabled through the use of an associated interrupt
enable bit in an SFR (IE–EIE1). However, interrupts must first be globally enabled by setting the EA bit
(IE.7) to logic 1 before the individual interrupt enables are recognized. Setting the EA bit to logic 0 disables
all interrupt sources regardless of the individual interrupt-enable settings.
N
ot
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ec
om
m
en
de
d
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r
Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR.
However, most are not cleared by the hardware and must be cleared by software before returning from the
ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI)
instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after
the completion of the next instruction.
Rev. 1.1
102
C8051F80x-83x
18.1. MCU Interrupt Sources and Vectors
es
ig
ns
The C8051F80x-83x MCUs support 15 interrupt sources. Software can simulate an interrupt by setting an
interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated
and the CPU will vector to the ISR address associated with the interrupt-pending flag. MCU interrupt
sources, associated vector addresses, priority order and control bits are summarized in Table 18.1. Refer
to the datasheet section associated with a particular on-chip peripheral for information regarding valid
interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).
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18.1.1. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP or EIP1) used to configure
its priority level. Low priority is the default. If two interrupts are recognized simultaneously, the interrupt with
the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is
used to arbitrate, given in Table 18.1.
N
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en
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r
18.1.2. Interrupt Latency
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5
system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the
ISR. If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL
is made to service the pending interrupt. Therefore, the maximum response time for an interrupt (when no
other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is
performing an RETI instruction followed by a DIV as the next instruction. In this case, the response time is
18 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the RETI, 8 clock
cycles to complete the DIV instruction and 4 clock cycles to execute the LCALL to the ISR. If the CPU is
executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the
current ISR completes, including the RETI and following instruction.
103
Rev. 1.1
C8051F80x-83x
Reset
0x0000
Top
None
External Interrupt 0
(INT0)
Timer 0 Overflow
External Interrupt 1
(INT1)
Timer 1 Overflow
UART0
0x0003
0
IE0 (TCON.1)
N/A N/A Always
Always
Enabled
Highest
Y
Y
EX0 (IE.0) PX0 (IP.0)
0x000B
0x0013
1
2
TF0 (TCON.5)
IE1 (TCON.3)
Y
Y
Y
Y
ET0 (IE.1) PT0 (IP.1)
EX1 (IE.2) PX1 (IP.2)
0x001B
0x0023
3
4
Y
Y
Y
N
ET1 (IE.3) PT1 (IP.3)
ES0 (IE.4) PS0 (IP.4)
Timer 2 Overflow
0x002B
5
Y
N
ET2 (IE.5) PT2 (IP.5)
SPI0
0x0033
6
TF1 (TCON.7)
RI0 (SCON0.0)
TI0 (SCON0.1)
TF2H (TMR2CN.7)
TF2L (TMR2CN.6)
SPIF (SPI0CN.7)
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
RXOVRN (SPI0CN.4)
SI (SMB0CN.0)
Y
N
ESMB0
(EIE1.0)
None
N/A N/A EMAT
(EIE1.1)
AD0WINT (ADC0CN.3) Y
N
EWADC0
(EIE1.2)
AD0INT (ADC0CN.5)
Y
N
EADC0
(EIE1.3)
CF (PCA0CN.7)
Y
N
EPCA0
(EIE1.4)
CCFn (PCA0CN.n)
CP0FIF (CPT0CN.4)
N
N
ECP0
(EIE1.5)
CP0RIF (CPT0CN.5)
PSMB0
(EIP1.0)
PMAT
(EIP1.1)
PWADC0
(EIP1.2)
PADC0
(EIP1.3)
PPCA0
(EIP1.4)
PCP0
(EIP1.5)
PSCCPT
(EIP2.0)
PSCGRT
(EIP2.1)
Port Match
ec
RESERVED
RESERVED
CS0 Conversion Complete
CS0 Greater Than
Priority
Control
D
N
ew
Y
ESPI0
(IE.6)
0x003B
7
0x0043
8
0x004B
9
0x0053
10
0x005B
11
0x0063
12
0x007B
15
CS0INT (CS0CN.5)
N
N
0x0083
16
CS0CMPF (CS0CN.0)
N
N
om
ADC0
Window Compare
ADC0
Conversion Complete
Programmable
Counter Array
Comparator0
N
ot
R
fo
r
m
en
de
d
SMB0
Enable
Flag
es
ig
ns
Interrupt Priority Pending Flag
Vector
Order
Cleared by HW?
Interrupt Source
Bit addressable?
Table 18.1. Interrupt Summary
ECSCPT
(EIE2.0)
ECSGRT
(EIE2.1)
PSPI0
(IP.6)
18.2. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described in this section.
Refer to the data sheet section associated with a particular on-chip peripheral for information regarding
valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).
Rev. 1.1
104
C8051F80x-83x
7
6
5
4
3
2
Name
EA
ESPI0
ET2
ES0
ET1
EX1
Type
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
SFR Address = 0xA8; Bit-Addressable
Bit
Name
Function
EA
6
ESPI0
5
ET2
Enable Timer 2 Interrupt.
This bit sets the masking of the Timer 2 interrupt.
0: Disable Timer 2 interrupt.
1: Enable interrupt requests generated by the TF2L or TF2H flags.
4
ES0
Enable UART0 Interrupt.
This bit sets the masking of the UART0 interrupt.
0: Disable UART0 interrupt.
1: Enable UART0 interrupt.
3
ET1
Enable Timer 1 Interrupt.
This bit sets the masking of the Timer 1 interrupt.
0: Disable all Timer 1 interrupt.
1: Enable interrupt requests generated by the TF1 flag.
2
EX1
Enable External Interrupt 1.
This bit sets the masking of External Interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the INT1 input.
N
ot
0
105
m
en
de
d
fo
r
Enable Serial Peripheral Interface (SPI0) Interrupt.
This bit sets the masking of the SPI0 interrupts.
0: Disable all SPI0 interrupts.
1: Enable interrupt requests generated by SPI0.
om
EX0
ET0
EX0
R/W
R/W
0
0
Enable All Interrupts.
Globally enables/disables all interrupts. It overrides individual interrupt mask settings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
ec
R
ET0
0
N
ew
7
1
1
D
Bit
es
ig
ns
SFR Definition 18.1. IE: Interrupt Enable
Enable Timer 0 Interrupt.
This bit sets the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupt.
1: Enable interrupt requests generated by the TF0 flag.
Enable External Interrupt 0.
This bit sets the masking of External Interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the INT0 input.
Rev. 1.1
C8051F80x-83x
7
Name
6
5
4
3
2
PSPI0
PT2
PS0
PT1
PX1
Type
R
R/W
R/W
R/W
R/W
R/W
Reset
1
0
0
0
0
0
SFR Address = 0xB8; Bit-Addressable
Bit
Name
Function
Unused
6
PSPI0
5
PT2
Timer 2 Interrupt Priority Control.
This bit sets the priority of the Timer 2 interrupt.
0: Timer 2 interrupt set to low priority level.
1: Timer 2 interrupt set to high priority level.
4
PS0
UART0 Interrupt Priority Control.
This bit sets the priority of the UART0 interrupt.
0: UART0 interrupt set to low priority level.
1: UART0 interrupt set to high priority level.
3
PT1
Timer 1 Interrupt Priority Control.
This bit sets the priority of the Timer 1 interrupt.
0: Timer 1 interrupt set to low priority level.
1: Timer 1 interrupt set to high priority level.
2
PX1
External Interrupt 1 Priority Control.
This bit sets the priority of the External Interrupt 1 interrupt.
0: External Interrupt 1 set to low priority level.
1: External Interrupt 1 set to high priority level.
PT0
PX0
R/W
R/W
0
0
om
m
en
de
d
fo
r
Serial Peripheral Interface (SPI0) Interrupt Priority Control.
This bit sets the priority of the SPI0 interrupt.
0: SPI0 interrupt set to low priority level.
1: SPI0 interrupt set to high priority level.
PT0
Timer 0 Interrupt Priority Control.
This bit sets the priority of the Timer 0 interrupt.
0: Timer 0 interrupt set to low priority level.
1: Timer 0 interrupt set to high priority level.
ec
1
Read = 1b, Write = Don't Care.
0
N
ew
7
1
D
Bit
es
ig
ns
SFR Definition 18.2. IP: Interrupt Priority
PX0
External Interrupt 0 Priority Control.
This bit sets the priority of the External Interrupt 0 interrupt.
0: External Interrupt 0 set to low priority level.
1: External Interrupt 0 set to high priority level.
N
ot
R
0
Rev. 1.1
106
C8051F80x-83x
7
Name Reserved
6
5
4
3
2
Reserved
ECP0
EADC0
EPCA0
EWADC0
Type
W
W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
SFR Address = 0xE6
Bit
Name
Reserved Must write 0.
6
Reserved Reserved.
Must write 0.
0
EMAT
ESMB0
R/W
R/W
0
0
N
ew
7
Function
1
D
Bit
es
ig
ns
SFR Definition 18.3. EIE1: Extended Interrupt Enable 1
ECP0
4
EADC0
Enable ADC0 Conversion Complete Interrupt.
This bit sets the masking of the ADC0 Conversion Complete interrupt.
0: Disable ADC0 Conversion Complete interrupt.
1: Enable interrupt requests generated by the AD0INT flag.
3
EPCA0
Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts.
1: Enable interrupt requests generated by PCA0.
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2
Enable Comparator0 (CP0) Interrupt.
This bit sets the masking of the CP0 rising edge or falling edge interrupt.
0: Disable CP0 interrupts.
1: Enable interrupt requests generated by the CP0RIF and CP0FIF flags.
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EWADC0 Enable Window Comparison ADC0 interrupt.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison interrupt.
1: Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT).
EMAT
0
ESMB0
Enable Port Match Interrupts.
This bit sets the masking of the Port Match event interrupt.
0: Disable all Port Match interrupts.
1: Enable interrupt requests generated by a Port Match.
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Enable SMBus (SMB0) Interrupt.
This bit sets the masking of the SMB0 interrupt.
0: Disable all SMB0 interrupts.
1: Enable interrupt requests generated by SMB0.
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Bit
7
6
5
4
3
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SFR Definition 18.4. EIE2: Extended Interrupt Enable 2
2
Type
R
R
R
R
R
R
Reset
0
0
0
0
0
0
SFR Address = 0xE7
Bit
Name
Unused
Read = 000000b; Write = don’t care.
ECSGRT
ECSCPT
R/W
R/W
0
0
N
ew
7:2
Function
0
D
Name
1
ECSGRT Enable Capacitive Sense Greater Than Comparator Interrupt.
0: Disable Capacitive Sense Greater Than Comparator interrupt.
1: Enable interrupt requests generated by CS0CMPF.
0
ECSCPT Enable Capacitive Sense Conversion Complete Interrupt.
0: Disable Capacitive Sense Conversion Complete interrupt.
1: Enable interrupt requests generated by CS0INT.
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7
Name Reserved
6
5
4
3
2
Reserved
PCP0
PPCA0
PADC0
PWADC0
Type
W
W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
SFR Address = 0xF3
Bit
Name
Reserved Must write 0.
0
PMAT
PSMB0
R/W
R/W
0
0
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7:6
Function
1
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Bit
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SFR Definition 18.5. EIP1: Extended Interrupt Priority 1
PCP0
4
PPCA0
Programmable Counter Array (PCA0) Interrupt Priority Control.
This bit sets the priority of the PCA0 interrupt.
0: PCA0 interrupt set to low priority level.
1: PCA0 interrupt set to high priority level.
3
PADC0
ADC0 Conversion Complete Interrupt Priority Control.
This bit sets the priority of the ADC0 Conversion Complete interrupt.
0: ADC0 Conversion Complete interrupt set to low priority level.
1: ADC0 Conversion Complete interrupt set to high priority level.
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2
Comparator0 (CP0) Interrupt Priority Control.
This bit sets the priority of the CP0 rising edge or falling edge interrupt.
0: CP0 interrupt set to low priority level.
1: CP0 interrupt set to high priority level.
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PWADC0 ADC0 Window Comparator Interrupt Priority Control.
This bit sets the priority of the ADC0 Window interrupt.
0: ADC0 Window interrupt set to low priority level.
1: ADC0 Window interrupt set to high priority level.
PMAT
0
PSMB0
Port Match Interrupt Priority Control.
This bit sets the priority of the Port Match Event interrupt.
0: Port Match interrupt set to low priority level.
1: Port Match interrupt set to high priority level.
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SMBus (SMB0) Interrupt Priority Control.
This bit sets the priority of the SMB0 interrupt.
0: SMB0 interrupt set to low priority level.
1: SMB0 interrupt set to high priority level.
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7
Name Reserved
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
PSCGRT
PSCCPT
R/W
R/W
0
0
Type
R
R
R
R
R
R
Reset
0
0
0
0
0
0
SFR Address = 0xF4
Bit
Name
Reserved
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7:2
Function
D
Bit
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SFR Definition 18.6. EIP2: Extended Interrupt Priority 2
PSCGRT Capacitive Sense Greater Than Comparator Priority Control.
This bit sets the priority of the Capacitive Sense Greater Than Comparator interrupt.
0: CS0 Greater Than Comparator interrupt set to low priority level.
1: CS0 Greater Than Comparator set to high priority level.
0
PSCCPT Capacitive Sense Conversion Complete Priority Control.
This bit sets the priority of the Capacitive Sense Conversion Complete interrupt.
0: CS0 Conversion Complete set to low priority level.
1: CS0 Conversion Complete set to high priority level.
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18.3. INT0 and INT1 External Interrupts
IN0PL
1
1
0
0
0
1
0
1
INT0 Interrupt
Active low, edge sensitive
Active high, edge sensitive
Active low, level sensitive
Active high, level sensitive
IT1
1
1
0
0
IN1PL
0
1
0
1
INT1 Interrupt
Active low, edge sensitive
Active high, edge sensitive
Active low, level sensitive
Active high, level sensitive
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IT0
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The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level sensitive. The IN0PL (INT0 Polarity) and IN1PL (INT1 Polarity) bits in the IT01CF register select active high or
active low; the IT0 and IT1 bits in TCON (Section “28.1. Timer 0 and Timer 1” on page 211) select level or
edge sensitive. The table below lists the possible configurations.
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INT0 and INT1 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 18.7). Note
that INT0 and INT0 Port pin assignments are independent of any Crossbar assignments. INT0 and INT1
will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin via the
Crossbar. To assign a Port pin only to INT0 and/or INT1, configure the Crossbar to skip the selected pin(s).
This is accomplished by setting the associated bit in register XBR0 (see Section “23.3. Priority Crossbar
Decoder” on page 143 for complete details on configuring the Crossbar).
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IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the INT0 and INT1 external interrupts, respectively. If an INT0 or INT1 external interrupt is configured as edge-sensitive, the corresponding
interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When
configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined
by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inactive. The
external interrupt source must hold the input active until the interrupt request is recognized. It must then
deactivate the interrupt request before execution of the ISR completes or another interrupt request will be
generated.
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Bit
7
Name
IN1PL
IN1SL[2:0]
IN0PL
IN0SL[2:0]
Type
R/W
R/W
R/W
R/W
Reset
0
0
5
0
4
3
0
0
SFR Address = 0xE4
Name
7
IN1PL
INT1 Polarity.
0: INT1 input is active low.
1: INT1 input is active high.
0
0
1
IN1SL[2:0] INT1 Port Pin Selection Bits.
These bits select which Port pin is assigned to INT1. Note that this pin assignment is
independent of the Crossbar; INT1 will monitor the assigned Port pin without disturbing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar
will not assign the Port pin to a peripheral if it is configured to skip the selected pin.
000: Select P0.0
001: Select P0.1
010: Select P0.2
011: Select P0.3
100: Select P0.4
101: Select P0.5
110: Select P0.6
111: Select P0.7
INT0 Polarity.
0: INT0 input is active low.
1: INT0 input is active high.
IN0SL[2:0] INT0 Port Pin Selection Bits.
These bits select which Port pin is assigned to INT0. Note that this pin assignment is
independent of the Crossbar; INT0 will monitor the assigned Port pin without disturbing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar
will not assign the Port pin to a peripheral if it is configured to skip the selected pin.
000: Select P0.0
001: Select P0.1
010: Select P0.2
011: Select P0.3
100: Select P0.4
101: Select P0.5
110: Select P0.6
111: Select P0.7
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2:0
IN0PL
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6:4
Function
0
1
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Bit
2
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SFR Definition 18.7. IT01CF: INT0/INT1 Configuration
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19. Flash Memory
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On-chip, re-programmable Flash memory is included for program code and non-volatile data storage. The
Flash memory can be programmed in-system through the C2 interface or by software using the MOVX
write instruction. Once cleared to logic 0, a Flash bit must be erased to set it back to logic 1. Flash bytes
would typically be erased (set to 0xFF) before being reprogrammed. The write and erase operations are
automatically timed by hardware for proper execution; data polling to determine the end of the write/erase
operations is not required. Code execution is stalled during Flash write/erase operations. Refer to
Table 7.6 for complete Flash memory electrical characteristics.
19.1. Programming The Flash Memory
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The simplest means of programming the Flash memory is through the C2 interface using programming
tools provided by Silicon Laboratories or a third party vendor. This is the only means for programming a
non-initialized device. For details on the C2 commands to program Flash memory, see Section “30. C2
Interface” on page 244.
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The Flash memory can be programmed by software using the MOVX write instruction with the address and
data byte to be programmed provided as normal operands. Before programming Flash memory using
MOVX, Flash programming operations must be enabled by: (1) setting the PSWE Program Store Write
Enable bit (PSCTL.0) to logic 1 (this directs the MOVX writes to target Flash memory); and (2) Writing the
Flash key codes in sequence to the Flash Lock register (FLKEY). The PSWE bit remains set until cleared
by software. For detailed guidelines on programming Flash from firmware, please see Section “19.4. Flash
Write and Erase Guidelines” on page 115.
Note: A minimum SYSCLK frequency is required for writing or erasing Flash memory, as detailed in “7. Electrical
Characteristics” on page 39.
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To ensure the integrity of the Flash contents, the on-chip VDD Monitor must be enabled and enabled as a
reset source in any system that includes code that writes and/or erases Flash memory from software. Furthermore, there should be no delay between enabling the VDD Monitor and enabling the VDD Monitor as a
reset source. Any attempt to write or erase Flash memory while the VDD Monitor is disabled, or not
enabled as a reset source, will cause a Flash Error device reset.
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19.1.1. Flash Lock and Key Functions
Flash writes and erases by user software are protected with a lock and key function. The Flash Lock and
Key Register (FLKEY) must be written with the correct key codes, in sequence, before Flash operations
may be performed. The key codes are: 0xA5, 0xF1. The timing does not matter, but the codes must be
written in order. If the key codes are written out of order, or the wrong codes are written, Flash writes and
erases will be disabled until the next system reset. Flash writes and erases will also be disabled if a Flash
write or erase is attempted before the key codes have been written properly. The Flash lock resets after
each write or erase; the key codes must be written again before a following Flash operation can be performed. The FLKEY register is detailed in SFR Definition 19.2.
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19.1.2. Flash Erase Procedure
The Flash memory is organized in 512-byte pages. The erase operation applies to an entire page (setting
all bytes in the page to 0xFF). To erase an entire 512-byte page, perform the following steps:
Save current interrupt state and disable interrupts.
Set the PSEE bit (register PSCTL).
Set the PSWE bit (register PSCTL).
Write the first key code to FLKEY: 0xA5.
Write the second key code to FLKEY: 0xF1.
Using the MOVX instruction, write a data byte to any location within the 512-byte page to be erased.
Clear the PSWE and PSEE bits.
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2.
3.
4.
5.
6.
7.
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C8051F80x-83x
8. Restore previous interrupt state.
Steps 4–6 must be repeated for each 512-byte page to be erased.
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Note: Flash security settings may prevent erasure of some Flash pages, such as the reserved area and the page
containing the lock bytes. For a summary of Flash security settings and restrictions affecting Flash erase
operations, please see Section “19.3. Security Options” on page 114.
19.1.3. Flash Write Procedure
A write to Flash memory can clear bits to logic 0 but cannot set them; only an erase operation can set bits
to logic 1 in Flash. A byte location to be programmed should be erased before a new value is written.
The recommended procedure for writing a single byte in Flash is as follows:
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Save current interrupt state and disable interrupts.
Ensure that the Flash byte has been erased (has a value of 0xFF).
Set the PSWE bit (register PSCTL).
Clear the PSEE bit (register PSCTL).
Write the first key code to FLKEY: 0xA5.
Write the second key code to FLKEY: 0xF1.
Using the MOVX instruction, write a single data byte to the desired location within the 512-byte sector.
Clear the PSWE bit.
Restore previous interrupt state.
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2.
3.
4.
5.
6.
7.
8.
9.
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Steps 5–7 must be repeated for each byte to be written.
Note: Flash security settings may prevent writes to some areas of Flash, such as the reserved area. For a summary
of Flash security settings and restrictions affecting Flash write operations, please see Section “19.3. Security
Options” on page 114.
19.2. Non-volatile Data Storage
The Flash memory can be used for non-volatile data storage as well as program code. This allows data
such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX
write instruction and read using the MOVC instruction.
Note: MOVX read instructions always target XRAM.
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19.3. Security Options
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The CIP-51 provides security options to protect the Flash memory from inadvertent modification by software as well as to prevent the viewing of proprietary program code and constants. The Program Store
Write Enable (bit PSWE in register PSCTL) and the Program Store Erase Enable (bit PSEE in register
PSCTL) bits protect the Flash memory from accidental modification by software. PSWE must be explicitly
set to 1 before software can modify the Flash memory; both PSWE and PSEE must be set to 1 before software can erase Flash memory. Additional security features prevent proprietary program code and data
constants from being read or altered across the C2 interface.
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A Security Lock Byte located at the last byte of Flash user space offers protection of the Flash program
memory from access (reads, writes, and erases) by unprotected code or the C2 interface. The Flash security mechanism allows the user to lock all Flash pages, starting at page 0, by writing a non-0xFF value to
the lock byte. Note that writing a non-0xFF value to the lock byte will lock all pages of FLASH from
reads, writes, and erases, including the page containing the lock byte.
The level of Flash security depends on the Flash access method. The three Flash access methods that
can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on
unlocked pages, and user firmware executing on locked pages. Table 19.1 summarizes the Flash security
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features of the C8051F80x-83x devices.
Permitted
User Firmware executing from:
an unlocked page a locked page
Permitted
Not Permitted FEDR
Permitted
Permitted
Permitted
Permitted
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Not Permitted FEDR
Permitted
Permitted
Permitted
Permitted
Permitted
Permitted
Permitted
FEDR
FEDR
Only by C2DE FEDR
FEDR
Not Permitted FEDR
FEDR
Not Permitted FEDR
FEDR
Not Permitted FEDR
FEDR
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Not Permitted FEDR
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Read, Write or Erase unlocked pages
(except page with Lock Byte)
Read, Write or Erase locked pages
(except page with Lock Byte)
Read or Write page containing Lock Byte
(if no pages are locked)
Read or Write page containing Lock Byte
(if any page is locked)
Read contents of Lock Byte
(if no pages are locked)
Read contents of Lock Byte
(if any page is locked)
Erase page containing Lock Byte
(if no pages are locked)
Erase page containing Lock Byte—Unlock all
pages (if any page is locked)
Lock additional pages
(change 1s to 0s in the Lock Byte)
Unlock individual pages
(change 0s to 1s in the Lock Byte)
Read, Write or Erase Reserved Area
C2 Debug
Interface
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Table 19.1. Flash Security Summary
C2DE—C2 Device Erase (Erases all Flash pages including the page containing the Lock Byte)
FEDR—Not permitted; Causes Flash Error Device Reset (FERROR bit in RSTSRC is 1 after reset)
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All prohibited operations that are performed via the C2 interface are ignored (do not cause device
reset).
Locking any Flash page also locks the page containing the Lock Byte.
Once written to, the Lock Byte cannot be modified except by performing a C2 Device Erase.
If user code writes to the Lock Byte, the Lock does not take effect until the next device reset.
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19.4. Flash Write and Erase Guidelines
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Any system which contains routines which write or erase Flash memory from software involves some risk
that the write or erase routines will execute unintentionally if the CPU is operating outside its specified
operating range of VDD, system clock frequency, or temperature. This accidental execution of Flash modifying code can result in alteration of Flash memory contents causing a system failure that is only recoverable by re-Flashing the code in the device.
To help prevent the accidental modification of Flash by firmware, the VDD Monitor must be enabled and
enabled as a reset source on C8051F80x-83x devices for the Flash to be successfully modified. If either
the VDD Monitor or the VDD Monitor reset source is not enabled, a Flash Error Device Reset will be
generated when the firmware attempts to modify the Flash.
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The following guidelines are recommended for any system that contains routines which write or erase
Flash from code.
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19.4.1. VDD Maintenance and the VDD Monitor
1. If the system power supply is subject to voltage or current "spikes," add sufficient transient protection
devices to the power supply to ensure that the supply voltages listed in the Absolute Maximum Ratings
table are not exceeded.
2. Make certain that the minimum VDD rise time specification of 1 ms is met. If the system cannot meet
this rise time specification, then add an external VDD brownout circuit to the RST pin of the device that
holds the device in reset until VDD reaches the minimum device operating voltage and re-asserts RST
if VDD drops below the minimum device operating voltage.
3. Keep the on-chip VDD Monitor enabled and enable the VDD Monitor as a reset source as early in code
as possible. This should be the first set of instructions executed after the Reset Vector. For C-based
systems, this will involve modifying the startup code added by the C compiler. See your compiler
documentation for more details. Make certain that there are no delays in software between enabling the
VDD Monitor and enabling the VDD Monitor as a reset source. Code examples showing this can be
found in “AN201: Writing to Flash from Firmware," available from the Silicon Laboratories website.
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Note: On C8051F80x-83x devices, both the VDD Monitor and the VDD Monitor reset source must be enabled to write
or erase Flash without generating a Flash Error Device Reset.
On C8051F80x-83x devices, both the VDD Monitor and the VDD Monitor reset source are enabled by hardware
after a power-on reset.
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4. As an added precaution, explicitly enable the VDD Monitor and enable the VDD Monitor as a reset
source inside the functions that write and erase Flash memory. The VDD Monitor enable instructions
should be placed just after the instruction to set PSWE to a 1, but before the Flash write or erase
operation instruction.
5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment operators
and explicitly DO NOT use the bit-wise operators (such as AND or OR). For example, "RSTSRC =
0x02" is correct, but "RSTSRC |= 0x02" is incorrect.
6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a 1. Areas to check
are initialization code which enables other reset sources, such as the Missing Clock Detector or
Comparator, for example, and instructions which force a Software Reset. A global search on "RSTSRC"
can quickly verify this.
19.4.2. PSWE Maintenance
1. Reduce the number of places in code where the PSWE bit (b0 in PSCTL) is set to a 1. There should be
exactly one routine in code that sets PSWE to a 1 to write Flash bytes and one routine in code that sets
both PSWE and PSEE both to a 1 to erase Flash pages.
2. Minimize the number of variable accesses while PSWE is set to a 1. Handle pointer address updates
and loop maintenance outside the "PSWE = 1;... PSWE = 0;" area. Code examples showing this can be
found in “AN201: Writing to Flash from Firmware," available from the Silicon Laboratories website.
3. Disable interrupts prior to setting PSWE to a 1 and leave them disabled until after PSWE has been
reset to 0. Any interrupts posted during the Flash write or erase operation will be serviced in priority
order after the Flash operation has been completed and interrupts have been re-enabled by software.
4. Make certain that the Flash write and erase pointer variables are not located in XRAM. See your
compiler documentation for instructions regarding how to explicitly locate variables in different memory
areas.
5. Add address bounds checking to the routines that write or erase Flash memory to ensure that a routine
called with an illegal address does not result in modification of the Flash.
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19.4.3. System Clock
1. If operating from an external crystal, be advised that crystal performance is susceptible to electrical
interference and is sensitive to layout and to changes in temperature. If the system is operating in an
electrically noisy environment, use the internal oscillator or use an external CMOS clock.
2. If operating from the external oscillator, switch to the internal oscillator during Flash write or erase
operations. The external oscillator can continue to run, and the CPU can switch back to the external
oscillator after the Flash operation has completed.
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Additional Flash recommendations and example code can be found in “AN201: Writing to Flash from Firmware," available from the Silicon Laboratories website.
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7
6
5
4
3
2
Name
Type
R
R
R
R
R
R
Reset
0
0
0
0
0
0
SFR Address =0x8F
Bit
Name
Function
0
PSEE
PSWE
R/W
R/W
0
0
7:2
Unused
1
PSEE
Program Store Erase Enable.
Setting this bit (in combination with PSWE) allows an entire page of Flash program
memory to be erased. If this bit is logic 1 and Flash writes are enabled (PSWE is logic
1), a write to Flash memory using the MOVX instruction will erase the entire page that
contains the location addressed by the MOVX instruction. The value of the data byte
written does not matter.
0: Flash program memory erasure disabled.
1: Flash program memory erasure enabled.
0
PSWE
Program Store Write Enable.
Setting this bit allows writing a byte of data to the Flash program memory using the
MOVX write instruction. The Flash location should be erased before writing data.
0: Writes to Flash program memory disabled.
1: Writes to Flash program memory enabled; the MOVX write instruction targets Flash
memory.
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Read = 000000b, Write = don’t care.
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SFR Definition 19.1. PSCTL: Program Store R/W Control
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Rev. 1.1
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Bit
7
6
5
4
3
Name
FLKEY[7:0]
Type
R/W
0
Reset
0
0
0
0
2
0
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SFR Definition 19.2. FLKEY: Flash Lock and Key
1
0
0
0
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SFR Address = 0xB7
Bit
Name
Function
7:0 FLKEY[7:0] Flash Lock and Key Register.
Write:
This register provides a lock and key function for Flash erasures and writes. Flash
writes and erases are enabled by writing 0xA5 followed by 0xF1 to the FLKEY register. Flash writes and erases are automatically disabled after the next write or erase is
complete. If any writes to FLKEY are performed incorrectly, or if a Flash write or erase
operation is attempted while these operations are disabled, the Flash will be permanently
locked from writes or erasures until the next device reset. If an application never
writes to Flash, it can intentionally lock the Flash by writing a non-0xA5 value to
FLKEY from software.
Read:
When read, bits 1–0 indicate the current Flash lock state.
00: Flash is write/erase locked.
01: The first key code has been written (0xA5).
10: Flash is unlocked (writes/erases allowed).
11: Flash writes/erases disabled until the next reset.
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20. Power Management Modes
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The C8051F80x-83x devices have three software programmable power management modes: Idle, Stop,
and Suspend. Idle mode and Stop mode are part of the standard 8051 architecture, while Suspend mode
is an enhanced power-saving mode implemented by the high-speed oscillator peripheral.
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Idle mode halts the CPU while leaving the peripherals and clocks active. In Stop mode, the CPU is halted,
all interrupts and timers (except the Missing Clock Detector) are inactive, and the internal oscillator is
stopped (analog peripherals remain in their selected states; the external oscillator is not affected). Suspend mode is similar to Stop mode in that the internal oscillator and CPU are halted, but the device can
wake on events such as a Port Mismatch, Comparator low output, or a Timer 3 overflow. Since clocks are
running in Idle mode, power consumption is dependent upon the system clock frequency and the number
of peripherals left in active mode before entering Idle. Stop mode and Suspend mode consume the least
power because the majority of the device is shut down with no clocks active. SFR Definition 20.1 describes
the Power Control Register (PCON) used to control the C8051F80x-83x's Stop and Idle power management modes. Suspend mode is controlled by the SUSPEND bit in the OSCICN register (SFR Definition
22.3).
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Although the C8051F80x-83x has Idle, Stop, and Suspend modes available, more control over the device
power can be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral
can be disabled when not in use and placed in low power mode. Digital peripherals, such as timers or
serial buses, draw little power when they are not in use. Turning off oscillators lowers power consumption
considerably, at the expense of reduced functionality.
20.1. Idle Mode
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Setting the Idle Mode Select bit (PCON.0) causes the hardware to halt the CPU and enter Idle mode as
soon as the instruction that sets the bit completes execution. All internal registers and memory maintain
their original data. All analog and digital peripherals can remain active during Idle mode.
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an
enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume
operation. The pending interrupt will be serviced and the next instruction to be executed after the return
from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit.
If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence
and begins program execution at address 0x0000.
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Note: If the instruction following the write of the IDLE bit is a single-byte instruction and an interrupt occurs during the
execution phase of the instruction that sets the IDLE bit, the CPU may not wake from Idle mode when a future
interrupt occurs. Therefore, instructions that set the IDLE bit should be followed by an instruction that has two
or more opcode bytes, for example:
// in ‘C’:
PCON |= 0x01;
// set IDLE bit
PCON = PCON;
// ... followed by a 3-cycle dummy instruction
R
; in assembly:
ORL PCON, #01h
MOV PCON, PCON
; set IDLE bit
; ... followed by a 3-cycle dummy instruction
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If enabled, the Watchdog Timer (WDT) will eventually cause an internal watchdog reset and thereby terminate the Idle mode. This feature protects the system from an unintended permanent shutdown in the event
of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by
software prior to entering the Idle mode if the WDT was initially configured to allow this operation. This provides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefinitely, waiting for an external stimulus to wake up the system. Refer to Section “29.4. Watchdog Timer
Mode” on page 236 for more information on the use and configuration of the WDT.
Rev. 1.1
120
C8051F80x-83x
20.2. Stop Mode
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Setting the Stop Mode Select bit (PCON.1) causes the controller core to enter Stop mode as soon as the
instruction that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital
peripherals are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral
(including the external oscillator circuit) may be shut down individually prior to entering Stop Mode. Stop
mode can only be terminated by an internal or external reset. On reset, the device performs the normal
reset sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode.
The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the
MCD timeout of 100 μs.
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20.3. Suspend Mode
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Suspend mode allows a system running from the internal oscillator to go to a very low power state similar
to Stop mode, but the processor can be awakened by certain events without requiring a reset of the device.
Setting the SUSPEND bit (OSCICN.5) causes the hardware to halt the CPU and the high-frequency internal oscillator, and go into Suspend mode as soon as the instruction that sets the bit completes execution.
All internal registers and memory maintain their original data. Most digital peripherals are not active in Suspend mode. The exception to this is the Port Match feature and Timer 3, when it is run from an external
oscillator source.
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The clock divider bits CLKDIV[2:0] in register CLKSEL must be set to "divide by 1" when entering suspend
mode.
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Suspend mode can be terminated by five types of events, a port match (described in Section “23.5. Port
Match” on page 150), a Timer 2 overflow (described in Section “28.2. Timer 2” on page 219), a comparator
low output (if enabled), a capacitive sense greater-than comparator event, or a device reset event. In order
to run Timer 3 in suspend mode, the timer must be configured to clock from the external clock source.
When suspend mode is terminated, the device will continue execution on the instruction following the one
that set the SUSPEND bit. If the wake event (port match or Timer 2 overflow) was configured to generate
an interrupt, the interrupt will be serviced upon waking the device. If suspend mode is terminated by an
internal or external reset, the CIP-51 performs a normal reset sequence and begins program execution at
address 0x0000.
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Note: The device will still enter suspend mode if a wake source is "pending", and the device will not wake on such
pending sources. It is important to ensure that the intended wake source will trigger after the device enters
suspend mode. For example, if a CS0 conversion completes and the interrupt fires before the device is in
suspend mode, that interrupt cannot trigger the wake event. Because port match events are level-sensitive,
pre-existing port match events will trigger a wake, as long as the match condition is still present when the
device enters suspend.
121
Rev. 1.1
C8051F80x-83x
7
6
5
4
Name
GF[5:0]
Type
R/W
0
Reset
0
SFR Address = 0x87
Bit
Name
0
3
0
0
Function
2
0
1
0
STOP
IDLE
R/W
R/W
0
0
D
Bit
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SFR Definition 20.1. PCON: Power Control
GF[5:0]
General Purpose Flags 5–0.
These are general purpose flags for use under software control.
1
STOP
Stop Mode Select.
Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0.
1: CPU goes into Stop mode (internal oscillator stopped).
0
IDLE
IDLE: Idle Mode Select.
Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0.
1: CPU goes into Idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts,
Serial Ports, and Analog Peripherals are still active.)
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7:2
Rev. 1.1
122
C8051F80x-83x
21. Reset Sources
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Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External Port pins are forced to a known state
Interrupts and timers are disabled.
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory are unaffected during a reset; any previously stored data is preserved. However, since the
stack pointer SFR is reset, the stack is effectively lost, even though the data on the stack is not altered.
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The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled
during and after the reset. For VDD Monitor and power-on resets, the RST pin is driven low until the device
exits the reset state.
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On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the internal oscillator. The Watchdog Timer is enabled with the system clock divided by 12 as its clock source. Program execution begins at location 0x0000.
Figure 21.1. Reset Sources
Rev. 1.1
123
C8051F80x-83x
21.1. Power-On Reset
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During power-up, the device is held in a reset state and the RST pin is driven low until VDD settles above
VRST. A delay occurs before the device is released from reset; the delay decreases as the VDD ramp time
increases (VDD ramp time is defined as how fast VDD ramps from 0 V to VRST). Figure 21.2. plots the
power-on and VDD monitor reset timing. The maximum VDD ramp time is 1 ms; slower ramp times may
cause the device to be released from reset before VDD reaches the VRST level. For ramp times less than
1 ms, the power-on reset delay (TPORDelay) is typically less than 10 ms.
Figure 21.2. Power-On and VDD Monitor Reset Timing
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On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data memory should be assumed to be undefined after a power-on reset. The VDD monitor is enabled and selected
as a reset source following a power-on reset.
124
Rev. 1.1
C8051F80x-83x
21.2. Power-Fail Reset / VDD Monitor
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When a power-down transition or power irregularity causes VDD to drop below VRST, the power supply
monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 21.2). When VDD returns
to a level above VRST, the CIP-51 will be released from the reset state. Even though internal data memory
contents are not altered by the power-fail reset, it is impossible to determine if VDD dropped below the level
required for data retention. If the PORSF flag reads 1, the data may no longer be valid. The VDD monitor is
enabled and selected as a reset source after power-on resets. Its defined state (enabled/disabled) is not
altered by any other reset source. For example, if the VDD monitor is disabled by code and a software reset
is performed, the VDD monitor will still be disabled after the reset.
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Important Note: If the VDD monitor is being turned on from a disabled state, it should be enabled before it
is selected as a reset source. Selecting the VDD monitor as a reset source before it is enabled and stabilized may cause a system reset. In some applications, this reset may be undesirable. If this is not desirable
in the application, a delay should be introduced between enabling the monitor and selecting it as a reset
source. The procedure for enabling the VDD monitor and configuring it as a reset source from a disabled
state is shown below:
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1. Enable the VDD monitor (VDMEN bit in VDM0CN = 1).
2. If necessary, wait for the VDD monitor to stabilize.
3. Select the VDD monitor as a reset source (PORSF bit in RSTSRC = 1).
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See Figure 21.2 for VDD monitor timing; note that the power-on-reset delay is not incurred after a VDD
monitor reset. See Section “7. Electrical Characteristics” on page 39 for complete electrical characteristics
of the VDD monitor.
Rev. 1.1
125
C8051F80x-83x
7
6
5
4
3
2
Name
VDMEN
VDDSTAT
Type
R/W
R
R
R
R
R
Reset
Varies
Varies
Varies
Varies
Varies
Varies
SFR Address = 0xFF
Bit
Name
VDMEN
VDD Monitor Enable.
0
R
R
Varies
Varies
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7
Function
1
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Bit
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SFR Definition 21.1. VDM0CN: VDD Monitor Control
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This bit turns the VDD monitor circuit on/off. The VDD Monitor cannot generate system resets until it is also selected as a reset source in register RSTSRC (SFR Definition 21.2). Selecting the VDD monitor as a reset source before it has stabilized
may generate a system reset. In systems where this reset would be undesirable, a
delay should be introduced between enabling the VDD Monitor and selecting it as a
reset source. After a power-on reset, the VDD monitor is enabled, and this bit will
read 1. The state of this bit is sticky through any other reset source.
0: VDD Monitor Disabled.
1: VDD Monitor Enabled.
VDDSTAT
VDD Status.
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This bit indicates the current power supply status (VDD Monitor output).
0: VDD is at or below the VDD monitor threshold.
1: VDD is above the VDD monitor threshold.
5:0
Unused
Read = Varies; Write = Don’t care.
21.3. External Reset
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The external RST pin provides a means for external circuitry to force the device into a reset state. Asserting an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Section “7. Electrical Characteristics”
on page 39 for complete RST pin specifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
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21.4. Missing Clock Detector Reset
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The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than the MCD timeout, the one-shot will time out and generate a reset.
After a MCD reset, the MCDRSF flag (RSTSRC.2) will read 1, signifying the MCD as the reset source; otherwise, this bit reads 0. Writing a 1 to the MCDRSF bit enables the Missing Clock Detector; writing a 0 disables it. The state of the RST pin is unaffected by this reset.
126
Rev. 1.1
C8051F80x-83x
21.5. Comparator0 Reset
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Comparator0 can be configured as a reset source by writing a 1 to the C0RSEF flag (RSTSRC.5). Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter
on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-inverting
input voltage (on CP0+) is less than the inverting input voltage (on CP0-), the device is put into the reset
state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read 1 signifying Comparator0 as the
reset source; otherwise, this bit reads 0. The state of the RST pin is unaffected by this reset.
21.6. PCA Watchdog Timer Reset
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The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be
used to prevent software from running out of control during a system malfunction. The PCA WDT function
can be enabled or disabled by software as described in Section “29.4. Watchdog Timer Mode” on
page 236; the WDT is enabled and clocked by SYSCLK / 12 following any reset. If a system malfunction
prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is
set to ‘1’. The state of the RST pin is unaffected by this reset.
21.7. Flash Error Reset
If a Flash read/write/erase or program read targets an illegal address, a system reset is generated. This
may occur due to any of the following:
A Flash write or erase is attempted above user code space. This occurs when PSWE is set to 1 and a
MOVX write operation targets an address above address 0x3DFF.
A Flash read is attempted above user code space. This occurs when a MOVC operation targets an
address above address 0x3DFF.
A Program read is attempted above user code space. This occurs when user code attempts to branch
to an address above 0x3DFF.
A Flash read, write or erase attempt is restricted due to a Flash security setting (see Section
“19.3. Security Options” on page 114).
The FERROR bit (RSTSRC.6) is set following a Flash error reset. The state of the RST pin is unaffected by
this reset.
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21.8. Software Reset
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Software may force a reset by writing a 1 to the SWRSF bit (RSTSRC.4). The SWRSF bit will read 1 following a software forced reset. The state of the RST pin is unaffected by this reset.
Rev. 1.1
127
C8051F80x-83x
Bit
7
Name
6
5
4
3
2
FERROR
C0RSEF
SWRSF
WDTRSF
1
0
MCDRSF
PORSF
PINRSF
R/W
R
Varies
Varies
R
R
R/W
R/W
R
R/W
Reset
0
Varies
Varies
Varies
Varies
Varies
Unused.
Don’t care.
Read
0
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Unused
Write
6
FERROR Flash Error Reset Flag.
N/A
5
C0RSEF Comparator0 Reset Enable
and Flag.
Writing a 1 enables
Comparator0 as a reset
source (active-low).
Set to 1 if Comparator0
caused the last reset.
4
SWRSF
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7
Description
D
Type
SFR Address = 0xEF
Bit
Name
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SFR Definition 21.2. RSTSRC: Reset Source
Writing a 1 forces a system reset.
Set to 1 if last reset was
caused by a write to
SWRSF.
Software Reset Force and
Flag.
WDTRSF Watchdog Timer Reset Flag. N/A
2
MCDRSF Missing Clock Detector
Enable and Flag.
PORSF
Power-On / VDD Monitor
Writing a 1 enables the
Reset Flag, and VDD monitor VDD monitor as a reset
source.
Reset Enable.
Writing 1 to this bit
before the VDD monitor
is enabled and stabilized
may cause a system
reset.
Set to 1 anytime a poweron or VDD monitor reset
occurs.
When set to 1 all other
RSTSRC flags are indeterminate.
HW Pin Reset Flag.
Set to 1 if RST pin caused
the last reset.
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PINRSF
R
0
N/A
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Note: Do not use read-modify-write operations on this register
128
Set to 1 if Watchdog Timer
overflow caused the last
reset.
Writing a 1 enables the
Set to 1 if Missing Clock
Missing Clock Detector.
Detector timeout caused
The MCD triggers a reset the last reset.
if a missing clock condition
is detected.
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1
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3
Set to 1 if Flash
read/write/erase error
caused the last reset.
Rev. 1.1
C8051F80x-83x
22. Oscillators and Clock Selection
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C8051F80x-83x devices include a programmable internal high-frequency oscillator and an external oscillator drive circuit. The internal high-frequency oscillator can be enabled/disabled and calibrated using the
OSCICN and OSCICL registers, as shown in Figure 22.1. The system clock can be sourced by the external oscillator circuit or the internal oscillator (default). The internal oscillator offers a selectable post-scaling
feature, which is initially set to divide the clock by 8.
Figure 22.1. Oscillator Options
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22.1. System Clock Selection
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The system clock source for the MCU can be selected using the CLKSEL register. The clock selected as
the system clock can be divided by 1, 2, 4, 8, 16, 32, 64, or 128. When switching between two clock divide
values, the transition may take up to 128 cycles of the undivided clock source. The CLKRDY flag can be
polled to determine when the new clock divide value has been applied. The clock divider must be set to
"divide by 1" when entering Suspend mode. The system clock source may also be switched on-the-fly. The
switchover takes effect after one clock period of the slower oscillator.
Rev. 1.1
129
C8051F80x-83x
Bit
7
6
5
4
3
2
Name
CLKRDY
Type
R
R/W
R/W
R/W
R
R/W
Reset
0
0
0
0
0
0
CLKDIV[2:0]
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SFR Definition 22.1. CLKSEL: Clock Select
1
0
CLKSEL[2:0]
SFR Address = 0xA9
Bit
Name
R/W
0
0
D
Function
R/W
CLKRDY
System Clock Divider Clock Ready Flag.
0: The selected clock divide setting has not been applied to the system clock.
1: The selected clock divide setting has been applied to the system clock.
6:4
CLKDIV
3
Unused
System Clock Divider Bits.
Selects the clock division to be applied to the selected source (internal or external).
000: Selected clock is divided by 1.
001: Selected clock is divided by 2.
010: Selected clock is divided by 4.
011: Selected clock is divided by 8.
100: Selected clock is divided by 16.
101: Selected clock is divided by 32.
110: Selected clock is divided by 64.
111: Selected clock is divided by 128.
Read = 0b. Must write 0b.
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2:0 CLKSEL[2:0] System Clock Select.
Selects the oscillator to be used as the undivided system clock source.
000: Internal Oscillator
001: External Oscillator
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All other values reserved.
130
Rev. 1.1
C8051F80x-83x
22.2. Programmable Internal High-Frequency (H-F) Oscillator
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All C8051F80x-83x devices include a programmable internal high-frequency oscillator that defaults as the
system clock after a system reset. The internal oscillator period can be adjusted via the OSCICL register
as defined by SFR Definition 22.2.
On C8051F80x-83x devices, OSCICL is factory calibrated to obtain a 24.5 MHz base frequency.
The internal oscillator output frequency may be divided by 1, 2, 4, or 8, as defined by the IFCN bits in register OSCICN. The divide value defaults to 8 following a reset.
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The precision oscillator supports a spread spectrum mode which modulates the output frequency in order
to reduce the EMI generated by the system. When enabled (SSE = 1), the oscillator output frequency is
modulated by a stepped triangle wave whose frequency is equal to the oscillator frequency divided by 384
(63.8 kHz using the factory calibration). The maximum deviation from the center frequency is ±0.75%. The
output frequency updates occur every 32 cycles and the step size is typically 0.25% of the center frequency.
SFR Definition 22.2. OSCICL: Internal H-F Oscillator Calibration
7
6
5
3
2
1
0
Varies
Varies
Varies
OSCICL[6:0]
Name
R/W
Type
Varies
Varies
Varies
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Varies
Reset
SFR Address = 0xB3
Bit
Name
Varies
Function
OSCICL[7:0] Internal Oscillator Calibration Bits.
These bits determine the internal oscillator period. When set to 00000000b, the H-F
oscillator operates at its fastest setting. When set to 11111111b, the H-F oscillator
operates at its slowest setting. The reset value is factory calibrated to generate an
internal oscillator frequency of 24.5 MHz.
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6:0
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Bit
Rev. 1.1
131
C8051F80x-83x
Bit
7
6
5
4
3
Name
IOSCEN
IFRDY
SUSPEND
STSYNC
SSE
Type
R/W
R
R/W
R
R/W
R
Reset
1
1
0
0
0
0
5
SUSPEND
4
STSYNC
3
SSE
2
Unused
Internal Oscillator Suspend Enable Bit.
Setting this bit to logic 1 places the internal oscillator in SUSPEND mode. The internal oscillator resumes operation when one of the SUSPEND mode awakening
events occurs.
Suspend Timer Synchronization Bit.
This bit is used to indicate when it is safe to read and write the registers associated
with the suspend wake-up timer. If a suspend wake-up source other than Timer 2
has brought the oscillator out of suspend mode, it make take up to three timer clocks
before the timer can be read or written.
0: Timer 2 registers can be read safely.
1: Timer 2 register reads and writes should not be performed.
Spread Spectrum Enable.
Spread spectrum enable bit.
0: Spread Spectrum clock dithering disabled.
1: Spread Spectrum clock dithering enabled.
Read = 0b; Write = Don’t Care
Internal H-F Oscillator Frequency Divider Control Bits.
00: SYSCLK derived from Internal H-F Oscillator divided by 8.
01: SYSCLK derived from Internal H-F Oscillator divided by 4.
10: SYSCLK derived from Internal H-F Oscillator divided by 2.
11: SYSCLK derived from Internal H-F Oscillator divided by 1.
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132
0
Internal H-F Oscillator Frequency Ready Flag.
0: Internal H-F Oscillator is not running at programmed frequency.
1: Internal H-F Oscillator is running at programmed frequency.
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IFCN[1:0]
R
1:0
0
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IFRDY
R/W
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Internal H-F Oscillator Enable Bit.
0: Internal H-F Oscillator Disabled.
1: Internal H-F Oscillator Enabled.
0
IFCN[1:0]
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IOSCEN
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Function
2
D
SFR Address = 0xB2
Bit
Name
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SFR Definition 22.3. OSCICN: Internal H-F Oscillator Control
Rev. 1.1
C8051F80x-83x
22.3. External Oscillator Drive Circuit
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The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor, or RC network. A
CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crystal/resonator must be wired across the XTAL1 and XTAL2 pins as shown in Option 1 of Figure 22.1. A
10 Mresistor also must be wired across the XTAL2 and XTAL1 pins for the crystal/resonator configuration. In RC, capacitor, or CMOS clock configuration, the clock source should be wired to the XTAL2 pin as
shown in Option 2, 3, or 4 of Figure 22.1. The type of external oscillator must be selected in the OSCXCN
register, and the frequency control bits (XFCN) must be selected appropriately (see SFR Definition 22.4).
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Important Note on External Oscillator Usage: Port pins must be configured when using the external
oscillator circuit. When the external oscillator drive circuit is enabled in crystal/resonator mode, Port pins
P0.2 and P0.3 are used as XTAL1 and XTAL2 respectively. When the external oscillator drive circuit is
enabled in capacitor, RC, or CMOS clock mode, Port pin P0.3 is used as XTAL2. The Port I/O Crossbar
should be configured to skip the Port pins used by the oscillator circuit; see Section “23.3. Priority Crossbar
Decoder” on page 143 for Crossbar configuration. Additionally, when using the external oscillator circuit in
crystal/resonator, capacitor, or RC mode, the associated Port pins should be configured as analog inputs.
In CMOS clock mode, the associated pin should be configured as a digital input. See Section “23.4. Port
I/O Initialization” on page 147 for details on Port input mode selection.
Rev. 1.1
133
C8051F80x-83x
7
6
Name
XTLVLD
XOSCMD[2:0]
Type
R
R/W
Reset
0
0
5
4
3
0
R
0
0
0
R/W
0
Function
0
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Crystal Oscillator Valid Flag.
(Read only when XOSCMD = 11x.)
0: Crystal Oscillator is unused or not yet stable.
1: Crystal Oscillator is running and stable.
0
XOSCMD[2:0] External Oscillator Mode Select.
00x: External Oscillator circuit off.
010: External CMOS Clock Mode.
011: External CMOS Clock Mode with divide by 2 stage.
100: RC Oscillator Mode.
101: Capacitor Oscillator Mode.
110: Crystal Oscillator Mode.
111: Crystal Oscillator Mode with divide by 2 stage.
Unused
2:0
XFCN[2:0]
Read = 0; Write = Don’t Care
External Oscillator Frequency Control Bits.
Set according to the desired frequency for Crystal or RC mode.
Set according to the desired K Factor for C mode.
XFCN
Crystal Mode
RC Mode
C Mode
000
f 32 kHz
f 25 kHz
K Factor = 0.87
001
32 kHz f 84 kHz
25 kHz f 50 kHz
K Factor = 2.6
010
84 kHz f 225 kHz
50 kHz f 100 kHz
K Factor = 7.7
011
225 kHz f 590 kHz
100 kHz f 200 kHz
K Factor = 22
100
590 kHz f 1.5 MHz
200 kHz f 400 kHz
K Factor = 65
101
1.5 MHz f 4 MHz
400 kHz f 800 kHz
K Factor = 180
110
4 MHz f 10 MHz
800 kHz f 1.6 MHz
K Factor = 664
111
10 MHz f 30 MHz
1.6 MHz f 3.2 MHz
K Factor = 1590
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3
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6:4
XTLVLD
1
XFCN[2:0]
SFR Address = 0xB1
Bit
Name
7
2
D
Bit
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SFR Definition 22.4. OSCXCN: External Oscillator Control
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22.3.1. External Crystal Example
If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be
configured as shown in Figure 22.1, Option 1. The External Oscillator Frequency Control value (XFCN)
should be chosen from the Crystal column of the table in SFR Definition 22.4 (OSCXCN register). For
example, an 11.0592 MHz crystal requires an XFCN setting of 111b and a 32.768 kHz Watch Crystal
requires an XFCN setting of 001b. After an external 32.768 kHz oscillator is stabilized, the XFCN setting
can be switched to 000 to save power. It is recommended to enable the missing clock detector before
switching the system clock to any external oscillator source.
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When the crystal oscillator is first enabled, the oscillator amplitude detection circuit requires a settling time
to achieve proper bias. Introducing a delay of 1 ms between enabling the oscillator and checking the
XTLVLD bit will prevent a premature switch to the external oscillator as the system clock. Switching to the
external oscillator before the crystal oscillator has stabilized can result in unpredictable behavior. The recommended procedure is as follows:
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1. Force XTAL1 and XTAL2 to a low state. This involves enabling the Crossbar and writing 0 to the port
pins associated with XTAL1 and XTAL2.
2. Configure XTAL1 and XTAL2 as analog inputs.
3. Enable the external oscillator.
4. Wait at least 1 ms.
5. Poll for XTLVLD = 1.
6. If desired, enable the Missing Clock Detector.
7. Switch the system clock to the external oscillator.
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Important Note on External Crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The
crystal should be placed as close as possible to the XTAL pins on the device. The traces should be as
short as possible and shielded with ground plane from any other traces which could introduce noise or
interference.
The capacitors shown in the external crystal configuration provide the load capacitance required by the
crystal for correct oscillation. These capacitors are "in series" as seen by the crystal and "in parallel" with
the stray capacitance of the XTAL1 and XTAL2 pins.
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Note: The desired load capacitance depends upon the crystal and the manufacturer. Please refer to the crystal data
sheet when completing these calculations.
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For example, a tuning-fork crystal of 32.768 kHz with a recommended load capacitance of 12.5 pF should
use the configuration shown in Figure 22.1, Option 1. The total value of the capacitors and the stray capacitance of the XTAL pins should equal 25 pF. With a stray capacitance of 3 pF per pin, the 22 pF capacitors
yield an equivalent capacitance of 12.5 pF across the crystal, as shown in Figure 22.2.
Rev. 1.1
135
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C8051F80x-83x
Figure 22.2. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram
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22.3.2. External RC Example
If an RC network is used as an external oscillator source for the MCU, the circuit should be configured as
shown in Figure 22.1, Option 2. The capacitor should be no greater than 100 pF; however for very small
capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To determine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, first
select the RC network value to produce the desired frequency of oscillation, according to Equation 22.1,
where f = the frequency of oscillation in MHz, C = the capacitor value in pF, and R = the pull-up resistor
value in k.
Equation 22.1. RC Mode Oscillator Frequency
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f = 1.23 10 R C
For example: If the frequency desired is 100 kHz, let R = 246 k and C = 50 pF:
f = 1.23( 103 ) / RC = 1.23 ( 103 ) / [ 246 x 50 ] = 0.1 MHz = 100 kHz
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Referring to the table in SFR Definition 22.4, the required XFCN setting is 010b.
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Equation 22.2. C Mode Oscillator Frequency
f = KF R V DD
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For example: Assume VDD = 3.0 V and f = 150 kHz:
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22.3.3. External Capacitor Example
If a capacitor is used as an external oscillator for the MCU, the circuit should be configured as shown in
Figure 22.1, Option 3. The capacitor should be no greater than 100 pF; however for very small capacitors,
the total capacitance may be dominated by parasitic capacitance in the PCB layout. To determine the
required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, select the capacitor to be used and find the frequency of oscillation according to Equation 22.2, where f = the frequency of
oscillation in MHz, C = the capacitor value in pF, and VDD = the MCU power supply in volts.
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f = KF / (C x VDD)
0.150 MHz = KF / (C x 3.0)
0.150 MHz = 22 / (C x 3.0)
C x 3.0 = 22 / 0.150 MHz
C = 146.6 / 3.0 pF = 48.8 pF
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Since the frequency of roughly 150 kHz is desired, select the K Factor from the table in SFR Definition 22.4
(OSCXCN) as KF = 22:
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Therefore, the XFCN value to use in this example is 011b and C = 50 pF.
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23. Port Input/Output
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Digital and analog resources are available through 17 I/O pins (24-pin and 20-pin packages) or 13 I/O pins
(16-pin packages). Port pins P0.0–P1.7 can be defined as general-purpose I/O (GPIO) or assigned to one
of the internal digital resources as shown in Figure 23.4. Port pin P2.0 can be used as GPIO and is shared
with the C2 Interface Data signal (C2D). The designer has complete control over which functions are
assigned, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved
through the use of a Priority Crossbar Decoder. Note that the state of a Port I/O pin can always be read in
the corresponding Port latch, regardless of the Crossbar settings.
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The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 23.5). The registers XBR0 and XBR1, defined in SFR Definition 23.1 and SFR Definition 23.2, are
used to select internal digital functions.
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All Port I/Os are 5 V tolerant (refer to Figure 23.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1). Complete
Electrical Specifications for Port I/O are given in Section “7. Electrical Characteristics” on page 39.
Figure 23.1. Port I/O Functional Block Diagram
Rev. 1.1
138
C8051F80x-83x
23.1. Port I/O Modes of Operation
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Port pins P0.0–P1.7 use the Port I/O cell shown in Figure 23.2. Each Port I/O cell can be configured by
software for analog I/O or digital I/O using the PnMDIN and PnMDOUT registers. Port pin P2.0 can be configured by software for digital I/O using the P2MDOUT register. On reset, all Port I/O cells default to a high
impedance state with weak pull-ups enabled. Until the crossbar is enabled (XBARE = 1), both the high and
low port I/O drive circuits are explicitly disabled on all crossbar pins.
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23.1.1. Port Pins Configured for Analog I/O
Any pins to be used as Comparator or ADC input, Capacitive Sense input, external oscillator input/output,
VREF output, or AGND connection should be configured for analog I/O (PnMDIN.n = 0, Pn.n = 1). When a
pin is configured for analog I/O, its weak pullup, digital driver, and digital receiver are disabled. To prevent
the low port I/o drive circuit from pulling the pin low, a ‘1’ should be written to the corresponding port latch
(Pn.n = 1). Port pins configured for analog I/O will always read back a value of 0 regardless of the actual
voltage on the pin.
Configuring pins as analog I/O saves power and isolates the Port pin from digital interference. Port pins
configured as digital I/O may still be used by analog peripherals; however, this practice is not recommended and may result in measurement errors.
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23.1.2. Port Pins Configured For Digital I/O
Any pins to be used by digital peripherals (UART, SPI, SMBus, etc.), external digital event capture functions, or as GPIO should be configured as digital I/O (PnMDIN.n = 1). For digital I/O pins, one of two output
modes (push-pull or open-drain) must be selected using the PnMDOUT registers.
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Push-pull outputs (PnMDOUT.n = 1) drive the Port pad to the VDD or GND supply rails based on the output logic value of the Port pin. Open-drain outputs have the high side driver disabled; therefore, they only
drive the Port pad to GND when the output logic value is 0 and become high impedance inputs (both high
and low drivers turned off) when the output logic value is 1.
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When a digital I/O cell is placed in the high impedance state, a weak pull-up transistor pulls the Port pad to
the VDD supply voltage to ensure the digital input is at a defined logic state. Weak pull-ups are disabled
when the I/O cell is driven to GND to minimize power consumption and may be globally disabled by setting
WEAKPUD to 1. The user should ensure that digital I/O are always internally or externally pulled or driven
to a valid logic state to minimize power consumption. Port pins configured for digital I/O always read back
the logic state of the Port pad, regardless of the output logic value of the Port pin.
Figure 23.2. Port I/O Cell Block Diagram
139
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23.1.3. Interfacing Port I/O to 5 V Logic
All Port I/O configured for digital, open-drain operation are capable of interfacing to digital logic operating at
a supply voltage up to 2 V higher than VDD and less than 5.25 V. An external pull-up resistor to the higher
supply voltage is typically required for most systems.
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Important Note: In a multi-voltage interface, the external pull-up resistor should be sized to allow a current
of at least 150 μA to flow into the Port pin when the supply voltage is between (VDD + 0. 6V) and
(VDD + 1.0V). Once the Port pin voltage increases beyond this range, the current flowing into the Port pin
is minimal. Figure 23.3 shows the input current characteristics of port pins driven above VDD. The port pin
requires 150 μA peak overdrive current when its voltage reaches approximately (VDD + 0.7 V).
Figure 23.3. Port I/O Overdrive Current
23.2. Assigning Port I/O Pins to Analog and Digital Functions
Port I/O pins P0.0–P1.7 can be assigned to various analog, digital, and external interrupt functions. The
Port pins assigned to analog functions should be configured for analog I/O, and Port pins assigned to digital or external interrupt functions should be configured for digital I/O.
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23.2.1. Assigning Port I/O Pins to Analog Functions
Table 23.1 shows all available analog functions that require Port I/O assignments. Port pins selected for
these analog functions should have their corresponding bit in PnSKIP set to 1. This reserves the pin
for use by the analog function and does not allow it to be claimed by the Crossbar. Any selected pins
should also have their corresponding bit in the Port Latch set to 1 (Pn.n = 1). This prevents the low
port I/O drive circuit from pulling the pin low. Table 23.1 shows the potential mapping of Port I/O to each
analog function.
Rev. 1.1
140
C8051F80x-83x
Table 23.1. Port I/O Assignment for Analog Functions
Potentially Assignable
Port Pins
SFR(s) used for
Assignment
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Analog Function
P0.0–P1.7
ADC0MX, PnSKIP,
PnMDIN
Comparator0 Input
P0.0–P1.7
CPT0MX, PnSKIP,
PnMDIN
CS0 Input
P0.0–P1.7
CS0MX, CS0SS,
CS0SE, PnMDIN
P0.0
Ground Reference (AGND)
External Oscillator in Crystal Mode (XTAL1)
P0.1
REF0CN, P0SKIP
P0.2
OSCXCN, P0SKIP,
P0MDIN
P0.3
OSCXCN, P0SKIP,
P0MDIN
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External Oscillator in RC, C, or Crystal Mode (XTAL2)
REF0CN, P0SKIP,
PnMDIN
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Voltage Reference (VREF0)
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ADC Input
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23.2.2. Assigning Port I/O Pins to Digital Functions
Any Port pins not assigned to analog functions may be assigned to digital functions or used as GPIO. Most
digital functions rely on the Crossbar for pin assignment; however, some digital functions bypass the
Crossbar in a manner similar to the analog functions listed above. Port pins used by these digital functions and any Port pins selected for use as GPIO should have their corresponding bit in PnSKIP set
to 1. Table 23.2 shows all available digital functions and the potential mapping of Port I/O to each digital
function.
141
Rev. 1.1
C8051F80x-83x
Table 23.2. Port I/O Assignment for Digital Functions
Any pin used for GPIO
SFR(s) used for
Assignment
Any Port pin available for assignment by the
Crossbar. This includes P0.0 - P1.72 pins which
have their PnSKIP bit set to 0.1
P0.0–P2.02
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UART0, SPI0, SMBus,
SYSCLK, PCA0 (CEX0-2
and ECI), T0, or T1.
Potentially Assignable Port Pins
XBR0, XBR1
PnSKIP
Notes:
1. The Crossbar will always assign UART0 pins to P0.4 and P0.5.
2. Port pins P1.4–P1.7 are not available on the 16-pin packages.
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Digital Function
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23.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions
External digital event capture functions can be used to trigger an interrupt or wake the device from a low
power mode when a transition occurs on a digital I/O pin. The digital event capture functions do not require
dedicated pins and will function on both GPIO pins (PnSKIP = 1) and pins in use by the Crossbar (PnSKIP
= 0). External digital event capture functions cannot be used on pins configured for analog I/O. Table 23.3
shows all available external digital event capture functions.
Table 23.3. Port I/O Assignment for External Digital Event Capture Functions
External Interrupt 0
External Interrupt 1
Port Match
Potentially Assignable Port Pins
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Digital Function
SFR(s) used for
Assignment
P0.0–P0.7
IT01CF
P0.0–P0.7
IT01CF
P0.0–P1.7*
P0MASK, P0MAT
P1MASK, P1MAT
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Note: Port pins P1.4–P1.7 are not available on the 16-pin packages.
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C8051F80x-83x
23.3. Priority Crossbar Decoder
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The Priority Crossbar Decoder assigns a priority to each I/O function, starting at the top with UART0. When
a digital resource is selected, the least-significant unassigned Port pin is assigned to that resource (excluding UART0, which is always at pins 4 and 5). If a Port pin is assigned, the Crossbar skips that pin when
assigning the next selected resource. Additionally, the Crossbar will skip Port pins whose associated bits in
the PnSKIP registers are set. The PnSKIP registers allow software to skip Port pins that are to be used for
analog input, dedicated functions, or GPIO.
Because of the nature of the Priority Crossbar Decoder, not all peripherals can be located on all port pins.
Figure 23.4 maps peripherals to the potential port pins on which the peripheral I/O can appear.
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Important Note on Crossbar Configuration: If a Port pin is claimed by a peripheral without use of the
Crossbar, its corresponding PnSKIP bit should be set. This applies to P0.0 if VREF is used, P0.1 if AGND
is used, P0.3 and/or P0.2 if the external oscillator circuit is enabled, P0.6 if the ADC is configured to use
the external conversion start signal (CNVSTR), and any selected ADC, Comparator, or Capacitive Sense
inputs. The Crossbar skips selected pins as if they were already assigned, and moves to the next unassigned pin.
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Registers XBR0, XBR1, and XBR2 are used to assign the digital I/O resources to the physical I/O Port
pins. Note that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus
(SDA and SCL); when a UART is selected, the Crossbar assigns both pins associated with the UART (TX
and RX). UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned to
P0.4; UART RX0 is always assigned to P0.5. Standard Port I/Os appear contiguously after the prioritized
functions have been assigned.
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Important Note: The SPI can be operated in either 3-wire or 4-wire modes, depending on the state of the
NSSMD1–NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not
be routed to a Port pin.
143
Rev. 1.1
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C8051F80x-83x
Figure 23.4. Priority Crossbar Decoder Potential Pin Assignments
Rev. 1.1
144
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C8051F80x-83x
Figure 23.5. Priority Crossbar Decoder Example 1—No Skipped Pins
145
Rev. 1.1
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C8051F80x-83x
Figure 23.6. Priority Crossbar Decoder Example 2—Skipping Pins
Rev. 1.1
146
C8051F80x-83x
23.4. Port I/O Initialization
Port I/O initialization consists of the following steps:
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1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN).
If the pin is in analog mode, a ‘1’ must also be written to the corresponding Port Latch (Pn).
2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port Output Mode register
(PnMDOUT).
3. Select any pins to be skipped by the I/O Crossbar using the Port Skip registers (PnSKIP).
4. Assign Port pins to desired peripherals (XBR0, XBR1).
5. Enable the Crossbar (XBARE = 1).
All Port pins must be configured as either analog or digital inputs. When a pin is configured as an analog
input, its weak pullup, digital driver, and digital receiver are disabled. This process saves power and
reduces noise on the analog input. Pins configured as digital inputs may still be used by analog peripherals; however this practice is not recommended.
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Additionally, all analog input pins should be configured to be skipped by the Crossbar (accomplished by
setting the associated bits in PnSKIP). Port input mode is set in the PnMDIN register, where a 1 indicates a
digital input, and a 0 indicates an analog input. All port pins in analog mode must have a ‘1’ set in the corresponding Port Latch register. All pins default to digital inputs on reset. See SFR Definition 23.8 and SFR
Definition 23.12 for the PnMDIN register details.
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The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMDOUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is
required even for the digital resources selected in the XBRn registers, and is not automatic. The only
exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the
PnMDOUT settings. When the WEAKPUD bit in XBR1 is 0, a weak pullup is enabled for all Port I/O configured as open-drain. WEAKPUD does not affect the push-pull Port I/O. Furthermore, the weak pullup is
turned off on an output that is driving a 0 to avoid unnecessary power dissipation.
Registers XBR0 and XBR1 must be loaded with the appropriate values to select the digital I/O functions
required by the design. Setting the XBARE bit in XBR1 to 1 enables the Crossbar. Until the Crossbar is
enabled, the external pins remain as standard Port I/O (in input mode), regardless of the XBRn Register
settings. For given XBRn Register settings, one can determine the I/O pin-out using the Priority Decode
Table; as an alternative, the Configuration Wizard utility will determine the Port I/O pin-assignments based
on the XBRn Register settings.
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The Crossbar must be enabled to use Port pins as standard Port I/O in output mode. Port output drivers
are disabled while the Crossbar is disabled.
147
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7
6
Name
5
4
3
2
1
0
CP0AE
CP0E
SYSCKE
SMB0E
SPI0E
URT0E
R/W
R/W
0
0
Type
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
SFR Address = 0xE1
Bit
Name
Function
Unused
Read = 00b. Write = don’t care.
5
CP0AE
Comparator0 Asynchronous Output Enable.
0: Asynchronous CP0 unavailable at Port pin.
1: Asynchronous CP0 routed to Port pin.
4
CP0E
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SYSCKE SYSCLK Output Enable.
0: SYSCLK unavailable at Port pin.
1: SYSCLK output routed to Port pin.
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3
Comparator0 Output Enable.
0: CP0 unavailable at Port pin.
1: CP0 routed to Port pin.
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SFR Definition 23.1. XBR0: Port I/O Crossbar Register 0
SMB0E
SMBus I/O Enable.
0: SMBus I/O unavailable at Port pins.
1: SMBus I/O routed to Port pins.
1
SPI0E
SPI I/O Enable.
0: SPI I/O unavailable at Port pins.
1: SPI I/O routed to Port pins. Note that the SPI can be assigned either 3 or 4 GPIO
pins.
0
URT0E
UART I/O Output Enable.
0: UART I/O unavailable at Port pin.
1: UART TX0, RX0 routed to Port pins P0.4 and P0.5.
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2
Rev. 1.1
148
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7
Name WEAKPUD
6
5
4
3
XBARE
T1E
T0E
ECIE
2
R/W
R/W
R/W
R/W
R/W
R
Reset
0
0
0
0
0
0
XBARE
5
T1E
4
T0E
3
ECIE
2
Unused
Crossbar Enable.
0: Crossbar disabled.
1: Crossbar enabled.
T1 Enable.
0: T1 unavailable at Port pin.
1: T1 routed to Port pin.
T0 Enable.
0: T0 unavailable at Port pin.
1: T0 routed to Port pin.
PCA0 External Counter Input Enable.
0: ECI unavailable at Port pin.
1: ECI routed to Port pin.
Read = 0b; Write = Don’t Care.
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1:0 PCA0ME[1:0] PCA Module I/O Enable Bits.
00: All PCA I/O unavailable at Port pins.
01: CEX0 routed to Port pin.
10: CEX0, CEX1 routed to Port pins.
11: CEX0, CEX1, CEX2 routed to Port pins.
149
R/W
0
0
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6
R/W
Port I/O Weak Pullup Disable.
0: Weak Pullups enabled (except for Ports whose I/O are configured for analog
mode).
1: Weak Pullups disabled.
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WEAKPUD
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7
Function
0
PCA0ME[1:0]
Type
SFR Address = 0xE2
Bit
Name
1
D
Bit
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SFR Definition 23.2. XBR1: Port I/O Crossbar Register 1
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C8051F80x-83x
23.5. Port Match
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Port match functionality allows system events to be triggered by a logic value change on P0 or P1. A software controlled value stored in the PnMATCH registers specifies the expected or normal logic values of P0
and P1. A Port mismatch event occurs if the logic levels of the Port’s input pins no longer match the software controlled value. This allows Software to be notified if a certain change or pattern occurs on P0 or P1
input pins regardless of the XBRn settings.
The PnMASK registers can be used to individually select which P0 and P1 pins should be compared
against the PnMATCH registers. A Port mismatch event is generated if (P0 & P0MASK) does not equal
(P0MATCH & P0MASK) or if (P1 & P1MASK) does not equal (P1MATCH & P1MASK).
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A Port mismatch event may be used to generate an interrupt or wake the device from a low power mode,
such as IDLE or SUSPEND. See the Interrupts and Power Options chapters for more details on interrupt
and wake-up sources.
Rev. 1.1
150
C8051F80x-83x
7
6
5
4
3
Name
P0MASK[7:0]
Type
R/W
0
Reset
0
0
0
0
SFR Address = 0xFE
Bit
Name
P0MASK[7:0]
0
1
0
0
0
Function
Port 0 Mask Value.
Selects P0 pins to be compared to the corresponding bits in P0MAT.
0: P0.n pin logic value is ignored and cannot cause a Port Mismatch event.
1: P0.n pin logic value is compared to P0MAT.n.
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SFR Definition 23.3. P0MASK: Port 0 Mask Register
Bit
7
6
5
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SFR Definition 23.4. P0MAT: Port 0 Match Register
4
3
0
1
1
1
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R/W
Type
1
Reset
1
1
1
SFR Address = 0xFD
Bit
Name
1
Function
Port 0 Match Value.
Match comparison value used on Port 0 for bits in P0MASK which are set to 1.
0: P0.n pin logic value is compared with logic LOW.
1: P0.n pin logic value is compared with logic HIGH.
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P0MAT[7:0]
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1
P0MAT[7:0]
Name
7:0
2
Rev. 1.1
C8051F80x-83x
7
6
5
4
3
Name
P1MASK[7:0]
Type
R/W
0
Reset
0
0
0
0
SFR Address = 0xEE
Bit
Name
P1MASK[7:0]
0
1
0
0
0
Function
Port 1 Mask Value.
Selects P1 pins to be compared to the corresponding bits in P1MAT.
0: P1.n pin logic value is ignored and cannot cause a Port Mismatch event.
1: P1.n pin logic value is compared to P1MAT.n.
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7:0
2
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SFR Definition 23.5. P1MASK: Port 1 Mask Register
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Note: P1.4–P1.7 are not available on 16-pin packages.
SFR Definition 23.6. P1MAT: Port 1 Match Register
7
6
4
3
2
1
0
1
1
1
P1MAT[7:0]
Name
R/W
Type
1
Reset
1
SFR Address = 0xED
Bit
Name
P1MAT[7:0]
1
1
1
Function
Port 1 Match Value.
Match comparison value used on Port 1 for bits in P1MASK which are set to 1.
0: P1.n pin logic value is compared with logic LOW.
1: P1.n pin logic value is compared with logic HIGH.
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Note: P1.4–P1.7 are not available on 16-pin packages.
23.6. Special Function Registers for Accessing and Configuring Port I/O
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All Port I/O are accessed through corresponding special function registers (SFRs) that are both byte
addressable and bit addressable. When writing to a Port, the value written to the SFR is latched to maintain the output data value at each pin. When reading, the logic levels of the Port's input pins are returned
regardless of the XBRn settings (i.e., even when the pin is assigned to another signal by the Crossbar, the
Port register can always read its corresponding Port I/O pin). The exception to this is the execution of the
read-modify-write instructions that target a Port Latch register as the destination. The read-modify-write
instructions when operating on a Port SFR are the following: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ
and MOV, CLR or SETB, when the destination is an individual bit in a Port SFR. For these instructions, the
value of the latch register (not the pin) is read, modified, and written back to the SFR.
Rev. 1.1
152
C8051F80x-83x
Each Port has a corresponding PnSKIP register which allows its individual Port pins to be assigned to digital functions or skipped by the Crossbar. All Port pins used for analog functions or GPIO should have their
PnSKIP bit set to 1.
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The Port input mode of the I/O pins is defined using the Port Input Mode registers (PnMDIN). Each Port
cell can be configured for analog or digital I/O. This selection is required even for the digital resources
selected in the XBRn registers, and is not automatic. The only exception to this is P2.0, which can only be
used for digital I/O.
SFR Definition 23.7. P0: Port 0
Bit
7
6
5
4
3
P0[7:0]
Type
R/W
1
1
1
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Name
Reset
1
Port 0 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells configured for digital I/O.
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153
1
2
1
0
1
1
1
Write
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
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P0[7:0]
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SFR Address = 0x80; Bit-Addressable
Bit
Name
Description
7:0
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The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMDOUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is
required even for the digital resources selected in the XBRn registers, and is not automatic. The only
exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the
PnMDOUT settings.
Rev. 1.1
Read
0: P0.n Port pin is logic
LOW.
1: P0.n Port pin is logic
HIGH.
C8051F80x-83x
7
6
5
4
3
Name
P0MDIN[7:0]
Type
R/W
1
Reset
1
1
1
1
SFR Address = 0xF1
Bit
Name
P0MDIN[7:0]
1
1
0
1
1
Function
Analog Configuration Bits for P0.7–P0.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disabled. In order for the P0.n pin to be in analog mode, there
MUST be a ‘1’ in the Port Latch register corresponding to that pin.
0: Corresponding P0.n pin is configured for analog mode.
1: Corresponding P0.n pin is not configured for analog mode.
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2
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SFR Definition 23.8. P0MDIN: Port 0 Input Mode
Bit
7
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SFR Definition 23.9. P0MDOUT: Port 0 Output Mode
6
5
4
3
2
1
0
0
0
0
P0MDOUT[7:0]
Name
R/W
Type
0
Reset
0
SFR Address = 0xA4
Bit
Name
0
0
0
Function
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7:0 P0MDOUT[7:0] Output Configuration Bits for P0.7–P0.0 (respectively).
These bits are ignored if the corresponding bit in register P0MDIN is logic 0.
0: Corresponding P0.n Output is open-drain.
1: Corresponding P0.n Output is push-pull.
Rev. 1.1
154
C8051F80x-83x
7
6
5
4
3
Name
P0SKIP[7:0]
Type
R/W
0
Reset
0
0
0
0
SFR Address = 0xD4
Bit
Name
P0SKIP[7:0]
0
1
0
0
0
Function
Port 0 Crossbar Skip Enable Bits.
These bits select Port 0 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P0.n pin is not skipped by the Crossbar.
1: Corresponding P0.n pin is skipped by the Crossbar.
SFR Definition 23.11. P1: Port 1
7
6
5
4
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Bit
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2
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Bit
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SFR Definition 23.10. P0SKIP: Port 0 Skip
1
0
1
1
1
1
R/W
Type
1
Reset
1
1
1
SFR Address = 0x90; Bit-Addressable
Bit
Name
Description
Port 1 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells configured for digital I/O.
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P1[7:0]
Write
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
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Note: P1.4–P1.7 are not
available on 16-pin
packages.
155
2
P1[7:0]
Name
7:0
3
Rev. 1.1
Read
0: P1.n Port pin is logic
LOW.
1: P1.n Port pin is logic
HIGH.
C8051F80x-83x
7
6
5
4
3
Name
P1MDIN[7:0]
Type
R/W
1*
Reset
1*
1*
1*
1
SFR Address = 0xF2
Bit
Name
P1MDIN[7:0]
1
1
0
1
1
Function
Analog Configuration Bits for P1.7–P1.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disabled. In order for the P1.n pin to be in analog mode, there
MUST be a 1 in the Port Latch register corresponding to that pin.
0: Corresponding P1.n pin is configured for analog mode.
1: Corresponding P1.n pin is not configured for analog mode.
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2
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Bit
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SFR Definition 23.12. P1MDIN: Port 1 Input Mode
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Note: P1.4–P1.7 are not available on 16-pin packages, with the reset value of 0000b for
P1MDIN[7:4].
Bit
7
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SFR Definition 23.13. P1MDOUT: Port 1 Output Mode
6
5
4
3
2
1
0
0
0
0
P1MDOUT[7:0]
Name
R/W
Type
0
Reset
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SFR Address = 0xA5
Bit
Name
0
0
0
0
Function
Note: P1.4–P1.7 are not available on 16-pin packages.
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7:0 P1MDOUT[7:0] Output Configuration Bits for P1.7–P1.0 (respectively).
These bits are ignored if the corresponding bit in register P1MDIN is logic 0.
0: Corresponding P1.n Output is open-drain.
1: Corresponding P1.n Output is push-pull.
Rev. 1.1
156
C8051F80x-83x
7
6
5
4
3
Name
P1SKIP[7:0]
Type
R/W
0*
Reset
0*
0*
0*
SFR Address = 0xD5
Bit
Name
P1SKIP[7:0]
0
1
0
0
0
Function
Port 1 Crossbar Skip Enable Bits.
These bits select Port 1 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P1.n pin is not skipped by the Crossbar.
1: Corresponding P1.n pin is skipped by the Crossbar.
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0
2
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Bit
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SFR Definition 23.14. P1SKIP: Port 1 Skip
Bit
7
Name
Type
R
Reset
0
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SFR Definition 23.15. P2: Port 2
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Note: P1.4–P1.7 are not available on 16-pin packages, with the reset value of 1111b for
P1SKIP[7:4].
6
5
4
P2[0]
P2[0]
R
R
R
R
R/W
0
0
0
0
0
0
1
Write
Read
Don’t Care
0000000b
Port 2 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells configured for digital I/O.
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
0: P2.0 Port pin is logic
LOW.
1: P2.0 Port pin is logic
HIGH.
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0
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0
1
Unused.
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Unused
2
R
SFR Address = 0xA0; Bit-Addressable
Bit
Name
Description
7:1
3
Rev. 1.1
C8051F80x-83x
Bit
7
6
5
4
3
2
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SFR Definition 23.16. P2MDOUT: Port 2 Output Mode
1
0
P2MDOUT[0]
Name
R
R
R
R
R
R
R
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xA6
Bit
Name
Function
Unused
Read = 0000000b; Write = Don’t Care
0
P2MDOUT[0]
Output Configuration Bits for P2.0.
0: P2.0 Output is open-drain.
1: P2.0 Output is push-pull.
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7:1
D
Type
Rev. 1.1
158
C8051F80x-83x
24. Cyclic Redundancy Check Unit (CRC0)
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C8051F80x-83x devices include a cyclic redundancy check unit (CRC0) that can perform a CRC using a
16-bit or 32-bit polynomial. CRC0 accepts a stream of 8-bit data written to the CRC0IN register. CRC0
posts the 16-bit or 32-bit result to an internal register. The internal result register may be accessed indirectly using the CRC0PNT bits and CRC0DAT register, as shown in Figure 24.1. CRC0 also has a bit
reverse register for quick data manipulation.
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Figure 24.1. CRC0 Block Diagram
Rev. 1.1
159
C8051F80x-83x
24.1. 16-bit CRC Algorithm
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The C8051F80x-83x CRC unit calculates the 16-bit CRC MSB-first, using a poly of 0x1021. The following
describes the 16-bit CRC algorithm performed by the hardware:
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1. XOR the most-significant byte of the current CRC result with the input byte. If this is the first iteration of
the CRC unit, the current CRC result will be the set initial value (0x0000 or 0xFFFF).
2. If the MSB of the CRC result is set, left-shift the CRC result, and then XOR the CRC result with the
polynomial (0x1021).
3. If the MSB of the CRC result is not set, left-shift the CRC result.
4. Repeat at Step 2 for the number of input bits (8).
For example, the 16-bit C8051F80x-83x CRC algorithm can be described by the following code:
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unsigned short UpdateCRC (unsigned short CRC_acc, unsigned char CRC_input){
unsigned char i;
// loop counter
#define POLY 0x1021
// Create the CRC "dividend" for polynomial arithmetic (binary arithmetic
// with no carries)
CRC_acc = CRC_acc ^ (CRC_input > 1;
}
}
return CRC_acc; // Return the final remainder (CRC value)
}
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Table 24.2 lists example input values and the associated outputs using the 32-bit C8051F80x-83x CRC
algorithm (an initial value of 0xFFFFFFFF is used):
Table 24.2. Example 32-bit CRC Outputs
Input
0x63
0xAA, 0xBB, 0xCC
0x00, 0x00, 0xAA, 0xBB, 0xCC
Output
0xF9462090
0x41B207B3
0x78D129BC
Rev. 1.1
161
C8051F80x-83x
24.3. Preparing for a CRC Calculation
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To prepare CRC0 for a CRC calculation, software should select the desired polynomial and set the initial
value of the result. Two polynomials are available: 0x1021 (16-bit) and 0x04C11DB7 (32-bit). The CRC0
result may be initialized to one of two values: 0x00000000 or 0xFFFFFFFF. The following steps can be
used to initialize CRC0.
1. Select a polynomial (Set CRC0SEL to 0 for 32-bit or 1 for 16-bit).
2. Select the initial result value (Set CRC0VAL to 0 for 0x00000000 or 1 for 0xFFFFFFFF).
3. Set the result to its initial value (Write 1 to CRC0INIT).
24.4. Performing a CRC Calculation
Prepare CRC0 for a CRC calculation as shown above.
Write the index of the starting page to CRC0AUTO.
Set the AUTOEN bit in CRC0AUTO.
Write the number of Flash sectors to perform in the CRC calculation to CRC0CNT.
Note: Each Flash sector is 512 bytes.
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1.
2.
3.
4.
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Once CRC0 is initialized, the input data stream is sequentially written to CRC0IN, one byte at a time. The
CRC0 result is automatically updated after each byte is written. The CRC engine may also be configured to
automatically perform a CRC on one or more Flash sectors. The following steps can be used to automatically perform a CRC on Flash memory.
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5. Write any value to CRC0CN (or OR its contents with 0x00) to initiate the CRC calculation. The CPU will
not execute code any additional code until the CRC operation completes.
6. Clear the AUTOEN bit in CRC0AUTO.
7. Read the CRC result using the procedure below.
24.5. Accessing the CRC0 Result
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The internal CRC0 result is 32-bits (CRC0SEL = 0b) or 16-bits (CRC0SEL = 1b). The CRC0PNT bits
select the byte that is targeted by read and write operations on CRC0DAT and increment after each read or
write. The calculation result will remain in the internal CR0 result register until it is set, overwritten, or additional data is written to CRC0IN.
162
Rev. 1.1
C8051F80x-83x
Bit
7
6
5
4
3
2
1
CRC0SEL CRC0INIT CRC0VAL
Type
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
SFR Address = 0xCE
Bit
Name
Function
CRC0PNT[1:0]
R/W
0
0
7:5
Unused
4
CRC0SEL
CRC0 Polynomial Select Bit.
This bit selects the CRC0 polynomial and result length (32-bit or 16-bit).
0: CRC0 uses the 32-bit polynomial 0x04C11DB7 for calculating the CRC result.
1: CRC0 uses the 16-bit polynomial 0x1021 for calculating the CRC result.
3
CRC0INIT
CRC0 Result Initialization Bit.
Writing a 1 to this bit initializes the entire CRC result based on CRC0VAL.
2
CRC0VAL
CRC0 Set Value Initialization Bit.
This bit selects the set value of the CRC result.
0: CRC result is set to 0x00000000 on write of 1 to CRC0INIT.
1: CRC result is set to 0xFFFFFFFF on write of 1 to CRC0INIT.
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Read = 000b; Write = Don’t Care.
0
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SFR Definition 24.1. CRC0CN: CRC0 Control
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1:0 CRC0PNT[1:0] CRC0 Result Pointer.
Specifies the byte of the CRC result to be read/written on the next access to
CRC0DAT. The value of these bits will auto-increment upon each read or write.
For CRC0SEL = 0:
00: CRC0DAT accesses bits 7–0 of the 32-bit CRC result.
01: CRC0DAT accesses bits 15–8 of the 32-bit CRC result.
10: CRC0DAT accesses bits 23–16 of the 32-bit CRC result.
11: CRC0DAT accesses bits 31–24 of the 32-bit CRC result.
For CRC0SEL = 1:
00: CRC0DAT accesses bits 7–0 of the 16-bit CRC result.
01: CRC0DAT accesses bits 15–8 of the 16-bit CRC result.
10: CRC0DAT accesses bits 7–0 of the 16-bit CRC result.
11: CRC0DAT accesses bits 15–8 of the 16-bit CRC result.
Rev. 1.1
163
C8051F80x-83x
7
6
5
4
3
Name
CRC0IN[7:0]
Type
R/W
0
Reset
0
0
0
0
SFR Address = 0xDD
Bit
Name
CRC0IN[7:0]
0
1
0
0
0
Function
CRC0 Data Input.
Each write to CRC0IN results in the written data being computed into the existing
CRC result according to the CRC algorithm described in Section 24.1
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2
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Bit
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SFR Definition 24.2. CRC0IN: CRC Data Input
Bit
7
6
5
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SFR Definition 24.3. CRC0DATA: CRC Data Output
4
3
2
1
0
0
0
0
CRC0DAT[7:0]
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Name
R/W
Type
0
Reset
0
0
0
SFR Address = 0xDE
Bit
Name
0
Function
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7:0 CRC0DAT[7:0] CRC0 Data Output.
Each read or write performed on CRC0DAT targets the CRC result bits pointed to
by the CRC0 Result Pointer (CRC0PNT bits in CRC0CN).
164
Rev. 1.1
C8051F80x-83x
Bit
7
6
5
Name
AUTOEN
CRCCPT
Reserved
4
3
2
CRC0ST[4:0]
R/W
0
Reset
1
0
0
0
SFR Address = 0xD2
Bit
Name
0
1
0
0
0
D
Type
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SFR Definition 24.4. CRC0AUTO: CRC Automatic Control
Function
AUTOEN
Automatic CRC Calculation Enable.
When AUTOEN is set to 1, any write to CRC0CN will initiate an automatic CRC
starting at Flash sector CRC0ST and continuing for CRC0CNT sectors.
6
CRCCPT
Automatic CRC Calculation Complete.
Set to 0 when a CRC calculation is in progress. Code execution is stopped during
a CRC calculation, therefore reads from firmware will always return 1.
5
Reserved
Must write 0.
4:0
CRC0ST[4:0]
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7
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Automatic CRC Calculation Starting Flash Sector.
These bits specify the Flash sector to start the automatic CRC calculation. The
starting address of the first Flash sector included in the automatic CRC calculation
is CRC0ST x 512.
SFR Definition 24.5. CRC0CNT: CRC Automatic Flash Sector Count
Bit
7
Name
Reset
0
5
4
0
0
ec
1
0
0
0
R/W
0
0
Function
Read = 00b; Write = Don’t Care.
CRC0CNT[5:0] Automatic CRC Calculation Flash Sector Count.
These bits specify the number of Flash sectors to include when performing an
automatic CRC calculation. The base address of the last flash sector included in
the automatic CRC calculation is equal to (CRC0ST + CRC0CNT) x 512.
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5:0
Unused
2
CRC0CNT[5:0]
0
SFR Address = 0xD3
Bit
Name
7:6
3
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Type
6
Rev. 1.1
165
C8051F80x-83x
24.6. CRC0 Bit Reverse Feature
SFR Definition 24.6. CRC0FLIP: CRC Bit Flip
Bit
7
6
5
4
3
CRC0FLIP[7:0]
Type
R/W
0
0
0
SFR Address = 0xCF
Bit
Name
CRC0FLIP[7:0]
0
0
0
CRC0 Bit Flip.
Any byte written to CRC0FLIP is read back in a bit-reversed order, i.e. the written
LSB becomes the MSB. For example:
If 0xC0 is written to CRC0FLIP, the data read back will be 0x03.
If 0x05 is written to CRC0FLIP, the data read back will be 0xA0.
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0
Function
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7:0
0
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0
Reset
1
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Name
2
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CRC0 includes hardware to reverse the bit order of each bit in a byte as shown in Figure 24.1. Each byte
of data written to CRC0FLIP is read back bit reversed. For example, if 0xC0 is written to CRC0FLIP, the
data read back is 0x03. Bit reversal is a useful mathematical function used in algorithms such as the FFT.
Rev. 1.1
C8051F80x-83x
25. Enhanced Serial Peripheral Interface (SPI0)
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The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous
serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input
to select SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding
contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can
also be configured as a chip-select output in master mode, or disabled for 3-wire operation. Additional general purpose port I/O pins can be used to select multiple slave devices in master mode.
Figure 25.1. SPI Block Diagram
Rev. 1.1
167
C8051F80x-83x
25.1. Signal Descriptions
The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below.
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25.1.1. Master Out, Slave In (MOSI)
The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It
is used to serially transfer data from the master to the slave. This signal is an output when SPI0 is operating as a master and an input when SPI0 is operating as a slave. Data is transferred most-significant bit
first. When configured as a master, MOSI is driven by the MSB of the shift register in both 3- and 4-wire
mode.
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25.1.2. Master In, Slave Out (MISO)
The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device.
It is used to serially transfer data from the slave to the master. This signal is an input when SPI0 is operating as a master and an output when SPI0 is operating as a slave. Data is transferred most-significant bit
first. The MISO pin is placed in a high-impedance state when the SPI module is disabled and when the SPI
operates in 4-wire mode as a slave that is not selected. When acting as a slave in 3-wire mode, MISO is
always driven by the MSB of the shift register.
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25.1.3. Serial Clock (SCK)
The serial clock (SCK) signal is an output from the master device and an input to slave devices. It is used
to synchronize the transfer of data between the master and slave on the MOSI and MISO lines. SPI0 generates this signal when operating as a master. The SCK signal is ignored by a SPI slave when the slave is
not selected (NSS = 1) in 4-wire slave mode.
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25.1.4. Slave Select (NSS)
The function of the slave-select (NSS) signal is dependent on the setting of the NSSMD1 and NSSMD0
bits in the SPI0CN register. There are three possible modes that can be selected with these bits:
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1. NSSMD[1:0] = 00: 3-Wire Master or 3-Wire Slave Mode: SPI0 operates in 3-wire mode, and NSS is
disabled. When operating as a slave device, SPI0 is always selected in 3-wire mode. Since no select
signal is present, SPI0 must be the only slave on the bus in 3-wire mode. This is intended for point-topoint communication between a master and one slave.
2. NSSMD[1:0] = 01: 4-Wire Slave or Multi-Master Mode: SPI0 operates in 4-wire mode, and NSS is
enabled as an input. When operating as a slave, NSS selects the SPI0 device. When operating as a
master, a 1-to-0 transition of the NSS signal disables the master function of SPI0 so that multiple
master devices can be used on the same SPI bus.
3. NSSMD[1:0] = 1x: 4-Wire Master Mode: SPI0 operates in 4-wire mode, and NSS is enabled as an
output. The setting of NSSMD0 determines what logic level the NSS pin will output. This configuration
should only be used when operating SPI0 as a master device.
See Figure 25.2, Figure 25.3, and Figure 25.4 for typical connection diagrams of the various operational
modes. Note that the setting of NSSMD bits affects the pinout of the device. When in 3-wire master or
3-wire slave mode, the NSS pin will not be mapped by the crossbar. In all other modes, the NSS signal will
be mapped to a pin on the device. See Section “23. Port Input/Output” on page 138 for general purpose
port I/O and crossbar information.
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25.2. SPI0 Master Mode Operation
A SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by setting the
Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data register (SPI0DAT) when
in master mode writes to the transmit buffer. If the SPI shift register is empty, the byte in the transmit buffer
is moved to the shift register, and a data transfer begins. The SPI0 master immediately shifts out the data
serially on the MOSI line while providing the serial clock on SCK. The SPIF (SPI0CN.7) flag is set to logic
1 at the end of the transfer. If interrupts are enabled, an interrupt request is generated when the SPIF flag
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is set. While the SPI0 master transfers data to a slave on the MOSI line, the addressed SPI slave device
simultaneously transfers the contents of its shift register to the SPI master on the MISO line in a full-duplex
operation. Therefore, the SPIF flag serves as both a transmit-complete and receive-data-ready flag. The
data byte received from the slave is transferred MSB-first into the master's shift register. When a byte is
fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by
reading SPI0DAT.
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When configured as a master, SPI0 can operate in one of three different modes: multi-master mode, 3-wire
single-master mode, and 4-wire single-master mode. The default, multi-master mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In this mode, NSS is an input to the device, and is
used to disable the master SPI0 when another master is accessing the bus. When NSS is pulled low in this
mode, MSTEN (SPI0CN.6) and SPIEN (SPI0CN.0) are set to 0 to disable the SPI master device, and a
Mode Fault is generated (MODF, SPI0CN.5 = 1). Mode Fault will generate an interrupt if enabled. SPI0
must be manually re-enabled in software under these circumstances. In multi-master systems, devices will
typically default to being slave devices while they are not acting as the system master device. In multi-master mode, slave devices can be addressed individually (if needed) using general-purpose I/O pins.
Figure 25.2 shows a connection diagram between two master devices in multiple-master mode.
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3-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. In this
mode, NSS is not used, and is not mapped to an external port pin through the crossbar. Any slave devices
that must be addressed in this mode should be selected using general-purpose I/O pins. Figure 25.3
shows a connection diagram between a master device in 3-wire master mode and a slave device.
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4-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 1. In this mode, NSS is configured as an
output pin, and can be used as a slave-select signal for a single SPI device. In this mode, the output value
of NSS is controlled (in software) with the bit NSSMD0 (SPI0CN.2). Additional slave devices can be
addressed using general-purpose I/O pins. Figure 25.4 shows a connection diagram for a master device in
4-wire master mode and two slave devices.
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Figure 25.2. Multiple-Master Mode Connection Diagram
Figure 25.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram
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Figure 25.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram
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25.3. SPI0 Slave Mode Operation
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When SPI0 is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are
shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK signal. A bit counter in the SPI0 logic counts SCK edges. When 8 bits have been shifted through the shift register, the SPIF flag is set to logic 1, and the byte is copied into the receive buffer. Data is read from the
receive buffer by reading SPI0DAT. A slave device cannot initiate transfers. Data to be transferred to the
master device is pre-loaded into the shift register by writing to SPI0DAT. Writes to SPI0DAT are doublebuffered, and are placed in the transmit buffer first. If the shift register is empty, the contents of the transmit
buffer will immediately be transferred into the shift register. When the shift register already contains data,
the SPI will load the shift register with the transmit buffer’s contents after the last SCK edge of the next (or
current) SPI transfer.
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When configured as a slave, SPI0 can be configured for 4-wire or 3-wire operation. The default, 4-wire
slave mode, is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In 4-wire mode, the
NSS signal is routed to a port pin and configured as a digital input. SPI0 is enabled when NSS is logic 0,
and disabled when NSS is logic 1. The bit counter is reset on a falling edge of NSS. Note that the NSS signal must be driven low at least 2 system clocks before the first active edge of SCK for each byte transfer.
Figure 25.4 shows a connection diagram between two slave devices in 4-wire slave mode and a master
device.
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3-wire slave mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. NSS is not
used in this mode, and is not mapped to an external port pin through the crossbar. Since there is no way of
uniquely addressing the device in 3-wire slave mode, SPI0 must be the only slave device present on the
bus. It is important to note that in 3-wire slave mode there is no external means of resetting the bit counter
that determines when a full byte has been received. The bit counter can only be reset by disabling and reenabling SPI0 with the SPIEN bit. Figure 25.3 shows a connection diagram between a slave device in 3wire slave mode and a master device.
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When SPI0 interrupts are enabled, the following four flags will generate an interrupt when they are set to
logic 1:
All of the following bits must be cleared by software.
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The SPI Interrupt Flag, SPIF (SPI0CN.7) is set to logic 1 at the end of each byte transfer. This flag can
occur in all SPI0 modes.
The Write Collision Flag, WCOL (SPI0CN.6) is set to logic 1 if a write to SPI0DAT is attempted when
the transmit buffer has not been emptied to the SPI shift register. When this occurs, the write to
SPI0DAT will be ignored, and the transmit buffer will not be written.This flag can occur in all SPI0
modes.
The Mode Fault Flag MODF (SPI0CN.5) is set to logic 1 when SPI0 is configured as a master, and for
multi-master mode and the NSS pin is pulled low. When a Mode Fault occurs, the MSTEN and SPIEN
bits in SPI0CN are set to logic 0 to disable SPI0 and allow another master device to access the bus.
The Receive Overrun Flag RXOVRN (SPI0CN.4) is set to logic 1 when configured as a slave, and a
transfer is completed and the receive buffer still holds an unread byte from a previous transfer. The new
byte is not transferred to the receive buffer, allowing the previously received data byte to be read. The
data byte which caused the overrun is lost.
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25.5. Serial Clock Phase and Polarity
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Four combinations of serial clock phase and polarity can be selected using the clock control bits in the
SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases
(edge used to latch the data). The CKPOL bit (SPI0CFG.4) selects between an active-high or active-low
clock. Both master and slave devices must be configured to use the same clock phase and polarity. SPI0
should be disabled (by clearing the SPIEN bit, SPI0CN.0) when changing the clock phase or polarity. The
clock and data line relationships for master mode are shown in Figure 25.5. For slave mode, the clock and
data relationships are shown in Figure 25.6 and Figure 25.7. Note that CKPHA should be set to 0 on both
the master and slave SPI when communicating between two Silicon Labs C8051 devices.
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The SPI0 Clock Rate Register (SPI0CKR) as shown in SFR Definition 25.3 controls the master mode
serial clock frequency. This register is ignored when operating in slave mode. When the SPI is configured
as a master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency or 12.5 MHz,
whichever is slower. When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for
full-duplex operation is 1/10 the system clock frequency, provided that the master issues SCK, NSS (in 4wire slave mode), and the serial input data synchronously with the slave’s system clock. If the master
issues SCK, NSS, and the serial input data asynchronously, the maximum data transfer rate (bits/sec)
must be less than 1/10 the system clock frequency. In the special case where the master only wants to
transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the
SPI slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency.
This is provided that the master issues SCK, NSS, and the serial input data synchronously with the slave’s
system clock.
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Figure 25.6. Slave Mode Data/Clock Timing (CKPHA = 0)
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Figure 25.5. Master Mode Data/Clock Timing
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25.6. SPI Special Function Registers
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Figure 25.7. Slave Mode Data/Clock Timing (CKPHA = 1)
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SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN
Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate
Register. The four special function registers related to the operation of the SPI0 Bus are described in the
following figures.
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6
5
4
3
2
Name
SPIBSY
MSTEN
CKPHA
CKPOL
SLVSEL
Type
R
R/W
R/W
R/W
Reset
0
0
0
0
SFR Address = 0xA1
Bit
Name
1
0
NSSIN
SRMT
RXBMT
R
R
R
R
0
1
1
1
Function
D
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SFR Definition 25.1. SPI0CFG: SPI0 Configuration
SPIBSY
SPI Busy.
This bit is set to logic 1 when a SPI transfer is in progress (master or slave mode).
6
MSTEN
Master Mode Enable.
0: Disable master mode. Operate in slave mode.
1: Enable master mode. Operate as a master.
5
CKPHA
SPI0 Clock Phase.
0: Data centered on first edge of SCK period.*
1: Data centered on second edge of SCK period.*
4
CKPOL
SPI0 Clock Polarity.
0: SCK line low in idle state.
1: SCK line high in idle state.
3
SLVSEL
2
NSSIN
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Slave Selected Flag.
This bit is set to logic 1 whenever the NSS pin is low indicating SPI0 is the selected
slave. It is cleared to logic 0 when NSS is high (slave not selected). This bit does
not indicate the instantaneous value at the NSS pin, but rather a de-glitched version of the pin input.
NSS Instantaneous Pin Input.
This bit mimics the instantaneous value that is present on the NSS port pin at the
time that the register is read. This input is not de-glitched.
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RXBMT
Shift Register Empty (valid in slave mode only).
This bit will be set to logic 1 when all data has been transferred in/out of the shift
register, and there is no new information available to read from the transmit buffer
or write to the receive buffer. It returns to logic 0 when a data byte is transferred to
the shift register from the transmit buffer or by a transition on SCK. SRMT = 1 when
in Master Mode.
Receive Buffer Empty (valid in slave mode only).
This bit will be set to logic 1 when the receive buffer has been read and contains no
new information. If there is new information available in the receive buffer that has
not been read, this bit will return to logic 0. RXBMT = 1 when in Master Mode.
Note: In slave mode, data on MOSI is sampled in the center of each data bit. In master mode, data on MISO is
sampled one SYSCLK before the end of each data bit, to provide maximum settling time for the slave device.
See Table 25.1 for timing parameters.
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5
4
3
Name
SPIF
WCOL
MODF
RXOVRN
Type
R/W
R/W
R/W
R/W
Reset
0
0
0
0
2
1
0
NSSMD[1:0]
TXBMT
SPIEN
R/W
R
R/W
1
0
0
SFR Address = 0xF8; Bit-Addressable
Bit
Name
Function
1
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SFR Definition 25.2. SPI0CN: SPI0 Control
SPIF
SPI0 Interrupt Flag.
This bit is set to logic 1 by hardware at the end of a data transfer. If SPI interrupts
are enabled, an interrupt will be generated. This bit is not automatically cleared by
hardware, and must be cleared by software.
6
WCOL
Write Collision Flag.
This bit is set to logic 1 if a write to SPI0DAT is attempted when TXBMT is 0. When
this occurs, the write to SPI0DAT will be ignored, and the transmit buffer will not be
written. If SPI interrupts are enabled, an interrupt will be generated. This bit is not
automatically cleared by hardware, and must be cleared by software.
5
MODF
Mode Fault Flag.
This bit is set to logic 1 by hardware when a master mode collision is detected
(NSS is low, MSTEN = 1, and NSSMD[1:0] = 01). If SPI interrupts are enabled, an
interrupt will be generated. This bit is not automatically cleared by hardware, and
must be cleared by software.
4
RXOVRN
3:2
NSSMD[1:0]
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0
Slave Select Mode.
Selects between the following NSS operation modes:
(See Section 25.2 and Section 25.3).
00: 3-Wire Slave or 3-Wire Master Mode. NSS signal is not routed to a port pin.
01: 4-Wire Slave or Multi-Master Mode (Default). NSS is an input to the device.
1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from the
device and will assume the value of NSSMD0.
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1
Receive Overrun Flag (valid in slave mode only).
This bit is set to logic 1 by hardware when the receive buffer still holds unread data
from a previous transfer and the last bit of the current transfer is shifted into the
SPI0 shift register. If SPI interrupts are enabled, an interrupt will be generated. This
bit is not automatically cleared by hardware, and must be cleared by software.
TXBMT
Transmit Buffer Empty.
This bit will be set to logic 0 when new data has been written to the transmit buffer.
When data in the transmit buffer is transferred to the SPI shift register, this bit will
be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer.
SPIEN
SPI0 Enable.
0: SPI disabled.
1: SPI enabled.
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6
5
4
Name
SCR[7:0]
Type
R/W
0
0
0
0
SFR Address = 0xA2
Bit
Name
7:0
SCR[7:0]
2
0
0
1
0
0
0
Function
SPI0 Clock Rate.
These bits determine the frequency of the SCK output when the SPI0 module is
configured for master mode operation. The SCK clock frequency is a divided version of the system clock, and is given in the following equation, where SYSCLK is
the system clock frequency and SPI0CKR is the 8-bit value held in the SPI0CKR
register.
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