C8051F85x/86x
Low-Cost 8-bit MCU Family with up to 8 kB of Flash
Memory
- Up to 8 kB flash
- Flash is in-system programmable in 512-Byte sectors
- Up to 512 Bytes RAM (256 + 256)
On-Chip Debug
- On-chip debug circuitry facilitates full speed, non-intrusive in-
12-Bit Analog-to-Digital Converter
- Up to 16 input channels
- Up to 200 ksps 12-bit mode or 800 ksps 10-bit mode
- Internal VREF or external VREF supported
Timer/Counters and PWM
- 4 General-Purpose 16-bit Timer/Counters
- 16-bit Programmable Counter Array (PCA) with three channels
of PWM, capture/compare, or frequency output capability, and
hardware kill/safe state capability
Internal Low-Power Oscillator
- Calibrated to 24.5 MHz
- Low supply current
- ±2% accuracy over supply and temperature
Additional Support Peripherals
- Independent watchdog timer clocked from LFO
- 16-bit CRC engine
Internal Low-Frequency Oscillator
- 80 kHz nominal operation
- Low supply current
- Independent clock source for watchdog timer
Unique Identifier
- 32-bit unique key for each device
Supply Voltage
- 2.2 to 3.6 V
2 Analog Comparators
- Programmable hysteresis and response time
- Configurable as interrupt or reset source
- Low current
Package Options
- 16-pin SOIC
- 20-pin QFN, 3 x 3 mm
- 24-pin QSOP
- Available in die form
- Qualified to AEC-Q100 Standards
General-Purpose I/O
- Up to 18 pins
- 5 V-Tolerant
- Crossbar-enabled
Temperature Ranges:
- –40 to +125 °C (-Ix) and –40 to +85 °C (-Gx)
256-512 B RAM
Core LDO
CIP-51
(25 MHz)
Watchdog
UART
I2C / SMBus
Supply Monitor
16-bit CRC
4 x 16-bit Timers
24.5 MHz Low Power Oscillator
80 kHz Low Frequency Oscillator
External Clock (CMOS Input)
3-Channel PCA
Clock Selection
C2 Serial Debug / Programming
Clocking / Oscillators
SPI
Analog Peripherals
SAR ADC
(12-bit 200 ksps,10-bit 800 ksps)
Voltage Reference
2 x Low Current Comparators
Copyright © 2018 by Silicon Laboratories
18 Multi-Function 5V-Tolerant I/O Pins
2-8 kB Flash
Digital Peripherals
Priority Crossbar
Encoder
Core / Memory / Support
Rev. 1.1 11/18
Communication Peripherals
- UART
- I2C / SMBus™
- SPI™
Flexible Pin Muxing
-
system debug (no emulator required)
Provides breakpoints, single stepping, inspect/modify memory
and registers
High-Speed CIP-51 µC Core
- Efficient, pipelined instruction architecture
- Up to 25 MIPS throughput with 25 MHz clock
- Uses standard 8051 instruction set
- Expanded interrupt handler
C8051F85x/86x
C8051F85x-86x
Table of Contents
1. Electrical Specifications............................................................................................ 8
1.1. Electrical Characteristics ..................................................................................... 8
1.2. Typical Performance Curves ............................................................................. 19
1.2.1. Operating Supply Current ......................................................................... 19
1.2.2. ADC Supply Current.................................................................................. 20
1.2.3. Port I/O Output Drive................................................................................. 21
1.3. Thermal Conditions ........................................................................................... 21
1.4. Absolute Maximum Ratings............................................................................... 22
2. System Overview ..................................................................................................... 23
2.1. Power ............................................................................................................ 25
2.1.1. LDO ....................................................................................................... 25
2.1.2. Voltage Supply Monitor (VMON0)............................................................. 25
2.1.3. Device Power Modes ................................................................................ 25
2.2. I/O
............................................................................................................ 26
2.2.1. General Features ...................................................................................... 26
2.2.2. Crossbar.................................................................................................... 26
2.3. Clocking ............................................................................................................ 27
2.4. Counters/Timers and PWM ............................................................................... 27
2.4.1. Programmable Counter Array (PCA0) ...................................................... 27
2.4.2. Timers (Timer 0, Timer 1, Timer 2 and Timer 3) ....................................... 27
2.4.3. Watchdog Timer (WDT0) .......................................................................... 27
2.5. Communications and other Digital Peripherals ................................................. 28
2.5.1. Universal Asynchronous Receiver/Transmitter (UART0).......................... 28
2.5.2. Serial Peripheral Interface (SPI0) ............................................................. 28
2.5.3. System Management Bus / I2C (SMBus0) ............................................... 28
2.5.4. 16/32-bit CRC (CRC0) .............................................................................. 28
2.6. Analog Peripherals ............................................................................................ 30
2.6.1. 12-Bit Analog-to-Digital Converter (ADC0) ............................................... 30
2.6.2. Low Current Comparators (CMP0, CMP1) ............................................... 30
2.7. Reset Sources ................................................................................................... 31
2.8. On-Chip Debugging........................................................................................... 31
3. Pin Definitions.......................................................................................................... 32
3.1. C8051F850/1/2/3/4/5 QSOP24 Pin Definitions ................................................. 32
3.2. C8051F850/1/2/3/4/5 QFN20 Pin Definitions .................................................... 36
3.3. C8051F860/1/2/3/4/5 SOIC16 Pin Definitions ................................................... 39
4. Ordering Information ............................................................................................... 42
5. QSOP-24 Package Specifications .......................................................................... 45
6. QFN-20 Package Specifications ............................................................................. 47
7. SOIC-16 Package Specifications ............................................................................ 50
8. Memory Organization .............................................................................................. 52
8.1. Program Memory............................................................................................... 53
8.1.1. MOVX Instruction and Program Memory .................................................. 53
8.2. Data Memory ..................................................................................................... 53
2
Rev. 1. 1
C8051F85x-86x
8.2.1. Internal RAM ............................................................................................. 53
8.2.2. External RAM ............................................................................................ 54
8.2.3. Special Function Registers ....................................................................... 55
9. Special Function Register Memory Map................................................................ 56
10. Flash Memory......................................................................................................... 61
10.1. Security Options .............................................................................................. 61
10.2. Programming the Flash Memory ..................................................................... 63
10.2.1. Flash Lock and Key Functions ................................................................ 63
10.2.2. Flash Erase Procedure ........................................................................... 63
10.2.3. Flash Write Procedure ............................................................................ 63
10.3. Non-Volatile Data Storage............................................................................... 64
10.4. Flash Write and Erase Guidelines ................................................................... 64
10.4.1. Voltage Supply Maintenance and the Supply Monitor ............................ 64
10.4.2. PSWE Maintenance ................................................................................ 65
10.4.3. System Clock .......................................................................................... 65
10.5. Flash Control Registers ................................................................................... 66
11. Device Identification and Unique Identifier ......................................................... 68
11.1. Device Identification Registers ........................................................................ 69
12. Interrupts ................................................................................................................ 72
12.1. MCU Interrupt Sources and Vectors................................................................ 72
12.1.1. Interrupt Priorities.................................................................................... 72
12.1.2. Interrupt Latency ..................................................................................... 72
12.2. Interrupt Control Registers .............................................................................. 75
13. Power Management and Internal Regulator ........................................................ 82
13.1. Power Modes................................................................................................... 82
13.1.1. Idle Mode ................................................................................................ 82
13.1.2. Stop Mode............................................................................................... 83
13.2. LDO Regulator................................................................................................. 83
13.3. Power Control Registers.................................................................................. 83
13.4. LDO Control Registers .................................................................................... 84
14. Analog-to-Digital Converter (ADC0)..................................................................... 85
14.1. ADC0 Analog Multiplexer ................................................................................ 86
14.2. ADC Operation ................................................................................................ 88
14.2.1. Starting a Conversion.............................................................................. 88
14.2.2. Tracking Modes....................................................................................... 88
14.2.3. Burst Mode.............................................................................................. 89
14.2.4. Settling Time Requirements.................................................................... 90
14.2.5. Gain Setting ............................................................................................ 91
14.3. 8-Bit Mode ....................................................................................................... 91
14.4. 12-Bit Mode ..................................................................................................... 91
14.5. Power Considerations ..................................................................................... 92
14.6. Output Code Formatting .................................................................................. 94
14.7. Programmable Window Detector..................................................................... 95
14.7.1. Window Detector In Single-Ended Mode ................................................ 95
14.8. Voltage and Ground Reference Options ......................................................... 97
Rev. 1. 1
3
C8051F85x-86x
14.8.1. External Voltage Reference .................................................................... 97
14.8.2. Internal Voltage Reference ..................................................................... 97
14.8.3. Analog Ground Reference ...................................................................... 97
14.9. Temperature Sensor........................................................................................ 98
14.9.1. Calibration ............................................................................................... 98
14.10. ADC Control Registers .................................................................................. 99
15. CIP-51 Microcontroller Core ............................................................................... 113
15.1. Performance .................................................................................................. 113
15.2. Programming and Debugging Support .......................................................... 114
15.3. Instruction Set................................................................................................ 114
15.3.1. Instruction and CPU Timing .................................................................. 114
15.4. CPU Core Registers ...................................................................................... 119
16. Clock Sources and Selection (HFOSC0, LFOSC0, and EXTCLK).................... 125
16.1. Programmable High-Frequency Oscillator .................................................... 125
16.2. Programmable Low-Frequency Oscillator ..................................................... 125
16.2.1. Calibrating the Internal L-F Oscillator.................................................... 125
16.3. External Clock ............................................................................................... 126
16.4. Clock Selection.............................................................................................. 126
16.5. High Frequency Oscillator Control Registers ................................................ 127
16.6. Low Frequency Oscillator Control Registers ................................................. 128
16.7. Clock Selection Control Registers ................................................................. 129
17. Comparators (CMP0 and CMP1)......................................................................... 130
17.1. System Connectivity ...................................................................................... 130
17.2. Functional Description ................................................................................... 133
17.3. Comparator Control Registers....................................................................... 134
18. Cyclic Redundancy Check Unit (CRC0)............................................................. 140
18.1. CRC Algorithm............................................................................................... 140
18.2. Preparing for a CRC Calculation ................................................................... 142
18.3. Performing a CRC Calculation ...................................................................... 142
18.4. Accessing the CRC0 Result .......................................................................... 142
18.5. CRC0 Bit Reverse Feature............................................................................ 142
18.6. CRC Control Registers .................................................................................. 143
19. External Interrupts (INT0 and INT1).................................................................... 149
19.1. External Interrupt Control Registers .............................................................. 150
20. Programmable Counter Array (PCA0)................................................................ 152
20.1. PCA Counter/Timer ....................................................................................... 153
20.2. PCA0 Interrupt Sources................................................................................. 153
20.3. Capture/Compare Modules ........................................................................... 154
20.3.1. Output Polarity ...................................................................................... 154
20.3.2. Edge-Triggered Capture Mode ............................................................. 155
20.3.3. Software Timer (Compare) Mode.......................................................... 156
20.3.4. High-Speed Output Mode ..................................................................... 157
20.3.5. Frequency Output Mode ....................................................................... 158
20.4. PWM Waveform Generation.......................................................................... 159
20.4.1. Edge Aligned PWM ............................................................................... 159
4
Rev. 1. 1
C8051F85x-86x
20.4.2. Center Aligned PWM............................................................................. 161
20.4.3. 8 to11-bit Pulse Width Modulator Modes ............................................. 163
20.4.4. 16-Bit Pulse Width Modulator Mode..................................................... 164
20.5. Comparator Clear Function ........................................................................... 165
20.6. PCA Control Registers .................................................................................. 167
21. Port I/O (Port 0, Port 1, Port 2, Crossbar, and Port Match) .............................. 184
21.1. General Port I/O Initialization......................................................................... 185
21.2. Assigning Port I/O Pins to Analog and Digital Functions............................... 186
21.2.1. Assigning Port I/O Pins to Analog Functions ........................................ 186
21.2.2. Assigning Port I/O Pins to Digital Functions.......................................... 186
21.2.3. Assigning Port I/O Pins to Fixed Digital Functions................................ 187
21.3. Priority Crossbar Decoder ............................................................................. 188
21.4. Port I/O Modes of Operation.......................................................................... 191
21.4.1. Configuring Port Pins For Analog Modes.............................................. 191
21.4.2. Configuring Port Pins For Digital Modes ............................................... 191
21.4.3. Port Drive Strength................................................................................ 192
21.5. Port Match ..................................................................................................... 192
21.6. Direct Read/Write Access to Port I/O Pins .................................................... 192
21.7. Port I/O and Pin Configuration Control Registers.......................................... 193
22. Reset Sources and Supply Monitor ................................................................... 211
22.1. Power-On Reset ............................................................................................ 212
22.2. Power-Fail Reset / Supply Monitor ................................................................ 213
22.3. Enabling the VDD Monitor ............................................................................. 213
22.4. External Reset ............................................................................................... 214
22.5. Missing Clock Detector Reset ....................................................................... 214
22.6. Comparator0 Reset ....................................................................................... 214
22.7. Watchdog Timer Reset.................................................................................. 214
22.8. Flash Error Reset .......................................................................................... 214
22.9. Software Reset .............................................................................................. 214
22.10. Reset Sources Control Registers ................................................................ 215
22.11. Supply Monitor Control Registers................................................................ 216
23. Serial Peripheral Interface (SPI0) ....................................................................... 217
23.1. Signal Descriptions........................................................................................ 218
23.1.1. Master Out, Slave In (MOSI)................................................................. 218
23.1.2. Master In, Slave Out (MISO)................................................................. 218
23.1.3. Serial Clock (SCK) ................................................................................ 218
23.1.4. Slave Select (NSS) ............................................................................... 218
23.2. SPI0 Master Mode Operation ........................................................................ 219
23.3. SPI0 Slave Mode Operation .......................................................................... 221
23.4. SPI0 Interrupt Sources .................................................................................. 221
23.5. Serial Clock Phase and Polarity .................................................................... 221
23.6. SPI Special Function Registers ..................................................................... 223
23.7. SPI Control Registers .................................................................................... 227
24. System Management Bus / I2C (SMBus0) ......................................................... 233
24.1. Supporting Documents .................................................................................. 234
Rev. 1. 1
5
C8051F85x-86x
24.2. SMBus Configuration..................................................................................... 234
24.3. SMBus Operation .......................................................................................... 234
24.3.1. Transmitter vs. Receiver ....................................................................... 235
24.3.2. Arbitration.............................................................................................. 235
24.3.3. Clock Low Extension............................................................................. 235
24.3.4. SCL Low Timeout.................................................................................. 235
24.3.5. SCL High (SMBus Free) Timeout ......................................................... 236
24.4. Using the SMBus........................................................................................... 236
24.4.1. SMBus Configuration Register.............................................................. 236
24.4.2. SMBus Pin Swap .................................................................................. 238
24.4.3. SMBus Timing Control .......................................................................... 238
24.4.4. SMB0CN Control Register .................................................................... 238
24.4.5. Hardware Slave Address Recognition .................................................. 240
24.4.6. Data Register ........................................................................................ 241
24.5. SMBus Transfer Modes................................................................................. 242
24.5.1. Write Sequence (Master) ...................................................................... 242
24.5.2. Read Sequence (Master) ...................................................................... 243
24.5.3. Write Sequence (Slave) ........................................................................ 244
24.5.4. Read Sequence (Slave) ........................................................................ 245
24.6. SMBus Status Decoding................................................................................ 245
24.7. I2C / SMBus Control Registers...................................................................... 251
25. Timers (Timer0, Timer1, Timer2 and Timer3) .................................................... 259
25.1. Timer 0 and Timer 1 ...................................................................................... 261
25.1.1. Mode 0: 13-bit Counter/Timer ............................................................... 262
25.1.2. Mode 1: 16-bit Counter/Timer ............................................................... 263
25.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload..................................... 264
25.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................ 265
25.2. Timer 2 and Timer 3 ...................................................................................... 266
25.2.1. 16-bit Timer with Auto-Reload............................................................... 266
25.2.2. 8-bit Timers with Auto-Reload............................................................... 267
25.2.3. Capture Mode ....................................................................................... 268
25.3. Timer Control Registers................................................................................. 269
26. Universal Asynchronous Receiver/Transmitter (UART0) ................................ 289
26.1. Enhanced Baud Rate Generation.................................................................. 289
26.2. Operational Modes ........................................................................................ 291
26.2.1. 8-Bit UART ............................................................................................ 291
26.2.2. 9-Bit UART ............................................................................................ 292
26.3. Multiprocessor Communications ................................................................... 293
26.4. UART Control Registers ................................................................................ 295
27. Watchdog Timer (WDT0) ..................................................................................... 298
27.1. Features ........................................................................................................ 298
27.2. Enabling / Resetting the WDT ....................................................................... 299
27.3. Disabling the WDT......................................................................................... 299
27.4. Disabling the WDT Lockout ........................................................................... 299
27.5. Setting the WDT Interval ............................................................................... 299
6
Rev. 1. 1
C8051F85x-86x
27.6. Synchronization ............................................................................................. 300
27.7. Watchdog Timer Control Registers ............................................................... 301
28. Revision-Specific Behavior................................................................................. 303
28.1. Revision Identification.................................................................................... 303
28.2. Temperature Sensor Offset and Slope.......................................................... 305
28.3. Flash Endurance ........................................................................................... 305
28.4. Latch-Up Performance .................................................................................. 305
28.5. Unique Identifier ............................................................................................ 305
29. C2 Interface .......................................................................................................... 306
29.1. C2 Pin Sharing .............................................................................................. 306
29.2. C2 Interface Registers................................................................................... 307
Document Change List.............................................................................................. 312
Rev. 1. 1
7
C8051F85x/86x
1. Electrical Specifications
1.1. Electrical Characteristics
All electrical parameters in all tables are specified under the conditions listed in Table 1.1, unless stated
otherwise.
Table 1.1. Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
VDD
2.2
—
3.6
V
fSYSCLK
0
—
25
MHz
Commercial Grade Devices
(-GM, -GS, -GU)
–40
—
85
°C
Industrial Grade Devices
(-IM, -IS, -IU)
–40
—
125
°C
Operating Supply Voltage on VDD
System Clock Frequency
Operating Ambient Temperature
TA
Test Condition
Note: All voltages with respect to GND
Table 1.2. Power Consumption
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
FSYSCLK = 24.5 MHz2
—
4.45
4.85
mA
2
—
915
1150
A
FSYSCLK = 80 kHz3, TA = 25 °C
—
250
290
A
FSYSCLK = 80 kHz3
—
250
380
A
FSYSCLK = 24.5 MHz2
—
2.05
2.3
mA
2
—
550
700
A
FSYSCLK = 80 kHz3, TA = 25 °C
—
125
130
A
FSYSCLK = 80 kHz3
—
125
200
A
Internal LDO ON, TA = 25 °C
—
105
120
A
Internal LDO ON
—
105
170
A
Internal LDO OFF
—
0.2
—
A
Digital Core Supply Current (–Gx Devices, -40°C to +85°C)
Normal Mode—Full speed
with code executing from flash
Idle Mode—Core halted with
peripherals running
Stop Mode—Core halted and
all clocks stopped, Supply
monitor off.
IDD
FSYSCLK = 1.53 MHz
IDD
FSYSCLK = 1.53 MHz
IDD
Notes:
1. Currents are additive. For example, where IDD is specified and the mode is not mutually exclusive, enabling the
functions increases supply current by the specified amount.
2. Includes supply current from internal regulator, supply monitor, and High Frequency Oscillator.
3. Includes supply current from internal regulator, supply monitor, and Low Frequency Oscillator.
4. ADC0 always-on power excludes internal reference supply current.
5. The internal reference is enabled as-needed when operating the ADC in burst mode to save power.
8
Rev. 1.1
C8051F85x/86x
Table 1.2. Power Consumption (Continued)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
FSYSCLK = 24.5 MHz2
—
4.45
5.25
mA
FSYSCLK = 1.53 MHz2
—
915
1600
A
FSYSCLK = 80 kHz , TA = 25 °C
—
250
290
A
FSYSCLK = 80 kHz3
—
250
725
A
FSYSCLK = 24.5 MHz2
—
2.05
2.6
mA
FSYSCLK = 1.53 MHz2
—
550
1000
A
FSYSCLK = 80 kHz , TA = 25 °C
—
125
130
A
FSYSCLK = 80 kHz3
—
125
550
A
Internal LDO ON, TA = 25 °C
—
105
120
A
Internal LDO ON
—
105
270
A
Internal LDO OFF
—
0.2
—
A
Digital Core Supply Current (–Ix Devices, -40°C to +125°C)
Normal Mode—Full speed
with code executing from flash
IDD
3
Idle Mode—Core halted with
peripherals running
IDD
3
Stop Mode—Core halted and
all clocks stopped, Supply
monitor off.
IDD
Analog Peripheral Supply Currents (Both –Gx and –Ix Devices)
High-Frequency Oscillator
IHFOSC
Operating at 24.5 MHz,
TA = 25 °C
—
155
—
µA
Low-Frequency Oscillator
ILFOSC
Operating at 80 kHz,
TA = 25 °C
—
3.5
—
µA
IADC
800 ksps, 10-bit conversions or
200 ksps, 12-bit conversions
Normal bias settings
VDD = 3.0 V
—
845
1200
µA
250 ksps, 10-bit conversions or
62.5 ksps 12-bit conversions
Low power bias settings
VDD = 3.0 V
—
425
580
µA
200 ksps, VDD = 3.0 V
—
370
—
µA
100 ksps, VDD = 3.0 V
—
185
—
µA
10 ksps, VDD = 3.0 V
—
19
—
µA
ADC0 Always-on4
ADC0 Burst Mode, 10-bit single conversions, external reference
IADC
Notes:
1. Currents are additive. For example, where IDD is specified and the mode is not mutually exclusive, enabling the
functions increases supply current by the specified amount.
2. Includes supply current from internal regulator, supply monitor, and High Frequency Oscillator.
3. Includes supply current from internal regulator, supply monitor, and Low Frequency Oscillator.
4. ADC0 always-on power excludes internal reference supply current.
5. The internal reference is enabled as-needed when operating the ADC in burst mode to save power.
Rev. 1.1
9
C8051F85x/86x
Table 1.2. Power Consumption (Continued)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
ADC0 Burst Mode, 10-bit single conversions, internal reference, Low power bias
settings
IADC
200 ksps, VDD = 3.0 V
—
490
—
µA
100 ksps, VDD = 3.0 V
—
245
—
µA
10 ksps, VDD = 3.0 V
—
23
—
µA
ADC0 Burst Mode, 12-bit single conversions, external reference
IADC
100 ksps, VDD = 3.0 V
—
530
—
µA
50 ksps, VDD = 3.0 V
—
265
—
µA
10 ksps, VDD = 3.0 V
—
53
—
µA
100 ksps, VDD = 3.0 V,
Normal bias
—
950
—
µA
50 ksps, VDD = 3.0 V,
Low power bias
—
420
—
µA
10 ksps, VDD = 3.0 V,
Low power bias
—
85
—
µA
Normal Power Mode
—
680
790
µA
Low Power Mode
—
160
210
µA
—
75
120
µA
CPnMD = 11
—
0.5
—
µA
CPnMD = 10
—
3
—
µA
CPnMD = 01
—
10
—
µA
CPnMD = 00
—
25
—
µA
—
15
20
µA
ADC0 Burst Mode, 12-bit single conversions, internal reference
Internal ADC0 Reference,
Always-on5
Temperature Sensor
Comparator 0 (CMP0),
Comparator 1 (CMP1)
Voltage Supply Monitor
(VMON0)
IADC
IIREF
ITSENSE
ICMP
IVMON
Notes:
1. Currents are additive. For example, where IDD is specified and the mode is not mutually exclusive, enabling the
functions increases supply current by the specified amount.
2. Includes supply current from internal regulator, supply monitor, and High Frequency Oscillator.
3. Includes supply current from internal regulator, supply monitor, and Low Frequency Oscillator.
4. ADC0 always-on power excludes internal reference supply current.
5. The internal reference is enabled as-needed when operating the ADC in burst mode to save power.
10
Rev. 1.1
C8051F85x/86x
Table 1.3. Reset and Supply Monitor
Parameter
VDD Supply Monitor Threshold
Power-On Reset (POR) Threshold
Symbol
Test Condition
Min
Typ
Max
Unit
1.85
1.95
2.1
V
Rising Voltage on VDD
—
1.4
—
V
Falling Voltage on VDD
0.75
—
1.36
V
VVDDM
VPOR
VDD Ramp Time
tRMP
Time to VDD > 2.2 V
10
—
—
µs
Reset Delay from POR
tPOR
Relative to VDD >
VPOR
3
10
31
ms
Reset Delay from non-POR source
tRST
Time between release
of reset source and
code execution
—
39
—
µs
RST Low Time to Generate Reset
tRSTL
15
—
—
µs
Missing Clock Detector Response
Time (final rising edge to reset)
tMCD
—
0.625
1.2
ms
Missing Clock Detector Trigger
Frequency
FMCD
—
7.5
13.5
kHz
VDD Supply Monitor Turn-On Time
tMON
—
2
—
µs
FSYSCLK > 1 MHz
Table 1.4. Flash Memory
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
tWRITE
One Byte,
FSYSCLK = 24.5 MHz
19
20
21
µs
Erase Time1,2
tERASE
One Page,
FSYSCLK = 24.5 MHz
5.2
5.35
5.5
ms
VDD Voltage During Programming3
VPROG
2.2
—
3.6
V
NWE
20k
100k
—
Cycles
Write Time
1,2
Endurance (Write/Erase Cycles)
Notes:
1. Does not include sequencing time before and after the write/erase operation, which may be multiple SYSCLK cycles.
2. The internal High-Frequency Oscillator has a programmable output frequency using the OSCICL register, which is
factory programmed to 24.5 MHz. If user firmware adjusts the oscillator speed, it must be between 22 and 25 MHz
during any flash write or erase operation. It is recommended to write the OSCICL register back to its reset value when
writing or erasing flash.
3. Flash can be safely programmed at any voltage above the supply monitor threshold (VVDDM).
4. Data Retention Information is published in the Quarterly Quality and Reliability Report.
Rev. 1.1
11
C8051F85x/86x
Table 1.5. Internal Oscillators
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
fHFOSC
Full Temperature and
Supply Range
24
24.5
25
MHz
Power Supply Sensitivity
PSSHFOSC
TA = 25 °C
—
0.5
—
%/V
Temperature Sensitivity
TSHFOSC
VDD = 3.0 V
—
40
—
ppm/°C
fLFOSC
Full Temperature and
Supply Range
75
80
85
kHz
Power Supply Sensitivity
PSSLFOSC
TA = 25 °C
—
0.05
—
%/V
Temperature Sensitivity
TSLFOSC
VDD = 3.0 V
—
65
—
ppm/°C
Test Condition
Min
Typ
Max
Unit
High Frequency Oscillator (24.5 MHz)
Oscillator Frequency
Low Frequency Oscillator (80 kHz)
Oscillator Frequency
Table 1.6. External Clock Input
Parameter
Symbol
External Input CMOS Clock
Frequency (at EXTCLK pin)
fCMOS
0
—
25
MHz
External Input CMOS Clock High Time
tCMOSH
18
—
—
ns
External Input CMOS Clock Low Time
tCMOSL
18
—
—
ns
12
Rev. 1.1
C8051F85x/86x
Table 1.7. ADC
Parameter
Resolution
Symbol
Test Condition
Nbits
12 Bit Mode
12
Bits
10 Bit Mode
10
Bits
Throughput Rate
(High Speed Mode)
fS
Throughput Rate
(Low Power Mode)
fS
Tracking Time
tTRK
Power-On Time
tPWR
SAR Clock Frequency
fSAR
Min
Typ
Max
Unit
12 Bit Mode
—
—
200
ksps
10 Bit Mode
—
—
800
ksps
12 Bit Mode
—
—
62.5
ksps
10 Bit Mode
—
—
250
ksps
High Speed Mode
230
—
—
ns
Low Power Mode
450
—
—
ns
1.2
—
—
µs
High Speed Mode,
Reference is 2.4 V internal
—
—
6.25
MHz
High Speed Mode,
Reference is not 2.4 V internal
—
—
12.5
MHz
Low Power Mode
—
—
4
MHz
Conversion Time
tCNV
10-Bit Conversion,
SAR Clock = 12.25 MHz,
System Clock = 24.5 MHz.
1.1
µs
Sample/Hold Capacitor
CSAR
Gain = 1
—
5
—
pF
Gain = 0.5
—
2.5
—
pF
Input Pin Capacitance
CIN
—
20
—
pF
Input Mux Impedance
RMUX
—
550
—
Voltage Reference Range
VREF
1
—
VDD
V
Gain = 1
0
—
VREF
V
Gain = 0.5
0
—
2xVREF
V
—
70
—
dB
12 Bit Mode
—
±1
±2.3
LSB
10 Bit Mode
—
±0.2
±0.6
LSB
12 Bit Mode
–1
±0.7
1.9
LSB
10 Bit Mode
—
±0.2
±0.6
LSB
Input Voltage Range*
Power Supply Rejection
Ratio
VIN
PSRRADC
DC Performance
Integral Nonlinearity
Differential Nonlinearity
(Guaranteed Monotonic)
INL
DNL
*Note: Absolute input pin voltage is limited by the VDD supply.
Rev. 1.1
13
C8051F85x/86x
Table 1.7. ADC (Continued)
Parameter
Offset Error
Offset Temperature Coefficient
Slope Error
Symbol
Test Condition
Min
Typ
Max
Unit
EOFF
12 Bit Mode, VREF = 1.65 V
–3
0
3
LSB
10 Bit Mode, VREF = 1.65 V
–2
0
2
LSB
—
0.004
—
LSB/°C
12 Bit Mode
—
±0.02
±0.1
%
10 Bit Mode
—
±0.06
±0.24
%
TCOFF
EM
Dynamic Performance 10 kHz Sine Wave Input 1dB below full scale, Max throughput, using AGND pin
Signal-to-Noise
Signal-to-Noise Plus Distortion
Total Harmonic Distortion
(Up to 5th Harmonic)
Spurious-Free Dynamic
Range
SNR
SNDR
THD
SFDR
12 Bit Mode
61
66
—
dB
10 Bit Mode
53
60
—
dB
12 Bit Mode
61
66
—
dB
10 Bit Mode
53
60
—
dB
12 Bit Mode
—
71
—
dB
10 Bit Mode
—
70
—
dB
12 Bit Mode
—
–79
—
dB
10 Bit Mode
—
–74
—
dB
*Note: Absolute input pin voltage is limited by the VDD supply.
14
Rev. 1.1
C8051F85x/86x
Table 1.8. Voltage Reference
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
VREFFS
1.65 V Setting
1.62
1.65
1.68
V
2.4 V Setting, VDD > 2.6 V
2.35
2.4
2.45
V
TCREFFS
—
50
—
ppm/°C
tREFFS
—
—
1.5
µs
PSRRREFFS
—
400
—
ppm/V
—
5
—
µA
Internal Fast Settling Reference
Output Voltage
(Full Temperature and Supply
Range)
Temperature Coefficient
Turn-on Time
Power Supply Rejection
External Reference
Input Current
IEXTREF
Sample Rate = 800 ksps;
VREF = 3.0 V
Table 1.9. Temperature Sensor
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Offset
VOFF
TA = 0 °C
—
757
—
mV
Offset Error*
EOFF
TA = 0 °C
—
17
—
mV
Slope
M
—
2.85
—
mV/°C
Slope Error*
EM
—
70
—
µV/°C
Linearity
—
0.5
—
°C
Turn-on Time
—
1.8
—
µs
*Note: Represents one standard deviation from the mean.
Rev. 1.1
15
C8051F85x/86x
Table 1.10. Comparators
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Response Time, CPnMD = 00
(Highest Speed)
tRESP0
+100 mV Differential
—
100
—
ns
–100 mV Differential
—
150
—
ns
Response Time, CPnMD = 11
(Lowest Power)
tRESP3
+100 mV Differential
—
1.5
—
µs
–100 mV Differential
—
3.5
—
µs
CPnHYP = 00
—
0.4
—
mV
CPnHYP = 01
—
8
—
mV
CPnHYP = 10
—
16
—
mV
CPnHYP = 11
—
32
—
mV
CPnHYN = 00
—
-0.4
—
mV
CPnHYN = 01
—
–8
—
mV
CPnHYN = 10
—
–16
—
mV
CPnHYN = 11
—
–32
—
mV
CPnHYP = 00
—
0.5
—
mV
CPnHYP = 01
—
6
—
mV
CPnHYP = 10
—
12
—
mV
CPnHYP = 11
—
24
—
mV
CPnHYN = 00
—
-0.5
—
mV
CPnHYN = 01
—
–6
—
mV
CPnHYN = 10
—
–12
—
mV
CPnHYN = 11
—
–24
—
mV
CPnHYP = 00
—
0.7
—
mV
CPnHYP = 01
—
4.5
—
mV
CPnHYP = 10
—
9
—
mV
CPnHYP = 11
—
18
—
mV
CPnHYN = 00
—
-0.6
—
mV
CPnHYN = 01
—
–4.5
—
mV
CPnHYN = 10
—
–9
—
mV
CPnHYN = 11
—
–18
—
mV
Positive Hysterisis
Mode 0 (CPnMD = 00)
Negative Hysterisis
Mode 0 (CPnMD = 00)
Positive Hysterisis
Mode 1 (CPnMD = 01)
Negative Hysterisis
Mode 1 (CPnMD = 01)
Positive Hysterisis
Mode 2 (CPnMD = 10)
Negative Hysterisis
Mode 2 (CPnMD = 10)
16
HYSCP+
HYSCP-
HYSCP+
HYSCP-
HYSCP+
HYSCP-
Rev. 1.1
C8051F85x/86x
Table 1.10. Comparators
Parameter
Positive Hysteresis
Mode 3 (CPnMD = 11)
Negative Hysteresis
Mode 3 (CPnMD = 11)
Symbol
Test Condition
Min
Typ
Max
Unit
HYSCP+
CPnHYP = 00
—
1.5
—
mV
CPnHYP = 01
—
4
—
mV
CPnHYP = 10
—
8
—
mV
CPnHYP = 11
—
16
—
mV
CPnHYN = 00
—
-1.5
—
mV
CPnHYN = 01
—
–4
—
mV
CPnHYN = 10
—
–8
—
mV
CPnHYN = 11
—
–16
—
mV
HYSCP-
Input Range (CP+ or CP–)
VIN
-0.25
—
VDD+0.25
V
Input Pin Capacitance
CCP
—
7.5
—
pF
Common-Mode Rejection Ratio
CMRRCP
—
70
—
dB
Power Supply Rejection Ratio
PSRRCP
—
72
—
dB
-10
0
10
mV
—
3.5
—
µV/°C
Input Offset Voltage
VOFF
Input Offset Tempco
TCOFF
TA = 25 °C
Rev. 1.1
17
C8051F85x/86x
Table 1.11. Port I/O
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output High Voltage (High Drive)
VOH
IOH = –3 mA
VDD – 0.7
—
—
V
Output Low Voltage (High Drive)
VOL
IOL = 8.5 mA
—
—
0.6
V
Output High Voltage (Low Drive)
VOH
IOH = –1 mA
VDD – 0.7
—
—
V
Output Low Voltage (Low Drive)
VOL
IOL = 1.4 mA
—
—
0.6
V
Input High Voltage
VIH
VDD – 0.6
—
—
V
Input Low Voltage
VIL
—
—
0.6
V
Pin Capacitance
CIO
—
7
—
pF
Weak Pull-Up Current
(VIN = 0 V)
IPU
VDD = 3.6
–30
–20
–10
µA
Input Leakage
(Pullups off or Analog)
ILK
GND < VIN < VDD
–1.1
—
1.1
µA
Input Leakage Current with VIN
above VDD
ILK
VDD < VIN < VDD+2.0 V
0
5
150
µA
18
Rev. 1.1
C8051F85x/86x
1.2. Typical Performance Curves
1.2.1. Operating Supply Current
5
NormalMode
4.5
IdleMode
SupplyCurrent(mA)
4
3.5
3
2.5
2
1.5
1
0.5
0
0
5
10
15
20
25
OperatingFrequency(MHz)
Figure 1.1. Typical Operating Current Running From 24.5 MHz Internal Oscillator
260
NormalMode
240
IdleMode
SupplyCurrent(μA)
220
200
180
160
140
120
100
10
20
30
40
50
60
70
80
OperatingFrequency(kHz)
Figure 1.2. Typical Operating Current Running From 80 kHz Internal Oscillator
Rev. 1.1
19
C8051F85x/86x
1.2.2. ADC Supply Current
10ͲbitBurstMode,SingleConversions
12ͲbitBurstMode,SingleConversions
1200
1200
InternalReference,NormalBias
1100
1000
InternalReference,LPBias
1000
OtherReference
900
OtherReference
900
SupplyCurrent(μA)
SupplyCurrent(μA)
InternalReference,NormalBias
1100
InternalReference,LPBias
800
700
600
500
400
800
700
600
500
400
300
300
200
200
100
100
0
0
0
50
100
150
200
250
300
0
20
SampleRate(ksps)
40
60
80
100
120
SampleRate(ksps)
Figure 1.3. Typical ADC and Internal Reference Power Consumption in Burst Mode
10ͲbitConversions,NormalBias
10ͲbitConversions,LowPowerBias
950
450
Vdd=3.6V
Vdd=3.0V
430
Vdd=2.2V
SupplyCurrent(μA)
SupplyCurrent(μA)
Vdd=3.6V
440
Vdd=3.0V
900
850
800
750
Vdd=2.2V
420
410
400
390
380
370
700
360
650
350
100
200
300
400
500
600
700
800
50
150
SampleRate(ksps)
12ͲbitConversions,NormalBias
12ͲbitConversions,LowPowerBias
950
450
Vdd=3.6V
Vdd=3.6V
440
Vdd=3.0V
900
Vdd=3.0V
430
Vdd=2.2V
SupplyCurrent(μA)
SupplyCurrent(μA)
250
SampleRate(ksps)
850
800
750
Vdd=2.2V
420
410
400
390
380
370
700
360
650
350
25
50
75
100
125
150
175
200
SampleRate(ksps)
10
20
30
40
SampleRate(ksps)
Figure 1.4. Typical ADC Power Consumption in Normal (Always-On) Mode
20
Rev. 1.1
50
60
C8051F85x/86x
1.2.3. Port I/O Output Drive
TypicalVOH vs.SourceCurrentinHighDriveMode
TypicalVOH vs.SourceCurrentinLowDriveMode
4
4
VDD=3.6V
3.5
VDD=3.6V
3.5
VDD=3.3V
VDD=2.7V
3
VDD=2.7V
3
VDD=2.2V
2.5
VDD=2.2V
2.5
VOH (V)
VOH (V)
VDD=3.3V
2
2
1.5
1.5
1
1
0.5
0.5
0
0
0
5
10
15
20
25
0
2
4
SourceCurrent(mA)
6
8
10
12
14
16
18
SourceCurrent(mA)
Figure 1.5. Typical VOH vs. Source Current
TypicalVOL vs.SinkCurrentinLowDriveMode
TypicalVOL vs.SinkCurrentinHighDriveMode
4
4
VDD=3.6V
VDD=3.6V
3.5
3.5
VDD=3.3V
3
3
VDD=2.2V
VDD=2.2V
2.5
VOL (V)
2.5
VOL (V)
VDD=3.3V
VDD=2.7V
VDD=2.7V
2
2
1.5
1.5
1
1
0.5
0.5
0
0
0
5
10
15
20
25
30
35
40
0
45
5
10
15
20
25
SinkCurrent(mA)
SinkCurrent(mA)
Figure 1.6. Typical VOL vs. Sink Current
1.3. Thermal Conditions
Table 1.12. Thermal Conditions
Parameter
Thermal Resistance*
Symbol
Test Condition
Min
Typ
Max
Unit
JA
SOIC-16 Packages
—
70
—
°C/W
QFN-20 Packages
—
60
—
°C/W
QSOP-24 Packages
—
65
—
°C/W
*Note: Thermal resistance assumes a multi-layer PCB with any exposed pad soldered to a PCB pad.
Rev. 1.1
21
C8051F85x/86x
1.4. Absolute Maximum Ratings
Stresses above those listed under Table 1.13 may cause permanent damage to the device. This is a
stress rating only and functional operation of the devices at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
For more information on the available quality and reliability data, see the Quality and Reliability Monitor
Report at http://www.silabs.com/support/quality/pages/default.aspx.
Table 1.13. Absolute Maximum Ratings
Parameter
Symbol
Test Condition
Min
Max
Unit
Ambient Temperature Under
Bias
TBIAS
–55
125
°C
Storage Temperature
TSTG
–65
150
°C
Voltage on VDD
VDD
GND–0.3
4.2
V
Voltage on I/O pins or RST
VIN
VDD > 3.3 V
GND–0.3
5.8
V
VDD < 3.3 V
GND–0.3
VDD+2.5
V
Total Current Sunk into Supply
Pin
IVDD
—
400
mA
Total Current Sourced out of
Ground Pin
IGND
400
—
mA
Current Sourced or Sunk by Any
I/O Pin or RST
IPIO
-100
100
mA
Operating Junction Temperature
TJ
Commercial Grade Devices
(-GM, -GS, -GU)
–40
105
°C
Industrial Grade Devices
(-IM, -IS, -IU)
–40
125
°C
Note: Exposure to maximum rating conditions for extended periods may affect device reliability.
22
Rev. 1.1
C8051F85x/86x
2. System Overview
The C8051F85x/86x device family are fully integrated, mixed-signal system-on-a-chip MCUs. Highlighted
features are listed below. Refer to Table 4.1 for specific product feature selection and part ordering
numbers.
Core:
Pipelined
CIP-51 Core
compatible with standard 8051 instruction set
70% of instructions execute in 1-2 clock cycles
25 MHz maximum operating frequency
Fully
Memory:
2-8
512
kB flash; in-system programmable in 512-byte sectors
bytes RAM (including 256 bytes standard 8051 RAM and 256 bytes on-chip XRAM)
Power:
Internal
low drop-out (LDO) regulator for CPU core voltage
reset circuit and brownout detectors
Power-on
I/O:
Up to 18 total multifunction I/O pins:
All
pins 5 V tolerant under bias
peripheral crossbar for peripheral routing
5 mA source, 12.5 mA sink allows direct drive of LEDs
Flexible
Clock
Sources:
Low-power
internal oscillator: 24.5 MHz ±2%
internal oscillator: 80 kHz
External CMOS clock option
Low-frequency
Timers/Counters
3-channel
and PWM:
Programmable Counter Array (PCA) supporting PWM, capture/compare and frequency output
modes
16-bit general-purpose timers
Independent watchdog timer, clocked from low frequency oscillator
4x
Communications
and Other Digital Peripherals:
UART
SPI™
I
2
C / SMBus™
CRC Unit, supporting automatic CRC of flash at 256-byte boundaries
16-bit
Analog:
12-Bit
2
Analog-to-Digital Converter (ADC)
x Low-Current Comparators
On-Chip Debugging
With on-chip power-on reset, voltage supply monitor, watchdog timer, and clock oscillator, the C8051F85x/
86x devices are truly standalone system-on-a-chip solutions. The flash memory is reprogrammable incircuit, providing non-volatile data storage and allowing field upgrades of the firmware.
The on-chip debugging interface (C2) allows non-intrusive (uses no on-chip resources), full speed, incircuit debugging using the production MCU installed in the final application. This debug logic supports
inspection and modification of memory and registers, setting breakpoints, single stepping, and run and halt
commands. All analog and digital peripherals are fully functional while debugging.
Each device is specified for 2.2 to 3.6 V operation, and are available in 20-pin QFN, 16-pin SOIC or 24-pin
QSOP packages. All package options are lead-free and RoHS compliant. The device is available in two
temperature grades: -40 to +85 °C or –40 to +125 °C. See Table 4.1 for ordering information. A block
diagram is included in Figure 2.1.
Rev. 1.1
23
C8051F85x/86x
Power On
Reset
Reset
C2CK/RST
Debug /
Programming
Hardware
Port I/O Configuration
CIP-51 8051
Controller Core
Port 0
Drivers
P0.0/VREF
P0.1/AGND
P0.2
P0.3/EXTCLK
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7
Port 1
Drivers
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Port 2
Driver
P2.0/C2D
P2.1
Digital Peripherals
8k Byte ISP Flash
Program Memory
UART
256 Byte SRAM
Timers 0,
1, 2, 3
Priority
Crossbar
Decoder
3-ch PCA
C2D
I2C /
SMBus
256 Byte XRAM
SPI
VDD
CRC
Power Net
Independent
Watchdog Timer
GND
SYSCLK
SFR
Bus
Analog Peripherals
Internal
Reference
24.5 MHz
2%
Oscillator
VDD
Low-Freq.
Oscillator
EXTCLK
Crossbar Control
12/10 bit
ADC
CMOS
Oscillator
Input
VREF
A
M
U
X
VDD
Temp
Sensor
+
-+
2 Comparators
System Clock
Configuration
Figure 2.1. C8051F85x/86x Family Block Diagram (QSOP-24 Shown)
24
Rev. 1.1
C8051F85x/86x
2.1. Power
2.1.1. LDO
The C8051F85x/86x devices include an internal regulator to regulate the supply voltage down the core
operating voltage of 1.8 V. This LDO consumes little power, but can be shut down in the power-saving Stop
mode.
2.1.2. Voltage Supply Monitor (VMON0)
The C8051F85x/86x devices include a voltage supply monitor which allows devices to function in known,
safe operating condition without the need for external hardware.
The supply monitor module includes the following features:
Holds
the device in reset if the main VDD supply drops below the VDD Reset threshold.
2.1.3. Device Power Modes
The C8051F85x/86x devices feature three low power modes in addition to normal operating mode,
allowing the designer to save power when the core is not in use. All power modes are detailed in Table 2.1.
Table 2.1. C8051F85x/86x Power Modes
Mode
Description
Normal
Core and peripherals operating
at full speed
Core
Idle
Mode Entrance
Mode Exit
Set IDLE bit in PCON
Any enabled interrupt or
reset source
Clear STOPCF in REG0MD
and
Set STOP bit in PCON
Device reset
Set STOPCF in REG0MD
and
Set STOP bit in PCON
Device reset
halted
Peripherals
operate at
full speed
All
Stop
clocks stopped
Core LDO and
(optionally)
comparators still
running
Pins retain state
All
Shutdown
clocks stopped
Core LDO and all
analog circuits shut
down
Pins retain state
In addition, the user may choose to lower the clock speed in Normal and Idle modes to save power when
the CPU requirements allow for lower speed.
Rev. 1.1
25
C8051F85x/86x
2.1.3.1. Normal Mode
Normal mode encompasses the typical full-speed operation. The power consumption of the device in this
mode will vary depending on the system clock speed and any analog peripherals that are enabled.
2.1.3.2. Idle Mode
Setting the IDLE bit in PCON causes the hardware to halt the CPU and enter idle mode as soon as the
instruction that sets the bit completes execution. All internal registers and memory maintain their original
data. All analog and digital peripherals can remain active during idle mode.
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an
enabled interrupt will cause the IDLE bit to be cleared and the CPU to resume operation. The pending
interrupt will be serviced and the next instruction to be executed after the return from interrupt (RETI) will
be the instruction immediately following the one that set the Idle Mode Select bit. If Idle mode is terminated
by an internal or external reset, the CIP-51 performs a normal reset sequence and begins program
execution at address 0x0000.
2.1.3.3. Stop Mode (Regulator On)
Setting the STOP bit in PCON when STOPCF in REG0CN is clear causes the controller core to enter stop
mode as soon as the instruction that sets the bit completes execution. In stop mode the internal oscillator,
CPU, and all digital peripherals are stopped. Each analog peripheral may be shut down individually prior to
entering stop mode. Stop mode can only be terminated by an internal or external reset.
2.1.3.4. Shutdown Mode (Regulator Off)
Shutdown mode is an extension of the normal stop mode operation. Setting the STOP bit in PCON when
STOPCF in REG0CN is also set causes the controller core to enter shutdown mode as soon as the
instruction that sets the bit completes execution, and then the internal regulator is powered down. In
shutdown mode, all core functions, memories and peripherals are powered off. An external pin reset or
power-on reset is required to exit shutdown mode.
2.2. I/O
2.2.1. General Features
The C8051F85x/86x ports have the following features:
Push-pull
or open-drain output modes and analog or digital modes.
Port Match allows the device to recognize a change on a port pin value and wake from idle mode
or generate an interrupt.
Internal pull-up resistors can be globally enabled or disabled.
Two external interrupts provide unique interrupt vectors for monitoring time-critical events.
Above-rail tolerance allows 5 V interface when device is powered.
2.2.2. Crossbar
The C8051F85x/86x devices have a digital peripheral crossbar with the following features:
Flexible
peripheral assignment to port pins.
Pins can be individually skipped to move peripherals as needed for design or layout
considerations.
The crossbar has a fixed priority for each I/O function and assigns these functions to the port pins. When a
digital resource is selected, the least-significant unassigned port pin is assigned to that resource. If a port
pin is assigned, the crossbar skips that pin when assigning the next selected resource. Additionally, the
crossbar will skip port pins whose associated bits in the PnSKIP registers are set. This provides some
flexibility when designing a system: pins involved with sensitive analog measurements can be moved away
from digital I/O and peripherals can be moved around the chip as needed to ease layout constraints.
26
Rev. 1.1
C8051F85x/86x
2.3. Clocking
The C8051F85x/86x devices have two internal oscillators and the option to use an external CMOS input at
a pin as the system clock. A programmable divider allows the user to internally run the system clock at a
slower rate than the selected oscillator if desired.
2.4. Counters/Timers and PWM
2.4.1. Programmable Counter Array (PCA0)
The C8051F85x/86x devices include a three-channel, 16-bit Programmable Counter Array with the
following features:
16-bit
time base.
clock divisor and clock source selection.
Three independently-configurable channels.
8, 9, 10, 11 and 16-bit PWM modes (center or edge-aligned operation).
Output polarity control.
Frequency output mode.
Capture on rising, falling or any edge.
Compare function for arbitrary waveform generation.
Software timer (internal compare) mode.
Can accept hardware “kill” signal from comparator 0.
Programmable
2.4.2. Timers (Timer 0, Timer 1, Timer 2 and Timer 3)
Timers include the following features:
Timer
0 and Timer 1 are standard 8051 timers, supporting backwards-compatibility with firmware
and hardware.
Timer 2 and Timer 3 can each operate as 16-bit auto-reload or two independent 8-bit auto-reload
timers, and include pin or LFO clock capture capabilities.
2.4.3. Watchdog Timer (WDT0)
The watchdog timer includes a 16-bit timer with a programmable reset period. The registers are protected
from inadvertent access by an independent lock and key interface.
The Watchdog Timer has the following features:
Programmable
timeout interval.
from the low frequency oscillator.
Lock-out feature to prevent any modification until a system reset.
Runs
Rev. 1.1
27
C8051F85x/86x
2.5. Communications and other Digital Peripherals
2.5.1. Universal Asynchronous Receiver/Transmitter (UART0)
The UART uses two signals (TX and RX) and a predetermined fixed baud rate to provide asynchronous
communications with other devices.
The UART module provides the following features:
Asynchronous
transmissions and receptions.
Baud rates up to SYSCLK / 2 (transmit) or SYSCLK / 8 (receive).
8- or 9-bit data.
Automatic start and stop generation.
2.5.2. Serial Peripheral Interface (SPI0)
SPI is a 3- or 4-wire communication interface that includes a clock, input data, output data, and an optional
select signal.
The SPI module includes the following features:
Supports
Supports
3- or 4-wire master or slave modes.
external clock frequencies up to SYSCLK / 2 in master mode and SYSCLK / 10 in slave
mode.
Support for all clock phase and polarity modes.
8-bit programmable clock rate.
Support for multiple masters on the same data lines.
2.5.3. System Management Bus / I2C (SMBus0)
The SMBus interface is a two-wire, bi-directional serial bus compatible with both I2C and SMBus protocols.
The two clock and data signals operate in open-drain mode with external pull-ups to support automatic bus
arbitration.
Reads and writes to the interface are byte-oriented with the SMBus interface autonomously controlling the
serial transfer of the data. Data can be transferred at up to 1/8th of the system clock as a master or slave,
which can be faster than allowed by the SMBus / I2C specification, depending on the clock source used. A
method of extending the clock-low duration is available to accommodate devices with different speed
capabilities on the same bus.
The SMBus interface may operate as a master and/or slave, and may function on a bus with multiple
masters. The SMBus provides control of SDA (serial data), SCL (serial clock) generation and
synchronization, arbitration logic, and start/stop control and generation.
The SMBus module includes the following features:
Standard
(up to 100 kbps) and Fast (400 kbps) transfer speeds.
Support for master, slave, and multi-master modes.
Hardware synchronization and arbitration for multi-master mode.
Clock low extending (clock stretching) to interface with faster masters.
Hardware support for 7-bit slave and general call address recognition.
Firmware support for 10-bit slave address decoding.
Ability to inhibit all slave states.
Programmable data setup/hold times.
2.5.4. 16/32-bit CRC (CRC0)
The CRC module is designed to provide hardware calculations for flash memory verification and
communications protocols. The CRC module supports the standard CCITT-16 16-bit polynomial (0x1021),
and includes the following features:
Support
28
for four CCITT-16 polynomial.
Rev. 1.1
C8051F85x/86x
Byte-level
bit reversal.
CRC of flash contents on one or more 256-byte blocks.
Initial seed selection of 0x0000 or 0xFFFF.
Automatic
Rev. 1.1
29
C8051F85x/86x
2.6. Analog Peripherals
2.6.1. 12-Bit Analog-to-Digital Converter (ADC0)
The ADC0 module on C8051F85x/86x devices is a Successive Approximation Register (SAR) Analog to
Digital Converter (ADC). The key features of the ADC module are:
Single-ended
12-bit and 10-bit modes.
an output update rate of 200 ksps samples per second in 12-bit mode or 800 ksps
samples per second in 10-bit mode.
Operation in low power modes at lower conversion speeds.
Selectable asynchronous hardware conversion trigger.
Output data window comparator allows automatic range checking.
Support for Burst Mode, which produces one set of accumulated data per conversion-start trigger
with programmable power-on settling and tracking time.
Conversion complete and window compare interrupts supported.
Flexible output data formatting.
Includes an internal fast-settling reference with two levels (1.65 V and 2.4 V) and support for
external reference and signal ground.
Supports
2.6.2. Low Current Comparators (CMP0, CMP1)
The comparators take two analog input voltages and output the relationship between these voltages (less
than or greater than) as a digital signal. The Low Power Comparator module includes the following
features:
Multiple
sources for the positive and negative poles, including VDD, VREF, and I/O pins.
outputs are available: a digital synchronous latched output and a digital asynchronous raw
output.
Programmable hysteresis and response time.
Falling or rising edge interrupt options on the comparator output.
Provide “kill” signal to PCA module.
Comparator 0 can be used to reset the device.
Two
30
Rev. 1.1
C8051F85x/86x
2.7. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
The
core halts program execution.
registers are initialized to their defined reset values unless the bits reset only with a poweron reset.
External port pins are forced to a known state.
Interrupts and timers are disabled.
All registers are reset to the predefined values noted in the register descriptions unless the bits only reset
with a power-on reset. The contents of RAM are unaffected during a reset; any previously stored data is
preserved as long as power is not lost.
Module
The Port I/O latches are reset to 1 in open-drain mode. Weak pullups are enabled during and after the
reset. For VDD Supply Monitor and power-on resets, the RST pin is driven low until the device exits the
reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the
internal low-power oscillator. The Watchdog Timer is enabled with the Low Frequency Oscillator (LFO0) as
its clock source. Program execution begins at location 0x0000.
2.8. On-Chip Debugging
The C8051F85x/86x devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow flash
programming and in-system debugging with the production part installed in the end application. The C2
interface uses a clock signal (C2CK) and a bi-directional C2 data signal (C2D) to transfer information
between the device and a host system. See the C2 Interface Specification for details on the C2 protocol.
Rev. 1.1
31
C8051F85x/86x
3. Pin Definitions
3.1. C8051F850/1/2/3/4/5 QSOP24 Pin Definitions
N/C
1
24
N/C
P0.2
2
23
P0.3
P0.1 / AGND
3
22
P0.4
P0.0 / VREF
4
21
P0.5
GND
5
20
P0.6
VDD
6
19
P0.7
24 pin QSOP
(Top View)
RST / C2CK
7
18
P1.0
C2D / P2.0
8
17
P1.1
P1.7
9
16
P1.2
P1.6
10
15
P1.3
P1.5
11
14
P1.4
P2.1
12
13
N/C
Figure 3.1. C8051F850/1/2/3/4/5-GU and C8051F850/1/2/3/4/5-IU Pinout
32
Type
GND
Ground
5
VDD
Power
6
RST /
C2CK
Active-low Reset /
C2 Debug Clock
7
Rev. 1.1
Analog Functions
Pin Name
Additional Digital Functions
Pin Numbers
Crossbar Capability
Table 3.1. Pin Definitions for C8051F850/1/2/3/4/5-GU and C8051F850/1/2/3/4/5-IU
C8051F85x/86x
Analog Functions
Additional Digital Functions
Pin Numbers
Crossbar Capability
Table 3.1. Pin Definitions for C8051F850/1/2/3/4/5-GU and C8051F850/1/2/3/4/5-IU
Pin Name
Type
P0.0
Standard I/O
4
Yes
P0MAT.0
INT0.0
INT1.0
ADC0.0
CP0P.0
CP0N.0
VREF
P0.1
Standard I/O
3
Yes
P0MAT.1
INT0.1
INT1.1
ADC0.1
CP0P.1
CP0N.1
AGND
P0.2
Standard I/O
2
Yes
P0MAT.2
INT0.2
INT1.2
ADC0.2
CP0P.2
CP0N.2
P0.3 /
EXTCLK
Standard I/O /
External CMOS Clock Input
23
Yes
P0MAT.3
EXTCLK
INT0.3
INT1.3
ADC0.3
CP0P.3
CP0N.3
P0.4
Standard I/O
22
Yes
P0MAT.4
INT0.4
INT1.4
ADC0.4
CP0P.4
CP0N.4
P0.5
Standard I/O
21
Yes
P0MAT.5
INT0.5
INT1.5
ADC0.5
CP0P.5
CP0N.5
P0.6
Standard I/O
20
Yes
P0MAT.6
CNVSTR
INT0.6
INT1.6
ADC0.6
CP0P.6
CP0N.6
P0.7
Standard I/O
19
Yes
P0MAT.7
INT0.7
INT1.7
ADC0.7
CP0P.7
CP0N.7
Rev. 1.1
33
C8051F85x/86x
34
Analog Functions
Additional Digital Functions
Pin Numbers
Crossbar Capability
Table 3.1. Pin Definitions for C8051F850/1/2/3/4/5-GU and C8051F850/1/2/3/4/5-IU
Pin Name
Type
P1.0
Standard I/O
18
Yes
P1MAT.0
ADC0.8
CP1P.0
CP1N.0
P1.1
Standard I/O
17
Yes
P1MAT.1
ADC0.9
CP1P.1
CP1N.1
P1.2
Standard I/O
16
Yes
P1MAT.2
ADC0.10
CP1P.2
CP1N.2
P1.3
Standard I/O
15
Yes
P1MAT.3
ADC0.11
CP1P.3
CP1N.3
P1.4
Standard I/O
14
Yes
P1MAT.4
ADC0.12
CP1P.4
CP1N.4
P1.5
Standard I/O
11
Yes
P1MAT.5
ADC0.13
CP1P.5
CP1N.5
P1.6
Standard I/O
10
Yes
P1MAT.6
ADC0.14
CP1P.6
CP1N.6
P1.7
Standard I/O
9
Yes
P1MAT.7
ADC0.15
CP1P.7
CP1N.7
P2.0 /
C2D
Standard I/O /
C2 Debug Data
8
P2.1
Standard I/O
12
Rev. 1.1
C8051F85x/86x
No Connection
Analog Functions
N/C
Additional Digital Functions
Type
Pin Numbers
Pin Name
Crossbar Capability
Table 3.1. Pin Definitions for C8051F850/1/2/3/4/5-GU and C8051F850/1/2/3/4/5-IU
1
13
24
Rev. 1.1
35
C8051F85x/86x
RST / C2CK
5
6
P0.3
P0.4
P0.5
19
18
17
GND
P1.6
C2D / P2.0
(Top View)
10
4
16
P0.6
15
P0.7
14
P1.0
13
P1.1
12
GND
11
P1.2
P1.3
VDD
20 pin QFN
9
3
P1.4
GND
8
2
P1.5
P0.0 / VREF
P0.2
1
7
P0.1 / AGND
20
3.2. C8051F850/1/2/3/4/5 QFN20 Pin Definitions
Figure 3.2. C8051F850/1/2/3/4/5-GM and C8051F850/1/2/3/4/5-IM Pinout
36
Type
GND
Ground
Center
3
12
VDD
Power
4
RST /
C2CK
Active-low Reset /
C2 Debug Clock
5
Rev. 1.1
Analog Functions
Pin Name
Additional Digital Functions
Pin Numbers
Crossbar Capability
Table 3.2. Pin Definitions for C8051F850/1/2/3/4/5-GM and C8051F850/1/2/3/4/5-IM
C8051F85x/86x
Analog Functions
Additional Digital Functions
Pin Numbers
Crossbar Capability
Table 3.2. Pin Definitions for C8051F850/1/2/3/4/5-GM and C8051F850/1/2/3/4/5-IM
Pin Name
Type
P0.0
Standard I/O
2
Yes
P0MAT.0
INT0.0
INT1.0
ADC0.0
CP0P.0
CP0N.0
VREF
P0.1
Standard I/O
1
Yes
P0MAT.1
INT0.1
INT1.1
ADC0.1
CP0P.1
CP0N.1
AGND
P0.2
Standard I/O
20
Yes
P0MAT.2
INT0.2
INT1.2
ADC0.2
CP0P.2
CP0N.2
P0.3
Standard I/O
19
Yes
P0MAT.3
EXTCLK
INT0.3
INT1.3
ADC0.3
CP0P.3
CP0N.3
P0.4
Standard I/O
18
Yes
P0MAT.4
INT0.4
INT1.4
ADC0.4
CP0P.4
CP0N.4
P0.5
Standard I/O
17
Yes
P0MAT.5
INT0.5
INT1.5
ADC0.5
CP0P.5
CP0N.5
P0.6
Standard I/O
16
Yes
P0MAT.6
CNVSTR
INT0.6
INT1.6
ADC0.6
CP0P.6
CP0N.6
P0.7
Standard I/O
15
Yes
P0MAT.7
INT0.7
INT1.7
ADC0.7
CP0P.7
CP0N.7
Rev. 1.1
37
C8051F85x/86x
38
Analog Functions
Additional Digital Functions
Pin Numbers
Crossbar Capability
Table 3.2. Pin Definitions for C8051F850/1/2/3/4/5-GM and C8051F850/1/2/3/4/5-IM
Pin Name
Type
P1.0
Standard I/O
14
Yes
P1MAT.0
ADC0.8
CP1P.0
CP1N.0
P1.1
Standard I/O
13
Yes
P1MAT.1
ADC0.9
CP1P.1
CP1N.1
P1.2
Standard I/O
11
Yes
P1MAT.2
ADC0.10
CP1P.2
CP1N.2
P1.3
Standard I/O
10
Yes
P1MAT.3
ADC0.11
CP1P.3
CP1N.3
P1.4
Standard I/O
9
Yes
P1MAT.4
ADC0.12
CP1P.4
CP1N.4
P1.5
Standard I/O
8
Yes
P1MAT.5
ADC0.13
CP1P.5
CP1N.5
P1.6
Standard I/O
7
Yes
P1MAT.6
ADC0.14
CP1P.6
CP1N.6
P2.0 /
C2D
Standard I/O /
C2 Debug Data
6
Rev. 1.1
C8051F85x/86x
3.3. C8051F860/1/2/3/4/5 SOIC16 Pin Definitions
P0.2
1
16
P0.3
P0.1 / AGND
2
15
P0.4
P0.0 / VREF
3
14
P0.5
GND
4
13
P0.6
VDD
5
12
P0.7
RST / C2CK
6
11
P1.0
C2D / P2.0
7
10
P1.1
P1.3
8
9
P1.2
16 pin SOIC
(Top View)
Figure 3.3. C8051F860/1/2/3/4/5-GS and C8051F860/1/2/3/4/5-IS Pinout
Type
GND
Ground
4
VDD
Power
5
RST /
C2CK
Active-low Reset /
C2 Debug Clock
6
P0.0
Standard I/O
3
Rev. 1.1
Yes
P0MAT.0
INT0.0
INT1.0
Analog Functions
Pin Name
Additional Digital Functions
Pin Numbers
Crossbar Capability
Table 3.3. Pin Definitions for C8051F860/1/2/3/4/5-GS and C8051F860/1/2/3/4/5-IS
ADC0.0
CP0P.0
CP0N.0
39
C8051F85x/86x
40
Analog Functions
Additional Digital Functions
Pin Numbers
Crossbar Capability
Table 3.3. Pin Definitions for C8051F860/1/2/3/4/5-GS and C8051F860/1/2/3/4/5-IS
Pin Name
Type
P0.1
Standard I/O
2
Yes
P0MAT.1
INT0.1
INT1.1
ADC0.1
CP0P.1
CP0N.1
P0.2
Standard I/O
1
Yes
P0MAT.2
INT0.2
INT1.2
ADC0.2
CP0P.2
CP0N.2
P0.3 /
EXTCLK
Standard I/O /
External CMOS Clock Input
16
Yes
P0MAT.3
EXTCLK
INT0.3
INT1.3
ADC0.3
CP0P.3
CP0N.3
P0.4
Standard I/O
15
Yes
P0MAT.4
INT0.4
INT1.4
ADC0.4
CP0P.4
CP0N.4
P0.5
Standard I/O
14
Yes
P0MAT.5
INT0.5
INT1.5
ADC0.5
CP0P.5
CP0N.5
P0.6
Standard I/O
13
Yes
P0MAT.6
CNVSTR
INT0.6
INT1.6
ADC0.6
CP1P.0
CP1N.0
P0.7
Standard I/O
12
Yes
P0MAT.7
INT0.7
INT1.7
ADC0.7
CP1P.1
CP1N.1
P1.0
Standard I/O
11
Yes
P1MAT.0
ADC0.8
CP1P.2
CP1N.2
Rev. 1.1
C8051F85x/86x
Analog Functions
Additional Digital Functions
Pin Numbers
Crossbar Capability
Table 3.3. Pin Definitions for C8051F860/1/2/3/4/5-GS and C8051F860/1/2/3/4/5-IS
Pin Name
Type
P1.1
Standard I/O
10
Yes
P1MAT.1
ADC0.9
CP1P.3
CP1N.3
P1.2
Standard I/O
9
Yes
P1MAT.2
ADC0.10
CP1P.4
CP1N.4
P1.3
Standard I/O
8
Yes
P1MAT.3
ADC0.11
CP1P.5
CP1N.5
P2.0 /
C2D
Standard I/O /
C2 Debug Data
7
Rev. 1.1
41
C8051F85x/86x
4. Ordering Information
C8051 F 850 – C – G M
Package Type M (QFN), U (QSOP), S (SSOP)
Temperature Grade G (-40 to +85), I (-40 to +125)
Revision
Family and Features – 85x and 86x
Memory Type – F (Flash)
Silicon Labs 8051 Family
Figure 4.1. C8051F85x/86x Part Numbering
All C8051F85x/86x family members have the following features:
CIP-51
Core running up to 25 MHz
Two Internal Oscillators (24.5 MHz and 80 kHz)
I2C/SMBus
SPI
UART
3-Channel Programmable Counter Array (PWM, Clock Generation, Capture/Compare)
4 16-bit Timers
2 Analog Comparators
16-bit CRC Unit
In addition to these features, each part number in the C8051F85x/86x family has a set of features that vary
across the product line. The product selection guide in Table 4.1 shows the features available on each
family member.
All devices in Table 4.1 are also available in an industrial version. For the industrial version, the -G in the
ordering part number is replaced with -I. For example, the industrial version of the C8051F850-C-GM is the
C8051F850-C-IM.
42
Rev. 1.1
C8051F85x/86x
Flash Memory (kB)
RAM (Bytes)
Digital Port I/Os (Total)
Number of ADC0 Channels
I/O with Comparator 0/1 Inputs
Pb-free (RoHS Compliant)
AEC-Q100 Qualified
Temperature Range
C8051F850-C-GM
8
512
16
15
15
-40 to 85 °C
QFN-20
C8051F850-C-GU
8
512
18
16
16
-40 to 85 °C
QSOP-24
C8051F851-C-GM
4
512
16
15
15
-40 to 85 °C
QFN-20
C8051F851-C-GU
4
512
18
16
16
-40 to 85 °C
QSOP-24
C8051F852-C-GM
2
256
16
15
15
-40 to 85 °C
QFN-20
C8051F852-C-GU
2
256
18
16
16
-40 to 85 °C
QSOP-24
C8051F853-C-GM
8
512
16
—
15
-40 to 85 °C
QFN-20
C8051F853-C-GU
8
512
18
—
16
-40 to 85 °C
QSOP-24
C8051F854-C-GM
4
512
16
—
15
-40 to 85 °C
QFN-20
C8051F854-C-GU
4
512
18
—
16
-40 to 85 °C
QSOP-24
C8051F855-C-GM
2
256
16
—
15
-40 to 85 °C
QFN-20
C8051F855-C-GU
2
256
18
—
16
-40 to 85 °C
QSOP-24
C8051F860-C-GS
8
512
13
12
12
-40 to 85 °C
SOIC-16
C8051F861-C-GS
4
512
13
12
12
-40 to 85 °C
SOIC-16
C8051F862-C-GS
2
256
13
12
12
-40 to 85 °C
SOIC-16
C8051F863-C-GS
8
512
13
—
12
-40 to 85 °C
SOIC-16
C8051F864-C-GS
4
512
13
—
12
-40 to 85 °C
SOIC-16
C8051F865-C-GS
2
256
13
—
12
-40 to 85 °C
SOIC-16
Rev. 1.1
Package
Ordering Part Number
Table 4.1. Product Selection Guide
43
44
Rev. 1.1
Package
Temperature Range
AEC-Q100 Qualified
Pb-free (RoHS Compliant)
I/O with Comparator 0/1 Inputs
Number of ADC0 Channels
Digital Port I/Os (Total)
RAM (Bytes)
Flash Memory (kB)
Ordering Part Number
C8051F85x/86x
Table 4.1. Product Selection Guide
-IM, -IU and -IS extended temperature range devices (-40 to 125 °C) are also available.
C8051F85x/86x
5. QSOP-24 Package Specifications
Figure 5.1. QSOP-24 Package Drawing
Table 5.1. QSOP-24 Package Dimensions
Dimension
Min
Nom
Max
Dimension
Min
Nom
Max
A
—
—
1.75
e
A1
0.10
—
0.25
L
0.40
—
1.27
b
0.20
—
0.30
0º
—
8º
c
0.10
—
0.25
aaa
0.20
0.635 BSC
D
8.65 BSC
bbb
0.18
E
6.00 BSC
ccc
0.10
E1
3.90 BSC
ddd
0.10
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-137, variation AE.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
Rev. 1.1
45
C8051F85x/86x
Figure 5.2. QSOP-24 PCB Land Pattern
Table 5.2. QSOP-24 PCB Land Pattern Dimensions
Dimension
Min
Max
C
E
X
Y
5.20
5.30
0.635 BSC
0.30
1.50
0.40
1.60
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This land pattern design is based on the IPC-7351 guidelines.
Solder Mask Design
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should
be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
Card Assembly
7. A No-Clean, Type-3 solder paste is recommended.
8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
46
Rev. 1.1
C8051F85x/86x
6. QFN-20 Package Specifications
Figure 6.1. QFN-20 Package Drawing
Table 6.1. QFN-20 Package Dimensions
Symbol
Millimeters
Symbol
Min
Nom
Max
Millimeters
Min
Nom
Max
A
0.70
0.75
0.80
f
A1
0.00
0.02
0.05
L
0.3
0.40
0.5
b
0.20
0.25
0.30
L1
0.00
—
0.10
c
0.25
0.30
0.35
aaa
—
—
0.05
bbb
—
—
0.05
ccc
—
—
0.08
D
D2
3.00 BSC
1.6
1.70
1.8
2.53 BSC
e
0.50 BSC
ddd
—
—
0.10
E
3.00 BSC
eee
—
—
0.10
E2
1.6
1.70
1.8
Notes:
1. All dimensions are shown in millimeters unless otherwise noted.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
Rev. 1.1
47
C8051F85x/86x
Figure 6.2. QFN-20 Landing Diagram
48
Rev. 1.1
C8051F85x/86x
Table 6.2. QFN-20 Landing Diagram Dimensions
Symbol
Millimeters
Min
D
D2
Symbol
Max
Min
2.71 REF
1.60
1.80
2.10
—
W
—
0.34
—
0.28
0.50 BSC
X
E
2.71 REF
Y
f
GD
1.60
1.80
2.53 BSC
2.10
Max
GE
e
E2
Millimeters
0.61 REF
ZE
—
3.31
ZD
—
3.31
—
Notes: General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Notes: Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Notes: Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should
be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides
approximately 70% solder paste coverage on the pad, which is optimum to assure
correct component stand-off.
Notes: Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification
for Small Body Components.
Rev. 1.1
49
C8051F85x/86x
7. SOIC-16 Package Specifications
Figure 7.1. SOIC-16 Package Drawing
Table 7.1. SOIC-16 Package Dimensions
Dimension
Min
A
Nom
Max
Dimension
Min
Nom
Max
—
1.75
L
0.40
A1
0.10
0.25
L2
A2
1.25
—
h
0.25
0.50
b
0.31
0.51
0º
8º
c
0.17
0.25
aaa
0.10
1.27
0.25 BSC
D
9.90 BSC
bbb
0.20
E
6.00 BSC
ccc
0.10
E1
3.90 BSC
ddd
0.25
e
1.27 BSC
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
50
Rev. 1.1
C8051F85x/86x
Figure 7.2. SOIC-16 PCB Land Pattern
Table 7.2. SOIC-16 PCB Land Pattern Dimensions
Dimension
Feature
(mm)
C1
E
X1
Y1
Pad Column Spacing
Pad Row Pitch
Pad Width
Pad Length
5.40
1.27
0.60
1.55
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N for Density
Level B (Median Land Protrusion).
3. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication
tolerance of 0.05 mm is assumed.
Rev. 1.1
51
C8051F85x/86x
8. Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The memory organization of the
C8051F85x/86x device family is shown in Figure 8.1.
PROGRAM/DATA MEMORY
(FLASH)
DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE
0xFF
0x1FFF
0x80
0x7F
Upper 128 RAM
(Indirect Addressing
Only)
Special Function
Registers
(Direct Addressing Only)
(Direct and Indirect Addressing)
0x30
0x2F
0x20
0x1F
0x00
32 Bit-Addressable Bytes
32 General Purpose Registers
8 kB FLASH
(In-System
Programmable in 512
Byte Sectors)
EXTERNAL DATA ADDRESS SPACE
0xFFFF
Same 256 bytes as 0x0000 to 0x00FF,
wrapped on 256-byte boundaries
0x0100
0x00FF
XRAM - 256 Bytes
0x0000
(accessable using MOVX instruction)
0x0000
Figure 8.1. C8051F85x/86x Memory Map (8 kB flash version shown)
52
Rev. 1.1
Lower 128 RAM
(Direct and Indirect
Addressing)
C8051F85x/86x
8.1. Program Memory
The CIP-51 core has a 64 kB program memory space. The C8051F85x/86x family implements 8 kB, 4 kB
or 2 kB of this program memory space as in-system, re-programmable flash memory. The last address in
the flash block (0x1FFF on 8 kB devices, 0x0FFF on 4 kB devices and 0x07FF on 2 kB devices) serves as
a security lock byte for the device, and provides read, write and erase protection. Addresses above the
lock byte within the 64 kB address space are reserved.
C8051F850/3
C8051F860/3
Lock Byte
FLASH memory organized in
512-byte pages
Lock Byte Page
0x1FFF
0x1FFE
0x1E00
C8051F851/4
C8051F861/4
Lock Byte
Lock Byte Page
0x0FFF
0x0FFE
0x0E00
C8051F852/5
C8051F862/5
Lock Byte
Flash Memory Space
Lock Byte Page
Flash Memory Space
0x07FF
0x07FE
0x0600
Flash Memory Space
0x0000
0x0000
0x0000
Figure 8.2. Flash Program Memory Map
8.1.1. MOVX Instruction and Program Memory
The MOVX instruction in an 8051 device is typically used to access external data memory. On the
C8051F85x/86x devices, the MOVX instruction is normally used to read and write on-chip XRAM, but can
be re-configured to write and erase on-chip flash memory space. MOVC instructions are always used to
read flash memory, while MOVX write instructions are used to erase and write flash. This flash access
feature provides a mechanism for the C8051F85x/86x to update program code and use the program
memory space for non-volatile data storage. Refer to Section “10. Flash Memory” on page 61 for further
details.
8.2. Data Memory
The C8051F85x/86x device family includes up to 512 bytes of RAM data memory. 256 bytes of this
memory is mapped into the internal RAM space of the 8051. On devices with 512 bytes total RAM, 256
additional bytes of memory are available as on-chip “external” memory. The data memory map is shown in
Figure 8.1 for reference.
8.2.1. Internal RAM
There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The
lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either
direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00
through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight
byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or
as 128 bit locations accessible with the direct addressing mode.
Rev. 1.1
53
C8051F85x/86x
The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the
same address space as the Special Function Registers (SFR) but is physically separate from the SFR
space. The addressing mode used by an instruction when accessing locations above 0x7F determines
whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use
direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the
upper 128 bytes of data memory. Figure 8.1 illustrates the data memory organization of the C8051F85x/
86x.
Revision C C8051F852/5 and C8051F862/5 devices implement the upper four bytes of internal RAM as a
32-bit Unique Identifier. More information can be found in “Device Identification and Unique Identifier” on
page 68.
8.2.1.1. General Purpose Registers
The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of
general-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7.
Only one of these banks may be enabled at a time. Two bits in the program status word (PSW) register,
RS0 and RS1, select the active register bank. This allows fast context switching when entering subroutines
and interrupt service routines. Indirect addressing modes use registers R0 and R1 as index registers.
8.2.1.2. Bit Addressable Locations
In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20
through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from
0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address
0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by
the type of instruction used (bit source or destination operands as opposed to a byte source or
destination).
The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where
XX is the byte address and B is the bit position within the byte. For example, the instruction:
MOV
C, 22.3h
moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag.
8.2.1.3. Stack
A programmer's stack can be located anywhere in the 256-byte data memory. The stack area is
designated using the Stack Pointer (SP) SFR. The SP will point to the last location used. The next value
pushed on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to
location 0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the
first register (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be
initialized to a location in the data memory not being used for data storage. The stack depth can extend up
to 256 bytes.
8.2.2. External RAM
On devices with 512 bytes total RAM, there are 256 bytes of on-chip RAM mapped into the external data
memory space. All of these address locations may be accessed using the external move instruction
(MOVX) and the data pointer (DPTR), or using MOVX indirect addressing mode. Note: The 16-bit MOVX
instruction is also used for writes to the flash memory. See Section “10. Flash Memory” on page 61 for
details. The MOVX instruction accesses XRAM by default.
For a 16-bit MOVX operation (@DPTR), the upper 8 bits of the 16-bit external data memory address word
are "don't cares". As a result, addresses 0x0000 through 0x00FF are mapped modulo style over the entire
64 k external data memory address range. For example, the XRAM byte at address 0x0000 is shadowed
at addresses 0x0100, 0x0200, 0x0300, 0x0400, etc.
Revision C C8051F850/1/3/4 and C8051F860/1/3/4 devices implement the upper four bytes of external
RAM as a 32-bit Unique Identifier. More information can be found in “Device Identification and Unique
Identifier” on page 68.
54
Rev. 1.1
C8051F85x/86x
8.2.3. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The
CIP-51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional
SFRs used to configure and access the sub-systems unique to the MCU. This allows the addition of new
functionality while retaining compatibility with the MCS-51™ instruction set.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are bitaddressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided.
Rev. 1.1
55
C8051F85x/86x
9. Special Function Register Memory Map
This section details the special function register memory map for the C8051F85x/86x devices.
Table 9.1. Special Function Register (SFR) Memory Map
F8
SPI0CN
PCA0L
PCA0H
F0
B
P0MDIN
P1MDIN
E8 ADC0CN0
PCA0CPL0 PCA0CPH0
EIP1
-
PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2
XBR1
XBR2
IT01CF
P0MAT
P0MASK
VDM0CN
-
PRTDRV
PCA0PWM
P1MAT
P1MASK
RSTSRC
-
EIE1
-
E0
ACC
XBR0
D8
PCA0CN
PCA0MD
PCA0CPM0 PCA0CPM1 PCA0CPM2
CRC0IN
CRC0DAT
ADC0PWR
D0
PSW
REF0CN
CRC0AUTO CRC0CNT
P0SKIP
P1SKIP
SMB0ADM
SMB0ADR
C8
TMR2CN
REG0CN
TMR2RLL
TMR2RLH
TMR2L
TMR2H
CRC0CN
CRC0FLIP
C0
SMB0CN
SMB0CF
SMB0DAT
ADC0GTL
ADC0GTH
ADC0LTL
ADC0LTH
OSCICL
B8
IP
ADC0TK
-
ADC0MX
ADC0CF
ADC0L
ADC0H
CPT1CN
B0
-
OSCLCN
ADC0CN1
ADC0AC
-
DEVICEID
REVID
FLKEY
A8
IE
CLKSEL
CPT1MX
CPT1MD
SMB0TC
DERIVID
-
-
A0
P2
SPI0CFG
SPI0CKR
SPI0DAT
P0MDOUT
P1MDOUT
P2MDOUT
-
98
SCON0
SBUF0
-
CPT0CN
PCA0CLR
CPT0MD
PCA0CENT
CPT0MX
90
P1
TMR3CN
TMR3RLL
TMR3RLH
TMR3L
TMR3H
PCA0POL
WDTCN
88
TCON
TMOD
TL0
TL1
TH0
TH1
CKCON
PSCTL
80
P0
SP
DPL
DPH
-
-
-
PCON
0(8)
1(9)
2(A)
3(B)
4(C)
5(D)
6(E)
7(F)
(bit addressable)
Table 9.2. Special Function Registers
Register
Address
Register Description
Page
ACC
0xE0
Accumulator
122
ADC0AC
0xB3
ADC0 Accumulator Configuration
102
ADC0CF
0xBC
ADC0 Configuration
101
ADC0CN0
0xE8
ADC0 Control 0
99
ADC0CN1
0xB2
ADC0 Control 1
100
ADC0GTH
0xC4
ADC0 Greater-Than High Byte
107
ADC0GTL
0xC3
ADC0 Greater-Than Low Byte
108
ADC0H
0xBE
ADC0 Data Word High Byte
105
56
Rev. 1.1
C8051F85x/86x
Table 9.2. Special Function Registers (Continued)
Register
Address
Register Description
Page
ADC0L
0xBD
ADC0 Data Word Low Byte
106
ADC0LTH
0xC6
ADC0 Less-Than High Byte
109
ADC0LTL
0xC5
ADC0 Less-Than Low Byte
110
ADC0MX
0xBB
ADC0 Multiplexer Selection
111
ADC0PWR
0xDF
ADC0 Power Control
103
ADC0TK
0xB9
ADC0 Burst Mode Track Time
104
B
0xF0
B Register
123
CKCON
0x8E
Clock Control
269
CLKSEL
0xA9
Clock Selection
129
CPT0CN
0x9B
Comparator 0 Control
134
CPT0MD
0x9D
Comparator 0 Mode
135
CPT0MX
0x9F
Comparator 0 Multiplexer Selection
136
CPT1CN
0xBF
Comparator 1 Control
137
CPT1MD
0xAB
Comparator 1 Mode
138
CPT1MX
0xAA
Comparator 1 Multiplexer Selection
139
CRC0AUTO
0xD2
CRC0 Automatic Control
146
CRC0CN
0xCE
CRC0 Control
143
CRC0CNT
0xD3
CRC0 Automatic Flash Sector Count
147
CRC0DAT
0xDE
CRC0 Data Output
145
CRC0FLIP
0xCF
CRC0 Bit Flip
148
CRC0IN
0xDD
CRC0 Data Input
144
DERIVID
0xAD
Derivative Identification
70
DEVICEID
0xB5
Device Identification
69
DPH
0x83
Data Pointer Low
120
DPL
0x82
Data Pointer High
119
EIE1
0xE6
Extended Interrupt Enable 1
78
EIP1
0xF3
Extended Interrupt Priority 1
80
FLKEY
0xB7
Flash Lock and Key
67
Rev. 1.1
57
C8051F85x/86x
Table 9.2. Special Function Registers (Continued)
Register
Address
Register Description
Page
IE
0xA8
Interrupt Enable
75
IP
0xB8
Interrupt Priority
77
IT01CF
0xE4
INT0 / INT1 Configuration
150
OSCICL
0xC7
High Frequency Oscillator Calibration
127
OSCLCN
0xB1
Low Frequency Oscillator Control
128
P0
0x80
Port 0 Pin Latch
199
P0MASK
0xFE
Port 0 Mask
197
P0MAT
0xFD
Port 0 Match
198
P0MDIN
0xF1
Port 0 Input Mode
200
P0MDOUT
0xA4
Port 0 Output Mode
201
P0SKIP
0xD4
Port 0 Skip
202
P1
0x90
Port 1 Pin Latch
205
P1MASK
0xEE
Port 1 Mask
203
P1MAT
0xED
Port 1 Match
204
P1MDIN
0xF2
Port 1 Input Mode
206
P1MDOUT
0xA5
Port 1 Output Mode
207
P1SKIP
0xD5
Port 1 Skip
208
P2
0xA0
Port 2 Pin Latch
209
P2MDOUT
0xA6
Port 2 Output Mode
210
PCA0CENT
0x9E
PCA Center Alignment Enable
177
PCA0CLR
0x9C
PCA Comparator Clear Control
170
PCA0CN
0xD8
PCA Control
167
PCA0CPH0
0xFC
PCA Capture Module High Byte 0
175
PCA0CPH1
0xEA
PCA Capture Module High Byte 1
181
PCA0CPH2
0xEC
PCA Capture Module High Byte 2
183
PCA0CPL0
0xFB
PCA Capture Module Low Byte 0
174
PCA0CPL1
0xE9
PCA Capture Module Low Byte 1
180
PCA0CPL2
0xEB
PCA Capture Module Low Byte 2
182
58
Rev. 1.1
C8051F85x/86x
Table 9.2. Special Function Registers (Continued)
Register
Address
Register Description
Page
PCA0CPM0
0xDA
PCA Capture/Compare Mode 0
171
PCA0CPM1
0xDB
PCA Capture/Compare Mode 1
178
PCA0CPM2
0xDC
PCA Capture/Compare Mode 1
179
PCA0H
0xFA
PCA Counter/Timer Low Byte
173
PCA0L
0xF9
PCA Counter/Timer High Byte
172
PCA0MD
0xD9
PCA Mode
168
PCA0POL
0x96
PCA Output Polarity
176
PCA0PWM
0xF7
PCA PWM Configuration
169
PCON
0x87
Power Control
83
PRTDRV
0xF6
Port Drive Strength
196
PSCTL
0x8F
Program Store Control
66
PSW
0xD0
Program Status Word
124
REF0CN
0xD1
Voltage Reference Control
112
REG0CN
0xC9
Voltage Regulator Control
84
REVID
0xB6
Revision Identification
71
RSTSRC
0xEF
Reset Source
215
SBUF0
0x99
UART0 Serial Port Data Buffer
297
SCON0
0x98
UART0 Serial Port Control
295
SMB0ADM
0xD6
SMBus0 Slave Address Mask
257
SMB0ADR
0xD7
SMBus0 Slave Address
256
SMB0CF
0xC1
SMBus0 Configuration
251
SMB0CN
0xC0
SMBus0 Control
254
SMB0DAT
0xC2
SMBus0 Data
258
SMB0TC
0xAC
SMBus0 Timing and Pin Control
253
SP
0x81
Stack Pointer
121
SPI0CFG
0xA1
SPI0 Configuration
227
SPI0CKR
0xA2
SPI0 Clock Control
231
SPI0CN
0xF8
SPI0 Control
229
Rev. 1.1
59
C8051F85x/86x
Table 9.2. Special Function Registers (Continued)
Register
Address
SPI0DAT
0xA3
SPI0 Data
232
TCON
0x88
Timer 0/1 Control
271
TH0
0x8C
Timer 0 High Byte
275
TH1
0x8D
Timer 1 High Byte
276
TL0
0x8A
Timer 0 Low Byte
273
TL1
0x8B
Timer 1 Low Byte
274
TMOD
0x89
Timer 0/1 Mode
272
TMR2CN
0xC8
Timer 2 Control
277
TMR2H
0xCD
Timer 2 High Byte
282
TMR2L
0xCC
Timer 2 Low Byte
281
TMR2RLH
0xCB
Timer 2 Reload High Byte
280
TMR2RLL
0xCA
Timer 2 Reload Low Byte
279
TMR3CN
0x91
Timer 3 Control
283
TMR3H
0x95
Timer 3 High Byte
288
TMR3L
0x94
Timer 3 Low Byte
287
TMR3RLH
0x93
Timer 3 Reload High Byte
286
TMR3RLL
0x92
Timer 3 Reload Low Byte
285
VDM0CN
0xFF
Supply Monitor Control
216
WDTCN
0x97
Watchdog Timer Control
301
XBR0
0xE1
Port I/O Crossbar 0
193
XBR1
0xE2
Port I/O Crossbar 1
194
XBR2
0xE3
Port I/O Crossbar 2
195
60
Register Description
Page
Rev. 1.1
C8051F85x/86x
10. Flash Memory
On-chip, re-programmable flash memory is included for program code and non-volatile data storage. The
flash memory is organized in 512-byte pages. It can be erased and written through the C2 interface or from
firmware by overloading the MOVX instruction. Any individual byte in flash memory must only be written
once between page erase operations.
10.1. Security Options
The CIP-51 provides security options to protect the flash memory from inadvertent modification by
software as well as to prevent the viewing of proprietary program code and constants. The Program Store
Write Enable (bit PSWE in register PSCTL) and the Program Store Erase Enable (bit PSEE in register
PSCTL) bits protect the flash memory from accidental modification by software. PSWE must be explicitly
set to ‘1’ before software can modify the flash memory; both PSWE and PSEE must be set to ‘1’ before
software can erase flash memory. Additional security features prevent proprietary program code and data
constants from being read or altered across the C2 interface.
A Security Lock Byte located in flash user space offers protection of the flash program memory from
access (reads, writes, or erases) by unprotected code or the C2 interface. See Section “8. Memory
Organization” on page 52 for the location of the security byte. The flash security mechanism allows the
user to lock n 512-byte flash pages, starting at page 0 (addresses 0x0000 to 0x01FF), where n is the 1’s
complement number represented by the Security Lock Byte. Note that the page containing the flash
Security Lock Byte is unlocked when no other flash pages are locked (all bits of the Lock Byte are
‘1’) and locked when any other flash pages are locked (any bit of the Lock Byte is ‘0’). An example is
shown in Figure 10.1.
Security Lock Byte:
11111101b
1s Complement:
00000010b
Flash pages locked:
3 (First two flash pages + Lock Byte Page)
Figure 10.1. Security Byte Decoding
The level of flash security depends on the flash access method. The three flash access methods that can
be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on
unlocked pages, and user firmware executing on locked pages. Table 10.1 summarizes the flash security
features of the C8051F85x/86x devices.
Table 10.1. Flash Security Summary
Action
C2 Debug
Interface
User Firmware executing from:
an unlocked page
a locked page
Permitted
Permitted
Permitted
Not Permitted
Flash Error Reset
Permitted
Read or Write page containing Lock Byte
(if no pages are locked)
Permitted
Permitted
N/A
Read or Write page containing Lock Byte
(if any page is locked)
Not Permitted
Flash Error Reset
Permitted
Read, Write or Erase unlocked pages
(except page with Lock Byte)
Read, Write or Erase locked pages
(except page with Lock Byte)
Rev. 1.1
61
C8051F85x/86x
Table 10.1. Flash Security Summary (Continued)
Read contents of Lock Byte
(if no pages are locked)
Permitted
Permitted
N/A
Read contents of Lock Byte
(if any page is locked)
Not Permitted
Flash Error Reset
Permitted
Permitted
Permitted
N/A
C2 Device Erase
Only
Flash Error Reset
Flash Error Reset
Lock additional pages
(change 1s to 0s in the Lock Byte)
Not Permitted
Flash Error Reset
Flash Error Reset
Unlock individual pages
(change 0s to 1s in the Lock Byte)
Not Permitted
Flash Error Reset
Flash Error Reset
Read, Write or Erase Reserved Area
Not Permitted
Flash Error Reset
Flash Error Reset
Erase page containing Lock Byte
(if no pages are locked)
Erase page containing Lock Byte—Unlock all
pages (if any page is locked)
C2 Device Erase—Erases all flash pages including the page containing the Lock Byte.
Flash Error Reset —Not permitted; Causes Flash Error Device Reset (FERROR bit in RSTSRC is '1' after reset).
- All prohibited operations that are performed via the C2 interface are ignored (do not cause device reset).
- Locking any flash page also locks the page containing the Lock Byte.
- Once written to, the Lock Byte cannot be modified except by performing a C2 Device Erase.
- If user code writes to the Lock Byte, the Lock does not take effect until the next device reset.
62
Rev. 1.1
C8051F85x/86x
10.2. Programming the Flash Memory
Writes to flash memory clear bits from logic 1 to logic 0, and can be performed on single byte locations.
Flash erasures set bits back to logic 1, and occur only on full pages. The write and erase operations are
automatically timed by hardware for proper execution; data polling to determine the end of the write/erase
operation is not required. Code execution is stalled during a flash write/erase operation.
The simplest means of programming the flash memory is through the C2 interface using programming
tools provided by Silicon Labs or a third party vendor. This is the only means for programming a noninitialized device.
To ensure the integrity of flash contents, it is strongly recommended that the on-chip supply monitor be
enabled in any system that includes code that writes and/or erases flash memory from software.
10.2.1. Flash Lock and Key Functions
Flash writes and erases by user software are protected with a lock and key function. The Flash Lock and
Key Register (FLKEY) must be written with the correct key codes, in sequence, before flash operations
may be performed. The key codes are: 0xA5, 0xF1. The timing does not matter, but the codes must be
written in order. If the key codes are written out of order, or the wrong codes are written, flash writes and
erases will be disabled until the next system reset. Flash writes and erases will also be disabled if a flash
write or erase is attempted before the key codes have been written properly. The flash lock resets after
each write or erase; the key codes must be written again before a following flash operation can be
performed.
10.2.2. Flash Erase Procedure
The flash memory can be programmed by software using the MOVX write instruction with the address and
data byte to be programmed provided as normal operands. Before writing to flash memory using MOVX,
flash write operations must be enabled by: (1) setting the PSWE Program Store Write Enable bit in the
PSCTL register to logic 1 (this directs the MOVX writes to target flash memory); and (2) Writing the flash
key codes in sequence to the Flash Lock register (FLKEY). The PSWE bit remains set until cleared by
software.
A write to flash memory can clear bits to logic 0 but cannot set them; only an erase operation can set bits
to logic 1 in flash. A byte location to be programmed should be erased before a new value is written.
Erase operation applies to an entire page (setting all bytes in the page to 0xFF). To erase an entire page,
perform the following steps:
1. Disable interrupts (recommended).
2. Set the PSEE bit (register PSCTL).
3. Set the PSWE bit (register PSCTL).
4. Write the first key code to FLKEY: 0xA5.
5. Write the second key code to FLKEY: 0xF1.
6. Using the MOVX instruction, write a data byte to any location within the page to be erased.
7. Clear the PSWE and PSEE bits.
10.2.3. Flash Write Procedure
Flash bytes are programmed by software with the following sequence:
1. Disable interrupts (recommended).
2. Erase the flash page containing the target location, as described in Section 10.2.2.
3. Set the PSWE bit (register PSCTL).
4. Clear the PSEE bit (register PSCTL).
5. Write the first key code to FLKEY: 0xA5.
6. Write the second key code to FLKEY: 0xF1.
7. Using the MOVX instruction, write a single data byte to the desired location within the desired
Rev. 1.1
63
C8051F85x/86x
page.
8. Clear the PSWE bit.
Steps 5–7 must be repeated for each byte to be written. After flash writes are complete, PSWE should be
cleared so that MOVX instructions do not target program memory.
10.3. Non-Volatile Data Storage
The flash memory can be used for non-volatile data storage as well as program code. This allows data
such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX
write instruction and read using the MOVC instruction. Note: MOVX read instructions always target XRAM.
10.4. Flash Write and Erase Guidelines
Any system which contains routines which write or erase flash memory from software involves some risk
that the write or erase routines will execute unintentionally if the CPU is operating outside its specified
operating range of supply voltage, system clock frequency or temperature. This accidental execution of
flash modifying code can result in alteration of flash memory contents causing a system failure that is only
recoverable by re-flashing the code in the device.
To help prevent the accidental modification of flash by firmware, hardware restricts flash writes and
erasures when the supply monitor is not active and selected as a reset source. As the monitor is enabled
and selected as a reset source by default, it is recommended that systems writing or erasing flash simply
maintain the default state.
The following guidelines are recommended for any system which contains routines which write or erase
flash from code.
10.4.1. Voltage Supply Maintenance and the Supply Monitor
1. If the system power supply is subject to voltage or current "spikes," add sufficient transient
protection devices to the power supply to ensure that the supply voltages listed in the Absolute
Maximum Ratings table are not exceeded.
2. Make certain that the minimum supply rise time specification is met. If the system cannot meet this
rise time specification, then add an external supply brownout circuit to the RST pin of the device
that holds the device in reset until the voltage supply reaches the lower limit, and re-asserts RST if
the supply drops below the low supply limit.
3. Do not disable the supply monitor. If the supply monitor must be disabled in the system, firmware
should be added to the startup routine to enable the on-chip supply monitor and enable the supply
monitor as a reset source as early in code as possible. This should be the first set of instructions
executed after the reset vector. For C-based systems, this may involve modifying the startup code
added by the C compiler. See your compiler documentation for more details. Make certain that
there are no delays in software between enabling the supply monitor and enabling the supply
monitor as a reset source. Code examples showing this can be found in “AN201: Writing to Flash
From Firmware", available from the Silicon Laboratories web site. Note that the supply monitor
must be enabled and enabled as a reset source when writing or erasing flash memory. A
flash error reset will occur if either condition is not met.
4. As an added precaution if the supply monitor is ever disabled, explicitly enable the supply monitor
and enable the supply monitor as a reset source inside the functions that write and erase flash
memory. The supply monitor enable instructions should be placed just after the instruction to set
PSWE to a 1, but before the flash write or erase operation instruction.
5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment
operators and explicitly DO NOT use the bit-wise operators (such as AND or OR). For example,
"RSTSRC = 0x02" is correct. "RSTSRC |= 0x02" is incorrect.
6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a '1'. Areas to
check are initialization code which enables other reset sources, such as the Missing Clock
64
Rev. 1.1
C8051F85x/86x
Detector or Comparator, for example, and instructions which force a Software Reset. A global
search on "RSTSRC" can quickly verify this.
10.4.2. PSWE Maintenance
7. Reduce the number of places in code where the PSWE bit (in register PSCTL) is set to a 1. There
should be exactly one routine in code that sets PSWE to a '1' to write flash bytes and one routine in
code that sets PSWE and PSEE both to a '1' to erase flash pages.
8. Minimize the number of variable accesses while PSWE is set to a 1. Handle pointer address
updates and loop variable maintenance outside the "PSWE = 1;... PSWE = 0;" area. Code
examples showing this can be found in “AN201: Writing to Flash From Firmware", available from
the Silicon Laboratories web site.
9. Disable interrupts prior to setting PSWE to a '1' and leave them disabled until after PSWE has
been reset to 0. Any interrupts posted during the flash write or erase operation will be serviced in
priority order after the flash operation has been completed and interrupts have been re-enabled by
software.
10. Make certain that the flash write and erase pointer variables are not located in XRAM. See your
compiler documentation for instructions regarding how to explicitly locate variables in different
memory areas.
11. Add address bounds checking to the routines that write or erase flash memory to ensure that a
routine called with an illegal address does not result in modification of the flash.
10.4.3. System Clock
12. If operating from an external crystal-based source, be advised that crystal performance is
susceptible to electrical interference and is sensitive to layout and to changes in temperature. If the
system is operating in an electrically noisy environment, use the internal oscillator or use an
external CMOS clock.
13. If operating from the external oscillator, switch to the internal oscillator during flash write or erase
operations. The external oscillator can continue to run, and the CPU can switch back to the
external oscillator after the flash operation has completed.
Additional flash recommendations and example code can be found in “AN201: Writing to Flash From
Firmware", available from the Silicon Laboratories website.
Rev. 1.1
65
C8051F85x/86x
10.5. Flash Control Registers
Register 10.1. PSCTL: Program Store Control
Bit
7
6
5
4
3
2
1
0
Name
Reserved
PSEE
PSWE
Type
R
RW
RW
0
0
Reset
0
0
0
0
0
0
SFR Address: 0x8F
Table 10.2. PSCTL Register Bit Descriptions
Bit
Name
7:2
Reserved
1
PSEE
Function
Must write reset value.
Program Store Erase Enable.
Setting this bit (in combination with PSWE) allows an entire page of flash program memory to be erased. If this bit is logic 1 and flash writes are enabled (PSWE is logic 1), a
write to flash memory using the MOVX instruction will erase the entire page that contains
the location addressed by the MOVX instruction. The value of the data byte written does
not matter.
0: Flash program memory erasure disabled.
1: Flash program memory erasure enabled.
0
PSWE
Program Store Write Enable.
Setting this bit allows writing a byte of data to the flash program memory using the MOVX
write instruction. The flash location should be erased before writing data.
0: Writes to flash program memory disabled.
1: Writes to flash program memory enabled; the MOVX write instruction targets flash
memory.
66
Rev. 1.1
C8051F85x/86x
Register 10.2. FLKEY: Flash Lock and Key
Bit
7
6
5
4
Name
FLKEY
Type
RW
Reset
0
0
0
0
3
2
1
0
0
0
0
0
SFR Address: 0xB7
Table 10.3. FLKEY Register Bit Descriptions
Bit
Name
7:0
FLKEY
Function
Flash Lock and Key Register.
Write:
This register provides a lock and key function for flash erasures and writes. Flash writes
and erases are enabled by writing 0xA5 followed by 0xF1 to the FLKEY register. Flash
writes and erases are automatically disabled after the next write or erase is complete. If
any writes to FLKEY are performed incorrectly, or if a flash write or erase operation is
attempted while these operations are disabled, the flash will be permanently locked from
writes or erasures until the next device reset. If an application never writes to flash, it can
intentionally lock the flash by writing a non-0xA5 value to FLKEY from software.
Read:
When read, bits 1-0 indicate the current flash lock state.
00: Flash is write/erase locked.
01: The first key code has been written (0xA5).
10: Flash is unlocked (writes/erases allowed).
11: Flash writes/erases are disabled until the next reset.
Rev. 1.1
67
C8051F85x/86x
11. Device Identification and Unique Identifier
The C8051F85x/86x has SFRs that identify the device family, derivative, and revision. These SFRs can be
read by firmware at runtime to determine the capabilities of the MCU that is executing code. This allows
the same firmware image to run on MCUs with different memory sizes and peripherals, and dynamically
change functionality to suit the capabilities of that MCU.
In addition to the device identification registers, a 32-bit unique identifier (UID) is pre-programmed into all
Revision C and later devices. The UID resides in the last four bytes of XRAM (C8051F850/1/3/4 and
C8051F860/1/3/4) or RAM (C8051F852/5 and C8051F862/5). For devices with the UID in RAM, the UID
can be read by firmware using indirect data accesses. For devices with the UID in XRAM, the UID can be
read by firmware using MOVX instructions. The UID can also be read through the debug port for all
devices.
Firmware can overwrite the UID during normal operation, and the bytes in memory will be automatically
reinitialized with the UID value after any device reset. Firmware using this area of memory should always
initialize the memory to a known value, as any previous data stored at these locations will be overwritten
and not retained through a reset.
Table 11.1. UID Implementation Information
68
Device
Memory Segment
Addresses
C8051F850
C8051F851
C8051F853
C8051F854
C8051F860
C8051F861
C8051F863
C8051F864
XRAM
(MSB) 0x00FF, 0x00FE, 0x00FD, 0x00FC (LSB)
C8051F852
C8051F855
C8051F862
C8051F865
RAM (indirect)
(MSB) 0xFF, 0xFE, 0xFD, 0xFC (LSB)
Rev. 1.1
C8051F85x/86x
11.1. Device Identification Registers
Register 11.1. DEVICEID: Device Identification
Bit
7
6
5
4
Name
DEVICEID
Type
R
Reset
0
0
1
1
3
2
1
0
0
0
0
0
SFR Address: 0xB5
Table 11.2. DEVICEID Register Bit Descriptions
Bit
Name
7:0
DEVICEID
Function
Device ID.
This read-only register returns the 8-bit device ID: 0x30 (C8051F85x/86x).
Rev. 1.1
69
C8051F85x/86x
Register 11.2. DERIVID: Derivative Identification
Bit
7
6
5
4
Name
DERIVID
Type
R
Reset
X
X
X
X
3
2
1
0
X
X
X
X
SFR Address: 0xAD
Table 11.3. DERIVID Register Bit Descriptions
Bit
Name
7:0
DERIVID
Function
Derivative ID.
This read-only register returns the 8-bit derivative ID, which can be used by firmware to
identify which device in the product family the code is executing on. The ‘{R}’ tag in the
part numbers below indicates the device revision letter in the ordering code.
0xD0: C8051F850-{R}-GU
0xD1: C8051F851-{R}-GU
0xD2: C8051F852-{R}-GU
0xD3: C8051F853-{R}-GU
0xD4: C8051F854-{R}-GU
0xD5: C8051F855-{R}-GU
0xE0: C8051F860-{R}-GS
0xE1: C8051F861-{R}-GS
0xE2: C8051F862-{R}-GS
0xE3: C8051F863-{R}-GS
0xE4: C8051F864-{R}-GS
0xE5: C8051F865-{R}-GS
0xF0: C8051F850-{R}-GM
0xF1: C8051F851-{R}-GM
0xF2: C8051F852-{R}-GM
0xF3: C8051F853-{R}-GM
0xF4: C8051F854-{R}-GM
0xF5: C8051F855-{R}-GM
70
Rev. 1.1
C8051F85x/86x
Register 11.3. REVID: Revision Identifcation
Bit
7
6
5
4
Name
REVID
Type
R
Reset
X
X
X
X
3
2
1
0
X
X
X
X
SFR Address: 0xB6
Table 11.4. REVID Register Bit Descriptions
Bit
Name
7:0
REVID
Function
Revision ID.
This read-only register returns the 8-bit revision ID.
00000000: Revision A
00000001: Revision B
00000010: Revision C
00000011-11111111: Reserved.
Rev. 1.1
71
C8051F85x/86x
12. Interrupts
The C8051F85x/86x includes an extended interrupt system supporting multiple interrupt sources with two
priority levels. The allocation of interrupt sources between on-chip peripherals and external input pins
varies according to the specific version of the device. Each interrupt source has one or more associated
interrupt-pending flag(s) located in an SFR. When a peripheral or external source meets a valid interrupt
condition, the associated interrupt-pending flag is set to logic 1.
If interrupts are enabled for the source, an interrupt request is generated when the interrupt-pending flag is
set. As soon as execution of the current instruction is complete, the CPU generates an LCALL to a
predetermined address to begin execution of an interrupt service routine (ISR). Each ISR must end with an
RETI instruction, which returns program execution to the next instruction that would have been executed if
the interrupt request had not occurred. If interrupts are not enabled, the interrupt-pending flag is ignored by
the hardware and program execution continues as normal. The interrupt-pending flag is set to logic 1
regardless of the interrupt's enable/disable state.
Each interrupt source can be individually enabled or disabled through the use of an associated interrupt
enable bit in an SFR (IE and EIE1). However, interrupts must first be globally enabled by setting the EA bit
in the IE register to logic 1 before the individual interrupt enables are recognized. Setting the EA bit to logic
0 disables all interrupt sources regardless of the individual interrupt-enable settings.
Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR.
However, most are not cleared by the hardware and must be cleared by software before returning from the
ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI)
instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after
the completion of the next instruction.
12.1. MCU Interrupt Sources and Vectors
The C8051F85x/86x MCUs support interrupt sources for each peripheral on the device. Software can
simulate an interrupt by setting any interrupt-pending flag to logic 1. If interrupts are enabled for the flag,
an interrupt request will be generated and the CPU will vector to the ISR address associated with the
interrupt-pending flag. MCU interrupt sources, associated vector addresses, priority order and control bits
are summarized in Table 12.1. Refer to the datasheet section associated with a particular on-chip
peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its
interrupt-pending flag(s).
12.1.1. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low
priority interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt
cannot be preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP or EIP1) used to
configure its priority level. Low priority is the default. If two interrupts are recognized simultaneously, the
interrupt with the higher priority is serviced first. If both interrupts have the same priority level, a fixed
priority order is used to arbitrate, given in Table 12.1.
12.1.2. Interrupt Latency
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5
system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the
ISR. If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL
is made to service the pending interrupt. Therefore, the maximum response time for an interrupt (when no
other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is
performing an RETI instruction followed by a DIV as the next instruction. In this case, the response time is
18 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the RETI, 8 clock
72
Rev. 1.1
C8051F85x/86x
cycles to complete the DIV instruction and 4 clock cycles to execute the LCALL to the ISR. If the CPU is
executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the
current ISR completes, including the RETI and following instruction. If more than one interrupt is pending
when the CPU exits an ISR, the CPU will service the next highest priority interrupt that is pending.
Rev. 1.1
73
C8051F85x/86x
Interrupt Source
Interrupt
Vector
Priority Pending Flags
Order
Bit addressable?
Cleared by HW?
Table 12.1. Interrupt Summary
Enable Flag
Reset
0x0000
Top
None
N/A
N/A
Always Enabled
External Interrupt 0 (INT0)
0x0003
0
IE0 (TCON.1)
Y
Y
EX0 (IE.0)
Timer 0 Overflow
0x000B
1
TF0 (TCON.5)
Y
Y
ET0 (IE.1)
External Interrupt 1 (INT1)
0x0013
2
IE1 (TCON.3)
Y
Y
EX1 (IE.2)
Timer 1 Overflow
0x001B
3
TF1 (TCON.7)
Y
Y
ET1 (IE.3)
UART0
0x0023
4
RI (SCON0.0)
TI (SCON0.1)
Y
N
ES0 (IE.4)
Timer 2 Overflow
0x002B
5
TF2H (TMR2CN.7)
TF2L (TMR2CN.6)
Y
N
ET2 (IE.5)
SPI0
0x0033
6
SPIF (SPI0CN.7)
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
RXOVRN (SPI0CN.4)
Y
N
ESPI0 (IE.6)
SMB0
0x003B
7
SI (SMB0CN.0)
Y
N
ESMB0 (EIE1.0)
Port Match
0x0043
8
None
N/A
N/A
EMAT (EIE1.1)
ADC0 Window Compare
0x004B
9
ADWINT (ADC0CN.3)
Y
N
EWADC0 (EIE1.2)
ADC0 Conversion Complete
0x0053
10
ADINT (ADC0CN.5)
Y
N
EADC0 (EIE1.3)
Programmable Counter
Array
0x005B
11
CF (PCA0CN.7)
CCFn (PCA0CN.n)
COVF (PCA0PWM.6)
Y
N
EPCA0 (EIE1.4)
Comparator0
0x0063
12
CPFIF (CPT0CN.4)
CPRIF (CPT0CN.5)
N
N
ECP0 (EIE1.5)
Comparator1
0x006B
13
CPFIF (CPT1CN.4)
CPRIF (CPT1CN.5)
N
N
ECP1 (EIE1.6)
Timer 3 Overflow
0x0073
14
TF3H (TMR3CN.7)
TF3L (TMR3CN.6)
N
N
ET3 (EIE1.7)
74
Rev. 1.1
C8051F85x/86x
12.2. Interrupt Control Registers
Register 12.1. IE: Interrupt Enable
Bit
7
6
5
4
3
2
1
0
Name
EA
ESPI0
ET2
ES0
ET1
EX1
ET0
EX0
Type
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
SFR Address: 0xA8 (bit-addressable)
Table 12.2. IE Register Bit Descriptions
Bit
Name
7
EA
Function
Enable All Interrupts.
Globally enables/disables all interrupts and overrides individual interrupt mask settings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
6
ESPI0
Enable SPI0 Interrupt.
This bit sets the masking of the SPI0 interrupts.
0: Disable all SPI0 interrupts.
1: Enable interrupt requests generated by SPI0.
5
ET2
Enable Timer 2 Interrupt.
This bit sets the masking of the Timer 2 interrupt.
0: Disable Timer 2 interrupt.
1: Enable interrupt requests generated by the TF2L or TF2H flags.
4
ES0
Enable UART0 Interrupt.
This bit sets the masking of the UART0 interrupt.
0: Disable UART0 interrupt.
1: Enable UART0 interrupt.
3
ET1
Enable Timer 1 Interrupt.
This bit sets the masking of the Timer 1 interrupt.
0: Disable all Timer 1 interrupt.
1: Enable interrupt requests generated by the TF1 flag.
2
EX1
Enable External Interrupt 1.
This bit sets the masking of External Interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the INT1 input.
1
ET0
Enable Timer 0 Interrupt.
This bit sets the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupt.
1: Enable interrupt requests generated by the TF0 flag.
Rev. 1.1
75
C8051F85x/86x
Table 12.2. IE Register Bit Descriptions
Bit
Name
0
EX0
Function
Enable External Interrupt 0.
This bit sets the masking of External Interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the INT0 input.
76
Rev. 1.1
C8051F85x/86x
Register 12.2. IP: Interrupt Priority
Bit
7
6
5
4
3
2
1
0
Name
Reserved
PSPI0
PT2
PS0
PT1
PX1
PT0
PX0
Type
R
RW
RW
RW
RW
RW
RW
RW
Reset
1
0
0
0
0
0
0
0
SFR Address: 0xB8 (bit-addressable)
Table 12.3. IP Register Bit Descriptions
Bit
Name
7
Reserved
6
PSPI0
Function
Must write reset value.
Serial Peripheral Interface (SPI0) Interrupt Priority Control.
This bit sets the priority of the SPI0 interrupt.
0: SPI0 interrupt set to low priority level.
1: SPI0 interrupt set to high priority level.
5
PT2
Timer 2 Interrupt Priority Control.
This bit sets the priority of the Timer 2 interrupt.
0: Timer 2 interrupt set to low priority level.
1: Timer 2 interrupt set to high priority level.
4
PS0
UART0 Interrupt Priority Control.
This bit sets the priority of the UART0 interrupt.
0: UART0 interrupt set to low priority level.
1: UART0 interrupt set to high priority level.
3
PT1
Timer 1 Interrupt Priority Control.
This bit sets the priority of the Timer 1 interrupt.
0: Timer 1 interrupt set to low priority level.
1: Timer 1 interrupt set to high priority level.
2
PX1
External Interrupt 1 Priority Control.
This bit sets the priority of the External Interrupt 1 interrupt.
0: External Interrupt 1 set to low priority level.
1: External Interrupt 1 set to high priority level.
1
PT0
Timer 0 Interrupt Priority Control.
This bit sets the priority of the Timer 0 interrupt.
0: Timer 0 interrupt set to low priority level.
1: Timer 0 interrupt set to high priority level.
0
PX0
External Interrupt 0 Priority Control.
This bit sets the priority of the External Interrupt 0 interrupt.
0: External Interrupt 0 set to low priority level.
1: External Interrupt 0 set to high priority level.
Rev. 1.1
77
C8051F85x/86x
Register 12.3. EIE1: Extended Interrupt Enable 1
Bit
7
6
5
4
3
2
1
0
Name
ET3
ECP1
ECP0
EPCA0
EADC0
EWADC0
EMAT
ESMB0
Type
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
SFR Address: 0xE6
Table 12.4. EIE1 Register Bit Descriptions
Bit
Name
7
ET3
Function
Enable Timer 3 Interrupt.
This bit sets the masking of the Timer 3 interrupt.
0: Disable Timer 3 interrupts.
1: Enable interrupt requests generated by the TF3L or TF3H flags.
6
ECP1
Enable Comparator1 (CP1) Interrupt.
This bit sets the masking of the CP1 interrupt.
0: Disable CP1 interrupts.
1: Enable interrupt requests generated by the comparator 1 CPRIF or CPFIF flags.
5
ECP0
Enable Comparator0 (CP0) Interrupt.
This bit sets the masking of the CP0 interrupt.
0: Disable CP0 interrupts.
1: Enable interrupt requests generated by the comparator 0 CPRIF or CPFIF flags.
4
EPCA0
Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts.
1: Enable interrupt requests generated by PCA0.
3
EADC0
Enable ADC0 Conversion Complete Interrupt.
This bit sets the masking of the ADC0 Conversion Complete interrupt.
0: Disable ADC0 Conversion Complete interrupt.
1: Enable interrupt requests generated by the ADINT flag.
2
EWADC0
Enable Window Comparison ADC0 Interrupt.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison interrupt.
1: Enable interrupt requests generated by ADC0 Window Compare flag (ADWINT).
1
EMAT
Enable Port Match Interrupts.
This bit sets the masking of the Port Match Event interrupt.
0: Disable all Port Match interrupts.
1: Enable interrupt requests generated by a Port Match.
78
Rev. 1.1
C8051F85x/86x
Table 12.4. EIE1 Register Bit Descriptions
Bit
Name
0
ESMB0
Function
Enable SMBus (SMB0) Interrupt.
This bit sets the masking of the SMB0 interrupt.
0: Disable all SMB0 interrupts.
1: Enable interrupt requests generated by SMB0.
Rev. 1.1
79
C8051F85x/86x
Register 12.4. EIP1: Extended Interrupt Priority 1
Bit
7
6
5
4
3
2
1
0
Name
PT3
PCP1
PCP0
PPCA0
PADC0
PWADC0
PMAT
PSMB0
Type
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
SFR Address: 0xF3
Table 12.5. EIP1 Register Bit Descriptions
Bit
Name
7
PT3
Function
Timer 3 Interrupt Priority Control.
This bit sets the priority of the Timer 3 interrupt.
0: Timer 3 interrupts set to low priority level.
1: Timer 3 interrupts set to high priority level.
6
PCP1
Comparator1 (CP1) Interrupt Priority Control.
This bit sets the priority of the CP1 interrupt.
0: CP1 interrupt set to low priority level.
1: CP1 interrupt set to high priority level.
5
PCP0
Comparator0 (CP0) Interrupt Priority Control.
This bit sets the priority of the CP0 interrupt.
0: CP0 interrupt set to low priority level.
1: CP0 interrupt set to high priority level.
4
PPCA0
Programmable Counter Array (PCA0) Interrupt Priority Control.
This bit sets the priority of the PCA0 interrupt.
0: PCA0 interrupt set to low priority level.
1: PCA0 interrupt set to high priority level.
3
PADC0
ADC0 Conversion Complete Interrupt Priority Control.
This bit sets the priority of the ADC0 Conversion Complete interrupt.
0: ADC0 Conversion Complete interrupt set to low priority level.
1: ADC0 Conversion Complete interrupt set to high priority level.
2
PWADC0
ADC0 Window Comparator Interrupt Priority Control.
This bit sets the priority of the ADC0 Window interrupt.
0: ADC0 Window interrupt set to low priority level.
1: ADC0 Window interrupt set to high priority level.
1
PMAT
Port Match Interrupt Priority Control.
This bit sets the priority of the Port Match Event interrupt.
0: Port Match interrupt set to low priority level.
1: Port Match interrupt set to high priority level.
80
Rev. 1.1
C8051F85x/86x
Table 12.5. EIP1 Register Bit Descriptions
Bit
Name
0
PSMB0
Function
SMBus (SMB0) Interrupt Priority Control.
This bit sets the priority of the SMB0 interrupt.
0: SMB0 interrupt set to low priority level.
1: SMB0 interrupt set to high priority level.
Rev. 1.1
81
C8051F85x/86x
13. Power Management and Internal Regulator
All internal circuitry on the C8051F85x/86x devices draws power from the VDD supply pin. Circuits with
external connections (I/O pins, analog muxes) are powered directly from the VDD supply voltage, while
most of the internal circuitry is supplied by an on-chip LDO regulator. The regulator output is fully internal to
the device, and is available also as an ADC input or reference source for the comparators and ADC.
The devices support the standard 8051 power modes: idle and stop. For further power savings in stop
mode, the internal LDO regulator may be disabled, shutting down the majority of the power nets on the
device.
Although the C8051F85x/86x has idle and stop modes available, more control over the device power can
be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral can be
disabled when not in use and placed in low power mode. Digital peripherals, such as timers and serial
buses, have their clocks gated off and draw little power when they are not in use.
13.1. Power Modes
Idle mode halts the CPU while leaving the peripherals and clocks active. In stop mode, the CPU is halted,
all interrupts and timers are inactive, and the internal oscillator is stopped (analog peripherals remain in
their selected states; the external oscillator is not affected). Since clocks are running in Idle mode, power
consumption is dependent upon the system clock frequency and the number of peripherals left in active
mode before entering Idle. Stop mode consumes the least power because the majority of the device is
shut down with no clocks active. The Power Control Register (PCON) is used to control the C8051F85x/
86x's Stop and Idle power management modes.
13.1.1. Idle Mode
Setting the Idle Mode Select bit (PCON.0) causes the hardware to halt the CPU and enter idle mode as
soon as the instruction that sets the bit completes execution. All internal registers and memory maintain
their original data. All analog and digital peripherals can remain active during idle mode.
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an
enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume
operation. The pending interrupt will be serviced and the next instruction to be executed after the return
from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit.
If idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence
and begins program execution at address 0x0000.
Note: If the instruction following the write of the IDLE bit is a single-byte instruction and an interrupt occurs during the
execution phase of the instruction that sets the IDLE bit, the CPU may not wake from Idle mode when a future
interrupt occurs. Therefore, instructions that set the IDLE bit should be followed by an instruction that has two
or more opcode bytes, for example:
// in ‘C’:
// set IDLE bit
PCON |= 0x01;
PCON = PCON;
// ... followed by a 3-cycle dummy instruction
; in assembly:
ORL PCON, #01h
MOV PCON, PCON
; set IDLE bit
; ... followed by a 3-cycle dummy instruction
If enabled, the Watchdog Timer (WDT) will eventually cause an internal watchdog reset and thereby
terminate the idle mode. This feature protects the system from an unintended permanent shutdown in the
event of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be
disabled by software prior to entering the Idle mode if the WDT was initially configured to allow this
operation. This provides the opportunity for additional power savings, allowing the system to remain in the
Idle mode indefinitely, waiting for an external stimulus to wake up the system.
82
Rev. 1.1
C8051F85x/86x
13.1.2. Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the controller core to enter stop mode as soon as the
instruction that sets the bit completes execution. Before entering stop mode, the system clock must be
sourced by the internal high-frequency oscillator. In stop mode the internal oscillator, CPU, and all digital
peripherals are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral
(including the external oscillator circuit) may be shut down individually prior to entering stop mode. Stop
mode can only be terminated by an internal or external reset. On reset, the device performs the normal
reset sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the stop mode.
The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the
MCD timeout.
13.2. LDO Regulator
C8051F85x/86x devices include an internal regulator that regulates the internal core and logic supply.
Under default conditions, the internal regulator will remain on when the device enters STOP mode. This
allows any enabled reset source to generate a reset for the device and bring the device out of STOP
mode. For additional power savings, the STOPCF bit can be used to shut down the regulator and the
internal power network of the device when the part enters STOP mode. When STOPCF is set to 1, the
RST pin and a full power cycle of the device are the only methods of generating a reset.
13.3. Power Control Registers
Register 13.1. PCON: Power Control
Bit
7
6
5
4
3
2
1
0
Name
GF
STOP
IDLE
Type
RW
RW
RW
0
0
Reset
0
0
0
0
0
0
SFR Address: 0x87
Table 13.1. PCON Register Bit Descriptions
Bit
Name
7:2
GF
Function
General Purpose Flags 5-0.
These are general purpose flags for use under software control.
1
STOP
Stop Mode Select.
Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0.
0
IDLE
Idle Mode Select.
Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0.
Rev. 1.1
83
C8051F85x/86x
13.4. LDO Control Registers
Register 13.2. REG0CN: Voltage Regulator Control
Bit
7
6
5
4
3
2
1
Name
Reserved
STOPCF
Reserved
Type
R
RW
R
Reset
0
0
0
0
0
0
0
0
0
SFR Address: 0xC9
Table 13.2. REG0CN Register Bit Descriptions
Bit
Name
Function
7:4
Reserved
Must write reset value.
3
STOPCF
Stop Mode Configuration.
This bit configures the regulator's behavior when the device enters stop mode.
0: Regulator is still active in stop mode. Any enabled reset source will reset the device.
1: Regulator is shut down in stop mode. Only the RST pin or power cycle can reset the
device.
2:0
84
Reserved
Must write reset value.
Rev. 1.1
C8051F85x/86x
14. Analog-to-Digital Converter (ADC0)
The ADC is a successive-approximation-register (SAR) ADC with 12-, 10-, and 8-bit modes, integrated
track-and-hold and a programmable window detector. These different modes allow the user to trade off
speed for resolution. ADC0 also has an autonomous low-power burst mode which can automatically
enable ADC0, capture and accumulate samples, then place ADC0 in a low power shutdown mode without
CPU intervention. It also has a 16-bit accumulator that can automatically oversample and average the
ADC results.
The ADC is fully configurable under software control via several registers. The ADC0 operates in singleended mode and may be configured to measure different signals using the analog multiplexer. The voltage
reference for the ADC is selectable between internal and external reference sources.
ADC0
Input
Selection
Control /
Configuration
P0 Pins (8)
Greater
Than
Less
Than
Window Compare
ADWINT
(Window Interrupt)
P1 Pins (8)
0.5x – 1x
gain
VDD
SAR Analog to
Digital Converter
Accumulator
GND
ADC0
ADINT
(Interrupt Flag)
Internal LDO
Temp
Sensor
ADBUSY (On Demand)
Timer 0 Overflow
1.65 V /
2.4 V
Reference
Internal LDO
VDD
VREF
Timer 2 Overflow
Timer 3 Overflow
CNVSTR (External Pin)
Trigger
Selection
Reference
Selection
Device Ground
AGND
SYSCLK
Clock
Divider
SAR clock
Figure 14.1. ADC0 Functional Block Diagram
Rev. 1.1
85
C8051F85x/86x
14.1. ADC0 Analog Multiplexer
ADC0 on C8051F85x/86x has an analog multiplexer capable of selecting any pin on ports P0 and P1 (up
to 16 total), the on-chip temperature sensor, the internal regulated supply, the VDD supply, or GND. ADC0
input channels are selected using the ADC0MX register.
Table 14.1. ADC0 Input Multiplexer Channels
ADC0MX setting
Signal Name
QSOP24 Pin Name
QFN20 Pin Name
SOIC16 Pin Name
00000
ADC0.0
P0.0
P0.0
P0.0
00001
ADC0.1
P0.1
P0.1
P0.1
00010
ADC0.2
P0.2
P0.2
P0.2
00011
ADC0.3
P0.3
P0.3
P0.3
00100
ADC0.4
P0.4
P0.4
P0.4
00101
ADC0.5
P0.5
P0.5
P0.5
00110
ADC0.6
P0.6
P0.6
P0.6
00111
ADC0.7
P0.7
P0.7
P0.7
01000
ADC0.8
P1.0
P1.0
P1.0
01001
ADC0.9
P1.1
P1.1
P1.1
01010
ADC0.10
P1.2
P1.2
P1.2
01011
ADC0.11
P1.3
P1.3
P1.3
01100
ADC0.12
P1.4
P1.4
Reserved
01101
ADC0.13
P1.5
P1.5
Reserved
01110
ADC0.14
P1.6
P1.6
Reserved
01111
ADC0.15
P1.7
Reserved
Reserved
10000
Temp Sensor
Internal Temperature Sensor
10001
LDO
Internal 1.8 V LDO Output
10010
VDD
VDD Supply Pin
10011
GND
GND Supply Pin
10100-11111
None
No connection
86
Rev. 1.1
C8051F85x/86x
Important note about ADC0 input configuration: Port pins selected as ADC0 inputs should be configured
as analog inputs, and should be skipped by the crossbar. To configure a Port pin for analog input, set to 0
the corresponding bit in register PnMDIN and disable the digital driver (PnMDOUT = 0 and Port Latch = 1).
To force the crossbar to skip a Port pin, set to 1 the corresponding bit in register PnSKIP.
Rev. 1.1
87
C8051F85x/86x
14.2. ADC Operation
The ADC is clocked by an adjustable conversion clock (SARCLK). SARCLK is a divided version of the
selected system clock when burst mode is disabled (ADBMEN = 0), or a divided version of the highfrequency oscillator when burst mode is enabled (ADBMEN = 1). The clock divide value is determined by
the ADSC bits in the ADC0CF register. In most applications, SARCLK should be adjusted to operate as
fast as possible, without exceeding the maximum electrical specifications. The SARCLK does not directly
determine sampling times or sampling rates.
14.2.1. Starting a Conversion
A conversion can be initiated in many ways, depending on the programmed states of the ADC0 Start of
Conversion Mode field (ADCM) in register ADC0CN0. Conversions may be initiated by one of the
following:
1. Writing a 1 to the ADBUSY bit of register ADC0CN0 (software-triggered)
2. A timer overflow (see the ADC0CN0 register and the timer section for timer options)
3. A rising edge on the CNVSTR input signal (external pin-triggered)
Writing a 1 to ADBUSY provides software control of ADC0 whereby conversions are performed "ondemand". All other trigger sources occur autonomous to code execution. When the conversion is
complete, the ADC posts the result to its output register and sets the ADC interrupt flag (ADINT). ADINT
may be used to trigger a system interrupts, if enabled, or polled by firmware.
During conversion, the ADBUSY bit is set to logic 1 and reset to logic 0 when the conversion is complete.
However, when polling for ADC conversion completions, the ADC0 interrupt flag (ADINT) should be used
instead of the ADBUSY bit. Converted data is available in the ADC0 data registers, ADC0H:ADC0L, when
the conversion is complete.
Important Note About Using CNVSTR: When the CNVSTR input is used as the ADC0 conversion
source, the associated port pin should be skipped in the crossbar settings.
14.2.2. Tracking Modes
Each ADC0 conversion must be preceded by a minimum tracking time in order for the converted result to
be accurate. The minimum tracking time is given in the electrical specifications tables. The ADTM bit in
register ADC0CN0 controls the ADC0 track-and-hold mode. In its default state when Burst Mode is
disabled, the ADC0 input is continuously tracked, except when a conversion is in progress. A conversion
will begin immediately when the start-of-conversion trigger occurs.
When the ADTM bit is logic 1, each conversion is preceded by a tracking period of 4 SAR clocks (after the
start-of-conversion signal) for any internal (non-CNVSTR) conversion trigger source. When the CNVSTR
signal is used to initiate conversions with ADTM set to 1, ADC0 tracks only when CNVSTR is low;
conversion begins on the rising edge of CNVSTR (see Figure 14.2). Setting ADTM to 1 is primarily useful
when AMUX settings are frequently changed and conversions are started using the ADBUSY bit.
88
Rev. 1.1
C8051F85x/86x
A. ADC0 Timing for External Trigger Source
CNVSTR
1
2
3
4
5
6
7
8
9 10 11 12 13 14
SAR Clocks
ADTM=1
ADTM=0
Low Power
or Convert
Track
Track or Convert
Convert
Low Power
Mode
Convert
Track
B. ADC0 Timing for Internal Trigger Source
Write '1' to ADBUSY,
Timer Overflow
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
SAR
Clocks
ADTM=1
Low Power
or Convert
Track
1
2
3
4
Convert
5
6
7
8
Low Power Mode
9 10 11 12 13 14
SAR
Clocks
ADTM=0
Track or
Convert
Convert
Track
Figure 14.2. 10-Bit ADC Track and Conversion Example Timing (ADBMEN = 0)
14.2.3. Burst Mode
Burst Mode is a power saving feature that allows ADC0 to remain in a low power state between
conversions. When Burst Mode is enabled, ADC0 wakes from a low power state, accumulates 1, 4, 8, 16,
32, or 64 samples using the internal low-power high-frequency oscillator, then re-enters a low power state.
Since the Burst Mode clock is independent of the system clock, ADC0 can perform multiple conversions
then enter a low power state within a single system clock cycle, even if the system clock is slow (e.g.
80 kHz).
Burst Mode is enabled by setting ADBMEN to logic 1. When in Burst Mode, ADEN controls the ADC0 idle
power state (i.e. the state ADC0 enters when not tracking or performing conversions). If ADEN is set to
logic 0, ADC0 is powered down after each burst. If ADEN is set to logic 1, ADC0 remains enabled after
each burst. On each convert start signal, ADC0 is awakened from its Idle Power State. If ADC0 is powered
down, it will automatically power up and wait the programmable Power-Up Time controlled by the ADPWR
bits. Otherwise, ADC0 will start tracking and converting immediately. Figure 14.3 shows an example of
Burst Mode Operation with a slow system clock and a repeat count of 4.
When Burst Mode is enabled, a single convert start will initiate a number of conversions equal to the repeat
count. When Burst Mode is disabled, a convert start is required to initiate each conversion. In both modes,
the ADC0 End of Conversion Interrupt Flag (ADINT) will be set after “repeat count” conversions have been
accumulated. Similarly, the Window Comparator will not compare the result to the greater-than and lessthan registers until “repeat count” conversions have been accumulated.
Rev. 1.1
89
C8051F85x/86x
In Burst Mode, tracking is determined by the settings in ADPWR and ADTK. Settling time requirements
may need adjustment in some applications. Refer to “14.2.4. Settling Time Requirements” on page 90 for
more details.
Notes:
Setting
ADTM to 1 will insert an additional 4 SAR clocks of tracking before each conversion,
regardless of the settings of ADPWR and ADTK.
When using Burst Mode, care must be taken to issue a convert start signal no faster than once
every four SYSCLK periods. This includes external convert start signals. The ADC will ignore
convert start signals which arrive before a burst is finished.
S yste m C lo ck
C o n ve rt S ta rt
ADTM = 1
ADEN = 0
P o w e re d
Down
P o w e r-U p
a n d T ra ck
T
4
ADTM = 0
ADEN = 0
P o w e re d
Down
P o w e r-U p
a n d T ra ck
C
C
T
T
C
T
4
C
T
T
C
ADPW R
T
4
T
C
T
T
4
C
C
P o w e re d
Down
P o w e re d
Down
P o w e r-U p
a n d T ra ck
T C ..
P o w e r-U p
a n d T ra ck
T C ..
ADTK
T = T ra ckin g se t b y A D T K
T 4 = T ra ckin g se t b y A D T M (4 S A R clo cks )
C = C o n ve rtin g
Figure 14.3. Burst Mode Tracking Example with Repeat Count Set to 4
14.2.4. Settling Time Requirements
A minimum amount of tracking time is required before each conversion can be performed, to allow the
sampling capacitor voltage to settle. This tracking time is determined by the AMUX0 resistance, the ADC0
sampling capacitance, any external source resistance, and the accuracy required for the conversion. Note
that when ADTM is set to 1, four SAR clocks are used for tracking at the start of every conversion. Large
external source impedance will increase the required tracking time.
Figure 14.4 shows the equivalent ADC0 input circuit. The required ADC0 settling time for a given settling
accuracy (SA) may be approximated by Equation 14.1. When measuring any internal source, RTOTAL
reduces to RMUX. See the electrical specification tables for ADC0 minimum settling time requirements as
well as the mux impedance and sampling capacitor values.
n
2
t = ln ------- R TOTAL C SAMPLE
SA
Equation 14.1. ADC0 Settling Time Requirements
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
RTOTAL is the sum of the AMUX0 resistance and any external source resistance.
90
Rev. 1.1
C8051F85x/86x
n is the ADC resolution in bits (8/10/12).
MUX Select
P0.x
R MUX
C SAMPLE
RCInput= R MUX * C SAMPLE
Note: The value of CSAMPLE depends on the PGA Gain. See electrical specifications for details.
Figure 14.4. ADC0 Equivalent Input Circuits
14.2.5. Gain Setting
The ADC has gain settings of 1x and 0.5x. In 1x mode, the full scale reading of the ADC is determined
directly by VREF. In 0.5x mode, the full-scale reading of the ADC occurs when the input voltage is
VREF x 2. The 0.5x gain setting can be useful to obtain a higher input voltage range when using a small
VREF voltage, or to measure input voltages that are between VREF and VDD. Gain settings for the ADC
are controlled by the ADGN bit in register ADC0CF. Note that even with a gain setting of 0.5, voltages
above the supply rail cannot be measured directly by the ADC.
14.3. 8-Bit Mode
Setting the ADC08BE bit in register ADC0CF to 1 will put the ADC in 8-bit mode. In 8-bit mode, only the
8 MSBs of data are converted, allowing the conversion to be completed in fewer SAR clock cycles than a
10-bit conversion. The two LSBs of a conversion are always 00 in this mode, and the ADC0L register will
always read back 0x00.
14.4. 12-Bit Mode
When configured for 12-bit conversions, the ADC performs four 10-bit conversions using four different
reference voltages and combines the results into a single 12-bit value. Unlike simple averaging
techniques, this method provides true 12-bit resolution of AC or DC input signals without depending on
noise to provide dithering. The converter also employs a hardware dynamic element matching algorithm
that reconfigures the largest elements of the internal DAC for each of the four 10-bit conversions. This
reconfiguration cancels any matching errors and enables the converter to achieve 12-bit linearity
performance to go along with its 12-bit resolution.
The 12-bit mode is enabled by setting the AD12BE bit in register ADC0AC to logic 1 and configuring the
ADC in burst mode (ADBMEN = 1) for four or more conversions. The conversion can be initiated using any
of the conversion start sources, and the 12-bit result will appear in the ADC0H and ADC0L registers. Since
the 12-bit result is formed from a combination of four 10-bit results, the maximum output value is 4 x (1023)
= 4092, rather than the max value of (2^12 – 1) = 4095 that is produced by a traditional 12-bit converter. To
further increase resolution, the burst mode repeat value may be configured to any multiple of four
conversions. For example, if a repeat value of 16 is selected, the ADC0 output will be a 14-bit number
(sum of four 12-bit numbers) with 13 effective bits of resolution.
The AD12SM bit in register ADC0TK controls when the ADC will track and sample the input signal. When
AD12SM is set to 1, the selected input signal will be tracked before the first conversion of a set and held
internally during all four conversions. When AD12SM is cleared to 0, the ADC will track and sample the
selected input before each of the four conversions in a set. When maximum throughput (180-200 ksps) is
Rev. 1.1
91
C8051F85x/86x
needed, it is recommended that AD12SM be set to 1 and ADTK to 0x3F, and that the ADC be placed in
always-on mode (ADEN = 1). For sample rates under 180 ksps, or when accumulating multiple samples,
AD12SM should normally be cleared to 0, and ADTK should be configured to provide the appropriate
settling time for the subsequent conversions.
14.5. Power Considerations
The ADC has several power-saving features which can help the user optimize power consumption
according to the needs of the application. The most efficient way to use the ADC for slower sample rates is
by using burst mode. Burst mode dynamically controls power to the ADC and (if used) the internal voltage
reference. By completely powering off these circuits when the ADC is not tracking or converting, the
average supply current required for lower sampling rates is reduced significantly.
The ADC also provides low power options that allow reduction in operating current when operating at low
SAR clock frequencies or with longer tracking times. The internal common-mode buffer can be configured
for low power mode by setting the ADLPM bit in ADC0PWR to 1. Two other fields in the ADC0PWR
register (ADBIAS and ADMXLP) may be used together to adjust the power consumed by the ADC and its
multiplexer and reference buffers, respectively. In general, these options are used together, when
operating with a SAR conversion clock frequency of 4 MHz.
Table 14.2. ADC0 Optimal Power Configuration (8- and 10-bit Mode)
Required
Throughput
Reference Source Mode Configuration
SAR Clock Speed
Other Register Field
Settings
325-800 ksps
Any
Always-On
(ADEN = 1
ADBMEN = 0)
12.25 MHz
(ADSC = 1)
ADC0PWR = 0x40
ADC0TK = N/A
ADRPT = 0
0-325 ksps
External
Burst Mode
(ADEN = 0
ADBMEN = 1)
12.25 MHz
(ADSC = 1)
ADC0PWR = 0x44
ADC0TK = 0x3A
ADRPT = 0
250-325 ksps
Internal
Burst Mode
(ADEN = 0
ADBMEN = 1)
12.25 MHz
(ADSC = 1)
ADC0PWR = 0x44
ADC0TK = 0x3A
ADRPT = 0
200-250 ksps
Internal
Always-On
(ADEN = 1
ADBMEN = 0)
4.08 MHz
(ADSC = 5)
ADC0PWR = 0xF0
ADC0TK = N/A
ADRPT = 0
0-200 ksps
Internal
Burst Mode
(ADEN = 0
ADBMEN = 1)
4.08 MHz
(ADSC = 5)
ADC0PWR = 0xF4
ADC0TK = 0x34
ADRPT = 0
Notes:
1. For always-on configuration, ADSC settings assume SYSCLK is the internal 24.5 MHz high-frequency oscillator.
Adjust ADSC as needed if using a different source for SYSCLK.
2. ADRPT reflects the minimum setting for this bit field. When using the ADC in Burst Mode, up to 64 samples may be
auto-accumulated per conversion start by adjusting ADRPT.
92
Rev. 1.1
C8051F85x/86x
Table 14.3. ADC0 Optimal Power Configuration (12-bit Mode)
Required
Throughput
Reference Source Mode Configuration
SAR Clock Speed
Other Register Field
Settings
Any
Always-On +
Burst Mode
(ADEN = 1
ADBMEN = 1)
12.25 MHz
(ADSC = 1)
ADC0PWR = 0x40
ADC0TK = 0xBF
ADRPT = 1
125-180 ksps
Any
Always-On +
Burst Mode
(ADEN = 1
ADBMEN = 1)
12.25 MHz
(ADSC = 1)
ADC0PWR = 0x40
ADC0TK = 0x3A
ADRPT = 1
0-125 ksps
External
Burst Mode
(ADEN = 0
ADBMEN = 1)
12.25 MHz
(ADSC = 1)
ADC0PWR = 0x44
ADC0TK = 0x3A
ADRPT = 1
50-125 ksps
Internal
Burst Mode
(ADEN = 0
ADBMEN = 1)
12.25 MHz
(ADSC = 1)
ADC0PWR = 0x44
ADC0TK = 0x3A
ADRPT = 1
0-50 ksps
Internal
Burst Mode
(ADEN = 0
ADBMEN = 1)
4.08 MHz
(ADSC = 5)
ADC0PWR = 0xF4
ADC0TK = 0x34
ADRPT = 1
180-200 ksps
Note: ADRPT reflects the minimum setting for this bit field. When using the ADC in Burst Mode, up to 64 samples may be
auto-accumulated per conversion trigger by adjusting ADRPT.
For applications where burst mode is used to automatically accumulate multiple results, additional supply
current savings can be realized. The length of time the ADC is active during each burst contains power-up
time at the beginning of the burst as well as the conversion time required for each conversion in the burst.
The power-on time is only required at the beginning of each burst. When compared with single-sample
bursts to collect the same number of conversions, multi-sample bursts will consume significantly less
power. For example, performing an eight-cycle burst of 10-bt conversions consumes about 61% of the
power required to perform those same eight samples in single-cycle bursts. For 12-bit conversions, an
eight-cycle burst results in about 85% of the equivalent single-cycle bursts. Figure 14.5 shows this
relationship for the different burst cycle lengths.
See the Electrical Characteristics chapter for details on power consumption and the maximum clock
frequencies allowed in each mode.
Rev. 1.1
93
C8051F85x/86x
10ͲBitBurstModePower
12ͲBitBurstModePower
100%
AverageCurrentComparedtoSingleͲCycle
AverageCurrentComparedtoSingleͲCycle
100%
95%
90%
85%
80%
75%
70%
65%
60%
55%
50%
98%
96%
94%
92%
90%
88%
86%
84%
82%
80%
1
2
4
8
16
32
64
1
NumberofCyclesAccumulatedinBurst
2
4
8
NumberofCyclesAccumulatedinBurst
Figure 14.5. Burst Mode Accumulation Power Savings
14.6. Output Code Formatting
The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code from the
ADC at the completion of each conversion. Data can be right-justified or left-justified, depending on the
setting of the ADSJST field. When the repeat count is set to 1 in 10-bit mode, conversion codes are
represented as 10-bit unsigned integers. Inputs are measured from 0 to VREF x 1023/1024. Example
codes are shown below for both right-justified and left-justified data. Unused bits in the ADC0H and ADC0L
registers are set to 0.
Input Voltage
Right-Justified
Left-Justified
ADC0H:ADC0L (ADSJST = 000)
ADC0H:ADC0L (ADSJST = 100)
VREF x 1023/1024
0x03FF
0xFFC0
VREF x 512/1024
0x0200
0x8000
VREF x 256/1024
0x0100
0x4000
0
0x0000
0x0000
When the repeat count is greater than 1, the output conversion code represents the accumulated result of
the conversions performed and is updated after the last conversion in the series is finished. Sets of 4, 8,
16, 32, or 64 consecutive samples can be accumulated and represented in unsigned integer format. The
repeat count can be selected using the ADRPT bits in the ADC0AC register. When a repeat count is higher
than 1, the ADC output must be right-justified (ADSJST = 0xx); unused bits in the ADC0H and ADC0L
registers are set to 0. The example below shows the right-justified result for various input voltages and
repeat counts. Notice that accumulating 2n samples is equivalent to left-shifting by n bit positions when all
samples returned from the ADC have the same value.
Input Voltage
Repeat Count = 4
Repeat Count = 16
Repeat Count = 64
VREF x 1023/1024
0x0FFC
0x3FF0
0xFFC0
VREF x 512/1024
0x0800
0x2000
0x8000
VREF x 511/1024
0x07FC
0x1FF0
0x7FC0
0
0x0000
0x0000
0x0000
94
Rev. 1.1
16
C8051F85x/86x
The ADSJST bits can be used to format the contents of the 16-bit accumulator. The accumulated result
can be shifted right by 1, 2, or 3 bit positions. Based on the principles of oversampling and averaging, the
effective ADC resolution increases by 1 bit each time the oversampling rate is increased by a factor of 4.
The example below shows how to increase the effective ADC resolution by 1, 2, and 3 bits to obtain an
effective ADC resolution of 11-bit, 12-bit, or 13-bit respectively without CPU intervention.
Input Voltage
Repeat Count = 4
Repeat Count = 16
Repeat Count = 64
Shift Right = 1
Shift Right = 2
Shift Right = 3
11-Bit Result
12-Bit Result
13-Bit Result
VREF x 1023/1024
0x07F7
0x0FFC
0x1FF8
VREF x 512/1024
0x0400
0x0800
0x1000
VREF x 511/1024
0x03FE
0x04FC
0x0FF8
0
0x0000
0x0000
0x0000
14.7. Programmable Window Detector
The ADC Programmable Window Detector continuously compares the ADC0 output registers to userprogrammed limits, and notifies the system when a desired condition is detected. This is especially
effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster
system response times. The window detector interrupt flag (ADWINT in register ADC0CN0) can also be
used in polled mode. The ADC0 Greater-Than (ADC0GTH, ADC0GTL) and Less-Than (ADC0LTH,
ADC0LTL) registers hold the comparison values. The window detector flag can be programmed to indicate
when measured data is inside or outside of the user-programmed limits, depending on the contents of the
ADC0 Less-Than and ADC0 Greater-Than registers.
14.7.1. Window Detector In Single-Ended Mode
Figure 14.6
shows
two
example
window
comparisons
for
right-justified
data,
with
ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). The input voltage can
range from 0 to VREF x (1023/1024) with respect to GND, and is represented by a 10-bit unsigned integer
value. In the left example, an ADWINT interrupt will be generated if the ADC0 conversion word
(ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL
(if 0x0040 < ADC0H:ADC0L < 0x0080). In the right example, and ADWINT interrupt will be generated if
the ADC0 conversion word is outside of the range defined by the ADC0GT and ADC0LT registers
(if ADC0H:ADC0L < 0x0040 or ADC0H:ADC0L > 0x0080). Figure 14.7 shows an example using leftjustified data with the same comparison values.
Rev. 1.1
95
C8051F85x/86x
ADC0H:ADC0L
ADC0H:ADC0L
Input Voltage
(Px.x - GND)
VREF x (1023/
1024)
Input Voltage
(Px.x - GND)
VREF x (1023/
1024)
0x03FF
0x03FF
ADWINT
not affected
ADWINT=1
0x0081
VREF x (128/1024)
0x0080
0x007F
0x0081
ADC0LTH:ADC0LTL
VREF x (128/1024)
0x0080
0x007F
ADWINT=1
VREF x (64/1024)
0x0041
0x0040
ADC0GTH:ADC0GTL
VREF x (64/1024)
0x003F
0x0041
0x0040
ADC0GTH:ADC0GTL
ADWINT
not affected
ADC0LTH:ADC0LTL
0x003F
ADWINT=1
ADWINT
not affected
0x0000
0
0
0x0000
Figure 14.6. ADC Window Compare Example: Right-Justified Single-Ended Data
ADC0H:ADC0L
ADC0H:ADC0L
Input Voltage
(Px.x - GND)
VREF x (1023/
1024)
Input Voltage
(Px.x - GND)
VREF x (1023/
1024)
0xFFC0
0xFFC0
ADWINT
not affected
ADWINT=1
0x2040
VREF x (128/1024)
0x2000
0x1FC0
0x2040
ADC0LTH:ADC0LTL
VREF x (128/1024)
0x2000
0x1FC0
ADWINT=1
0x1040
VREF x (64/1024)
0x1000
0x1040
ADC0GTH:ADC0GTL
VREF x (64/1024)
0x0FC0
0x1000
ADC0GTH:ADC0GTL
ADWINT
not affected
ADC0LTH:ADC0LTL
0x0FC0
ADWINT=1
ADWINT
not affected
0
0x0000
0
0x0000
Figure 14.7. ADC Window Compare Example: Left-Justified Single-Ended Data
96
Rev. 1.1
C8051F85x/86x
14.8. Voltage and Ground Reference Options
The voltage reference multiplexer is configurable to use an externally connected voltage reference, the
internal voltage reference, or one of two power supply voltages. The ground reference mux allows the
ground reference for ADC0 to be selected between the ground pin (GND) or a port pin dedicated to analog
ground (AGND).
The voltage and ground reference options are configured using the REF0CN register.
Important Note About the VREF and AGND Inputs: Port pins are used as the external VREF and AGND
inputs. When using an external voltage reference, VREF should be configured as an analog input and
skipped by the digital crossbar. When using AGND as the ground reference to ADC0, AGND should be
configured as an analog input and skipped by the Digital Crossbar.
14.8.1. External Voltage Reference
To use an external voltage reference, REFSL should be set to 00. Bypass capacitors should be added as
recommended by the manufacturer of the external voltage reference. If the manufacturer does not provide
recommendations, a 4.7uF in parallel with a 0.1uF capacitor is recommended.
14.8.2. Internal Voltage Reference
For applications requiring the maximum number of port I/O pins, or very short VREF turn-on time, the highspeed reference will be the best internal reference option to choose. The internal reference is selected by
setting REFSL to 11. When selected, the internal reference will be automatically enabled/disabled on an
as-needed basis by the ADC. The reference can be set to one of two voltage values: 1.65 V or 2.4 V,
depending on the value of the IREFLVL bit.
For applications with a non-varying power supply voltage, using the power supply as the voltage reference
can provide the ADC with added dynamic range at the cost of reduced power supply noise rejection. To
use the external supply pin (VDD) or the 1.8 V regulated digital supply voltage as the reference source,
REFSL should be set to 01 or 10, respectively.
Internal reference sources are not routed to the VREF pin, and do not require external capacitors. The
electrical specifications tables detail SAR clock and throughput limitations for each reference source.
14.8.3. Analog Ground Reference
To prevent ground noise generated by switching digital logic from affecting sensitive analog
measurements, a separate analog ground reference option is available. When enabled, the ground
reference for the ADC during both the tracking/sampling and the conversion periods is taken from the
AGND pin. Any external sensors sampled by the ADC should be referenced to the AGND pin. If an
external voltage reference is used, the AGND pin should be connected to the ground of the external
reference and its associated decoupling capacitor. The separate analog ground reference option is
enabled by setting GNDSL to 1. Note that when sampling the internal temperature sensor, the internal chip
ground is always used for the sampling operation, regardless of the setting of the GNDSL bit. Similarly,
whenever the internal 1.65 V high-speed reference is selected, the internal chip ground is always used
during the conversion period, regardless of the setting of the GNDSL bit.
Rev. 1.1
97
C8051F85x/86x
14.9. Temperature Sensor
An on-chip temperature sensor is included, which can be directly accessed via the ADC multiplexer in
single-ended configuration. To use the ADC to measure the temperature sensor, the ADC mux channel
should select the temperature sensor. The temperature sensor transfer function is shown in Figure 14.8.
The output voltage (VTEMP) is the positive ADC input when the ADC multiplexer is set correctly. The
TEMPE bit in register REF0CN enables/disables the temperature sensor. While disabled, the temperature
sensor defaults to a high impedance state and any ADC measurements performed on the sensor will result
in meaningless data. Refer to the electrical specification tables for the slope and offset parameters of the
temperature sensor.
VTEMP = (Slope x TempC) + Offset
TempC = (VTEMP - Offset) / Slope
Voltage
Slope (V / deg C)
Offset (V at 0 Celsius)
Temperature
Figure 14.8. Temperature Sensor Transfer Function
14.9.1. Calibration
The uncalibrated temperature sensor output is extremely linear and suitable for relative temperature
measurements. For absolute temperature measurements, offset and/or gain calibration is recommended.
Typically a 1-point (offset) calibration includes the following steps:
1. Control/measure the ambient temperature (this temperature must be known).
2. Power the device, and delay for a few seconds to allow for self-heating.
3. Perform an ADC conversion with the temperature sensor selected as the ADC input.
4. Calculate the offset characteristics, and store this value in non-volatile memory for use with
subsequent temperature sensor measurements.
98
Rev. 1.1
C8051F85x/86x
14.10. ADC Control Registers
Register 14.1. ADC0CN0: ADC0 Control 0
Bit
7
6
5
4
3
2
Name
ADEN
ADBMEN
ADINT
ADBUSY
ADWINT
ADCM
Type
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
1
0
0
0
SFR Address: 0xE8 (bit-addressable)
Table 14.4. ADC0CN0 Register Bit Descriptions
Bit
Name
7
ADEN
Function
Enable.
0: ADC0 Disabled (low-power shutdown).
1: ADC0 Enabled (active and ready for data conversions).
6
ADBMEN
Burst Mode Enable.
0: ADC0 Burst Mode Disabled.
1: ADC0 Burst Mode Enabled.
5
ADINT
Conversion Complete Interrupt Flag.
Set by hardware upon completion of a data conversion (ADBMEN=0), or a burst of conversions (ADBMEN=1). Can trigger an interrupt. Must be cleared by software.
4
ADBUSY
ADC Busy.
Writing 1 to this bit initiates an ADC conversion when ADC0CM = 000. This bit should not
be polled to indicate when a conversion is complete. Instead, the ADINT bit should be
used when polling for conversion completion.
3
ADWINT
Window Compare Interrupt Flag.
Set by hardware when the contents of ADC0H:ADC0L fall within the window specified by
ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL. Can trigger an interrupt. Must be
cleared by software.
2:0
ADCM
Start of Conversion Mode Select.
Specifies the ADC0 start of conversion source. All remaining bit combinations are
reserved.
000: ADC0 conversion initiated on write of 1 to ADBUSY.
001: ADC0 conversion initiated on overflow of Timer 0.
010: ADC0 conversion initiated on overflow of Timer 2.
011: ADC0 conversion initiated on overflow of Timer 3.
100: ADC0 conversion initiated on rising edge of CNVSTR.
101-111: Reserved.
Rev. 1.1
99
C8051F85x/86x
Register 14.2. ADC0CN1: ADC0 Control 1
Bit
7
6
5
4
3
2
1
0
Name
Reserved
ADCMBE
Type
R
RW
Reset
0
0
0
0
0
0
0
0
SFR Address: 0xB2
Table 14.5. ADC0CN1 Register Bit Descriptions
Bit
Name
Function
7:1
Reserved
Must write reset value.
0
ADCMBE
Common Mode Buffer Enable.
0: Disable the common mode buffer. This setting should be used only if the tracking time
of the signal is greater than 1.5 us.
1: Enable the common mode buffer. This setting should be used in most cases, and will
give the best dynamic ADC performance. The common mode buffer must be enabled if
signal tracking time is less than or equal to 1.5 us.
100
Rev. 1.1
C8051F85x/86x
Register 14.3. ADC0CF: ADC0 Configuration
Bit
7
6
5
4
3
2
1
0
Name
ADSC
AD8BE
ADTM
ADGN
Type
RW
RW
RW
RW
0
0
0
Reset
1
1
1
1
1
SFR Address: 0xBC
Table 14.6. ADC0CF Register Bit Descriptions
Bit
Name
7:3
ADSC
Function
SAR Clock Divider.
This field sets the ADC clock divider value. It should be configured to be as close to the
maximum SAR clock speed as the datasheet will allow. The SAR clock frequency is
given by the following equation:
F ADCCLK
F CLKSAR = ------------------------ADSC + 1
FADCCLK is equal to the selected SYSCLK when ADBMEN is 0 and the high-frequency
oscillator when ADBMEN is 1.
2
AD8BE
8-Bit Mode Enable.
0: ADC0 operates in 10-bit or 12-bit mode (normal operation).
1: ADC0 operates in 8-bit mode.
1
ADTM
Track Mode.
Selects between Normal or Delayed Tracking Modes.
0: Normal Track Mode. When ADC0 is enabled, conversion begins immediately following
the start-of-conversion signal.
1: Delayed Track Mode. When ADC0 is enabled, conversion begins 4 SAR clock cycles
following the start-of-conversion signal. The ADC is allowed to track during this time.
0
ADGN
Gain Control.
0: The on-chip PGA gain is 0.5.
1: The on-chip PGA gain is 1.
Rev. 1.1
101
C8051F85x/86x
Register 14.4. ADC0AC: ADC0 Accumulator Configuration
Bit
7
6
5
Name
AD12BE
ADAE
ADSJST
ADRPT
Type
RW
RW
RW
RW
Reset
0
0
0
4
0
3
0
2
0
1
0
0
0
SFR Address: 0xB3
Table 14.7. ADC0AC Register Bit Descriptions
Bit
Name
7
AD12BE
Function
12-Bit Mode Enable.
Enables 12-bit Mode. In 12-bit mode, the ADC throughput is reduced by a factor of 4.
0: 12-bit Mode Disabled.
1: 12-bit Mode Enabled.
6
ADAE
Accumulate Enable.
Enables multiple conversions to be accumulated when burst mode is disabled.
0: ADC0H:ADC0L contain the result of the latest conversion when Burst Mode is disabled.
1: ADC0H:ADC0L contain the accumulated conversion results when Burst Mode is disabled. Software must write 0x0000 to ADC0H:ADC0L to clear the accumulated result.
5:3
ADSJST
Accumulator Shift and Justify.
Specifies the format of data read from ADC0H:ADC0L. All remaining bit combinations
are reserved.
000: Right justified. No shifting applied.
001: Right justified. Shifted right by 1 bit.
010: Right justified. Shifted right by 2 bits.
011: Right justified. Shifted right by 3 bits.
100: Left justified. No shifting applied.
101-111: Reserved.
2:0
ADRPT
Repeat Count.
Selects the number of conversions to perform and accumulate in Burst Mode. This bit
field must be set to 000 if Burst Mode is disabled.
000: Perform and Accumulate 1 conversion (not used in 12-bit mode).
001: Perform and Accumulate 4 conversions (1 conversion in 12-bit mode).
010: Perform and Accumulate 8 conversions (2 conversions in 12-bit mode).
011: Perform and Accumulate 16 conversions (4 conversions in 12-bit mode).
100: Perform and Accumulate 32 conversions (8 conversions in 12-bit mode).
101: Perform and Accumulate 64 conversions (16 conversions in 12-bit mode).
110-111: Reserved.
102
Rev. 1.1
C8051F85x/86x
Register 14.5. ADC0PWR: ADC0 Power Control
Bit
7
6
5
4
3
2
Name
ADBIAS
ADMXLP
ADLPM
ADPWR
Type
RW
RW
RW
RW
0
0
Reset
0
0
1
1
1
0
1
1
SFR Address: 0xDF
Table 14.8. ADC0PWR Register Bit Descriptions
Bit
Name
7:6
ADBIAS
Function
Bias Power Select.
This field can be used to adjust the ADC's power consumption based on the conversion
speed. Higher bias currents allow for faster conversion times.
00: Select bias current mode 0. Recommended to use modes 1, 2, or 3.
01: Select bias current mode 1 (SARCLK CP1N.
5
CPRIF
Comparator 1 Rising-Edge Flag. Must be cleared by software.
0: No Comparator Rising Edge has occurred since this flag was last cleared.
1: Comparator Rising Edge has occurred.
4
CPFIF
Comparator 1 Falling-Edge Flag. Must be cleared by software.
0: No Comparator Falling Edge has occurred since this flag was last cleared.
1: Comparator Falling Edge has occurred.
3:2
CPHYP
Comparator 1 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 mV.
1:0
CPHYN
Comparator 1 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 mV.
Rev. 1.1
137
C8051F85x/86x
Register 17.5. CPT1MD: Comparator 1 Mode
Bit
7
6
5
4
3
2
Name
CPLOUT
Reserved
CPRIE
CPFIE
Reserved
CPMD
Type
RW
R
RW
RW
R
RW
Reset
0
0
0
0
0
0
1
0
1
0
SFR Address: 0xAB
Table 17.9. CPT1MD Register Bit Descriptions
Bit
Name
7
CPLOUT
Function
Comparator 1 Latched Output Flag.
This bit represents the comparator output value at the most recent PCA counter overflow.
0: Comparator output was logic low at last PCA overflow.
1: Comparator output was logic high at last PCA overflow.
6
Reserved
5
CPRIE
Must write reset value.
Comparator 1 Rising-Edge Interrupt Enable.
0: Comparator Rising-Edge interrupt disabled.
1: Comparator Rising-Edge interrupt enabled.
4
CPFIE
Comparator 1 Falling-Edge Interrupt Enable.
0: Comparator Falling-Edge interrupt disabled.
1: Comparator Falling-Edge interrupt enabled.
3:2
Reserved
1:0
CPMD
Must write reset value.
Comparator 1 Mode Select.
These bits affect the response time and power consumption of the comparator.
00: Mode 0 (Fastest Response Time, Highest Power Consumption)
01: Mode 1
10: Mode 2
11: Mode 3 (Slowest Response Time, Lowest Power Consumption)
138
Rev. 1.1
C8051F85x/86x
Register 17.6. CPT1MX: Comparator 1 Multiplexer Selection
Bit
7
6
5
4
3
2
Name
CMXN
CMXP
Type
RW
RW
Reset
1
1
1
1
1
1
1
0
1
1
SFR Address: 0xAA
Table 17.10. CPT1MX Register Bit Descriptions
Bit
Name
7:4
CMXN
Function
Comparator 1 Negative Input MUX Selection.
0000: External pin CP1N.0
0001: External pin CP1N.1
0010: External pin CP1N.2
0011: External pin CP1N.3
0100: External pin CP1N.4
0101: External pin CP1N.5
0110: External pin CP1N.6
0111: External pin CP1N.7
1000: GND
1001-1111: Reserved.
3:0
CMXP
Comparator 1 Positive Input MUX Selection.
0000: External pin CP1P.0
0001: External pin CP1P.1
0010: External pin CP1P.2
0011: External pin CP1P.3
0100: External pin CP1P.4
0101: External pin CP1P.5
0110: External pin CP1P.6
0111: External pin CP1P.7
1000: Internal LDO output
1001-1111: Reserved.
Rev. 1.1
139
C8051F85x/86x
18. Cyclic Redundancy Check Unit (CRC0)
C8051F85x/86x devices include a cyclic redundancy check unit (CRC0) that can perform a CRC using a
16-bit polynomial. CRC0 accepts a stream of 8-bit data written to the CRC0IN register. CRC0 posts the 16bit result to an internal register. The internal result register may be accessed indirectly using the CRCPNT
bits and CRC0DAT register, as shown in Figure 18.1. CRC0 also has a bit reverse register for quick data
manipulation.
CRC0
CRC0IN
Flash
Memory
Automatic
flash read
control
8
8
CRC0FLIP
Seed
(0x0000 or
0xFFFF)
8
byte-level bit
reversal
Hardware CRC
Calculation
Unit
8
8
8
CRC0DAT
Figure 18.1. CRC0 Block Diagram
18.1. CRC Algorithm
The CRC unit generates a CRC result equivalent to the following algorithm:
1. XOR the input with the most-significant bits of the current CRC result. If this is the first iteration of
the CRC unit, the current CRC result will be the set initial value (0x0000 or 0xFFFF).
2a. If the MSB of the CRC result is set, shift the CRC result and XOR the result with the selected
polynomial.
2b. If the MSB of the CRC result is not set, shift the CRC result.
Repeat Steps 2a/2b for the number of input bits (8). The algorithm is also described in the following
example.
140
Rev. 1.1
C8051F85x/86x
The 16-bit CRC algorithm can be described by the following code:
unsigned short UpdateCRC (unsigned short CRC_acc, unsigned char CRC_input)
{
unsigned char i;
// loop counter
#define POLY 0x1021
// Create the CRC "dividend" for polynomial arithmetic (binary arithmetic
// with no carries)
CRC_acc = CRC_acc ^ (CRC_input
工商网监
湘ICP备2023018690号
