C8051F920-F-GQR

C8051F93x-C8051F92x Single/Dual Battery, 0.9–3.6 V, 64/32 kB, SmaRTClock, 10-Bit ADC MCU Supply Voltage 0.9 to 3.6 V - One-Cell Mode supports 0.9 to 1.8 V operation - Two-Cell Mode supports 1.8 to 3.6 V operation - Built-in dc-dc converter with 1.8 to 3.3 V output for High-Speed 8051 µC Core - Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks use in one-cell mode Built-in LDO regulator allows a high analog supply voltage and low digital core voltage - 2 built in supply monitors (brownout detectors) 10-Bit Analog to Digital Converter - ±1 LSB INL; no missing codes - Programmable throughput up to 300 ksps - Up to 23 external inputs - On-Chip Voltage Reference - On-Chip PGA allows measuring voltages up to twice the reference voltage - 16-bit Auto-Averaging Accumulator with Burst Mode provides increased ADC resolution - Data dependent windowed interrupt generator - Built-in temperature sensor - Two Comparators - Programmable hysteresis and response time - Configurable as wake-up or reset source - Up to 23 Capacitive Touch Sense Inputs 6-Bit Programmable Current Reference - Up to ±500 µA. Can be used as a bias or for - supports UART operation; 20 MHz low power oscillator requires very little bias current External oscillator: Crystal, RC, C, or CMOS Clock SmaRTClock oscillator: 32 kHz Crystal or internal self-oscillate mode Can switch between clock sources on-the-fly; useful in implementing various power saving modes + + – – VOLTAGE COMPARATORS CROSSBAR IREF DIGITAL I/O UART SMBus 2 x SPI PCA Timer 0 Timer 1 Timer 2 Timer 3 CRC EMIF 10-bit 300 ksps ADC VREG - Packages - 32-pin QFN (5 x 5 mm) - 24-pin QFN (4 x 4 mm) - 32-pin LQFP (7 x 7 mm, easy to hand-solder) Temperature Range: –40 to +85 °C ANALOG PERIPHERALS VREF current and programmable drive strength-Hardware SMBus™ (I2C™ Compatible), 2 x SPI™, and UART serial ports available concurrently Four general purpose 16-bit counter/timers Programmable 16-bit counter/timer array with six capture/compare modules and watchdog timer Hardware SmaRTClock operates down to 0.9 V and requires less than 0.5 µA supply current - intrusive in-system debug (no emulator required) Provides breakpoints, single stepping Inspect/modify memory and registers Complete development kit TEMP SENSOR Digital Peripherals - 24 or 16 port I/O; All 5 V tolerant with high sink  - generating a custom reference voltage A M U X grammable in 1024-byte sectors—1024 bytes are reserved in the 64 kB devices Clock Sources - Internal oscillators: 24.5 MHz, 2% accuracy On-Chip Debug - On-chip debug circuitry facilitates full-speed, non- - Up to 25 MIPS throughput with 25 MHz clock - Expanded interrupt handler Memory - 4352 bytes internal data RAM (256 + 4096) - 64 kB (‘F93x) or 32 kB (‘F92x) Flash; In-system pro- Port 0 Port 1 Port 2 24.5 MHz PRECISION INTERNAL OSCILLATOR 20 MHz LOW POWER INTERNAL OSCILLATOR External Oscillator HARDWARE SmaRTClock HIGH-SPEED CONTROLLER CORE 64/32 kB ISP FLASH FLEXIBLE INTERRUPTS Rev. 1.2 5/11 8051 CPU (25 MIPS) DEBUG CIRCUITRY 4352 B SRAM POR WDT Copyright © 2011 by Silicon Laboratories C8051F93x-C8051F92x C8051F93x-C8051F92x 2 Rev. 1.2 C8051F93x-C8051F92x Table of Contents 1. System Overview.................................................................................................... 18 1.1. CIP-51™ Microcontroller Core.......................................................................... 21 1.1.1. Fully 8051 Compatible.............................................................................. 21 1.1.2. Improved Throughput ............................................................................... 21 1.1.3. Additional Features .................................................................................. 21 1.2. Port Input/Output............................................................................................... 21 1.3. Serial Ports ....................................................................................................... 22 1.4. Programmable Counter Array ........................................................................... 23 1.5. 10-Bit SAR ADC with 16-bit Auto-Averaging Accumulator and  Autonomous Low Power Burst Mode.................................................................. 23 1.6. Programmable Current Reference (IREF0) ...................................................... 25 1.7. Comparators ..................................................................................................... 25 2. Ordering Information.............................................................................................. 27 3. Pinout and Package Definitions............................................................................ 28 4. Electrical Characteristics....................................................................................... 43 4.1. Absolute Maximum Specifications .................................................................... 43 4.2. Electrical Characteristics................................................................................... 44 5. 10-Bit SAR ADC with 16-bit Auto-Averaging Accumulator and  Autonomous Low Power Burst Mode................................................................... 65 5.1. Output Code Formatting ................................................................................... 66 5.2. Modes of Operation .......................................................................................... 67 5.2.1. Starting a Conversion............................................................................... 67 5.2.2. Tracking Modes........................................................................................ 68 5.2.3. Burst Mode ............................................................................................... 69 5.2.4. Settling Time Requirements ..................................................................... 70 5.2.5. Gain Setting.............................................................................................. 71 5.3. 8-Bit Mode......................................................................................................... 71 5.4. Programmable Window Detector ...................................................................... 78 5.4.1. Window Detector In Single-Ended Mode ................................................. 80 5.4.2. ADC0 Specifications................................................................................. 80 5.5. ADC0 Analog Multiplexer.................................................................................. 81 5.6. Temperature Sensor ......................................................................................... 83 5.6.1. Calibration ................................................................................................ 84 5.7. Voltage and Ground Reference Options........................................................... 86 5.8. External Voltage References ............................................................................ 87 5.9. Internal Voltage References ............................................................................. 87 5.10.Analog Ground Reference................................................................................ 87 5.11.Temperature Sensor Enable ............................................................................ 87 5.12.Voltage Reference Electrical Specifications ..................................................... 88 6. Programmable Current Reference (IREF0) .......................................................... 89 6.1. IREF0 Specifications......................................................................................... 89 7. Comparators ........................................................................................................... 90 7.1. Comparator Inputs ............................................................................................ 90 Rev. 1.2 3 C8051F93x-C8051F92x 7.2. Comparator Outputs ......................................................................................... 91 7.3. Comparator Response Time............................................................................. 92 7.4. Comparator Hysterisis ...................................................................................... 92 7.5. Comparator Register Descriptions.................................................................... 93 7.6. Comparator0 and Comparator1 Analog Multiplexers........................................ 97 8. CIP-51 Microcontroller ......................................................................................... 100 8.1. Instruction Set ................................................................................................. 101 8.1.1. Instruction and CPU Timing ................................................................... 101 8.2. CIP-51 Register Descriptions.......................................................................... 106 9. Memory Organization........................................................................................... 109 9.1. Program Memory ............................................................................................ 110 9.1.1. MOVX Instruction and Program Memory ............................................... 110 9.2. Data Memory .................................................................................................. 111 9.2.1. Internal RAM .......................................................................................... 111 9.2.2. External RAM ......................................................................................... 112 10. External Data Memory Interface and On-Chip XRAM........................................ 113 10.1.Accessing XRAM............................................................................................ 113 10.1.1.16-Bit MOVX Example ........................................................................... 113 10.1.2.8-Bit MOVX Example ............................................................................. 113 10.2.Configuring the External Memory Interface for Off-Chip Access.................... 114 10.3.External Memory Interface Port Input/Output Configuration........................... 114 10.4.Multiplexed External Memory Interface .......................................................... 115 10.5.External Memory Interface Operating Modes................................................. 117 10.5.1.Internal XRAM Only ............................................................................... 117 10.5.2.Split Mode without Bank Select.............................................................. 117 10.5.3.Split Mode with Bank Select................................................................... 118 10.5.4.External Only.......................................................................................... 118 10.6.External Memory Interface Timing.................................................................. 118 10.7.EMIF Special Function Registers ................................................................... 119 10.8.EMIF Timing Diagrams................................................................................... 122 10.8.1.Multiplexed 16-bit MOVX: EMI0CF[3:2] = 01, 10, or 11......................... 122 10.8.2.Multiplexed 8-bit MOVX without Bank Select: EMI0CF[3:2] = 01 or 11. 123 11. Special Function Registers ................................................................................. 126 11.1.SFR Paging .................................................................................................... 127 12. Interrupt Handler .................................................................................................. 133 12.1.Enabling Interrupt Sources ............................................................................. 133 12.2.MCU Interrupt Sources and Vectors............................................................... 133 12.3.Interrupt Priorities ........................................................................................... 134 12.4.Interrupt Latency............................................................................................. 134 12.5.Interrupt Register Descriptions ....................................................................... 136 12.6.External Interrupts INT0 and INT1.................................................................. 143 13. Flash Memory ....................................................................................................... 145 13.1.Programming The Flash Memory ................................................................... 145 13.1.1.Flash Lock and Key Functions ............................................................... 145 13.1.2.Flash Erase Procedure .......................................................................... 146 4 Rev. 1.2 C8051F93x-C8051F92x 13.1.3.Flash Write Procedure ........................................................................... 146 13.2.Non-volatile Data Storage .............................................................................. 147 13.3.Security Options ............................................................................................. 147 13.4.Determining the Device Part Number at Run Time ........................................ 149 13.5.Flash Write and Erase Guidelines .................................................................. 150 13.5.1.VDD Maintenance and the VDD Monitor ............................................... 150 13.5.2.PSWE Maintenance ............................................................................... 151 13.5.3.System Clock ......................................................................................... 151 13.6.Minimizing Flash Read Current ...................................................................... 152 14. Power Management.............................................................................................. 156 14.1.Normal Mode .................................................................................................. 157 14.2.Idle Mode........................................................................................................ 158 14.3.Stop Mode ...................................................................................................... 158 14.4.Suspend Mode ............................................................................................... 159 14.5.Sleep Mode .................................................................................................... 159 14.6.Configuring Wakeup Sources......................................................................... 160 14.7.Determining the Event that Caused the Last Wakeup.................................... 161 14.8.Power Management Specifications ................................................................ 163 15. Cyclic Redundancy Check Unit (CRC0) ............................................................. 164 15.1.CRC Algorithm................................................................................................ 164 15.2.Preparing for a CRC Calculation .................................................................... 166 15.3.Performing a CRC Calculation ....................................................................... 166 15.4.Accessing the CRC0 Result ........................................................................... 166 15.5.CRC0 Bit Reverse Feature............................................................................. 170 16. On-Chip DC-DC Converter (DC0) ........................................................................ 171 16.1.Startup Behavior............................................................................................. 172 16.2.High Power Applications................................................................................. 173 16.3.Pulse Skipping Mode...................................................................................... 173 16.4.Enabling the DC-DC Converter ...................................................................... 174 16.5.Minimizing Power Supply Noise ..................................................................... 175 16.6.Selecting the Optimum Switch Size................................................................ 175 16.7.DC-DC Converter Clocking Options ............................................................... 175 16.8.DC-DC Converter Behavior in Sleep Mode .................................................... 175 16.9.DC-DC Converter Register Descriptions ........................................................ 177 16.10.DC-DC Converter Specifications .................................................................. 178 17. Voltage Regulator (VREG0) ................................................................................. 179 17.1.Voltage Regulator Electrical Specifications .................................................... 179 18. Reset Sources....................................................................................................... 180 18.1.Power-On (VBAT Supply Monitor) Reset ....................................................... 181 18.2.Power-Fail (VDD/DC+ Supply Monitor) Reset................................................ 182 18.3.External Reset ................................................................................................ 184 18.4.Missing Clock Detector Reset ........................................................................ 184 18.5.Comparator0 Reset ........................................................................................ 184 18.6.PCA Watchdog Timer Reset .......................................................................... 184 18.7.Flash Error Reset ........................................................................................... 185 Rev. 1.2 5 C8051F93x-C8051F92x 18.8.SmaRTClock (Real Time Clock) Reset .......................................................... 185 18.9.Software Reset ............................................................................................... 185 19. Clocking Sources ................................................................................................. 187 19.1.Programmable Precision Internal Oscillator ................................................... 188 19.2.Low Power Internal Oscillator......................................................................... 188 19.3.External Oscillator Drive Circuit...................................................................... 188 19.3.1.External Crystal Mode............................................................................ 188 19.3.2.External RC Mode.................................................................................. 190 19.3.3.External Capacitor Mode........................................................................ 191 19.3.4.External CMOS Clock Mode .................................................................. 192 19.4.Special Function Registers for Selecting and Configuring the System Clock 193 20. SmaRTClock (Real Time Clock) .......................................................................... 196 20.1.SmaRTClock Interface ................................................................................... 197 20.1.1.SmaRTClock Lock and Key Functions................................................... 197 20.1.2.Using RTC0ADR and RTC0DAT to Access  SmaRTClock Internal Registers ............................................................. 198 20.1.3.RTC0ADR Short Strobe Feature............................................................ 198 20.1.4.SmaRTClock Interface Autoread Feature .............................................. 199 20.1.5.RTC0ADR Autoincrement Feature......................................................... 199 20.2.SmaRTClock Clocking Sources ..................................................................... 202 20.2.1.Using the SmaRTClock Oscillator with a Crystal or  External CMOS Clock ............................................................................ 202 20.2.2.Using the SmaRTClock Oscillator in Self-Oscillate Mode...................... 202 20.2.3.Programmable Load Capacitance.......................................................... 203 20.2.4.Automatic Gain Control (Crystal Mode Only) and  SmaRTClock Bias Doubling ................................................................... 204 20.2.5.Missing SmaRTClock Detector .............................................................. 206 20.2.6.SmaRTClock Oscillator Crystal Valid Detector ...................................... 206 20.3.SmaRTClock Timer and Alarm Function ........................................................ 206 20.3.1.Setting and Reading the SmaRTClock Timer Value .............................. 206 20.3.2.Setting a SmaRTClock Alarm ................................................................ 207 20.3.3.Software Considerations for using the SmaRTClock Timer and Alarm . 207 21. Port Input/Output.................................................................................................. 212 21.1.Port I/O Modes of Operation........................................................................... 213 21.1.1.Port Pins Configured for Analog I/O....................................................... 213 21.1.2.Port Pins Configured For Digital I/O....................................................... 213 21.1.3.Interfacing Port I/O to 5 V Logic ............................................................. 214 21.1.4.Increasing Port I/O Drive Strength ......................................................... 214 21.2.Assigning Port I/O Pins to Analog and Digital Functions................................ 214 21.2.1.Assigning Port I/O Pins to Analog Functions ......................................... 214 21.2.2.Assigning Port I/O Pins to Digital Functions........................................... 215 21.2.3.Assigning Port I/O Pins to External Digital Event Capture Functions .... 215 21.3.Priority Crossbar Decoder .............................................................................. 216 21.4.Port Match ...................................................................................................... 222 21.5.Special Function Registers for Accessing and Configuring Port I/O .............. 224 6 Rev. 1.2 C8051F93x-C8051F92x 22. SMBus ................................................................................................................... 233 22.1.Supporting Documents ................................................................................... 234 22.2.SMBus Configuration...................................................................................... 234 22.3.SMBus Operation ........................................................................................... 235 22.3.1.Transmitter Vs. Receiver........................................................................ 235 22.3.2.Arbitration............................................................................................... 235 22.3.3.Clock Low Extension.............................................................................. 236 22.3.4.SCL Low Timeout................................................................................... 236 22.3.5.SCL High (SMBus Free) Timeout .......................................................... 236 22.4.Using the SMBus............................................................................................ 237 22.4.1.SMBus Configuration Register............................................................... 238 22.4.2.SMB0CN Control Register ..................................................................... 241 22.4.3.Hardware Slave Address Recognition ................................................... 244 22.4.4.Data Register ......................................................................................... 246 22.5.SMBus Transfer Modes.................................................................................. 247 22.5.1.Write Sequence (Master) ....................................................................... 247 22.5.2.Read Sequence (Master) ....................................................................... 248 22.5.3.Write Sequence (Slave) ......................................................................... 249 22.5.4.Read Sequence (Slave) ......................................................................... 250 22.6.SMBus Status Decoding................................................................................. 250 23. UART0.................................................................................................................... 255 23.1.Enhanced Baud Rate Generation................................................................... 256 23.2.Operational Modes ......................................................................................... 257 23.2.1.8-Bit UART ............................................................................................. 257 23.2.2.9-Bit UART ............................................................................................. 258 23.3.Multiprocessor Communications .................................................................... 258 24. Enhanced Serial Peripheral Interface (SPI0 and SPI1)...................................... 263 24.1.Signal Descriptions......................................................................................... 264 24.1.1.Master Out, Slave In (MOSI).................................................................. 264 24.1.2.Master In, Slave Out (MISO).................................................................. 264 24.1.3.Serial Clock (SCK) ................................................................................. 264 24.1.4.Slave Select (NSS) ................................................................................ 264 24.2.SPI Master Mode Operation ........................................................................... 265 24.3.SPI Slave Mode Operation ............................................................................. 267 24.4.SPI Interrupt Sources ..................................................................................... 267 24.5.Serial Clock Phase and Polarity ..................................................................... 268 24.6.SPI Special Function Registers ...................................................................... 270 25. Timers.................................................................................................................... 278 25.1.Timer 0 and Timer 1 ....................................................................................... 280 25.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 280 25.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 281 25.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 282 25.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 283 25.2.Timer 2 .......................................................................................................... 288 25.2.1.16-bit Timer with Auto-Reload................................................................ 288 Rev. 1.2 7 C8051F93x-C8051F92x 25.2.2.8-bit Timers with Auto-Reload................................................................ 289 25.2.3.Comparator 0/SmaRTClock Capture Mode ........................................... 290 25.3.Timer 3 .......................................................................................................... 294 25.3.1.16-bit Timer with Auto-Reload................................................................ 294 25.3.2.8-bit Timers with Auto-Reload................................................................ 295 25.3.3.Comparator 1/External Oscillator Capture Mode ................................... 296 26. Programmable Counter Array ............................................................................. 300 26.1.PCA Counter/Timer ........................................................................................ 301 26.2.PCA0 Interrupt Sources.................................................................................. 302 26.3.Capture/Compare Modules ............................................................................ 303 26.3.1.Edge-triggered Capture Mode................................................................ 304 26.3.2.Software Timer (Compare) Mode........................................................... 305 26.3.3.High-Speed Output Mode ...................................................................... 306 26.3.4.Frequency Output Mode ........................................................................ 307 26.3.5.8-Bit, 9-Bit, 10-Bit and 11-Bit Pulse Width Modulator Modes................. 308 26.3.6.16-Bit Pulse Width Modulator Mode....................................................... 310 26.4.Watchdog Timer Mode ................................................................................... 311 26.4.1.Watchdog Timer Operation .................................................................... 311 26.4.2.Watchdog Timer Usage ......................................................................... 312 26.5.Register Descriptions for PCA0...................................................................... 313 27. C2 Interface ........................................................................................................... 319 27.1.C2 Interface Registers.................................................................................... 319 27.2.C2 Pin Sharing ............................................................................................... 322 Document Change List............................................................................................. 323 Contact Information.................................................................................................. 324 8 Rev. 1.2 C8051F93x-C8051F92x List of Figures 1. System Overview Figure 1.1. C8051F930 Block Diagram .................................................................... 19 Figure 1.2. C8051F931 Block Diagram .................................................................... 19 Figure 1.3. C8051F920 Block Diagram .................................................................... 20 Figure 1.4. C8051F921 Block Diagram .................................................................... 20 Figure 1.5. Port I/O Functional Block Diagram ......................................................... 22 Figure 1.6. PCA Block Diagram................................................................................ 23 Figure 1.7. ADC0 Functional Block Diagram............................................................ 24 Figure 1.8. ADC0 Multiplexer Block Diagram ........................................................... 25 Figure 1.9. Comparator 0 Functional Block Diagram ............................................... 26 Figure 1.10. Comparator 1 Functional Block Diagram ............................................. 26 2. Ordering Information 3. Pinout and Package Definitions Figure 3.1. QFN-32 Pinout Diagram (Top View) ...................................................... 32 Figure 3.2. QFN-24 Pinout Diagram (Top View) ...................................................... 33 Figure 3.3. LQFP-32 Pinout Diagram (Top View)..................................................... 34 Figure 3.4. QFN-32 Package Drawing ..................................................................... 35 Figure 3.5. Typical QFN-32 Landing Diagram.......................................................... 36 Figure 3.6. QFN-24 Package Drawing ..................................................................... 38 Figure 3.7. Typical QFN-24 Landing Diagram.......................................................... 39 Figure 3.8. LQFP-32 Package Diagram ................................................................... 41 Figure 3.9. Typical LQFP-32 Landing Diagram ........................................................ 42 4. Electrical Characteristics Figure 4.1. Active Mode Current (External CMOS Clock) ........................................ 46 Figure 4.2. Idle Mode Current (External CMOS Clock) ............................................ 47 Figure 4.3. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 2 V) ... 48 Figure 4.4. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 3 V) ... 49 Figure 4.5. Typical DC-DC Converter Efficiency (Low Current, VDD/DC+ = 2 V).... 50 Figure 4.6. Typical One-Cell Suspend Mode Current............................................... 51 Figure 4.7. Typical VOH Curves, 1.8 – 3.6 V ........................................................... 53 Figure 4.8. Typical VOH Curves, 0.9 – 1.8 V ........................................................... 54 Figure 4.9. Typical VOL Curves, 1.8 – 3.6 V ............................................................ 55 Figure 4.10. Typical VOL Curves, 0.9 – 1.8 V .......................................................... 56 5. 10-Bit SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous Low Power Burst Mode Figure 5.1. ADC0 Functional Block Diagram............................................................ 65 Figure 5.2. 10-Bit ADC Track and Conversion Example Timing (BURSTEN = 0).... 68 Figure 5.3. Burst Mode Tracking Example with Repeat Count Set to 4 ................... 69 Figure 5.4. ADC0 Equivalent Input Circuits .............................................................. 70 Figure 5.5. ADC Window Compare Example: Right-Justified Single-Ended Data ... 80 Figure 5.6. ADC Window Compare Example: Left-Justified Single-Ended Data...... 80 Figure 5.7. ADC0 Multiplexer Block Diagram ........................................................... 81 Figure 5.8. Temperature Sensor Transfer Function ................................................. 83 Rev. 1.2 9 C8051F93x-C8051F92x Figure 5.9. Temperature Sensor Error with 1-Point Calibration (VREF = 1.68 V) ..... 84 Figure 5.10. Voltage Reference Functional Block Diagram...................................... 86 6. Programmable Current Reference (IREF0) 7. Comparators Figure 7.1. Comparator 0 Functional Block Diagram ............................................... 90 Figure 7.2. Comparator 1 Functional Block Diagram ............................................... 91 Figure 7.3. Comparator Hysteresis Plot ................................................................... 92 Figure 7.4. CPn Multiplexer Block Diagram.............................................................. 97 8. CIP-51 Microcontroller Figure 8.1. CIP-51 Block Diagram.......................................................................... 100 9. Memory Organization Figure 9.1. C8051F93x-C8051F92x Memory Map ................................................. 109 Figure 9.2. Flash Program Memory Map................................................................ 110 10. External Data Memory Interface and On-Chip XRAM Figure 10.1. Multiplexed Configuration Example.................................................... 115 Figure 10.2. Multiplexed to Non-Multiplexed Configuration Example..................... 116 Figure 10.3. EMIF Operating Modes ...................................................................... 117 Figure 10.4. Multiplexed 16-bit MOVX Timing........................................................ 122 Figure 10.5. Multiplexed 8-bit MOVX without Bank Select Timing ......................... 123 Figure 10.6. Multiplexed 8-bit MOVX with Bank Select Timing .............................. 124 11. Special Function Registers 12. Interrupt Handler 13. Flash Memory Figure 13.1. Flash Program Memory Map.............................................................. 147 14. Power Management Figure 14.1. C8051F93x-C8051F92x Power Distribution....................................... 157 15. Cyclic Redundancy Check Unit (CRC0) Figure 15.1. CRC0 Block Diagram ......................................................................... 164 Figure 15.2. Bit Reverse Register .......................................................................... 170 16. On-Chip DC-DC Converter (DC0) Figure 16.1. DC-DC Converter Block Diagram....................................................... 171 Figure 16.2. DC-DC Converter Configuration Options ........................................... 174 17. Voltage Regulator (VREG0) 18. Reset Sources Figure 18.1. Reset Sources.................................................................................... 180 Figure 18.2. Power-Fail Reset Timing Diagram ..................................................... 181 Figure 18.3. Power-Fail Reset Timing Diagram ..................................................... 182 19. Clocking Sources Figure 19.1. Clocking Sources Block Diagram ....................................................... 187 Figure 19.2. 25 MHz External Crystal Example...................................................... 189 20. SmaRTClock (Real Time Clock) Figure 20.1. SmaRTClock Block Diagram.............................................................. 196 Figure 20.2. Interpreting Oscillation Robustness (Duty Cycle) Test Results.......... 204 21. Port Input/Output Figure 21.1. Port I/O Functional Block Diagram ..................................................... 212 10 Rev. 1.2 C8051F93x-C8051F92x Figure 21.2. Port I/O Cell Block Diagram ............................................................... 213 Figure 21.3. Crossbar Priority Decoder with No Pins Skipped ............................... 217 Figure 21.4. Crossbar Priority Decoder with Crystal Pins Skipped ........................ 218 22. SMBus Figure 22.1. SMBus Block Diagram ....................................................................... 233 Figure 22.2. Typical SMBus Configuration ............................................................. 234 Figure 22.3. SMBus Transaction ............................................................................ 235 Figure 22.4. Typical SMBus SCL Generation......................................................... 238 Figure 22.5. Typical Master Write Sequence ......................................................... 247 Figure 22.6. Typical Master Read Sequence ......................................................... 248 Figure 22.7. Typical Slave Write Sequence ........................................................... 249 Figure 22.8. Typical Slave Read Sequence ........................................................... 250 23. UART0 Figure 23.1. UART0 Block Diagram ....................................................................... 255 Figure 23.2. UART0 Baud Rate Logic .................................................................... 256 Figure 23.3. UART Interconnect Diagram .............................................................. 257 Figure 23.4. 8-Bit UART Timing Diagram............................................................... 257 Figure 23.5. 9-Bit UART Timing Diagram............................................................... 258 Figure 23.6. UART Multi-Processor Mode Interconnect Diagram .......................... 259 24. Enhanced Serial Peripheral Interface (SPI0 and SPI1) Figure 24.1. SPI Block Diagram ............................................................................. 263 Figure 24.2. Multiple-Master Mode Connection Diagram ....................................... 266 Figure 24.3. 3-Wire Single Master and 3-Wire Single Slave Mode  Connection Diagram .............................................................................. 266 Figure 24.4. 4-Wire Single Master Mode and 4-Wire Slave Mode  Connection Diagram .............................................................................. 266 Figure 24.5. Master Mode Data/Clock Timing ........................................................ 268 Figure 24.6. Slave Mode Data/Clock Timing (CKPHA = 0) .................................... 269 Figure 24.7. Slave Mode Data/Clock Timing (CKPHA = 1) .................................... 269 Figure 24.8. SPI Master Timing (CKPHA = 0)........................................................ 275 Figure 24.9. SPI Master Timing (CKPHA = 1)........................................................ 275 Figure 24.10. SPI Slave Timing (CKPHA = 0)........................................................ 276 Figure 24.11. SPI Slave Timing (CKPHA = 1)........................................................ 276 25. Timers Figure 25.1. T0 Mode 0 Block Diagram.................................................................. 281 Figure 25.2. T0 Mode 2 Block Diagram.................................................................. 282 Figure 25.3. T0 Mode 3 Block Diagram.................................................................. 283 Figure 25.4. Timer 2 16-Bit Mode Block Diagram .................................................. 288 Figure 25.5. Timer 2 8-Bit Mode Block Diagram .................................................... 289 Figure 25.6. Timer 2 Capture Mode Block Diagram ............................................... 290 Figure 25.7. Timer 3 16-Bit Mode Block Diagram .................................................. 294 Figure 25.8. Timer 3 8-Bit Mode Block Diagram. ................................................... 295 Figure 25.9. Timer 3 Capture Mode Block Diagram ............................................... 296 26. Programmable Counter Array Figure 26.1. PCA Block Diagram............................................................................ 300 Rev. 1.2 11 C8051F93x-C8051F92x Figure 26.2. PCA Counter/Timer Block Diagram.................................................... 302 Figure 26.3. PCA Interrupt Block Diagram ............................................................. 302 Figure 26.4. PCA Capture Mode Diagram.............................................................. 304 Figure 26.5. PCA Software Timer Mode Diagram .................................................. 305 Figure 26.6. PCA High-Speed Output Mode Diagram............................................ 306 Figure 26.7. PCA Frequency Output Mode ............................................................ 307 Figure 26.8. PCA 8-Bit PWM Mode Diagram ......................................................... 308 Figure 26.9. PCA 9, 10 and 11-Bit PWM Mode Diagram ....................................... 309 Figure 26.10. PCA 16-Bit PWM Mode.................................................................... 310 Figure 26.11. PCA Module 5 with Watchdog Timer Enabled ................................. 311 27. C2 Interface Figure 27.1. Typical C2 Pin Sharing....................................................................... 322 12 Rev. 1.2 C8051F93x-C8051F92x List of Tables 1. System Overview 2. Ordering Information Table 2.1. Product Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3. Pinout and Package Definitions Table 3.1. Pin Definitions for the C8051F92x-C8051F93x . . . . . . . . . . . . . . . . . . . 28 Table 3.2. QFN-32 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 3.3. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 3.4. QFN-24 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 3.5. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 3.6. LQFP-32 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 3.7. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4. Electrical Characteristics Table 4.1. Absolute Maximum Ratings .................................................................... 43 Table 4.2. Global Electrical Characteristics ............................................................. 44 Table 4.3. Port I/O DC Electrical Characteristics ..................................................... 52 Table 4.4. Reset Electrical Characteristics .............................................................. 57 Table 4.5. Power Management Electrical Specifications ......................................... 58 Table 4.6. Flash Electrical Characteristics .............................................................. 58 Table 4.7. Internal Precision Oscillator Electrical Characteristics ........................... 58 Table 4.8. Internal Low-Power Oscillator Electrical Characteristics ........................ 58 Table 4.9. ADC0 Electrical Characteristics .............................................................. 59 Table 4.10. Temperature Sensor Electrical Characteristics .................................... 60 Table 4.11. Voltage Reference Electrical Characteristics ....................................... 60 Table 4.12. IREF0 Electrical Characteristics ........................................................... 61 Table 4.13. Comparator Electrical Characteristics .................................................. 62 Table 4.14. DC-DC Converter (DC0) Electrical Characteristics .............................. 64 Table 4.15. VREG0 Electrical Characteristics ......................................................... 64 5. 10-Bit SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous Low Power Burst Mode 6. Programmable Current Reference (IREF0) 7. Comparators 8. CIP-51 Microcontroller Table 8.1. CIP-51 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 9. Memory Organization 10. External Data Memory Interface and On-Chip XRAM Table 10.1. AC Parameters for External Memory Interface ................................... 125 11. Special Function Registers Table 11.1. Special Function Register (SFR) Memory Map (Page 0x0) . . . . . . . . 126 Table 11.2. Special Function Register (SFR) Memory Map (Page 0xF) . . . . . . . . 127 Table 11.3. Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 12. Interrupt Handler Table 12.1. Interrupt Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Rev. 1.2 13 C8051F93x-C8051F92x 13. Flash Memory Table 13.1. Flash Security Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 14. Power Management Table 14.1. Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 15. Cyclic Redundancy Check Unit (CRC0) Table 15.1. Example 16-bit CRC Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 16. On-Chip DC-DC Converter (DC0) Table 16.1. IPeak Inductor Current Limit Settings . . . . . . . . . . . . . . . . . . . . . . . . . 172 17. Voltage Regulator (VREG0) 18. Reset Sources 19. Clocking Sources Table 19.1. Recommended XFCN Settings for Crystal Mode . . . . . . . . . . . . . . . . 189 Table 19.2. Recommended XFCN Settings for RC and C modes . . . . . . . . . . . . . 190 20. SmaRTClock (Real Time Clock) Table 20.1. SmaRTClock Internal Registers ......................................................... 197 Table 20.2. SmaRTClock Load Capacitance Settings . . . . . . . . . . . . . . . . . . . . . 203 Table 20.3. SmaRTClock Bias Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 21. Port Input/Output Table 21.1. Port I/O Assignment for Analog Functions . . . . . . . . . . . . . . . . . . . . . 214 Table 21.2. Port I/O Assignment for Digital Functions . . . . . . . . . . . . . . . . . . . . . . 215 Table 21.3. Port I/O Assignment for External Digital Event Capture Functions . . 215 22. SMBus Table 22.1. SMBus Clock Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 Table 22.2. Minimum SDA Setup and Hold Times . . . . . . . . . . . . . . . . . . . . . . . . 239 Table 22.3. Sources for Hardware Changes to SMB0CN . . . . . . . . . . . . . . . . . . . 243 Table 22.4. Hardware Address Recognition Examples (EHACK = 1) . . . . . . . . . . 244 Table 22.5. SMBus Status Decoding With Hardware ACK Generation Disabled (EHACK = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Table 22.6. SMBus Status Decoding With Hardware ACK Generation Enabled (EHACK = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 23. UART0 Table 23.1. Timer Settings for Standard Baud Rates  Using The Internal 24.5 MHz Oscillator . . . . . . . . . . . . . . . . . . . . . . . 262 Table 23.2. Timer Settings for Standard Baud Rates  Using an External 22.1184 MHz Oscillator . . . . . . . . . . . . . . . . . . . . . 262 24. Enhanced Serial Peripheral Interface (SPI0 and SPI1) Table 24.1. SPI Slave Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 25. Timers Table 25.1. Timer 0 Running Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 26. Programmable Counter Array Table 26.1. PCA Timebase Input Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 Table 26.2. PCA0CPM and PCA0PWM Bit Settings for PCA  Capture/Compare Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 Table 26.3. Watchdog Timer Timeout Intervals1 . . . . . . . . . . . . . . . . . . . . . . . . . . 312 27. C2 Interface 14 Rev. 1.2 C8051F93x-C8051F92x List of Registers SFR Definition 5.1. ADC0CN: ADC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 SFR Definition 5.2. ADC0CF: ADC0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 SFR Definition 5.3. ADC0AC: ADC0 Accumulator Configuration . . . . . . . . . . . . . . . . . 74 SFR Definition 5.4. ADC0PWR: ADC0 Burst Mode Power-Up Time . . . . . . . . . . . . . . 75 SFR Definition 5.5. ADC0TK: ADC0 Burst Mode Track Time . . . . . . . . . . . . . . . . . . . . 76 SFR Definition 5.6. ADC0H: ADC0 Data Word High Byte . . . . . . . . . . . . . . . . . . . . . . 77 SFR Definition 5.7. ADC0L: ADC0 Data Word Low Byte . . . . . . . . . . . . . . . . . . . . . . . 77 SFR Definition 5.8. ADC0GTH: ADC0 Greater-Than High Byte . . . . . . . . . . . . . . . . . . 78 SFR Definition 5.9. ADC0GTL: ADC0 Greater-Than Low Byte . . . . . . . . . . . . . . . . . . 78 SFR Definition 5.10. ADC0LTH: ADC0 Less-Than High Byte . . . . . . . . . . . . . . . . . . . 79 SFR Definition 5.11. ADC0LTL: ADC0 Less-Than Low Byte . . . . . . . . . . . . . . . . . . . . 79 SFR Definition 5.12. ADC0MX: ADC0 Input Channel Select . . . . . . . . . . . . . . . . . . . . 82 SFR Definition 5.13. TOFFH: ADC0 Data Word High Byte . . . . . . . . . . . . . . . . . . . . . 85 SFR Definition 5.14. TOFFL: ADC0 Data Word Low Byte . . . . . . . . . . . . . . . . . . . . . . 85 SFR Definition 5.15. REF0CN: Voltage Reference Control . . . . . . . . . . . . . . . . . . . . . 88 SFR Definition 6.1. IREF0CN: Current Reference Control . . . . . . . . . . . . . . . . . . . . . . 89 SFR Definition 7.1. CPT0CN: Comparator 0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 93 SFR Definition 7.2. CPT0MD: Comparator 0 Mode Selection . . . . . . . . . . . . . . . . . . . 94 SFR Definition 7.3. CPT1CN: Comparator 1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 95 SFR Definition 7.4. CPT1MD: Comparator 1 Mode Selection . . . . . . . . . . . . . . . . . . . 96 SFR Definition 7.5. CPT0MX: Comparator0 Input Channel Select . . . . . . . . . . . . . . . . 98 SFR Definition 7.6. CPT1MX: Comparator1 Input Channel Select . . . . . . . . . . . . . . . . 99 SFR Definition 8.1. DPL: Data Pointer Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 SFR Definition 8.2. DPH: Data Pointer High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 SFR Definition 8.3. SP: Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 SFR Definition 8.4. ACC: Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 SFR Definition 8.5. B: B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 SFR Definition 8.6. PSW: Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 SFR Definition 10.1. EMI0CN: External Memory Interface Control . . . . . . . . . . . . . . 119 SFR Definition 10.2. EMI0CF: External Memory Configuration . . . . . . . . . . . . . . . . . 120 SFR Definition 10.3. EMI0TC: External Memory Timing Control . . . . . . . . . . . . . . . . 121 SFR Definition 11.1. SFR Page: SFR Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 SFR Definition 12.1. IE: Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 SFR Definition 12.2. IP: Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 SFR Definition 12.3. EIE1: Extended Interrupt Enable 1 . . . . . . . . . . . . . . . . . . . . . . 139 SFR Definition 12.4. EIP1: Extended Interrupt Priority 1 . . . . . . . . . . . . . . . . . . . . . . 140 SFR Definition 12.5. EIE2: Extended Interrupt Enable 2 . . . . . . . . . . . . . . . . . . . . . . 141 SFR Definition 12.6. EIP2: Extended Interrupt Priority 2 . . . . . . . . . . . . . . . . . . . . . . 142 SFR Definition 12.7. IT01CF: INT0/INT1 Configuration . . . . . . . . . . . . . . . . . . . . . . . 144 SFR Definition 13.1. PSCTL: Program Store R/W Control . . . . . . . . . . . . . . . . . . . . . 153 SFR Definition 13.2. FLKEY: Flash Lock and Key . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 SFR Definition 13.3. FLSCL: Flash Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 SFR Definition 13.4. FLWR: Flash Write Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Rev. 1.2 15 C8051F93x-C8051F92x SFR Definition 14.1. PMU0CF: Power Management Unit Configuration1,2 . . . . . . . . 162 SFR Definition 14.2. PCON: Power Management Control Register . . . . . . . . . . . . . . 163 SFR Definition 15.1. CRC0CN: CRC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 SFR Definition 15.2. CRC0IN: CRC0 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 SFR Definition 15.3. CRC0DAT: CRC0 Data Output . . . . . . . . . . . . . . . . . . . . . . . . . 168 SFR Definition 15.4. CRC0AUTO: CRC0 Automatic Control . . . . . . . . . . . . . . . . . . . 169 SFR Definition 15.5. CRC0CNT: CRC0 Automatic Flash Sector Count . . . . . . . . . . . 169 SFR Definition 15.6. CRC0FLIP: CRC0 Bit Flip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 SFR Definition 16.1. DC0CN: DC-DC Converter Control . . . . . . . . . . . . . . . . . . . . . . 177 SFR Definition 16.2. DC0CF: DC-DC Converter Configuration . . . . . . . . . . . . . . . . . 178 SFR Definition 17.1. REG0CN: Voltage Regulator Control . . . . . . . . . . . . . . . . . . . . 179 SFR Definition 18.1. VDM0CN: VDD/DC+ Supply Monitor Control . . . . . . . . . . . . . . 183 SFR Definition 18.2. RSTSRC: Reset Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 SFR Definition 19.1. CLKSEL: Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 SFR Definition 19.2. OSCICN: Internal Oscillator Control . . . . . . . . . . . . . . . . . . . . . 194 SFR Definition 19.3. OSCICL: Internal Oscillator Calibration . . . . . . . . . . . . . . . . . . . 194 SFR Definition 19.4. OSCXCN: External Oscillator Control . . . . . . . . . . . . . . . . . . . . 195 SFR Definition 20.1. RTC0KEY: SmaRTClock Lock and Key . . . . . . . . . . . . . . . . . . 200 SFR Definition 20.2. RTC0ADR: SmaRTClock Address . . . . . . . . . . . . . . . . . . . . . . 201 SFR Definition 20.3. RTC0DAT: SmaRTClock Data . . . . . . . . . . . . . . . . . . . . . . . . . 201 Internal Register Definition 20.4. RTC0CN: SmaRTClock Control . . . . . . . . . . . . . . . 208 Internal Register Definition 20.5. RTC0XCN: SmaRTClock Oscillator Control . . . . . . 209 Internal Register Definition 20.6. RTC0XCF: SmaRTClock Oscillator Configuration . 210 Internal Register Definition 20.7. RTC0PIN: SmaRTClock Pin Configuration . . . . . . 210 Internal Register Definition 20.8. CAPTUREn: SmaRTClock Timer Capture . . . . . . . 211 Internal Register Definition 20.9. ALARMn: SmaRTClock Alarm Programmed Value 211 SFR Definition 21.1. XBR0: Port I/O Crossbar Register 0 . . . . . . . . . . . . . . . . . . . . . 219 SFR Definition 21.2. XBR1: Port I/O Crossbar Register 1 . . . . . . . . . . . . . . . . . . . . . 220 SFR Definition 21.3. XBR2: Port I/O Crossbar Register 2 . . . . . . . . . . . . . . . . . . . . . 221 SFR Definition 21.4. P0MASK: Port0 Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . 222 SFR Definition 21.5. P0MAT: Port0 Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . 222 SFR Definition 21.6. P1MASK: Port1 Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . 223 SFR Definition 21.7. P1MAT: Port1 Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . 223 SFR Definition 21.8. P0: Port0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 SFR Definition 21.9. P0SKIP: Port0 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 SFR Definition 21.10. P0MDIN: Port0 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 SFR Definition 21.11. P0MDOUT: Port0 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 226 SFR Definition 21.12. P0DRV: Port0 Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . 227 SFR Definition 21.13. P1: Port1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 SFR Definition 21.14. P1SKIP: Port1 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 SFR Definition 21.15. P1MDIN: Port1 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 SFR Definition 21.16. P1MDOUT: Port1 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 229 SFR Definition 21.17. P1DRV: Port1 Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . 230 SFR Definition 21.18. P2: Port2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 SFR Definition 21.19. P2SKIP: Port2 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 16 Rev. 1.2 C8051F93x-C8051F92x SFR Definition 21.20. P2MDIN: Port2 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 SFR Definition 21.21. P2MDOUT: Port2 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 232 SFR Definition 21.22. P2DRV: Port2 Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . 232 SFR Definition 22.1. SMB0CF: SMBus Clock/Configuration . . . . . . . . . . . . . . . . . . . 240 SFR Definition 22.2. SMB0CN: SMBus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 SFR Definition 22.3. SMB0ADR: SMBus Slave Address . . . . . . . . . . . . . . . . . . . . . . 245 SFR Definition 22.4. SMB0ADM: SMBus Slave Address Mask . . . . . . . . . . . . . . . . . 245 SFR Definition 22.5. SMB0DAT: SMBus Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 SFR Definition 23.1. SCON0: Serial Port 0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 260 SFR Definition 23.2. SBUF0: Serial (UART0) Port Data Buffer . . . . . . . . . . . . . . . . . 261 SFR Definition 24.1. SPInCFG: SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 SFR Definition 24.2. SPInCN: SPI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 SFR Definition 24.3. SPInCKR: SPI Clock Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 SFR Definition 24.4. SPInDAT: SPI Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 SFR Definition 25.1. CKCON: Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 SFR Definition 25.2. TCON: Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 SFR Definition 25.3. TMOD: Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 SFR Definition 25.4. TL0: Timer 0 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 SFR Definition 25.5. TL1: Timer 1 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 SFR Definition 25.6. TH0: Timer 0 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 SFR Definition 25.7. TH1: Timer 1 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 SFR Definition 25.8. TMR2CN: Timer 2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 SFR Definition 25.9. TMR2RLL: Timer 2 Reload Register Low Byte . . . . . . . . . . . . . 292 SFR Definition 25.10. TMR2RLH: Timer 2 Reload Register High Byte . . . . . . . . . . . 292 SFR Definition 25.11. TMR2L: Timer 2 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 SFR Definition 25.12. TMR2H Timer 2 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 SFR Definition 25.13. TMR3CN: Timer 3 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 SFR Definition 25.14. TMR3RLL: Timer 3 Reload Register Low Byte . . . . . . . . . . . . 298 SFR Definition 25.15. TMR3RLH: Timer 3 Reload Register High Byte . . . . . . . . . . . 298 SFR Definition 25.16. TMR3L: Timer 3 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 SFR Definition 25.17. TMR3H Timer 3 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 SFR Definition 26.1. PCA0CN: PCA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 SFR Definition 26.2. PCA0MD: PCA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 SFR Definition 26.3. PCA0PWM: PCA PWM Configuration . . . . . . . . . . . . . . . . . . . . 315 SFR Definition 26.4. PCA0CPMn: PCA Capture/Compare Mode . . . . . . . . . . . . . . . 316 SFR Definition 26.5. PCA0L: PCA Counter/Timer Low Byte . . . . . . . . . . . . . . . . . . . 317 SFR Definition 26.6. PCA0H: PCA Counter/Timer High Byte . . . . . . . . . . . . . . . . . . . 317 SFR Definition 26.7. PCA0CPLn: PCA Capture Module Low Byte . . . . . . . . . . . . . . . 318 SFR Definition 26.8. PCA0CPHn: PCA Capture Module High Byte . . . . . . . . . . . . . . 318 C2 Register Definition 27.1. C2ADD: C2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 C2 Register Definition 27.2. DEVICEID: C2 Device ID . . . . . . . . . . . . . . . . . . . . . . . . 320 C2 Register Definition 27.3. REVID: C2 Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . 320 C2 Register Definition 27.4. FPCTL: C2 Flash Programming Control . . . . . . . . . . . . 321 C2 Register Definition 27.5. FPDAT: C2 Flash Programming Data . . . . . . . . . . . . . . 321 Rev. 1.2 17 C8051F93x-C8051F92x 1. System Overview C8051F93x-C8051F92x devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are listed below. Refer to Table 2.1 for specific product feature selection and part ordering numbers. • • • • • • • • • • • • • • Single/Dual Battery operation with on-chip dc-dc boost converter. High-speed pipelined 8051-compatible microcontroller core (up to 25 MIPS) In-system, full-speed, non-intrusive debug interface (on-chip) True 10-bit 300 ksps 23-channel single-ended ADC with analog multiplexer 6-Bit Programmable Current Reference Precision programmable 24.5 MHz internal oscillator with spread spectrum technology. 64 kB or 32 kB of on-chip Flash memory 4352 bytes of on-chip RAM SMBus/I2C, Enhanced UART, and two Enhanced SPI serial interfaces implemented in hardware Four general-purpose 16-bit timers Programmable Counter/Timer Array (PCA) with six capture/compare modules and Watchdog Timer function On-chip Power-On Reset, VDD Monitor, and Temperature Sensor Two On-chip Voltage Comparators with 23 Touch Sense inputs. 24 or 16 Port I/O (5 V tolerant) With on-chip Power-On Reset, VDD monitor, Watchdog Timer, and clock oscillator, the C8051F93xC8051F92x devices are truly stand-alone System-on-a-Chip solutions. The Flash memory can be reprogrammed even in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. User software has complete control of all peripherals, and may individually shut down any or all peripherals for power savings. The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging without occupying package pins. Each device is specified for 0.9 to 1.8 V or 1.8 to 3.6 V operation over the industrial temperature range  (–40 to +85 °C). The Port I/O and RST pins are tolerant of input signals up to 5 V. The C8051F930/20 are available in 32-pin QFN or LQFP packages and the C8051F931/21 are available in a 24-pin QFN package. Both package options are lead-free and RoHS compliant. See Table 2.1 for ordering information. Block diagrams are included in Figure 1.1 through Figure 1.4. 18 Rev. 1.2 C8051F93x-C8051F92x Wake Reset C2CK/RST Debug / Programming Hardware Power Net UART 256 Byte SRAM Timers 0, 1, 2, 3 4096 Byte XRAM VREG Analog Power GND/DC- DCEN VBAT DC/DC Converter SPI 0,1 Crossbar Control SFR Bus Low Power 20 MHz Oscillator GND XTAL2 XTAL3 Port 0 Drivers P0.0/VREF P0.1/AGND P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6/CNVSTR P0.7/IREF0 IREF0 Internal External VREF VREF VDD VREF Temp Sensor A M U X 10-bit 300ksps ADC SmaRTClock Oscillator XTAL4 Analog Peripherals 6-bit IREF External Oscillator Circuit XTAL1 Port 2 Drivers P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/ALE P2.5/RD P2.6/WR P2.7/C2D SMBus SYSCLK Precision 24.5 MHz Oscillator Port 1 Drivers P1.0/AD0 P1.1/AD1 P1.2/AD2 P1.3/AD3 P1.4/AD4 P1.5/AD5 P1.6/AD6 P1.7/AD7 Priority Crossbar Decoder PCA/ WDT CRC Engine Digital Power Port 0 Drivers P0.0/VREF P0.1/AGND P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6/CNVSTR P0.7/IREF0 Digital Peripherals 64 kB ISP Flash Program Memory C2D VDD/DC+ Port I/O Configuration CIP-51 8051 Controller Core Power On Reset/PMU GND CP0, CP0A System Clock Configuration CP1, CP1A + - + - Comparators Figure 1.1. C8051F930 Block Diagram Wake Reset C2CK/RST Debug / Programming Hardware Power Net Analog Power GND/DC- DCEN VBAT UART 256 Byte SRAM Timers 0, 1, 2, 3 4096 Byte XRAM GND XTAL1 XTAL2 XTAL3 XTAL4 VREG Digital Power Priority Crossbar Decoder PCA/ WDT CRC Engine SMBus SPI 0,1 SYSCLK Precision 24.5 MHz Oscillator DC/DC Converter Digital Peripherals 64 kB ISP Flash Program Memory C2D VDD/DC+ Port I/O Configuration CIP-51 8051 Controller Core Power On Reset/PMU Low Power 20 MHz Oscillator External Oscillator Circuit SmaRTClock Oscillator Crossbar Control SFR Bus Analog Peripherals 6-bit IREF IREF0 Internal External VREF VREF Port 2 Drivers A M U X 10-bit 300ksps ADC VDD VREF Temp Sensor P2.7/C2D GND CP0, CP0A System Clock Configuration Port 1 Drivers P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 CP1, CP1A + - + - Comparators Figure 1.2. C8051F931 Block Diagram Rev. 1.2 19 C8051F93x-C8051F92x Wake Reset C2CK/RST Debug / Programming Hardware Power Net UART 256 Byte SRAM Timers 0, 1, 2, 3 4096 Byte XRAM VREG Analog Power GND/DC- DCEN VBAT DC/DC Converter SPI 0,1 Crossbar Control SFR Bus Low Power 20 MHz Oscillator GND XTAL2 XTAL3 Port 0 Drivers P0.0/VREF P0.1/AGND P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6/CNVSTR P0.7/IREF0 IREF0 Internal External VREF VREF VDD VREF Temp Sensor A M U X 10-bit 300ksps ADC SmaRTClock Oscillator XTAL4 Analog Peripherals 6-bit IREF External Oscillator Circuit XTAL1 Port 2 Drivers P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/ALE P2.5/RD P2.6/WR P2.7/C2D SMBus SYSCLK Precision 24.5 MHz Oscillator Port 1 Drivers P1.0/AD0 P1.1/AD1 P1.2/AD2 P1.3/AD3 P1.4/AD4 P1.5/AD5 P1.6/AD6 P1.7/AD7 Priority Crossbar Decoder PCA/ WDT CRC Engine Digital Power Port 0 Drivers P0.0/VREF P0.1/AGND P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6/CNVSTR P0.7/IREF0 Digital Peripherals 32 kB ISP Flash Program Memory C2D VDD/DC+ Port I/O Configuration CIP-51 8051 Controller Core Power On Reset/PMU GND CP0, CP0A System Clock Configuration CP1, CP1A + - + - Comparators Figure 1.3. C8051F920 Block Diagram Wake Reset C2CK/RST Debug / Programming Hardware Power Net Analog Power GND/DC- DCEN UART 256 Byte SRAM Timers 0, 1, 2, 3 4096 Byte XRAM VBAT GND XTAL1 XTAL2 XTAL3 XTAL4 VREG Digital Power Priority Crossbar Decoder PCA/ WDT CRC Engine SMBus SPI 0,1 SYSCLK Precision 24.5 MHz Oscillator DC/DC Converter Digital Peripherals 32 kB ISP Flash Program Memory C2D VDD/DC+ Port I/O Configuration CIP-51 8051 Controller Core Power On Reset/PMU Low Power 20 MHz Oscillator External Oscillator Circuit SmaRTClock Oscillator Crossbar Control SFR Bus Analog Peripherals 6-bit IREF IREF0 Internal External VREF VREF Port 2 Drivers A M U X 10-bit 300ksps ADC VDD VREF Temp Sensor GND CP0, CP0A System Clock Configuration CP1, CP1A + - + - Comparators Figure 1.4. C8051F921 Block Diagram 20 Port 1 Drivers P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 Rev. 1.2 P2.7/C2D C8051F93x-C8051F92x 1.1. CIP-51™ Microcontroller Core 1.1.1. Fully 8051 Compatible The C8051F93x-C8051F92x family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The CIP-51 core offers all the peripherals included with a standard 8052. 1.1.2. Improved Throughput The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than four system clock cycles. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execution time. Clocks to Execute 1 2 2/3 3 3/4 4 4/5 5 8 Number of Instructions 26 50 5 14 7 3 1 2 1 With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. 1.1.3. Additional Features The C8051F93x-C8051F92x SoC family includes several key enhancements to the CIP-51 core and peripherals to improve performance and ease of use in end applications. The extended interrupt handler provides multiple interrupt sources into the CIP-51 allowing numerous analog and digital peripherals to interrupt the controller. An interrupt driven system requires less intervention by the MCU, giving it more effective throughput. The extra interrupt sources are very useful when building multi-tasking, real-time systems. Eight reset sources are available: power-on reset circuitry (POR), an on-chip VDD monitor (forces reset when power supply voltage drops below safe levels), a Watchdog Timer, a Missing Clock Detector, SmaRTClock oscillator fail or alarm, a voltage level detection from Comparator0, a forced software reset, an external reset pin, and an illegal Flash access protection circuit. Each reset source except for the POR, Reset Input Pin, or Flash error may be disabled by the user in software. The WDT may be permanently disabled in software after a power-on reset during MCU initialization. The internal oscillator factory calibrated to 24.5 MHz and is accurate to ±2% over the full temperature and supply range. The internal oscillator period can also be adjusted by user firmware. An additional 20 MHz low power oscillator is also available which facilitates low-power operation. An external oscillator drive circuit is included, allowing an external crystal, ceramic resonator, capacitor, RC, or CMOS clock source to generate the system clock. If desired, the system clock source may be switched on-the-fly between both internal and external oscillator circuits. An external oscillator can also be extremely useful in low power applications, allowing the MCU to run from a slow (power saving) source, while periodically switching to the fast (up to 25 MHz) internal oscillator as needed. 1.2. Port Input/Output Digital and analog resources are available through 24 I/O pins (C8051F930/20) or 16 I/O pins (C8051F931/21). Port pins are organized as three byte-wide ports. Port pins P0.0–P2.6 can be defined as digital or analog I/O. Digital I/O pins can be assigned to one of the internal digital resources or used as general purpose I/O (GPIO). Analog I/O pins are used by the internal analog resources. P2.7 can be used Rev. 1.2 21 C8051F93x-C8051F92x as GPIO and is shared with the C2 Interface Data signal (C2D). See Section “27. C2 Interface” on page 319 for more details. The designer has complete control over which digital and analog functions are assigned to individual Port pins, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder. See Section “21.3. Priority Crossbar Decoder” on page 216 for more information on the Crossbar. All Port I/Os are 5 V tolerant when used as digital inputs or open-drain outputs. For Port I/Os configured as push-pull outputs, current is sourced from the VDD/DC+ supply. Port I/Os used for analog functions can operate up to the VDD/DC+ supply voltage. See Section “21.1. Port I/O Modes of Operation” on page 213 for more information on Port I/O operating modes and the electrical specifications chapter for detailed electrical specifications. XBR0, XBR1, XBR2, PnSKIP Registers Port Match P0MASK, P0MAT P1MASK, P1MAT External Interrupts EX0 and EX1 Priority Decoder Highest Priority UART 4 (Internal Digital Signals) SPI0 SPI1 P0.0 2 SMBus CP0 CP1 Outputs Digital Crossbar 8 4 P1.0 8 P1 I/O Cells 7 T0, T1 P0 I/O Cells P0.7 SYSCLK PCA Lowest Priority PnMDOUT, PnMDIN Registers 2 P1.7 2 8 (Port Latches) P0 P2.0 8 (P0.0-P0.7) P2 I/O Cell 8 P1 To EMIF (P1.0-P1.7) 8 P2 P1.6 To Analog Peripherals (ADC0, CP0, and CP1 inputs, VREF, IREF0, AGND) (P2.0-P2.7) P2.6 P2.7 P1.7–2.6 only available on 32-pin devices P2.7 is available on all devices Figure 1.5. Port I/O Functional Block Diagram 1.3. Serial Ports The C8051F93x-C8051F92x Family includes an SMBus/I2C interface, a full-duplex UART with enhanced baud rate configuration, and two Enhanced SPI interfaces. Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention. 22 Rev. 1.2 C8051F93x-C8051F92x 1.4. Programmable Counter Array An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit general purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with six programmable capture/compare modules. The PCA clock is derived from one of six sources: the system clock divided by 12, the system clock divided by 4, Timer 0 overflows, an External Clock Input (ECI), the system clock, or the external oscillator clock source divided by 8. Each capture/compare module can be configured to operate in a variety of modes: edge-triggered capture, software timer, high-speed output, pulse width modulator (8, 9, 10, 11, or 16-bit), or frequency output. Additionally, Capture/Compare Module 5 offers watchdog timer (WDT) capabilities. Following a system reset, Module 5 is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O and External Clock Input may be routed to Port I/O via the Digital Crossbar. SYSCLK /12 SYSCLK /4 Timer 0 Overflow ECI PCA CLOCK MUX 16 -Bit Counter/Timer SYSCLK External Clock /8 Capture/ Compare Module 0 Capture/ Compare Module 1 Capture/ Compare Module 2 Capture/ Compare Module 3 Capture/ Compare Module 4 Capture/ Compare Module5 / WDT CEX5 CEX4 CEX3 CEX2 CEX1 CEX0 ECI Crossbar Port I/O Figure 1.6. PCA Block Diagram 1.5. 10-Bit SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous Low Power Burst Mode C8051F93x-C8051F92x devices have a 300 ksps, 10-bit successive-approximation-register (SAR) ADC with integrated track-and-hold and programmable window detector. ADC0 also has an autonomous low power Burst Mode which can automatically enable ADC0, capture and accumulate samples, then place ADC0 in a low power shutdown mode without CPU intervention. It also has a 16-bit accumulator that can automatically average the ADC results, providing an effective 11, 12, or 13 bit ADC result without any additional CPU intervention. Rev. 1.2 23 C8051F93x-C8051F92x The ADC can sample the voltage at any of the GPIO pins (with the exception of P2.7) and has an on-chip attenuator that allows it to measure voltages up to twice the voltage reference. Additional ADC inputs include an on-chip temperature sensor, the VDD/DC+ supply voltage, the VBAT supply voltage, and the internal digital supply voltage. AD0CM0 AD0CM1 AD0CM2 AD0WINT AD0INT AD0BUSY BURSTEN AD0EN ADC0CN VDD Start Conversion ADC0TK Burst Mode Logic ADC0PWR ADC0L AIN+ ADC REF 16-Bit Accumulator SYSCLK AD0TM AMP0GN AD08BE AD0SC0 AD0SC1 AD0SC2 AD0SC3 AD0SC4 ADC0CF AD0WINT 32 ADC0LTH ADC0LTL ADC0GTH ADC0GTL Figure 1.7. ADC0 Functional Block Diagram 24 AD0BUSY (W) Timer 0 Overflow Timer 2 Overflow Timer 3 Overflow CNVSTR Input ADC0H From AMUX0 10-Bit SAR 000 001 010 011 100 Rev. 1.2 Window Compare Logic C8051F93x-C8051F92x AD0MX4 AD0MX3 AD0MX2 AD0MX1 AM0MX0 ADC0MX P0.0 Programmable Attenuator AIN+ P2.6* AMUX ADC0 Temp Sensor Gain = 0. 5 or 1 VBAT Digital Supply VDD/DC+ *P1.7-P2. 6 only available as inputs on 32- pin packages Figure 1.8. ADC0 Multiplexer Block Diagram 1.6. Programmable Current Reference (IREF0) C8051F93x-C8051F92x devices include an on-chip programmable current reference (source or sink) with two output current settings: low power mode and high current mode. The maximum current output in low power mode is 63 µA (1 µA steps) and the maximum current output in high current mode is 504 µA (8 µA steps). 1.7. Comparators C8051F93x-C8051F92x devices include two on-chip programmable voltage comparators: Comparator 0 (CPT0) which is shown in Figure 1.9; Comparator 1 (CPT1) which is shown in Figure 1.10. The two comparators operate identically but may differ in their ability to be used as reset or wake-up sources. See Section “18. Reset Sources” on page 180 and the Section “14. Power Management” on page 156 for details on reset sources and low power mode wake-up sources, respectively. The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an asynchronous “raw” output (CP0A, CP1A). The asynchronous CP0A signal is available even when the system clock is not active. This allows the Comparator to operate and generate an output when the device is in some low power modes. The comparator inputs may be connected to Port I/O pins or to other internal signals. Port pins may also be used to directly sense capacitive touch switches. Rev. 1.2 25 CPT0CN C8051F93x-C8051F92x CP0EN CP0OUT CP0RIF CP0FIF VDD CP0HYP1 CP0HYP0 CP0HYN1 CP0 Interrupt CP0HYN0 CPT0MD Analog Input Multiplexer CP0FIE CP0RIE CP0MD1 CP0MD0 Px.x CP0 Rising-edge CP0 + CP0 Falling-edge Interrupt Logic Px.x CP0 + SET D - CLR D Q Q SET CLR Q Q Px.x Crossbar (SYNCHRONIZER) GND CP0 - CP0A (ASYNCHRONOUS) Reset Decision Tree Px.x Figure 1.9. Comparator 0 Functional Block Diagram CPT0CN CP1EN CP1OUT CP1RIF VDD CP1FIF CP1HYP1 CP1 Interrupt CP1HYP0 CP1HYN1 CP1HYN0 CPT0MD Analog Input Multiplexer CP1FIE CP1RIE CP1MD1 CP1MD0 Px.x CP1 Rising-edge CP1 + CP1 Falling-edge Interrupt Logic Px.x CP1 + D - SET CLR Q Q D SET CLR Q Q Px.x Crossbar (SYNCHRONIZER) CP1 - GND (ASYNCHRONOUS) Reset Decision Tree Px.x Figure 1.10. Comparator 1 Functional Block Diagram 26 Rev. 1.2 CP1A C8051F93x-C8051F92x Ordering Information UART Enhanced SPI Timers (16-bit) Programmable Counter Array 10-bit 300ksps ADC Programmable Current Reference Internal Voltage Reference Temperature Sensor Analog Comparators Lead-free (RoHS Compliant) Package 1 1 2 4  24     2  QFN-32 C8051F930-GQ 25 64 4352  1 1 2 4  24     2  LQFP-32 C8051F931-GM 25 64 4352  1 1 2 4  16     2  QFN-24 C8051F920-GM 25 32 4352  1 1 2 4  24     2  QFN-32 C8051F920-GQ 25 32 4352  1 1 2 4  24     2  LQFP-32 C8051F921-GM 25 32 4352  1 1 2 4  16     2  QFN-24 Rev. 1.2 Digital Port I/Os SMBus/I2C  RAM (bytes) 25 64 4352 Flash Memory (kB) C8051F930-GM MIPS (Peak) SmaRTClock Real Time Clock Table 2.1. Product Selection Guide Ordering Part Number 2. 27 C8051F93x-C8051F92x 3. Pinout and Package Definitions Table 3.1. Pin Definitions for the C8051F92x-C8051F93x Name Pin Numbers ‘F920/30 ‘F921/31 Type Description VBAT 5 5 P In Battery Supply Voltage. Must be 0.9 to 1.8 V in single-cell battery mode and 1.8 to 3.6 V in dual-cell battery mode. VDD / 3 3 P In Power Supply Voltage. Must be 1.8 to 3.6 V. This supply voltage is not required in low power sleep mode. This voltage must always be > VBAT. DC+ DC– / 1 1 GND P Out Positive output of the dc-dc converter. In single-cell battery mode, a 1uF ceramic capacitor is required between DC+ and DC–. This pin can supply power to external devices when operating in single-cell battery mode. P In DC-DC converter return current path. In single-cell battery mode, this pin is typically not connected to ground. G In dual-cell battery mode, this pin must be connected directly to ground. Required Ground. GND 2 2 G DCEN 4 4 P In G RST/ 6 6 C2CK P2.7/ 7 7 C2D DC-DC Enable Pin. In single-cell battery mode, this pin must be connected to VBAT through a 0.68 µH inductor. In dual-cell battery mode, this pin must be connected directly to ground. D I/O Device Reset. Open-drain output of internal POR or VDD monitor. An external source can initiate a system reset by driving this pin low for at least 15 µs. A 1 k to 5 k pullup to VDD is recommended. See Reset Sources Section for a complete description. D I/O Clock signal for the C2 Debug Interface. D I/O Port 2.7. This pin can only be used as GPIO. The Crossbar cannot route signals to this pin and it cannot be configured as an analog input. See Port I/O Section for a complete description. D I/O Bi-directional data signal for the C2 Debug Interface. XTAL3 10 9 A In SmaRTClock Oscillator Crystal Input. See Section 20 for a complete description. XTAL4 9 8 A Out SmaRTClock Oscillator Crystal Output. See Section 20 for a complete description. *Note: Available only on the C8051F920/30. 28 Rev. 1.2 C8051F93x-C8051F92x Table 3.1. Pin Definitions for the C8051F92x-C8051F93x (Continued) Name P0.0 Pin Numbers ‘F920/30 ‘F921/31 32 24 VREF P0.1 31 23 22 XTAL1 P0.3 21 XTAL2 A Out A In 28 20 TX P0.5 19 RX P0.6 18 CNVSTR P0.7 IREF0 17 UART RX Pin. See Port I/O Section. D I/O or Port 0.6. See Port I/O Section for a complete description. A In D In 25 UART TX Pin. See Port I/O Section. D I/O or Port 0.5. See Port I/O Section for a complete description. A In D In 26 External Clock Output. This pin is the excitation driver for an external crystal or resonator. External Clock Input. This pin is the external clock input in external CMOS clock mode. External Clock Input. This pin is the external clock input in capacitor or RC oscillator configurations. See Oscillator Section for complete details. D I/O or Port 0.4. See Port I/O Section for a complete description. A In D Out 27 External Clock Input. This pin is the external oscillator return for a crystal or resonator. See Oscillator Section. D I/O or Port 0.3. See Port I/O Section for a complete description. A In D In P0.4 Optional Analog Ground. See ADC0 Section for details. D I/O or Port 0.2. See Port I/O Section for a complete description. A In A In 29 External VREF Input. Internal VREF Output. External VREF decoupling capacitors are recommended. See ADC0 Section for details. D I/O or Port 0.1. See Port I/O Section for a complete description. A In G 30 Description D I/O or Port 0.0. See Port I/O Section for a complete description. A In A In A Out AGND P0.2 Type External Convert Start Input for ADC0. See ADC0 section for a complete description. D I/O or Port 0.7. See Port I/O Section for a complete description. A In A Out IREF0 Output. See IREF Section for complete description. *Note: Available only on the C8051F920/30. Rev. 1.2 29 C8051F93x-C8051F92x Table 3.1. Pin Definitions for the C8051F92x-C8051F93x (Continued) Name P1.0 Pin Numbers ‘F920/30 ‘F921/31 24 16 AD0* P1.1 23 15 14 AD2* P1.3 13 AD3* P1.4 12 AD4* P1.5 11 AD5* Address/Data 3. D I/O or Port 1.4. See Port I/O Section for a complete description. A In D I/O 19 Address/Data 2. D I/O or Port 1.3. See Port I/O Section for a complete description. A In May also be used as NSS for SPI1. D I/O 20 Address/Data 1. D I/O or Port 1.2. See Port I/O Section for a complete description. A In May also be used as MOSI for SPI1. D I/O 21 Address/Data 0. D I/O or Port 1.1. See Port I/O Section for a complete description. A In May also be used as MISO for SPI1. D I/O 22 Description D I/O or Port 1.0. See Port I/O Section for a complete description. May also be used as SCK for SPI1. A In D I/O AD1* P1.2 Type Address/Data 4. D I/O or Port 1.5. See Port I/O Section for a complete description. A In D I/O Address/Data 5. P1.6 18 AD6* P1.7* AD8* D I/O or Port 1.6. See Port I/O Section for a complete description. A In D I/O 17 AD7* P2.0* 10 D I/O or Port 1.7. See Port I/O Section for a complete description. A In D I/O 16 Address/Data 6. Address/Data 7. D I/O or Port 2.0. See Port I/O Section for a complete description. A In D I/O Address/Data 8. *Note: Available only on the C8051F920/30. 30 Rev. 1.2 C8051F93x-C8051F92x Table 3.1. Pin Definitions for the C8051F92x-C8051F93x (Continued) Name P2.1* Pin Numbers ‘F920/30 ‘F921/31 15 AD9* P2.2* 14 AD11* P2.4* ALE* P2.5* RD* P2.6* WR* Address Latch Enable. D I/O or Port 2.5. See Port I/O Section for a complete description. A In DO 8 Address/Data 11. D I/O or Port 2.4. See Port I/O Section for a complete description. A In DO 11 Address/Data 10. D I/O or Port 2.3. See Port I/O Section for a complete description. A In D I/O 12 Address/Data 9. D I/O or Port 2.2. See Port I/O Section for a complete description. A In D I/O 13 Description D I/O or Port 2.1. See Port I/O Section for a complete description. A In D I/O AD10* P2.3* Type Read Strobe. D I/O or Port 2.6. See Port I/O Section for a complete description. A In DO Write Strobe. *Note: Available only on the C8051F920/30. Rev. 1.2 31 P0.0/VREF P0.1/AGND P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6/CNVSTR P0.7/IREF0 32 31 30 29 28 27 26 25 C8051F93x-C8051F92x GND/DC- 1 24 P1.0/AD0 GND 2 23 P1.1/AD1 VDD/DC+ 3 22 P1.2/AD2 DCEN 4 21 P1.3/AD3 VBAT 5 20 P1.4/AD4 RST/C2CK 6 19 P1.5/AD5 P2.7/C2D 7 18 P1.6/AD6 P2.6/WR 8 17 P1.7/AD7 9 10 11 12 13 14 15 16 XTAL4 XTAL3 P2.5/RD P2.4/ALE P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8 C8051F930/20-GM Top View Figure 3.1. QFN-32 Pinout Diagram (Top View) 32 Rev. 1.2 P0.0/VREF P0.1/AGND P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX 24 23 22 21 20 19 C8051F93x-C8051F92x GND/DC- 1 18 P0.6/CNVSTR GND 2 17 P0.7/IREF0 VDD/DC+ 3 16 P1.0 DCEN 4 15 P1.1 VBAT 5 14 P1.2 RST/C2CK 6 13 P1.3 11 12 P1.5 P1.4 9 XTAL3 10 8 XTAL4 P1.6 7 P2.7/C2D C8051F931/21-GM Top View Figure 3.2. QFN-24 Pinout Diagram (Top View) Rev. 1.2 33 P0.0 / VREF P0.1 / AGND P0.2 / XTAL1 P0.3 / XTAL2 P0.4 / TX P0.5 / RX P0.6 / CNVSTR P0.7 / IREF0 32 31 30 29 28 27 26 25 C8051F93x-C8051F92x GND / DC- 1 24 P1.0 / AD0 GND 2 23 P1.1 / AD1 VDD / DC+ 3 22 P1.2 / AD2 DCEN 4 21 P1.3 / AD3 VBAT 5 20 P1.4 / AD4 RST / C2CK 6 19 P1.5 / AD5 P2.7 / C2D 7 18 P1.6 / AD6 P2.6 / WR 8 17 P1.7 / AD7 9 10 11 12 13 14 15 16 XTAL4 XTAL3 P2.5 / RD P2.4 / ALE P2.3 / A11 P2.2 / A10 P2.1 / A9 P2.0 / A8 C8051F930/20-GQ Top View Figure 3.3. LQFP-32 Pinout Diagram (Top View) 34 Rev. 1.2 C8051F93x-C8051F92x Figure 3.4. QFN-32 Package Drawing Table 3.2. QFN-32 Package Dimensions Dimension Min Typ Max Dimension Min Typ Max A A1 b D D2 e E 0.80 0.00 0.18 0.9 0.02 0.25 5.00 BSC 3.30 0.50 BSC 5.00 BSC 1.00 0.05 0.30 E2 L L1 aaa bbb ddd eee 3.20 0.30 0.00 — — — — 3.30 0.40 — — — — — 3.40 0.50 0.15 0.15 0.10 0.05 0.08 3.20 3.40 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-220, variation VHHD except for custom features D2, E2, and L which are toleranced per supplier designation. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.2 35 C8051F93x-C8051F92x Figure 3.5. Typical QFN-32 Landing Diagram 36 Rev. 1.2 C8051F93x-C8051F92x Table 3.3. PCB Land Pattern Dimension MIN MAX C1 4.80 4.90 C2 4.80 4.90 E 0.50 BSC X1 0.20 0.30 X2 3.20 3.40 Y1 0.75 0.85 Y2 3.20 3.40 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 4. A 3 x 3 array of 1.0 mm square openings on 1.2 mm pitch should be used for the center ground pad. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.2 37 C8051F93x-C8051F92x Figure 3.6. QFN-24 Package Drawing Table 3.4. QFN-24 Package Dimensions Dimension Min Typ Max Dimension Min Typ Max A 0.70 0.75 0.80 L 0.30 0.40 0.50 A1 0.00 0.02 0.05 L1 0.00 — 0.15 b 0.18 0.25 0.30 aaa — — 0.15 bbb — — 0.10 ddd — — 0.05 D D2 4.00 BSC 2.55 2.70 2.80 e 0.50 BSC eee — — 0.08 E 4.00 BSC Z — 0.24 — Y — 0.18 — E2 2.55 2.70 2.80 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-220, variation WGGD except for custom features D2, E2, Z, Y, and L which are toleranced per supplier designation. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 38 Rev. 1.2 C8051F93x-C8051F92x Figure 3.7. Typical QFN-24 Landing Diagram Rev. 1.2 39 C8051F93x-C8051F92x Table 3.5. PCB Land Pattern Dimension MIN MAX C1 3.90 4.00 C2 3.90 4.00 E 0.50 BSC X1 0.20 0.30 X2 2.70 2.80 Y1 0.65 0.75 Y2 2.70 2.80 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 4. A 2 x 2 array of 1.0 x 1.0 mm square openings on 1.30 mm pitch should be used for the center ground pad. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 40 Rev. 1.2 C8051F93x-C8051F92x Figure 3.8. LQFP-32 Package Diagram Table 3.6. LQFP-32 Package Dimensions Dimension Min Typ Max Dimension Min A — — 1.60 E 9.00 BSC A1 0.05 — 0.15 E1 7.00 BSC A2 1.35 1.40 1.45 L b 0.30 0.37 0.45 aaa 0.20 c 0.09 — 0.20 bbb 0.20 0.45 Typ 0.60 D 9.00 BSC. ccc 0.10 D1 7.00 BSC ddd 0.20 e 0.80 BSC  0º 3.5º Max 0.75 7º Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MS-026, variation BBA. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.2 41 C8051F93x-C8051F92x Figure 3.9. Typical LQFP-32 Landing Diagram Table 3.7. PCB Land Pattern Dimension MIN MAX C1 8.40 8.50 C2 8.40 8.50 E 0.80 BSC X1 0.40 0.50 Y1 1.25 1.35 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 42 Rev. 1.2 C8051F93x-C8051F92x 4. Electrical Characteristics Throughout the Electrical Characteristics chapter, “VDD” refers to the VDD/DC+ Supply Voltage. 4.1. Absolute Maximum Specifications Table 4.1. Absolute Maximum Ratings Parameter Conditions Min Typ Max Units Ambient temperature under bias –55 — 125 °C Storage Temperature –65 — 150 °C Voltage on any Port I/O Pin or RST with respect to GND VDD > 2.2 V VDD < 2.2 V –0.3 –0.3 — — 5.8 VDD + 3.6 V Voltage on VBAT with respect to GND One-Cell Mode Two-Cell Mode –0.3 –0.3 — — 2.0 4.0 V Voltage on VDD/DC+ with respect to GND –0.3 — 4.0 V Maximum Total current through VBAT, DCEN, VDD/DC+ or GND — — 500 mA Maximum output current sunk by RST or any Port pin — — 100 mA Maximum total current through all Port pins — — 200 mA DC-DC Converter Output Power — — 110 mW Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Rev. 1.2 43 C8051F93x-C8051F92x 4.2. Electrical Characteristics Table 4.2. Global Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the ‘F9xx" for details on how to achieve the supply current specifications listed in this table. Parameter Conditions Min Typ Max Units Battery Supply Voltage (VBAT) One-Cell Mode Two-Cell Mode 0.9 1.8 1.2 2.4 1.8 3.6 V Supply Voltage (VDD/DC+) One-Cell Mode Two-Cell Mode 1.8 1.8 1.9 2.4 3.6 3.6 V Minimum RAM Data  Retention Voltage1 VDD (not in Sleep Mode) VBAT (in Sleep Mode) — — 1.4 0.3 — 0.5 V SYSCLK (System Clock)2 0 — 25 MHz TSYSH (SYSCLK High Time) 18 — — ns TSYSL (SYSCLK Low Time) 18 — — ns Specified Operating  Temperature Range –40 — +85 °C Digital Supply Current—CPU Active (Normal Mode, fetching instructions from Flash) VDD = 1.8–3.6 V, F = 24.5 MHz  (includes precision oscillator current) — 4.1 5.0 mA VDD = 1.8–3.6 V, F = 20 MHz (includes low power oscillator current) — 3.5 — mA VDD = 1.8 V, F = 1 MHz VDD = 3.6 V, F = 1 MHz (includes external oscillator/GPIO current) — — 295 365 — — µA µA VDD = 1.8–3.6 V, F = 32.768 kHz  (includes SmaRTClock oscillator current) — 90 — µA IDD Frequency Sensitivity3, 5, 6 VDD = 1.8–3.6 V, T = 25 °C, F < 10 MHz (Flash oneshot active, see Section 13.6) — 226 — µA/MHz — 120 — µA/MHz IDD 3, 4, 5, 6 VDD = 1.8–3.6 V, T = 25 °C, F > 10 MHz (Flash oneshot bypassed, see Section 13.6) Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from Flash) IDD4, 6, 7 IDD Frequency Sensitivity1,6,7 44 VDD = 1.8–3.6 V, F = 24.5 MHz  (includes precision oscillator current) — 2.5 3.0 mA VDD = 1.8–3.6 V, F = 20 MHz (includes low power oscillator current) — 1.8 — mA VDD = 1.8 V, F = 1 MHz VDD = 3.6 V, F = 1 MHz (includes external oscillator/GPIO current) — — 165 235 — — µA µA VDD = 1.8–3.6 V, F = 32.768 kHz (includes SmaRTClock oscillator current) — 84 — µA VDD = 1.8–3.6 V, T = 25 °C — 95 — µA/MHz Rev. 1.2 C8051F93x-C8051F92x Table 4.2. Global Electrical Characteristics (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the ‘F9xx" for details on how to achieve the supply current specifications listed in this table. Parameter Conditions Min Typ Max Units Digital Supply Current—Suspend and Sleep Mode Digital Supply Current6  (Suspend Mode) VDD = 1.8–3.6 V, two-cell mode — 77 — µA Digital Supply Current (Sleep Mode, SmaRTClock running) 1.8 V, T = 25 °C 3.0 V, T = 25 °C 3.6 V, T = 25 °C 1.8 V, T = 85 °C 3.0 V, T = 85 °C 3.6 V, T = 85 °C (includes SmaRTClock oscillator and VBAT Supply Monitor) — — — — — — 0.60 0.75 0.85 1.30 1.60 1.90 — — — — — — µA µA µA µA µA µA Digital Supply Current (Sleep Mode) 1.8 V, T = 25 °C 3.0 V, T = 25 °C 3.6 V, T = 25 °C 1.8 V, T = 85 °C 3.0 V, T = 85 °C 3.6 V, T = 85 °C (includes VBAT supply monitor) — — — — — — 0.05 0.08 0.12 0.75 0.90 1.20 — — — — — — µA µA µA µA µA µA Notes: 1. Based on device characterization data; Not production tested. 2. SYSCLK must be at least 32 kHz to enable debugging. 3. Digital Supply Current depends upon the particular code being executed. The values in this table are obtained with the CPU executing an “sjmp $” loop, which is the compiled form of a while(1) loop in C. One iteration requires 3 CPU clock cycles, and the Flash memory is read on each cycle. The supply current will vary slightly based on the physical location of the sjmp instruction and the number of Flash address lines that toggle as a result. In the worst case, current can increase by up to 30% if the sjmp loop straddles a 128-byte Flash address boundary (e.g., 0x007F to 0x0080). Real-world code with larger loops and longer linear sequences will have few transitions across the 128-byte address boundaries. 4. Includes oscillator and regulator supply current. 5. IDD can be estimated for frequencies 10 MHz, the estimate should be the current at 25 MHz minus the difference in current indicated by the frequency sensitivity number. For example: VDD = 3.0 V; F = 20 MHz, IDD = 4.1 mA – (25 MHz – 20 MHz) x 0.120 mA/MHz = 3.5 mA. 6. The supply current specifications in Table 4.2 are for two cell mode. The VBAT current in one-cell mode can be estimated using the following equation: Supply Voltage  Supply Current (two-cell mode) VBAT Current (one-cell mode) = ----------------------------------------------------------------------------------------------------------------------------------DC-DC Converter Efficiency  VBAT Voltage The VBAT Voltage is the voltage at the VBAT pin, typically 0.9 to 1.8 V. The Supply Current (two-cell mode) is the data sheet specification for supply current. The Supply Voltage is the voltage at the VDD/DC+ pin, typically 1.8 to 3.3 V (default = 1.9 V). The DC-DC Converter Efficiency can be estimated using Figure 4.3–Figure 4.5. 7. Idle IDD can be estimated by taking the current at 25 MHz minus the difference in current indicated by the frequency sensitivity number. For example: VDD = 3.0 V; F = 5 MHz, Idle IDD = 2.5 mA – (25 MHz – 5 MHz) x 0.095 mA/MHz = 0.6 mA. Rev. 1.2 45 C8051F93x-C8051F92x 4200 4100 F < 10 MHz Oneshot Enabled 4000 3900 F > 10 MHz Oneshot Bypassed 3800 3700 3600 3500 3400 < 170 µA/MHz 3300 3200 3100 3000 2900 200 µA/MHz 2800 2700 2600 215 µA/MHz Supply Current (uA) 2500 2400 2300 2200 2100 2000 1900 1800 1700 1600 1500 1400 240 µA/MHz 1300 1200 1100 1000 900 800 250 µA/MHz 700 600 500 400 300 300 µA/MHz 200 100 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Frequency (MHz) Figure 4.1. Active Mode Current (External CMOS Clock) 46 Rev. 1.2 22 23 24 25 C8051F93x-C8051F92x 4200 4100 4000 3900 3800 3700 3600 3500 3400 3300 3200 3100 3000 2900 2800 2700 2600 Supply Current (uA) 2500 2400 2300 2200 2100 2000 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Frequency (MHz) Figure 4.2. Idle Mode Current (External CMOS Clock) Rev. 1.2 47 C8051F93x-C8051F92x  6:6(/  6:6(/              Efficiency (%)   9%$7 9  9%$7 9  9%$7 9  9%$7 9  9%$7 9  9%$7 9 9%$7 9   X+,QGXFWRUSDFNDJH(65 2KPV 9'''& 90LQLPXP3XOVH:LGWK QV3XOVH6NLSSLQJ'LVDEOHG   1RWH(IILFLHQF\DWKLJKFXUUHQWVPD\EHLPSURYHGE\FKRRVLQJDQ LQGXFWRUZLWKDORZHU(65                                  Load Current (mA) Figure 4.3. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 2 V) 48 Rev. 1.2 C8051F93x-C8051F92x 6:6(/   6:6(/             9%$7 9 Efficiency (%)  9%$7 9 9%$7 9  9%$7 9  9%$7 9  9%$7 9 9%$7 9    X+,QGXFWRUSDFNDJH(65 2KPV 9'''& 90LQLPXP3XOVH:LGWK QV 3XOVH6NLSSLQJ'LVDEOHG 1RWH(IILFLHQF\DWKLJKFXUUHQWVPD\EHLPSURYHGE\ FKRRVLQJDQLQGXFWRUZLWKDORZHU(65                                 Load current (mA) Figure 4.4. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 3 V) Rev. 1.2 49 C8051F93x-C8051F92x     9%$7 9 9%$7 9 Efficiency (%)  9%$7 9 9%$7 9 9%$7 9  9%$7 9 9%$7 9   X+,QGXFWRUSDFNDJH(65 2KPV 6:6(/ 9'''& 90LQLPXP3XOVH:LGWK QV                 Load current (mA) Figure 4.5. Typical DC-DC Converter Efficiency (Low Current, VDD/DC+ = 2 V) 50 Rev. 1.2 C8051F93x-C8051F92x  X+,QGXFWRUSDFNDJH(65 2KPV 6:6(/ 9'''& 9/RDG&XUUHQW X$    0LQ3XOVH:LGWKQV  0LQ3XOVH:LGWKQV  0LQ3XOVH:LGWKQV 0LQ3XOVH:LGWKQV  9%$7&XUUHQWX$                      9%$79 Figure 4.6. Typical One-Cell Suspend Mode Current Rev. 1.2 51 C8051F93x-C8051F92x Table 4.3. Port I/O DC Electrical Characteristics VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. Parameters Conditions Min Typ Max IOH = –3 mA, Port I/O push-pull VDD – 0.7 — — IOH = –10 µA, Port I/O push-pull VDD – 0.1 — — Units Output High Voltage High Drive Strength, PnDRV.n = 1 IOH = –10 mA, Port I/O push-pull See Chart V Low Drive Strength, PnDRV.n = 0 IOH = –1 mA, Port I/O push-pull VDD – 0.7 — — IOH = –10 µA, Port I/O push-pull VDD – 0.1 — — — See Chart — IOL = 8.5 mA — — 0.6 IOL = 10 µA — — 0.1 IOL = 25 mA — See Chart — IOH = –3 mA, Port I/O push-pull Output Low Voltage High Drive Strength, PnDRV.n = 1 V Low Drive Strength, PnDRV.n = 0 Input High Voltage Input Low Voltage Input Leakage  Current 52 IOL = 1.4 mA — — 0.6 IOL = 10 µA — — 0.1 IOL = 4 mA — See Chart — VDD = 2.0 to 3.6 V VDD – 0.6 — — V VDD = 0.9 to 2.0 V 0.7 x VDD — — V VDD = 2.0 to 3.6 V — — 0.6 V VDD = 0.9 to 2.0 V — — 0.3 x VDD V Weak Pullup Off — — ±1 Weak Pullup On, VIN = 0 V, VDD = 1.8 V — 4 — Weak Pullup On, Vin = 0 V, VDD = 3.6 V — 20 30 Rev. 1.2 µA C8051F93x-C8051F92x Typical VOH (High Drive Mode) Voltage 3.6 3.3 VDD = 3.6V 3 VDD = 3.0V 2.7 VDD = 2.4V 2.4 VDD = 1.8V 2.1 1.8 1.5 1.2 0.9 0 5 10 15 20 25 30 35 40 45 50 Load Current (mA) Typical VOH (Low Drive Mode) Voltage 3.6 3.3 VDD = 3.6V 3 VDD = 3.0V 2.7 VDD = 2.4V 2.4 VDD = 1.8V 2.1 1.8 1.5 1.2 0.9 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Load Current (mA) Figure 4.7. Typical VOH Curves, 1.8–3.6 V Rev. 1.2 53 C8051F93x-C8051F92x Typical VOH (High Drive Mode) 1.8 VDD = 1.8V 1.7 1.6 VDD = 1.5V 1.5 1.4 VDD = 1.2V Voltage 1.3 VDD = 0.9V 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0 1 2 3 4 5 6 7 8 9 10 11 12 Load Current (mA) Typical VOH (Low Drive Mode) 1.8 1.7 VDD = 1.8V 1.6 VDD = 1.5V 1.5 1.4 VDD = 1.2V Voltage 1.3 1.2 VDD = 0.9V 1.1 1 0.9 0.8 0.7 0.6 0.5 0 1 2 3 Load Current (mA) Figure 4.8. Typical VOH Curves, 0.9–1.8 V 54 Rev. 1.2 C8051F93x-C8051F92x Typical VOL (High Drive Mode) 1.8 VDD = 3.6V 1.5 VDD = 3.0V Voltage 1.2 VDD = 2.4V VDD = 1.8V 0.9 0.6 0.3 0 -80 -70 -60 -50 -40 -30 -20 -10 0 Load Current (mA) Typical VOL (Low Drive Mode) 1.8 VDD = 3.6V 1.5 VDD = 3.0V Voltage 1.2 VDD = 2.4V VDD = 1.8V 0.9 0.6 0.3 0 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 Load Current (mA) Figure 4.9. Typical VOL Curves, 1.8–3.6 V Rev. 1.2 55 C8051F93x-C8051F92x Typical VOL (High Drive Mode) 0.5 VDD = 1.8V Voltage 0.4 VDD = 1.5V VDD = 1.2V 0.3 VDD = 0.9V 0.2 0.1 0 -5 -4 -3 -2 -1 0 Load Current (mA) Typical VOL (Low Drive Mode) 0.5 Voltage 0.4 0.3 VDD = 1.8V 0.2 VDD = 1.5V VDD = 1.2V 0.1 VDD = 0.9V 0 -3 -2 -1 0 Load Current (mA) Figure 4.10. Typical VOL Curves, 0.9–1.8 V 56 Rev. 1.2 C8051F93x-C8051F92x Table 4.4. Reset Electrical Characteristics VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. Parameter Conditions Min Typ Max Units — — 0.6 V RST Output Low Voltage IOL = 1.4 mA, RST Input High Voltage VDD = 2.0 to 3.6 V VDD – 0.6 — — V VDD = 0.9 to 2.0 V 0.7 x VDD — — V VDD = 2.0 to 3.6 V — — 0.6 V VDD = 0.9 to 2.0 V — — 0.3 x VDD V RST Input Pullup Current RST = 0.0 V, VDD = 1.8 V RST = 0.0 V, VDD = 3.6 V — 4 — — 20 30 VDD/DC+ Monitor Threshold (VRST) Early Warning Reset Trigger (all power modes except Sleep) 1.8 1.85 1.9 1.7 1.75 1.8 VBAT Ramp Time for Power On VBAT Ramp from 0–0.9 V — — 3 RST Input Low Voltage µA V ms VBAT Monitor Threshold (VPOR) Initial Power-On (VBAT Rising) Brownout Condition (VBAT Falling) Recovery from Brownout (VBAT Rising) — 0.75 — 0.7 0.8 0.9 — 0.95 — Missing Clock Detector Timeout Time from last system clock rising edge to reset initiation 100 650 1000 µs Minimum System Clock w/ Missing Clock Detector Enabled System clock frequency which triggers a missing clock detector timeout — 7 10 kHz Reset Time Delay Delay between release of any reset source and code  execution at location 0x0000 — 10 — µs Minimum RST Low Time to Generate a System Reset 15 — — µs VDD Monitor Turn-on Time — 300 — ns VDD Monitor Supply  Current — 7 — µA Rev. 1.2 V 57 C8051F93x-C8051F92x Table 4.5. Power Management Electrical Specifications VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. Parameter Conditions Min Typ Max Units Idle Mode Wake-up Time 2 — 3 SYSCLKs Suspend Mode Wake-up Time Low power oscillator — 400 — ns Precision oscillator — 1.3 — µs Two-cell mode — 2 — µs One-cell mode — 10 — µs Sleep Mode Wake-up Time Table 4.6. Flash Electrical Characteristics VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. Parameter Flash Size Conditions C8051F930/1 C8051F920/1 Min 65536* 32768 1024 Typ — — — Max — — 1024 Endurance 1k 30k — Erase Cycle Time Write Cycle Time 28 57 32 64 36 71 Scratchpad Size Units bytes bytes bytes Erase/Write Cycles ms µs *Note: 1024 bytes at addresses 0xFC00 to 0xFFFF are reserved. Table 4.7. Internal Precision Oscillator Electrical Characteristics VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings. Parameter Oscillator Frequency Oscillator Supply Current  (from VDD) Min Typ Max Units –40 to +85 °C,  VDD = 1.8–3.6 V Conditions 24 24.5 25 MHz 25 °C; includes bias current of 90–100 µA — 300* — µA *Note: Does not include clock divider or clock tree supply current. Table 4.8. Internal Low-Power Oscillator Electrical Characteristics VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings. Parameter Oscillator Frequency Oscillator Supply Current  (from VDD) Conditions –40 to +85 °C,  VDD = 1.8–3.6 V 25 °C No separate bias current required. *Note: Does not include clock divider or clock tree supply current. 58 Rev. 1.2 Min Typ Max Units 18 20 22 MHz — 100* — µA C8051F93x-C8051F92x Table 4.9. ADC0 Electrical Characteristics VDD = 1.8 to 3.6V V, VREF = 1.65 V (REFSL[1:0] = 11), –40 to +85 °C unless otherwise specified. Parameter Conditions DC Accuracy Min Resolution Typ Max 10 Integral Nonlinearity Units bits — ±0.5 ±1 LSB — ±0.5 ±1 LSB Offset Error — ±