C8051F96x
Ultra-Low-Power, High-Efficiency, Battery-Powered Metering MCU
Ultra-Low Power @ 3.6 V High-Speed Enhanced 8051 µC Core
-
110 µA/MHz, Low-Power Active, DC-DC enabled 110 nA sleep current with data retention; POR monitor enabled 400 nA sleep current with smaRTClock (internal LFO) 700 nA sleep current with smaRTClock (external XTAL) 2 µs wake-up from any sleep mode
- Pipe-lined instruction architecture executes 70% of instructions
in 1 or 2 system clocks
Memory
- Up to 128 kB Flash; In-system programmable; Full read/write/
erase functionality over the entire supply range
12-Bit; 16 ch. Analog to Digital Converter
- Up to 8 kB data retention RAM
Digital Peripherals
- Up to 75 ksps, 12-bit mode or 300 ksps 10-bit mode - External pin or internal VREF (no external capacitor required) - On-chip PGA allows measuring voltages up to twice the
reference voltage
- Up to 57 port I/O; All 5 V tolerant with programmable drive
strength
- Hardware enhanced UART, 2 SPI and I2C serial ports available
concurrently
- Autonomous burst mode with 16-bit automatic averaging
accumulator
- Integrated temperature sensor
Two Low Current Comparators
- Four general-purpose 16-bit counter/timers - 16-bit programmable counter array (PCA) with six capture/compare/PWM modules and watchdog timer
- Programmable hysteresis and response time - Configurable as interrupt or reset source
Internal 6-Bit Current Reference
Clock Sources
- Precision internal oscillators: 24.5 MHz with ±2% accuracy supports UART operation; spread-spectrum mode for reduced EMI
- Up to ±500 µA; source and sink capability - Enhanced resolution via PWM interpolation
Integrated LCD Controller
- Low power internal oscillator: 20 MHz - External oscillator: Crystal, RC, C, CMOS clock - SmaRTClock oscillator: 32.768 kHz crystal or 16.4 kHz internal
LFO with three independent alarms
- Supports up to 128 segments (32x4) - Integrated charge pump for contrast control
Metering-Specific Peripherals
On-Chip Debug
- On-chip debug circuitry facilitates full speed, non-intrusive insystem debug (no emulator required)
- DC-DC buck converter allows dynamic voltage scaling for
maximum efficiency (250 mW output)
- Provides four breakpoints, single stepping
Package Options
- Sleep-mode pulse accumulator with programmable switch de-bounce and pull-up control interfaces directly to metering sensor Data Packet Processing Engine (DPPE) includes hardware AES, DMA, CRC, and encoding blocks for acceleration of wireless protocols Manchester and Three-out-of-Six encoder hardware for powerefficient implementation of the wireless M-bus specification
CIP-51 8051 Controller Core
128k Byte ISP Flash Program Memory 256 Byte SRAM 8092 Byte XRAM
- 76-pin DQFN (6x6 mm), RoHS compliant - 40-pin QFN (6x6 mm), RoHS compliant - 80-pin QFP (12x12 mm), RoHS compliant
Development Kit: C8051F960DK Supply Voltage: 1.8 to 3.8 V Temperature Range: –40 to +85 °C
Power On Reset/PMU
Wake Reset
Port I/O Configuration
Digital Peripherals
UART Timers 0, 1, 2, 3 PCA/WDT SMBus Priority Crossbar Decoder Port 0 Drivers
C2CK/RST
Debug / Programming Hardware C2D
P0.0/VREF P0.1/AGND P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6/CNVSTR P0.7 P1.0/PC0 P1.1/PC1 P1.2/XTAL3 P1.3/XTAL4 P1.4 P1.5/INT5 P1.6/INT6 P1.7 P2.0/SCK1 P2.1/MISO1 P2.2/MOSI1 P2.3/NSS1 P2.4 P2.5 P2.6 P2.7
32
DMA VBAT VDC
VBAT VDD Analog Power
SPI 0 SPI 1
(DMA Enabled)
CRC Engine AES Engine
Encoder
VREG
Digital Power
Port 1 Drivers
Crossbar Control
VBATDC IND GNDDC
DC/DC Buck Converter Precision 24.5 MHz Oscillator LCD Charge Pump XTAL1 XTAL2 Low Power 20 MHz Oscillator External Oscillator Circuit Enhanced smaRTClock Oscillator
SYSCLK
SFR Bus
LCD (up to 4x32) EMIF Pulse Counter Port 2 Drivers
Analog Peripherals
Internal VREF External VREF A M U X VDD VREF Temp Sensor GND CP0, CP0A CP1, CP1A
+ -
CAP
P3-6 Drivers P7 Driver
P3.0...P6.7
16
GND
XTAL3 XTAL4
12-bit 75ksps ADC
P7.0/C2D
System Clock Configuration
+ -
Comparators
Low-Voltage/Low-Power
Copyright © 2011 by Silicon Laboratories
11.03.11
C8051F96x
Ultra-Low-Power, High-Efficiency, Battery-Powered Metering MCU
Selected Electrical Specifications
Parameter Active mode current Active mode current Symbol IBAT IBAT Conditions VBAT = 3.6 V, F = 20 MHz F = 20 MHz LFO; DC-DC enabled executing code from FLASH; PCLKACT = 0x00; VBAT = 3.6 V Sleep Mode, SmaRTClock running, internal LFO; 3.6 V Sleep Mode, SmaRTClock running, 32.768 kHz crystal; 3.6 V 3.6 V input voltage Internal LFO, LCD charge pump disabled; 60 Hz; non-multiplexed operation (static mode); 3.6 V Min — — Typ 110 2.2 Max — — Units uA/MHz mA
Sleep mode current
IDD
—
0.4
—
uA
Sleep mode current
IDD
—
0.7
—
uA
Buck regulator efficiency LCD refresh current 1
— —
80 0.4
— —
% uA
LCD refresh current 2
Internal LFO, LCD charge pump disabled; 60 Hz; multiplexed operation; 3.6 V VBAT
—
0.8
—
uA
Supply input voltage
1.8
3.6
3.8
V
Product Family
Part Number C8051F960-A-GM C8051F960-A-GQ C8051F961-A-GM C8051F962-A-GM C8051F962-A-GQ C8051F963-A-GM C8051F964-A-GM C8051F964-A-GQ C8051F965-A-GM C8051F966-A-GM C8051F966-A-GQ C8051F967-A-GM C8051F968-A-GM C8051F968-A-GQ C8051F969-A-GM Memory (Flash/RAM) 128 kB / 8 kB 128 kB / 8 kB 128 kB / 8 kB 128 kB / 8 kB 128 kB / 8 kB 128 kB / 8 kB 64 kB / 8 kB 64 kB / 8 kB 64 kB / 8 kB 32 kB / 8 kB 32 kB / 8 kB 32 kB / 8 kB 16 kB / 4 kB 16 kB / 4 kB 16 kB / 4 kB I/O 57 57 34 57 57 34 57 57 34 57 57 34 57 57 34 LCD 32x4 32x4 9x4 — — — 32x4 32x4 9x4 32x4 32x4 9x4 32x4 32x4 9x4 Package (mm) DQFN76 (6x6) QFP80 (12x12) QFN40 (6x6) DQFN76 (6x6) QFP80 (12x12) QFN40 (6x6) DQFN76 (6x6) QFP80 (12x12) QFN40 (6x6) DQFN76 (6x6) QFP80 (12x12) QFN40 (6x6) DQFN76 (6x6) QFP80 (12x12) QFN40 (6x6)
Low-Voltage/Low-Power
Copyright © 2011 by Silicon Laboratories
11.03.11
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders
很抱歉,暂时无法提供与“C8051F960-A-GQ”相匹配的价格&库存,您可以联系我们找货
免费人工找货