C8051F96x
Ultra Low Power 128K, LCD MCU Family
Ultra Low Power Consumption at 3.6V
- 130 µA/MHz Low-Power Active mode with dc-dc
enabled
- 110 nA sleep current w/ data retention; POR monitor
enabled
- 400 nA sleep mode with SmaRTClock
(internal LFO)
- 700 nA sleep mode with SmaRTClock (ext. crystal)
- 2 µs wakeup time; 1.5 µA analog settling time
12-Bit; 16 Ch. Analog-to-Digital Converter
- Up to 75 ksps (12-bit mode) or 300 ksps
(10-bit mode)
- External pin or internal VREF (no ext cap required)
- On-chip voltage reference; 0.5x gain allows measuring voltages up to twice the reference voltage
- Autonomous burst mode with 16-bit auto-averaging
accumulator
- Integrated temperature sensor
Two Low Current Comparators
- Programmable hysteresis and response time
- Configurable as wake-up or reset source
Internal 6-Bit Current Reference
- Up to ±500 µA; source and sink capability
- Enhanced resolution via PWM interpolation
Integrated LCD Controller
- Supports up to 128 segments (32x4)
- LCD controller consumes only 400 nA for 32segment static display
- Integrated charge pump for contrast control
Metering-Specific Peripherals
- DC-DC buck converter allows dynamic voltage
scaling for maximum efficiency (250 mW output)
- Sleep-mode pulse accumulator with programmable
switch, de-bounce and pull-up control; interfaces
directly to metering sensor
Wake
Reset
C2CK/RST
Debug /
Programming
Hardware
128k Byte ISP Flash
Program Memory
UART
256 Byte SRAM
Timers
0, 1, 2, 3
8092 Byte XRAM
PCA/WDT
DMA
Analog
Power
VDD
VDC
VREG
Digital
Power
VBATDC
IND
DC/DC Buck
Converter
LCD Charge
Pump
XTAL1
XTAL2
GND
XTAL3
XTAL4
Low Power
20 MHz
Oscillator
External
Oscillator
Circuit
Enhanced
smaRTClock
Oscillator
EMIF
Pulse Counter
Analog Peripherals
Internal
External
VREF
VREF
A
M
U
X
12-bit
75ksps
ADC
Rev. 0.3 10/11
VDD
VREF
Temp
Sensor
P3-6
Drivers
32
P7
Driver
16
P3.0...P6.7
P7.0/C2D
GND
CP0, CP0A
System Clock
Configuration
Port 2
Drivers
Crossbar Control
LCD (up to 4x32)
SFR
Bus
Precision
24.5 MHz
Oscillator
GNDDC
CAP
SPI 1
(DMA Enabled)
AES
Engine
SYSCLK
P2.0/SCK1
P2.1/MISO1
P2.2/MOSI1
P2.3/NSS1
P2.4
P2.5
P2.6
P2.7
SPI 0
CRC
Engine
Encoder
Port 1
Drivers
P1.0/PC0
P1.1/PC1
P1.2/XTAL3
P1.3/XTAL4
P1.4
P1.5/INT5
P1.6/INT6
P1.7
Priority
Crossbar
Decoder
SMBus
VBAT
Port 0
Drivers
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7
Digital Peripherals
C2D
VBAT
Data Packet Processing Engine (DPPE) includes
hardware AES, DMA, CRC and encoding blocks for
acceleration of wireless protocols
High-Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
Memory
- Up to 128 kB Flash; In-system programmable; Full
read/write/erase functionality over supply range
- Up to 8 kB internal data RAM
Digital Peripherals
- 57 or 34 port I/O; All 5 V tolerant with high sink
current and programmable drive strength
- Hardware SMBus™ (I2C™ Compatible), 2 x SPI™,
and UART serial ports available concurrently
- Four general purpose 16-bit counter/timers
- Programmable 16-bit counter/timer array with six
capture/compare modules and watchdog timer
Clock Sources
- Precision Internal oscillator: 24.5 MHz, 2% accuracy
supports UART operation; spread-spectrum mode
for reduced EMI
- Low power internal oscillator: 20 MHz
- External oscillator: Crystal, RC, C, or CMOS Clock
- SmaRTClock oscillator: 32 kHz Crystal or 16.4 kHz
internal LFO
On-Chip Debug
- On-chip debug circuitry facilitates full-speed, nonintrusive in-system debug (no emulator required)
- Provides 4 breakpoints, single stepping
Packages
- 76-pin DQFN (6 x 6 mm)
- 40-pin QFN (6 x 6 mm)
- 80-pin TQFP (12 x 12 mm)
- Temperature Range: –40 to +85 °C
Port I/O Configuration
CIP-51 8051
Controller Core
Power On
Reset/PMU
-
CP1, CP1A
+
-
+
-
Comparators
Copyright © 2011 by Silicon Laboratories
C8051F96x
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
C8051F96x
2
Rev. 0.3
C8051F96x
Table of Contents
1. System Overview ..................................................................................................... 23
1.1. CIP-51™ Microcontroller Core .......................................................................... 29
1.1.1. Fully 8051 Compatible .............................................................................. 29
1.1.2. Improved Throughput................................................................................ 29
1.1.3. Additional Features ................................................................................... 29
1.2. Port Input/Output ............................................................................................... 30
1.3. Serial Ports ........................................................................................................ 31
1.4. Programmable Counter Array............................................................................ 31
1.5. SAR ADC with 16-bit Auto-Averaging Accumulator and
Autonomous Low Power Burst Mode................................................................ 32
1.6. Programmable Current Reference (IREF0)....................................................... 33
1.7. Comparators...................................................................................................... 33
2. Ordering Information ............................................................................................... 35
3. Pinout and Package Definitions ............................................................................. 36
3.1. DQFN-76 Package Specifications ..................................................................... 46
3.1.1. Package Drawing ...................................................................................... 46
3.1.2. Land Pattern.............................................................................................. 47
3.1.3. Soldering Guidelines ................................................................................. 48
3.2. QFN-40 Package Specifications........................................................................ 50
3.3. TQFP-80 Package Specifications...................................................................... 52
3.3.1. Soldering Guidelines ................................................................................. 55
4. Electrical Characteristics ........................................................................................ 56
4.1. Absolute Maximum Specifications..................................................................... 56
4.2. Electrical Characteristics ................................................................................... 57
5. SAR ADC with 16-bit Auto-Averaging Accumulator and
Autonomous Low Power Burst Mode ................................................................... 78
5.1. Output Code Formatting .................................................................................... 78
5.2. Modes of Operation ........................................................................................... 80
5.2.1. Starting a Conversion................................................................................ 80
5.2.2. Tracking Modes......................................................................................... 80
5.2.3. Burst Mode................................................................................................ 82
5.2.4. Settling Time Requirements...................................................................... 83
5.2.5. Gain Setting .............................................................................................. 83
5.3. 8-Bit Mode ......................................................................................................... 84
5.4. 12-Bit Mode ....................................................................................................... 84
5.5. Low Power Mode............................................................................................... 85
5.6. Programmable Window Detector....................................................................... 91
5.6.1. Window Detector In Single-Ended Mode .................................................. 93
5.6.2. ADC0 Specifications ................................................................................. 94
5.7. ADC0 Analog Multiplexer .................................................................................. 95
5.8. Temperature Sensor.......................................................................................... 97
5.8.1. Calibration ................................................................................................. 97
5.9. Voltage and Ground Reference Options ......................................................... 100
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3
C8051F96x
5.10. External Voltage Reference........................................................................... 101
5.11. Internal Voltage Reference............................................................................ 101
5.12. Analog Ground Reference............................................................................. 101
5.13. Temperature Sensor Enable ......................................................................... 101
5.14. Voltage Reference Electrical Specifications .................................................. 102
6. Programmable Current Reference (IREF0).......................................................... 103
6.1. PWM Enhanced Mode..................................................................................... 103
6.2. IREF0 Specifications ....................................................................................... 104
7. Comparators........................................................................................................... 105
7.1. Comparator Inputs........................................................................................... 105
7.2. Comparator Outputs ........................................................................................ 106
7.3. Comparator Response Time ........................................................................... 107
7.4. Comparator Hysterisis ..................................................................................... 107
7.5. Comparator Register Descriptions .................................................................. 108
7.6. Comparator0 and Comparator1 Analog Multiplexers ...................................... 112
8. CIP-51 Microcontroller........................................................................................... 115
8.1. Instruction Set.................................................................................................. 116
8.1.1. Instruction and CPU Timing .................................................................... 116
8.2. CIP-51 Register Descriptions .......................................................................... 121
9. Memory Organization ............................................................................................ 124
9.1. Program Memory............................................................................................. 124
9.1.1. MOVX Instruction and Program Memory ................................................ 127
9.2. Data Memory ................................................................................................... 127
9.2.1. Internal RAM ........................................................................................... 128
9.2.2. External RAM .......................................................................................... 128
10. External Data Memory Interface and On-Chip XRAM ....................................... 129
10.1. Accessing XRAM........................................................................................... 129
10.1.1. 16-Bit MOVX Example .......................................................................... 129
10.1.2. 8-Bit MOVX Example ............................................................................ 129
10.2. Configuring the External Memory Interface ................................................... 130
10.3. Port Configuration.......................................................................................... 130
10.4. Multiplexed and Non-multiplexed Selection................................................... 134
10.4.1. Multiplexed Configuration...................................................................... 134
10.4.2. Non-multiplexed Configuration.............................................................. 134
10.5. Memory Mode Selection................................................................................ 135
10.5.1. Internal XRAM Only .............................................................................. 136
10.5.2. Split Mode without Bank Select............................................................. 136
10.5.3. Split Mode with Bank Select.................................................................. 136
10.5.4. External Only......................................................................................... 136
10.6. Timing .......................................................................................................... 137
10.6.1. Non-Multiplexed Mode .......................................................................... 139
10.6.2. Multiplexed Mode .................................................................................. 142
11. Direct Memory Access (DMA0)........................................................................... 146
11.1. DMA0 Architecture ........................................................................................ 147
11.2. DMA0 Arbitration ........................................................................................... 148
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C8051F96x
11.2.1. DMA0 Memory Access Arbitration ........................................................ 148
11.2.2. DMA0 Channel Arbitration .................................................................... 148
11.3. DMA0 Operation in Low Power Modes ......................................................... 148
11.4. Transfer Configuration................................................................................... 149
12. Cyclic Redundancy Check Unit (CRC0)............................................................. 160
12.1. 16-bit CRC Algorithm..................................................................................... 160
12.3. Preparing for a CRC Calculation ................................................................... 163
12.4. Performing a CRC Calculation ...................................................................... 163
12.5. Accessing the CRC0 Result .......................................................................... 163
12.6. CRC0 Bit Reverse Feature............................................................................ 167
13. DMA-Enabled Cyclic Redundancy Check Module (CRC1)............................... 168
13.1. Polynomial Specification................................................................................ 168
13.2. Endianness.................................................................................................... 169
13.3. CRC Seed Value ........................................................................................... 170
13.4. Inverting the Final Value................................................................................ 170
13.5. Flipping the Final Value ................................................................................. 170
13.6. Using CRC1 with SFR Access ...................................................................... 171
13.7. Using the CRC1 module with the DMA ......................................................... 171
14. Advanced Encryption Standard (AES) Peripheral ............................................ 175
14.1. Hardware Description .................................................................................... 176
14.1.1. AES Encryption/Decryption Core .......................................................... 177
14.1.2. Data SFRs............................................................................................. 177
14.1.3. Configuration sfrs .................................................................................. 178
14.1.4. Input Multiplexer.................................................................................... 178
14.1.5. Output Multiplexer ................................................................................. 178
14.1.6. Internal State Machine .......................................................................... 178
14.2. Key Inversion................................................................................................. 179
14.2.1. Key Inversion using DMA...................................................................... 180
14.2.2. Key Inversion using SFRs..................................................................... 181
14.2.3. Extended Key Output Byte Order.......................................................... 182
14.2.4. Using the DMA to unwrap the extended Key ........................................ 183
14.3. AES Block Cipher .......................................................................................... 184
14.4. AES Block Cipher Data Flow......................................................................... 185
14.4.1. AES Block Cipher Encryption using DMA ............................................. 186
14.4.2. AES Block Cipher Encryption using SFRs ............................................ 187
14.5. AES Block Cipher Decryption........................................................................ 188
14.5.1. AES Block Cipher Decryption using DMA............................................. 188
14.5.2. AES Block Cipher Decryption using SFRs............................................ 189
14.6. Block Cipher Modes ...................................................................................... 190
14.6.1. Cipher Block Chaining Mode................................................................. 190
14.6.2. CBC Encryption Initialization Vector Location....................................... 192
14.6.3. CBC Encryption using DMA .................................................................. 192
14.6.4. CBC Decryption .................................................................................... 195
14.6.5. Counter Mode ....................................................................................... 198
14.6.6. CTR Encryption using DMA .................................................................. 200
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5
C8051F96x
15. Encoder/Decoder ................................................................................................. 207
15.1. Manchester Encoding.................................................................................... 208
15.2. Manchester Decoding.................................................................................... 209
15.3. Three-out-of-Six Encoding............................................................................ 210
15.4. Three-out-of-Six Decoding ............................................................................ 211
15.5. Encoding/Decoding with SFR Access ........................................................... 212
15.6. Decoder Error Interrupt.................................................................................. 212
15.7. Using the ENC0 module with the DMA.......................................................... 213
16. Special Function Registers................................................................................. 216
16.1. SFR Paging ................................................................................................... 216
16.2. Interrupts and SFR Paging ............................................................................ 216
16.3. SFR Page Stack Example ............................................................................. 218
17. Interrupt Handler.................................................................................................. 237
17.1. Enabling Interrupt Sources ............................................................................ 237
17.2. MCU Interrupt Sources and Vectors.............................................................. 237
17.3. Interrupt Priorities .......................................................................................... 238
17.4. Interrupt Latency............................................................................................ 238
17.5. Interrupt Register Descriptions ...................................................................... 240
17.6. External Interrupts INT0 and INT1................................................................. 247
18. Flash Memory....................................................................................................... 249
18.1. Programming the Flash Memory ................................................................... 249
18.1.1. Flash Lock and Key Functions .............................................................. 249
18.1.2. Flash Erase Procedure ......................................................................... 249
18.1.3. Flash Write Procedure .......................................................................... 250
18.1.4. Flash Write Optimization ....................................................................... 251
18.2. Non-volatile Data Storage ............................................................................. 252
18.3. Security Options ............................................................................................ 252
18.4. Determining the Device Part Number at Run Time ....................................... 254
18.5. Flash Write and Erase Guidelines ................................................................. 255
18.5.1. VDD Maintenance and the VDD Monitor .............................................. 255
18.5.2. PSWE Maintenance .............................................................................. 256
18.5.3. System Clock ........................................................................................ 256
18.6. Minimizing Flash Read Current ..................................................................... 257
19. Power Management ............................................................................................. 262
19.1. Normal Mode ................................................................................................. 263
19.2. Idle Mode....................................................................................................... 263
19.3. Stop Mode ..................................................................................................... 264
19.4. Low Power Idle Mode .................................................................................... 264
19.5. Suspend Mode .............................................................................................. 268
19.6. Sleep Mode ................................................................................................... 268
19.7. Configuring Wakeup Sources........................................................................ 269
19.8. Determining the Event that Caused the Last Wakeup................................... 269
19.9. Power Management Specifications ............................................................... 273
20. On-Chip DC-DC Buck Converter (DC0).............................................................. 274
20.1. Startup Behavior............................................................................................ 275
6
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C8051F96x
20.4. Optimizing Board Layout ............................................................................... 276
20.5. Selecting the Optimum Switch Size............................................................... 276
20.6. DC-DC Converter Clocking Options .......................................................... 276
20.7. Bypass Mode................................................................................................. 277
20.8. DC-DC Converter Register Descriptions ....................................................... 277
20.9. DC-DC Converter Specifications ................................................................... 281
21. Voltage Regulator (VREG0)................................................................................. 282
21.1. Voltage Regulator Electrical Specifications ................................................... 282
22. Reset Sources ...................................................................................................... 283
22.1. Power-On Reset ............................................................................................ 284
22.2. Power-Fail Reset ........................................................................................... 285
22.3. External Reset ............................................................................................... 288
22.4. Missing Clock Detector Reset ....................................................................... 288
22.5. Comparator0 Reset ....................................................................................... 288
22.6. PCA Watchdog Timer Reset ......................................................................... 288
22.7. Flash Error Reset .......................................................................................... 289
22.8. SmaRTClock (Real Time Clock) Reset ......................................................... 289
22.9. Software Reset .............................................................................................. 289
23. Clocking Sources................................................................................................. 291
23.1. Programmable Precision Internal Oscillator .................................................. 292
23.2. Low Power Internal Oscillator........................................................................ 292
23.3. External Oscillator Drive Circuit..................................................................... 292
23.3.1. External Crystal Mode........................................................................... 292
23.3.2. External RC Mode................................................................................. 294
23.3.3. External Capacitor Mode....................................................................... 295
23.3.4. External CMOS Clock Mode ................................................................. 295
23.4. Special Function Registers for Selecting and Configuring the
System Clock ................................................................................................ 296
24. SmaRTClock (Real Time Clock).......................................................................... 300
24.1. SmaRTClock Interface .................................................................................. 301
24.1.1. SmaRTClock Lock and Key Functions.................................................. 302
24.1.2. Using RTC0ADR and RTC0DAT to Access SmaRTClock
Internal Registers.................................................................................. 302
24.1.3. SmaRTClock Interface Autoread Feature ............................................. 302
24.1.4. RTC0ADR Autoincrement Feature........................................................ 302
24.2. SmaRTClock Clocking Sources .................................................................... 305
24.2.1. Using the SmaRTClock Oscillator with a Crystal or
External CMOS Clock ........................................................................... 305
24.2.2. Using the SmaRTClock Oscillator in Self-Oscillate Mode..................... 306
24.2.3. Using the Low Frequency Oscillator (LFO) ........................................... 306
24.2.4. Programmable Load Capacitance......................................................... 306
24.2.5. Automatic Gain Control (Crystal Mode Only) and SmaRTClock
Bias Doubling ........................................................................................ 307
24.2.6. Missing SmaRTClock Detector ............................................................. 309
24.2.7. SmaRTClock Oscillator Crystal Valid Detector ..................................... 309
Rev. 0.3
7
C8051F96x
24.3. SmaRTClock Timer and Alarm Function ....................................................... 309
24.3.1. Setting and Reading the SmaRTClock Timer Value ............................. 309
24.3.2. Setting a SmaRTClock Alarm ............................................................... 310
24.3.3. Software Considerations for using the SmaRTClock
Timer and Alarm ................................................................................... 310
25. Low-Power Pulse Counter .................................................................................. 317
25.1. Counting Modes ............................................................................................ 318
25.2. Reed Switch Types........................................................................................ 319
25.3. Programmable Pull-Up Resistors .................................................................. 320
25.4. Automatic Pull-Up Resistor Calibration ......................................................... 322
25.5. Sample Rate.................................................................................................. 322
25.6. Debounce ...................................................................................................... 322
25.7. Reset Behavior .............................................................................................. 323
25.8. Wake up and Interrupt Sources..................................................................... 323
25.9. Real-Time Register Access ........................................................................... 324
25.10. Advanced Features ..................................................................................... 324
25.10.1. Quadrature Error ................................................................................. 324
25.10.2. Flutter Detection.................................................................................. 325
26. LCD Segment Driver ............................................................................................ 339
26.1. Configuring the LCD Segment Driver ............................................................ 339
26.2. Mapping Data Registers to LCD Pins............................................................ 340
26.3. LCD Contrast Adjustment.............................................................................. 343
26.3.1. Contrast Control Mode 1 (Bypass Mode).............................................. 343
26.3.2. Contrast Control Mode 2 (Minimum Contrast Mode) ............................ 344
26.3.3. Contrast Control Mode 3 (Constant Contrast Mode)............................. 344
26.3.4. Contrast Control Mode 4 (Auto-Bypass Mode) ..................................... 345
26.4. Adjusting the VBAT Monitor Threshold ......................................................... 349
26.5. Setting the LCD Refresh Rate ....................................................................... 350
26.6. Blinking LCD Segments................................................................................. 351
26.7. Advanced LCD Optimizations........................................................................ 353
27. Port Input/Output ................................................................................................. 356
27.1. Port I/O Modes of Operation.......................................................................... 357
27.1.1. Port Pins Configured for Analog I/O...................................................... 357
27.1.2. Port Pins Configured For Digital I/O...................................................... 357
27.1.3. Interfacing Port I/O to High Voltage Logic............................................. 358
27.1.4. Increasing Port I/O Drive Strength ........................................................ 358
27.2. Assigning Port I/O Pins to Analog and Digital Functions............................... 358
27.2.1. Assigning Port I/O Pins to Analog Functions ........................................ 358
27.2.2. Assigning Port I/O Pins to Digital Functions.......................................... 359
27.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions ... 359
27.3. Priority Crossbar Decoder ............................................................................. 360
27.4. Port Match ..................................................................................................... 366
27.5. Special Function Registers for Accessing and Configuring Port I/O ............. 368
28. SMBus................................................................................................................... 386
28.1. Supporting Documents .................................................................................. 387
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C8051F96x
28.2. SMBus Configuration..................................................................................... 387
28.3. SMBus Operation .......................................................................................... 387
28.3.1. Transmitter Vs. Receiver....................................................................... 388
28.3.2. Arbitration.............................................................................................. 388
28.3.3. Clock Low Extension............................................................................. 388
28.3.4. SCL Low Timeout.................................................................................. 388
28.3.5. SCL High (SMBus Free) Timeout ......................................................... 389
28.4. Using the SMBus........................................................................................... 389
28.4.1. SMBus Configuration Register.............................................................. 389
28.4.2. SMB0CN Control Register .................................................................... 393
28.4.3. Hardware Slave Address Recognition .................................................. 395
28.4.4. Data Register ........................................................................................ 398
28.5. SMBus Transfer Modes................................................................................. 398
28.5.1. Write Sequence (Master) ...................................................................... 398
28.5.2. Read Sequence (Master) ...................................................................... 399
28.5.3. Write Sequence (Slave) ........................................................................ 400
28.5.4. Read Sequence (Slave) ........................................................................ 401
28.6. SMBus Status Decoding................................................................................ 402
29. UART0 ................................................................................................................... 407
29.1. Enhanced Baud Rate Generation.................................................................. 408
29.2. Operational Modes ........................................................................................ 409
29.2.1. 8-Bit UART ............................................................................................ 409
29.2.2. 9-Bit UART ............................................................................................ 409
29.3. Multiprocessor Communications ................................................................... 410
30. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 416
30.1. Signal Descriptions........................................................................................ 417
30.1.1. Master Out, Slave In (MOSI)................................................................. 417
30.1.2. Master In, Slave Out (MISO)................................................................. 417
30.1.3. Serial Clock (SCK) ................................................................................ 417
30.1.4. Slave Select (NSS) ............................................................................... 417
30.2. SPI0 Master Mode Operation ........................................................................ 417
30.3. SPI0 Slave Mode Operation .......................................................................... 419
30.4. SPI0 Interrupt Sources .................................................................................. 420
30.5. Serial Clock Phase and Polarity .................................................................... 420
30.6. SPI Special Function Registers ..................................................................... 422
32. Timers ................................................................................................................... 448
32.1. Timer 0 and Timer 1 ...................................................................................... 450
32.1.1. Mode 0: 13-bit Counter/Timer ............................................................... 450
32.1.2. Mode 1: 16-bit Counter/Timer ............................................................... 451
32.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload..................................... 451
32.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................ 452
32.2. Timer 2 .......................................................................................................... 458
32.2.1. 16-bit Timer with Auto-Reload............................................................... 458
32.2.2. 8-bit Timers with Auto-Reload............................................................... 459
32.2.3. Comparator 0/SmaRTClock Capture Mode .......................................... 459
Rev. 0.3
9
C8051F96x
32.3. Timer 3 .......................................................................................................... 464
32.3.1. 16-bit Timer with Auto-Reload............................................................... 464
32.3.2. 8-Bit Timers with Auto-Reload .............................................................. 465
32.3.3. SmaRTClock/External Oscillator Capture Mode ................................... 465
33. Programmable Counter Array............................................................................. 470
33.1. PCA Counter/Timer ....................................................................................... 471
33.2. PCA0 Interrupt Sources................................................................................. 472
33.3. Capture/Compare Modules ........................................................................... 473
33.3.1. Edge-triggered Capture Mode............................................................... 474
33.3.2. Software Timer (Compare) Mode.......................................................... 475
33.3.3. High-Speed Output Mode ..................................................................... 476
33.3.4. Frequency Output Mode ....................................................................... 477
33.3.5. 8-Bit, 9-Bit, 10-Bit and 11-Bit Pulse Width Modulator Modes.............. 478
33.3.6. 16-Bit Pulse Width Modulator Mode..................................................... 480
33.4. Watchdog Timer Mode .................................................................................. 481
33.4.1. Watchdog Timer Operation ................................................................... 481
33.4.2. Watchdog Timer Usage ........................................................................ 482
33.5. Register Descriptions for PCA0..................................................................... 484
34. C2 Interface .......................................................................................................... 490
34.1. C2 Interface Registers................................................................................... 490
34.2. C2 Pin Sharing .............................................................................................. 493
Document Change List ............................................................................................. 494
Contact Information .................................................................................................. 496
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C8051F96x
List of Figures
Figure 1.1. C8051F960 Block Diagram ................................................................... 24
Figure 1.2. C8051F961 Block Diagram ................................................................... 24
Figure 1.3. C8051F962 Block Diagram ................................................................... 25
Figure 1.4. C8051F963 Block Diagram ................................................................... 25
Figure 1.5. C8051F964 Block Diagram ................................................................... 26
Figure 1.6. C8051F965 Block Diagram ................................................................... 26
Figure 1.7. C8051F966 Block Diagram ................................................................... 27
Figure 1.8. C8051F967 Block Diagram ................................................................... 27
Figure 1.9. C8051F968 Block Diagram ................................................................... 28
Figure 1.10. C8051F969 Block Diagram ................................................................. 28
Figure 1.11. Port I/O Functional Block Diagram ...................................................... 30
Figure 1.12. PCA Block Diagram ............................................................................. 31
Figure 1.13. ADC0 Functional Block Diagram ......................................................... 32
Figure 1.14. ADC0 Multiplexer Block Diagram ........................................................ 33
Figure 1.15. Comparator 0 Functional Block Diagram ............................................ 34
Figure 1.16. Comparator 1 Functional Block Diagram ............................................ 34
Figure 3.1. DQFN-76 Pinout Diagram (Top View) ................................................... 43
Figure 3.2. QFN-40 Pinout Diagram (Top View) ..................................................... 44
Figure 3.3. TQFP-80 Pinout Diagram (Top View) ................................................... 45
Figure 3.4. DQFN-76 Package Drawing .................................................................. 46
Figure 3.5. DQFN-76 Land Pattern ......................................................................... 47
Figure 3.6. Recomended Inner Via Placement ........................................................ 49
Figure 3.7. Typical QFN-40 Package Drawing ........................................................ 50
Figure 3.8. QFN-40 Landing Diagram ..................................................................... 51
Figure 3.9. TQFP-80 Package Drawing .................................................................. 52
Figure 3.10. TQFP80 Landing Diagram .................................................................. 54
Figure 4.1. Frequency Sensitivity (External CMOS Clock, 25°C) ............................ 64
Figure 4.2. Typical VOH Curves, 1.8–3.6 V ............................................................ 66
Figure 4.3. Typical VOL Curves, 1.8–3.6 V ............................................................. 67
Figure 5.1. ADC0 Functional Block Diagram ........................................................... 78
Figure 5.2. 10-Bit ADC Track and Conversion Example Timing
(BURSTEN = 0) ..................................................................................... 81
Figure 5.3. Burst Mode Tracking Example with Repeat Count Set to 4 .................. 82
Figure 5.4. ADC0 Equivalent Input Circuits ............................................................. 83
Figure 5.5. ADC Window Compare Example: Right-Justified
Single-Ended Data ................................................................................ 94
Figure 5.6. ADC Window Compare Example: Left-Justified
Single-Ended Data ................................................................................ 94
Figure 5.7. ADC0 Multiplexer Block Diagram .......................................................... 95
Figure 5.8. Temperature Sensor Transfer Function ................................................ 97
Figure 5.9. Temperature Sensor Error with 1-Point Calibration
(VREF = 1.68 V) ..................................................................................... 98
Figure 5.10. Voltage Reference Functional Block Diagram ................................... 100
Rev. 0.3
11
C8051F96x
Figure 7.1. Comparator 0 Functional Block Diagram ............................................ 105
Figure 7.2. Comparator 1 Functional Block Diagram ............................................ 106
Figure 7.3. Comparator Hysteresis Plot ................................................................ 107
Figure 7.4. CPn Multiplexer Block Diagram ........................................................... 112
Figure 8.1. CIP-51 Block Diagram ......................................................................... 115
Figure 9.1. C8051F96x Memory Map .................................................................... 124
Figure 9.2. Flash Program Memory Map ............................................................... 125
Figure 9.3. Address Memory Map for Instruction Fetches ..................................... 126
Figure 10.1. Multiplexed Configuration Example ................................................... 134
Figure 10.2. Non-multiplexed Configuration Example ........................................... 135
Figure 10.3. EMIF Operating Modes ..................................................................... 135
Figure 10.4. Non-multiplexed 16-bit MOVX Timing ............................................... 139
Figure 10.5. Non-multiplexed 8-bit MOVX without Bank Select Timing ................ 140
Figure 10.6. Non-multiplexed 8-bit MOVX with Bank Select Timing ..................... 141
Figure 10.7. Multiplexed 16-bit MOVX Timing ....................................................... 142
Figure 10.8. Multiplexed 8-bit MOVX without Bank Select Timing ........................ 143
Figure 10.9. Multiplexed 8-bit MOVX with Bank Select Timing ............................. 144
Figure 11.1. DMA0 Block Diagram ........................................................................ 147
Figure 12.1. CRC0 Block Diagram ........................................................................ 160
Figure 12.2. Bit Reverse Register ......................................................................... 167
Figure 13.1. Polynomial Representation ............................................................... 168
Figure 14.1. AES Peripheral Block Diagram ......................................................... 176
Figure 14.2. Key Inversion Data Flow ................................................................... 179
Figure 14.3. AES Block Cipher Data Flow ............................................................. 185
Figure 14.4. Cipher Block Chaining Mode ............................................................. 190
Figure 14.5. CBC Encryption Data Flow ................................................................ 191
Figure 14.6. CBC Decryption Data Flow ............................................................... 195
Figure 14.7. Counter Mode .................................................................................... 198
Figure 14.8. Counter Mode Data Flow .................................................................. 199
Figure 16.1. SFR Page Stack ................................................................................ 217
Figure 16.2. SFR Page Stack While Using SFR Page 0x0 To
Access SMB0ADR ............................................................................ 218
Figure 16.3. SFR Page Stack After SPI0 Interrupt Occurs .................................... 219
Figure 16.4. SFR Page Stack Upon PCA Interrupt Occurring
During a SPI0 ISR ............................................................................. 220
Figure 16.5. SFR Page Stack Upon Return From PCA Interrupt .......................... 221
Figure 16.6. SFR Page Stack Upon Return From SPI0 Interrupt .......................... 222
Figure 18.1. Flash Security Example ..................................................................... 252
Figure 19.1. C8051F96x Power Distribution .......................................................... 263
Figure 19.2. Clock Tree Distribution ...................................................................... 264
Figure 20.1. Step Down DC-DC Buck Converter Block Diagram .......................... 274
Figure 22.1. Reset Sources ................................................................................... 283
Figure 22.2. Power-On Reset Timing Diagram ..................................................... 284
Figure 23.1. Clocking Sources Block Diagram ...................................................... 291
Figure 23.2. 25 MHz External Crystal Example ..................................................... 293
12
Rev. 0.3
C8051F96x
Figure 24.1. SmaRTClock Block Diagram ............................................................. 300
Figure 24.2. Interpreting Oscillation Robustness (Duty Cycle) Test Results ......... 308
Figure 25.1. Pulse Counter Block Diagram ........................................................... 317
Figure 25.2. Mode Examples ................................................................................. 318
Figure 25.3. Reed Switch Configurations .............................................................. 319
Figure 25.4. Debounce Timing .............................................................................. 323
Figure 25.5. Flutter Example ................................................................................. 325
Figure 26.1. LCD Segment Driver Block Diagram ................................................. 339
Figure 26.2. LCD Data Register to LCD Pin Mapping ........................................... 341
Figure 26.3. Contrast Control Mode 1 ................................................................... 343
Figure 26.4. Contrast Control Mode 2 ................................................................... 344
Figure 26.5. Contrast Control Mode 3 ................................................................... 344
Figure 26.6. Contrast Control Mode 4 ................................................................... 345
Figure 27.1. Port I/O Functional Block Diagram .................................................... 356
Figure 27.2. Port I/O Cell Block Diagram .............................................................. 357
Figure 27.3. Crossbar Priority Decoder with No Pins Skipped .............................. 361
Figure 27.4. Crossbar Priority Decoder with Crystal Pins Skipped ....................... 362
Figure 28.1. SMBus Block Diagram ...................................................................... 386
Figure 28.2. Typical SMBus Configuration ............................................................ 387
Figure 28.3. SMBus Transaction ........................................................................... 388
Figure 28.4. Typical SMBus SCL Generation ........................................................ 390
Figure 28.5. Typical Master Write Sequence ........................................................ 399
Figure 28.6. Typical Master Read Sequence ........................................................ 400
Figure 28.7. Typical Slave Write Sequence .......................................................... 401
Figure 28.8. Typical Slave Read Sequence .......................................................... 402
Figure 29.1. UART0 Block Diagram ...................................................................... 407
Figure 29.2. UART0 Baud Rate Logic ................................................................... 408
Figure 29.3. UART Interconnect Diagram ............................................................. 409
Figure 29.4. 8-Bit UART Timing Diagram .............................................................. 409
Figure 29.5. 9-Bit UART Timing Diagram .............................................................. 410
Figure 29.6. UART Multi-Processor Mode Interconnect Diagram ......................... 411
Figure 30.1. SPI Block Diagram ............................................................................ 416
Figure 30.2. Multiple-Master Mode Connection Diagram ...................................... 419
Figure 30.3. 3-Wire Single Master and 3-Wire Single Slave Mode
Connection Diagram ......................................................................... 419
Figure 30.4. 4-Wire Single Master Mode and 4-Wire Slave Mode
Connection Diagram ......................................................................... 419
Figure 30.5. Master Mode Data/Clock Timing ....................................................... 421
Figure 30.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 421
Figure 30.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 422
Figure 30.8. SPI Master Timing (CKPHA = 0) ....................................................... 426
Figure 30.9. SPI Master Timing (CKPHA = 1) ....................................................... 426
Figure 30.10. SPI Slave Timing (CKPHA = 0) ....................................................... 427
Figure 30.11. SPI Slave Timing (CKPHA = 1) ....................................................... 427
Figure 32.1. T0 Mode 0 Block Diagram ................................................................. 451
Rev. 0.3
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C8051F96x
Figure 32.2. T0 Mode 2 Block Diagram ................................................................. 452
Figure 32.3. T0 Mode 3 Block Diagram ................................................................. 453
Figure 32.4. Timer 2 16-Bit Mode Block Diagram ................................................. 458
Figure 32.5. Timer 2 8-Bit Mode Block Diagram ................................................... 459
Figure 32.6. Timer 2 Capture Mode Block Diagram .............................................. 460
Figure 32.7. Timer 3 16-Bit Mode Block Diagram ................................................. 464
Figure 32.8. Timer 3 8-Bit Mode Block Diagram ................................................... 465
Figure 32.9. Timer 3 Capture Mode Block Diagram .............................................. 466
Figure 33.1. PCA Block Diagram ........................................................................... 470
Figure 33.2. PCA Counter/Timer Block Diagram ................................................... 472
Figure 33.3. PCA Interrupt Block Diagram ............................................................ 473
Figure 33.4. PCA Capture Mode Diagram ............................................................. 475
Figure 33.5. PCA Software Timer Mode Diagram ................................................. 476
Figure 33.6. PCA High-Speed Output Mode Diagram ........................................... 477
Figure 33.7. PCA Frequency Output Mode ........................................................... 478
Figure 33.8. PCA 8-Bit PWM Mode Diagram ........................................................ 479
Figure 33.9. PCA 9, 10 and 11-Bit PWM Mode Diagram ...................................... 480
Figure 33.10. PCA 16-Bit PWM Mode ................................................................... 481
Figure 33.11. PCA Module 5 with Watchdog Timer Enabled ................................ 482
Figure 34.1. Typical C2 Pin Sharing ...................................................................... 493
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C8051F96x
List of Tables
Table 2.1. Product Selection Guide ......................................................................... 35
Table 3.1. Pin Definitions for the C8051F96x .......................................................... 36
Table 3.2. DQFN-76 Package Dimensions ............................................................. 46
Table 3.3. DQFN-76 Land Pattern Dimensions ....................................................... 47
Table 3.4. Recomended Inner Via Placement Dimensions ..................................... 49
Table 3.5. QFN-40 Package Dimensions ................................................................ 50
Table 3.6. QFN-40 Landing Diagram Dimensions ................................................... 51
Table 3.7. TQFP-80 Package Dimensions .............................................................. 52
Table 3.8. TQFP80 Landing Diagram Dimensions .................................................. 54
Table 4.1. Absolute Maximum Ratings .................................................................... 56
Table 4.2. Global Electrical Characteristics ............................................................. 57
Table 4.3. Digital Supply Current at VBAT pin with DC-DC Converter Enabled ..... 57
Table 4.4. Digital Supply Current with DC-DC Converter Disabled ......................... 58
Table 4.5. Port I/O DC Electrical Characteristics ..................................................... 65
Table 4.6. Reset Electrical Characteristics .............................................................. 68
Table 4.7. Power Management Electrical Specifications ......................................... 69
Table 4.8. Flash Electrical Characteristics .............................................................. 69
Table 4.9. Internal Precision Oscillator Electrical Characteristics ........................... 69
Table 4.10. Internal Low-Power Oscillator Electrical Characteristics ...................... 69
Table 4.11. SmaRTClock Characteristics ................................................................ 70
Table 4.12. ADC0 Electrical Characteristics ............................................................ 70
Table 4.13. Temperature Sensor Electrical Characteristics .................................... 71
Table 4.14. Voltage Reference Electrical Characteristics ....................................... 72
Table 4.15. IREF0 Electrical Characteristics ........................................................... 73
Table 4.16. Comparator Electrical Characteristics .................................................. 74
Table 4.17. VREG0 Electrical Characteristics ......................................................... 75
Table 4.18. LCD0 Electrical Characteristics ............................................................ 76
Table 4.19. PC0 Electrical Characteristics .............................................................. 76
Table 4.20. DC0 (Buck Converter) Electrical Characteristics .................................. 77
Table 5.1. Representative Conversion Times and Energy Consumption
for the SAR ADC with 1.65 V High-Speed VREF ................................... 85
Table 8.1. CIP-51 Instruction Set Summary .......................................................... 117
Table 10.1. EMIF Pinout (C8051F960/3/6) ............................................................ 131
Table 10.2. AC Parameters for External Memory Interface ................................... 145
Table 12.1. Example 16-bit CRC Outputs ............................................................. 161
Table 12.2. Example 32-bit CRC Outputs ............................................................. 163
Table 14.1. Extended Key Output Byte Order ....................................................... 182
Table 14.2. 192-Bit Key DMA Usage ..................................................................... 183
Table 14.3. 256-bit Key DMA Usage ..................................................................... 183
Table 15.1. Encoder Input and Output Data Sizes ................................................ 207
Table 15.2. Manchester Encoding ......................................................................... 208
Table 15.3. Manchester Decoding ......................................................................... 209
Table 15.4. Three-out-of-Six Encoding Nibble ...................................................... 210
Rev. 0.3
15
C8051F96x
Table 15.5. Three-out-of-Six Decoding ................................................................. 211
Table 16.1. SFR Map (0xC0–0xFF) ...................................................................... 227
Table 16.2. SFR Map (0x80–0xBF) ....................................................................... 228
Table 16.3. Special Function Registers ................................................................. 229
Table 17.1. Interrupt Summary .............................................................................. 239
Table 18.1. Flash Security Summary .................................................................... 253
Table 19.1. Power Modes ...................................................................................... 262
Table 20.1. IPeak Inductor Current Limit Settings ................................................. 275
Table 23.1. Recommended XFCN Settings for Crystal Mode ............................... 293
Table 23.2. Recommended XFCN Settings for RC and C modes ......................... 294
Table 24.1. SmaRTClock Internal Registers ......................................................... 301
Table 24.2. SmaRTClock Load Capacitance Settings .......................................... 307
Table 24.3. SmaRTClock Bias Settings ................................................................ 308
Table 25.1. Pull-Up Resistor Current ..................................................................... 320
Table 25.2. Sample Rate Duty-Cycle Multiplier ..................................................... 320
Table 25.3. Pull-Up Duty-Cycle Multiplier .............................................................. 320
Table 25.4. Average Pull-Up Current (Sample Rate = 250 µs) ............................. 321
Table 25.5. Average Pull-Up Current (Sample Rate = 500 µs) ............................. 321
Table 25.6. Average Pull-Up Current (Sample Rate = 1 ms) ............................... 321
Table 25.7. Average Pull-Up Current (Sample Rate = 2 ms) ................................ 321
Table 26.1. Bit Configurations to select Contrast Control Modes .......................... 343
Table 27.1. Port I/O Assignment for Analog Functions ......................................... 358
Table 27.2. Port I/O Assignment for Digital Functions ........................................... 359
Table 27.3. Port I/O Assignment for External Digital Event Capture Functions .... 359
Table 28.1. SMBus Clock Source Selection .......................................................... 390
Table 28.2. Minimum SDA Setup and Hold Times ................................................ 391
Table 28.3. Sources for Hardware Changes to SMB0CN ..................................... 395
Table 28.4. Hardware Address Recognition Examples (EHACK = 1) ................... 396
Table 28.5. SMBus Status Decoding With Hardware ACK Generation
Disabled (EHACK = 0) ........................................................................ 403
Table 28.6. SMBus Status Decoding With Hardware ACK Generation
Enabled (EHACK = 1) ......................................................................... 405
Table 29.1. Timer Settings for Standard Baud Rates
Using The Internal 24.5 MHz Oscillator .............................................. 414
Table 29.2. Timer Settings for Standard Baud Rates
Using an External 22.1184 MHz Oscillator ......................................... 414
Table 30.1. SPI Slave Timing Parameters ............................................................ 428
Table 31.1. SPI Slave Timing Parameters ............................................................ 447
Table 32.1. Timer 0 Running Modes ..................................................................... 450
Table 33.1. PCA Timebase Input Options ............................................................. 471
Table 33.2. PCA0CPM and PCA0PWM Bit Settings for PCA
Capture/Compare Modules ................................................................ 473
Table 33.3. Watchdog Timer Timeout Intervals1 ................................................... 483
16
Rev. 0.3
C8051F96x
List of Registers
SFR Definition 5.1. ADC0CN: ADC0 Control ................................................................ 86
SFR Definition 5.2. ADC0CF: ADC0 Configuration ...................................................... 87
SFR Definition 5.3. ADC0AC: ADC0 Accumulator Configuration ................................. 88
SFR Definition 5.4. ADC0PWR: ADC0 Burst Mode Power-Up Time ............................ 89
SFR Definition 5.5. ADC0TK: ADC0 Burst Mode Track Time ....................................... 90
SFR Definition 5.6. ADC0H: ADC0 Data Word High Byte ............................................ 91
SFR Definition 5.7. ADC0L: ADC0 Data Word Low Byte .............................................. 91
SFR Definition 5.8. ADC0GTH: ADC0 Greater-Than High Byte ................................... 92
SFR Definition 5.9. ADC0GTL: ADC0 Greater-Than Low Byte .................................... 92
SFR Definition 5.10. ADC0LTH: ADC0 Less-Than High Byte ...................................... 93
SFR Definition 5.11. ADC0LTL: ADC0 Less-Than Low Byte ........................................ 93
SFR Definition 5.12. ADC0MX: ADC0 Input Channel Select ........................................ 96
SFR Definition 5.13. TOFFH: Temperature Sensor Offset High Byte ........................... 99
SFR Definition 5.14. TOFFL: Temperature Sensor Offset Low Byte ............................ 99
SFR Definition 5.15. REF0CN: Voltage Reference Control ........................................ 102
SFR Definition 6.1. IREF0CN: Current Reference Control ......................................... 103
SFR Definition 6.2. IREF0CF: Current Reference Configuration ................................ 104
SFR Definition 7.1. CPT0CN: Comparator 0 Control .................................................. 108
SFR Definition 7.2. CPT0MD: Comparator 0 Mode Selection .................................... 109
SFR Definition 7.3. CPT1CN: Comparator 1 Control .................................................. 110
SFR Definition 7.4. CPT1MD: Comparator 1 Mode Selection .................................... 111
SFR Definition 7.5. CPT0MX: Comparator0 Input Channel Select ............................. 113
SFR Definition 7.6. CPT1MX: Comparator1 Input Channel Select ............................. 114
SFR Definition 8.1. DPL: Data Pointer Low Byte ........................................................ 121
SFR Definition 8.2. DPH: Data Pointer High Byte ....................................................... 121
SFR Definition 8.3. SP: Stack Pointer ......................................................................... 122
SFR Definition 8.4. ACC: Accumulator ....................................................................... 122
SFR Definition 8.5. B: B Register ................................................................................ 122
SFR Definition 8.6. PSW: Program Status Word ........................................................ 123
SFR Definition 9.1. PSBANK: Program Space Bank Select ....................................... 127
SFR Definition 10.1. EMI0CN: External Memory Interface Control ............................ 132
SFR Definition 10.2. EMI0CF: External Memory Configuration .................................. 133
SFR Definition 10.3. EMI0TC: External Memory Timing Control ................................ 138
SFR Definition 11.1. DMA0EN: DMA0 Channel Enable ............................................. 150
SFR Definition 11.2. DMA0INT: DMA0 Full-Length Interrupt ...................................... 151
SFR Definition 11.3. DMA0MINT: DMA0 Mid-Point Interrupt ..................................... 152
SFR Definition 11.4. DMA0BUSY: DMA0 Busy .......................................................... 153
SFR Definition 11.5. DMA0SEL: DMA0 Channel Select for Configuration ................. 154
SFR Definition 11.6. DMA0NMD: DMA Channel Mode .............................................. 155
SFR Definition 11.7. DMA0NCF: DMA Channel Configuration ................................... 156
SFR Definition 11.8. DMA0NBAH: Memory Base Address High Byte ........................ 157
SFR Definition 11.9. DMA0NBAL: Memory Base Address Low Byte ......................... 157
SFR Definition 11.10. DMA0NAOH: Memory Address Offset High Byte .................... 158
Rev. 0.3
17
C8051F96x
SFR Definition 11.11. DMA0NAOL: Memory Address Offset Low Byte ..................... 158
SFR Definition 11.12. DMA0NSZH: Transfer Size High Byte ..................................... 159
SFR Definition 11.13. DMA0NSZL: Memory Transfer Size Low Byte ........................ 159
SFR Definition 12.1. CRC0CN: CRC0 Control ........................................................... 164
SFR Definition 12.2. CRC0IN: CRC0 Data Input ........................................................ 165
SFR Definition 12.3. CRC0DAT: CRC0 Data Output .................................................. 165
SFR Definition 12.4. CRC0AUTO: CRC0 Automatic Control ...................................... 166
SFR Definition 12.5. CRC0CNT: CRC0 Automatic Flash Sector Count ..................... 166
SFR Definition 12.6. CRC0FLIP: CRC0 Bit Flip .......................................................... 167
SFR Definition 13.1. CRC1CN: CRC1 Control ........................................................... 172
SFR Definition 13.2. CRC1IN: CRC1 Data IN ............................................................ 173
SFR Definition 13.3. CRC1POLL: CRC1 Polynomial LSB .......................................... 173
SFR Definition 13.4. CRC1POLH: CRC1 Polynomial MSB ........................................ 173
SFR Definition 13.5. CRC1OUTL: CRC1 Output LSB ................................................ 174
SFR Definition 13.6. CRC1OUTH: CRC1 Output MSB .............................................. 174
SFR Definition 14.1. AES0BCFG: AES Block Configuration ...................................... 202
SFR Definition 14.2. AES0DCFG: AES Data Configuration ....................................... 203
SFR Definition 14.3. AES0BIN: AES Block Input ........................................................ 204
SFR Definition 14.4. AES0XIN: AES XOR Input ......................................................... 205
SFR Definition 14.5. AES0KIN: AES Key Input .......................................................... 205
SFR Definition 14.6. AES0YOUT: AES Y Output ....................................................... 206
SFR Definition 15.1. ENC0CN: Encoder Decoder 0 Control ...................................... 214
SFR Definition 15.2. ENC0L: ENC0 Data Low Byte ................................................... 215
SFR Definition 15.3. ENC0M: ENC0 Data Middle Byte .............................................. 215
SFR Definition 15.4. ENC0H: ENC0 Data High Byte .................................................. 215
SFR Definition 16.1. SFRPGCN: SFR Page Control .................................................. 223
SFR Definition 16.2. SFRPAGE: SFR Page ............................................................... 224
SFR Definition 16.3. SFRNEXT: SFR Next ................................................................ 225
SFR Definition 16.4. SFRLAST: SFR Last .................................................................. 226
SFR Definition 17.1. IE: Interrupt Enable .................................................................... 241
SFR Definition 17.2. IP: Interrupt Priority .................................................................... 242
SFR Definition 17.3. EIE1: Extended Interrupt Enable 1 ............................................ 243
SFR Definition 17.4. EIP1: Extended Interrupt Priority 1 ............................................ 244
SFR Definition 17.5. EIE2: Extended Interrupt Enable 2 ............................................ 245
SFR Definition 17.6. EIP2: Extended Interrupt Priority 2 ............................................ 246
SFR Definition 17.7. IT01CF: INT0/INT1 Configuration .............................................. 248
SFR Definition 18.1. DEVICEID: Device Identification ................................................ 254
SFR Definition 18.2. REVID: Revision Identification ................................................... 254
SFR Definition 18.3. PSCTL: Program Store R/W Control ......................................... 258
SFR Definition 18.4. FLKEY: Flash Lock and Key ...................................................... 259
SFR Definition 18.5. FLSCL: Flash Scale ................................................................... 260
SFR Definition 18.6. FLWR: Flash Write Only ............................................................ 260
SFR Definition 18.7. FRBCN: Flash Read Buffer Control ........................................... 261
SFR Definition 19.1. PCLKACT: Peripheral Active Clock Enable ............................... 265
SFR Definition 19.2. PCLKEN: Peripheral Clock Enable ............................................ 266
18
Rev. 0.3
C8051F96x
SFR Definition 19.3. CLKMODE: Clock Mode ............................................................ 267
SFR Definition 19.4. PMU0CF: Power Management Unit Configuration ..................... 270
SFR Definition 19.5. PMU0FL: Power Management Unit Flag ................................... 271
SFR Definition 19.6. PMU0MD: Power Management Unit Mode ................................ 272
SFR Definition 19.7. PCON: Power Management Control Register ........................... 273
SFR Definition 20.1. DC0CN: DC-DC Converter Control ........................................... 278
SFR Definition 20.2. DC0CF: DC-DC Converter Configuration .................................. 279
SFR Definition 20.3. DC0MD: DC-DC Converter Mode .............................................. 280
SFR Definition 20.4. DC0RDY: DC-DC Converter Ready Indicator ........................... 281
SFR Definition 21.1. REG0CN: Voltage Regulator Control ........................................ 282
SFR Definition 22.1. VDM0CN: VDD Supply Monitor Control .................................... 287
SFR Definition 22.2. RSTSRC: Reset Source ............................................................ 290
SFR Definition 23.1. CLKSEL: Clock Select ............................................................... 296
SFR Definition 23.2. OSCICN: Internal Oscillator Control .......................................... 297
SFR Definition 23.3. OSCICL: Internal Oscillator Calibration ..................................... 298
SFR Definition 23.4. OSCXCN: External Oscillator Control ........................................ 299
SFR Definition 24.1. RTC0KEY: SmaRTClock Lock and Key .................................... 303
SFR Definition 24.2. RTC0ADR: SmaRTClock Address ............................................ 303
SFR Definition 24.3. RTC0DAT: SmaRTClock Data .................................................. 304
Internal Register Definition 24.4. RTC0CN: SmaRTClock Control ............................. 311
Internal Register Definition 24.5. RTC0XCN: SmaRTClock
Oscillator Control ............................................................................. 312
Internal Register Definition 24.6. RTC0XCF: SmaRTClock
Oscillator Configuration ................................................................... 313
Internal Register Definition 24.7. RTC0CF: SmaRTClock Configuration .................... 314
Internal Register Definition 24.8. CAPTUREn: SmaRTClock Timer Capture ............. 315
Internal Register Definition 24.9. ALARM0Bn: SmaRTClock Alarm 0
Match Value ..................................................................................... 315
Internal Register Definition 24.10. ALARM1Bn: SmaRTClock Alarm 1
Match Value ..................................................................................... 316
Internal Register Definition 24.11. ALARM2Bn: SmaRTClock Alarm 2
Match Value ..................................................................................... 316
SFR Definition 25.1. PC0MD: PC0 Mode Configuration ............................................. 326
SFR Definition 25.2. PC0PCF: PC0 Mode Pull-Up Configuration .............................. 327
SFR Definition 25.3. PC0TH: PC0 Threshold Configuration ....................................... 328
SFR Definition 25.4. PC0STAT: PC0 Status .............................................................. 329
SFR Definition 25.5. PC0DCH: PC0 Debounce Configuration High ........................... 330
SFR Definition 25.6. PC0DCL: PC0 Debounce Configuration Low ............................ 331
SFR Definition 25.7. PC0CTR0H: PC0 Counter 0 High (MSB) .................................. 332
SFR Definition 25.8. PC0CTR0M: PC0 Counter 0 Middle .......................................... 332
SFR Definition 25.9. PC0CTR0L: PC0 Counter 0 Low (LSB) ..................................... 332
SFR Definition 25.10. PC0CTR1H: PC0 Counter 1 High (MSB) ................................ 333
SFR Definition 25.11. PC0CTR1M: PC0 Counter 1 Middle ........................................ 333
SFR Definition 25.12. PC0CTR1L: PC0 Counter 1 Low (LSB) ................................... 333
SFR Definition 25.13. PC0CMP0H: PC0 Comparator 0 High (MSB) .......................... 334
Rev. 0.3
19
C8051F96x
SFR Definition 25.14. PC0CMP0M: PC0 Comparator 0 Middle ................................. 334
SFR Definition 25.15. PC0CMP0L: PC0 Comparator 0 Low (LSB) ............................ 334
SFR Definition 25.16. PC0CMP1H: PC0 Comparator 1 High (MSB) .......................... 335
SFR Definition 25.17. PC0CMP1M: PC0 Comparator 1 Middle ................................. 335
SFR Definition 25.18. PC0CMP1L: PC0 Comparator 1 Low (LSB) ............................ 335
SFR Definition 25.19. PC0HIST: PC0 History ............................................................ 336
SFR Definition 25.20. PC0INT0: PC0 Interrupt 0 ........................................................ 337
SFR Definition 25.21. PC0INT1: PC0 Interrupt 1 ........................................................ 338
SFR Definition 26.1. LCD0Dn: LCD0 Data ................................................................. 340
SFR Definition 26.2. LCD0CN: LCD0 Control Register .............................................. 342
SFR Definition 26.3. LCD0CNTRST: LCD0 Contrast Adjustment .............................. 346
SFR Definition 26.4. LCD0MSCN: LCD0 Master Control ........................................... 347
SFR Definition 26.5. LCD0MSCF: LCD0 Master Configuration .................................. 348
SFR Definition 26.6. LCD0PWR: LCD0 Power ........................................................... 348
SFR Definition 26.7. LCD0VBMCN: LCD0 VBAT Monitor Control ............................. 349
SFR Definition 26.8. LCD0CLKDIVH: LCD0 Refresh Rate Prescaler High Byte ........ 350
SFR Definition 26.9. LCD0CLKDIVL: LCD Refresh Rate Prescaler Low Byte ........... 350
SFR Definition 26.10. LCD0BLINK: LCD0 Blink Mask ................................................ 351
SFR Definition 26.11. LCD0TOGR: LCD0 Toggle Rate ............................................. 352
SFR Definition 26.12. LCD0CF: LCD0 Configuration ................................................. 353
SFR Definition 26.13. LCD0CHPCN: LCD0 Charge Pump Control ............................ 353
SFR Definition 26.14. LCD0CHPCF: LCD0 Charge Pump Configuration .................. 354
SFR Definition 26.15. LCD0CHPMD: LCD0 Charge Pump Mode .............................. 354
SFR Definition 26.16. LCD0BUFCN: LCD0 Buffer Control ......................................... 354
SFR Definition 26.17. LCD0BUFCF: LCD0 Buffer Configuration ............................... 355
SFR Definition 26.18. LCD0BUFMD: LCD0 Buffer Mode ........................................... 355
SFR Definition 26.19. LCD0VBMCF: LCD0 VBAT Monitor Configuration .................. 355
SFR Definition 27.1. XBR0: Port I/O Crossbar Register 0 .......................................... 363
SFR Definition 27.2. XBR1: Port I/O Crossbar Register 1 .......................................... 364
SFR Definition 27.3. XBR2: Port I/O Crossbar Register 2 .......................................... 365
SFR Definition 27.4. P0MASK: Port0 Mask Register .................................................. 366
SFR Definition 27.5. P0MAT: Port0 Match Register ................................................... 366
SFR Definition 27.6. P1MASK: Port1 Mask Register .................................................. 367
SFR Definition 27.7. P1MAT: Port1 Match Register ................................................... 367
SFR Definition 27.8. P0: Port0 .................................................................................... 369
SFR Definition 27.9. P0SKIP: Port0 Skip .................................................................... 369
SFR Definition 27.10. P0MDIN: Port0 Input Mode ...................................................... 370
SFR Definition 27.11. P0MDOUT: Port0 Output Mode ............................................... 370
SFR Definition 27.12. P0DRV: Port0 Drive Strength .................................................. 371
SFR Definition 27.13. P1: Port1 .................................................................................. 371
SFR Definition 27.14. P1SKIP: Port1 Skip .................................................................. 372
SFR Definition 27.15. P1MDIN: Port1 Input Mode ...................................................... 372
SFR Definition 27.16. P1MDOUT: Port1 Output Mode ............................................... 373
SFR Definition 27.17. P1DRV: Port1 Drive Strength .................................................. 373
SFR Definition 27.18. P2: Port2 .................................................................................. 374
20
Rev. 0.3
C8051F96x
SFR Definition 27.19. P2SKIP: Port2 Skip .................................................................. 374
SFR Definition 27.20. P2MDIN: Port2 Input Mode ...................................................... 375
SFR Definition 27.21. P2MDOUT: Port2 Output Mode ............................................... 375
SFR Definition 27.22. P2DRV: Port2 Drive Strength .................................................. 376
SFR Definition 27.23. P3: Port3 .................................................................................. 376
SFR Definition 27.24. P3MDIN: Port3 Input Mode ...................................................... 377
SFR Definition 27.25. P3MDOUT: Port3 Output Mode ............................................... 377
SFR Definition 27.26. P3DRV: Port3 Drive Strength .................................................. 378
SFR Definition 27.27. P4: Port4 .................................................................................. 378
SFR Definition 27.28. P4MDIN: Port4 Input Mode ...................................................... 379
SFR Definition 27.29. P4MDOUT: Port4 Output Mode ............................................... 379
SFR Definition 27.30. P4DRV: Port4 Drive Strength .................................................. 380
SFR Definition 27.31. P5: Port5 .................................................................................. 380
SFR Definition 27.32. P5MDIN: Port5 Input Mode ...................................................... 381
SFR Definition 27.33. P5MDOUT: Port5 Output Mode ............................................... 381
SFR Definition 27.34. P5DRV: Port5 Drive Strength .................................................. 382
SFR Definition 27.35. P6: Port6 .................................................................................. 382
SFR Definition 27.36. P6MDIN: Port6 Input Mode ...................................................... 383
SFR Definition 27.37. P6MDOUT: Port6 Output Mode ............................................... 383
SFR Definition 27.38. P6DRV: Port6 Drive Strength .................................................. 384
SFR Definition 27.39. P7: Port7 .................................................................................. 384
SFR Definition 27.40. P7MDOUT: Port7 Output Mode ............................................... 385
SFR Definition 27.41. P7DRV: Port7 Drive Strength .................................................. 385
SFR Definition 28.1. SMB0CF: SMBus Clock/Configuration ...................................... 392
SFR Definition 28.2. SMB0CN: SMBus Control .......................................................... 394
SFR Definition 28.3. SMB0ADR: SMBus Slave Address ............................................ 396
SFR Definition 28.4. SMB0ADM: SMBus Slave Address Mask .................................. 397
SFR Definition 28.5. SMB0DAT: SMBus Data ............................................................ 398
SFR Definition 29.1. SCON0: Serial Port 0 Control .................................................... 412
SFR Definition 29.2. SBUF0: Serial (UART0) Port Data Buffer .................................. 413
SFR Definition 30.1. SPI0CFG: SPI0 Configuration ................................................... 423
SFR Definition 30.2. SPI0CN: SPI0 Control ............................................................... 424
SFR Definition 30.3. SPI0CKR: SPI0 Clock Rate ....................................................... 425
SFR Definition 30.4. SPI0DAT: SPI0 Data ................................................................. 425
SFR Definition 31.1. SPI1CFG: SPI1 Configuration ................................................... 442
SFR Definition 31.2. SPI1CN: SPI1 Control ............................................................... 443
SFR Definition 31.3. SPI1CKR: SPI1 Clock Rate ....................................................... 444
SFR Definition 31.4. SPI1DAT: SPI1 Data ................................................................. 444
SFR Definition 32.1. CKCON: Clock Control .............................................................. 449
SFR Definition 32.2. TCON: Timer Control ................................................................. 454
SFR Definition 32.3. TMOD: Timer Mode ................................................................... 455
SFR Definition 32.4. TL0: Timer 0 Low Byte ............................................................... 456
SFR Definition 32.5. TL1: Timer 1 Low Byte ............................................................... 456
SFR Definition 32.6. TH0: Timer 0 High Byte ............................................................. 457
SFR Definition 32.7. TH1: Timer 1 High Byte ............................................................. 457
Rev. 0.3
21
C8051F96x
SFR Definition 32.8. TMR2CN: Timer 2 Control ......................................................... 461
SFR Definition 32.9. TMR2RLL: Timer 2 Reload Register Low Byte .......................... 462
SFR Definition 32.10. TMR2RLH: Timer 2 Reload Register High Byte ...................... 462
SFR Definition 32.11. TMR2L: Timer 2 Low Byte ....................................................... 463
SFR Definition 32.12. TMR2H Timer 2 High Byte ....................................................... 463
SFR Definition 32.13. TMR3CN: Timer 3 Control ....................................................... 467
SFR Definition 32.14. TMR3RLL: Timer 3 Reload Register Low Byte ........................ 468
SFR Definition 32.15. TMR3RLH: Timer 3 Reload Register High Byte ...................... 468
SFR Definition 32.16. TMR3L: Timer 3 Low Byte ....................................................... 469
SFR Definition 32.17. TMR3H Timer 3 High Byte ....................................................... 469
SFR Definition 33.1. PCA0CN: PCA Control .............................................................. 484
SFR Definition 33.2. PCA0MD: PCA Mode ................................................................ 485
SFR Definition 33.3. PCA0PWM: PCA PWM Configuration ....................................... 486
SFR Definition 33.4. PCA0CPMn: PCA Capture/Compare Mode .............................. 487
SFR Definition 33.5. PCA0L: PCA Counter/Timer Low Byte ...................................... 488
SFR Definition 33.6. PCA0H: PCA Counter/Timer High Byte ..................................... 488
SFR Definition 33.7. PCA0CPLn: PCA Capture Module Low Byte ............................. 489
SFR Definition 33.8. PCA0CPHn: PCA Capture Module High Byte ........................... 489
C2 Register Definition 34.1. C2ADD: C2 Address ...................................................... 490
C2 Register Definition 34.2. DEVICEID: C2 Device ID ............................................... 491
C2 Register Definition 34.3. REVID: C2 Revision ID .................................................. 491
C2 Register Definition 34.4. FPCTL: C2 Flash Programming Control ........................ 492
C2 Register Definition 34.5. FPDAT: C2 Flash Programming Data ............................ 492
22
Rev. 0.3
C8051F96x
1. System Overview
C8051F96x devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are
listed below. Refer to Table 2.1 for specific product feature selection and part ordering numbers.
Power efficient on-chip dc-dc buck converter.
High-speed pipelined 8051-compatible microcontroller core (up to 25 MIPS)
In-system, full-speed, non-intrusive debug interface (on-chip)
True 10-bit 300 ksps, or 12-bit 75 ksps single-ended ADC with 16 external analog inputs and 4 internal
inputs such as various power supply voltages and the temperature sensor.
6-Bit Programmable Current Reference
Precision programmable 24.5 MHz internal oscillator with spread spectrum technology.
128 kB, 64 kB, 32 kB, or 16 kB of on-chip flash memory
8448 or 4352 bytes of on-chip RAM
128 Segment LCD Driver
SMBus/I2C, Enhanced UART, and two Enhanced SPI serial interfaces implemented in hardware
Four general-purpose 16-bit timers
Programmable Counter/Timer Array (PCA) with six capture/compare modules and Watchdog Timer
function
Hardware AES, DMA, and Pulse Counter
On-chip Power-On Reset, VDD Monitor, and Temperature Sensor
Two On-chip Voltage Comparators.
57 or 34 Port I/O
With on-chip Power-On Reset, VDD monitor, Watchdog Timer, and clock oscillator, the C8051F96x devices
are truly stand-alone System-on-a-Chip solutions. The flash memory can be reprogrammed even in-circuit,
providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. User software
has complete control of all peripherals, and may individually shut down any or all peripherals for power
savings.
The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip
resources), full speed, in-circuit debugging using the production MCU installed in the final application. This
debug logic supports inspection and modification of memory and registers, setting breakpoints, single
stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging
using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging without occupying package pins.
Each device is specified for 1.8 to 3.8 V operation over the industrial temperature range (–40 to +85 °C).
The Port I/O and RST pins are tolerant of input signals up to VIO + 2.0 V. The C8051F960/2/4/6/8 are
available in a 76-pin DQFN package and an 80-pin TQFP package. The C8051F961/3/5/7/9 are available
in a 40-pin QFN package. All package options are lead-free and RoHS compliant. See Table 2.1 for ordering information. Block diagrams are included in Figure 1.1 through Figure 1.16.
Rev. 0.3
23
C8051F96x
Wake
Reset
C2CK/RST
Debug /
Programming
Hardware
VBAT
UART
256 Byte SRAM
Timers 0,
1, 2, 3
8092 Byte XRAM
VDD
VDC
VREG
Analog
Power
VREG
Digital
Power
DC/DC
“Buck”
Converter
DMA
SMBus
CRC
Engine
SPI 0,1
VLCD
LCD Charge
Pump
Low Power
20 MHz
Oscillator
Analog Peripherals
External
Oscillator
Circuit
XTAL2
GND
XTAL4
Internal
External
VREF
VREF
VDD
VREF
Temp
Sensor
A
M
U
X
12-bit
75ksps
ADC
Enhanced
smaRTClock
Oscillator
XTAL3
EMIF
Pulse Counter
XTAL1
Port 2
Drivers
LCD (up to 4x32)
SFR
Bus
Precision
24.5 MHz
Oscillator
GNDDC
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
Crossbar Control
AES
Engine
SYSCLK
Port 1
Drivers
P1.0/PC0
P1.1/PC1
P1.2/XTAL3
P1.3/XTAL4
P1.4
P1.5
P1.6
P1.7
Priority
Crossbar
Decoder
PCA/
WDT
Encoder
VBATDC
IND
Port 0
Drivers
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7/IREF0
Digital Peripherals
128k Byte ISP Flash
Program Memory
C2D
VBAT
Port I/O Configuration
CIP-51 8051
Controller Core
Power On
Reset/PMU
P3-6
Drivers
32
P7
Driver
1
P3.0...P6.7
P7.0/C2D
VIO
GND
CP0, CP0A
System Clock
Configuration
CP1, CP1A
VIORF
+
-
+
-
Comparators
Figure 1.1. C8051F960 Block Diagram
Wake
Reset
C2CK/RST
Debug /
Programming
Hardware
VBAT
UART
256 Byte SRAM
Timers 0,
1, 2, 3
8092 Byte XRAM
VDD
VDC
VREG
Analog
Power
VREG
Digital
Power
DC/DC
“Buck”
Converter
DMA
SMBus
CRC
Engine
SPI 0,1
GNDDC
VLCD
LCD Charge
Pump
XTAL1
LCD (up to 4x32)
XTAL2
GND
XTAL3
XTAL4
SFR
Bus
EMIF
Precision
24.5 MHz
Oscillator
Pulse Counter
Low Power
20 MHz
Oscillator
Analog Peripherals
External
Oscillator
Circuit
Enhanced
smaRTClock
Oscillator
Internal
External
VREF
VREF
A
M
U
X
12-bit
75ksps
ADC
VDD
VREF
Temp
Sensor
GND
CP0, CP0A
System Clock
Configuration
CP1, CP1A
+
-
+
-
Comparators
Figure 1.2. C8051F961 Block Diagram
24
Port 2
Drivers
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
Crossbar Control
AES
Engine
SYSCLK
Port 1
Drivers
P1.0/PC0
P1.1/PC1
P1.2/XTAL3
P1.3/XTAL4
P1.4
P1.5
P1.6
P1.7
Priority
Crossbar
Decoder
PCA/
WDT
Encoder
VBATDC
IND
Port 0
Drivers
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7/IREF0
Digital Peripherals
128k Byte ISP Flash
Program Memory
C2D
VBAT
Port I/O Configuration
CIP-51 8051
Controller Core
Power On
Reset/PMU
Rev. 0.3
P3-4
Drivers
8
P7
Driver
1
P3.0...P4.0
P7.0/C2D
C8051F96x
Wake
Reset
C2CK/RST
Debug /
Programming
Hardware
VBAT
UART
256 Byte SRAM
Timers 0,
1, 2, 3
8092 Byte XRAM
VDD
VDC
VREG
Analog
Power
VREG
Digital
Power
Port 0
Drivers
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7/IREF0
Port 1
Drivers
P1.0/PC0
P1.1/PC1
P1.2/XTAL3
P1.3/XTAL4
P1.4
P1.5
P1.6
P1.7
Port 2
Drivers
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
Digital Peripherals
128k Byte ISP Flash
Program Memory
C2D
VBAT
Port I/O Configuration
CIP-51 8051
Controller Core
Power On
Reset/PMU
Priority
Crossbar
Decoder
PCA/
WDT
DMA
SMBus
CRC
Engine
SPI 0,1
Crossbar Control
AES
Engine
Encoder
VBATDC
IND
DC/DC
“Buck”
Converter
SYSCLK
Pulse Counter
Low Power
20 MHz
Oscillator
Analog Peripherals
External
Oscillator
Circuit
XTAL1
XTAL2
XTAL4
Internal
External
VREF
VREF
A
M
U
X
12-bit
75ksps
ADC
Enhanced
smaRTClock
Oscillator
XTAL3
EMIF
Precision
24.5 MHz
Oscillator
GNDDC
GND
SFR
Bus
VDD
VREF
Temp
Sensor
P3-6
Drivers
32
P7
Driver
1
P3.0...P6.7
P7.0/C2D
VIO
GND
CP0, CP0A
System Clock
Configuration
CP1, CP1A
VIORF
+
-
+
-
Comparators
Figure 1.3. C8051F962 Block Diagram
Wake
Reset
C2CK/RST
Debug /
Programming
Hardware
VBAT
UART
256 Byte SRAM
Timers 0,
1, 2, 3
8092 Byte XRAM
VDD
VDC
VREG
Analog
Power
VREG
Digital
Power
Port 0
Drivers
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7/IREF0
Port 1
Drivers
P1.0/PC0
P1.1/PC1
P1.2/XTAL3
P1.3/XTAL4
P1.4
P1.5
P1.6
P1.7
Port 2
Drivers
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
Digital Peripherals
128k Byte ISP Flash
Program Memory
C2D
VBAT
Port I/O Configuration
CIP-51 8051
Controller Core
Power On
Reset/PMU
Priority
Crossbar
Decoder
PCA/
WDT
DMA
SMBus
CRC
Engine
SPI 0,1
Crossbar Control
AES
Engine
Encoder
VBATDC
IND
DC/DC
“Buck”
Converter
GNDDC
XTAL1
XTAL2
GND
XTAL3
XTAL4
SYSCLK
SFR
Bus
EMIF
Precision
24.5 MHz
Oscillator
Pulse Counter
Low Power
20 MHz
Oscillator
Analog Peripherals
External
Oscillator
Circuit
Enhanced
smaRTClock
Oscillator
Internal
External
VREF
VREF
A
M
U
X
12-bit
75ksps
ADC
P3-4
Drivers
8
P7
Driver
1
P3.0...P4.0
P7.0/C2D
GND
CP0, CP0A
System Clock
Configuration
VDD
VREF
Temp
Sensor
CP1, CP1A
+
-
+
-
Comparators
Figure 1.4. C8051F963 Block Diagram
Rev. 0.3
25
C8051F96x
Wake
Reset
C2CK/RST
Debug /
Programming
Hardware
VBAT
UART
256 Byte SRAM
Timers 0,
1, 2, 3
8092 Byte XRAM
VDD
VDC
VREG
Analog
Power
VREG
Digital
Power
DC/DC
“Buck”
Converter
DMA
SMBus
CRC
Engine
SPI 0,1
VLCD
LCD Charge
Pump
Low Power
20 MHz
Oscillator
Analog Peripherals
External
Oscillator
Circuit
XTAL2
GND
XTAL4
Internal
External
VREF
VREF
VDD
VREF
Temp
Sensor
A
M
U
X
12-bit
75ksps
ADC
Enhanced
smaRTClock
Oscillator
XTAL3
EMIF
Pulse Counter
XTAL1
Port 2
Drivers
LCD (up to 4x32)
SFR
Bus
Precision
24.5 MHz
Oscillator
GNDDC
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
Crossbar Control
AES
Engine
SYSCLK
Port 1
Drivers
P1.0/PC0
P1.1/PC1
P1.2/XTAL3
P1.3/XTAL4
P1.4
P1.5
P1.6
P1.7
Priority
Crossbar
Decoder
PCA/
WDT
Encoder
VBATDC
IND
Port 0
Drivers
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7/IREF0
Digital Peripherals
64k Byte ISP Flash
Program Memory
C2D
VBAT
Port I/O Configuration
CIP-51 8051
Controller Core
Power On
Reset/PMU
P3-6
Drivers
32
P7
Driver
1
P3.0...P6.7
P7.0/C2D
VIO
GND
CP0, CP0A
System Clock
Configuration
CP1, CP1A
VIORF
+
-
+
-
Comparators
Figure 1.5. C8051F964 Block Diagram
Wake
Reset
C2CK/RST
Debug /
Programming
Hardware
VBAT
UART
256 Byte SRAM
Timers 0,
1, 2, 3
8092 Byte XRAM
VDD
VDC
VREG
Analog
Power
VREG
Digital
Power
DC/DC
“Buck”
Converter
DMA
SMBus
CRC
Engine
SPI 0,1
GNDDC
VLCD
LCD Charge
Pump
XTAL1
LCD (up to 4x32)
XTAL2
GND
XTAL3
XTAL4
SFR
Bus
EMIF
Precision
24.5 MHz
Oscillator
Pulse Counter
Low Power
20 MHz
Oscillator
Analog Peripherals
External
Oscillator
Circuit
Enhanced
smaRTClock
Oscillator
Internal
External
VREF
VREF
A
M
U
X
12-bit
75ksps
ADC
VDD
VREF
Temp
Sensor
GND
CP0, CP0A
System Clock
Configuration
CP1, CP1A
+
-
+
-
Comparators
Figure 1.6. C8051F965 Block Diagram
26
Port 2
Drivers
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
Crossbar Control
AES
Engine
SYSCLK
Port 1
Drivers
P1.0/PC0
P1.1/PC1
P1.2/XTAL3
P1.3/XTAL4
P1.4
P1.5
P1.6
P1.7
Priority
Crossbar
Decoder
PCA/
WDT
Encoder
VBATDC
IND
Port 0
Drivers
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7/IREF0
Digital Peripherals
64k Byte ISP Flash
Program Memory
C2D
VBAT
Port I/O Configuration
CIP-51 8051
Controller Core
Power On
Reset/PMU
Rev. 0.3
P3-4
Drivers
8
P7
Driver
1
P3.0...P4.0
P7.0/C2D
C8051F96x
Wake
Reset
C2CK/RST
Debug /
Programming
Hardware
VBAT
UART
256 Byte SRAM
Timers 0,
1, 2, 3
8092 Byte XRAM
VDD
VDC
VREG
Analog
Power
VREG
Digital
Power
DC/DC
“Buck”
Converter
DMA
SMBus
CRC
Engine
SPI 0,1
VLCD
LCD Charge
Pump
Low Power
20 MHz
Oscillator
Analog Peripherals
External
Oscillator
Circuit
XTAL2
GND
XTAL4
Internal
External
VREF
VREF
VDD
VREF
Temp
Sensor
A
M
U
X
12-bit
75ksps
ADC
Enhanced
smaRTClock
Oscillator
XTAL3
EMIF
Pulse Counter
XTAL1
Port 2
Drivers
LCD (up to 4x32)
SFR
Bus
Precision
24.5 MHz
Oscillator
GNDDC
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
Crossbar Control
AES
Engine
SYSCLK
Port 1
Drivers
P1.0/PC0
P1.1/PC1
P1.2/XTAL3
P1.3/XTAL4
P1.4
P1.5
P1.6
P1.7
Priority
Crossbar
Decoder
PCA/
WDT
Encoder
VBATDC
IND
Port 0
Drivers
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7/IREF0
Digital Peripherals
32k Byte ISP Flash
Program Memory
C2D
VBAT
Port I/O Configuration
CIP-51 8051
Controller Core
Power On
Reset/PMU
P3-6
Drivers
32
P7
Driver
1
P3.0...P6.7
P7.0/C2D
VIO
GND
CP0, CP0A
System Clock
Configuration
CP1, CP1A
VIORF
+
-
+
-
Comparators
Figure 1.7. C8051F966 Block Diagram
Wake
Reset
C2CK/RST
Debug /
Programming
Hardware
VBAT
UART
256 Byte SRAM
Timers 0,
1, 2, 3
8092 Byte XRAM
VDD
VDC
VREG
Analog
Power
VREG
Digital
Power
DC/DC
“Buck”
Converter
DMA
SMBus
CRC
Engine
SPI 0,1
GNDDC
VLCD
LCD Charge
Pump
XTAL1
LCD (up to 4x32)
XTAL2
GND
XTAL3
XTAL4
SFR
Bus
EMIF
Precision
24.5 MHz
Oscillator
Pulse Counter
Low Power
20 MHz
Oscillator
Analog Peripherals
External
Oscillator
Circuit
Enhanced
smaRTClock
Oscillator
Internal
External
VREF
VREF
A
M
U
X
12-bit
75ksps
ADC
VDD
VREF
Temp
Sensor
P3-4
Drivers
8
P7
Driver
1
P3.0...P4.0
P7.0/C2D
GND
CP0, CP0A
System Clock
Configuration
Port 2
Drivers
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
Crossbar Control
AES
Engine
SYSCLK
Port 1
Drivers
P1.0/PC0
P1.1/PC1
P1.2/XTAL3
P1.3/XTAL4
P1.4
P1.5
P1.6
P1.7
Priority
Crossbar
Decoder
PCA/
WDT
Encoder
VBATDC
IND
Port 0
Drivers
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7/IREF0
Digital Peripherals
32k Byte ISP Flash
Program Memory
C2D
VBAT
Port I/O Configuration
CIP-51 8051
Controller Core
Power On
Reset/PMU
CP1, CP1A
+
-
+
-
Comparators
Figure 1.8. C8051F967 Block Diagram
Rev. 0.3
27
C8051F96x
Wake
Reset
C2CK/RST
Debug /
Programming
Hardware
VBAT
UART
256 Byte SRAM
Timers 0,
1, 2, 3
4096 Byte XRAM
VDD
VDC
VREG
Analog
Power
VREG
Digital
Power
DC/DC
“Buck”
Converter
DMA
SMBus
CRC
Engine
SPI 0,1
VLCD
LCD Charge
Pump
Low Power
20 MHz
Oscillator
Analog Peripherals
External
Oscillator
Circuit
XTAL2
GND
XTAL4
Internal
External
VREF
VREF
VDD
VREF
Temp
Sensor
A
M
U
X
12-bit
75ksps
ADC
Enhanced
smaRTClock
Oscillator
XTAL3
EMIF
Pulse Counter
XTAL1
Port 2
Drivers
LCD (up to 4x32)
SFR
Bus
Precision
24.5 MHz
Oscillator
GNDDC
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
Crossbar Control
AES
Engine
SYSCLK
Port 1
Drivers
P1.0/PC0
P1.1/PC1
P1.2/XTAL3
P1.3/XTAL4
P1.4
P1.5
P1.6
P1.7
Priority
Crossbar
Decoder
PCA/
WDT
Encoder
VBATDC
IND
Port 0
Drivers
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7/IREF0
Digital Peripherals
16k Byte ISP Flash
Program Memory
C2D
VBAT
Port I/O Configuration
CIP-51 8051
Controller Core
Power On
Reset/PMU
P3-6
Drivers
32
P7
Driver
1
P3.0...P6.7
P7.0/C2D
VIO
GND
CP0, CP0A
System Clock
Configuration
CP1, CP1A
VIORF
+
-
+
-
Comparators
Figure 1.9. C8051F968 Block Diagram
Wake
Reset
C2CK/RST
Debug /
Programming
Hardware
VBAT
UART
256 Byte SRAM
Timers 0,
1, 2, 3
4096 Byte XRAM
VDD
VDC
VREG
Analog
Power
VREG
Digital
Power
DC/DC
“Buck”
Converter
DMA
SMBus
CRC
Engine
SPI 0,1
GNDDC
VLCD
LCD Charge
Pump
XTAL1
LCD (up to 4x32)
XTAL2
GND
XTAL3
XTAL4
SFR
Bus
EMIF
Precision
24.5 MHz
Oscillator
Pulse Counter
Low Power
20 MHz
Oscillator
Analog Peripherals
External
Oscillator
Circuit
Enhanced
smaRTClock
Oscillator
Internal
External
VREF
VREF
A
M
U
X
12-bit
75ksps
ADC
VDD
VREF
Temp
Sensor
GND
CP0, CP0A
System Clock
Configuration
CP1, CP1A
+
-
+
-
Comparators
Figure 1.10. C8051F969 Block Diagram
28
Port 2
Drivers
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
Crossbar Control
AES
Engine
SYSCLK
Port 1
Drivers
P1.0/PC0
P1.1/PC1
P1.2/XTAL3
P1.3/XTAL4
P1.4
P1.5
P1.6
P1.7
Priority
Crossbar
Decoder
PCA/
WDT
Encoder
VBATDC
IND
Port 0
Drivers
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7/IREF0
Digital Peripherals
16k Byte ISP Flash
Program Memory
C2D
VBAT
Port I/O Configuration
CIP-51 8051
Controller Core
Power On
Reset/PMU
Rev. 0.3
P3-4
Drivers
8
P7
Driver
1
P3.0...P4.0
P7.0/C2D
C8051F96x
1.1. CIP-51™ Microcontroller Core
1.1.1. Fully 8051 Compatible
The C8051F96x family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully
compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used
to develop software. The CIP-51 core offers all the peripherals included with a standard 8052.
1.1.2. Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than
four system clock cycles.
The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that
require each execution time.
Clocks to Execute
1
2
2/3
3
3/4
4
4/5
5
8
Number of Instructions
26
50
5
14
7
3
1
2
1
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS.
1.1.3. Additional Features
The C8051F96x SoC family includes several key enhancements to the CIP-51 core and peripherals to
improve performance and ease of use in end applications.
The extended interrupt handler provides multiple interrupt sources into the CIP-51 allowing numerous analog and digital peripherals to interrupt the controller. An interrupt driven system requires less intervention
by the MCU, giving it more effective throughput. The extra interrupt sources are very useful when building
multi-tasking, real-time systems.
Eight reset sources are available: power-on reset circuitry (POR), an on-chip VDD monitor (forces reset
when power supply voltage drops below safe levels), a Watchdog Timer, a Missing Clock Detector,
SmaRTClock oscillator fail or alarm, a voltage level detection from Comparator0, a forced software reset,
an external reset pin, and an illegal flash access protection circuit. Each reset source except for the POR,
Reset Input Pin, or flash error may be disabled by the user in software. The WDT may be permanently disabled in software after a power-on reset during MCU initialization.
The internal oscillator factory calibrated to 24.5 MHz and is accurate to ±2% over the full temperature and
supply range. The internal oscillator period can also be adjusted by user firmware. An additional 20 MHz
low power oscillator is also available which facilitates low-power operation. An external oscillator drive circuit is included, allowing an external crystal, ceramic resonator, capacitor, RC, or CMOS clock source to
generate the system clock. If desired, the system clock source may be switched on-the-fly between both
internal and external oscillator circuits. An external oscillator can also be extremely useful in low power
applications, allowing the MCU to run from a slow (power saving) source, while periodically switching to
the fast (up to 25 MHz) internal oscillator as needed.
Rev. 0.3
29
C8051F96x
1.2. Port Input/Output
Digital and analog resources are available through 57 I/O pins (C8051F960/2/4/6/8) or 34 I/O pins
(C8051F961/3/5/7/9). Port pins are organized as eight byte-wide ports. Port pins can be defined as digital
or analog I/O. Digital I/O pins can be assigned to one of the internal digital resources or used as general
purpose I/O (GPIO). Analog I/O pins are used by the internal analog resources. P7.0 can be used as GPIO
and is shared with the C2 Interface Data signal (C2D). See Section “34. C2 Interface” on page 490 for
more details.
The designer has complete control over which digital and analog functions are assigned to individual port
pins. This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder. See
Section “27. Port Input/Output” on page 356 for more information on the Crossbar.
For Port I/Os configured as push-pull outputs, current is sourced from the VIO, VIORF, or VBAT supply pin.
Port I/Os used for analog functions can operate up to the supply voltage. See Section “27. Port Input/Output” on page 356 for more information on Port I/O operating modes and the electrical specifications chapter for detailed electrical specifications.
Port Match
P0MASK, P0MAT
P1MASK, P1MAT
Highest
Priority
2
UART
(Internal Digital Signals)
Priority
Decoder
PnMDOUT,
PnMDIN Registers
8
8
4
SPI0
SPI1
P1
I/O
Cells
SMBus
8
CP0
CP1
Outputs
4
Digital
Crossbar
8
SYSCLK
7
2
T0, T1
8
8
8
P0
(Port Latches)
P0
I/O
Cells
8
P6
8
(P6.0-P6.7)
1
P7
1
(P7.0)
To Analog Peripherals
(ADC0, CP0, and CP1 inputs,
VREF, IREF0, AGND)
P2
I/O
Cells
P3
I/O
Cells
P4
I/O
Cells
P5
I/O
Cells
P6
I/O
Cells
P7
To EMIF
Figure 1.11. Port I/O Functional Block Diagram
30
External Interrupts
EX0 and EX1
P0.0
P0.7
P1.0
P1.7
2
PCA
Lowest
Priority
XBR0, XBR1,
XBR2, PnSKIP
Registers
Rev. 0.3
P2.0
P2.7
P3.0
P3.7
P4.0
P4.7
P5.0
P5.7
P6.0
P6.7
P7.0
To LCD
C8051F96x
1.3. Serial Ports
The C8051F96x Family includes an SMBus/I2C interface, a full-duplex UART with enhanced baud rate
configuration, and two Enhanced SPI interfaces. Each of the serial buses is fully implemented in hardware
and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention.
1.4. Programmable Counter Array
An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit general purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with six programmable capture/compare modules. The PCA clock is derived from one of six sources: the system clock divided
by 12, the system clock divided by 4, Timer 0 overflows, an External Clock Input (ECI), the system clock, or
the external oscillator clock source divided by 8.
Each capture/compare module can be configured to operate in a variety of modes: edge-triggered capture,
software timer, high-speed output, pulse width modulator (8, 9, 10, 11, or 16-bit), or frequency output. Additionally, Capture/Compare Module 5 offers watchdog timer (WDT) capabilities. Following a system reset,
Module 5 is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O and External
Clock Input may be routed to Port I/O via the Digital Crossbar.
SYSCLK /12
SYSCLK /4
Timer 0 Overflow
ECI
PCA
CLOCK
MUX
16 -Bit Counter/Timer
SYSCLK
External Clock /8
Capture/ Compare
Module 0
Capture/ Compare
Module 1
Capture/ Compare
Module 2
Capture/ Compare
Module 3
Capture/ Compare
Module 4
Capture/ Compare
Module5 / WDT
CEX5
CEX4
CEX3
CEX2
CEX1
CEX0
ECI
Crossbar
Port I/O
Figure 1.12. PCA Block Diagram
Rev. 0.3
31
C8051F96x
1.5. SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous Low
Power Burst Mode
The ADC0 on C8051F96x devices is a 300 ksps, 10-bit or 75 ksps, 12-bit successive-approximation-register (SAR) ADC with integrated track-and-hold and programmable window detector. ADC0 also has an
autonomous low power Burst Mode which can automatically enable ADC0, capture and accumulate samples, then place ADC0 in a low power shutdown mode without CPU intervention. It also has a 16-bit accumulator that can automatically oversample and average the ADC results. See Section “5.4. 12-Bit Mode”
on page 84 for more details on using the ADC in 12-bit mode.
The ADC is fully configurable under software control via Special Function Registers. The ADC0 operates in
single-ended mode and may be configured to measure various different signals using the analog multiplexer described in Section “5.7. ADC0 Analog Multiplexer” on page 95. The voltage reference for the ADC
is selected as described in Section “5.9. Voltage and Ground Reference Options” on page 100.
AD0EN
BURSTEN
AD0INT
AD0BUSY
AD0WINT
AD0CM2
AD0CM1
AD0CM0
ADC0CN
VDD
Start
Conversion
ADC0TK
Burst Mode Logic
AIN+
ADC
AD0SC4
AD0SC3
AD0SC2
AD0SC1
AD0SC0
AD08BE
AD0TM
AMP0GN
SYSCLK
REF
16-Bit Accumulator
ADC0H
From
AMUX0
10/12-Bit
SAR
ADC0LTH ADC0LTL
ADC0CF
ADC0GTH ADC0GTL
AD0WINT
32
Figure 1.13. ADC0 Functional Block Diagram
32
AD0BUSY (W)
Timer 0 Overflow
Timer 2 Overflow
Timer 3 Overflow
CNVSTR Input
ADC0L
ADC0PWR
000
001
010
011
100
Rev. 0.3
Window
Compare
Logic
C8051F96x
AD0MX4
AD0MX3
AD0MX2
AD0MX1
AM0MX0
ADC0MX
P0.0
Programmable
Attenuator
AIN+
P2.6*
AMUX
ADC0
Temp
Sensor
Gain = 0. 5 or 1
VBAT
Digital Supply
VDD/DC+
*P1.7-P2. 6 only available as
inputs on 32- pin packages
Figure 1.14. ADC0 Multiplexer Block Diagram
1.6. Programmable Current Reference (IREF0)
C8051F96x devices include an on-chip programmable current reference (source or sink) with two output
current settings: low power mode and high current mode. The maximum current output in low power mode
is 63 µA (1 µA steps) and the maximum current output in high current mode is 504 µA (8 µA steps).
1.7. Comparators
C8051F96x devices include two on-chip programmable voltage comparators: Comparator 0 (CPT0) which
is shown in Figure 1.15; Comparator 1 (CPT1) which is shown in Figure 1.16. The two comparators operate identically but may differ in their ability to be used as reset or wake-up sources. See Section “22. Reset
Sources” on page 283 and the Section “19. Power Management” on page 262 for details on reset sources
and low power mode wake-up sources, respectively.
The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an
asynchronous “raw” output (CP0A, CP1A). The asynchronous CP0A signal is available even when the
system clock is not active. This allows the Comparator to operate and generate an output when the device
is in some low power modes.
The comparator inputs may be connected to Port I/O pins or to other internal signals. Port pins may also be
used to directly sense capacitive touch switches. See Application Note AN338 for details on Capacitive
Touch Switch sensing.
Rev. 0.3
33
CPT0CN
C8051F96x
CP0EN
CP0OUT
CP0RIF
CP0FIF
VDD
CP0HYP1
CP0HYP0
CP0HYN1
CP0
Interrupt
CP0HYN0
CPT0MD
Analog Input Multiplexer
CP0FIE
CP0RIE
CP0MD1
CP0MD0
Px.x
CP0
Rising-edge
CP0 +
CP0
Falling-edge
Interrupt
Logic
Px.x
CP0
+
SET
D
-
CLR
D
Q
Q
SET
CLR
Q
Q
Px.x
Crossbar
(SYNCHRONIZER)
GND
CP0 -
CP0A
(ASYNCHRONOUS)
Reset
Decision
Tree
Px.x
Figure 1.15. Comparator 0 Functional Block Diagram
CPT0CN
CP1EN
CP1OUT
CP1RIF
VDD
CP1FIF
CP1HYP1
CP1
Interrupt
CP1HYP0
CP1HYN1
CP1HYN0
CPT0MD
Analog Input Multiplexer
CP1FIE
CP1RIE
CP1MD1
CP1MD0
Px.x
CP1
Rising-edge
CP1 +
CP1
Falling-edge
Interrupt
Logic
Px.x
CP1
+
D
-
SET
CLR
Q
Q
D
SET
CLR
Q
Q
Px.x
Crossbar
(SYNCHRONIZER)
CP1 -
GND
(ASYNCHRONOUS)
Reset
Decision
Tree
Px.x
Figure 1.16. Comparator 1 Functional Block Diagram
34
Rev. 0.3
CP1A
C8051F96x
2. Ordering Information
AES 128, 192, 256 Encryption
LCD Segments (4-MUX)
SmaRTClock Real Time Clock
SMBus/I2C
UART
Enhanced SPI
Timers (16-bit)
PCA Channels
10/12-bit 300/75 ksps ADC channels
with internal VREF and temp sensor
Analog Comparators
Package
128
1
1
2
4
6
16
2
DQFN-76 (6x6)
C8051F960-A-GQ
25 128 8448 57
128
1
1
2
4
6
16
2
TQFP80 (12x12)
C8051F961-A-GM
25 128 8448 34
36
1
1
2
4
6
16
2
QFN-40 (6x6)
C8051F962-A-GM
25 128 8448 57
—
1
1
2
4
6
16
2
DQFN-76 (6x6)
C8051F962-A-GQ
25 128 8448 57
—
1
1
2
4
6
16
2
TQFP80 (12x12)
C8051F963-A-GM
25 128 8448 34
—
1
1
2
4
6
16
2
QFN-40 (6x6)
C8051F964-A-GM
25
64
8448 57
128
1
1
2
4
6
16
2
DQFN-76 (6x6)
C8051F964-A-GQ
25
64
8448 57
128
1
1
2
4
6
16
2
TQFP80 (12x12)
C8051F965-A-GM
25
64
8448 34
36
1
1
2
4
6
16
2
QFN-40 (6x6)
C8051F966-A-GM
25
32
8448 57
128
1
1
2
4
6
16
2
DQFN-76 (6x6)
C8051F966-A-GQ
25
32
8448 57
128
1
1
2
4
6
16
2
TQFP80 (12x12)
C8051F967-A-GM
25
32
8448 34
36
1
1
2
4
6
16
2
QFN-40 (6x6)
C8051F968-A-GM
25
16
4352 57
128
1
1
2
4
6
16
2
DQFN-76 (6x6)
C8051F968-A-GQ
25
16
4352 57
128
1
1
2
4
6
16
2
TQFP80 (12x12)
C8051F969-A-GM
25
16
4352 34
36
1
1
2
4
6
16
2
QFN-40 (6x6)
RAM (bytes)
Flash Memory (kB)
25 128 8448 57
MIPS (Peak)
C8051F960-A-GM
Ordering Part Number
Digital Port I/Os
Table 2.1. Product Selection Guide
All packages are Lead-free (RoHS Compliant).
Rev. 0.3
35
C8051F96x
3. Pinout and Package Definitions
Table 3.1. Pin Definitions for the C8051F96x
Name
Pin Numbers
DQFN76 TQFP80 QFN40
Description
VBAT
A5
8
5
P In
Battery Supply Voltage. Must be 1.8 to 3.6 V.
VBATDC
A6
10
5
P In
DC0 Input Voltage. Must be 1.8 to 3.6 V.
VDC
A8
14
8
P In
Alternate Power Supply Voltage. Must be 1.8 to 3.6 V. This
supply voltage must always be VBAT. Software may
select this supply voltage to power the digital logic.
P Out
Positive output of the dc-dc converter. A 1uF to 10uF
ceramic capacitor is required on this pin when using the dcdc converter. This pin can supply power to external devices
when the dc-dc converter is enabled.
GNDDC
A
12
7
P In
GND
B6
13,64,66
,68
7
G
IND
B5
11
6
P In
DC-DC Inductor Pin. This pin requires a 560 nH inductor to
VDC if the DC-DC converter is used.
VIO
B4
9
5
P In
I/O Power Supply for P0.0–P1.4 and P2.4–P7.0 pins. This
supply voltage must always be VBAT.
VIORF
B7
15
8
P In
I/O Power Supply for P1.5–P2.3 pins. This supply voltage
must always be VBAT.
RST/
A9
16
9
D I/O
Device Reset. Open-drain output of internal POR or VDD
monitor. An external source can initiate a system reset by
driving this pin low for at least 15 µs. A 1 k to 5 k pullup
to VDD is recommended. See Reset Sources Section for a
complete description.
D I/O
Clock signal for the C2 Debug Interface.
D I/O
Port 7.0. This pin can only be used as GPIO. The Crossbar
cannot route signals to this pin and it cannot be configured
as an analog input. See Port I/O Section for a complete
description.
D I/O
Bi-directional data signal for the C2 Debug Interface.
P I/O
LCD Power Supply. This pin requires a 10 µF capacitor to
stabilize the charge pump.
C2CK
P7.0/
A10
17
10
C2D
VLCD
36
Type
A32
61
32
DC-DC converter return current path. This pin is typically
tied to the ground plane.
Required Ground.
Rev. 0.3
C8051F96x
Table 3.1. Pin Definitions for the C8051F96x (Continued)
Name
P0.0
Pin Numbers
DQFN76 TQFP80 QFN40
A4
6
4
A3
4
3
P0.2
A2
2
2
P0.3
A1
1
1
D In
A In
P0.4
A40
79
40
P0.5
A39
78
39
P0.6
A38
76
38
P0.7
IREF0
A37
74
37
UART RX Pin. See Port I/O Section.
D I/O or Port 0.6. See Port I/O Section for a complete description.
A In
D In
CNVSTR
UART TX Pin. See Port I/O Section.
D I/O or Port 0.5. See Port I/O Section for a complete description.
A In
D In
RX
External Clock Output. This pin is the excitation driver for an
external crystal or resonator.
External Clock Input. This pin is the external clock input in
external CMOS clock mode.
External Clock Input. This pin is the external clock input in
capacitor or RC oscillator configurations.
See Oscillator Section for complete details.
D I/O or Port 0.4. See Port I/O Section for a complete description.
A In
D Out
TX
External Clock Input. This pin is the external oscillator
return for a crystal or resonator. See Oscillator Section.
D I/O or Port 0.3. See Port I/O Section for a complete description.
A In
A Out
XTAL2
Optional Analog Ground. See ADC0 Section for details.
D I/O or Port 0.2. See Port I/O Section for a complete description.
A In
A In
XTAL1
External VREF Input.
Internal VREF Output. External VREF decoupling capacitors
are recommended. See ADC0 Section for details.
D I/O or Port 0.1. See Port I/O Section for a complete description.
A In
G
AGND
Description
D I/O or Port 0.0. See Port I/O Section for a complete description.
A In
A In
A Out
VREF
P0.1
Type
External Convert Start Input for ADC0. See ADC0 section
for a complete description.
D I/O or Port 0.7. See Port I/O Section for a complete description.
A In
A Out IREF0 Output. See IREF Section for complete description.
Rev. 0.3
37
C8051F96x
Table 3.1. Pin Definitions for the C8051F96x (Continued)
Name
P1.0
Pin Numbers
DQFN76 TQFP80 QFN40
A36
72
36
PC0
P1.1
A35
70
35
67
34
XTAL3
P1.3
65
33
XTAL4
SmaRTClock Oscillator Crystal Input.
D I/O or Port 1.3. See Port I/O Section for a complete description.
A In
May also be used as NSS for SPI0.
A Out
SmaRTClock Oscillator Crystal Output.
P1.4
A31
60
31
D I/O or Port 1.4. See Port I/O Section for a complete description.
A In
P1.5
A30
57
30
D I/O or Port 1.5. See Port I/O Section for a complete description.
A In
P1.6
A29
56
29
D I/O or Port 1.6. See Port I/O Section for a complete description.
A In
P1.7
A28
54
28
D I/O or Port 1.7. See Port I/O Section for a complete description.
A In
P2.0
A27
53
27
D I/O or Port 2.0. See Port I/O Section for a complete description.
A In
P2.1
A26
49
26
D I/O or Port 2.1. See Port I/O Section for a complete description.
A In
P2.2
A25
48
25
D I/O or Port 2.2. See Port I/O Section for a complete description.
A In
P2.3
A24
47
24
D I/O or Port 2.3. See Port I/O Section for a complete description.
A In
P2.4
A23
46
23
D I/O or Port 2.4. See Port I/O Section for a complete description.
A In
COM0
P2.5
COM1
38
Pulse Counter 1.
D I/O or Port 1.2. See Port I/O Section for a complete description.
A In
May also be used as MOSI for SPI0.
A In
A33
Pulse Counter 0.
D I/O or Port 1.1. See Port I/O Section for a complete description.
A In
May also be used as MISO for SPI0.
D I/O
A34
Description
D I/O or Port 1.0. See Port I/O Section for a complete description.
May also be used as SCK for SPI0.
A In
D I/O
PC1
P1.2
Type
AO
A22
45
22
LCD Common Pin 0 (Backplane Driver)
D I/O or Port 2.5. See Port I/O Section for a complete description.
A In
AO
LCD Common Pin 1 (Backplane Driver)
Rev. 0.3
C8051F96x
Table 3.1. Pin Definitions for the C8051F96x (Continued)
Name
P2.6
Pin Numbers
DQFN76 TQFP80 QFN40
A21
43
21
COM2
P2.7
A20
41
20
39
19
LCD0
P3.1
38
18
LCD1
P3.2
36
17
LCD2
P3.3
34
16
LCD3
P3.4
32
15
LCD4
P3.5
28
14
LCD5
P3.6
26
13
LCD6
P3.7
LCD7
24
12
LCD Segment Pin 5
D I/O or Port 3.6. See Port I/O Section for a complete description.
A In
AO
A12
LCD Segment Pin 4
D I/O or Port 3.5. See Port I/O Section for a complete description.
A In
AO
A13
LCD Segment Pin 3
D I/O or Port 3.4. See Port I/O Section for a complete description.
A In
AO
A14
LCD Segment Pin 2
D I/O or Port 3.3. See Port I/O Section for a complete description.
A In
AO
A15
LCD Segment Pin 1
D I/O or Port 3.2. See Port I/O Section for a complete description.
A In
AO
A16
LCD Segment Pin 0
D I/O or Port 3.1. See Port I/O Section for a complete description.
A In
AO
A17
LCD Common Pin 3 (Backplane Driver)
D I/O or Port 3.0. See Port I/O Section for a complete description.
A In
AO
A18
LCD Common Pin 2 (Backplane Driver)
D I/O or Port 2.7. See Port I/O Section for a complete description.
A In
AO
A19
Description
D I/O or Port 2.6. See Port I/O Section for a complete description.
A In
AO
COM2
P3.0
Type
LCD Segment Pin 6
D I/O or Port 3.7. See Port I/O Section for a complete description.
A In
AO
LCD Segment Pin 7
Rev. 0.3
39
C8051F96x
Table 3.1. Pin Definitions for the C8051F96x (Continued)
Name
P4.0
Pin Numbers
DQFN76 TQFP80 QFN40
A11
23
LCD8
P4.1
B3
7
5
LCD10
P4.3
3
LCD11
P4.4
80
LCD12
P4.5
77
LCD13
P4.6
75
LCD14
P4.7
73
LCD15
P5.0
71
LCD16
P5.1
LCD17
40
69
LCD Segment Pin 15
D I/O or Port 5.0. See Port I/O Section for a complete description.
A In
AO
B24
LCD Segment Pin 14
D I/O or Port 4.7. See Port I/O Section for a complete description.
A In
AO
B25
LCD Segment Pin 13
D I/O or Port 4.6. See Port I/O Section for a complete description.
A In
AO
B26
LCD Segment Pin 12
D I/O or Port 4.5. See Port I/O Section for a complete description.
A In
AO
B27
LCD Segment Pin 11
D I/O or Port 4.4. See Port I/O Section for a complete description.
A In
AO
B28
LCD Segment Pin 10
D I/O or Port 4.3. See Port I/O Section for a complete description.
A In
AO
D1
LCD Segment Pin 9
D I/O or Port 4.2. See Port I/O Section for a complete description.
A In
AO
B1
LCD Segment Pin 8
D I/O or Port 4.1. See Port I/O Section for a complete description.
A In
AO
B2
Description
D I/O or Port 4.0. See Port I/O Section for a complete description.
A In
AO
LCD9
P4.2
11
Type
LCD Segment Pin 16
D I/O or Port 5.1. See Port I/O Section for a complete description.
A In
AO
LCD Segment Pin 17
Rev. 0.3
C8051F96x
Table 3.1. Pin Definitions for the C8051F96x (Continued)
Name
P5.2
Pin Numbers
DQFN76 TQFP80 QFN40
B23
63
LCD18
P5.3
B22
62
59
LCD20
P5.5
55
LCD21
P5.6
44
LCD22
P5.7
42
LCD23
P6.0
40
LCD24
P6.1
37
LCD25
P6.2
35
LCD26
P6.3
LCD27
33
LCD Segment Pin 25
D I/O or Port 6.2. See Port I/O Section for a complete description.
A In
AO
B11
LCD Segment Pin 24
D I/O or Port 6.1. See Port I/O Section for a complete description.
A In
AO
B12
LCD Segment Pin 23
D I/O or Port 6.0. See Port I/O Section for a complete description.
A In
AO
B13
LCD Segment Pin 22
D I/O or Port 5.7. See Port I/O Section for a complete description.
A In
AO
B14
LCD Segment Pin 21
D I/O or Port 5.6. See Port I/O Section for a complete description.
A In
AO
D3
LCD Segment Pin 20
D I/O or Port 5.5. See Port I/O Section for a complete description.
A In
AO
B15
LCD Segment Pin 19
D I/O or Port 5.4. See Port I/O Section for a complete description.
A In
AO
B21
LCD Segment Pin 18
D I/O or Port 5.3. See Port I/O Section for a complete description.
A In
AO
D4
Description
D I/O or Port 5.2. See Port I/O Section for a complete description.
A In
AO
LCD19
P5.4
Type
LCD Segment Pin 26
D I/O or Port 6.3. See Port I/O Section for a complete description.
A In
AO
LCD Segment Pin 27
Rev. 0.3
41
C8051F96x
Table 3.1. Pin Definitions for the C8051F96x (Continued)
Name
P6.4
Pin Numbers
DQFN76 TQFP80 QFN40
B10
29
LCD28
P6.5
B9
27
25
LCD30
P6.7
LCD31
42
18
LCD Segment Pin 29
D I/O or Port 6.6. See Port I/O Section for a complete description.
A In
AO
D2
LCD Segment Pin 28
D I/O or Port 6.5. See Port I/O Section for a complete description.
A In
AO
B8
Description
D I/O or Port 6.4. See Port I/O Section for a complete description.
A In
AO
LCD29
P6.6
Type
LCD Segment Pin 30
D I/O or Port 6.7. See Port I/O Section for a complete description.
A In
AO
LCD Segment Pin 31
Rev. 0.3
C8051F96x
P0.4/
TX
P4.4/
LCD12
D1
A40
P0.3/
XTAL2
A1
D5
NC
P0.2/
XTAL1
P0.1/
AGND
P0.0/
VREF
VBAT
A2
B27
A36
B26
A35
B25
A34
B24
A33
B23
A32
B22
P4.5/ P4.6/ P4.7/ P5.0/ P5.1/ P5.2/ P5.3/
LCD13 LCD14 LCD15 LCD16 LCD17 LCD18 LCD19
B2
P4.2/
LCD10
B3
P4.1/
LCD9
P1.4
A31
D4
P5.4/
LCD20
D8
A30
P1.5
A29
P1.6
A28
P1.7
A27
P2.0
A26
P2.1
A25
P2.2
A24
P2.3
A23
P2.4/
COM0
A22
P2.5/
COM1
D7
A21
P2.6/
COM2
A20
D3
P5.7/
LCD23
NC
P5.5/ B21
LCD21
NC B20
A4
NC B19
A5
C8051F960/2/4/6/8 - GM
VIO
NC B18
A6
NC B17
IND
A7
NC B16
GND
A8
B7
RST/
C2CK
B28
A37
P1.1/ P1.2/ P1.3/
VLCD
PC1 XTAL3 XTAL4
A3
B6
VDC
A38
B1
B5
GNDDC
A39
P4.3/
LCD11
B4
VBATDC
P0.5/ P0.6/ P0.7/ P1.0/
RX CNVSTR IREF0 PC0
A9
NC
P7.0/
C2D
A10
D6
P6.7/
LCD31
D2
A11
P5.6/
B15
LCD22
VIORF
P6.6/ P6.5/ P6.4/ P6.3/ P6.2/ P6.1/ P6.0/
LCD30 LCD29 LCD28 LCD27 LCD26 LCD25 LCD24
B8
A12
B9
A13
B10
A14
B11
A15
B12
A16
B13
A17
P4.0/ P3.7/ P3.6/ P3.5/ P3.4/ P3.3/ P3.2/
LCD8 LCD7 LCD6 LCD5 LCD4 LCD3 LCD2
B14
A18
A19
NC
P3.1/ P3.0/ P2.7/
LCD1 LCD0 COM3
Figure 3.1. DQFN-76 Pinout Diagram (Top View)
Rev. 0.3
43
C8051F96x
P0.4/
TX
40
P0.5/ P0.6/ P0.7/ P1.0/
RX CNVSTR IREF0 PC0
39
38
37
36
P1.1/ P1.2/ P1.3/
VLCD
PC1 XTAL3 XTAL4
35
34
33
32
31
P0.3/
XTAL2
1
30
P1.5
P0.2/
XTAL1
2
29
P1.6
P0.1/
AGND
3
28
P1.7
P0.0/
VREF
4
27
P2.0
VBAT/
VBATDC
/VIO
5
26
P2.1
IND
6
25
P2.2
GND/
GNDDC
7
24
P2.3
VDC/
VIORF
8
23
P2.4/
COM0
RST/
C2CK
9
22
P2.5/
COM1
P7.0/
C2D
10
21
P2.6/
COM2
C8051F961/3/5/7/9 - GM
11
12
13
14
15
16
17
P4.0/ P3.7/ P3.6/ P3.5/ P3.4/ P3.3/ P3.2/
LCD8 LCD7 LCD6 LCD5 LCD4 LCD3 LCD2
18
19
Rev. 0.3
20
P3.1/ P3.0/ P2.7/
LCD1 LCD0 COM3
Figure 3.2. QFN-40 Pinout Diagram (Top View)
44
P1.4
P4.4/LCD12
P0.4/TX
P0.5/RX
P4.5/LCD13
P0.6/CNVSTR
P4.6/LCD14
P0.7/IREF
P4.7/LCD15
P1.0/PC0
P5.0/LCD16
P1.1/PC1
P5.1/LCD17
GND
P1.2/XTAL3
GND
P1.3/XTAL4
GND
P5.2/LCD18
P5.3/LCD19
VLCD
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
C8051F96x
P0.3/XTAL2
1
60
P1.4
P0.2/XTAL1
2
59
P5.4/LCD20
P4.3/LCD11
3
58
NC
P0.1/AGND
4
57
P1.5
P4.2/LCD10
5
56
P1.6
P0.0/VREF
6
55
P5.5/LCD21
P4.1/LCD9
7
54
P1.7
VBAT
8
53
P2.0/SCK1
VIO
9
52
NC
VBATDC
10
51
NC
IND
11
50
NC
GNDDC
12
49
P2.1/MISO1
GND
13
48
P2.2/MOSI1
VDC
14
47
P2.3/NSS1
C8051F960/2/4/6/8 GQ
29
30
31
32
33
34
35
36
37
38
39
40
NC
NC
P3.4/LCD4
P6.3/LCD27
P3.3/LCD3
P6.2/LCD26
P3.2/LCD2
P6.1/LCD25
P3.1/LCD1
P3.0/LCD0
P6.0/LCD24
NC
P6.4/LCD28
P2.7/COM3
28
41
27
20
P3.5/LCD5
P5.7/LCD23
NC
P6.5/LCD29
P2.6/COM2
42
26
43
19
P3.6/LCD6
18
NC
25
P6.7/LCD31
24
P5.6/LCD22
P3.7/LCD7
44
P6.6/LCD30
17
23
P2.5/COM1
P7.0/C2D
22
P2.4/COM0
45
NC
46
16
P4.0/LCD8
15
21
VIORF
RST/C2CK
Figure 3.3. TQFP-80 Pinout Diagram (Top View)
Rev. 0.3
45
C8051F96x
3.1. DQFN-76 Package Specifications
3.1.1. Package Drawing
Figure 3.4. DQFN-76 Package Drawing
Table 3.2. DQFN-76 Package Dimensions
Dimension
Min
Typ
Max
Dimension
Min
Typ
Max
A
0.74
0.84
0.94
E2
3.00
3.10
3.20
b
0.25
0.30
0.35
aaa
—
—
0.10
bbb
—
—
0.10
ddd
—
—
0.08
eee
—
—
0.10
D
D2
6.00 BSC
3.00
3.10
e
0.50 BSC
E
6.00 BSC
3.20
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
46
Rev. 0.3
C8051F96x
3.1.2. Land Pattern
Figure 3.5. DQFN-76 Land Pattern
Table 3.3. DQFN-76 Land Pattern Dimensions
Dimension (mm)
Symbol
Typ
Max
C1
5.50
—
C2
5.50
—
e
0.50
—
f
—
0.35
P1
—
3.20
P2
—
3.20
Notes:
1. All feature sizes shown are at Maximum Material Condition
(MMC) and a card fabrication tolerance of 0.05 mm is assumed.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994
specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
Rev. 0.3
47
C8051F96x
3.1.3. Soldering Guidelines
3.1.3.1. Solder Mask Design
All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the
metal pad is to be 60 m minimum, all the way around the pad.
3.1.3.2. Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to
assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
4. A 2x2 array of 1.25 mm square openings on 1.60 mm pitch should be used for the center ground
pad.
3.1.3.3. Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
3.1.3.4. Inner via placement
1. Inner vias placement per Figure 3.6.
2. Reccomended via hole size is 0.150 mm (6 mil) laser drilled holes.
48
Rev. 0.3
C8051F96x
C1
v
h
C2
e
Detail A
28X
Detail A
Figure 3.6. Recomended Inner Via Placement
Table 3.4. Recomended Inner Via Placement Dimensions
Dimension
Min
Nominal
Max
C1
—
3.8
—
C2
—
3.8
—
v
—
0.35
—
h
—
0.150
—
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Via hole should be laser 0.150 mm (6 mil) laser drilled.
Rev. 0.3
49
C8051F96x
3.2. QFN-40 Package Specifications
Figure 3.7. Typical QFN-40 Package Drawing
Table 3.5. QFN-40 Package Dimensions
Dimension
Min
Typ
Max
Dimension
Min
Typ
Max
A
A1
b
D
D2
e
E
0.80
0.00
0.18
0.85
—
0.23
6.00 BSC
4.10
0.50 BSC
6.00 BSC
0.90
0.05
0.28
E2
L
L1
aaa
bbb
ddd
eee
4.00
0.35
—
—
—
—
—
4.10
0.40
—
—
—
—
—
4.20
0.45
0.10
0.10
0.10
0.05
0.08
4.00
4.20
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Solid State Outline MO-220, variation VJJD-5, except for
features A, D2, and E2 which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
50
Rev. 0.3
C8051F96x
Figure 3.8. QFN-40 Landing Diagram
Table 3.6. QFN-40 Landing Diagram Dimensions
Dimension
Min
Max
Dimension
Min
Max
C1
5.80
5.90
X2
4.10
4.20
C2
5.80
5.90
Y1
0.75
0.85
Y2
4.10
4.20
e
X1
0.50 BSC
0.15
0.25
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimension and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-SM-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is
calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and
the metal pad is to be 60 m minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to
assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
9. A 4x4 array of 0.80 mm square openings on a 1.05 mm pitch should be used for the center ground
pad.
Card Assembly
10. A No-Clean, Type-3 solder paste is recommended.
11. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
Rev. 0.3
51
C8051F96x
3.3. TQFP-80 Package Specifications
Figure 3.9. TQFP-80 Package Drawing
Table 3.7. TQFP-80 Package Dimensions
Dimension
Min
Nominal
Max
A
—
—
1.20
A1
0.05
—
0.15
A2
0.95
1.00
1.05
b
0.17
0.20
0.27
c
0.09
—
0.20
D
14.00 BSC
D1
12.00 BSC
e
0.50 BSC
E
14.00 BSC
E1
12.00 BSC
L
0.45
0.60
L1
52
1.00 Ref
Rev. 0.3
0.75
C8051F96x
Table 3.7. TQFP-80 Package Dimensions
Dimension
Min
Nominal
Max
0°
3.5°
7°
aaa
0.20
bbb
0.20
ccc
0.08
ddd
0.08
eee
0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This package outline conforms to JEDEC MS-026, variant ADD.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
Rev. 0.3
53
C8051F96x
Figure 3.10. TQFP80 Landing Diagram
Table 3.8. TQFP80 Landing Diagram Dimensions
Dimension
Min
Max
C1
13.30
13.40
C2
13.30
13.40
E
0.50 BSC
X
0.20
0.30
Y
1.40
1.50
Notes:
1. All feature sizes shown are in mm unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
54
Rev. 0.3
C8051F96x
3.3.1. Soldering Guidelines
3.3.1.1. Solder Mask Design
All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the
metal pad is to be 60 m minimum, all the way around the pad.
3.3.1.2. Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good
solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
4. A 2x2 array of 1.25 mm square openings on 1.60 mm pitch should be used for the center ground pad.
3.3.1.3. Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
Rev. 0.3
55
C8051F96x
4. Electrical Characteristics
Throughout the Electrical Characteristics chapter:
“VIO” refers to the VIO or VIORF Supply Voltage.
4.1. Absolute Maximum Specifications
Table 4.1. Absolute Maximum Ratings
Parameter
Conditions
Min
Typ
Max
Units
Ambient Temperature under Bias
–55
—
125
°C
Storage Temperature
–65
—
150
°C
Voltage on any VIO Port I/O Pin
(all Port I/O pins except P1.5/6/7
and P2.0/1/2/3) or RST with
respect to GND
–0.3
—
VIO + 2
V
Voltage on P1.5/6/7 or P2.0/1/2/3
with respect to GND.
–0.3
—
VIORF + 2
V
Voltage on VBAT, VBATDC, VIO,
or VIORF with respect to GND
–0.3
—
4.0
V
Maximum Total Current through
VBAT or GND
—
—
500
mA
Maximum Current through RST
or any Port Pin
—
—
100
mA
Maximum Total Current through
all Port Pins
—
—
200
mA
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the devices at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
56
Rev. 0.3
C8051F96x
4.2. Electrical Characteristics
Table 4.2. Global Electrical Characteristics
–40 to +85 °C, 25 MHz system clock unless otherwise specified.
Parameter
Conditions
Supply Voltage (VBAT)
Minimum RAM Data
Retention Voltage1
Min
Typ
1.8
Max
Units
3.8
V
—
—
1.4
0.3
—
0.5
V
SYSCLK (System Clock)2
0
—
25
MHz
TSYSH (SYSCLK High Time)
18
—
—
ns
TSYSL (SYSCLK Low Time)
18
—
—
ns
Specified Operating
Temperature Range
–40
—
+85
°C
Max
Units
Not in sleep mode
in sleep mode
Notes:
1. Based on device characterization data; Not production tested.
2. SYSCLK must be at least 32 kHz to enable debugging.
Table 4.3. Digital Supply Current at VBAT pin with DC-DC Converter Enabled
–40 to +85 °C, VBAT = 3.6V, VDC = 1.9 V, 24.5 MHz system clock unless otherwise specified.
Parameter
Conditions
Min
Typ
Digital Supply Current—CPU Active (Normal Mode, fetching instructions from flash, no external
load)
IBAT 1,2,3
VBAT= 3.0 V
—
4.1
—
mA
VBAT= 3.3 V
—
4.0
—
mA
VBAT= 3.6 V
—
3.8
—
mA
Digital Supply Current—CPU Inactive (Sleep Mode, sourcing current to external device)
IBAT1
sourcing 9 mA to external device
—
6.5
—
mA
sourcing 19 mA to external device
—
13
—
mA
Notes:
1. Based on device characterization data; Not production tested.
2. Digital Supply Current depends upon the particular code being executed. The values in this table are obtained
with the CPU executing a mix of instructions in two loops: djnz R1, $, followed by a loop that accesses an
SFR, and moves data around using the CPU (between accumulator and b-register). The supply current will
vary slightly based on the physical location of this code in flash. As described in the Flash Memory chapter, it
is best to align the jump addresses with a flash word address (byte location /4), to minimize flash accesses
and power consumption.
3. Includes oscillator and regulator supply current.
Rev. 0.3
57
C8051F96x
Table 4.4. Digital Supply Current with DC-DC Converter Disabled
–40 to +85 °C, 25 MHz system clock unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
Digital Supply Current - Active Mode, No Clock Gating (PCLKACT=0x0F)
(CPU Active, fetching instructions from flash)
IBAT 1, 2
IBAT Frequency
Sensitivity
1,3,4
VBAT = 1.8–3.8 V, F = 24.5 MHz
(includes precision oscillator current)
—
4.9
6.2
mA
VBAT = 1.8–3.8 V, F = 20 MHz
(includes low power oscillator current)
—
3.9
—
mA
VBAT = 1.8 V, F = 1 MHz
VBAT = 3.8 V, F = 1 MHz
(includes external oscillator/GPIO current)
—
—
175
190
—
—
µA
µA
VBAT = 1.8–3.8 V, F = 32.768 kHz
(includes SmaRTClock oscillator current)
—
85
—
µA
—
183
—
µA/MHz
VBAT = 1.8–3.8 V, T = 25 °C
Digital Supply Current - Active Mode, All Peripheral Clocks Disabled (PCLKACT=0x00)
(CPU Active, fetching instructions from flash)
IBAT 1, 2
IBAT Frequency
Sensitivity
1, 3
VBAT = 1.8–3.8 V, F = 24.5 MHz
(includes precision oscillator current)
—
3.9
--
mA
VBAT = 1.8–3.8 V, F = 20 MHz
(includes low power oscillator current)
—
3.1
—
mA
VBAT = 1.8 V, F = 1 MHz
VBAT = 3.8 V, F = 1 MHz
(includes external oscillator/GPIO current)
—
—
165
180
—
—
µA
µA
—
TBD
—
µA/MHz
VBAT = 1.8–3.8 V, T = 25 °C
Notes:
1. Active Current measure using typical code loop - Digital Supply Current depends upon the particular code
being executed. Digital Supply Current depends on the particular code being executed. The values in this
table are obtained with the CPU executing a mix of instructions in two loops: djnz R1, $, followed by a loop
that accesses an SFR, and moves data around using the CPU (between accumulator and b-register). The
supply current will vary slightly based on the physical location of this code in flash. As described in the Flash
Memory chapter, it is best to align the jump addresses with a flash word address (byte location /4), to
minimize flash accesses and power consumption.
2. Includes oscillator and regulator supply current.
3. Based on device characterization data; Not production tested.
4. Measured with one-shot enabled.
5. Low-Power Idle mode current measured with CLKMODE = 0x04, PCON = 0x01, and PCLKEN = 0x0F.
6. Using SmaRTClock osillator with external 32.768 kHz CMOS clock. Does not include crystal bias current.
7. Low-Power Idle mode current measured with CLKMODE = 0x04, PCON = 0x01, and PCLKEN = 0x00.
58
Rev. 0.3
C8051F96x
Table 4.4. Digital Supply Current with DC-DC Converter Disabled (Continued)
–40 to +85 °C, 25 MHz system clock unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
VBAT = 1.8–3.8 V, F = 24.5 MHz
(includes precision oscillator current)
—
3.5
—
mA
VBAT = 1.8–3.8 V, F = 20 MHz
(includes low power oscillator current)
—
2.6
—
mA
VBAT = 1.8 V, F = 1 MHz
VBAT = 3.8 V, F = 1 MHz
(includes external oscillator/GPIO current)
—
—
340
360
—
—
µA
µA
VBAT = 1.8–3.8 V, F = 32.768 kHz
(includes SmaRTClock oscillator current)
—
2305
—
µA
VBAT = 1.8–3.8 V, T = 25 °C
—
135
—
µA/MHz
Digital Supply Current—Idle Mode
(CPU Inactive, not Fetching Instructions from Flash)
IBAT2
IBAT Frequency Sensitivity3
Notes:
1. Active Current measure using typical code loop - Digital Supply Current depends upon the particular code
being executed. Digital Supply Current depends on the particular code being executed. The values in this
table are obtained with the CPU executing a mix of instructions in two loops: djnz R1, $, followed by a loop
that accesses an SFR, and moves data around using the CPU (between accumulator and b-register). The
supply current will vary slightly based on the physical location of this code in flash. As described in the Flash
Memory chapter, it is best to align the jump addresses with a flash word address (byte location /4), to
minimize flash accesses and power consumption.
2. Includes oscillator and regulator supply current.
3. Based on device characterization data; Not production tested.
4. Measured with one-shot enabled.
5. Low-Power Idle mode current measured with CLKMODE = 0x04, PCON = 0x01, and PCLKEN = 0x0F.
6. Using SmaRTClock osillator with external 32.768 kHz CMOS clock. Does not include crystal bias current.
7. Low-Power Idle mode current measured with CLKMODE = 0x04, PCON = 0x01, and PCLKEN = 0x00.
Rev. 0.3
59
C8051F96x
Table 4.4. Digital Supply Current with DC-DC Converter Disabled (Continued)
–40 to +85 °C, 25 MHz system clock unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
Digital Supply Current— Low Power Idle Mode, All peripheral clocks enabled (PCLKEN = 0x0F)
(CPU Inactive, not fetching instructions from flash)
IBAT2, 6
IBAT Frequency Sensitivity3
VBAT = 1.8–3.8 V, F = 24.5 MHz
(includes precision oscillator current)
—
1.5
1.9
mA
VBAT = 1.8–3.8 V, F = 20 MHz
(includes low power oscillator current)
—
1.07
—
mA
VBAT = 1.8 V, F = 1 MHz
VBAT = 3.8 V, F = 1 MHz
(includes external oscillator/GPIO current)
—
—
270
280
—
—
µA
µA
VBAT = 1.8–3.8 V, F = 32.768 kHz
(includes SmaRTClock oscillator current)
—
2325
—
µA
VBAT = 1.8–3.8 V, T = 25 °C
—
475
—
µA/MHz
Digital Supply Current— Low Power Idle Mode, All Peripheral Clocks Disabled (PCLKEN = 0x00)
(CPU Inactive, not fetching instructions from flash)
IBAT2, 7
IBAT Frequency Sensitivity3
VBAT = 1.8–3.8 V, F = 24.5 MHz
(includes precision oscillator current)
—
487
—
µA
VBAT = 1.8–3.8 V, F = 20 MHz
(includes low power oscillator current)
—
340
—
µA
VBAT = 1.8 V, F = 1 MHz
VBAT = 3.8 V, F = 1 MHz
(includes external oscillator/GPIO current)
—
—
90
94
—
—
µA
µA
VBAT = 1.8–3.8 V, T = 25 °C
—
115
—
µA/MHz
—
—
77
84
—
—
µA
Digital Supply Current—Suspend Mode
Digital Supply Current
(Suspend Mode)
VBAT = 1.8 V
VBAT = 3.8 V
Notes:
1. Active Current measure using typical code loop - Digital Supply Current depends upon the particular code
being executed. Digital Supply Current depends on the particular code being executed. The values in this
table are obtained with the CPU executing a mix of instructions in two loops: djnz R1, $, followed by a loop
that accesses an SFR, and moves data around using the CPU (between accumulator and b-register). The
supply current will vary slightly based on the physical location of this code in flash. As described in the Flash
Memory chapter, it is best to align the jump addresses with a flash word address (byte location /4), to
minimize flash accesses and power consumption.
2. Includes oscillator and regulator supply current.
3. Based on device characterization data; Not production tested.
4. Measured with one-shot enabled.
5. Low-Power Idle mode current measured with CLKMODE = 0x04, PCON = 0x01, and PCLKEN = 0x0F.
6. Using SmaRTClock osillator with external 32.768 kHz CMOS clock. Does not include crystal bias current.
7. Low-Power Idle mode current measured with CLKMODE = 0x04, PCON = 0x01, and PCLKEN = 0x00.
60
Rev. 0.3
C8051F96x
Table 4.4. Digital Supply Current with DC-DC Converter Disabled (Continued)
–40 to +85 °C, 25 MHz system clock unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
1.8 V, T = 25 °C, static LCD
3.0 V, T = 25 °C, static LCD
3.6 V, T = 25 °C, static LCD
—
—
—
0.4
0.6
0.8
—
—
—
µA
1.8 V, T = 25 °C, 2-Mux LCD
3.0 V, T = 25 °C, 2-Mux LCD
3.6 V, T = 25 °C, 2-Mux LCD
—
—
—
0.7
1.0
1.2
—
—
—
µA
1.8 V, T = 25 °C, 4-Mux LCD
3.0 V, T = 25 °C, 4-Mux LCD
3.6 V, T = 25 °C, 4-Mux LCD
—
—
—
0.7
1.1
1.2
—
—
—
µA
1.8 V, T = 25 °C, static LCD
3.0 V, T = 25 °C, static LCD
3.6 V, T = 25 °C, static LCD
—
—
—
0.8
1.1
1.4
—
—
—
µA
1.8 V, T = 25 °C, 2-Mux LCD
3.0 V, T = 25 °C, 2-Mux LCD
3.6 V, T = 25 °C, 2-Mux LCD
—
—
—
1.1
1.5
1.8
—
—
—
µA
1.8 V, T = 25 °C, 4-Mux LCD
3.0 V, T = 25 °C, 4-Mux LCD
3.6 V, T = 25 °C, 4-Mux LCD
—
—
—
1.2
1.6
1.9
—
—
—
µA
1.8 V, T = 25 °C, static LCD
1.8 V, T = 25 °C, 2-Mux LCD
1.8 V, T = 25 °C, 3-Mux LCD
1.8 V, T = 25 °C, 4-Mux LCD
—
—
—
—
1.2
1.6
1.8
2.0
—
—
—
—
µA
Digital Supply Current—Sleep Mode (LCD Enabled, RTC enabled)
Digital Supply Current
(Sleep Mode, SmaRTClock
running, internal LFO, LCD
Contrast Mode 1, charge
pump disabled, 60 Hz
refresh rate, driving 32 segment pins w/ no load)
Digital Supply Current
(Sleep Mode, SmaRTClock
running, 32.768 kHz Crystal, LCD Contrast Mode 1,
charge pump disabled,
60 Hz refresh rate, driving
32 segment pins w/ no load)
Digital Supply Current
(Sleep Mode, SmaRTClock
running, internal LFO, LCD
Contrast Mode 3 (2.7 V),
charge pump enabled,
60 Hz refresh rate, driving
32 segment pins w/ no load)
Notes:
1. Active Current measure using typical code loop - Digital Supply Current depends upon the particular code
being executed. Digital Supply Current depends on the particular code being executed. The values in this
table are obtained with the CPU executing a mix of instructions in two loops: djnz R1, $, followed by a loop
that accesses an SFR, and moves data around using the CPU (between accumulator and b-register). The
supply current will vary slightly based on the physical location of this code in flash. As described in the Flash
Memory chapter, it is best to align the jump addresses with a flash word address (byte location /4), to
minimize flash accesses and power consumption.
2. Includes oscillator and regulator supply current.
3. Based on device characterization data; Not production tested.
4. Measured with one-shot enabled.
5. Low-Power Idle mode current measured with CLKMODE = 0x04, PCON = 0x01, and PCLKEN = 0x0F.
6. Using SmaRTClock osillator with external 32.768 kHz CMOS clock. Does not include crystal bias current.
7. Low-Power Idle mode current measured with CLKMODE = 0x04, PCON = 0x01, and PCLKEN = 0x00.
Rev. 0.3
61
C8051F96x
Table 4.4. Digital Supply Current with DC-DC Converter Disabled (Continued)
–40 to +85 °C, 25 MHz system clock unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
Digital Supply Current
(Sleep Mode, SmaRTClock
running, 32.768 kHz Crystal, LCD Contrast Mode 3
(2.7 V), charge pump
enabled, 60 Hz refresh rate,
driving 32 segment pins w/
no load)
1.8 V, T = 25 °C, static LCD
1.8 V, T = 25 °C, 2-Mux LCD
1.8 V, T = 25 °C, 3-Mux LCD
1.8 V, T = 25 °C, 4-Mux LCD
—
—
—
—
1.3
1.8
1.8
2.0
—
—
—
—
µA
Notes:
1. Active Current measure using typical code loop - Digital Supply Current depends upon the particular code
being executed. Digital Supply Current depends on the particular code being executed. The values in this
table are obtained with the CPU executing a mix of instructions in two loops: djnz R1, $, followed by a loop
that accesses an SFR, and moves data around using the CPU (between accumulator and b-register). The
supply current will vary slightly based on the physical location of this code in flash. As described in the Flash
Memory chapter, it is best to align the jump addresses with a flash word address (byte location /4), to
minimize flash accesses and power consumption.
2. Includes oscillator and regulator supply current.
3. Based on device characterization data; Not production tested.
4. Measured with one-shot enabled.
5. Low-Power Idle mode current measured with CLKMODE = 0x04, PCON = 0x01, and PCLKEN = 0x0F.
6. Using SmaRTClock osillator with external 32.768 kHz CMOS clock. Does not include crystal bias current.
7. Low-Power Idle mode current measured with CLKMODE = 0x04, PCON = 0x01, and PCLKEN = 0x00.
62
Rev. 0.3
C8051F96x
Table 4.4. Digital Supply Current with DC-DC Converter Disabled (Continued)
–40 to +85 °C, 25 MHz system clock unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
Digital Supply Current—Sleep Mode (LCD disabled, RTC enabled)
Digital Supply Current
(Sleep Mode, SmaRTClock
running, 32.768 kHz crystal)
1.8 V, T = 25 °C
3.0 V, T = 25 °C
3.6 V, T = 25 °C
1.8 V, T = 85 °C
3.0 V, T = 85 °C
3.6 V, T = 85 °C
(includes SmaRTClock oscillator and
VBAT Supply Monitor)
Digital Supply Current
(Sleep Mode, SmaRTClock
running, internal LFO)
1.8 V, T = 25 °C
3.0 V, T = 25 °C
3.6 V, T = 25 °C
1.8 V, T = 85 °C
3.0 V, T = 85 °C
3.6 V, T = 85 °C
(includes SmaRTClock oscillator and
VBAT Supply Monitor)
—
—
—
—
—
—
0.40
0.60
0.70
1.56
2.38
2.79
—
—
—
—
—
—
µA
—
—
—
—
—
—
0.20
0.30
0.40
1.30
2.06
2.41
—
—
—
—
—
—
µA
1.8 V, T = 25 °C
3.0 V, T = 25 °C
3.6 V, T = 25 °C
1.8 V, T = 85 °C
3.0 V, T = 85 °C
3.6 V, T = 85 °C
(includes POR supply monitor)
—
—
—
—
—
—
0.05
0.07
0.11
1.13
1.83
2.25
—
—
—
—
—
—
µA
1.8 V, T = 25 °C
3.0 V, T = 25 °C
3.6 V, T = 25 °C
1.8 V, T = 85 °C
3.0 V, T = 85 °C
3.6 V, T = 85 °C
—
—
—
—
—
—
0.01
0.02
0.03
TBD
TBD
TBD
—
—
—
—
—
—
µA
Digital Supply Current—Sleep Mode (LCD disabled, RTC disabled)
Digital Supply Current
(Sleep Mode)
Digital Supply Current
(Sleep Mode, POR Supply
Monitor Disabled)
Notes:
1. Active Current measure using typical code loop - Digital Supply Current depends upon the particular code
being executed. Digital Supply Current depends on the particular code being executed. The values in this
table are obtained with the CPU executing a mix of instructions in two loops: djnz R1, $, followed by a loop
that accesses an SFR, and moves data around using the CPU (between accumulator and b-register). The
supply current will vary slightly based on the physical location of this code in flash. As described in the Flash
Memory chapter, it is best to align the jump addresses with a flash word address (byte location /4), to
minimize flash accesses and power consumption.
2. Includes oscillator and regulator supply current.
3. Based on device characterization data; Not production tested.
4. Measured with one-shot enabled.
5. Low-Power Idle mode current measured with CLKMODE = 0x04, PCON = 0x01, and PCLKEN = 0x0F.
6. Using SmaRTClock osillator with external 32.768 kHz CMOS clock. Does not include crystal bias current.
7. Low-Power Idle mode current measured with CLKMODE = 0x04, PCON = 0x01, and PCLKEN = 0x00.
Rev. 0.3
63
C8051F96x
7
6
Active
IDD (mA)
5
4
Idle
3
2
LP Idle (PCLKEN=0x0F)
1
LP Idle (PCLKEN=0x00)
0
0
5
10
15
20
25
Frequency (MHz)
Figure 4.1. Frequency Sensitivity (External CMOS Clock, 25°C)
64
Rev. 0.3
30
C8051F96x
Table 4.5. Port I/O DC Electrical Characteristics
VIO = 1.8 to 3.8 V, –40 to +85 °C unless otherwise specified.
Parameters
Conditions
Min
Typ
Max
IOH = –3 mA, Port I/O push-pull
VIO– 0.7
—
—
IOH = –10 µA, Port I/O push-pull
VIO – 0.1
—
—
Units
Output High Voltage High Drive Strength, PnDRV.n = 1
IOH = –10 mA, Port I/O push-pull
See Chart
V
Low Drive Strength, PnDRV.n = 0
VIO – 0.7
—
—
VIO – 0.1
—
—
—
See Chart
—
IOL = 8.5 mA
—
—
0.6
IOL = 10 µA
—
—
0.1
IOL = 25 mA
—
See Chart
—
IOH = –1 mA, Port I/O push-pull
IOH = –10 µA, Port I/O push-pull
IOH = –3 mA, Port I/O push-pull
Output Low Voltage High Drive Strength, PnDRV.n = 1
V
Low Drive Strength, PnDRV.n = 0
Input High Voltage
Input Low Voltage
IOL = 1.4 mA
—
—
0.6
IOL = 10 µA
—
—
0.1
IOL = 4 mA
—
See Chart
—
VBAT = 2.0 to 3.8 V
VIO – 0.6
—
—
V
VBAT = 1.8 to 2.0 V
0.7 x VIO
—
—
V
VBAT = 2.0 to 3.8 V
—
—
0.6
V
VBAT = 1.8 to 2.0 V
—
—
0.3 x VIO
V
Weak Pullup On, VIN = 0 V,
VBAT = 1.8 V
—
—
±1
—
4
—
Weak Pullup On, Vin = 0 V,
VBAT = 3.8 V
—
20
35
Weak Pullup Off
Input Leakage
Current
Rev. 0.3
µA
65
C8051F96x
Typical VOH (High Drive Mode)
Voltage
3.6
3.3
VDD = 3.6V
3
VDD = 3.0V
2.7
VDD = 2.4V
2.4
VDD = 1.8V
2.1
1.8
1.5
1.2
0.9
0
5
10
15
20
25
30
35
40
45
50
Load Current (mA)
Typical VOH (Low Drive Mode)
Voltage
3.6
3.3
VDD = 3.6V
3
VDD = 3.0V
2.7
VDD = 2.4V
2.4
VDD = 1.8V
2.1
1.8
1.5
1.2
0.9
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Load Current (mA)
Figure 4.2. Typical VOH Curves, 1.8–3.6 V
66
Rev. 0.3
C8051F96x
Typical VOL (High Drive Mode)
1.8
VDD = 3.6V
1.5
VDD = 3.0V
Voltage
1.2
VDD = 2.4V
VDD = 1.8V
0.9
0.6
0.3
0
-80
-70
-60
-50
-40
-30
-20
-10
0
Load Current (mA)
Typical VOL (Low Drive Mode)
1.8
VDD = 3.6V
1.5
VDD = 3.0V
Voltage
1.2
VDD = 2.4V
VDD = 1.8V
0.9
0.6
0.3
0
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
Load Current (mA)
Figure 4.3. Typical VOL Curves, 1.8–3.6 V
Rev. 0.3
67
C8051F96x
Table 4.6. Reset Electrical Characteristics
VBAT = 1.8 to 3.8 V, –40 to +85 °C unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
IOL = 1.4 mA,
—
—
0.6
V
VBAT = 2.0 to 3.8 V
VBAT –
0.6
—
—
V
VBAT = 1.8 to 2.0 V
0.7 x
VBAT
—
—
V
VBAT = 2.0 to 3.8 V
—
—
0.6
V
VBAT = 1.8 to 2.0 V
—
—
0.3 x
VBAT
V
RST Input Pullup Current
RST = 0.0 V, VBAT = 1.8 V
RST = 0.0 V, VBAT = 3.8 V
—
4
—
—
20
35
VBAT Monitor Threshold
(VRST)
Early Warning
Reset Trigger
(all power modes except Sleep)
1.8
1.85
1.9
1.7
1.75
1.8
VBAT Ramp from 0–1.8 V
—
—
3
RST Output Low Voltage
RST Input High Voltage
RST Input Low Voltage
VBAT Ramp Time for
Power On
µA
V
ms
POR Monitor Threshold
(VPOR)
Brownout Condition (VBAT Falling)
0.45
0.7
1.0
Recovery from Brownout (VBAT Rising)
—
1.75
—
Missing Clock Detector
Timeout
Time from last system clock rising edge
to reset initiation
100
650
1000
µs
Minimum System Clock w/
Missing Clock Detector
Enabled
System clock frequency which triggers
a missing clock detector timeout
—
7
10
kHz
Delay between release of any reset
source and code
execution at location 0x0000
—
10
—
µs
Minimum RST Low Time to
Generate a System Reset
15
—
—
µs
Digital/Analog Monitor
Turn-on Time
—
300
—
ns
Digital Monitor Supply
Current
—
14
—
µA
Analog Monitor Supply
Current
—
14
—
µA
Reset Time Delay
68
Rev. 0.3
V
C8051F96x
Table 4.7. Power Management Electrical Specifications
VBAT = 1.8 to 3.8 V, –40 to +85 °C unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
2
—
3
SYSCLKs
—
400
—
ns
—
2
—
µs
Idle Mode Wake-up Time
Suspend Mode Wake-up Time
CLKDIV = 0x00
Low Power or Precision Osc.
Sleep Mode Wake-up Time
Table 4.8. Flash Electrical Characteristics
VBAT = 1.8 to 3.8 V, –40 to +85 °C unless otherwise specified.,
Parameter
Flash Size
Conditions
C8051F960/1/2/3
C8051F964/5
C8051F966/7
C8051F968/9
Endurance
Erase Cycle Time
Write Cycle Time
Min
131072
65536
32768
16384
Typ
—
—
—
—
Max
—
—
—
—
20 k
100k
—
28
57
32
64
36
71
Units
bytes
bytes
bytes
bytes
Erase/Write
Cycles
ms
µs
Table 4.9. Internal Precision Oscillator Electrical Characteristics
VBAT = 1.8 to 3.8 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings.
Parameter
Oscillator Frequency
Oscillator Supply Current
(from VBAT)
Conditions
–40 to +85 °C,
VBAT = 1.8–3.8 V
25 °C; includes bias current
of 50 µA typical
Min
Typ
Max
Units
24
24.5
25
MHz
—
300*
—
µA
*Note: Does not include clock divider or clock tree supply current.
Table 4.10. Internal Low-Power Oscillator Electrical Characteristics
VBAT = 1.8 to 3.8 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings.
Parameter
Oscillator Frequency
Oscillator Supply Current
(from VBAT)
Conditions
–40 to +85 °C,
VBAT = 1.8–3.8 V
25 °C
No separate bias current
required
Min
Typ
Max
Units
18
20
22
MHz
—
100*
—
µA
*Note: Does not include clock divider or clock tree supply current.
Rev. 0.3
69
C8051F96x
Table 4.11. SmaRTClock Characteristics
VBAT = 1.8 to 3.8 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings.
Parameter
Oscillator Frequency (LFO)
Conditions
Min
13.1
Typ
16.4
Max
19.7
Units
kHz
Table 4.12. ADC0 Electrical Characteristics
VBAT = 1.8 to 3.8 V, VREF = 1.65 V (REFSL[1:0] = 11), –40 to +85 °C unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
12-bit mode
10-bit mode
12-bit mode1
10-bit mode
—
—
12
10
±1
±0.5
±3
±1
LSB
12-bit mode1
10-bit mode
—
—
±0.8
±0.5
±2
±1
LSB
12-bit mode
10-bit mode
12-bit mode2
10-bit mode
—
—
—
—
±