C8051T320-GQ

C8051T620/1/6/7 & C8051T320/1/2/3 Full Speed USB EPROM MCU Family Analog Peripherals - 10-Bit ADC (‘T620/6/7 and ‘T320/1 only) • Up to 500 ksps • Up to 21 external inputs • VREF from on-chip VREF, external pin, Internal 1.8 V Comparators - ation Integrated clock recovery; no external oscillator required for full speed or low speed Supports eight flexible endpoints 1 kB USB buffer memory Integrated transceiver; no external resistors required enhanced UART serial ports Four general purpose 16-bit counter/timers 16-Bit programmable counter array (PCA) with five capture/compare modules and enhanced PWM functionality fo r Clock Sources - Two internal oscillators: • 48 MHz: ±0.25% accuracy with clock recovery - • enabled. Supports all USB and UART modes 80/40/20/10 kHz low frequency, low power External oscillator: Crystal, RC, C, or CMOS Clock Can switch between clock sources on-the-fly; useful in power saving modes Package Options: - 5 x 5 mm QFN28 or QFN32 - 9 x 9 mm LQFP32 Temperature Range: –40 to +85 °C N ot R ec om Supply Voltage 1.8 to 5.25 V - On-chip LDO for internal core supply - Built-in supply voltage monitor 3072) Up to 64 kB byte-programmable EPROM code memory EPROM can be programmed from firmware running on the device Digital Peripherals - 25 Port I/O with high sink current capability - Hardware enhanced SPI™, SMBus™, and two m en de d - form; Complete development kit available On-chip debug circuitry facilitates full speed, nonintrusive in-system debug Provides breakpoints, single stepping, inspect/modify memory and registers - - On-Chip Debug - C8051F34A can be used as code development plat- - D Regulator or VDD Internal or external start of conversion source Built-in temperature sensor • Programmable hysteresis and response time • Configurable as interrupt or reset source • Low current ( 2.2 V VDD < 2.2 V –0.3 –0.3 — — Voltage on VPP with respect to VDD > 2.4 V GND during a programming operation –0.3 — Max Unit 125 °C 150 °C 5.8 VDD + 3.6 V V 7.0 V 10 s D Min Voltage on RST or any Port I/O Pin (except VPP during programming) with respect to GND Test Condition N ew Parameters es ig ns 7.1. Absolute Maximum Specifications VPP > 3.6 V and In-Application Programming enabled or a non-zero value written to EPCTL Voltage on VDD with respect to GND Regulator1 in Normal Mode Regulator1 in Bypass Mode fo r Duration of High-voltage on VPP pin (cumulative) — — 4.2 1.98 V V Maximum Total current through VDD, VIO, REGIN, or GND — — 500 mA Maximum output current sunk by RST or any Port pin — — 100 mA m en de d –0.3 –0.3 N ot R ec om Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Rev. 1.3 34 C8051T620/1/6/7 & C8051T320/1/2/3 7.2. Electrical Characteristics Table 7.2. Global Electrical Characteristics Parameters Test Condition Min Typ Max Unit 1.8 3.0 3.6 V VDD = 1.8 V, Clock = 48 MHz VDD = 1.8 V, Clock = 1 MHz — — 9.4 1.6 11.4 — mA mA VDD = 3.3 V, Clock = 48 MHz VDD = 3.3 V, Clock = 1 MHz — — VDD = 3.6 V, Clock = 48 MHz VDD = 3.6 V, Clock = 1 MHz VDD (Note 1) 11.0 1.7 13.7 — mA mA — — 11.1 1.8 13.8 — mA mA — — 4.6 0.4 5.5 — mA mA — — 5.1 0.45 5.9 — mA mA — — 5.1 0.5 6.0 — mA mA Oscillator not running (stop mode), Internal Regulator Off — .1 — μA Oscillator not running (stop or suspend mode), Internal Regulator On — 375 — μA Digital Supply Current for USB Module (USB Active Mode) VDD = 3.6 V, USB Clock = 48 MHz VDD = 3.3 V, USB Clock = 48 MHz — — 11.8 11.4 — — mA mA Digital Supply Current for USB Module (USB Suspend Mode) Oscillator not running; VDD monitor disabled. C8051T620/1/T320/1/2/3 C8051T626/7 — — 60 90 — — μA μA — 1.5 — V –40 — +85 °C 0 — 48 MHz Tsysl (SYSCLK low time) 9.75 — — ns Tsysh (SYSCLK high time) 9.75 — — ns Digital Supply Current with CPU Inactive (not accessing EPROM) VDD = 1.8 V, Clock = 48 MHz VDD = 1.8 V, Clock = 1 MHz fo r VDD = 3.3 V, Clock = 48 MHz VDD = 3.3 V, Clock = 1 MHz N ew D Digital Supply Current with CPU Active es ig ns –40 to +85 °C, 25 MHz system clock unless otherwise specified. om Digital Supply Current (shutdown) m en de d VDD = 3.6 V, Clock = 48 MHz VDD = 3.6 V, Clock = 1 MHz ec Digital Supply RAM Data Retention Voltage R Specified Operating Temperature Range N ot SYSCLK (System Clock) (Note 2) Notes: 1. VDD must be at least 3.0 V to support USB operation. 2. SYSCLK must be at least 32 kHz to enable debugging. 35 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 Table 7.3. Port I/O DC Electrical Characteristics Table 7.4. Reset Electrical Characteristics –40 to +85 °C unless otherwise specified. RST Output Low Voltage IOL = 8.5 mA, VDD = 1.8 V to 3.6 V m en de d RST Input High Voltage RST Input Low Voltage RST Input Pullup Current VDD POR Threshold (VRST) Missing Clock Detector Timeout Reset Time Delay Test Condition RST = 0.0 V Time from last system clock rising edge to reset initiation Delay between release of any reset source and code execution at location 0x0000 VDD = VRST – 0.1 v Unit — — — 0.1 0.4 — — 0.6 +1 50 V V V μA μA Typ Max Unit — — 0.6 V 0.75 x VIO — — 1.7 500 — — 25 1.75 625 — 0.6 50 1.8 750 V V μA V μs — — 60 μs 15 — — μs — — 50 20 — 30 μs μA D Typ — — VIO – 0.4 — — 0.6 — — — 25 Min V N ot R ec om Minimum RST Low Time to Generate a System Reset VDD Monitor Turn-on Time VDD Monitor Supply Current Max fo r Parameters Min VIO – 0.1 VIO – 0.2 — — — — 0.7 x VIO — –1 — N ew Parameters Test Condition Output High Voltage IOH = –10 μA, Port I/O push-pull IOH = –3 mA, Port I/O push-pull IOH = –10 mA, Port I/O push-pull Output Low Voltage IOL = 10 μA IOL = 8.5 mA IOL = 25 mA Input High Voltage Input Low Voltage Input Leakage Weak Pullup Off Current Weak Pullup On, VIN = 0 V es ig ns VDD = 1.8 to 3.6 V, VIO < VDD, –40 to +85 °C unless otherwise specified. Rev. 1.3 36 C8051T620/1/6/7 & C8051T320/1/2/3 Table 7.5. Internal Voltage Regulator Electrical Characteristics Test Condition Min Typ Max Unit 2.7 — 5.25 V 3.3 3.45 3.6 V — — 100 mA 2.5 — — V D Parameters Voltage Regulator (REG0) Input Voltage Range1, 3 Output Output Voltage (VDD)2 Current2 Output Current = 1 to 100 mA VBUS Detection Input Threshold Normal Mode (REG0MD = 0) Low Power Mode (REG0MD = 1) — — 83 38 98 52 μA Dropout Voltage (VDO)3 IDD = 1 mA IDD = 100 mA — — 1 100 — — mV/mA mV/mA 1.8 — 3.6 V Normal Mode (REG1MD = 0) — 320 425 μA Low Power Mode (REG1MD = 1) C8051T626/7/T320/1/2/3 C8051T626/7 — — 175 200 μA μA N ew Bias Current Voltage Regulator (REG1) Input Voltage Range m en de d fo r Bias Current es ig ns –40 to +85 °C unless otherwise specified. N ot R ec om Notes: 1. Input range specified for regulation. When an external regulator is used, should be tied to VDD. 2. Output current is total regulator output, including any current required by the C8051T620/1/6/7 & C8051T320/1/2/3. 3. The minimum input voltage is 2.7 V or VDD + VDO (max load), whichever is greater. 37 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 EPROM Size (Note 1) Write Cycle Time (per Byte) (Note 2) In-Application Programming Write Cycle Time (per Byte) (Note 3) Programming Voltage (VPP) Capacitor on VPP for Inapplication Programming C8051T620/1 & C8051T320/1/2/3 C8051T626 C8051T627 Min Typ 16384 65535 32768 105 — — — 155 — 37 — Capacitor on VPP = 4.7 μF and fully discharged Capacitor on VPP = 4.7 μF and initially charged to 3.3 V Max Unit es ig ns Test Condition 26 N ew Parameters D Table 7.6. EPROM Electrical Characteristics — — — 205 bytes bytes bytes μs — ms — ms 5.75 6.0 6.25 V — 4.7 — μF m en de d fo r Notes: 1. 512 bytes at location 0x3E00 to 0x3FFF are not available for program storage on the 16k devices, and 512 bytes at location 0xFE00 to 0xFFFF are not available for program storage on the C8051T626. 2. For devices with a Date Code prior to 1040, the programming time over the C2 interface is twice as long. See Section 18.1.1 for more information. 3. Duration of write time is largely dependent on VIO voltage, supply voltage, and residual charge on the VPP capacitor. The majority of the write time consists of charging the voltage on VPP to 6.0 V. These measurements include the VPP ramp time and VDD = VIO = 3.3 V Table 7.7. Internal High-Frequency Oscillator Electrical Characteristics VDD = 2.7 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings. om Parameters Oscillator Frequency Oscillator Supply Current (from VDD) ec Power Supply Sensitivity Temperature Sensitivity Test Condition IFCN = 11b 25 °C, VDD = 3.0 V, OSCICN.7 = 1, OSCICN.5 = 0 C8051T626/7/T320/1/2/3 C8051T626/7 Constant Temperature Constant Supply Min 47.28 Typ 48 Max 48.72 Unit MHz — — — — 900 925 ±0.02 ±20 1000 1100 — — μA μA %/V ppm/°C N ot R Note: Represents mean ±1 standard deviation. Rev. 1.3 38 C8051T620/1/6/7 & C8051T320/1/2/3 Table 7.8. Internal Low-Frequency Oscillator Electrical Characteristics VDD = 2.7 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings. Min 72 Typ 80 — — — — 3 4 ±0.09 ±30 Max 88 Unit kHz 6 7 — — μA μA %/V ppm/°C es ig ns Power Supply Sensitivity Temperature Sensitivity Test Condition OSCLD = 11b 25 °C, VDD = 3.0 V, OSCLCN.7 = 1 C8051T626/7/T320/1/2/3 C8051T626/7 Constant Temperature Constant Supply D Parameters Oscillator Frequency Oscillator Supply Current (from VDD) Note: Represents mean ±1 standard deviation. VDD = 2.7 to 3.6 V; TA = –40 to +85 °C unless otherwise specified. Test Condition Min .02 0 N ot R ec om m en de d fo r Parameters External Crystal Frequency External CMOS Oscillator Frequency N ew Table 7.9. External Oscillator Electrical Characteristics 39 Rev. 1.3 Typ — — Max 30 48 Unit MHz MHz C8051T620/1/6/7 & C8051T320/1/2/3 Table 7.10. ADC0 Electrical Characteristics VDD = 3.0 V, VREF = 2.40 V (REFSL=0), PGA Gain = 1, –40 to +85 °C unless otherwise specified. Test Condition Min Typ — — –2 –2 — 10 ±0.5 ±0.5 0 0 45 Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale Error Offset Temperature Coefficient Guaranteed Monotonic Unit ±1 ±1 +2 +2 — bits LSB LSB LSB LSB ppm/°C D DC Accuracy Max es ig ns Parameters Signal-to-Noise Plus Distortion Total Harmonic Distortion Spurious-Free Dynamic Range Up to the 5th harmonic SAR Conversion Clock Conversion Time in SAR Clocks Throughput Rate Analog Inputs m en de d Track/Hold Acquisition Time 10-bit Mode 8-bit Mode VDD > 2.0 V VDD < 2.0 V 56 — — 60 70 93 — — — dB dB dB — 13 11 300 2.0 — — — — — — — 8.00 — — — — 500 MHz clocks clocks ns μs ksps 0 0 — — VREF VIO V V — — — 5 3 5 — — — pF pF k — — — 600 640 –70 900 900 — μA μA dB fo r Conversion Rate N ew Dynamic performance (10 kHz sine-wave single-ended input, 1 dB below Full Scale, 500 ksps) ADC Input Voltage Range Single Ended (AIN+ – GND) Absolute Pin Voltage with respect to GND Sampling Capacitance Gain = 1x (AMP0GN0 = 1) Gain = 0.5x (AMP0GN0 = 0) Input Multiplexer Impedance om Power Specifications ec Power Supply Current (VDD supplied to ADC0) Operating Mode, 500 ksps C8051T626/7/T320/1/2/3 C8051T626/7 Power Supply Rejection N ot R Note: Represents one standard deviation from the mean. Rev. 1.3 40 C8051T620/1/6/7 & C8051T320/1/2/3 Table 7.11. Temperature Sensor Electrical Characteristics VDD = 3.0 V, –40 to +85 °C unless otherwise specified. Linearity Slope Min Typ — — — — ± 0.2 2.87 2.99 337 — — — 912 925 ± 11 C8051T626/7/T320/1/2/3 C8051T626/7 Slope Error* Offset Offset Error* Note: Represents one standard deviation from the mean. N ew Temp = 0 °C C8051T626/7/T320/1/2/3 C8051T626/7 Temp = 0 °C Max Unit — — — — °C mV/°C mV/°C μV/°C — — — mV mV mV es ig ns Test Condition D Parameters Table 7.12. Voltage Reference Electrical Characteristics VDD = 3.0 V; –40 to +85 °C unless otherwise specified. Test Condition Min Typ Max Unit 1.1 2.3 1.2 2.4 1.3 2.5 V VREF Short-Circuit Current — 4.5 6 mA VREF Temperature Coefficient — ±15 — ppm/°C Load = 0 to 200 μA to GND, 1.2 V Setting Load = 0 to 200 μA to GND, 2.4 V Setting — — 3.3 5.7 — — μV/μA μV/μA 4.7 μF tantalum, 0.1 μF ceramic bypass — 1.2 — ms 0.1 μF ceramic bypass — 25 — μs 4.7 μF tantalum, 0.1 μF ceramic bypass — 3.8 — ms 0.1 μF ceramic bypass — 90 — μs 1.2 V Setting — 160 — μV/V 2.4 V Setting — 330 — μV/V 0 — VDD V Sample Rate = 500 ksps; VREF = 3.0 V — 12 — μA REFBE = 1 or TEMPE = 1 — 75 100 μA Internal Reference (REFBE = 1) Load Regulation VREF Turn-on Time (1.2 V setting) om VREF Turn-on Time (2.4 V setting) 1.2 V Setting, 25 °C ambient 2.4 V Setting, 25 °C ambient m en de d Output Voltage fo r Parameters Power Supply Rejection ec External Reference (REFBE = 0) Input Voltage Range R Input Current Power Specifications N ot Reference Bias Generator 41 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 Table 7.13. Comparator Electrical Characteristics Response Time: Mode 2, Vcm* = 1.5 V Response Time: Mode 3, Vcm* = 1.5 V Input Capacitance Input Offset Voltage Power Supply om Power Supply Rejection Power-up Time Supply Current at DC ec CP0HYP1–0 = 00 CP0HYP1–0 = 01 CP0HYP1–0 = 10 CP0HYP1–0 = 11 CP0HYN1–0 = 00 CP0HYN1–0 = 01 CP0HYN1–0 = 10 CP0HYN1–0 = 11 m en de d Common-Mode Rejection Ratio Positive Hysteresis 1 Positive Hysteresis 2 Positive Hysteresis 3 Positive Hysteresis 4 Negative Hysteresis 1 Negative Hysteresis 2 Negative Hysteresis 3 Negative Hysteresis 4 Inverting or Non-Inverting Input Voltage Range Typ Mode 0 Mode 1 Mode 2 Mode 3 Max Unit — — — — — — — — — — 2 6 12 2 6 12 –0.25 240 240 400 400 650 1100 2000 5500 1.0 0 5 10 20 0 5 10 20 — — — — — — — — — 4 1 8 14 28 1 8 14 28 ns ns ns ns ns ns ns ns mV/V mV mV mV mV mV mV mV mV VDD + 0.25 V — –7.5 4 — — +7.5 pF mV — — — — — — 0.5 10 26 10 3 0.5 — — 50 20 6 2 mV/V μs μA μA μA μA D Response Time: Mode 1, Vcm* = 1.5 V CP0+ – CP0– = 100 mV CP0+ – CP0– = –100 mV CP0+ – CP0– = 100 mV CP0+ – CP0– = –100 mV CP0+ – CP0– = 100 mV CP0+ – CP0– = –100 mV CP0+ – CP0– = 100 mV CP0+ – CP0– = –100 mV Min N ew Response Time: Mode 0, Vcm* = 1.5 V Test Condition fo r Parameters es ig ns VDD = 3.0 V, –40 to +85 °C unless otherwise noted. N ot R Note: Vcm is the common-mode voltage on CP0+ and CP0–. Rev. 1.3 42 C8051T620/1/6/7 & C8051T320/1/2/3 Table 7.14. USB Transceiver Electrical Characteristics Min Typ Output High Voltage (VOH) 2.8 — Output Low Voltage (VOL) — — Output Crossover Point (VCRS) 1.3 — — — 36 36 — —  1.425 1.5 1.575 k 75 4 — — 300 20 ns 75 4 — — 300 20 ns fo r Parameters Test Condition es ig ns VDD = 3.0 V to 3.6 V, –40 to +85 °C unless otherwise specified. 0.2 — — V Differential Input Common Mode Range (VCM) 0.8 — 2.5 V Input Leakage Current (IL) Pullups Disabled — 0x0080). Figure 8.5 shows an example using left-justified data with the same comparison values. N ot R ec om Figure 8.4. ADC Window Compare Example: Right-Justified Data 54 Figure 8.5. ADC Window Compare Example: Left-Justified Data Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 8.5. ADC0 Analog Multiplexer (C8051T620/6/7 and C8051T320/1 Only) m en de d fo r N ew D es ig ns ADC0 on the C8051T620/6/7 and C8051T320/1 uses an analog input multiplexer to select the positive input to the ADC. Any of the following may be selected as the positive input: Port 1, 2, P3.0 and some Port 0 I/O pins, the on-chip temperature sensor, or the positive power supply (VDD). The ADC0 input channel is selected in the AMX0P register described in SFR Definition 8.9. Figure 8.6. ADC0 Multiplexer Block Diagram N ot R ec om Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be configured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for analog input, set to 0 the corresponding bit in register PnMDIN. To force the Crossbar to skip a Port pin, set to 1 the corresponding bit in register PnSKIP. See Section “22. Port Input/Output” on page 138 for more Port I/O configuration details. Rev. 1.3 55 C8051T620/1/6/7 & C8051T320/1/2/3 Bit 7 6 5 4 3 R R R Reset 1 0 0 R/W 0 SFR Address = 0xBB Bit Name 0 Function 7:5 Unused Read = 100b; Write = Don’t Care. 4:0 AMX0P[4:0] AMUX0 Positive Input Selection. fo r P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 (C8051T320/2 and C8051T620/6/7 Only) P2.5 (C8051T320/2 and C8051T620/6/7 Only) P2.6 (C8051T320/2 and C8051T620/6/7 Only) P2.7 (C8051T320/2 Only) P3.0 P0.0 P0.1 P0.4 P0.5 Reserved Temp Sensor VDD N ot R ec om m en de d 00000: 00001: 00010: 00011: 00100: 00101: 00110: 00111: 01000: 01001: 01010: 01011: 01100: 01101: 01110: 01111: 10000: 10001: 10010: 10011: 10100: 10101-11101: 11110: 11111: 0 N ew Type Rev. 1.3 1 0 0 0 D AMX0P[4:0] Name 56 2 es ig ns SFR Definition 8.9. AMX0P: AMUX0 Positive Channel Select C8051T620/1/6/7 & C8051T320/1/2/3 9. Temperature Sensor (C8051T620/6/7 and C8051T320/1 Only) om m en de d fo r N ew D es ig ns An on-chip temperature sensor is included on the C8051T620/6/7 and C8051T320/1 which can be directly accessed via the ADC multiplexer in single-ended configuration. To use the ADC to measure the temperature sensor, the ADC mux channel should be configured to connect to the temperature sensor. The temperature sensor transfer function is shown in Figure 9.1. The output voltage (VTEMP) is the positive ADC input when the ADC multiplexer is set correctly. The TEMPE bit in register REF0CN enables/disables the temperature sensor, as described in SFR Definition 10.1. While disabled, the temperature sensor defaults to a high impedance state and any ADC measurements performed on the sensor will result in meaningless data. Refer to Table 7.11 for the slope and offset parameters of the temperature sensor. N ot R ec Figure 9.1. Temperature Sensor Transfer Function Rev. 1.3 57 C8051T620/1/6/7 & C8051T320/1/2/3 9.1. Calibration es ig ns The uncalibrated temperature sensor output is extremely linear and suitable for relative temperature measurements (see Table 7.11 on page 41 for specifications). For absolute temperature measurements, offset and/or gain calibration is recommended. N ew D A single-point offset measurement of the temperature sensor is performed on each device during production test. The TOFFH and TOFFL calibration values represent the output of the ADC when reading the temperature sensor at 0 degrees Celsius, and using the internal regulator as a voltage reference. The TOFFH and TOFFL values can be read from EPROM memory and are located at 0x3FFB (TOFFH) and 0x3FFA (TOFFL). The temperature sensor offset information is left-justified, so TOFFH contains the 8 most-significant bits of the calibration value and TOFFL.7-6 contain the 2 least-significant bits of the calibration value, as shown in Figure 9.2. One LSB of this measurement is equivalent to one LSB of the ADC output under the measurement conditions. fo r Figure 9.2. TOFFH and TOFFL Calibration Value Orientation N ot R ec om m en de d Figure 9.3 shows the typical temperature sensor error assuming a 1-point calibration at 0 °C. Parameters that affect ADC measurement, in particular the voltage reference value, will also affect temperature measurement. 58 Figure 9.3. Temperature Sensor Error with 1-Point Calibration at 0 Celsius Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 10. Voltage Reference Options es ig ns The Voltage reference multiplexer for the ADC is configurable to use an externally connected voltage reference, the on-chip reference voltage generator routed to the VREF pin, the unregulated power supply voltage (VDD), or the regulated 1.8 V internal supply (see Figure 10.1). The REFSL bit in the Reference Control register (REF0CN, SFR Definition 10.1) selects the reference source for the ADC. For an external source or the on-chip reference, REFSL should be set to 0 to select the VREF pin. To use VDD as the reference source, REFSL should be set to 1. To override this selection and use the internal regulator (REG1) as the reference source, the REGOVR bit can be set to 1. N ew D The BIASE bit enables the internal voltage bias generator, which is used by many of the analog peripherals on the device. This bias is automatically enabled when any peripheral which requires it is enabled, and it does not need to be enabled manually. The bias generator may be enabled manually by writing a 1 to the BIASE bit in register REF0CN. The electrical specifications for the voltage reference circuit are given in Table 7.12. fo r The C8051T620/6/7 and C8051T320/1 devices also include an on-chip voltage reference circuit which consists of a 1.2 V, temperature stable bandgap voltage reference generator and a selectable-gain output buffer amplifier. The buffer is configured for 1x or 2x gain using the REFBGS bit in register REF0CN. On the 1x gain setting the output voltage is nominally 1.2 V, and on the 2x gain setting the output voltage is nominally 2.4 V. The on-chip voltage reference can be driven on the VREF pin by setting the REFBE bit in register REF0CN to a 1. The maximum load seen by the VREF pin must be less than 200 μA to GND. Bypass capacitors of 0.1 μF and 4.7 μF are recommended from the VREF pin to GND, and a minimum of 0.1uF is required. If the on-chip reference is not used, the REFBE bit should be cleared to 0. Electrical specifications for the on-chip voltage reference are given in Table 7.12. N ot R ec om m en de d Important Note about the VREF Pin: When using either an external voltage reference or the on-chip reference circuitry, the VREF pin should be configured as an analog pin and skipped by the Digital Crossbar. Refer to Section “22. Port Input/Output” on page 138 for the location of the VREF pin, as well as details of how to configure the pin in analog mode and to be skipped by the crossbar. Figure 10.1. Voltage Reference Functional Block Diagram Rev. 1.3 59 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 Name REFBGS Type R/W R Reset 0 0 5 4 3 2 REGOVR REFSL R R/W 0 0 SFR Address = 0xD1 Bit Name TEMPE BIASE REFBE R/W R/W R/W R/W 0 0 0 0 Function REFBGS Reference Buffer Gain Select. This bit selects between 1x and 2x gain for the on-chip voltage reference buffer. 0: 2x Gain 1: 1x Gain Unused Read = 00b; Write = don’t care. REGOVR Regulator Reference Override. This bit “overrides” the REFSL bit, and allows the internal regulator to be used as a reference source. 0: The voltage reference source is selected by the REFSL bit. 1: The internal regulator (REG1) is used as the voltage reference. m en de d fo r 6:5 4 0 N ew 7 1 D Bit es ig ns SFR Definition 10.1. REF0CN: Reference Control REFSL Voltage Reference Select. This bit selects the ADCs voltage reference. 0: VREF pin used as voltage reference. 1: VDD used as voltage reference. 2 TEMPE Temperature Sensor Enable Bit. 0: Internal Temperature Sensor off. 1: Internal Temperature Sensor on. 1 BIASE Internal Analog Bias Generator Enable Bit. 0: Internal Bias Generator off. 1: Internal Bias Generator on. 0 REFBE om 3 N ot R ec On-chip Reference Buffer Enable Bit. 0: On-chip Reference Buffer off. 1: On-chip Reference Buffer on. Internal voltage reference driven on the VREF pin. 60 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 11. Voltage Regulators (REG0 and REG1) es ig ns C8051T620/1/6/7 & C8051T320/1/2/3 devices include two internal voltage regulators: one regulates a voltage source on REGIN to 3.45 V (REG0), and the other regulates the internal core supply to 1.8 V from a VDD supply of 1.8 to 3.6 V (REG1). When enabled, the REG0 output appears on the VDD pin and can be used to power external devices. REG0 can be enabled/disabled by software using bit REG0DIS in register REG01CN (SFR Definition 11.1). REG1 has two power-saving modes built into the regulator to help reduce current consumption in low-power applications. These modes are accessed through the REG01CN register. Electrical characteristics for the on-chip regulators are specified in Table 7.5 on page 37. D Note that the VBUS signal must be connected to the VBUS pin when using the device in a USB network. The VBUS signal should only be connected to the REGIN pin when operating the device as a bus-powered function. REG0 configuration options are shown in Figure 11.1–Figure 11.4. 11.1. Voltage Regulator (REG0) N ew 11.1.1. Regulator Mode Selection REG0 offers a low power mode intended for use when the device is in suspend mode. In this low power mode, the REG0 output remains as specified; however the REG0 dynamic performance (response time) is degraded. See Table 7.5 for normal and low power mode supply current specifications. The REG0 mode selection is controlled via the REG0MD bit in register REG01CN. m en de d fo r 11.1.2. VBUS Detection When the USB Function Controller is used (see section Section “23. Universal Serial Bus Controller (USB0)” on page 160), the VBUS signal should be connected to the VBUS pin. The VBSTAT bit (register REG01CN) indicates the current logic level of the VBUS signal. If enabled, a VBUS interrupt will be generated when the VBUS signal has either a falling or rising edge. The VBUS interrupt is edge-sensitive, and has no associated interrupt pending flag. See Table 7.5 for VBUS input parameters. N ot R ec om Important Note: When USB is selected as a reset source, a system reset will be generated when a falling or rising edge occurs on the VBUS pin. See Section “20. Reset Sources” on page 121 for details on selecting USB as a reset source. Figure 11.1. REG0 Configuration: USB Bus-Powered Rev. 1.3 61 fo r N ew D es ig ns C8051T620/1/6/7 & C8051T320/1/2/3 ec om m en de d Figure 11.2. REG0 Configuration: USB Self-Powered N ot R Figure 11.3. REG0 Configuration: USB Self-Powered, Regulator Disabled 62 Rev. 1.3 N ew D es ig ns C8051T620/1/6/7 & C8051T320/1/2/3 N ot R ec om m en de d fo r Figure 11.4. REG0 Configuration: No USB Connection Rev. 1.3 63 C8051T620/1/6/7 & C8051T320/1/2/3 11.2. Voltage Regulator (REG1) es ig ns Under default conditions, the internal REG1 regulator will remain on when the device enters STOP mode. This allows any enabled reset source to generate a reset for the device and bring the device out of STOP mode. For additional power savings, the STOPCF bit can be used to shut down the regulator and the internal power network of the device when the part enters STOP mode. When STOPCF is set to 1, the RST pin and a full power cycle of the device are the only methods of generating a reset. REG1 offers an additional low power mode intended for use when the device is in suspend mode. This low power mode should not be used during normal operation or if the REG0 Voltage Regulator is disabled. See Table 7.5 for normal and low power mode supply current specifications. The REG1 mode selection is controlled via the REG1MD bit in register REG01CN. N ot R ec om m en de d fo r N ew D Important Note: At least 12 clock instructions must occur after placing REG1 in low power mode before the Internal High Frequency Oscillator is Suspended (OSCICN.5 = 1b). 64 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 3 2 Name REG0DIS VBSTAT Reserved REG0MD STOPCF Type R/W R R/W R/W Reset 0 0 0 0 SFR Address = 0xC9 Bit Name 1 0 Reserved REG1MD MPCE R/W R/W R/W R/W 0 0 0 0 Function D Bit es ig ns SFR Definition 11.1. REG01CN: Voltage Regulator Control 7 REG0DIS 6 VBSTAT VBUS Signal Status. This bit indicates whether the device is connected to a USB network. 0: VBUS signal currently absent (device not attached to USB network). 1: VBUS signal currently present (device attached to USB network). 5 4 Reserved REG0MD Must Write 0b. 3 STOPCF Stop Mode Configuration (REG1). This bit configures the REG1 regulator’s behavior when the device enters STOP mode. 0: REG1 Regulator is still active in STOP mode. Any enabled reset source will reset the device. 1: REG1 Regulator is shut down in STOP mode. Only the RST pin or power cycle can reset the device. 2 1 Reserved REG1MD Must Write 0b. fo r N ew Voltage Regulator (REG0) Disable. This bit enables or disables the REG0 Voltage Regulator. 0: Voltage Regulator Enabled. 1: Voltage Regulator Disabled. m en de d Voltage Regulator (REG0) Mode Select. This bit selects the Voltage Regulator mode for REG0. When REG0MD is set to 1, the REG0 voltage regulator operates in lower power (suspend) mode. 0: REG0 Voltage Regulator in normal mode. 1: REG0 Voltage Regulator in low power mode. ec om Voltage Regulator (REG1) Mode. This bit selects the Voltage Regulator mode for REG1. When REG1MD is set to 1, the REG1 voltage regulator operates in lower power mode. 0: REG1 Voltage Regulator in normal mode. 1: REG1 Voltage Regulator in low power mode. Note: This bit should not be set to '1' if the REG0 Voltage Regulator is disabled. MPCE N ot R 0 Memory Power Controller Enable. This bit can help the system save power at slower system clock frequencies (about 2.0 MHz or less) by automatically shutting down the EPROM memory between clocks when information is not being fetched from the EPROM memory. This bit has no effect when the prefetch engine is enabled. 0: Normal Mode - Memory power controller disabled (EPROM memory is always on). 1: Low Power Mode - Memory power controller enabled (EPROM turns on/off as needed). Note: If an external clock source is used with the Memory Power Controller enabled, and the clock frequency changes from slow (< 2.0 MHz) to fast (> 2.0 MHz), up to 20 clocks may be "skipped" to ensure that the EPROM power is stable before reading memory. Rev. 1.3 65 C8051T620/1/6/7 & C8051T320/1/2/3 12. CIP-51 Microcontroller es ig ns The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has a superset of all the peripherals included with a standard 8051. The CIP-51 also includes on-chip debug hardware (see description in Section 30), and interfaces directly with the analog and digital subsystems providing a complete data acquisition or control-system solution in a single integrated circuit.    Fully Compatible with MCS-51 Instruction Set 48 MIPS Peak Throughput with 48 MHz Clock 0 to 48 MHz Clock Frequency Extended Interrupt Handler     Reset Input Power Management Modes On-chip Debug Logic Program and Data Memory Security N ew  D The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals and functions to extend its capability (see Figure 12.1 for a block diagram). The CIP-51 includes the following features: N ot R ec om m en de d fo r Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more than eight system clock cycles. Figure 12.1. CIP-51 Block Diagram Rev. 1.3 66 C8051T620/1/6/7 & C8051T320/1/2/3 Clocks to Execute 1 2 2/4 3 3/5 4 5 Number of Instructions 26 50 5 10 7 5 2 es ig ns With the CIP-51's maximum system clock at 48 MHz, it has a peak throughput of 48 MIPS. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execution time. 4/6 6 8 1 2 1 D Programming and Debugging Support In-system programming of the EPROM program memory and communication with on-chip debug support logic is accomplished via the Silicon Labs 2-Wire Development Interface (C2). N ew The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware breakpoints, starting, stopping and single stepping through program execution (including interrupt service routines), examination of the program's call stack, and reading/writing the contents of registers and memory. This method of on-chip debugging is completely non-intrusive, requiring no RAM, Stack, timers, or other on-chip resources. C2 details can be found in Section “30. C2 Interface” on page 288. fo r The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs provides an integrated development environment (IDE) including editor, debugger and programmer. The IDE's debugger and programmer interface to the CIP-51 via the C2 interface to provide fast and efficient in-system device programming and debugging. Third party macro assemblers and C compilers are also available. m en de d 12.1. Instruction Set The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruction set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51 instructions are the binary and functional equivalent of their MCS-51™ counterparts, including opcodes, addressing modes and effect on PSW flags. However, instruction timing is different than that of the standard 8051. om 12.1.1. Instruction and CPU Timing In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based solely on clock cycle timing. All instruction timings are specified in terms of clock cycles. N ot R ec Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock cycles as there are program bytes in the instruction. Conditional branch instructions take one less clock cycle to complete when the branch is not taken as opposed to when the branch is taken. Table 12.1 is the CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock cycles for each instruction. 67 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 Table 12.1. CIP-51 Instruction Set Summary Description Bytes Add register to A ADD A, direct Add direct byte to A ADD A, @Ri Add indirect RAM to A ADD A, #data Add immediate to A ADDC A, Rn Add register to A with carry ADDC A, direct Add direct byte to A with carry ADDC A, @Ri Add indirect RAM to A with carry ADDC A, #data Add immediate to A with carry SUBB A, Rn 1 1 2 2 1 2 2 2 D Arithmetic Operations ADD A, Rn Clock Cycles es ig ns Mnemonic 1 2 2 1 2 2 2 Subtract register from A with borrow 1 1 SUBB A, direct Subtract direct byte from A with borrow 2 2 SUBB A, @Ri Subtract indirect RAM from A with borrow 1 2 SUBB A, #data Subtract immediate from A with borrow 2 2 INC A Increment A 1 1 INC Rn Increment register 1 1 Increment direct byte 2 2 Increment indirect RAM 1 2 Decrement A 1 1 Decrement register 1 1 Decrement direct byte 2 2 Decrement indirect RAM 1 2 Increment Data Pointer 1 1 Multiply A and B 1 4 Divide A by B 1 8 Decimal adjust A 1 1 ANL A, Rn AND Register to A 1 1 ANL A, direct AND direct byte to A 2 2 ANL A, @Ri AND indirect RAM to A 1 2 ANL A, #data AND immediate to A 2 2 ANL direct, A AND A to direct byte 2 2 ANL direct, #data AND immediate to direct byte 3 3 ORL A, Rn OR Register to A 1 1 INC @Ri DEC A DEC Rn DEC direct DEC @Ri MUL AB DIV AB ec DA A om INC DPTR fo r m en de d INC direct N ew 1 N ot R Logical Operations Rev. 1.3 68 C8051T620/1/6/7 & C8051T320/1/2/3 Table 12.1. CIP-51 Instruction Set Summary(Continued) Description 2 OR indirect RAM to A 1 2 ORL A, #data OR immediate to A 2 2 ORL direct, A OR A to direct byte 2 2 ORL direct, #data OR immediate to direct byte 3 3 XRL A, Rn Exclusive-OR Register to A 1 1 XRL A, direct Exclusive-OR direct byte to A 2 2 XRL A, @Ri Exclusive-OR indirect RAM to A 1 2 XRL A, #data Exclusive-OR immediate to A 2 2 XRL direct, A Exclusive-OR A to direct byte 2 2 XRL direct, #data Exclusive-OR immediate to direct byte 3 3 CLR A Clear A 1 1 CPL A Complement A 1 1 RL A Rotate A left 1 1 RLC A Rotate A left through Carry 1 1 Rotate A right 1 1 Rotate A right through Carry 1 1 Swap nibbles of A 1 1 Move Register to A 1 1 Move direct byte to A 2 2 Move indirect RAM to A 1 2 Move immediate to A 2 2 MOV Rn, A Move A to Register 1 1 MOV Rn, direct Move direct byte to Register 2 2 MOV Rn, #data Move immediate to Register 2 2 MOV direct, A Move A to direct byte 2 2 MOV direct, Rn Move Register to direct byte 2 2 MOV direct, direct Move direct byte to direct byte 3 3 MOV direct, @Ri Move indirect RAM to direct byte 2 2 MOV direct, #data Move immediate to direct byte 3 3 MOV @Ri, A Move A to indirect RAM 1 2 MOV @Ri, direct Move direct byte to indirect RAM 2 2 MOV @Ri, #data Move immediate to indirect RAM 2 2 RRC A SWAP A Data Transfer MOV A, Rn MOV A, direct MOV A, @Ri N ot R ec om MOV A, #data m en de d RR A 69 D ORL A, @Ri Clock Cycles 2 N ew OR direct byte to A fo r ORL A, direct Bytes es ig ns Mnemonic Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 Table 12.1. CIP-51 Instruction Set Summary(Continued) Description Bytes 3 3 MOVC A, @A+DPTR Move code byte relative DPTR to A 1 3 MOVC A, @A+PC Move code byte relative PC to A 1 3 MOVX A, @Ri Move external data (8-bit address) to A 1 3 MOVX @Ri, A Move A to external data (8-bit address) 1 3 MOVX A, @DPTR Move external data (16-bit address) to A 1 3 MOVX @DPTR, A Move A to external data (16-bit address) 1 3 PUSH direct Push direct byte onto stack 2 2 POP direct Pop direct byte from stack 2 2 XCH A, Rn Exchange Register with A 1 1 XCH A, direct Exchange direct byte with A 2 2 XCH A, @Ri Exchange indirect RAM with A 1 2 XCHD A, @Ri Exchange low nibble of indirect RAM with A 1 2 Clear Carry 1 1 Clear direct bit 2 2 Set Carry 1 1 Set direct bit 2 2 Complement Carry 1 1 Complement direct bit 2 2 AND direct bit to Carry 2 2 AND complement of direct bit to Carry 2 2 OR direct bit to carry 2 2 ORL C, /bit OR complement of direct bit to Carry 2 2 MOV C, bit Move direct bit to Carry 2 2 MOV bit, C Move Carry to direct bit 2 2 JC rel Jump if Carry is set 2 2/4 JNC rel Jump if Carry is not set 2 2/4 JB bit, rel Jump if direct bit is set 3 3/5 JNB bit, rel Jump if direct bit is not set 3 3/5 JBC bit, rel Jump if direct bit is set and clear bit 3 3/5 ACALL addr11 Absolute subroutine call 2 4 LCALL addr16 Long subroutine call 3 5 fo r Boolean Manipulation CLR bit SETB C SETB bit CPL C CPL bit ANL C, bit ANL C, /bit N ot R ec om ORL C, bit m en de d CLR C D Load DPTR with 16-bit constant N ew MOV DPTR, #data16 Clock Cycles es ig ns Mnemonic Program Branching Rev. 1.3 70 C8051T620/1/6/7 & C8051T320/1/2/3 Table 12.1. CIP-51 Instruction Set Summary(Continued) 6 Return from interrupt 1 6 AJMP addr11 Absolute jump 2 4 LJMP addr16 Long jump 3 5 SJMP rel Short jump (relative address) 2 4 JMP @A+DPTR Jump indirect relative to DPTR 1 4 JZ rel Jump if A equals zero 2 2/4 JNZ rel Jump if A does not equal zero 2 2/4 CJNE A, direct, rel Compare direct byte to A and jump if not equal 3 3/5 CJNE A, #data, rel Compare immediate to A and jump if not equal 3 3/5 CJNE Rn, #data, rel Compare immediate to Register and jump if not equal 3 3/5 CJNE @Ri, #data, rel Compare immediate to indirect and jump if not equal 3 4/6 DJNZ Rn, rel Decrement Register and jump if not zero 2 2/4 DJNZ direct, rel Decrement direct byte and jump if not zero 3 3/5 No operation 1 1 N ot R ec om NOP 71 Rev. 1.3 D RETI Clock Cycles 1 N ew Return from subroutine m en de d RET Bytes es ig ns Description fo r Mnemonic C8051T620/1/6/7 & C8051T320/1/2/3 Rn - Register R0–R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. es ig ns Notes on Registers, Operands and Addressing Modes: D rel - 8-bit, signed (two’s complement) offset relative to the first byte of the following instruction. Used by SJMP and all conditional jumps. N ew direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location (0x00– 0x7F) or an SFR (0x80–0xFF). #data - 8-bit constant #data16 - 16-bit constant fo r bit - Direct-accessed bit in Data RAM or SFR addr11 - 11-bit destination address used by ACALL and AJMP. The destination must be within the same 2 kB page of program memory as the first byte of the following instruction. m en de d addr16 - 16-bit destination address used by LCALL and LJMP. The destination may be anywhere within the 8 kB program memory space. N ot R ec om There is one unused opcode (0xA5) that performs the same function as NOP. All mnemonics copyrighted © Intel Corporation 1980. Rev. 1.3 72 C8051T620/1/6/7 & C8051T320/1/2/3 12.2. CIP-51 Register Descriptions SFR Definition 12.1. DPL: Data Pointer Low Byte 6 5 4 3 Name DPL[7:0] Type R/W Reset 0 0 0 0 0 0 0 3 2 1 0 0 0 0 0 Data Pointer Low. The DPL register is the low byte of the 16-bit DPTR. fo r DPL[7:0] 0 Function m en de d 7:0 1 0 SFR Address = 0x82 Bit Name 2 D 7 N ew Bit es ig ns Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should always be written to the value indicated in the SFR description. Future product versions may use these bits to implement new features in which case the reset value of the bit will be the indicated value, selecting the feature's default state. Detailed descriptions of the remaining SFRs are included in the sections of the datasheet associated with their corresponding system function. SFR Definition 12.2. DPH: Data Pointer High Byte Bit 7 6 Name 5 4 DPH[7:0] Type R/W Reset 0 0 0 0 DPH[7:0] Function Data Pointer High. The DPH register is the high byte of the 16-bit DPTR. N ot R ec 7:0 om SFR Address = 0x83 Bit Name 73 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 Name SP[7:0] Type R/W Reset 0 0 0 0 SFR Address = 0x81 Bit Name SP[7:0] 1 1 0 1 1 Stack Pointer. The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented before every PUSH operation. The SP register defaults to 0x07 after reset. 6 5 fo r 7 4 3 2 1 0 0 0 0 0 ACC[7:0] m en de d Name Type R/W Reset 0 0 0 0 SFR Address = 0xE0; Bit-Addressable Bit Name ACC[7:0] Function Accumulator. This register is the accumulator for arithmetic operations. om 7:0 0 Function SFR Definition 12.4. ACC: Accumulator Bit 2 N ew 7:0 3 D Bit es ig ns SFR Definition 12.3. SP: Stack Pointer ec SFR Definition 12.5. B: B Register 7 6 5 4 Name B[7:0] R Bit R/W Type N ot Reset 0 0 0 0 SFR Address = 0xF0; Bit-Addressable Bit Name 7:0 B[7:0] 3 2 1 0 0 0 0 0 Function B Register. This register serves as a second accumulator for certain arithmetic operations. Rev. 1.3 74 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 3 Name CY AC F0 RS[1:0] OV Type R/W R/W R/W R/W R/W Reset 0 0 0 0 SFR Address = 0xD0; Bit-Addressable Bit Name 0 Function 2 0 1 0 F1 PARITY R/W R 0 0 D Bit es ig ns SFR Definition 12.6. PSW: Program Status Word CY Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow (subtraction). It is cleared to logic 0 by all other arithmetic operations. 6 AC Auxiliary Carry Flag. This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow from (subtraction) the high order nibble. It is cleared to logic 0 by all other arithmetic operations. 5 F0 User Flag 0. This is a bit-addressable, general purpose flag for use under software control. 4:3 RS[1:0] 2 OV fo r N ew 7 m en de d Register Bank Select. These bits select which register bank is used during register accesses. 00: Bank 0, Addresses 0x00-0x07 01: Bank 1, Addresses 0x08-0x0F 10: Bank 2, Addresses 0x10-0x17 11: Bank 3, Addresses 0x18-0x1F Overflow Flag. This bit is set to 1 under the following circumstances: An ADD, ADDC, or SUBB instruction causes a sign-change overflow. MUL instruction results in an overflow (result is greater than 255). A DIV instruction causes a divide-by-zero condition. om A ec The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other cases. F1 R 1 N ot 0 75 PARITY User Flag 1. This is a bit-addressable, general purpose flag for use under software control. Parity Flag. This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum is even. Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 13. Prefetch Engine es ig ns The C8051T620/1/6/7 & C8051T320/1/2/3 family of devices incorporate a 2-byte prefetch engine. Because the access time of the EPROM memory is 40 ns, and the minimum instruction time is roughly 20 ns, the prefetch engine is necessary for code execution above 25 MHz. When operating at speeds greater than 25 MHz, the prefetch engine must be enabled by setting PFE0CN.PFEN to 1. Instructions are read from EPROM memory two bytes at a time by the prefetch engine and given to the CIP-51 processor core to execute. When running linear code (code without any jumps or branches), the prefetch engine allows instructions to be executed at full speed. When a code branch occurs, the processor may be stalled for up to two clock cycles while the next set of code bytes is retrieved from EPROM memory. D Note: The prefetch engine should be disabled when the device is in suspend mode to save power. Bit 7 6 5 N ew SFR Definition 13.1. PFE0CN: Prefetch Engine Control 4 PFEN Name R R R/W R Reset 0 0 1 0 SFR Address = 0xAF Bit Name 4:0 Unused 0 R R R R 0 0 0 0 Function m en de d Unused PFEN 1 Read = 00b, Write = don’t care. Prefetch Enable. This bit enables the prefetch engine. 0: Prefetch engine is disabled. 1: Prefetch engine is enabled. Read = 00000b. Write = don’t care. N ot R ec om 7:6 5 2 fo r Type 3 Rev. 1.3 76 C8051T620/1/6/7 & C8051T320/1/2/3 14. Comparator0 and Comparator1 es ig ns C8051T620/1/6/7 & C8051T320/1/2/3 devices include two on-chip programmable voltage comparators: Comparator0 is shown in Figure 14.1, Comparator1 is shown in Figure 14.2. The two comparators operate identically with the following exceptions: (1) Their input selections differ as described in Section “14.1. Comparator Multiplexers” on page 84; (2) Comparator0 can be used as a reset source. D The Comparators offer programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0 or CP1), or an asynchronous “raw” output (CP0A or CP1A). The asynchronous signals are available even when the system clock is not active. This allows the Comparators to operate and generate an output with the device in STOP mode. When assigned to a Port pin, the Comparator outputs may be configured as open drain or push-pull (see Section “22.4. Port I/O Initialization” on page 146). Comparator0 may also be used as a reset source (see Section “20.5. Comparator0 Reset” on page 124). Figure 14.1. Comparator0 Functional Block Diagram N ot R ec om m en de d fo r N ew The Comparator inputs are selected by the comparator input multiplexers, as detailed in Section “14.1. Comparator Multiplexers” on page 84. Rev. 1.3 77 m en de d fo r N ew D es ig ns C8051T620/1/6/7 & C8051T320/1/2/3 Figure 14.2. Comparator1 Functional Block Diagram om The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin. When routed to a Port pin, the Comparator output is available asynchronous or synchronous to the system clock; the asynchronous output is available even in STOP mode (with no system clock active). When disabled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state, and the power supply to the comparator is turned off. See Section “22.3. Priority Crossbar Decoder” on page 142 for details on configuring Comparator outputs via the digital Crossbar. Comparator inputs can be externally driven from –0.25 V to (VDD) + 0.25 V without damage or upset. The complete Comparator electrical specifications are given in Section “7. Electrical Characteristics” on page 34. N ot R ec The Comparator response time may be configured in software via the CPTnMD registers (see SFR Definition 14.2 and SFR Definition 14.4). Selecting a longer response time reduces the Comparator supply current. 78 Rev. 1.3 m en de d fo r N ew D es ig ns C8051T620/1/6/7 & C8051T320/1/2/3 Figure 14.3. Comparator Hysteresis Plot The Comparator hysteresis is software-programmable via its Comparator Control register CPTnCN (for n = 0 or 1). The user can program both the amount of hysteresis voltage (referred to the input voltage) and the positive and negative-going symmetry of this hysteresis around the threshold voltage. om The Comparator hysteresis is programmed using Bits3–0 in the Comparator Control Register CPTnCN (shown in SFR Definition 14.1). The amount of negative hysteresis voltage is determined by the settings of the CPnHYN bits. Settings of 20, 10 or 5 mV of nominal negative hysteresis can be programmed, or negative hysteresis can be disabled. In a similar way, the amount of positive hysteresis is determined by the setting the CPnHYP bits. R ec Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Interrupt enable and priority control, see Section “17.1. MCU Interrupt Sources and Vectors” on page 102). The CPnFIF flag is set to logic 1 upon a Comparator falling-edge occurrence, and the CPnRIF flag is set to logic 1 upon the Comparator rising-edge occurrence. Once set, these bits remain set until cleared by software. The Comparator rising-edge interrupt mask is enabled by setting CPnRIE to a logic 1. The Comparator falling-edge interrupt mask is enabled by setting CPnFIE to a logic 1. N ot The output state of the Comparator can be obtained at any time by reading the CPnOUT bit. The Comparator is enabled by setting the CPnEN bit to logic 1, and is disabled by clearing this bit to logic 0. Note that false rising edges and falling edges can be detected when the comparator is first powered on or if changes are made to the hysteresis or response time control bits. Therefore, it is recommended that the rising-edge and falling-edge flags be explicitly cleared to logic 0 a short time after the comparator is enabled or its mode bits have been changed. Rev. 1.3 79 C8051T620/1/6/7 & C8051T320/1/2/3 Bit 7 6 5 4 Name CP0EN CP0OUT CP0RIF CP0FIF CP0HYP[1:0] Type R/W R R/W R/W R/W Reset 0 0 0 0 2 0 Function 1 0 CP0HYN[1:0] R/W 0 0 0 D SFR Address = 0x9B Bit Name 3 es ig ns SFR Definition 14.1. CPT0CN: Comparator0 Control CP0EN 6 CP0OUT Comparator0 Output State Flag. 0: Voltage on CP0+ < CP0–. 1: Voltage on CP0+ > CP0–. 5 CP0RIF Comparator0 Rising-Edge Flag. Must be cleared by software. 0: No Comparator0 Rising Edge has occurred since this flag was last cleared. 1: Comparator0 Rising Edge has occurred. 4 CP0FIF m en de d fo r Comparator0 Enable Bit. 0: Comparator0 Disabled. 1: Comparator0 Enabled. N ew 7 Comparator0 Falling-Edge Flag. Must be cleared by software. 0: No Comparator0 Falling-Edge has occurred since this flag was last cleared. 1: Comparator0 Falling-Edge has occurred. 3:2 CP0HYP[1:0] Comparator0 Positive Hysteresis Control Bits. 00: Positive Hysteresis Disabled. 01: Positive Hysteresis = 5 mV. 10: Positive Hysteresis = 10 mV. 11: Positive Hysteresis = 20 mV. N ot R ec om 1:0 CP0HYN[1:0] Comparator0 Negative Hysteresis Control Bits. 00: Negative Hysteresis Disabled. 01: Negative Hysteresis = 5 mV. 10: Negative Hysteresis = 10 mV. 11: Negative Hysteresis = 20 mV. 80 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 Name 5 4 CP0RIE CP0FIE 3 2 R R R/W R/W R R Reset 0 0 0 0 0 0 4 CP0FIE 0 Comparator0 Rising-Edge Interrupt Enable. 0: Comparator0 Rising-edge interrupt disabled. 1: Comparator0 Rising-edge interrupt enabled. Comparator0 Falling-Edge Interrupt Enable. 0: Comparator0 Falling-edge interrupt disabled. 1: Comparator0 Falling-edge interrupt enabled. Unused Read = 00b, Write = don’t care. CP0MD[1:0] Comparator0 Mode Select. These bits affect the response time and power consumption for Comparator0. 00: Mode 0 (Fastest Response Time, Highest Power Consumption) 01: Mode 1 10: Mode 2 11: Mode 3 (Slowest Response Time, Lowest Power Consumption) N ot R ec om m en de d 3:2 1:0 Read = 00b, Write = Don’t Care. 1 N ew Unused CP0RIE Function R/W fo r 7:6 5 0 CP0MD[1:0] Type SFR Address = 0x9D Bit Name 1 D Bit es ig ns SFR Definition 14.2. CPT0MD: Comparator0 Mode Selection Rev. 1.3 81 C8051T620/1/6/7 & C8051T320/1/2/3 Bit 7 6 5 4 Name CP1EN CP1OUT CP1RIF CP1FIF CP1HYP[1:0] Type R/W R R/W R/W R/W Reset 0 0 0 0 2 0 Function 1 0 CP1HYN[1:0] R/W 0 0 0 D SFR Address = 0x9A Bit Name 3 es ig ns SFR Definition 14.3. CPT1CN: Comparator1 Control CP1EN 6 CP1OUT Comparator1 Output State Flag. 0: Voltage on CP1+ < CP0–. 1: Voltage on CP1+ > CP0–. 5 CP1RIF Comparator1 Rising-Edge Flag. Must be cleared by software. 0: No Comparator1 Rising Edge has occurred since this flag was last cleared. 1: Comparator1 Rising Edge has occurred. 4 CP1FIF m en de d fo r Comparator1 Enable Bit. 0: Comparator1 Disabled. 1: Comparator1 Enabled. N ew 7 Comparator1 Falling-Edge Flag. Must be cleared by software. 0: No Comparator1 Falling-Edge has occurred since this flag was last cleared. 1: Comparator1 Falling-Edge has occurred. 3:2 CP1HYP[1:0] Comparator1 Positive Hysteresis Control Bits. 00: Positive Hysteresis Disabled. 01: Positive Hysteresis = 5 mV. 10: Positive Hysteresis = 10 mV. 11: Positive Hysteresis = 20 mV. N ot R ec om 1:0 CP1HYN[1:0] Comparator1 Negative Hysteresis Control Bits. 00: Negative Hysteresis Disabled. 01: Negative Hysteresis = 5 mV. 10: Negative Hysteresis = 10 mV. 11: Negative Hysteresis = 20 mV. 82 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 Name 5 4 CP1RIE CP1FIE 3 2 R R R/W R/W R R Reset 0 0 0 0 0 0 Function Unused CP1RIE Read = 00b, Write = Don’t Care. 4 CP1FIE Comparator1 Falling-Edge Interrupt Enable. 0: Comparator1 Falling-edge interrupt disabled. 1: Comparator1 Falling-edge interrupt enabled. R/W 1 0 N ew 7:6 5 fo r Comparator1 Rising-Edge Interrupt Enable. 0: Comparator1 Rising-edge interrupt disabled. 1: Comparator1 Rising-edge interrupt enabled. Unused Read = 00b, Write = don’t care. CP1MD[1:0] Comparator1 Mode Select. These bits affect the response time and power consumption for Comparator1. 00: Mode 0 (Fastest Response Time, Highest Power Consumption) 01: Mode 1 10: Mode 2 11: Mode 3 (Slowest Response Time, Lowest Power Consumption) N ot R ec om m en de d 3:2 1:0 0 CP1MD[1:0] Type SFR Address = 0x9C Bit Name 1 D Bit es ig ns SFR Definition 14.4. CPT1MD: Comparator1 Mode Selection Rev. 1.3 83 C8051T620/1/6/7 & C8051T320/1/2/3 14.1. Comparator Multiplexers es ig ns C8051T620/1/6/7 & C8051T320/1/2/3 devices include an analog input multiplexer to connect Port I/O pins to the comparator inputs. The Comparator inputs are selected in the CPTnMX registers (SFR Definition 14.5 and SFR Definition 14.6). The CMXnP2–CMXnP0 bits select the Comparator positive input; the CMXnN2–CMXnN0 bits select the Comparator negative input. om m en de d fo r N ew D Important Note About Comparator Inputs: The Port pins selected as comparator inputs should be configured as analog inputs in their associated Port configuration register, and configured to be skipped by the Crossbar (for details on Port configuration, see Section “22.6. Special Function Registers for Accessing and Configuring Port I/O” on page 152). N ot R ec Figure 14.4. Comparator Input Multiplexer Block Diagram Rev. 1.3 84 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 Type R Reset 0 R/W 0 0 R 0 Function Read = 0b; Write = don’t care. CMX0P[2:0] Comparator0 Positive Input MUX Selection. P1.0 P1.4 P2.0 P2.4 P0.0 RESERVED N ot R ec om 0000: 0001: 0010: 0011: 0100: 101–111: 85 0 Rev. 1.3 R/W 0 0 N ew fo r Unused P1.1 P1.5 P2.1 P2.5 P0.1 RESERVED m en de d 2:0 0 Unused Read = 0b; Write = don’t care. CMX0N[2:0] Comparator0 Negative Input MUX Selection. 000: 001: 010: 011: 100: 101-111: 1 CMX0P[2:0] SFR Address = 0x9F Bit Name 3 2 CMX0N[2:0] Name 7 6:4 3 D Bit es ig ns SFR Definition 14.5. CPT0MX: Comparator0 MUX Selection 0 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 Type R Reset 0 R/W 0 0 1 0 CMX1P[2:0] R 0 SFR Address = 0x9E Bit Name 0 Function 0 0 fo r 000: P1.3 001: P1.7 010: P2.3 011: RESERVED 100: P0.5 101-111: RESERVED Read = 0b; Write = don’t care. 0 N ew Unused Read = 0b; Write = don’t care. CMX1N[2:0] Comparator1 Negative Input MUX Selection. R/W Unused CMX1P[2:0] Comparator1 Positive Input MUX Selection. m en de d 3 2:0 2 CMX1N[2:0] Name 7 6:4 3 D Bit es ig ns SFR Definition 14.6. CPT1MX: Comparator1 MUX Selection P1.2 P1.6 P2.2 RESERVED P0.4 RESERVED N ot R ec om 000: 001: 010: 011: 100: 101-111: Rev. 1.3 86 C8051T620/1/6/7 & C8051T320/1/2/3 15. Memory Organization m en de d fo r N ew D es ig ns The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space but are accessed via different instruction types. The memory organization of the C8051T620/1/6/7 & C8051T320/1/2/3 device family is shown in Figure 15.1 N ot R ec om Figure 15.1. C8051T620/1 and C8051T320/1/2/3 Memory Map Rev. 1.3 87 m en de d fo r N ew D es ig ns C8051T620/1/6/7 & C8051T320/1/2/3 Figure 15.2. C8051T626/7 Memory Map 15.1. Program Memory N ot R ec om The CIP-51 core has a 64 kB program memory space. The C8051T620/1/6/7 & C8051T320/1/2/3 implements up to 65535 bytes of this program memory space as in-system byte-programmable EPROM. Refer to Table 2.1 on page 21 or Figure 15.1 for additional details on program memory size. Figure 15.3 shows the program memory maps for C8051T620/1/6/7 & C8051T320/1/2/3 devices. 88 Rev. 1.3 N ew D es ig ns C8051T620/1/6/7 & C8051T320/1/2/3 fo r Figure 15.3. Program Memory Map Program memory is read-only from within firmware. Individual program memory bytes can be read using the MOVC instruction. This facilitates the use of byte-programmable EPROM space for constant storage. ec om m en de d 15.1.1. Derivative ID To distinguish between individual derivatives in the C8051T620/1/6/7 & C8051T320/1/2/3 device family, the Derivative ID is located at the address indicated in Figure 15.3 in EPROM memory. The Derivative ID for the devices in the C8051T620/1/6/7 & C8051T320/1/2/3 are as follows: Device C8051T620 C8051T621 C8051T626 C8051T627 C8051T320 C8051T321 C8051T322 C8051T323 Derivative ID 0xD0 0xD3 0xD6 0xD7 0xD1 0xD2 0xD4 0xD5 N ot R 15.1.2. Temperature Offset Calibration The C8051T620/1/6/7 & C8051T320/1/2/3 devices include a factory calibrated temperature sensor offset coefficient located in the EPROM memory. The TOFFH and TOFFL values are located at the address indicated in Figure 15.3. More information on using the temperature sensor calibration values can be found in Section “9.1. Calibration” on page 58. 15.1.3. Serialization All C8051T620/1/6/7 & C8051T320/1/2/3 devices have a factory serialization located in EPROM memory. This value is unique to each device. The serial number is located at the address indicated in Figure 15.3 and can be accessed like any constant array in program memory. Rev. 1.3 89 C8051T620/1/6/7 & C8051T320/1/2/3 15.2. Data Memory es ig ns The C8051T620/1 and C8051T320/1/2/3 device family includes 1280 bytes of RAM data memory, while the C8051T626/6 devices include 3328 bytes. 256 bytes of this memory is mapped into the internal RAM space of the 8051. The remaining 1024 or 3072 bytes of this memory is on-chip "external" memory. The data memory map is shown in Figure 15.1 and Figure 15.2 for reference. D 15.2.1. Internal RAM There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or as 128 bit locations accessible with the direct addressing mode. fo r N ew The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the same address space as the Special Function Registers (SFR) but is physically separate from the SFR space. The addressing mode used by an instruction when accessing locations above 0x7F determines whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the upper 128 bytes of data memory. Figure 15.1 illustrates the data memory organization of the C8051T620/1/6/7 & C8051T320/1/2/3. m en de d 15.2.1.1. General Purpose Registers The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of general-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1 (PSW.4), select the active register bank (see description of the PSW in SFR Definition 12.6). This allows fast context switching when entering subroutines and interrupt service routines. Indirect addressing modes use registers R0 and R1 as index registers. om 15.2.1.2. Bit Addressable Locations In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from 0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address 0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by the type of instruction used (bit source or destination operands as opposed to a byte source or destination). ec The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where XX is the byte address and B is the bit position within the byte. For example, the instruction: C, 22.3h R MOV moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag. N ot 15.2.1.3. Stack A programmer's stack can be located anywhere in the 256-byte data memory. The stack area is designated using the Stack Pointer (SP) SFR. The SP will point to the last location used. The next value pushed on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to location 0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the first register (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be initialized to a location in the data memory not being used for data storage. The stack depth can extend up to 256 bytes. 90 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 es ig ns 15.2.2. External RAM There are 1024 bytes (C8051T620/1/320/1/2/3 devices) or 3072 bytes (C8051T626/7 devices) of on-chip RAM mapped into the external data memory space. All of these address locations may be accessed using the external move instruction (MOVX) and the data pointer (DPTR), or using MOVX indirect addressing mode. If the MOVX instruction is used with an 8-bit address operand (such as @R1), then the high byte of the 16-bit address is provided by the External Memory Interface Control Register (EMI0CN as shown in SFR Definition 15.1). N ew D For a 16-bit MOVX operation (@DPTR), the upper three or five bits of the 16-bit external data memory address word are "don't cares" (when USBFAE is cleared to 0). As a result, the XRAM is mapped modulo style over the entire 64 k external data memory address range. For example, on the C8051T620/1 the XRAM byte at address 0x0000 is shadowed at addresses 0x0400, 0x0800, 0x0C00, 0x1000, etc. This is a useful feature when performing a linear memory fill, as the address pointer doesn't have to be reset when reaching the RAM block boundary. SFR Definition 15.1. EMI0CN: External Memory Interface Control Bit 7 6 5 3 2 1 0 PGSEL[4:0] fo r Name 4 R R R R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 m en de d Type SFR Address = 0xAA Bit Name Function om 7:5 Unused Read = 00000b; Write = Don’t Care. 4:0 PGSEL[4:0] XRAM Page Select. The EMI0CN register provides the high byte of the 16-bit external data memory address when using an 8-bit MOVX command, effectively selecting a 256-byte page of RAM. Since the upper (unused) bits of the register are always zero, the PGSEL determines which page of XRAM is accessed. For Example: If EMI0CN = 0x01, addresses 0x0100 through 0x01FF will be accessed. Note: PGSEL[4:3] are only valid on the C8051T626/7 devices. N ot R ec 15.2.3. Accessing USB FIFO Space The C8051T620/1/6/7 & C8051T320/1/2/3 include 1k of RAM which functions as USB FIFO space. Figure 15.4 shows an expanded view of the FIFO space and user XRAM. FIFO space is normally accessed via USB FIFO registers; see Section “23.5. FIFO Management” on page 169 for more information on accessing these FIFOs. The MOVX instruction should not be used to load or modify USB data in the FIFO space. Unused areas of the USB FIFO space may be used as general purpose XRAM if necessary. The FIFO block operates on the USB clock domain; thus the USB clock must be active when accessing FIFO space. Note that the number of SYSCLK cycles required by the MOVX instruction is increased when accessing USB FIFO space. To access the FIFO RAM directly using MOVX instructions, the following conditions must be met: (1) the USBFAE bit in register EMI0CF must be set to 1, and (2) the USB clock frequency must be greater than or Rev. 1.3 91 C8051T620/1/6/7 & C8051T320/1/2/3 m en de d fo r N ew D Important Note: The USB clock must be active when accessing FIFO space. es ig ns equal to twice the SYSCLK (USBCLK > 2 x SYSCLK). When this bit is set, the USB FIFO space is mapped into XRAM space at addresses 0x0400 to 0x07FF. The normal on-chip XRAM at the same addresses cannot be accessed when the USBFAE bit is set to 1. N ot R ec om Figure 15.4. C8051T620/1 and C8051T320/1/2/3 USB FIFO Space and XRAM Memory Map with USBFAE Set to 1 92 Rev. 1.3 m en de d fo r N ew D es ig ns C8051T620/1/6/7 & C8051T320/1/2/3 N ot R ec om Figure 15.5. C8051T626/7 USB FIFO Space and XRAM Memory Map with USBFAE set to 1 Rev. 1.3 93 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 3 2 USBFAE Name Type R R/W R R R R Reset 0 0 0 0 0 0 SFR Address = 0x85 Bit Name Function Unused USBFAE Read = 0b; Write = Don’t Care. 5:0 Unused Read = 000011b; Write = Don’t Care. N ew 7 6 0 R R 1 1 R ec om m en de d fo r USB FIFO Access Enable. 0: USB FIFO RAM not available through MOVX instructions. 1: USB FIFO RAM available using MOVX instructions. The 1k of USB RAM will be mapped in XRAM space at addresses 0x0400 to 0x07FF. The USB clock must be active and greater than or equal to twice the SYSCLK (USBCLK > 2 x SYSCLK) to access this area with MOVX instructions. N ot 94 1 D Bit es ig ns SFR Definition 15.2. EMI0CF: External Memory Configuration Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 16. Special Function Registers es ig ns The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the C8051T620/1/6/7 & C8051T320/1/2/3's resources and peripherals. The CIP-51 controller core duplicates the SFRs found in a typical 8051 implementation as well as implementing additional SFRs used to configure and access the sub-systems unique to the C8051T620/1/6/7 & C8051T320/1/2/3. This allows the addition of new functionality while retaining compatibility with the MCS-51™ instruction set. Table 16.1 lists the SFRs implemented in the C8051T620/1/6/7 & C8051T320/1/2/3 device family. N ew D The SFR registers are accessed anytime the direct addressing mode is used to access memory locations from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g., P0, TCON, SCON0, IE, etc.) are bitaddressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate effect and should be avoided. Refer to the corresponding pages of the data sheet, as indicated in Table 16.2, for a detailed description of each register. Table 16.1. Special Function Register (SFR) Memory Map fo r PCA0L PCA0H PCA0CPL0 PCA0CPH0 PCA0CPL4 P0MDIN P1MDIN P2MDIN PCA0PWM IAPCN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 PCA0CPL3 XBR0 XBR1 XBR2 IT01CF SMOD1 PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 PCA0CPM3 REF0CN SCON1 SBUF1 P0SKIP P1SKIP REG01CN TMR2RLL TMR2RLH TMR2L TMR2H SMB0CF SMB0DAT ADC0GTL ADC0GTH ADC0LTL CLKMUL P1MASK AMX0P ADC0CF ADC0L OSCXCN OSCICN OSCICL SBRLL1 SBRLH1 CLKSEL EMI0CN SBCON1 SPI0CFG SPI0CKR SPI0DAT P0MDOUT P1MDOUT SBUF0 CPT1CN CPT0CN CPT1MD CPT0MD TMR3CN TMR3RLL TMR3RLH TMR3L TMR3H TMOD TL0 TL1 TH0 TH1 SP DPL DPH P0MAT EMI0CF 1(9) 2(A) 3(B) 4(C) 5(D) m en de d SPI0CN B ADC0CN ACC PCA0CN PSW TMR2CN SMB0CN IP P3 IE P2 SCON0 P1 TCON P0 0(8) om F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 PCA0CPH4 EIP1 PCA0CPH3 EIE1 PCA0CPM4 P2SKIP ADC0LTH ADC0H P1MAT P0MASK P2MDOUT CPT1MX USB0ADR CKCON OSCLCN 6(E) VDM0CN EIP2 RSTSRC EIE2 USB0XCN SMB0ADM SMB0ADR MEMKEY PFE0CN P3MDOUT CPT0MX USB0DAT PSCTL PCON 7(F) N ot R ec Note: SFR Addresses ending in 0x0 or 0x8 are bit-addressable locations and can be used with bitwise instructions. Rev. 1.3 95 C8051T620/1/6/7 & C8051T320/1/2/3 Table 16.2. Special Function Registers Register Address Description es ig ns SFRs are listed in alphabetical order. All undefined SFR locations are reserved Page ACC 0xE0 Accumulator ADC0CF 0xBC ADC0 Configuration ADC0CN 0xE8 ADC0 Control ADC0GTH 0xC4 ADC0 Greater-Than Compare High ADC0GTL 0xC3 ADC0 Greater-Than Compare Low ADC0H 0xBE ADC0 High ADC0L 0xBD ADC0 Low ADC0LTH 0xC6 ADC0 Less-Than Compare Word High 53 ADC0LTL 0xC5 ADC0 Less-Than Compare Word Low 53 AMX0P 0xBB AMUX0 Positive Channel Select 56 B 0xF0 B Register 74 CKCON 0x8E Clock Control CLKMUL 0xB9 Clock Multiplier Control 132 CLKSEL 0xA9 Clock Select 129 CPT0CN 0x9B Comparator0 Control 80 CPT0MD 0x9D Comparator0 Mode Selection 81 CPT0MX 0x9F Comparator0 MUX Selection 85 CPT1CN 0x9B Comparator1 Control 82 0x9D Comparator1 Mode Selection 83 0x9F Comparator1 MUX Selection 86 0x83 Data Pointer High 73 0x82 Data Pointer Low 73 EIE1 0xE6 Extended Interrupt Enable 1 106 EIE2 0xE7 Extended Interrupt Enable 2 108 EIP1 0xF6 Extended Interrupt Priority 1 107 EIP2 0xF7 Extended Interrupt Priority 2 109 EMI0CF 0x85 External Memory Configuration 94 EMI0CN 0xAA External Memory Interface Control 91 CPT1MX N ot R DPL 96 49 51 D 52 N ew fo r m en de d ec DPH om CPT1MD 74 Rev. 1.3 52 50 50 247 C8051T620/1/6/7 & C8051T320/1/2/3 Table 16.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Address Description Page es ig ns Register IAPCN 0xF5 In-Application Programming Control IE 0xA8 Interrupt Enable IP 0xB8 Interrupt Priority IT01CF 0xE4 INT0/INT1 Configuration MEMKEY 0xB7 EPROM Memory Lock and Key OSCICL 0xB3 Internal Oscillator Calibration OSCICN 0xB2 Internal Oscillator Control OSCLCN 0x86 Low-Frequency Oscillator Control 133 OSCXCN 0xB1 External Oscillator Control 137 P0 0x80 Port 0 Latch P0MASK 0xAE Port 0 Mask Configuration 150 P0MAT 0x84 Port 0 Match Configuration 150 P0MDIN 0xF1 Port 0 Input Mode Configuration 153 P0MDOUT 0xA4 Port 0 Output Mode Configuration 153 P0SKIP 0xD4 Port 0 Skip 154 P1 0x90 Port 1 Latch 154 P1MASK 0xBA Port 1Mask Configuration 151 P1MAT 0xB6 Port 1 Match Configuration 151 P1MDIN 0xF2 Port 1 Input Mode Configuration 155 P1MDOUT 0xA5 Port 1 Output Mode Configuration 155 P1SKIP 0xD5 Port 1 Skip 156 104 105 fo r N ew D 111 m en de d om ec 117 116 130 131 152 0xA0 Port 2 Latch 156 P2MDIN 0xF3 Port 2 Input Mode Configuration 157 P2MDOUT 0xA6 Port 2 Output Mode Configuration 157 P2SKIP 0xD6 Port 2 Skip 158 P3 0xB0 Port 3 Latch 158 P3MDOUT 0xA7 Port 3 Output Mode Configuration 159 PCA0CN 0xD8 PCA Control 282 N ot R P2 Rev. 1.3 97 C8051T620/1/6/7 & C8051T320/1/2/3 Table 16.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Address PCA0CPH0 0xFC PCA Capture 0 High PCA0CPH1 0xEA PCA Capture 1 High PCA0CPH2 0xEC PCA Capture 2 High PCA0CPH3 0xEE PCA Capture 3 High PCA0CPH4 0xFE PCA Capture 4 High PCA0CPL0 0xFB PCA Capture 0 Low PCA0CPL1 0xE9 PCA Capture 1 Low PCA0CPL2 0xEB PCA Capture 2 Low PCA0CPL3 0xED PCA Capture 3 Low PCA0CPL4 0xFD PCA Capture 4 Low PCA0CPM0 0xDA PCA Module 0 Mode Register 285 PCA0CPM1 0xDB PCA Module 1 Mode Register 285 PCA0CPM2 0xDC PCA Module 2 Mode Register 285 PCA0CPM3 0xDD PCA Module 3 Mode Register 285 PCA0CPM4 0xDE PCA Module 4 Mode Register 285 PCA0H 0xFA PCA Counter High 286 PCA0L 0xF9 PCA Counter Low 286 PCA0MD 0xD9 PCA Mode 283 PCA0PWM 0xF4 PCA PWM Configuration 284 PCON 0x87 Power Control 120 0xAF Prefetch Engine Control 76 Page 287 287 287 fo r N ew D 287 m en de d om ec PFE0CN Description es ig ns Register 287 287 287 287 287 287 0x8F Program Store R/W Control 116 PSW 0xD0 Program Status Word 75 REF0CN 0xD1 Voltage Reference Control 60 REG01CN 0xC9 Voltage Regulator Control 65 RSTSRC 0xEF Reset Source Configuration/Status 126 SBCON1 0xAC UART1 Baud Rate Generator Control 231 SBRLH1 0xB5 UART1 Baud Rate Generator High Byte 231 N ot R PSCTL 98 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 Table 16.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Address Description Page es ig ns Register SBRLL1 0xB4 UART1 Baud Rate Generator Low Byte SBUF0 0x99 UART0 Data Buffer SBUF1 0xD3 UART1 Data Buffer SCON0 0x98 UART0 Control SCON1 0xD2 UART1 Control SMB0ADM 0xCF SMBus Slave Address Mask SMB0ADR 0xC7 SMBus Slave Address SMB0CF 0xC1 SMBus Configuration SMB0CN 0xC0 SMBus Control SMB0DAT 0xC2 SMBus Data SMOD1 0xE5 UART1 Mode SP 0x81 Stack Pointer SPI0CFG 0xA1 SPI Configuration 240 SPI0CKR 0xA2 SPI Clock Rate Control 242 SPI0CN 0xF8 SPI Control 241 SPI0DAT 0xA3 SPI Data 242 TCON 0x88 Timer/Counter Control 252 TH0 0x8C Timer/Counter 0 High 255 TH1 0x8D Timer/Counter 1 High 255 0x8A Timer/Counter 0 Low 254 0x8B Timer/Counter 1 Low 254 221 230 fo r N ew D 220 m en de d ec TL1 om TL0 232 228 205 204 200 202 206 229 74 0x89 Timer/Counter Mode 253 TMR2CN 0xC8 Timer/Counter 2 Control 259 TMR2H 0xCD Timer/Counter 2 High 261 TMR2L 0xCC Timer/Counter 2 Low 260 TMR2RLH 0xCB Timer/Counter 2 Reload High 260 TMR2RLL 0xCA Timer/Counter 2 Reload Low 260 TMR3CN 0x91 Timer/Counter 3Control 265 N ot R TMOD Rev. 1.3 99 C8051T620/1/6/7 & C8051T320/1/2/3 Table 16.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved 0x95 Timer/Counter 3 High TMR3L 0x94 Timer/Counter 3Low TMR3RLH 0x93 Timer/Counter 3 Reload High TMR3RLL 0x92 Timer/Counter 3 Reload Low USB0ADR 0x96 USB0 Indirect Address USB0DAT 0x97 USB0 Data USB0XCN 0xD7 USB0 Transceiver Control VDM0CN 0xFF VDD Monitor Control XBR0 0xE1 Port I/O Crossbar Control 0 XBR1 0xE2 Port I/O Crossbar Control 1 XBR2 0xE3 Port I/O Crossbar Control 2 m en de d om ec R N ot 100 267 266 266 266 fo r TMR3H Rev. 1.3 Page es ig ns Description D Address N ew Register 164 165 162 124 147 148 149 C8051T620/1/6/7 & C8051T320/1/2/3 17. Interrupts es ig ns The C8051T620/1/6/7 & C8051T320/1/2/3 include an extended interrupt system supporting a total of 18 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and external inputs pins varies according to the specific version of the device. Each interrupt source has one or more associated interrupt-pending flag(s) located in an SFR. When a peripheral or external source meets a valid interrupt condition, the associated interrupt-pending flag is set to logic 1. N ew D If interrupts are enabled for the source, an interrupt request is generated when the interrupt-pending flag is set. As soon as execution of the current instruction is complete, the CPU generates an LCALL to a predetermined address to begin execution of an interrupt service routine (ISR). Each ISR must end with an RETI instruction, which returns program execution to the next instruction that would have been executed if the interrupt request had not occurred. If interrupts are not enabled, the interrupt-pending flag is ignored by the hardware and program execution continues as normal. (The interrupt-pending flag is set to logic 1 regardless of the interrupt's enable/disable state). Each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in an SFR (IE, EIE1, or EIE2). However, interrupts must first be globally enabled by setting the EA bit (IE.7) to logic 1 before the individual interrupt enables are recognized. Setting the EA bit to logic 0 disables all interrupt sources regardless of the individual interrupt-enable settings. fo r Note: Any instruction that clears a bit to disable an interrupt should be immediately followed by an instruction that has two or more opcode bytes. Using EA (global interrupt enable) as an example: m en de d // in 'C': EA = 0; // clear EA bit. EA = 0; // this is a dummy instruction with two-byte opcode. ; in assembly: CLR EA ; clear EA bit. CLR EA ; this is a dummy instruction with two-byte opcode. For example, if an interrupt is posted during the execution phase of a "CLR EA" opcode (or any instruction which clears a bit to disable an interrupt source), and the instruction is followed by a single-cycle instruction, the interrupt may be taken. However, a read of the enable bit will return a '0' inside the interrupt service routine. When the bit-clearing opcode is followed by a multi-cycle instruction, the interrupt will not be taken. N ot R ec om Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR. However, most are not cleared by the hardware and must be cleared by software before returning from the ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI) instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after the completion of the next instruction. Rev. 1.3 101 C8051T620/1/6/7 & C8051T320/1/2/3 17.1. MCU Interrupt Sources and Vectors es ig ns The C8051T620/1/6/7 & C8051T320/1/2/3 MCUs support 18 interrupt sources. Software can simulate an interrupt by setting any interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated and the CPU will vector to the ISR address associated with the interrupt-pending flag. MCU interrupt sources, associated vector addresses, priority order and control bits are summarized in Table 17.1. Refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). N ew D 17.1.1. Interrupt Priorities Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP, EIP1, or EIP2) used to configure its priority level. Low priority is the default. If two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is used to arbitrate, given in Table 17.1. m en de d fo r 17.1.2. Interrupt Latency Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 6 system clock cycles: 1 clock cycle to detect the interrupt and 5 clock cycles to complete the LCALL to the ISR. If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL is made to service the pending interrupt. Therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is performing an RETI instruction followed by a DIV as the next instruction. In this case, the response time is 20 system clock cycles: 1 clock cycle to detect the interrupt, 6 clock cycles to execute the RETI, 8 clock cycles to complete the DIV instruction and 5 clock cycles to execute the LCALL to the ISR. If the CPU is executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the current ISR completes, including the RETI and following instruction. Note that the CPU is stalled during EPROM write operations and USB FIFO MOVX accesses (see Section “15.2.3. Accessing USB FIFO Space” on page 91). Interrupt service latency will be increased for interrupts occurring while the CPU is stalled. The latency for these situations will be determined by the standard interrupt service procedure (as described above) and the amount of time the CPU is stalled. 17.2. Interrupt Register Descriptions N ot R ec om The SFRs used to enable the interrupt sources and set their priority level are described in this section. Refer to the data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). 102 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 Reset 0x0000 Top External Interrupt 0 (INT0) Timer 0 Overflow External Interrupt 1 (INT1) Timer 1 Overflow UART0 0x0003 0 IE0 (TCON.1) 0x000B 0x0013 1 2 TF0 (TCON.5) IE1 (TCON.3) 0x001B 0x0023 3 4 Timer 2 Overflow 0x002B 5 SPI0 0x0033 6 SMB0 USB0 N/A N/A Always Always Enabled Highest Y Y EX0 (IE.0) PX0 (IP.0) ET1 (IE.3) PT1 (IP.3) ES0 (IE.4) PS0 (IP.4) Y N ET2 (IE.5) PT2 (IP.5) Y N ESPI0 (IE.6) PSPI0 (IP.6) Y N ESMB0 (EIE1.0) EUSB0 (EIE1.0) EWADC0 (EIE1.2) EADC0 (EIE1.3) EPCA0 (EIE1.4) PSMB0 (EIP1.0) PUSB0 (EIP1.1) PWADC0 (EIP1.2) PADC0 (EIP1.3) PPCA0 (EIP1.4) ECP0 (EIE1.5) ECP1 (EIE1.6) ET3 (EIE1.7) EVBUS (EIE2.0) ES1 (EIE2.1) N/A EMAT (EIE2.3) N/A PCP0 (EIP1.5) PCP1 (EIP1.6) PT3 (EIP1.7) PVBUS (EIP2.0) PS1 (EIP2.1) N/A PMAT (EIP2.3) N/A N N 0x004B 9 Y N 0x0053 10 AD0WINT (ADC0CN.3) AD0INT (ADC0CN.5) Y N 0x005B 11 Y N N N N N N N fo r Special 0x006B 13 Timer 3 Overflow 0x0073 14 0x007B 15 UART1 0x0083 16 Reserved Port Match 0x008B 0x0093 ec Y N 8 Comparator1 R Y Y 0x0043 12 N ot ET0 (IE.1) PT0 (IP.1) EX1 (IE.2) PX1 (IP.2) 7 0x0063 Reserved Y Y 0x003B Comparator0 VBUS Level Y Y TF1 (TCON.7) RI0 (SCON0.0) TI0 (SCON0.1) TF2H (TMR2CN.7) TF2L (TMR2CN.6) SPIF (SPI0CN.7) WCOL (SPI0CN.6) MODF (SPI0CN.5) RXOVRN (SPI0CN.4) SI (SMB0CN.0) om ADC0 Window Compare ADC0 Conversion Complete Programmable Counter Array CF (PCA0CN.7) CCFn (PCA0CN.n) COVF (PCA0PWM.6) CP0FIF (CPT0CN.4) CP0RIF (CPT0CN.5) CP1FIF (CPT1CN.4) CP1RIF (CPT1CN.5) TF3H (TMR3CN.7) TF3L (TMR3CN.6) N/A N/A N/A 17 18 RI1 (SCON1.0) TI1 (SCON1.1) N/A None N/A N/A N/A N/A 19 N/A N/A N/A Rev. 1.3 Priority Control N ew None Enable Flag es ig ns Pending Flag D Priority Order Bit addressable? Interrupt Vector m en de d Interrupt Source Cleared by HW? Table 17.1. Interrupt Summary N N 103 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 3 2 Name EA ESPI0 ET2 ES0 ET1 EX1 Type R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 SFR Address = 0xA8; Bit-Addressable Bit Name Function 7 EA 6 ESPI0 5 ET2 Enable Timer 2 Interrupt. This bit sets the masking of the Timer 2 interrupt. 0: Disable Timer 2 interrupt. 1: Enable interrupt requests generated by the TF2L or TF2H flags. 4 ES0 Enable UART0 Interrupt. This bit sets the masking of the UART0 interrupt. 0: Disable UART0 interrupt. 1: Enable UART0 interrupt. 3 ET1 Enable Timer 1 Interrupt. This bit sets the masking of the Timer 1 interrupt. 0: Disable all Timer 1 interrupt. 1: Enable interrupt requests generated by the TF1 flag. 2 EX1 0 104 0 ET0 EX0 R/W R/W 0 0 N ew Enable All Interrupts. Globally enables/disables all interrupts. It overrides individual interrupt mask settings. 0: Disable all interrupt sources. 1: Enable each interrupt according to its individual mask setting. om m en de d fo r Enable Serial Peripheral Interface (SPI0) Interrupt. This bit sets the masking of the SPI0 interrupts. 0: Disable all SPI0 interrupts. 1: Enable interrupt requests generated by SPI0. Enable External Interrupt 1. This bit sets the masking of External Interrupt 1. 0: Disable external interrupt 1. 1: Enable interrupt requests generated by the INT1 input. ec R N ot 1 1 D Bit es ig ns SFR Definition 17.1. IE: Interrupt Enable ET0 Enable Timer 0 Interrupt. This bit sets the masking of the Timer 0 interrupt. 0: Disable all Timer 0 interrupt. 1: Enable interrupt requests generated by the TF0 flag. EX0 Enable External Interrupt 0. This bit sets the masking of External Interrupt 0. 0: Disable external interrupt 0. 1: Enable interrupt requests generated by the INT0 input. Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 7 Name 6 5 4 3 2 PSPI0 PT2 PS0 PT1 PX1 Type R R/W R/W R/W R/W R/W Reset 1 0 0 0 0 0 SFR Address = 0xB8; Bit-Addressable Bit Name Function Unused PSPI0 Read = 1b, Write = Don't Care. 5 PT2 Timer 2 Interrupt Priority Control. This bit sets the priority of the Timer 2 interrupt. 0: Timer 2 interrupt set to low priority level. 1: Timer 2 interrupt set to high priority level. 4 PS0 UART0 Interrupt Priority Control. This bit sets the priority of the UART0 interrupt. 0: UART0 interrupt set to low priority level. 1: UART0 interrupt set to high priority level. 3 PT1 Timer 1 Interrupt Priority Control. This bit sets the priority of the Timer 1 interrupt. 0: Timer 1 interrupt set to low priority level. 1: Timer 1 interrupt set to high priority level. 2 PX1 External Interrupt 1 Priority Control. This bit sets the priority of the External Interrupt 1 interrupt. 0: External Interrupt 1 set to low priority level. 1: External Interrupt 1 set to high priority level. 1 PT0 0 PT0 PX0 R/W R/W 0 0 N ew 7 6 1 D Bit es ig ns SFR Definition 17.2. IP: Interrupt Priority om m en de d fo r Serial Peripheral Interface (SPI0) Interrupt Priority Control. This bit sets the priority of the SPI0 interrupt. 0: SPI0 interrupt set to low priority level. 1: SPI0 interrupt set to high priority level. R ec Timer 0 Interrupt Priority Control. This bit sets the priority of the Timer 0 interrupt. 0: Timer 0 interrupt set to low priority level. 1: Timer 0 interrupt set to high priority level. N ot 0 PX0 External Interrupt 0 Priority Control. This bit sets the priority of the External Interrupt 0 interrupt. 0: External Interrupt 0 set to low priority level. 1: External Interrupt 0 set to high priority level. Rev. 1.3 105 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 3 2 Name ET3 ECP1 ECP0 EPCA0 EADC0 Type R/W R/W R/W R/W Reset 0 0 0 0 SFR Address = 0xE6 Bit Name 1 0 EWADC0 EUSB0 ESMB0 R/W R/W R/W R/W 0 0 0 0 Function D Bit es ig ns SFR Definition 17.3. EIE1: Extended Interrupt Enable 1 7 ET3 6 ECP1 Enable Comparator1 (CP1) Interrupt. This bit sets the masking of the CP1 interrupt. 0: Disable CP1 interrupts. 1: Enable interrupt requests generated by the CP1RIF or CP1FIF flags. 5 ECP0 Enable Comparator0 (CP0) Interrupt. This bit sets the masking of the CP0 interrupt. 0: Disable CP0 interrupts. 1: Enable interrupt requests generated by the CP0RIF or CP0FIF flags. 4 EPCA0 Enable Programmable Counter Array (PCA0) Interrupt. This bit sets the masking of the PCA0 interrupts. 0: Disable all PCA0 interrupts. 1: Enable interrupt requests generated by PCA0. 3 EADC0 Enable ADC0 Conversion Complete Interrupt. This bit sets the masking of the ADC0 Conversion Complete interrupt. 0: Disable ADC0 Conversion Complete interrupt. 1: Enable interrupt requests generated by the AD0INT flag. N ew fo r m en de d om EWADC0 Enable Window Comparison ADC0 Interrupt. This bit sets the masking of ADC0 Window Comparison interrupt. 0: Disable ADC0 Window Comparison interrupt. 1: Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT). R ec 2 Enable Timer 3 Interrupt. This bit sets the masking of the Timer 3 interrupt. 0: Disable Timer 3 interrupts. 1: Enable interrupt requests generated by the TF3L or TF3H flags. N ot 1 0 106 EUSB0 Enable USB (USB0) Interrupt. This bit sets the masking of the USB0 interrupt. 0: Disable all USB0 interrupts. 1: Enable interrupt requests generated by USB0. ESMB0 Enable SMBus (SMB0) Interrupt. This bit sets the masking of the SMB0 interrupt. 0: Disable all SMB0 interrupts. 1: Enable interrupt requests generated by SMB0. Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 3 2 Name PT3 PCP1 PCP0 PPCA0 PADC0 Type R/W R/W R/W R/W Reset 0 0 0 0 SFR Address = 0xF6 Bit Name 1 0 PWADC0 PUSB0 PSMB0 R/W R/W R/W R/W 0 0 0 0 Function D Bit es ig ns SFR Definition 17.4. EIP1: Extended Interrupt Priority 1 PT3 Timer 3 Interrupt Priority Control. This bit sets the priority of the Timer 3 interrupt. 0: Timer 3 interrupts set to low priority level. 1: Timer 3 interrupts set to high priority level. 6 PCP1 Comparator1 (CP1) Interrupt Priority Control. This bit sets the priority of the CP1 interrupt. 0: CP1 interrupt set to low priority level. 1: CP1 interrupt set to high priority level. 5 PCP0 Comparator0 (CP0) Interrupt Priority Control. This bit sets the priority of the CP0 interrupt. 0: CP0 interrupt set to low priority level. 1: CP0 interrupt set to high priority level. 4 PPCA0 Programmable Counter Array (PCA0) Interrupt Priority Control. This bit sets the priority of the PCA0 interrupt. 0: PCA0 interrupt set to low priority level. 1: PCA0 interrupt set to high priority level. 3 PADC0 ADC0 Conversion Complete Interrupt Priority Control. This bit sets the priority of the ADC0 Conversion Complete interrupt. 0: ADC0 Conversion Complete interrupt set to low priority level. 1: ADC0 Conversion Complete interrupt set to high priority level. fo r m en de d om PWADC0 ADC0 Window Comparator Interrupt Priority Control. This bit sets the priority of the ADC0 Window interrupt. 0: ADC0 Window interrupt set to low priority level. 1: ADC0 Window interrupt set to high priority level. R ec 2 N ew 7 N ot 1 0 PUSB0 USB (USB0) Interrupt Priority Control. This bit sets the priority of the USB0 interrupt. 0: USB0 interrupt set to low priority level. 1: USB0 interrupt set to high priority level. PSMB0 SMBus (SMB0) Interrupt Priority Control. This bit sets the priority of the SMB0 interrupt. 0: SMB0 interrupt set to low priority level. 1: SMB0 interrupt set to high priority level. Rev. 1.3 107 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 Name 4 3 2 Reserved EMAT Reserved Type R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 SFR Address = 0xE7 Bit Name 0 N ot R ec om This bit sets the masking of the VBUS interrupt. 0: Disable all VBUS interrupts. 1: Enable interrupt requests generated by VBUS level sense. 108 0 ES1 EVBUS R/W R/W 0 0 N ew Reserved Must write 0b. ES1 Enable UART1 Interrupt. This bit sets the masking of the UART1 interrupt. 0: Disable UART1 interrupt. 1: Enable UART1 interrupt. EVBUS Enable VBUS Level Interrupt. fo r 2 1 Unused Read = 0000b, Write = Don't Care. Reserved Must write 0b. EMAT Enable Port Match Interrupts. This bit sets the masking of the Port Match Event interrupt. 0: Disable all Port Match interrupts. 1: Enable interrupt requests generated by a Port Match. m en de d 7:3 4 3 Function 1 D Bit es ig ns SFR Definition 17.5. EIE2: Extended Interrupt Enable 2 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 Name 4 3 2 Reserved PMAT Reserved Type R R R R/W R/W R/W Reset 0 0 0 0 0 0 SFR Address = 0xF7 Bit Name PVBUS R/W R/W 0 0 N ew Reserved Must Write 0b. PS1 UART1 Interrupt Priority Control. This bit sets the priority of the UART1 interrupt. 0: UART1 interrupt set to low priority level. 1: UART1 interrupt set to high priority level. PVBUS VBUS Level Interrupt Priority Control. This bit sets the priority of the VBUS interrupt. 0: VBUS interrupt set to low priority level. 1: VBUS interrupt set to high priority level. N ot R ec om 0 PS1 fo r 2 1 Unused Read = 0000b, Write = Don't Care. Reserved Must Write 0b. PMAT Port Match Interrupt Priority Control. This bit sets the priority of the Port Match Event interrupt. 0: Port Match interrupt set to low priority level. 1: Port Match interrupt set to high priority level. 0 m en de d 7:5 4 3 Function 1 D Bit es ig ns SFR Definition 17.6. EIP2: Extended Interrupt Priority 2 Rev. 1.3 109 C8051T620/1/6/7 & C8051T320/1/2/3 17.3. INT0 and INT1 External Interrupt Sources IN0PL 1 1 0 0 0 1 0 1 INT0 Interrupt Active low, edge sensitive Active high, edge sensitive Active low, level sensitive Active high, level sensitive IT1 1 1 0 0 IN1PL 0 1 0 1 INT1 Interrupt Active low, edge sensitive Active high, edge sensitive Active low, level sensitive Active high, level sensitive D IT0 es ig ns The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level sensitive. The IN0PL (INT0 Polarity) and IN1PL (INT1 Polarity) bits in the IT01CF register select active high or active low; the IT0 and IT1 bits in TCON (Section “28.1. Timer 0 and Timer 1” on page 248) select level or edge sensitive. The table below lists the possible configurations. N ew INT0 and INT1 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 17.7). Note that INT0 and INT0 Port pin assignments are independent of any Crossbar assignments. INT0 and INT1 will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin via the Crossbar. To assign a Port pin only to INT0 and/or INT1, configure the Crossbar to skip the selected pin(s). This is accomplished by setting the associated bit in register PnSKIP (see Section “22.3. Priority Crossbar Decoder” on page 142 for complete details on configuring the Crossbar). N ot R ec om m en de d fo r IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the INT0 and INT1 external interrupts, respectively. If an INT0 or INT1 external interrupt is configured as edge-sensitive, the corresponding interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inactive. The external interrupt source must hold the input active until the interrupt request is recognized. It must then deactivate the interrupt request before execution of the ISR completes or another interrupt request will be generated. 110 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 Bit 7 Name IN1PL IN1SL[2:0] IN0PL IN0SL[2:0] Type R/W R/W R/W R/W Reset 0 0 5 0 4 0 SFR Address = 0xE4 Bit Name Function INT1 Polarity. 0: INT1 input is active low. 1: INT1 input is active high. 0 1 0 0 1 IN1SL[2:0] INT1 Port Pin Selection Bits. These bits select which Port pin is assigned to INT1. Note that this pin assignment is independent of the Crossbar; INT1 will monitor the assigned Port pin without disturbing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar will not assign the Port pin to a peripheral if it is configured to skip the selected pin. 000: Select P0.0 001: Select P0.1 010: Select P0.2 011: Select P0.3 100: Select P0.4 101: Select P0.5 110: Select P0.6 111: Select P0.7 INT0 Polarity. 0: INT0 input is active low. 1: INT0 input is active high. IN0SL[2:0] INT0 Port Pin Selection Bits. These bits select which Port pin is assigned to INT0. Note that this pin assignment is independent of the Crossbar; INT0 will monitor the assigned Port pin without disturbing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar will not assign the Port pin to a peripheral if it is configured to skip the selected pin. 000: Select P0.0 001: Select P0.1 010: Select P0.2 011: Select P0.3 100: Select P0.4 101: Select P0.5 110: Select P0.6 111: Select P0.7 N ot R ec 2:0 IN0PL om 3 m en de d fo r 6:4 IN1PL 0 2 N ew 7 3 D 6 es ig ns SFR Definition 17.7. IT01CF: INT0/INT1 ConfigurationO Rev. 1.3 111 C8051T620/1/6/7 & C8051T320/1/2/3 18. Program Memory (EPROM) es ig ns C8051T620/1/6/7 & C8051T320/1/2/3 devices include 64, 32, or 16 kB of on-chip byte-programmable EPROM for program code storage. The EPROM memory can be programmed via the C2 debug and programming interface when a special programming voltage is applied to the VPP pin. Additionally, EPROM bytes can be programmed in system using an external capacitor on the VPP pin. Each location in EPROM memory is programmable only once (i.e. non-erasable). Table 7.6 on page 38 shows the EPROM specifications. 18.1. Programming the EPROM Memory N ew D 18.1.1. EPROM Programming over the C2 Interface Programming of the EPROM memory is accomplished through the C2 programming and debug interface. When creating hardware to program the EPROM, it is necessary to follow the programming steps listed below. Please refer to the “C2 Interface Specification” available at http://www.silabs.com for details on communicating via the C2 interface. Section “30. C2 Interface” on page 288 has information about C2 register addresses for the C8051T620/1/6/7 & C8051T320/1/2/3. 1. Reset the device using the RST pin. fo r 2. Wait at least 20 ms before sending the first C2 command. 3. Place the device in core reset: Write 0x04 to the DEVCTL register. 4. Set the device to program mode (1st step): Write 0x40 to the EPCTL register. 5. Set the device to program mode (2nd step): Write 0x4A to the EPCTL register. Note: Devices with a Date Code prior to 1040 should write 0x58 to the EPCTL register. Apply the VPP programming Voltage. Write the first EPROM address for programming to EPADDRH and EPADDRL. Write a data byte to EPDAT. EPADDRH:L will increment by 1 after this write. Poll the EPBusy bit using a C2 Address Read command. Note: If EPError is set at this time, the write operation failed. 10.If programming is not finished, return to Step 8 to write the next address in sequence, or return to Step 7 to program a new address. 11. Remove the VPP programming Voltage. 12.Remove program mode (1st step): Write 0x40 to the EPCTL register. 13.Remove program mode (2nd step): Write 0x00 to the EPCTL register. 14.Reset the device: Write 0x02 and then 0x00 to the DEVCTL register. ec om m en de d 6. 7. 8. 9. N ot R Important Note 1: There is a finite amount of time which VPP can be applied without damaging the device, which is cumulative over the life of the device. Refer to Table 7.1 on page 34 for the VPP timing specification. Rev. 1.3 112 C8051T620/1/6/7 & C8051T320/1/2/3 es ig ns 18.1.2. EPROM In-Application Programming The EPROM of the C8051T620/1/6/7 & C8051T320/1/2/3 devices has an In-Application Programming option. In-Application Programming will be much slower than normal programming where the VPP programming voltage is applied to the VPP pin, but it allows a small number of bytes to be programmed anywhere in the non-reserved areas of the EPROM. In order to use this option, VIO must be within a specific range and a capacitor must be connected externally to the VPP pin. Refer to Section “7. Electrical Characteristics” on page 34 for the acceptable range of values for VIO and the capacitor on the VPP pin. Bytes in the EPROM memory must be written one byte at a time. An EPROM write will be performed after each MOVX write instruction. The recommended procedure for writing to the EPROM is as follows: m en de d fo r N ew D 1. Disable interrupts. 2. Change the core clock to 25 MHz or less. 3. Enable the VDD Monitor. Write 0x80 to VDM0CN. 4. Enable the VDD Monitor as a reset source. Write 0x02 to RSTSRC. 5. Disable the Prefetch engine. Write 0x00 to the PFE0CN register. 6. Set the VPP Pin to an open-drain configuration, with a ‘1’ in the port latch. 7. Set the PSWE bit (register PSCTL). 8. Write the first key code to MEMKEY: 0xA5. 9. Write the second key code to MEMKEY: 0xF1. 10.Enable in-application programming. Write 0x80 to the IAPCN register. 11. Using a MOVX write instruction, write a single data byte to the desired location. 12.Disable in-application EPROM programming. Write 0x00 to the IAPCN register. 13.Clear the PSWE bit. 14.Re-enable the Prefetch engine. Write 0x20 to the PFE0CN register. 15.Delay for at least 1 us. 16.Disable the programming hardware. Write 0x40 to the IAPCN register. 17.Restore the core clock (if changed in Step 2) 18.Re-enable interrupts. Steps 8–11 must be repeated for each byte to be written. ec om When an application uses the In-Application Programming feature, the VPP pin must be set to open-drain mode, with a ‘1’ in the port latch. The pin can still be used a as a general-purpose I/O pin if the programming circuitry of the pin is disabled after all writes are completed by using the IAPHWD bit in the IAPCN register (IAPCN.6). It is not necessary to disable the programming hardware if the In-Application Programming feature has not been used. N ot R Important Note: Software should delay for at least 1 μs after the last EPROM write before setting the IAPHWD bit. 113 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 18.2. Security Options es ig ns The C8051T620/1/6/7 & C8051T320/1/2/3 devices provide security options to prevent unauthorized viewing of proprietary program code and constants. A security byte stored in the EPROM address space can be used to lock the program memory from being read or written across the C2 interface. On the C8051T626/7 devices, the security byte is located at address 0xFFF8. On the C8051T620/1 and C8051T320/1/2/3, the security byte is located at address 0x3FF8. Table 18.1 shows the security byte decoding. Refer to “Figure 15.3. Program Memory Map” on page 89 for the location of the security byte in EPROM memory. N ew Table 18.1. Security Byte Decoding D Important Note: Once the security byte has been written, there are no means of unlocking the device. Locking memory from write access should be performed only after all other code has been successfully programmed to memory. Description Write Lock: Clearing any of these bits to logic 0 prevents all code memory from being written across the C2 interface. Read Lock: Clearing any of these bits to logic 0 prevents all code memory from being read across the C2 interface. 3–0 18.3. EPROM Writing Guidelines fo r Bits 7–4 m en de d Any system which contains routines which write EPROM memory from software involves some risk that the write routines will execute unintentionally if the CPU is operating outside its specified operating range of VDD, system clock frequency, or temperature. This accidental execution of EPROM modifying code can result in alteration of EPROM memory contents causing a system failure. The following guidelines are recommended for any system which contains routines which write EPROM memory from code. N ot R ec om 18.3.1. VDD Maintenance and the VDD monitor 1. If the system power supply is subject to voltage or current "spikes," add sufficient transient protection devices to the power supply to ensure that the supply voltages listed in the Absolute Maximum Ratings table are not exceeded. 2. Make certain that the minimum VDD rise time specification of 1 ms is met. If the system cannot meet this rise time specification, then add an external VDD brownout circuit to the RST pin of the device that holds the device in reset until VDD reaches VRST and re-asserts RST if VDD drops below VRST. 3. Enable the on-chip VDD monitor and enable the VDD monitor as a reset source as early in code as possible. This should be the first set of instructions executed after the Reset Vector. For 'C'-based systems, this will involve modifying the startup code added by the 'C' compiler. See your compiler documentation for more details. Make certain that there are no delays in software between enabling the VDD monitor and enabling the VDD monitor as a reset source. Note: Both the VDD Monitor and the VDD Monitor reset source must be enabled to write the EPROM without generating an EPROM Error Device Reset. 4. As an added precaution, explicitly enable the VDD monitor and enable the VDD monitor as a reset source inside the functions that write EPROM memory. The VDD monitor enable instructions should be placed just after the instruction to set PSWE to a 1, but before the EPROM write operation instruction. 5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment operators and explicitly DO NOT use the bit-wise operators (such as AND or OR). For example,"RSTSRC = 0x02" is correct. "RSTSRC |= 0x02" is incorrect. Rev. 1.3 114 C8051T620/1/6/7 & C8051T320/1/2/3 m en de d fo r N ew D es ig ns 6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a 1. Areas to check are initialization code which enables other reset sources, such as the Missing Clock Detector, for example, and instructions which force a Software Reset. A global search on "RSTSRC" can quickly verify this. 18.3.2. PSWE Maintenance 7. Reduce the number of places in code where the PSWE bit (PSCTL.0) is set to a 1. There should be exactly one routine in code that sets PSWE to a 1 to write EPROM bytes. 8. Minimize the number of variable accesses while PSWE is set to a 1. Handle pointer address updates and loop variable maintenance outside the "PSWE = 1;... PSWE = 0;" area. 9. Disable interrupts prior to setting PSWE to a '1' and leave them disabled until after PSWE has been reset to '0'. Any interrupts posted during the EPROM write operation will be serviced in priority order after the EPROM operation has been completed and interrupts have been re-enabled by software. 10.Make certain that the EPROM write pointer variables are not located in XRAM. See your compiler documentation for instructions regarding how to explicitly locate variables in different memory areas. 11.Add address bounds checking to the routines that write EPROM memory to ensure that a routine called with an illegal address does not result in modification of the EPROM. 18.3.3. System Clock 12.If operating from an external crystal, be advised that crystal performance is susceptible to electrical interference and is sensitive to layout and to changes in temperature. If the system is operating in an electrically noisy environment, use the internal oscillator or an external CMOS clock. 13.If operating from the external oscillator, switch to the internal oscillator during EPROM write operations. The external oscillator can continue to run, and the CPU can switch back to the external oscillator after the EPROM operation has completed. 18.4. Program Memory CRC A CRC engine is included on-chip which provides a means of verifying EPROM contents once the device has been programmed. The CRC engine is available for EPROM verification even if the device is fully read and write locked, allowing for verification of code contents at any time. om The CRC engine is operated through the C2 debug and programming interface, and performs 16-bit CRCs on individual 256-Byte blocks of program memory, or a 32-bit CRC on the entire memory space. To prevent hacking and extrapolation of security-locked source code, the CRC engine will only allow CRCs to be performed on contiguous 256-Byte blocks beginning on 256-Byte boundaries (lowest 8-bits of address are 0x00). For example, the CRC engine can perform a CRC for locations 0x0400 through 0x04FF, but it cannot perform a CRC for locations 0x0401 through 0x0500, or on block sizes smaller or larger than 256 Bytes. N ot R ec 18.4.1. Performing 32-bit CRCs on Full EPROM Content A 32-bit CRC on the entire EPROM space is initiated by writing to the CRC1 byte over the C2 interface. The CRC calculation begins at address 0x0000, and ends at the end of user EPROM space. The EPBusy bit in register C2ADD will be set during the CRC operation, and cleared once the operation is complete. The 32-bit results will be available in the CRC3-0 registers. CRC3 is the MSB, and CRC0 is the LSB. The polynomial used for the 32-bit CRC calculation is 0x04C11DB7. Note: If a 16-bit CRC has been performed since the last device reset, a device reset should be initiated before performing a 32-bit CRC operation. 18.4.2. Performing 16-bit CRCs on 256-Byte EPROM Blocks A 16-bit CRC of individual 256-byte blocks of EPROM can be initiated by writing to the CRC0 byte over the C2 interface. The value written to CRC0 is the high byte of the beginning address for the CRC. For example, if CRC0 is written to 0x02, the CRC will be performed on the 256-bytes beginning at address 0x0200, and ending at address 0x2FF. The EPBusy bit in register C2ADD will be set during the CRC operation, and cleared once the operation is complete. The 16-bit results will be available in the CRC1-0 registers. CRC1 is the MSB, and CRC0 is the LSB. The polynomial for the 16-bit CRC calculation is 0x1021. 115 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 Bit 7 6 5 4 3 2 1 0 PSWE Name R R R R R R Reset 0 0 0 0 0 0 SFR Address = 0x8F Bit Name R/W 0 0 Function N ew Read = 0000000b. Write = don’t care. Program Store Write Enable. Setting this bit allows writing a byte of data to the EPROM program memory using the MOVX write instruction. 0: Writes to EPROM program memory disabled. 1: Writes to EPROM program memory enabled; the MOVX write instruction targets EPROM memory. fo r Unused PSWE R D Type 7:1 0 es ig ns SFR Definition 18.1. PSCTL: Program Store R/W Control Bit 7 m en de d SFR Definition 18.2. MEMKEY: EPROM Memory Lock and Key 6 5 4 3 2 1 0 0 0 0 MEMKEY[7:0] Name R/W Type 0 Reset 0 0 0 om SFR Address = 0xB7 Bit Name 0 Function N ot R ec 7:0 MEMKEY[7:0] EPROM Lock and Key Register. Write: This register provides a lock and key function for EPROM writes. EPROM writes are enabled by writing 0xA5 followed by 0xF1 to the MEMKEY register. EPROM writes are automatically disabled after the next write is complete. If any writes to MEMKEY are performed incorrectly, or if a EPROM write operation is attempted while these operations are disabled, the EPROM will be permanently locked from writes until the next device reset. If an application never writes to EPROM, it can intentionally lock the EPROM by writing a non-0xA5 value to MEMKEY from software. Read: When read, bits 1–0 indicate the current EPROM lock state. 00: EPROM is write locked. 01: The first key code has been written (0xA5). 10: EPROM is unlocked (writes allowed). 11: EPROM writes disabled until the next reset. Rev. 1.3 116 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 3 2 Name IAPEN IAPDISD Type R/W R/W R R R R Reset 0 0 0 0 0 0 SFR Address = 0xF5 Bit Name IAPEN 6 IAPHWD In-Application Programming Enable. 0: In-Application Programming is disabled. 1: In-Application Programming is enabled. 0 R R 0 0 N ew 7 Function 1 D Bit es ig ns SFR Definition 18.3. IAPCN: In-Application Programming Control In-Application Programming Hardware Disable. This bit disables the In-Application Programming hardware so the VPP programming pin can be used as a normal GPIO pin. fo r Note: This bit should not be set less than 1 μs after the last EPROM write. 0: In-Application Programming discharge hardware enabled. 1: In-Application Programming discharge hardware disabled. Unused Read = 000000b. Write = don’t care. N ot R ec om m en de d 5:0 117 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 19. Power Management Modes es ig ns The C8051T620/1/6/7 & C8051T320/1/2/3 devices have three software programmable power management modes: Idle, Stop, and Suspend. Idle mode and stop mode are part of the standard 8051 architecture, while suspend mode is an enhanced power-saving mode implemented by the high-speed oscillator peripheral. N ew D Idle mode halts the CPU while leaving the peripherals and clocks active. In stop mode, the CPU is halted, all interrupts and timers (except the Missing Clock Detector) are inactive, and the internal oscillator is stopped (analog peripherals remain in their selected states; the external oscillator is not affected). Suspend mode is similar to stop mode in that the internal oscillator is halted, but the device can wake on events such as a Port Mismatch, Timer 3 overflow, or activity with the USB transceiver. Additionally, the CPU is not halted in suspend mode, so it can run on another oscillator, if desired. Since clocks are running in Idle mode, power consumption is dependent upon the system clock frequency and the number of peripherals left in active mode before entering Idle. Stop mode and suspend mode consume the least power because the majority of the device is shut down with no clocks active. SFR Definition 19.1 describes the Power Control Register (PCON) used to control the C8051T620/1/6/7 & C8051T320/1/2/3's Stop and Idle power management modes. Suspend mode is controlled by the SUSPEND bit in the OSCICN register (SFR Definition 21.3). 19.1. Idle Mode m en de d fo r Although the C8051T620/1/6/7 & C8051T320/1/2/3 has Idle, Stop, and suspend modes available, more control over the device power can be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral can be disabled when not in use and placed in low power mode. Digital peripherals, such as timers or serial buses, draw little power when they are not in use. Turning off oscillators lowers power consumption considerably, at the expense of reduced functionality. Setting the Idle Mode Select bit (PCON.0) causes the hardware to halt the CPU and enter Idle mode as soon as the instruction that sets the bit completes execution. All internal registers and memory maintain their original data. All analog and digital peripherals can remain active during idle mode. om Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume operation. The pending interrupt will be serviced and the next instruction to be executed after the return from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit. If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence and begins program execution at address 0x0000. ec Note: If the instruction following the write of the IDLE bit is a single-byte instruction and an interrupt occurs during the execution phase of the instruction that sets the IDLE bit, the CPU may not wake from Idle mode when a future interrupt occurs. Therefore, instructions that set the IDLE bit should be followed by an instruction that has two or more opcode bytes, for example: // set IDLE bit // ... followed by a 3-cycle dummy instruction ; in assembly: ORL PCON, #01h MOV PCON, PCON ; set IDLE bit ; ... followed by a 3-cycle dummy instruction N ot R // in ‘C’: PCON |= 0x01; PCON = PCON; If enabled, the Watchdog Timer (WDT) will eventually cause an internal watchdog reset and thereby terminate the Idle mode. This feature protects the system from an unintended permanent shutdown in the event of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by software prior to entering the Idle mode if the WDT was initially configured to allow this operation. This pro- Rev. 1.3 118 C8051T620/1/6/7 & C8051T320/1/2/3 vides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefinitely, waiting for an external stimulus to wake up the system. Refer to Section “20.6. PCA Watchdog Timer Reset” on page 125 for more information on the use and configuration of the WDT. es ig ns 19.2. Stop Mode Setting the stop mode Select bit (PCON.1) causes the controller core to enter stop mode as soon as the instruction that sets the bit completes execution. In stop mode the internal oscillator, CPU, and all digital peripherals are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral (including the external oscillator circuit) may be shut down individually prior to entering stop mode. Stop mode can only be terminated by an internal or external reset. On reset, the device performs the normal reset sequence and begins program execution at address 0x0000. N ew D If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the stop mode. The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the MCD timeout. 19.3. Suspend Mode fo r By default, when in stop mode the internal regulator is still active. However, the regulator can be configured to shut down while in stop mode to save power. To shut down the regulator in stop mode, the STOPCF bit in register REG01CN should be set to 1 prior to setting the STOP bit (see SFR Definition 11.1). If the regulator is shut down using the STOPCF bit, only the RST pin or a full power cycle are capable of resetting the device. m en de d Setting the SUSPEND bit (OSCICN.5) causes the hardware to halt the high-frequency internal oscillator and go into suspend mode as soon as the instruction that sets the bit completes execution. All internal registers and memory maintain their original data. The CPU is not halted in Suspend, so code can still be executed using an oscillator other than the internal High Frequency Oscillator. Most digital peripherals are not active in suspend mode. The exception to this are the USB0 Transceiver, Port Match feature, and Timer 3, when it is run from an external oscillator source or the internal low-frequency oscillator. N ot R ec om Suspend mode can be terminated by four types of events: a port match (described in Section “22.5. Port Match” on page 149), a Timer 3 overflow (described in Section “28.3. Timer 3” on page 262), resume signalling on the USB data pins, or a device reset event. Note that in order to run Timer 3 in suspend mode, the timer must be configured to clock from either the external clock source or the internal low-frequency oscillator source. When suspend mode is terminated, the device will continue execution on the instruction following the one that set the SUSPEND bit. If the wake event (USB0 resume signalling, port match, or Timer 3 overflow) was configured to generate an interrupt, the interrupt will be serviced upon waking the device. If suspend mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence and begins program execution at address 0x0000. 119 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 Bit 7 6 5 4 3 es ig ns SFR Definition 19.1. PCON: Power Control 2 1 0 Name GF[5:0] STOP IDLE Type R/W R/W R/W 0 0 0 0 0 SFR Address = 0x87 Bit Name 0 Function 0 D 0 Reset 7:2 GF[5:0] 1 STOP Stop Mode Select. Setting this bit will place the CIP-51 in stop mode. This bit will always be read as 0. 1: CPU goes into stop mode (internal oscillator stopped). 0 IDLE IDLE: Idle Mode Select. Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0. 1: CPU goes into Idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, Serial Ports, and Analog Peripherals are still active.) N ot R ec om m en de d fo r N ew General Purpose Flags 5–0. These are general purpose flags for use under software control. Rev. 1.3 120 C8051T620/1/6/7 & C8051T320/1/2/3 20. Reset Sources     CIP-51 halts program execution Special Function Registers (SFRs) are initialized to their defined reset values External Port pins are forced to a known state Interrupts and timers are disabled. es ig ns Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: D All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal data memory are unaffected during a reset; any previously stored data is preserved. However, since the stack pointer SFR is reset, the stack is effectively lost, even though the data on the stack is not altered. N ew The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled during and after the reset. For VDD Monitor and power-on resets, the RST pin is driven low until the device exits the reset state. N ot R ec om m en de d fo r On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the internal oscillator. The Watchdog Timer is enabled with the system clock divided by 12 as its clock source. Program execution begins at location 0x0000. Figure 20.1. Reset Sources Rev. 1.3 121 C8051T620/1/6/7 & C8051T320/1/2/3 20.1. Power-On Reset es ig ns During power-up, the device is held in a reset state and the RST pin is driven low until VDD settles above VRST. A delay occurs before the device is released from reset; the delay decreases as the VDD ramp time increases (VDD ramp time is defined as how fast VDD ramps from 0 V to VRST). Figure 20.2. plots the power-on and VDD monitor event timing. The maximum VDD ramp time is 1 ms; slower ramp times may cause the device to be released from reset before VDD reaches the VRST level. For ramp times less than 1 ms, the power-on reset delay (TPORDelay) is typically less than 0.3 ms. Figure 20.2. Power-On and VDD Monitor Reset Timing N ot R ec om m en de d fo r N ew D On exit from a power-on or VDD monitor reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other resets). Since all resets cause program execution to begin at the same location (0x0000) software can read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data memory should be assumed to be undefined after a power-on reset. The VDD monitor is enabled following a power-on reset. 20.2. Power-Fail Reset / VDD Monitor When a power-down transition or power irregularity causes VDD to drop below VRST, the power supply monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 20.2). When VDD returns to a level above VRST, the CIP-51 will be released from the reset state. Note that even though internal data memory contents are not altered by the power-fail reset, it is impossible to determine if VDD dropped below 122 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 es ig ns the level required for data retention. If the PORSF flag reads 1, the data may no longer be valid. The VDD monitor is enabled after power-on resets. Its defined state (enabled/disabled) is not altered by any other reset source. For example, if the VDD monitor is disabled by code and a software reset is performed, the VDD monitor will still be disabled after the reset. D Important Note: If the VDD monitor is being turned on from a disabled state, it should be enabled before it is selected as a reset source. Selecting the VDD monitor as a reset source before it is enabled and stabilized may cause a system reset. In some applications, this reset may be undesirable. If this is not desirable in the application, a delay should be introduced between enabling the monitor and selecting it as a reset source. The procedure for enabling the VDD monitor and configuring it as a reset source from a disabled state is shown below: 1. Enable the VDD monitor (VDMEN bit in VDM0CN = 1). N ew 2. If necessary, wait for the VDD monitor to stabilize (see Table 7.4 for the VDD Monitor turn-on time). 3. Select the VDD monitor as a reset source (PORSF bit in RSTSRC = 1). N ot R ec om m en de d fo r See Figure 20.2 for VDD monitor timing; note that the power-on-reset delay is not incurred after a VDD monitor reset. See Table 7.4 for complete electrical characteristics of the VDD monitor. Rev. 1.3 123 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 3 2 Name VDMEN VDDSTAT Type R/W R R R R R Reset Varies Varies Varies Varies Varies Varies SFR Address = 0xFF Bit Name VDMEN VDD Monitor Enable. 0 R R Varies Varies N ew 7 Function 1 D Bit es ig ns SFR Definition 20.1. VDM0CN: VDD Monitor Control VDDSTAT VDD Status. m en de d 6 fo r This bit turns the VDD monitor circuit on/off. The VDD Monitor cannot generate system resets until it is also selected as a reset source in register RSTSRC (SFR Definition 20.2). Selecting the VDD monitor as a reset source before it has stabilized may generate a system reset. In systems where this reset would be undesirable, a delay should be introduced between enabling the VDD Monitor and selecting it as a reset source. See Table 7.4 for the minimum VDD Monitor turn-on time. 0: VDD Monitor Disabled. 1: VDD Monitor Enabled. This bit indicates the current power supply status (VDD Monitor output). 0: VDD is at or below the VDD monitor threshold. 1: VDD is above the VDD monitor threshold. 5:0 Unused Read = Varies; Write = Don’t care. 20.3. External Reset om The external RST pin provides a means for external circuitry to force the device into a reset state. Asserting an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST pin may be necessary to avoid erroneous noise-induced resets. See Table 7.4 for complete RST pin specifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset. 20.4. Missing Clock Detector Reset R ec The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system clock remains high or low for more than the MCD time-out, a reset will be generated. After a MCD reset, the MCDRSF flag (RSTSRC.2) will read 1, signifying the MCD as the reset source; otherwise, this bit reads 0. Writing a 1 to the MCDRSF bit enables the Missing Clock Detector; writing a 0 disables it. The state of the RST pin is unaffected by this reset. N ot 20.5. Comparator0 Reset Comparator0 can be configured as a reset source by writing a 1 to the C0RSEF flag (RSTSRC.5). Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-inverting input voltage (on CP0+) is less than the inverting input voltage (on CP0-), the device is put into the reset state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read 1 signifying Comparator0 as the reset source; otherwise, this bit reads 0. The state of the RST pin is unaffected by this reset. 124 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 20.6. PCA Watchdog Timer Reset es ig ns The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be used to prevent software from running out of control during a system malfunction. The PCA WDT function can be enabled or disabled by software as described in Section “29.4. Watchdog Timer Mode” on page 279; the WDT is enabled and clocked by SYSCLK / 12 following any reset. If a system malfunction prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is set to 1. The state of the RST pin is unaffected by this reset. 20.7. EPROM Error Reset   Programming hardware attempts to write or read an EPROM location which is above the user code space address limit. An EPROM read from firmware is attempted above user code space. This occurs when a MOVC operation is attempted above the user code space address limit. A Program read is attempted above user code space. This occurs when user code attempts to branch to an address above the user code space address limit. N ew  D If an EPROM program read or write targets an illegal address, a system reset is generated. This may occur due to any of the following: 20.8. Software Reset fo r The MEMERR bit (RSTSRC.6) is set following an EPROM error reset. The state of the RST pin is unaffected by this reset. m en de d Software may force a reset by writing a 1 to the SWRSF bit (RSTSRC.4). The SWRSF bit will read 1 following a software forced reset. The state of the RST pin is unaffected by this reset. 20.9. USB Reset Writing 1 to the USBRSF bit in register RSTSRC selects USB0 as a reset source. With USB0 selected as a reset source, a system reset will be generated when either of the following occur: om 1. RESET signaling is detected on the USB network. The USB Function Controller (USB0) must be enabled for RESET signaling to be detected. See Section “23. Universal Serial Bus Controller (USB0)” on page 160 for information on the USB Function Controller. 2. A falling or rising voltage on the VBUS pin matches the edge polarity selected by the VBPOL bit in register REG01CN. See Section “11. Voltage Regulators (REG0 and REG1)” on page 61 for details on the VBUS detection circuit. N ot R ec The USBRSF bit will read 1 following a USB reset. The state of the /RST pin is unaffected by this reset. Rev. 1.3 125 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 3 2 Name USBRSF MEMERR C0RSEF SWRSF WDTRSF Type R/W R R/W R/W Reset Varies Varies Varies Varies Description USBRSF USB Reset Flag 6 MEMERR EPROM Error Reset Flag. 5 C0RSEF Comparator0 Reset Enable and Flag. 4 SWRSF 2 MCDRSF Missing Clock Detector Enable and Flag. om N ot Note: Do not use read-modify-write operations on this register 126 R/W R/W R Varies Varies Varies Varies Writing a 1 enables the Missing Clock Detector. The MCD triggers a reset if a missing clock condition is detected. Writing a 1 enables the Power-On / VDD Monitor Reset Flag, and VDD monitor VDD monitor as a reset source. Reset Enable. Writing 1 to this bit before the VDD monitor is enabled and stabilized may cause a system reset. N/A HW Pin Reset Flag. ec PINRSF R 0 R Writing a 1 enables Comparator0 as a reset source (active-low). Writing a 1 forces a system reset. WDTRSF Watchdog Timer Reset Flag. N/A PORSF PINRSF Writing a 1 enables USB as a reset source. N/A 3 1 PORSF Write m en de d Software Reset Force and Flag. MCDRSF Read Set to 1 if USB caused the last reset. Set to 1 if EPROM read/write error caused the last reset. Set to 1 if Comparator0 caused the last reset. N ew 7 0 fo r SFR Address = 0xEF Bit Name 1 D Bit es ig ns SFR Definition 20.2. RSTSRC: Reset Source Rev. 1.3 Set to 1 if last reset was caused by a write to SWRSF. Set to 1 if Watchdog Timer overflow caused the last reset. Set to 1 if Missing Clock Detector timeout caused the last reset. Set to 1 anytime a poweron or VDD monitor reset occurs. When set to 1 all other RSTSRC flags are indeterminate. Set to 1 if RST pin caused the last reset. C8051T620/1/6/7 & C8051T320/1/2/3 21. Oscillators and Clock Selection Figure 21.1. Oscillator Options N ot R ec om m en de d fo r N ew D es ig ns C8051T620/1/6/7 & C8051T320/1/2/3 devices include a programmable internal high-frequency oscillator, a programmable internal low-frequency oscillator, and an external oscillator drive circuit. The internal highfrequency oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as shown in Figure 21.1. The internal low-frequency oscillator can be enabled/disabled and calibrated using the OSCLCN register. The system clock can be sourced by the external oscillator circuit or either internal oscillator. Both internal oscillators offer a selectable post-scaling feature. The USB clock (USBCLK) can be derived from the internal oscillators or external oscillator. Rev. 1.3 127 C8051T620/1/6/7 & C8051T320/1/2/3 21.1. System Clock Selection es ig ns The CLKSL[2:0] bits in register CLKSEL select which oscillator source is used as the system clock. CLKSL[2:0] must be set to 001b for the system clock to run from the external oscillator; however the external oscillator may still clock certain peripherals (timers, PCA) when the internal oscillator is selected as the system clock. The system clock may be switched on-the-fly between the internal oscillators and external oscillator so long as the selected clock source is enabled and running. The internal high-frequency and low-frequency oscillators require little start-up time and may be selected as the system clock immediately following the register write which enables the oscillator. The external RC and C modes also typically require no startup time. D 21.2. USB Clock Selection N ew The USBCLK[2:0] bits in register CLKSEL select which oscillator source is used as the USB clock. The USB clock may be derived from the internal oscillators, a divided version of the internal High-Frequency oscillator, or a divided version of the external oscillator. Note that the USB clock must be 48 MHz when operating USB0 as a Full Speed Function; the USB clock must be 6 MHz when operating USB0 as a Low Speed Function. See SFR Definition 21.1 for USB clock selection options. Some example USB clock configurations for Full and Low Speed mode are given below: fo r USB Full Speed (48 MHz) Internal Oscillator Clock Signal USB Clock External Oscillator Input Source Selection Internal Oscillator* Divide by 1 External Oscillator Register Bit Settings USBCLK = 000b IFCN = 11b Input Source Selection External Oscillator CMOS Oscillator Mode 48 MHz Oscillator Register Bit Settings USBCLK = 010b XOSCMD = 010b m en de d Clock Signal USB Clock Internal Oscillator Note: Clock Recovery must be enabled for this configuration. om USB Low Speed (6 MHz) R ec Clock Signal USB Clock Internal Oscillator N ot Clock Signal USB Clock External Oscillator 128 Internal Oscillator Input Source Selection Internal Oscillator / 8 Divide by 1 External Oscillator Register Bit Settings USBCLK = 001b IFCN = 11b Input Source Selection External Oscillator / 4 CMOS Oscillator Mode 24 MHz Oscillator Crystal Oscillator Mode 24 MHz Oscillator Register Bit Settings USBCLK = 101b XOSCMD = 010b XOSCMD = 110b XFCN = 111b Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 Name Type R Reset 0 0 5 4 3 2 1 USBCLK[2:0] OUTCLK CLKSL[2:0] R/W R/W R/W 0 0 SFR Address = 0xA9 Bit Name 0 Function 0 0 0 0 D Bit es ig ns SFR Definition 21.1. CLKSEL: Clock Select OUTCLK 2:0 CLKSL[2:0] Crossbar Clock Out Select. If the SYSCLK signal is enabled on the Crossbar, this bit selects between outputting SYSCLK and SYSCLK synchronized with the Port I/O pins. 0: Enabling the Crossbar SYSCLK signal outputs SYSCLK. 1: Enabling the Crossbar SYSCLK signal outputs SYSCLK synchronized with the Port I/O. System Clock Source Select Bits. 000: SYSCLK derived from the Internal High-Frequency Oscillator and scaled per the IFCN bits in register OSCICN. 001: SYSCLK derived from the External Oscillator circuit. 010: SYSCLK derived from the Internal High-Frequency Oscillator / 2. 011: SYSCLK derived from the Internal High-Frequency Oscillator. 100: SYSCLK derived from the Internal Low-Frequency Oscillator and scaled per the OSCLD bits in register OSCLCN. 101-111: RESERVED. N ot R ec om 3 m en de d fo r N ew 7 Unused Read = 0b; Write = Don’t Care 6:4 USBCLK[2:0] USB Clock Source Select Bits. 000: USBCLK derived from the Internal High-Frequency Oscillator. 001: USBCLK derived from the Internal High-Frequency Oscillator / 8. 010: USBCLK derived from the External Oscillator. 011: USBCLK derived from the External Oscillator / 2. 100: USBCLK derived from the External Oscillator / 3. 101: USBCLK derived from the External Oscillator / 4. 110: USBCLK derived from the Internal Low-Frequency Oscillator. 111: RESERVED. Rev. 1.3 129 C8051T620/1/6/7 & C8051T320/1/2/3 21.3. Programmable Internal High-Frequency (H-F) Oscillator es ig ns All C8051T620/1/6/7 & C8051T320/1/2/3 devices include a programmable internal high-frequency oscillator that defaults as the system clock after a system reset. The internal oscillator period can be adjusted via the OSCICL register as defined by SFR Definition 21.2. On C8051T620/1/6/7 & C8051T320/1/2/3 devices, OSCICL is factory calibrated to obtain a 48 MHz base frequency. Note that the system clock may be derived from the programmed internal oscillator divided by 1, 2, 4, or 8 after a divide by 4 stage, as defined by the IFCN bits in register OSCICN. The divide value defaults to 8 following a reset, which results in a 1.5 MHz system clock. D 21.3.1. Internal Oscillator Suspend Mode When software writes a logic 1 to SUSPEND (OSCICN.5), the internal oscillator is suspended. If the system clock is derived from the internal oscillator, the input clock to the peripheral or CIP-51 will be stopped until one of the following events occur:    Port 0 Match Event. Port 1 Match Event. Timer3 Overflow Event. USB0 Transceiver Resume Signalling N ew  fo r When one of the oscillator awakening events occur, the internal oscillator, CIP-51, and affected peripherals resume normal operation, regardless of whether the event also causes an interrupt. The CPU resumes execution at the instruction following the write to the SUSPEND bit. m en de d Note: The prefetch engine can be turned off in suspend mode to save power. Additionally, both Voltage Regulators (REG0 and REG1) have low-power modes for additional power savings in suspend mode. See Section “13. Prefetch Engine” on page 76 and Section “11. Voltage Regulators (REG0 and REG1)” on page 61 for more information. SFR Definition 21.2. OSCICL: Internal H-F Oscillator Calibration Bit 7 om R Reset 5 4 0 Varies Varies Varies ec SFR Address = 0xB3 Bit Name 2 1 0 Varies Varies Varies R/W Varies Function Unused Read = 0; Write = Don’t Care OSCICL[6:0] Internal Oscillator Calibration Bits. These bits determine the internal oscillator period. When set to 0000000b, the H-F oscillator operates at its fastest setting. When set to 1111111b, the H-F oscillator operates at its slowest setting. The reset value is factory calibrated to generate an internal oscillator frequency of 48 MHz. N ot R 7 6:0 3 OSCICL[6:0] Name Type 6 Rev. 1.3 130 C8051T620/1/6/7 & C8051T320/1/2/3 Bit 7 6 5 4 Name IOSCEN IFRDY SUSPEND Type R/W R R/W R R R Reset 1 1 0 0 0 0 4:2 1:0 Unused IFCN[1:0] 0 0 Internal H-F Oscillator Frequency Ready Flag. 0: Internal H-F Oscillator is not running at programmed frequency. 1: Internal H-F Oscillator is running at programmed frequency. Internal Oscillator Suspend Enable Bit. Setting this bit to logic 1 places the internal oscillator in SUSPEND mode. The internal oscillator resumes operation when one of the SUSPEND mode awakening events occurs. Read = 000b; Write = Don’t Care Internal H-F Oscillator Frequency Divider Control Bits. The Internal H-F Oscillator is divided by the IFCN bit setting after a divide-by-4 stage. 00: SYSCLK can be derived from Internal H-F Oscillator divided by 8 (1.5 MHz). 01: SYSCLK can be derived from Internal H-F Oscillator divided by 4 (3 MHz). 10: SYSCLK can be derived from Internal H-F Oscillator divided by 2 (6 MHz). 11: SYSCLK can be derived from Internal H-F Oscillator divided by 1 (12 MHz). ec R N ot 131 R/W D SUSPEND 0 N ew 5 1 fo r IFRDY Internal H-F Oscillator Enable Bit. 0: Internal H-F Oscillator Disabled. 1: Internal H-F Oscillator Enabled. m en de d 6 Function om IOSCEN 2 IFCN[1:0] SFR Address = 0xB2 Bit Name 7 3 es ig ns SFR Definition 21.3. OSCICN: Internal H-F Oscillator Control Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 21.4. Clock Multiplier es ig ns The C8051T620/1/6/7 & C8051T320/1/2/3 device includes a 48 MHz high-frequency oscillator instead of a 12 MHz oscillator and a 4x Clock Multiplier, so the USB0 module can be run directly from the internal highfrequency oscillator. For compatibility with the Flash development platform, however, the CLKMUL register (SFR Definition 21.4) behaves as if the Clock Multiplier is present. SFR Definition 21.4. CLKMUL: Clock Multiplier Control Bit 7 6 5 Name MULEN MULINIT MULRDY Type R R R R Reset 1 1 1 0 6 MULINIT 5 MULRDY Description 1 0 R D R 0 R 0 Write Clock Multiplier Enable Bit. 0: Clock Multiplier disabled. 1: Clock Multiplier enabled. This bit always reads 1. Clock Multiplier Initialize This bit should be a 0 Bit. when the Clock Multiplier is enabled. Once enabled, writing a 1 to this bit will initialize the Clock Multiplier. Clock Multiplier Ready Bit. 0: Clock Multiplier not ready. 1: Clock Multiplier ready (locked). This bit always reads 1. Read = 000b; Write = Don’t Care fo r MULEN 2 MULSEL[1:0] m en de d 7 3 N ew SFR Address = 0xB9 Bit Name 4 0 0 Read The MULRDY bit reads 1 when the Clock Multiplier is stabilized. This bit always reads 1. N ot R ec om 4:2 Unused 1:0 MULSEL[1:0] Clock Multiplier Input Select Bits. These bits select the clock supplied to the Clock Multiplier. 00: Internal High-Frequency Oscillator 01: External Oscillator 10: External Oscillator/2 11: Reserved. These bits always read 00. Rev. 1.3 132 C8051T620/1/6/7 & C8051T320/1/2/3 21.5. Programmable Internal Low-Frequency (L-F) Oscillator es ig ns All C8051T620/1/6/7 & C8051T320/1/2/3 devices include a programmable low-frequency internal oscillator, which is calibrated to a nominal frequency of 80 kHz. The low-frequency oscillator circuit includes a divider that can be changed to divide the clock by 1, 2, 4, or 8, using the OSCLD bits in the OSCLCN register (see SFR Definition 21.5). Additionally, the OSCLF[3:0] bits can be used to adjust the oscillator’s output frequency. N ew D 21.5.1. Calibrating the Internal L-F Oscillator Timers 2 and 3 include capture functions that can be used to capture the oscillator frequency, when running from a known time base. When either Timer 2 or Timer 3 is configured for L-F Oscillator Capture Mode, a falling edge (Timer 2) or rising edge (Timer 3) of the low-frequency oscillator’s output will cause a capture event on the corresponding timer. As a capture event occurs, the current timer value (TMRnH:TMRnL) is copied into the timer reload registers (TMRnRLH:TMRnRLL). By recording the difference between two successive timer capture values, the low-frequency oscillator’s period can be calculated. The OSCLF bits can then be adjusted to produce the desired oscillator frequency. SFR Definition 21.5. OSCLCN: Internal L-F Oscillator Control 6 Name OSCLEN OSCLRDY Type R/W R Reset 0 0 5 4 3 Varies 6 OSCLRDY 0 OSCLD[1:0] R.W R/W Varies Varies Varies 0 0 Function Internal L-F Oscillator Enable. 0: Internal L-F Oscillator Disabled. 1: Internal L-F Oscillator Enabled. Internal L-F Oscillator Ready. 0: Internal L-F Oscillator frequency not stabilized. 1: Internal L-F Oscillator frequency stabilized. om OSCLEN 1 OSCLF[3:0] SFR Address = 0x86 Bit Name 7 2 fo r 7 m en de d Bit Note: OSCLRDY is only set back to 0 in the event of a device reset or a change to the OSCLD[1:0] bits. OSCLF[3:0] Internal L-F Oscillator Frequency Control Bits. Fine-tune control bits for the Internal L-F oscillator frequency. When set to 0000b, the L-F oscillator operates at its fastest setting. When set to 1111b, the L-F oscillator operates at its slowest setting. R ec 5:2 N ot 1:0 OSCLD[1:0] Internal L-F Oscillator Divider Select. 00: Divide by 8 selected. 01: Divide by 4 selected. 10: Divide by 2 selected. 11: Divide by 1 selected. Rev. 1.3 133 C8051T620/1/6/7 & C8051T320/1/2/3 21.6. External Oscillator Drive Circuit es ig ns The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor, or RC network. A CMOS clock may also provide a clock input. Figure 21.1 shows a block diagram of the four external oscillator options. The external oscillator is enabled and configured using the OSCXCN register (see SFR Definition 21.6). N ew D Important Note on External Oscillator Usage: Port pins must be configured when using the external oscillator circuit. When the external oscillator drive circuit is enabled in crystal/resonator mode, Port pins P0.2 and P0.3 are used as XTAL1 and XTAL2, respectively. When the external oscillator drive circuit is enabled in capacitor, RC, or CMOS clock mode, Port pin P0.3 is used as XTAL2. The Port I/O Crossbar should be configured to skip the Port pin used by the oscillator circuit; see Section “22.3. Priority Crossbar Decoder” on page 142 for Crossbar configuration. Additionally, when using the external oscillator circuit in crystal/resonator, capacitor, or RC mode, the associated Port pins should be configured as analog inputs. In CMOS clock mode, the associated pin should be configured as a digital input. See Section “22.4. Port I/O Initialization” on page 146 for details on Port input mode selection. The external oscillator output may be selected as the system clock or used to clock some of the digital peripherals (e.g. Timers, PCA, etc.). See the data sheet chapters for each digital peripheral for details. See Section “7. Electrical Characteristics” on page 34 for complete oscillator specifications. fo r 21.6.1. External Crystal Mode If a crystal or ceramic resonator is used as the external oscillator, the crystal/resonator and a 10 Mresistor must be wired across the XTAL1 and XTAL2 pins as shown in Figure 21.1, “Crystal Mode”. Appropriate loading capacitors should be added to XTAL1 and XTAL2, and both pins should be configured for analog I/O with the digital output drivers disabled. m en de d The capacitors shown in the external crystal configuration provide the load capacitance required by the crystal for correct oscillation. These capacitors are “in series” as seen by the crystal and “in parallel” with the stray capacitance of the XTAL1 and XTAL2 pins. Note: The recommended load capacitance depends upon the crystal and the manufacturer. Please refer to the crystal data sheet when completing these calculations. The equation for determining the load capacitance for two capacitors is CA  CB C L = -------------------- + CS CA + CB ec om Where: CA and CB are the capacitors connected to the crystal leads. CS is the total stray capacitance of the PCB. The stray capacitance for a typical layout where the crystal is as close as possible to the pins is 2-5 pF per pin. C C L = ---- + C S 2 N ot R If CA and CB are the same (C), then the equation becomes For example, a tuning-fork crystal of 32 kHz with a recommended load capacitance of 12.5 pF should use the configuration shown in Figure 21.1, Option 1. With a stray capacitance of 3 pF per pin (6 pF total), the 13 pF capacitors yield an equivalent capacitance of 12.5 pF across the crystal, as shown in Figure 21.2. Rev. 1.3 134 D es ig ns C8051T620/1/6/7 & C8051T320/1/2/3 N ew Figure 21.2. External Crystal Example Important Note on External Crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The crystal should be placed as close as possible to the XTAL pins on the device. The traces should be as short as possible and shielded with ground plane from any other traces which could introduce noise or interference. m en de d fo r When using an external crystal, the external oscillator drive circuit must be configured by software for Crystal Oscillator Mode or Crystal Oscillator Mode with divide by 2 stage. The divide by 2 stage ensures that the clock derived from the external oscillator has a duty cycle of 50%. The External Oscillator Frequency Control value (XFCN) must also be specified based on the crystal frequency (see SFR Definition 21.6). When the crystal oscillator is first enabled, the external oscillator valid detector allows software to determine when the external system clock is valid and running. Switching to the external oscillator before the crystal oscillator has stabilized can result in unpredictable behavior. The recommended procedure for starting the crystal is: N ot R ec om 1. Configure XTAL1 and XTAL2 for analog I/O. 2. Disable the XTAL1 and XTAL2 digital output drivers by writing 1s to the appropriate bits in the Port Latch register. 3. Configure and enable the external oscillator. 4. Wait at least 1 ms. 5. Poll for XTLVLD => '1'. 6. Switch the system clock to the external oscillator. 135 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 es ig ns 21.6.2. External RC Example If an RC network is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 21.1, “RC Mode”. The capacitor should be no greater than 100 pF; however, for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To determine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, first select the RC network value to produce the desired frequency of oscillation, according to Equation , where f = the frequency of oscillation in MHz, C = the capacitor value in pF, and R = the pull-up resistor value in k. 3 D f = 1.23  10   R  C  Equation 21.1. RC Mode Oscillator Frequency N ew For example: If the frequency desired is 100 kHz, let R = 246 k and C = 50 pF: f = 1.23( 103 ) / RC = 1.23 ( 103 ) / [ 246 x 50 ] = 0.1 MHz = 100 kHz Referring to the table in SFR Definition 21.6, the required XFCN setting is 010b. m en de d fo r 21.6.3. External Capacitor Example If a capacitor is used as an external oscillator for the MCU, the circuit should be configured as shown in Figure 21.1, “C Mode”. The capacitor should be no greater than 100 pF; however, for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To determine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, select the capacitor to be used and find the frequency of oscillation according to Equation , where f = the frequency of oscillation in MHz, C = the capacitor value in pF, and VDD = the MCU power supply in Volts. f =  KF    C  V DD  Equation 21.2. C Mode Oscillator Frequency For example: Assume VDD = 3.0 V and f = 150 kHz: f = KF / (C x VDD) 0.150 MHz = KF / (C x 3.0) om Since the frequency of roughly 150 kHz is desired, select the K Factor from the table in SFR Definition 21.6 (OSCXCN) as KF = 22: ec 0.150 MHz = 22 / (C x 3.0) C x 3.0 = 22 / 0.150 MHz C = 146.6 / 3.0 pF = 48.8 pF N ot R Therefore, the XFCN value to use in this example is 011b and C = 50 pF. Rev. 1.3 136 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 Name XCLKVLD Type R Reset 0 0 5 4 3 0 - XFCN[2:0] R/W R R/W 0 0 0 0 Function 0 0 External Oscillator Valid Flag. Provides External Oscillator status and is valid at all times for all modes of operation except External CMOS Clock Mode and External CMOS Clock Mode with divide by 2. In these modes, XCLKVLD always returns 0. 0: External Oscillator is unused or not yet stable. 1: External Oscillator is running and stable. N ew XCLKVLD 1 XOSCMD[2:0] SFR Address = 0xB1 Bit Name 7 2 D Bit es ig ns SFR Definition 21.6. OSCXCN: External Oscillator Control fo r XOSCMD[2:0] External Oscillator Mode Select. 00x: External Oscillator circuit off. 010: External CMOS Clock Mode. 011: External CMOS Clock Mode with divide by 2 stage. 100: RC Oscillator Mode. 101: Capacitor Oscillator Mode. 110: Crystal Oscillator Mode. 111: Crystal Oscillator Mode with divide by 2 stage. Unused 2:0 XFCN[2:0] External Oscillator Frequency Control Bits. Set according to the desired frequency for RC mode. Set according to the desired K Factor for C mode. Crystal Mode RC Mode C Mode 000 f 20 kHz f 25 kHz K Factor = 0.87 001 20 kHz f 58 kHz 25 kHz f 50 kHz K Factor = 2.6 010 58 kHz f 155 kHz 50 kHz f 100 kHz K Factor = 7.7 011 155 kHz f 415 kHz 100 kHz f 200 kHz K Factor = 22 100 415 kHz f 1.1 MHz 200 kHz f 400 kHz K Factor = 65 101 1.1 MHz f 3.1 MHz 400 kHz f 800 kHz K Factor = 180 110 3.1 MHz f 8.2 MHz 800 kHz f 1.6 MHz K Factor = 664 111 8.2 MHz f 25 MHz 1.6 MHz f 3.2 MHz K Factor = 1590 ec XFCN R N ot 137 Read = 0; Write = Don’t Care om 3 m en de d 6:4 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 22. Port Input/Output es ig ns Digital and analog resources are available through 21, 24, or 25 I/O pins, depending on the specific device. Port pins P0.0-P2.7 can be defined as general-purpose I/O (GPIO), assigned to one of the internal digital resources, or assigned to an analog function as shown in Figure 22.3. Port pin P3.0 on can be used as GPIO and is shared with the C2 Interface Data signal (C2D). The designer has complete control over which functions are assigned, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder. Note that the state of a Port I/O pin can always be read in the corresponding Port latch, regardless of the Crossbar settings. D The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder (Figure 22.4). The registers XBR0, XBR1, and XBR2, defined in SFR Definition 22.1, SFR Definition 22.2, and SFR Definition 22.2, are used to select internal digital functions. N ot R ec om m en de d fo r N ew All Port I/Os are 5 V tolerant (refer to Figure 22.2 for the Port cell circuit). The Port I/O cells are configured as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1). Complete Electrical Specifications for Port I/O are given in Table 7.3 on page 36. Figure 22.1. Port I/O Functional Block Diagram Rev. 1.3 138 C8051T620/1/6/7 & C8051T320/1/2/3 22.1. Port I/O Modes of Operation es ig ns Port pins use the Port I/O cell shown in Figure 22.2. Each Port I/O cell can be configured by software for analog I/O or digital I/O using the PnMDIN registers. On reset, all Port I/O cells default to a high impedance state with weak pull-ups enabled until the Crossbar is enabled (XBARE = 1). 22.1.1. Port Pins Configured for Analog I/O Any pins to be used as Comparator or ADC input, external oscillator input/output, or VREF should be configured for analog I/O (PnMDIN.n = 1). When a pin is configured for analog I/O, its weak pullup, digital driver, and digital receiver are disabled. Port pins configured for analog I/O will always read back a value of 0. D Configuring pins as analog I/O saves power and isolates the Port pin from digital interference. Port pins configured as digital inputs may still be used by analog peripherals; however, this practice is not recommended and may result in measurement errors. N ew 22.1.2. Port Pins Configured For Digital I/O Any pins to be used by digital peripherals (UART, SPI, SMBus, etc.), external digital event capture functions, or as GPIO should be configured as digital I/O (PnMDIN.n = 1). For digital I/O pins, one of two output modes (push-pull or open-drain) must be selected using the PnMDOUT registers. fo r Push-pull outputs (PnMDOUT.n = 1) drive the Port pad to the VIO or GND supply rails based on the output logic value of the Port pin. Open-drain outputs have the high side driver disabled; therefore, they only drive the Port pad to GND when the output logic value is 0 and become high impedance inputs (both high and low drivers turned off) when the output logic value is 1. N ot R ec om m en de d When a digital I/O cell is placed in the high impedance state, a weak pull-up transistor pulls the Port pad to the VDD supply voltage to ensure the digital input is at a defined logic state. Weak pull-ups are disabled when the I/O cell is driven to GND to minimize power consumption and may be globally disabled by setting WEAKPUD to 1. The user should ensure that digital I/O are always internally or externally pulled or driven to a valid logic state to minimize power consumption. Port pins configured for digital I/O always read back the logic state of the Port pad, regardless of the output logic value of the Port pin. Figure 22.2. Port I/O Cell Block Diagram 139 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 es ig ns 22.1.3. Interfacing Port I/O to 5 V Logic All Port I/O configured for digital, open-drain operation are capable of interfacing to digital logic operating at a supply voltage higher than VIO and less than 5.25 V. An external pull-up resistor to the higher supply voltage is typically required for most systems. Important Note: In a multi-voltage interface, the external pull-up resistor should be sized to allow a current of at least 150 uA to flow into the Port pin when the supply voltage is between (VIO + 0.6V) and (VIO + 1.0 V). Once the Port pin voltage increases beyond this range, the current flowing into the Port pin is minimal. 22.2. Assigning Port I/O Pins to Analog and Digital Functions D Port I/O pins can be assigned to various analog, digital, and external interrupt functions. The Port pins assigned to analog functions should be configured for analog I/O, and Port pins assigned to digital or external interrupt functions should be configured for digital I/O. N ew 22.2.1. Assigning Port I/O Pins to Analog Functions Table 22.1 shows all available analog functions that require Port I/O assignments. Port pins selected for these analog functions should have their corresponding bit in PnSKIP set to 1. This reserves the pin for use by the analog function and does not allow it to be claimed by the Crossbar. Table 22.1 shows the potential mapping of Port I/O to each analog function. fo r Table 22.1. Port I/O Assignment for Analog Functions ADC Input Comparator Input Potentially Assignable Port Pins m en de d Analog Function SFR(s) used for Assignment P0.0, P0.1, P0.4, P0.5, P1.0- P3.0 AMX0P, PnSKIP P0.0, P0.1, P0.4, P0.5, P1.0-P1.7, P2.0-P2.5 CPT0MX, CPT1MX, PnSKIP P0.7 REF0CN, PnSKIP P0.2, P0.3 OSCXCN, PnSKIP P0.3 OSCXCN, PnSKIP Voltage Reference (VREF0) External Oscillator in Crystal Mode (XTAL1, XTAL2) om External Oscillator in RC or C Mode (XTAL2) N ot R ec 22.2.2. Assigning Port I/O Pins to Digital Functions Any Port pins not assigned to analog functions may be assigned to digital functions or used as GPIO. Most digital functions rely on the Crossbar for pin assignment; however, some digital functions bypass the Crossbar in a manner similar to the analog functions listed above. Port pins used by these digital functions and any Port pins selected for use as GPIO should have their corresponding bit in PnSKIP set to 1. Table 22.2 shows all available digital functions and the potential mapping of Port I/O to each digital function. Rev. 1.3 140 C8051T620/1/6/7 & C8051T320/1/2/3 Table 22.2. Port I/O Assignment for Digital Functions UART0, SPI0, SMBus, CP0, CP0A, CP1, CP1A, SYSCLK, PCA0 (CEX0-4 and ECI), T0, T1, or UART1. Any pin used for GPIO Any Port pin available for assignment by the Crossbar. This includes P0.0 - P2.6 pins which have their PnSKIP bit set to 0. Note: The Crossbar will always assign UART0 pins to P0.4 and P0.5. P0.0 - P3.0 SFR(s) used for Assignment es ig ns Potentially Assignable Port Pins XBR0, XBR1, XBR2 PnSKIP D Digital Function N ot R ec om m en de d fo r N ew 22.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions External digital event capture functions can be used to trigger an interrupt or wake the device from a low power mode when a transition occurs on a digital I/O pin. The digital event capture functions do not require dedicated pins and will function on both GPIO pins (PnSKIP = 1) and pins in use by the Crossbar (PnSKIP = 0). External digital event capture functions cannot be used on pins configured for analog I/O. Table 22.3 shows all available external digital event capture functions. 141 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 Table 22.3. Port I/O Assignment for External Digital Event Capture Functions Potentially Assignable Port Pins P0.0 - P0.7 External Interrupt 1 P0.0 - P0.7 Port Match P0.0 - P1.7 IT01CF IT01CF P0MASK, P0MAT P1MASK, P1MAT D External Interrupt 0 SFR(s) used for Assignment es ig ns Digital Function 22.3. Priority Crossbar Decoder N ew The Priority Crossbar Decoder assigns a priority to each I/O function, starting at the top with UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that resource (excluding UART0, which is always at pins 4 and 5). If a Port pin is assigned, the Crossbar skips that pin when assigning the next selected resource. Additionally, the Crossbar will skip Port pins whose associated bits in the PnSKIP registers are set. The PnSKIP registers allow software to skip Port pins that are to be used for analog input, dedicated functions, or GPIO. fo r Because of the nature of the Priority Crossbar Decoder, not all peripherals can be located on all port pins. Figure 22.3 shows the possible pins on which peripheral I/O can appear. m en de d Important Note on Crossbar Configuration: If a Port pin is claimed by a peripheral without use of the Crossbar, its corresponding PnSKIP bit should be set. The Crossbar skips selected pins as if they were already assigned, and moves to the next unassigned pin. Registers XBR0, XBR1, and XBR2 are used to assign the digital I/O resources to the physical I/O Port pins. Note that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus (SDA and SCL); when a UART is selected, the Crossbar assigns both pins associated with the UART (TX and RX). UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned to P0.4; UART RX0 is always assigned to P0.5. Standard Port I/Os appear contiguously after the prioritized functions have been assigned. Figure 22.4 and Figure 22.5 show examples of how the crossbar assigns peripherals according to the XBRn and PnSKIP register settings. N ot R ec om Important Note: The SPI can be operated in either 3-wire or 4-wire modes, pending the state of the NSSMD1–NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not be routed to a Port pin. Rev. 1.3 142 N ot R ec om m en de d fo r N ew D es ig ns C8051T620/1/6/7 & C8051T320/1/2/3 143 Figure 22.3. Priority Crossbar Decoder Potential Pin Assignments Rev. 1.3 N ot R ec om m en de d fo r N ew D es ig ns C8051T620/1/6/7 & C8051T320/1/2/3 Figure 22.4. Priority Crossbar Decoder Example 1—No Skipped Pins Rev. 1.3 144 N ot R ec om m en de d fo r N ew D es ig ns C8051T620/1/6/7 & C8051T320/1/2/3 Figure 22.5. Priority Crossbar Decoder Example 2—Skipping Pins 145 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 22.4. Port I/O Initialization Port I/O initialization consists of the following steps: N ew D es ig ns 1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN). 2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port Output Mode register (PnMDOUT). 3. Select any pins to be skipped by the I/O Crossbar using the Port Skip registers (PnSKIP). 4. Assign Port pins to desired peripherals (XBR0, XBR1, XBR2). 5. Enable the Crossbar (XBARE = 1). All Port pins must be configured as either analog or digital inputs. Any pins to be used as Comparator or ADC inputs should be configured as an analog inputs. When a pin is configured as an analog input, its weak pullup, digital driver, and digital receiver are disabled. This process saves power and reduces noise on the analog input. Pins configured as digital inputs may still be used by analog peripherals; however this practice is not recommended. Additionally, all analog input pins should be configured to be skipped by the Crossbar (accomplished by setting the associated bits in PnSKIP). Port input mode is set in the PnMDIN register, where a 1 indicates a digital input, and a 0 indicates an analog input. All pins default to digital inputs on reset. See SFR Definition 22.9, SFR Definition 22.13, and SFR Definition 22.17 for the PnMDIN register details. m en de d fo r The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMDOUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is required even for the digital resources selected in the XBRn registers, and is not automatic. The only exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the PnMDOUT settings. When the WEAKPUD bit in XBR1 is 0, a weak pullup is enabled for all Port I/O configured as open-drain. WEAKPUD does not affect the push-pull Port I/O. Furthermore, the weak pullup is turned off on an output that is driving a 0 to avoid unnecessary power dissipation. Registers XBR0, XBR1, and XBR2 must be loaded with the appropriate values to select the digital I/O functions required by the design. Setting the XBARE bit in XBR1 to 1 enables the Crossbar. Until the Crossbar is enabled, the external pins remain as standard Port I/O (in input mode), regardless of the XBRn Register settings. For given XBRn Register settings, one can determine the I/O pin-out using the Priority Decode Table; as an alternative, the Configuration Wizard utility of the Silicon Labs IDE software will determine the Port I/O pin-assignments based on the XBRn Register settings. N ot R ec om The Crossbar must be enabled to use Port pins as standard Port I/O in output mode. Port output drivers are disabled while the Crossbar is disabled. Rev. 1.3 146 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 3 2 Name CP1AE CP1E CP0AE CP0E SYSCKE Type R/W R/W R/W R/W Reset 0 0 0 0 SFR Address = 0xE1 Bit Name CP1E 5 CP0AE 4 CP0E 3 SPI0E URT0E R/W R/W R/W R/W 0 0 0 0 Function Comparator1 Asynchronous Output Enable. 0: Asynchronous CP1 unavailable at Port pin. 1: Asynchronous CP1 routed to Port pin. N ew 6 SMB0E Comparator1 Output Enable. 0: CP1 unavailable at Port pin. 1: CP1 routed to Port pin. fo r CP1AE 0 Comparator0 Asynchronous Output Enable. 0: Asynchronous CP0 unavailable at Port pin. 1: Asynchronous CP0 routed to Port pin. m en de d 7 1 Comparator0 Output Enable. 0: CP0 unavailable at Port pin. 1: CP0 routed to Port pin. SYSCKE /SYSCLK Output Enable. The source of this signal is determined by the OUTCLK bit (see SFR Definition 21.1). 0: /SYSCLK unavailable at Port pin. 1: /SYSCLK output routed to Port pin. SMB0E 1 SPI0E SMBus I/O Enable. 0: SMBus I/O unavailable at Port pins. 1: SMBus I/O routed to Port pins. om 2 SPI I/O Enable. 0: SPI I/O unavailable at Port pins. 1: SPI I/O routed to Port pins. Note that the SPI can be assigned either 3 or 4 GPIO pins. ec R N ot 0 147 D Bit es ig ns SFR Definition 22.1. XBR0: Port I/O Crossbar Register 0 URT0E UART I/O Output Enable. 0: UART I/O unavailable at Port pin. 1: UART TX0, RX0 routed to Port pins P0.4 and P0.5. Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 7 Name WEAKPUD 6 5 4 3 XBARE T1E T0E ECIE PCA0ME[2:0] R/W Type R/W R/W R/W R/W R/W Reset 0 0 0 0 0 SFR Address = 0xE2 Bit Name XBARE 5 T1E 4 T0E 3 ECIE 0 0 Port I/O Weak Pullup Disable. 0: Weak Pullups enabled (except for Ports whose I/O are configured for analog mode). 1: Weak Pullups disabled. N ew 6 0 0 Crossbar Enable. 0: Crossbar disabled. 1: Crossbar enabled. T1 Enable. 0: T1 unavailable at Port pin. 1: T1 routed to Port pin. fo r WEAKPUD 1 m en de d 7 Function 2 D Bit es ig ns SFR Definition 22.2. XBR1: Port I/O Crossbar Register 1 T0 Enable. 0: T0 unavailable at Port pin. 1: T0 routed to Port pin. PCA0 External Counter Input Enable. 0: ECI unavailable at Port pin. 1: ECI routed to Port pin. N ot R ec om 2:0 PCA0ME[2:0] PCA Module I/O Enable Bits. 000: All PCA I/O unavailable at Port pins. 001: CEX0 routed to Port pin. 010: CEX0, CEX1 routed to Port pins. 011: CEX0, CEX1, CEX2 routed to Port pins. 100: CEX0, CEX1, CEX2, CEX3 routed to Port pins. 101: CEX0, CEX1, CEX2, CEX3, CEX4 routed to Port pins. 110-111: Reserved. Rev. 1.3 148 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 3 2 Name Type R R R R R R Reset 0 0 0 0 0 0 SFR Address = 0xE3 Bit Name 1 Reserved 0 URT1E Read = 0000000b; Write = Don’t Care. Reserved URT1E R/W R/W 0 0 N ew Unused 0 Must write 0. UART1 I/O Output Enable Bit. 0: UART1 I/O unavailable at Port pins. 1: UART1 TX1, RX1 routed to Port pins. 22.5. Port Match fo r 7:2 Function 1 D Bit es ig ns SFR Definition 22.3. XBR2: Port I/O Crossbar Register 2 m en de d Port match functionality allows system events to be triggered by a logic value change on P0 or P1. A software controlled value stored in the PnMATCH registers specifies the expected or normal logic values of P0 and P1. A Port mismatch event occurs if the logic levels of the Port’s input pins no longer match the software controlled value. This allows Software to be notified if a certain change or pattern occurs on P0 or P1 input pins regardless of the XBRn settings. The PnMASK registers can be used to individually select which P0 and P1 pins should be compared against the PnMATCH registers. A Port mismatch event is generated if (P0 & P0MASK) does not equal (P0MATCH & P0MASK) or if (P1 & P1MASK) does not equal (P1MATCH & P1MASK). N ot R ec om A Port mismatch event may be used to generate an interrupt or wake the device from a low power mode, such as IDLE or SUSPEND. See the Interrupts and Power Options chapters for more details on interrupt and wake-up sources. 149 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 3 Name P0MASK[7:0] Type R/W Reset 0 0 0 0 0 SFR Address = 0xAE Bit Name P0MASK[7:0] 0 1 0 0 0 Function Port 0 Mask Value. Selects P0 pins to be compared to the corresponding bits in P0MAT. 0: P0.n pin logic value is ignored and cannot cause a Port Mismatch event. 1: P0.n pin logic value is compared to P0MAT.n. N ew 7:0 2 D Bit es ig ns SFR Definition 22.4. P0MASK: Port 0 Mask Register 7 Name 6 5 4 3 m en de d Bit fo r SFR Definition 22.5. P0MAT: Port 0 Match Register 1 0 1 1 1 P0MAT[7:0] Type R/W Reset 1 1 1 1 SFR Address = 0x84 Bit Name P0MAT[7:0] 1 Function Port 0 Match Value. Match comparison value used on Port 0 for bits in P0MASK which are set to 1. 0: P0.n pin logic value is compared with logic LOW. 1: P0.n pin logic value is compared with logic HIGH. N ot R ec om 7:0 2 Rev. 1.3 150 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 3 Name P1MASK[7:0] Type R/W Reset 0 0 0 0 0 SFR Address = 0xBA Bit Name P1MASK[7:0] 0 1 0 0 0 Function Port 1 Mask Value. Selects P1 pins to be compared to the corresponding bits in P1MAT. 0: P1.n pin logic value is ignored and cannot cause a Port Mismatch event. 1: P1.n pin logic value is compared to P1MAT.n. N ew 7:0 2 D Bit es ig ns SFR Definition 22.6. P1MASK: Port 1 Mask Register 7 Name 6 5 4 3 m en de d Bit fo r SFR Definition 22.7. P1MAT: Port 1 Match Register 0 1 1 1 R/W Reset 1 1 1 1 SFR Address = 0xB6 Bit Name 1 Function Port 1 Match Value. Match comparison value used on Port 1 for bits in P1MASK which are set to 1. 0: P1.n pin logic value is compared with logic LOW. 1: P1.n pin logic value is compared with logic HIGH. R ec om P1MAT[7:0] N ot 151 1 P1MAT[7:0] Type 7:0 2 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 22.6. Special Function Registers for Accessing and Configuring Port I/O es ig ns All Port I/O are accessed through corresponding special function registers (SFRs) that are both byte addressable and bit addressable. When writing to a Port, the value written to the SFR is latched to maintain the output data value at each pin. When reading, the logic levels of the Port's input pins are returned regardless of the XBRn settings (i.e., even when the pin is assigned to another signal by the Crossbar, the Port register can always read its corresponding Port I/O pin). The exception to this is the execution of the read-modify-write instructions that target a Port Latch register as the destination. The read-modify-write instructions when operating on a Port SFR are the following: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ and MOV, CLR or SETB, when the destination is an individual bit in a Port SFR. For these instructions, the value of the latch register (not the pin) is read, modified, and written back to the SFR. D Each Port has a corresponding PnSKIP register which allows its individual Port pins to be assigned to digital functions or skipped by the Crossbar. All Port pins used for analog functions or GPIO should have their PnSKIP bit set to 1. N ew The Port input mode of the I/O pins is defined using the Port Input Mode registers (PnMDIN). Each Port cell can be configured for analog or digital I/O. This selection is required even for the digital resources selected in the XBRn registers, and is not automatic. The only exception to this is P3.0, which can only be used for digital I/O. m en de d fo r The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMDOUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is required even for the digital resources selected in the XBRn registers, and is not automatic. The only exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the PnMDOUT settings. SFR Definition 22.8. P0: Port 0 Bit 7 6 Name 5 4 2 1 0 1 1 1 1 P0[7:0] Type R/W 1 1 om Reset 1 1 SFR Address = 0x80; Bit-Addressable Bit Name Description P0[7:0] Port 0 Data. Sets the Port latch logic value or reads the Port pin logic state in Port cells configured for digital I/O. Write 0: Set output latch to logic LOW. 1: Set output latch to logic HIGH. Read 0: P0.n Port pin is logic LOW. 1: P0.n Port pin is logic HIGH. N ot R ec 7:0 3 Rev. 1.3 152 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 3 Name P0MDIN[7:0] Type R/W Reset 1 1 1 1 1 SFR Address = 0xF1 Bit Name P0MDIN[7:0] 1 1 0 1 1 Function Analog Configuration Bits for P0.7–P0.0 (respectively). Port pins configured for analog mode have their weak pullup, digital driver, and digital receiver disabled. 0: Corresponding P0.n pin is configured for analog mode. 1: Corresponding P0.n pin is not configured for analog mode. fo r N ew 7:0 2 D Bit es ig ns SFR Definition 22.9. P0MDIN: Port 0 Input Mode SFR Definition 22.10. P0MDOUT: Port 0 Output Mode 7 Name 6 5 4 m en de d Bit 3 2 1 0 0 0 0 P0MDOUT[7:0] Type R/W Reset 0 0 0 0 SFR Address = 0xA4 Bit Name 0 Function N ot R ec om 7:0 P0MDOUT[7:0] Output Configuration Bits for P0.7–P0.0 (respectively). These bits are ignored if the corresponding bit in register P0MDIN is logic 0. 0: Corresponding P0.n Output is open-drain. 1: Corresponding P0.n Output is push-pull. 153 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 3 Name P0SKIP[7:0] Type R/W Reset 0 0 0 0 0 SFR Address = 0xD4 Bit Name P0SKIP[7:0] 0 1 0 0 0 Function Port 0 Crossbar Skip Enable Bits. These bits select Port 0 pins to be skipped by the Crossbar Decoder. Port pins used for analog, special functions or GPIO should be skipped by the Crossbar. 0: Corresponding P0.n pin is not skipped by the Crossbar. 1: Corresponding P0.n pin is skipped by the Crossbar. SFR Definition 22.12. P1: Port 1 7 6 Name 5 4 m en de d Bit fo r N ew 7:0 2 D Bit es ig ns SFR Definition 22.11. P0SKIP: Port 0 Skip 2 1 0 1 1 1 1 P1[7:0] Type R/W Reset 1 1 1 1 SFR Address = 0x90; Bit-Addressable Bit Name Description P1[7:0] Port 1 Data. Sets the Port latch logic value or reads the Port pin logic state in Port cells configured for digital I/O. Write 0: Set output latch to logic LOW. 1: Set output latch to logic HIGH. Read 0: P1.n Port pin is logic LOW. 1: P1.n Port pin is logic HIGH. N ot R ec om 7:0 3 Rev. 1.3 154 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 3 Name P1MDIN[7:0] Type R/W Reset 1 1 1 1 1 SFR Address = 0xF2 Bit Name P1MDIN[7:0] 1 1 0 1 1 Function Analog Configuration Bits for P1.7–P1.0 (respectively). Port pins configured for analog mode have their weak pullup, digital driver, and digital receiver disabled. 0: Corresponding P1.n pin is configured for analog mode. 1: Corresponding P1.n pin is not configured for analog mode. fo r N ew 7:0 2 D Bit es ig ns SFR Definition 22.13. P1MDIN: Port 1 Input Mode SFR Definition 22.14. P1MDOUT: Port 1 Output Mode 7 Name 6 5 4 m en de d Bit 3 2 1 0 0 0 0 P1MDOUT[7:0] Type R/W Reset 0 0 0 0 SFR Address = 0xA5 Bit Name 0 Function N ot R ec om 7:0 P1MDOUT[7:0] Output Configuration Bits for P1.7–P1.0 (respectively). These bits are ignored if the corresponding bit in register P1MDIN is logic 0. 0: Corresponding P1.n Output is open-drain. 1: Corresponding P1.n Output is push-pull. 155 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 3 Name P1SKIP[7:0] Type R/W Reset 0 0 0 0 0 SFR Address = 0xD5 Bit Name P1SKIP[7:0] 0 1 0 0 0 Function Port 1 Crossbar Skip Enable Bits. These bits select Port 1 pins to be skipped by the Crossbar Decoder. Port pins used for analog, special functions or GPIO should be skipped by the Crossbar. 0: Corresponding P1.n pin is not skipped by the Crossbar. 1: Corresponding P1.n pin is skipped by the Crossbar. SFR Definition 22.16. P2: Port 2 7 6 Name 5 4 m en de d Bit fo r N ew 7:0 2 D Bit es ig ns SFR Definition 22.15. P1SKIP: Port 1 Skip 2 1 0 1 1 1 1 P2[7:0] Type R/W Reset 1 1 1 1 SFR Address = 0xA0; Bit-Addressable Bit Name Description P2[7:0] Port 2 Data. Sets the Port latch logic value or reads the Port pin logic state in Port cells configured for digital I/O. Write 0: Set output latch to logic LOW. 1: Set output latch to logic HIGH. Read 0: P2.n Port pin is logic LOW. 1: P2.n Port pin is logic HIGH. N ot R ec om 7:0 3 Rev. 1.3 156 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 3 Name P2MDIN[7:0] Type R/W Reset 1 1 1 1 1 SFR Address = 0xF3 Bit Name P2MDIN[7:0] 1 1 0 1 1 Function Analog Configuration Bits for P2.7–P2.0 (respectively). Port pins configured for analog mode have their weak pullup, digital driver, and digital receiver disabled. 0: Corresponding P2.n pin is configured for analog mode. 1: Corresponding P2.n pin is not configured for analog mode. fo r N ew 7:0 2 D Bit es ig ns SFR Definition 22.17. P2MDIN: Port 2 Input Mode SFR Definition 22.18. P2MDOUT: Port 2 Output Mode 7 Name 6 5 4 m en de d Bit 3 2 1 0 0 0 0 P2MDOUT[7:0] Type R/W Reset 0 0 0 0 SFR Address = 0xA6 Bit Name 0 Function N ot R ec om 7:0 P2MDOUT[7:0] Output Configuration Bits for P2.7–P2.0 (respectively). These bits are ignored if the corresponding bit in register P2MDIN is logic 0. 0: Corresponding P2.n Output is open-drain. 1: Corresponding P2.n Output is push-pull. 157 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 3 Name P2SKIP[7:0] Type R/W Reset 0 0 0 0 SFR Address = 0xD6 Bit Name P2SKIP[7:0] 0 1 0 0 0 Function Port 2 Crossbar Skip Enable Bits. These bits select Port 2 pins to be skipped by the Crossbar Decoder. Port pins used for analog, special functions or GPIO should be skipped by the Crossbar. 0: Corresponding P2.n pin is not skipped by the Crossbar. 1: Corresponding P2.n pin is skipped by the Crossbar. SFR Definition 22.20. P3: Port 3 7 6 Name Type R Reset 0 5 4 m en de d Bit fo r N ew 7:0 0 2 D Bit es ig ns SFR Definition 22.19. P2SKIP: Port 2 Skip 0 P3[0] 0 P3[0] R R R R R/W 0 0 0 0 0 0 1 Unused. Port 3 Data. Sets the Port latch logic value or reads the Port pin logic state in Port cells configured for digital I/O. Write Read Don’t Care 0000000b 0: Set output latch to logic LOW. 1: Set output latch to logic HIGH. 0: P3.0 Port pin is logic LOW. 1: P3.0 Port pin is logic HIGH. N ot R ec 1 R om Unused 2 R SFR Address = 0xB0; Bit-Addressable Bit Name Description 7:1 3 Rev. 1.3 158 C8051T620/1/6/7 & C8051T320/1/2/3 Bit 7 6 5 4 3 2 Name es ig ns SFR Definition 22.21. P3MDOUT: Port 3 Output Mode 1 0 P3MDOUT[0] R R R R R R R R/W Reset 0 0 0 0 0 0 0 0 SFR Address = 0xA7 Bit Name Unused Read = 0000000b; Write = Don’t Care 0 P3MDOUT[0] Output Configuration Bits for P3.0. 0: P3.0 Output is open-drain. 1: P3.0 Output is push-pull. N ot R ec om m en de d fo r 7:1 N ew Function 159 Rev. 1.3 D Type C8051T620/1/6/7 & C8051T320/1/2/3 23. Universal Serial Bus Controller (USB0) m en de d fo r N ew D es ig ns C8051T620/1/6/7 & C8051T320/1/2/3 devices include a complete Full/Low Speed USB function for USB peripheral implementations. The USB Function Controller (USB0) consists of a Serial Interface Engine (SIE), USB Transceiver (including matching resistors and configurable pull-up resistors), 1 kB FIFO block, and clock recovery mechanism for crystal-less operation. No external components are required. The USB Function Controller and Transceiver is Universal Serial Bus Specification 2.0 compliant. Figure 23.1. USB0 Block Diagram Important Note: This document assumes a comprehensive understanding of the USB Protocol. Terms and abbreviations used in this document are defined in the USB Specification. We encourage you to review the latest version of the USB Specification before proceeding. N ot R ec om Note: The C8051T620/1/6/7 & C8051T320/1/2/3 cannot be used as a USB Host device. Rev. 1.3 160 C8051T620/1/6/7 & C8051T320/1/2/3 23.1. Endpoint Addressing es ig ns A total of eight endpoint pipes are available. The control endpoint (Endpoint0) always functions as a bidirectional IN/OUT endpoint. The other endpoints are implemented as three pairs of IN/OUT endpoint pipes: Table 23.1. Endpoint Addressing Scheme Endpoint2 Endpoint3 23.2. USB Transceiver USB Protocol Address 0x00 0x00 0x81 0x01 0x82 0x02 D Endpoint1 Associated Pipes Endpoint0 IN Endpoint0 OUT Endpoint1 IN Endpoint1 OUT Endpoint2 IN Endpoint2 OUT Endpoint3 IN Endpoint3 OUT N ew Endpoint Endpoint0 0x83 0x03 m en de d fo r The USB Transceiver is configured via the USB0XCN register shown in SFR Definition 23.1. This configuration includes Transceiver enable/disable, pull-up resistor enable/disable, and device speed selection (Full or Low Speed). When bit SPEED = 1, USB0 operates as a Full Speed USB function, and the on-chip pull-up resistor (if enabled) appears on the D+ pin. When bit SPEED = 0, USB0 operates as a Low Speed USB function, and the on-chip pull-up resistor (if enabled) appears on the D- pin. Bits4-0 of register USB0XCN can be used for Transceiver testing as described in SFR Definition 23.1. The pull-up resistor is enabled only when VBUS is present (see Section “11.1.2. VBUS Detection” on page 61 for details on VBUS detection). N ot R ec om Important Note: The USB clock should be active before the Transceiver is enabled. 161 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 3 Name PREN PHYEN SPEED PHYTST[1:0] DFREC Type R/W R/W R/W R/W R Reset 0 0 0 0 SFR Address = 0xD7 Bit Name 2 0 0 Function 1 0 Dp Dn R R 0 0 D Bit es ig ns SFR Definition 23.1. USB0XCN: USB0 Transceiver Control 7 PREN 6 PHYEN Physical Layer Enable. 0: USB0 physical layer Transceiver disabled (suspend). 1: USB0 physical layer Transceiver enabled (normal). 5 SPEED USB0 Speed Select. This bit selects the USB0 speed. 0: USB0 operates as a Low Speed device. If enabled, the internal pull-up resistor appears on the D– line. 1: USB0 operates as a Full Speed device. If enabled, the internal pull-up resistor appears on the D+ line. m en de d fo r N ew Internal Pull-up Resistor Enable. The location of the pull-up resistor (D+ or D-) is determined by the SPEED bit. 0: Internal pull-up resistor disabled (device effectively detached from USB network). 1: Internal pull-up resistor enabled when VBUS is present (device attached to the USB network). DFREC ec 2 om 4:3 PHYTST[1:0] Physical Layer Test Bits. 00: Mode 0: Normal (non-test mode) (D+ = X, D- = X) 01: Mode 1: Differential 1 Forced (D+ = 1, D- = 0) 10: Mode 2: Differential 0 Forced (D+ = 0, D- = 1) 11: Mode 3: Single-Ended 0 Forced (D+ = 0, D– = 0) N ot R 1 0 Differential Receiver Bit The state of this bit indicates the current differential value present on the D+ and Dlines when PHYEN = 1. 0: Differential 0 signalling on the bus. 1: Differential 1 signalling on the bus. Dp D+ Signal Status. This bit indicates the current logic level of the D+ pin. 0: D+ signal currently at logic 0. 1: D+ signal currently at logic 1. Dn D– Signal Status. This bit indicates the current logic level of the D- pin. 0: D– signal currently at logic 0. 1: D– signal currently at logic 1. Rev. 1.3 162 C8051T620/1/6/7 & C8051T320/1/2/3 23.3. USB Register Access es ig ns The USB0 controller registers listed in Table 23.2 are accessed through two SFRs: USB0 Address (USB0ADR) and USB0 Data (USB0DAT). The USB0ADR register selects which USB register is targeted by reads/writes of the USB0DAT register. See Figure 23.2. Endpoint control/status registers are accessed by first writing the USB register INDEX with the target endpoint number. Once the target endpoint number is written to the INDEX register, the control/status registers associated with the target endpoint may be accessed. See the “Indexed Registers” section of Table 23.2 for a list of endpoint control/status registers. Figure 23.2. USB0 Register Access Scheme N ot R ec om m en de d fo r N ew D Important Note: The USB clock must be active when accessing USB registers. 163 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 Name BUSY AUTORD USBADDR[5:0] Type R/W R/W R/W Reset 0 0 SFR Address = 0x96 Bit Name 6 AUTORD 0 0 Description 3 2 0 0 Write USB0 Register Read Busy Flag. This bit is used during indirect USB0 register accesses. 0: No effect. 1: A USB0 indirect register read is initiated at the address specified by the USBADDR bits. 1 0 0 0 Read 0: USB0DAT register data is valid. 1: USB0 is busy accessing an indirect register; USB0DAT register data is invalid. N ew BUSY 4 USB0 Register Auto-read Flag. This bit is used for block FIFO reads. 0: BUSY must be written manually for each USB0 indirect register read. 1: The next indirect register read will automatically be initiated when software reads USB0DAT (USBADDR bits will not be changed). m en de d fo r 7 5 D Bit es ig ns SFR Definition 23.2. USB0ADR: USB0 Indirect Address N ot R ec om 5:0 USBADDR[5:0] USB0 Indirect Register Address Bits. These bits hold a 6-bit address used to indirectly access the USB0 core registers. Table 23.2 lists the USB0 core registers and their indirect addresses. Reads and writes to USB0DAT will target the register indicated by the USBADDR bits. Rev. 1.3 164 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 3 Name USB0DAT[7:0] Type R/W 0 SFR Address = 0x97 Bit Name 0 Description USB0DAT[7:0] USB0 Data Bits. This SFR is used to indirectly read and write USB0 registers. 0 Write Procedure: 1. Poll for BUSY (USB0ADR.7) => 0. 2. Load the target USB0 register address into the USBADDR bits in register USB0ADR. 3. Write data to USB0DAT. 4. Repeat (Step 2 may be skipped when writing to the same USB0 register). m en de d om ec R N ot 165 0 Write fo r 7:0 0 Rev. 1.3 1 0 0 0 Read Read Procedure: 1. Poll for BUSY (USB0ADR.7) => 0. 2. Load the target USB0 register address into the USBADDR bits in register USB0ADR. 3. Write 1 to the BUSY bit in register USB0ADR (steps 2 and 3 can be performed in the same write). 4. Poll for BUSY (USB0ADR.7) => 0. 5. Read data from USB0DAT. 6. Repeat from Step 2 (Step 2 may be skipped when reading the same USB0 register; Step 3 may be skipped when the AUTORD bit (USB0ADR.6) is logic 1). N ew 0 Reset 2 D Bit es ig ns SFR Definition 23.3. USB0DAT: USB0 Data C8051T620/1/6/7 & C8051T320/1/2/3 Table 23.2. USB0 Controller Registers FADDR POWER FRAMEL FRAMEH INDEX CLKREC EENABLE FIFOn 0x00 0x01 0x0C 0x0D 0x0E 0x0F 0x1E 0x20-0x23 m en de d 0x11 0x12 0x14 0x15 0x16 0x17 176 177 178 179 180 181 172 174 175 175 167 168 186 171 184 188 189 191 192 185 192 193 N ot R ec om E0CSR EINCSRL EINCSRH EOUTCSRL EOUTCSRH E0CNT EOUTCNTL EOUTCNTH Interrupt Registers Endpoint0 and Endpoints1-3 IN Interrupt Flags Endpoints1-3 OUT Interrupt Flags Common USB Interrupt Flags Endpoint0 and Endpoints1-3 IN Interrupt Enables Endpoints1-3 OUT Interrupt Enables Common USB Interrupt Enables Common Registers Function Address Power Management Frame Number Low Byte Frame Number High Byte Endpoint Index Selection Clock Recovery Control Endpoint Enable Endpoints0-3 FIFOs Indexed Registers Endpoint0 Control / Status Endpoint IN Control / Status Low Byte Endpoint IN Control / Status High Byte Endpoint OUT Control / Status Low Byte Endpoint OUT Control / Status High Byte Number of Received Bytes in Endpoint0 FIFO Endpoint OUT Packet Count Low Byte Endpoint OUT Packet Count High Byte D 0x02 0x04 0x06 0x07 0x09 0x0B Page Number N ew IN1INT OUT1INT CMINT IN1IE OUT1IE CMIE Description es ig ns USB Register Address fo r USB Register Name Rev. 1.3 166 C8051T620/1/6/7 & C8051T320/1/2/3 Bit 7 6 5 4 3 Name 1 0 EPSEL[3:0] R R R R Reset 0 0 0 0 USB Register Address = 0x0E Bit Name 3:0 EPSEL[3:0] Function Read = 0000b. Write = don’t care. 0 0 N ew Unused 0 0 Endpoint Select Bits. These bits select which endpoint is targeted when indexed USB0 registers are accessed. 0000: Endpoint 0 0001: Endpoint 1 0010: Endpoint 2 0011: Endpoint 3 0100-1111: Reserved. N ot R ec om m en de d fo r 7:4 R/W D Type 167 2 es ig ns USB Register Definition 23.4. INDEX: USB0 Endpoint Index Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 23.4. USB Clock Configuration es ig ns USB0 is capable of communication as a Full or Low Speed USB function. Communication speed is selected via the SPEED bit in SFR USB0XCN. When operating as a Low Speed function, the USB0 clock must be 6 MHz. When operating as a Full Speed function, the USB0 clock must be 48 MHz. Clock options are described in Section “21. Oscillators and Clock Selection” on page 127. The USB0 clock is selected via SFR CLKSEL (see SFR Definition 21.1). Clock Recovery circuitry uses the incoming USB data stream to adjust the internal oscillator; this allows the internal oscillator to meet the requirements for USB clock tolerance. Clock Recovery should be used in the following configurations: USB Clock Internal Oscillator Internal Oscillator / 8 N ew D Communication Speed Full Speed Low Speed When operating USB0 as a Low Speed function with Clock Recovery, software must write 1 to the CRLOW bit to enable Low Speed Clock Recovery. Clock Recovery is typically not necessary in Low Speed mode. fo r Single Step Mode can be used to help the Clock Recovery circuitry to lock when high noise levels are present on the USB network. This mode is not required (or recommended) in typical USB environments. USB Register Definition 23.5. CLKREC: Clock Recovery Control 7 Name CRE Type R/W Reset 0 6 5 4 3 2 1 0 CRSSEN CRLOW Reserved Reserved Reserved Reserved Reserved R/W R/W R/W R/W R/W R/W R/W 0 0 0 1 1 1 1 m en de d Bit USB Register Address = 0x0F Bit Name CRE Clock Recovery Enable Bit. This bit enables/disables the USB clock recovery feature. 0: Clock recovery disabled. 1: Clock recovery enabled. 6 CRSSEN Clock Recovery Single Step. This bit forces the oscillator calibration into ‘single-step’ mode during clock recovery. 0: Normal calibration mode. 1: Single step mode. 5 CRLOW Low Speed Clock Recovery Mode. This bit must be set to 1 if clock recovery is used when operating as a Low Speed USB device. 0: Full Speed Mode. 1: Low Speed Mode. 4:0 Reserved Read = Variable. Must Write = 01111b. N ot R ec om 7 Function Rev. 1.3 168 C8051T620/1/6/7 & C8051T320/1/2/3 23.5. FIFO Management m en de d fo r N ew D es ig ns 1024 bytes of on-chip XRAM are used as FIFO space for USB0. This FIFO space is split between Endpoints0-3 as shown in Figure 23.3. FIFO space allocated for Endpoints1-3 is configurable as IN, OUT, or both (Split Mode: half IN, half OUT). N ot R ec om Figure 23.3. C8051T620/1 and C8051T320/1/2/3 USB FIFO Allocation 169 Rev. 1.3 m en de d fo r N ew D es ig ns C8051T620/1/6/7 & C8051T320/1/2/3 Figure 23.4. C8051T626/7 USB FIFO Allocation om 23.5.1. FIFO Split Mode The FIFO space for Endpoints1-3 can be split such that the upper half of the FIFO space is used by the IN endpoint, and the lower half is used by the OUT endpoint. For example: if the Endpoint3 FIFO is configured for Split Mode, the upper 256 bytes (0x0540 to 0x063F) are used by Endpoint3 IN and the lower 256 bytes (0x0440 to 0x053F) are used by Endpoint3 OUT. ec If an endpoint FIFO is not configured for split mode, that endpoint IN/OUT pair’s FIFOs are combined to form a single IN or OUT FIFO. In this case only one direction of the endpoint IN/OUT pair may be used at a time. The endpoint direction (IN/OUT) is determined by the DIRSEL bit in the corresponding endpoint’s EINCSRH register (see SFR Definition 23.13). N ot R 23.5.2. FIFO Double Buffering FIFO slots for Endpoints1-3 can be configured for double-buffered mode. In this mode, the maximum packet size is halved and the FIFO may contain two packets at a time. This mode is available for Endpoints1-3. When an endpoint is configured for split mode, double buffering may be enabled for the IN Endpoint and/or the OUT endpoint. When split mode is not enabled, double-buffering may be enabled for the entire endpoint FIFO. See Table 23.3 for a list of maximum packet sizes for each FIFO configuration. Rev. 1.3 170 C8051T620/1/6/7 & C8051T320/1/2/3 Table 23.3. FIFO Configurations 0 N/A N Y N Y N Y 1 2 3 Maximum IN Packet Size (Double Buffer Disabled / Enabled) Maximum OUT Packet Size (Double Buffer Disabled / Enabled) es ig ns Split Mode Enabled? 64 128 / 64 64 / 32 64 / 32 256 / 128 128 / 64 128 / 64 512 / 256 256 / 128 D Endpoint Number 256 / 128 fo r N ew 23.5.1. FIFO Access Each endpoint FIFO is accessed through a corresponding FIFOn register. A read of an endpoint FIFOn register unloads one byte from the FIFO; a write of an endpoint FIFOn register loads one byte into the endpoint FIFO. When an endpoint FIFO is configured for Split Mode, a read of the endpoint FIFOn register unloads one byte from the OUT endpoint FIFO; a write of the endpoint FIFOn register loads one byte into the IN endpoint FIFO. USB Register Definition 23.6. FIFOn: USB0 Endpoint FIFO Access 7 6 5 4 m en de d Bit 2 1 0 0 0 0 FIFODATA[7:0] Name R/W Type 0 Reset 0 0 0 USB Register Address = 0x20-0x23 Bit Name 0 Function FIFODATA[7:0] Endpoint FIFO Access Bits. USB Addresses 0x20-0x23 provide access to the 4 pairs of endpoint FIFOs: 0x20: Endpoint 0 0x21: Endpoint 1 0x22: Endpoint 2 0x23: Endpoint 3 Writing to the FIFO address loads data into the IN FIFO for the corresponding endpoint. Reading from the FIFO address unloads data from the OUT FIFO for the corresponding endpoint. N ot R ec om 7:0 3 171 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 23.6. Function Addressing 7 Name UPDATE FADDR[6:0] Type R R/W Reset 0 0 USB Register Address = 0x00 Bit Name UPDATE 0 4 3 0 2 0 0 1 0 0 0 Function Function Address Update Bit. Set to 1 when software writes the FADDR register. USB0 clears this bit to 0 when the new address takes effect. 0: The last address written to FADDR is in effect. 1: The last address written to FADDR is not yet in effect. 6:0 FADDR[6:0] Function Address Bits. Holds the 7-bit function address for USB0. This address should be written by software when the SET_ADDRESS standard device request is received on Endpoint0. The new address takes effect when the device request completes. N ot R ec om m en de d 7 5 fo r 6 N ew Bit D USB Register Definition 23.7. FADDR: USB0 Function Address es ig ns The FADDR register holds the current USB0 function address. Software should write the host-assigned 7bit function address to the FADDR register when received as part of a SET_ADDRESS command. A new address written to FADDR will not take effect (USB0 will not respond to the new address) until the end of the current transfer (typically following the status phase of the SET_ADDRESS command transfer). The UPDATE bit (FADDR.7) is set to 1 by hardware when software writes a new address to the FADDR register. Hardware clears the UPDATE bit when the new address takes effect as described above. Rev. 1.3 172 C8051T620/1/6/7 & C8051T320/1/2/3 23.7. Function Configuration and Control es ig ns The USB register POWER (USB Register Definition 23.8) is used to configure and control USB0 at the device level (enable/disable, Reset/Suspend/Resume handling, etc.). USB Reset: The USBRST bit (POWER.3) is set to 1 by hardware when Reset signaling is detected on the bus. Upon this detection, the following occur: D The USB0 Address is reset (FADDR = 0x00). Endpoint FIFOs are flushed. Control/status registers are reset to 0x00 (E0CSR, EINCSRL, EINCSRH, EOUTCSRL, EOUTCSRH). USB register INDEX is reset to 0x00. All USB interrupts (excluding the Suspend interrupt) are enabled and their corresponding flags cleared. A USB Reset interrupt is generated if enabled. N ew 1. 2. 3. 4. 5. 6. Writing a 1 to the USBRST bit will generate an asynchronous USB0 reset. All USB registers are reset to their default values following this asynchronous reset. fo r Suspend Mode: With Suspend Detection enabled (SUSEN = 1), USB0 will enter Suspend Mode when Suspend signaling is detected on the bus. An interrupt will be generated if enabled (SUSINTE = 1). The Suspend Interrupt Service Routine (ISR) should perform application-specific configuration tasks such as disabling appropriate peripherals and/or configuring clock sources for low power modes. See Section “21.3. Programmable Internal High-Frequency (H-F) Oscillator” on page 130 for more details on internal oscillator configuration, including the Suspend mode feature of the internal oscillator. m en de d USB0 exits Suspend mode when any of the following occur: (1) Resume signaling is detected or generated, (2) Reset signaling is detected, or (3) a device or USB reset occurs. If suspended, the internal oscillator will exit Suspend mode upon any of the above listed events. Resume Signaling: USB0 will exit Suspend mode if Resume signaling is detected on the bus. A Resume interrupt will be generated upon detection if enabled (RESINTE = 1). Software may force a Remote Wakeup by writing 1 to the RESUME bit (POWER.2). When forcing a Remote Wakeup, software should write RESUME = 0 to end Resume signaling 10-15 ms after the Remote Wakeup is initiated (RESUME = 1). om ISO Update: When software writes 1 to the ISOUP bit (POWER.7), the ISO Update function is enabled. With ISO Update enabled, new packets written to an ISO IN endpoint will not be transmitted until a new Start-Of-Frame (SOF) is received. If the ISO IN endpoint receives an IN token before a SOF, USB0 will transmit a zero-length packet. When ISOUP = 1, ISO Update is enabled for all ISO endpoints. ec USB Enable: USB0 is disabled following a Power-On-Reset (POR). USB0 is enabled by clearing the USBINH bit (POWER.4). Once written to 0, the USBINH can only be set to 1 by one of the following: (1) a Power-On-Reset (POR), or (2) an asynchronous USB0 reset generated by writing 1 to the USBRST bit (POWER.3). R Software should perform all USB0 configuration before enabling USB0. The configuration sequence should be performed as follows: Select and enable the USB clock source. Reset USB0 by writing USBRST= 1. Configure and enable the USB Transceiver. Perform any USB0 function configuration (interrupts, Suspend detect). Enable USB0 by writing USBINH = 0. N ot 1. 2. 3. 4. 5. 173 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 Name ISOUD Type R/W R/W Reset 0 0 5 4 3 2 USBINH USBRST R/W R/W 0 1 USB Register Address = 0x01 Bit Name 1 0 RESUME SUSMD SUSEN R/W R/W R R/W 0 0 0 0 Function D Bit es ig ns USB Register Definition 23.8. POWER: USB0 Power ISOUD ISO Update Bit. This bit affects all IN Isochronous endpoints. 0: When software writes INPRDY = 1, USB0 will send the packet when the next IN token is received. 1: When software writes INPRDY = 1, USB0 will wait for a SOF token before sending the packet. If an IN token is received before a SOF token, USB0 will send a zero-length data packet. 6:5 Unused Read = 00b. Write = don’t care. fo r N ew 7 USBINH USB0 Inhibit Bit. This bit is set to 1 following a power-on reset (POR) or an asynchronous USB0 reset. Software should clear this bit after all USB0 transceiver initialization is complete. Software cannot set this bit to 1. 0: USB0 enabled. 1: USB0 inhibited. All USB traffic is ignored. 3 USBRST Reset Detect. 2 RESUME Force Resume. Writing a 1 to this bit while in Suspend mode (SUSMD = 1) forces USB0 to generate Resume signaling on the bus (a remote wakeup event). Software should write RESUME = 0 after 10 to 15 ms to end the Resume signaling. An interrupt is generated, and hardware clears SUSMD, when software writes RESUME = 0. m en de d 4 ec om Read: Write: 0: Reset signaling is not present. Writing 1 to this bit forces an asynchronous USB0 reset. 1: Reset signaling detected on the bus. SUSMD Suspend Mode. Set to 1 by hardware when USB0 enters suspend mode. Cleared by hardware when software writes RESUME = 0 (following a remote wakeup) or reads the CMINT register after detection of Resume signaling on the bus. 0: USB0 not in suspend mode. 1: USB0 in suspend mode. N ot R 1 0 SUSEN Suspend Detection Enable. 0: Suspend detection disabled. USB0 will ignore suspend signaling on the bus. 1: Suspend detection enabled. USB0 will enter suspend mode if it detects suspend signaling on the bus. Rev. 1.3 174 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 3 Name FRMEL[7:0] Type R 0 Reset 0 0 0 USB Register Address = 0x0C Bit Name 0 2 0 1 0 0 0 D Bit es ig ns USB Register Definition 23.9. FRAMEL: USB0 Frame Number Low Function N ew 7:0 FRMEL[7:0] Frame Number Low Bits. This register contains bits 7-0 of the last received frame number. Bit 7 6 5 Name R Reset 0 4 3 R R R R 0 0 0 0 m en de d Type fo r USB Register Definition 23.10. FRAMEH: USB0 Frame Number High USB Register Address = 0x0D Bit Name 2 1 FRMEH[2:0] R 0 Function N ot R ec om 7:3 Unused Read = 00000b. Write = don’t care. 2:0 FRMEH[2:0] Frame Number High Bits. This register contains bits 10-8 of the last received frame number. 175 Rev. 1.3 0 0 0 C8051T620/1/6/7 & C8051T320/1/2/3 23.8. Interrupts es ig ns The read-only USB0 interrupt flags are located in the USB registers shown in USB Register Definition 23.11 through USB Register Definition 23.13. The associated interrupt enable bits are located in the USB registers shown in USB Register Definition 23.14 through USB Register Definition 23.16. A USB0 interrupt is generated when any of the USB interrupt flags is set to 1. The USB0 interrupt is enabled via the EIE1 SFR (see Section “17. Interrupts” on page 101). Important Note: Reading a USB interrupt flag register resets all flags in that register to 0. Bit 7 6 5 4 Type R R R R Reset 0 0 0 0 1 0 IN3 IN2 IN1 EP0 R R R R 0 0 0 0 Function fo r USB Register Address = 0x02 Bit Name 2 N ew Name 3 D USB Register Definition 23.11. IN1INT: USB0 IN Endpoint Interrupt 7:4 3 Unused IN3 Read = 0000b. Write = don’t care. 2 IN2 IN Endpoint 2 Interrupt-Pending Flag. This bit is cleared when software reads the IN1INT register. 0: IN Endpoint 2 interrupt inactive. 1: IN Endpoint 2 interrupt active. 1 IN1 IN Endpoint 1 Interrupt-Pending Flag. m en de d IN Endpoint 3 Interrupt-Pending Flag. This bit is cleared when software reads the IN1INT register. 0: IN Endpoint 3 interrupt inactive. 1: IN Endpoint 3 interrupt active. EP0 Endpoint 0 Interrupt-Pending Flag. This bit is cleared when software reads the IN1INT register. 0: Endpoint 0 interrupt inactive. 1: Endpoint 0 interrupt active. N ot R ec 0 om This bit is cleared when software reads the IN1INT register. 0: IN Endpoint 1 interrupt inactive. 1: IN Endpoint 1 interrupt active. Rev. 1.3 176 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 Name 3 2 OUT3 OUT2 OUT1 R R 0 0 Type R R R R R R Reset 0 0 0 0 0 0 USB Register Address = 0x04 Bit Name Function 7:4 3 Unused OUT3 2 OUT2 OUT Endpoint 2 Interrupt-pending Flag. This bit is cleared when software reads the OUT1INT register. 0: OUT Endpoint 2 interrupt inactive. 1: OUT Endpoint 2 interrupt active. 1 OUT1 OUT Endpoint 1 Interrupt-pending Flag. N ew Read = 0000b. Write = don’t care. 1 D Bit es ig ns USB Register Definition 23.12. OUT1INT: USB0 OUT Endpoint Interrupt m en de d fo r OUT Endpoint 3 Interrupt-pending Flag. This bit is cleared when software reads the OUT1INT register. 0: OUT Endpoint 3 interrupt inactive. 1: OUT Endpoint 3 interrupt active. This bit is cleared when software reads the OUT1INT register. 0: OUT Endpoint 1 interrupt inactive. 1: OUT Endpoint 1 interrupt active. Unused Read = 0b. Write = don’t care. N ot R ec om 0 177 Rev. 1.3 0 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 Name 3 2 1 0 SOF RSTINT RSUINT SUSINT R R 0 0 Type R R R R R R Reset 0 0 0 0 0 0 USB Register Address = 0x06 Bit Name Function 7:4 3 Unused SOF 2 RSTINT Reset Interrupt-pending Flag. Set by hardware when Reset signaling is detected on the bus. This bit is cleared when software reads the CMINT register. 0: Reset interrupt inactive. 1: Reset interrupt active. 1 RSUINT Resume Interrupt-pending Flag. Set by hardware when Resume signaling is detected on the bus while USB0 is in suspend mode. This bit is cleared when software reads the CMINT register. 0: Resume interrupt inactive. 1: Resume interrupt active. 0 SUSINT N ew Read = 0000b. Write = don’t care. D Bit es ig ns USB Register Definition 23.13. CMINT: USB0 Common Interrupt om m en de d fo r Start of Frame Interrupt Flag. Set by hardware when a SOF token is received. This interrupt event is synthesized by hardware: an interrupt will be generated when hardware expects to receive a SOF event, even if the actual SOF signal is missed or corrupted. This bit is cleared when software reads the CMINT register. 0: SOF interrupt inactive. 1: SOF interrupt active. N ot R ec Suspend Interrupt-pending Flag. When Suspend detection is enabled (bit SUSEN in register POWER), this bit is set by hardware when Suspend signaling is detected on the bus. This bit is cleared when software reads the CMINT register. 0: Suspend interrupt inactive. 1: Suspend interrupt active. Rev. 1.3 178 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 Name 3 2 IN3E IN2E Type R R R R R/W R/W Reset 0 0 0 0 1 1 USB Register Address = 0x07 Bit Name 7:4 3 Unused IN3E Read = 0000b. Write = don’t care. 2 IN2E IN Endpoint 2 Interrupt Enable. 0: IN Endpoint 2 interrupt disabled. 1: IN Endpoint 2 interrupt enabled. 1 IN1E IN Endpoint 1 Interrupt Enable. 0: IN Endpoint 1 interrupt disabled. 1: IN Endpoint 1 interrupt enabled. 0 EP0E Endpoint 0 Interrupt Enable. 0: Endpoint 0 interrupt disabled. 1: Endpoint 0 interrupt enabled. N ot R ec om m en de d fo r IN Endpoint 3 Interrupt Enable. 0: IN Endpoint 3 interrupt disabled. 1: IN Endpoint 3 interrupt enabled. 179 Rev. 1.3 0 IN1E EP0E R/W R/W 1 1 N ew Function 1 D Bit es ig ns USB Register Definition 23.14. IN1IE: USB0 IN Endpoint Interrupt Enable C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 Name 3 2 OUT3E OUT2E OUT1E R/W R 1 0 Type R R R R R/W R/W Reset 0 0 0 0 1 1 USB Register Address = 0x09 Bit Name 7:4 3 Unused OUT3E Read = 0000b. Write = don’t care. 2 OUT2E OUT Endpoint 2 Interrupt Enable. 0: OUT Endpoint 2 interrupt disabled. 1: OUT Endpoint 2 interrupt enabled. 1 OUT1E OUT Endpoint 1 Interrupt Enable. 0: OUT Endpoint 1 interrupt disabled. 1: OUT Endpoint 1 interrupt enabled. 0 Unused Read = 0b. Write = don’t care. N ot R ec om m en de d fo r OUT Endpoint 3 Interrupt Enable. 0: OUT Endpoint 3 interrupt disabled. 1: OUT Endpoint 3 interrupt enabled. 0 N ew Function 1 D Bit es ig ns USB Register Definition 23.15. OUT1IE: USB0 OUT Endpoint Interrupt Enable Rev. 1.3 180 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 Name 3 2 1 0 SOFE RSTINTE RSUINTE SUSINTE R/W R/W 1 0 Type R R R R R/W R/W Reset 0 0 0 0 0 1 USB Register Address = 0x0B Bit Name Function Unused SOFE Read = 0000b. Write = don’t care. 2 RSTINTE Reset Interrupt Enable. 0: Reset interrupt disabled. 1: Reset interrupt enabled. 1 RSUINTE Resume Interrupt Enable. 0: Resume interrupt disabled. 1: Resume interrupt enabled. 0 SUSINTE Suspend Interrupt Enable. 0: Suspend interrupt disabled. 1: Suspend interrupt enabled. m en de d fo r Start of Frame Interrupt Enable. 0: SOF interrupt disabled. 1: SOF interrupt enabled. N ew 7:4 3 D Bit es ig ns USB Register Definition 23.16. CMIE: USB0 Common Interrupt Enable 23.9. The Serial Interface Engine om The Serial Interface Engine (SIE) performs all low level USB protocol tasks, interrupting the processor when data has successfully been transmitted or received. When receiving data, the SIE will interrupt the processor when a complete data packet has been received; appropriate handshaking signals are automatically generated by the SIE. When transmitting data, the SIE will interrupt the processor when a complete data packet has been transmitted and the appropriate handshake signal has been received. The SIE will not interrupt the processor when corrupted/erroneous packets are received. ec 23.10. Endpoint0 R Endpoint0 is managed through the USB register E0CSR (USB Register Definition 23.18). The INDEX register must be loaded with 0x00 to access the E0CSR register. An Endpoint0 interrupt is generated when: N ot 1. A data packet (OUT or SETUP) has been received and loaded into the Endpoint0 FIFO. The OPRDY bit (E0CSR.0) is set to 1 by hardware. 2. An IN data packet has successfully been unloaded from the Endpoint0 FIFO and transmitted to the host; INPRDY is reset to 0 by hardware. 3. An IN transaction is completed (this interrupt generated during the status stage of the transaction). 4. Hardware sets the STSTL bit (E0CSR.2) after a control transaction ended due to a protocol violation. 181 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 5. Hardware sets the SUEND bit (E0CSR.4) because a control transfer ended before firmware sets the DATAEND bit (E0CSR.3). es ig ns The E0CNT register (USB Register Definition 23.11) holds the number of received data bytes in the Endpoint0 FIFO. Hardware will automatically detect protocol errors and send a STALL condition in response. Firmware may force a STALL condition to abort the current transfer. When a STALL condition is generated, the STSTL bit will be set to 1 and an interrupt generated. The following conditions will cause hardware to generate a STALL condition: D The host sends an OUT token during a OUT data phase after the DATAEND bit has been set to 1. The host sends an IN token during an IN data phase after the DATAEND bit has been set to 1. The host sends a packet that exceeds the maximum packet size for Endpoint0. The host sends a non-zero length DATA1 packet during the status phase of an IN transaction. N ew 1. 2. 3. 4. Firmware sets the SDSTL bit (E0CSR.5) to 1. m en de d fo r 23.10.1. Endpoint0 SETUP Transactions All control transfers must begin with a SETUP packet. SETUP packets are similar to OUT packets, containing an 8-byte data field sent by the host. Any SETUP packet containing a command field of anything other than 8 bytes will be automatically rejected by USB0. An Endpoint0 interrupt is generated when the data from a SETUP packet is loaded into the Endpoint0 FIFO. Software should unload the command from the Endpoint0 FIFO, decode the command, perform any necessary tasks, and set the SOPRDY bit to indicate that it has serviced the OUT packet. om 23.10.2. Endpoint0 IN Transactions When a SETUP request is received that requires USB0 to transmit data to the host, one or more IN requests will be sent by the host. For the first IN transaction, firmware should load an IN packet into the Endpoint0 FIFO, and set the INPRDY bit (E0CSR.1). An interrupt will be generated when an IN packet is transmitted successfully. Note that no interrupt will be generated if an IN request is received before firmware has loaded a packet into the Endpoint0 FIFO. If the requested data exceeds the maximum packet size for Endpoint0 (as reported to the host), the data should be split into multiple packets; each packet should be of the maximum packet size excluding the last (residual) packet. If the requested data is an integer multiple of the maximum packet size for Endpoint0, the last data packet should be a zero-length packet signaling the end of the transfer. Firmware should set the DATAEND bit to 1 after loading into the Endpoint0 FIFO the last data packet for a transfer. ec Upon reception of the first IN token for a particular control transfer, Endpoint0 is said to be in Transmit Mode. In this mode, only IN tokens should be sent by the host to Endpoint0. The SUEND bit (E0CSR.4) is set to 1 if a SETUP or OUT token is received while Endpoint0 is in Transmit Mode. Endpoint0 will remain in Transmit Mode until any of the following occur: N ot R 1. USB0 receives an Endpoint0 SETUP or OUT token. 2. Firmware sends a packet less than the maximum Endpoint0 packet size. 3. Firmware sends a zero-length packet. Firmware should set the DATAEND bit (E0CSR.3) to 1 when performing (2) and (3) above. The SIE will transmit a NAK in response to an IN token if there is no packet ready in the IN FIFO (INPRDY = 0). Rev. 1.3 182 C8051T620/1/6/7 & C8051T320/1/2/3 es ig ns 23.10.3. Endpoint0 OUT Transactions When a SETUP request is received that requires the host to transmit data to USB0, one or more OUT requests will be sent by the host. When an OUT packet is successfully received by USB0, hardware will set the OPRDY bit (E0CSR.0) to 1 and generate an Endpoint0 interrupt. Following this interrupt, firmware should unload the OUT packet from the Endpoint0 FIFO and set the SOPRDY bit (E0CSR.6) to 1. If the amount of data required for the transfer exceeds the maximum packet size for Endpoint0, the data will be split into multiple packets. If the requested data is an integer multiple of the maximum packet size for Endpoint0 (as reported to the host), the host will send a zero-length data packet signaling the end of the transfer. D Upon reception of the first OUT token for a particular control transfer, Endpoint0 is said to be in Receive Mode. In this mode, only OUT tokens should be sent by the host to Endpoint0. The SUEND bit (E0CSR.4) is set to 1 if a SETUP or IN token is received while Endpoint0 is in Receive Mode. N ew Endpoint0 will remain in Receive mode until: 1. The SIE receives a SETUP or IN token. 2. The host sends a packet less than the maximum Endpoint0 packet size. 3. The host sends a zero-length packet. N ot R ec om m en de d fo r Firmware should set the DATAEND bit (E0CSR.3) to 1 when the expected amount of data has been received. The SIE will transmit a STALL condition if the host sends an OUT packet after the DATAEND bit has been set by firmware. An interrupt will be generated with the STSTL bit (E0CSR.2) set to 1 after the STALL is transmitted. 183 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 3 2 Name SSUEND SOPRDY SDSTL SUEND DATAEND Type R/W R/W R/W R Reset 0 0 0 0 USB Register Address = 0x11 Bit Name Description 5 STSTL INPRDY OPRDY R/W R/W R/W R 0 0 0 0 Write Software should set this bit to 1 This bit always reads 0. after servicing a Setup End (bit SUEND) event. Hardware clears the SUEND bit when software writes 1 to SSUEND. SOPRDY Serviced OPRDY Bit. Software should write 1 to this bit This bit always reads 0. after servicing a received Endpoint0 packet. The OPRDY bit will be cleared by a write of 1 to SOPRDY. SDSTL Send Stall Bit. N ew SSUEND Serviced Setup End Bit. Read fo r 6 0 m en de d 7 1 D Bit es ig ns USB Register Definition 23.17. E0CSR: USB0 Endpoint0 Control Software can write 1 to this bit to terminate the current transfer (due to an error condition, unexpected transfer request, etc.). Hardware will clear this bit to 0 when the STALL handshake is transmitted. 3 Setup End Bit. Hardware sets this read-only bit to 1 when a control transaction ends before software has written 1 to the DATAEND bit. Hardware clears this bit when software writes 1 to SSUEND. DATAEND Data End Bit. Software should write 1 to this bit: 1) When writing 1 to INPRDY for the last outgoing data packet. 2) When writing 1 to INPRDY for a zero-length data packet. 3) When writing 1 to SOPRDY after servicing the last incoming data packet. This bit is automatically cleared by hardware. STSTL Sent Stall Bit. Hardware sets this bit to 1 after transmitting a STALL handshake signal. This flag must be cleared by software. R ec 2 SUEND om 4 N ot 1 0 INPRDY IN Packet Ready Bit. Software should write 1 to this bit after loading a data packet into the Endpoint0 FIFO for transmit. Hardware clears this bit and generates an interrupt under either of the following conditions: 1) The packet is transmitted. 2) The packet is overwritten by an incoming SETUP packet. 3) The packet is overwritten by an incoming OUT packet. OPRDY OUT Packet Ready Bit. Hardware sets this read-only bit and generates an interrupt when a data packet has been received. This bit is cleared only when software writes 1 to the SOPRDY bit. Rev. 1.3 184 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 3 2 E0CNT[6:0] Name Type R Reset 0 R 0 0 0 USB Register Address = 0x16 Bit Name 0 Function 0 1 0 0 0 D Bit es ig ns USB Register Definition 23.18. E0CNT: USB0 Endpoint0 Data Count N ew 7 Unused Read = 0b. Write = don’t care. 6:0 E0CNT[6:0] Endpoint 0 Data Count. This 7-bit number indicates the number of received data bytes in the Endpoint 0 FIFO. This number is only valid while bit OPRDY is a 1. 23.11. Configuring Endpoints1-3 m en de d fo r Endpoints1-3 are configured and controlled through their own sets of the following control/status registers: IN registers EINCSRL and EINCSRH, and OUT registers EOUTCSRL and EOUTCSRH. Only one set of endpoint control/status registers is mapped into the USB register address space at a time, defined by the contents of the INDEX register (USB Register Definition 23.4). Endpoints1-3 can be configured as IN, OUT, or both IN/OUT (Split Mode) as described in Section 23.5.1. The endpoint mode (Split/Normal) is selected via the SPLIT bit in register EINCSRH. When SPLIT = 1, the corresponding endpoint FIFO is split, and both IN and OUT pipes are available. When SPLIT = 0, the corresponding endpoint functions as either IN or OUT; the endpoint direction is selected by the DIRSEL bit in register EINCSRH. N ot R ec om Endpoints1-3 can be disabled individually by the corresponding bits in the ENABLE register. When an Endpoint is disabled, it will not respond to bus traffic or stall the bus. All Endpoints are enabled by default. 185 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 Name 3 2 1 0 EEN3 EEN2 EEN1 Reserved R/W R/W 1 1 Type R R R R R/W R/W Reset 1 1 1 1 1 1 USB Register Address = 0x1E Bit Name Function 7:4 3 Unused EEN3 2 EEN2 Endpoint 2 Enable. This bit enables/disables Endpoint 2. 0: Endpoint 2 is disabled (no NACK, ACK, or STALL on the USB network). 1: Endpoint 2 is enabled (normal). 1 EEN1 Endpoint 1 Enable. This bit enables/disables Endpoint 1. 0: Endpoint 1 is disabled (no NACK, ACK, or STALL on the USB network). 1: Endpoint 1 is enabled (normal). 0 Reserved N ew Read = 1111b. Write = don’t care. D Bit es ig ns USB Register Definition 23.19. EENABLE: USB0 Endpoint Enable m en de d fo r Endpoint 3 Enable. This bit enables/disables Endpoint 3. 0: Endpoint 3 is disabled (no NACK, ACK, or STALL on the USB network). 1: Endpoint 3 is enabled (normal). Read = 1b. Must Write 1b. 23.12. Controlling Endpoints1-3 IN om Endpoints1-3 IN are managed via USB registers EINCSRL and EINCSRH. All IN endpoints can be used for Interrupt, Bulk, or Isochronous transfers. Isochronous (ISO) mode is enabled by writing 1 to the ISO bit in register EINCSRH. Bulk and Interrupt transfers are handled identically by hardware. An Endpoint1-3 IN interrupt is generated by any of the following conditions: N ot R ec 1. An IN packet is successfully transferred to the host. 2. Software writes 1 to the FLUSH bit (EINCSRL.3) when the target FIFO is not empty. 3. Hardware generates a STALL condition. 23.12.1. Endpoints1-3 IN Interrupt or Bulk Mode When the ISO bit (EINCSRH.6) = 0 the target endpoint operates in Bulk or Interrupt Mode. Once an endpoint has been configured to operate in Bulk/Interrupt IN mode (typically following an Endpoint0 SET_INTERFACE command), firmware should load an IN packet into the endpoint IN FIFO and set the INPRDY bit (EINCSRL.0). Upon reception of an IN token, hardware will transmit the data, clear the INPRDY bit, and generate an interrupt. Writing 1 to INPRDY without writing any data to the endpoint FIFO will cause a zero-length packet to be transmitted upon reception of the next IN token. A Bulk or Interrupt pipe can be shut down (or Halted) by writing 1 to the SDSTL bit (EINCSRL.4). While SDSTL = 1, hardware will respond to all IN requests with a STALL condition. Each time hardware gener- Rev. 1.3 186 C8051T620/1/6/7 & C8051T320/1/2/3 ates a STALL condition, an interrupt will be generated and the STSTL bit (EINCSRL.5) set to 1. The STSTL bit must be reset to 0 by firmware. es ig ns Hardware will automatically reset INPRDY to 0 when a packet slot is open in the endpoint FIFO. Note that if double buffering is enabled for the target endpoint, it is possible for firmware to load two packets into the IN FIFO at a time. In this case, hardware will reset INPRDY to 0 immediately after firmware loads the first packet into the FIFO and sets INPRDY to 1. An interrupt will not be generated in this case; an interrupt will only be generated when a data packet is transmitted. D When firmware writes 1 to the FCDT bit (EINCSRH.3), the data toggle for each IN packet will be toggled continuously, regardless of the handshake received from the host. This feature is typically used by Interrupt endpoints functioning as rate feedback communication for Isochronous endpoints. When FCDT = 0, the data toggle bit will only be toggled when an ACK is sent from the host in response to an IN packet. N ew 23.12.2. Endpoints1-3 IN Isochronous Mode When the ISO bit (EINCSRH.6) is set to 1, the target endpoint operates in Isochronous (ISO) mode. Once an endpoint has been configured for ISO IN mode, the host will send one IN token (data request) per frame; the location of data within each frame may vary. Because of this, it is recommended that double buffering be enabled for ISO IN endpoints. fo r Hardware will automatically reset INPRDY (EINCSRL.0) to 0 when a packet slot is open in the endpoint FIFO. Note that if double buffering is enabled for the target endpoint, it is possible for firmware to load two packets into the IN FIFO at a time. In this case, hardware will reset INPRDY to 0 immediately after firmware loads the first packet into the FIFO and sets INPRDY to 1. An interrupt will not be generated in this case; an interrupt will only be generated when a data packet is transmitted. m en de d If there is not a data packet ready in the endpoint FIFO when USB0 receives an IN token from the host, USB0 will transmit a zero-length data packet and set the UNDRUN bit (EINCSRL.2) to 1. N ot R ec om The ISO Update feature (see Section 23.7) can be useful in starting a double buffered ISO IN endpoint. If the host has already set up the ISO IN pipe (has begun transmitting IN tokens) when firmware writes the first data packet to the endpoint FIFO, the next IN token may arrive and the first data packet sent before firmware has written the second (double buffered) data packet to the FIFO. The ISO Update feature ensures that any data packet written to the endpoint FIFO will not be transmitted during the current frame; the packet will only be sent after a SOF signal has been received. 187 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 Bit 7 Name 6 5 4 3 2 CLRDT STSTL SDSTL FLUSH 1 0 UNDRUN FIFONE INPRDY R/W R/W 0 0 R W R/W R/W R/W R/W Reset 0 0 0 0 0 0 D Type USB Register Address = 0x11 Bit Name Description es ig ns USB Register Definition 23.20. EINCSRL: USB0 IN Endpoint Control Low Write Read Unused CLRDT Read = 0b. Write = don’t care. Clear Data Toggle Bit. Software should write 1 to this bit to reset the IN Endpoint data toggle to 0. 5 STSTL Sent Stall Bit. Hardware sets this bit to 1 when a STALL handshake signal is transmitted. The FIFO is flushed, and the INPRDY bit cleared. This flag must be cleared by software. 4 SDSTL Send Stall. Software should write 1 to this bit to generate a STALL handshake in response to an IN token. Software should write 0 to this bit to terminate the STALL signal. This bit has no effect in ISO mode. 3 FLUSH FIFO Flush Bit. Writing a 1 to this bit flushes the next packet to be transmitted from the IN Endpoint FIFO. The FIFO pointer is reset and the INPRDY bit is cleared. If the FIFO contains multiple packets, software must write 1 to FLUSH for each packet. Hardware resets the FLUSH bit to 0 when the FIFO flush is complete. m en de d fo r This bit always reads 0. UNDRUN Data Underrun Bit. The function of this bit depends on the IN Endpoint mode: ISO: Set when a zero-length packet is sent after an IN token is received while bit INPRDY = 0. Interrupt/Bulk: Set when a NAK is returned in response to an IN token. This bit must be cleared by software. FIFONE FIFO Not Empty. 0: The IN Endpoint FIFO is empty. 1. The IN Endpoint FIFO contains one or more packets. R ec 1 om 2 N ew 7 6 N ot 0 INPRDY In Packet Ready. Software should write 1 to this bit after loading a data packet into the IN Endpoint FIFO. Hardware clears INPRDY due to any of the following: 1) A data packet is transmitted. 2) Double buffering is enabled (DBIEN = 1) and there is an open FIFO packet slot. 3) If the endpoint is in Isochronous Mode (ISO = 1) and ISOUD = 1, INPRDY will read 0 until the next SOF is received. Note: An interrupt (if enabled) will be generated when hardware clears INPRDY as a result of a packet being transmitted. Rev. 1.3 188 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 Name DBIEN ISO DIRSEL Type R/W R/W R/W Reset 0 0 0 4 3 2 FCDT SPLIT R R/W R/W 0 0 0 USB Register Address = 0x12 Bit Name Function 7 DBIEN 6 ISO 5 DIRSEL Endpoint Direction Select. This bit is valid only when the selected FIFO is not split (SPLIT = 0). 0: Endpoint direction selected as OUT. 1: Endpoint direction selected as IN. 4 3 Unused FCDT Read = 0b. Write = don’t care. 2 SPLIT 1:0 Unused 0 R R 0 0 N ew IN Endpoint Double-buffer Enable. 0: Double-buffering disabled for the selected IN endpoint. 1: Double-buffering enabled for the selected IN endpoint. 1 D Bit es ig ns USB Register Definition 23.21. EINCSRH: USB0 IN Endpoint Control High m en de d fo r Isochronous Transfer Enable. This bit enables/disables isochronous transfers on the current endpoint. 0: Endpoint configured for bulk/interrupt transfers. 1: Endpoint configured for isochronous transfers. Force Data Toggle Bit. 0: Endpoint data toggle switches only when an ACK is received following a data packet transmission. 1: Endpoint data toggle forced to switch after every data packet is transmitted, regardless of ACK reception. om FIFO Split Enable. When SPLIT = 1, the selected endpoint FIFO is split. The upper half of the selected FIFO is used by the IN endpoint; the lower half of the selected FIFO is used by the OUT endpoint. ec Read = 00b. Write = don’t care. 23.13. Controlling Endpoints1-3 OUT N ot R Endpoints1-3 OUT are managed via USB registers EOUTCSRL and EOUTCSRH. All OUT endpoints can be used for Interrupt, Bulk, or Isochronous transfers. Isochronous (ISO) mode is enabled by writing 1 to the ISO bit in register EOUTCSRH. Bulk and Interrupt transfers are handled identically by hardware. An Endpoint1-3 OUT interrupt may be generated by the following: 1. Hardware sets the OPRDY bit (EINCSRL.0) to 1. 2. Hardware generates a STALL condition. 189 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 es ig ns 23.13.1. Endpoints1-3 OUT Interrupt or Bulk Mode When the ISO bit (EOUTCSRH.6) = 0 the target endpoint operates in Bulk or Interrupt mode. Once an endpoint has been configured to operate in Bulk/Interrupt OUT mode (typically following an Endpoint0 SET_INTERFACE command), hardware will set the OPRDY bit (EOUTCSRL.0) to 1 and generate an interrupt upon reception of an OUT token and data packet. The number of bytes in the current OUT data packet (the packet ready to be unloaded from the FIFO) is given in the EOUTCNTH and EOUTCNTL registers. In response to this interrupt, firmware should unload the data packet from the OUT FIFO and reset the OPRDY bit to 0. D A Bulk or Interrupt pipe can be shut down (or Halted) by writing 1 to the SDSTL bit (EOUTCSRL.5). While SDSTL = 1, hardware will respond to all OUT requests with a STALL condition. Each time hardware generates a STALL condition, an interrupt will be generated and the STSTL bit (EOUTCSRL.6) set to 1. The STSTL bit must be reset to 0 by firmware. N ew Hardware will automatically set OPRDY when a packet is ready in the OUT FIFO. Note that if double buffering is enabled for the target endpoint, it is possible for two packets to be ready in the OUT FIFO at a time. In this case, hardware will set OPRDY to 1 immediately after firmware unloads the first packet and resets OPRDY to 0. A second interrupt will be generated in this case. fo r 23.13.2. Endpoints1-3 OUT Isochronous Mode When the ISO bit (EOUTCSRH.6) is set to 1, the target endpoint operates in Isochronous (ISO) mode. Once an endpoint has been configured for ISO OUT mode, the host will send exactly one data per USB frame; the location of the data packet within each frame may vary, however. Because of this, it is recommended that double buffering be enabled for ISO OUT endpoints. m en de d Each time a data packet is received, hardware will load the received data packet into the endpoint FIFO, set the OPRDY bit (EOUTCSRL.0) to 1, and generate an interrupt (if enabled). Firmware would typically use this interrupt to unload the data packet from the endpoint FIFO and reset the OPRDY bit to 0. N ot R ec om If a data packet is received when there is no room in the endpoint FIFO, an interrupt will be generated and the OVRUN bit (EOUTCSRL.2) set to 1. If USB0 receives an ISO data packet with a CRC error, the data packet will be loaded into the endpoint FIFO, OPRDY will be set to 1, an interrupt (if enabled) will be generated, and the DATAERR bit (EOUTCSRL.3) will be set to 1. Software should check the DATAERR bit each time a data packet is unloaded from an ISO OUT endpoint FIFO. Rev. 1.3 190 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 3 2 Name CLRDT STSTL SDSTL FLUSH DATERR Type W R/W R/W R/W Reset 0 0 0 0 USB Register Address = 0x14 Bit Name Description 1 0 OVRUN FIFOFUL OPRDY R R/W R R/W 0 0 0 0 D Bit es ig ns USB Register Definition 23.22. EOUTCSRL: USB0 OUT Endpoint Control Low Byte Write Read CLRDT This bit always reads 0. Clear Data Toggle Bit. Software should write 1 to this bit to reset the OUT endpoint data toggle to 0. 6 STSTL Sent Stall Bit. Hardware sets this bit to 1 when a STALL handshake signal is transmitted. This flag must be cleared by software. 5 SDSTL Send Stall Bit. Software should write 1 to this bit to generate a STALL handshake. Software should write 0 to this bit to terminate the STALL signal. This bit has no effect in ISO mode. 4 FLUSH FIFO Flush Bit. Writing a 1 to this bit flushes the next packet to be read from the OUT endpoint FIFO. The FIFO pointer is reset and the OPRDY bit is cleared. Multiple packets must be flushed individually. Hardware resets the FLUSH bit to 0 when the flush is complete. m en de d fo r N ew 7 Note: If data for the current packet has already been read from the FIFO, the FLUSH bit should not be used to flush the packet. Instead, the FIFO should be read manually. DATERR Data Error Bit. In ISO mode, this bit is set by hardware if a received packet has a CRC or bit-stuffing error. It is cleared when software clears OPRDY. This bit is only valid in ISO mode. 2 OVRUN Data Overrun Bit. This bit is set by hardware when an incoming data packet cannot be loaded into the OUT endpoint FIFO. This bit is only valid in ISO mode, and must be cleared by software. 0: No data overrun. 1: A data packet was lost because of a full FIFO since this flag was last cleared. ec om 3 FIFOFUL OUT FIFO Full. This bit indicates the contents of the OUT FIFO. If double buffering is enabled (DBIEN = 1), the FIFO is full when the FIFO contains two packets. If DBIEN = 0, the FIFO is full when the FIFO contains one packet. 0: OUT endpoint FIFO is not full. 1: OUT endpoint FIFO is full. N ot R 1 0 191 OPRDY OUT Packet Ready. Hardware sets this bit to 1 and generates an interrupt when a data packet is available. Software should clear this bit after each data packet is unloaded from the OUT endpoint FIFO. Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 3 2 Name DBOEN ISO Type R/W R/W R R R R Reset 0 0 0 0 0 0 USB Register Address = 0x15 Bit Name ISO 5:0 Unused R R 0 0 N ew 6 0 Double-buffer Enable. 0: Double-buffering disabled for the selected OUT endpoint. 1: Double-buffering enabled for the selected OUT endpoint. Isochronous Transfer Enable. This bit enables/disables isochronous transfers on the current endpoint. 0: Endpoint configured for bulk/interrupt transfers. 1: Endpoint configured for isochronous transfers. fo r DBOEN Function Read = 000000b. Write = don’t care. m en de d 7 1 D Bit es ig ns USB Register Definition 23.23. EOUTCSRH: USB0 OUT Endpoint Control High Byte USB Register Definition 23.24. EOUTCNTL: USB0 OUT Endpoint Count Low Bit 7 6 5 4 3 2 1 0 0 0 0 0 EOCL[7:0] Name R Type 0 0 0 0 om Reset USB Register Address = 0x16 Bit Name Function N ot R ec 7:0 EOCL[7:0] OUT Endpoint Count Low Byte. EOCL holds the lower 8-bits of the 10-bit number of data bytes in the last received packet in the current OUT endpoint FIFO. This number is only valid while OPRDY = 1. Rev. 1.3 192 C8051T620/1/6/7 & C8051T320/1/2/3 Bit 7 6 5 4 3 2 es ig ns USB Register Definition 23.25. EOUTCNTH: USB0 OUT Endpoint Count High 1 0 EOCH[1:0] Type R R R R R R Reset 0 0 0 0 0 0 USB Register Address = 0x17 Bit Name Function R R 0 0 D Name N ot R ec om m en de d fo r N ew 7:2 Unused Read = 000000b. Write = don’t care. 1:0 EOCH[1:0] OUT Endpoint Count High Byte. EOCH holds the upper 2-bits of the 10-bit number of data bytes in the last received packet in the current OUT endpoint FIFO. This number is only valid while OPRDY = 1. 193 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 24. SMBus es ig ns The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specification, version 1.1, and compatible with the I2C serial bus. Reads and writes to the interface by the system controller are byte oriented with the SMBus interface autonomously controlling the serial transfer of the data. Data can be transferred at up to 1/20th of the system clock as a master or slave (this can be faster than allowed by the SMBus specification, depending on the system clock used). A method of extending the clock-low duration is available to accommodate devices with different speed capabilities on the same bus. N ot R ec om m en de d fo r N ew D The SMBus interface may operate as a master and/or slave, and may function on a bus with multiple masters. The SMBus provides control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration logic, and START/STOP control and generation. The SMBus peripheral can be fully driven by software (i.e., software accepts/rejects slave addresses, and generates ACKs), or hardware slave address recognition and automatic ACK generation can be enabled to minimize software overhead. A block diagram of the SMBus peripheral and the associated SFRs is shown in Figure 24.1. Figure 24.1. SMBus Block Diagram Rev. 1.3 194 C8051T620/1/6/7 & C8051T320/1/2/3 24.1. Supporting Documents 1. The I2C-Bus and How to Use It (including specifications), Philips Semiconductor. 2. The I2C-Bus Specification—Version 2.0, Philips Semiconductor. 3. System Management Bus Specification—Version 1.1, SBS Implementers Forum. 24.2. SMBus Configuration es ig ns It is assumed the reader is familiar with or has access to the following supporting documents: m en de d fo r N ew D Figure 24.2 shows a typical SMBus configuration. The SMBus specification allows any recessive voltage between 3.0 V and 5.0 V; different devices on the bus may operate at different voltage levels. The bi-directional SCL (serial clock) and SDA (serial data) lines must be connected to a positive power supply voltage through a pullup resistor or similar circuit. Every device connected to the bus must have an open-drain or open-collector output for both the SCL and SDA lines, so that both are pulled high (recessive state) when the bus is free. The maximum number of devices on the bus is limited only by the requirement that the rise and fall times on the bus not exceed 300 ns and 1000 ns, respectively. Figure 24.2. Typical SMBus Configuration 24.3. SMBus Operation R ec om Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver (WRITE), and data transfers from an addressed slave transmitter to a master receiver (READ). The master device initiates both types of data transfers and provides the serial clock pulses on SCL. The SMBus interface may operate as a master or a slave, and multiple master devices on the same bus are supported. If two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme is employed with a single master always winning the arbitration. Note that it is not necessary to specify one device as the Master in a system; any device who transmits a START and a slave address becomes the master for the duration of that transfer. N ot A typical SMBus transaction consists of a START condition followed by an address byte (Bits7–1: 7-bit slave address; Bit0: R/W direction bit), one or more bytes of data, and a STOP condition. Bytes that are received (by a master or slave) are acknowledged (ACK) with a low SDA during a high SCL (see Figure 24.3). If the receiving device does not ACK, the transmitting device will read a NACK (not acknowledge), which is a high SDA during a high SCL. The direction bit (R/W) occupies the least-significant bit position of the address byte. The direction bit is set to logic 1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation. 195 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 N ew D es ig ns All transactions are initiated by a master, with one or more addressed slave devices as the target. The master generates the START condition and then transmits the slave address and direction bit. If the transaction is a WRITE operation from the master to the slave, the master transmits the data a byte at a time waiting for an ACK from the slave at the end of each byte. For READ operations, the slave transmits the data waiting for an ACK from the master at the end of each byte. At the end of the data transfer, the master generates a STOP condition to terminate the transaction and free the bus. Figure 24.3 illustrates a typical SMBus transaction. Figure 24.3. SMBus Transaction m en de d fo r 24.3.1. Transmitter Vs. Receiver On the SMBus communications interface, a device is the “transmitter” when it is sending an address or data byte to another device on the bus. A device is a “receiver” when an address or data byte is being sent to it from another device on the bus. The transmitter controls the SDA line during the address or data byte. After each byte of address or data information is sent by the transmitter, the receiver sends an ACK or NACK bit during the ACK phase of the transfer, during which time the receiver controls the SDA line. om 24.3.2. Arbitration A master may start a transfer only if the bus is free. The bus is free after a STOP condition or after the SCL and SDA lines remain high for a specified time (see Section “24.3.5. SCL High (SMBus Free) Timeout” on page 197). In the event that two or more devices attempt to begin a transfer at the same time, an arbitration scheme is employed to force one master to give up the bus. The master devices continue transmitting until one attempts a HIGH while the other transmits a LOW. Since the bus is open-drain, the bus will be pulled LOW. The master attempting the HIGH will detect a LOW SDA and lose the arbitration. The winning master continues its transmission without interruption; the losing master becomes a slave and receives the rest of the transfer if addressed. This arbitration scheme is non-destructive: one device always wins, and no data is lost. R ec 24.3.3. Clock Low Extension SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line LOW to extend the clock low period, effectively decreasing the serial clock frequency. N ot 24.3.4. SCL Low Timeout If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore, the master cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than 25 ms as a “timeout” condition. Devices that have detected the timeout condition must reset the communication no later than 10 ms after detecting the timeout condition. When the SMBTOE bit in SMB0CF is set, Timer 3 is used to detect SCL low timeouts. Timer 3 is forced to reload when SCL is high, and allowed to count when SCL is low. With Timer 3 enabled and configured to Rev. 1.3 196 C8051T620/1/6/7 & C8051T320/1/2/3 overflow after 25 ms (and SMBTOE set), the Timer 3 interrupt service routine can be used to reset (disable and re-enable) the SMBus in the event of an SCL low timeout. es ig ns 24.3.5. SCL High (SMBus Free) Timeout The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 μs, the bus is designated as free. When the SMBFTE bit in SMB0CF is set, the bus will be considered free if SCL and SDA remain high for more than 10 SMBus clock source periods (as defined by the timer configured for the SMBus clock source). If the SMBus is waiting to generate a Master START, the START will be generated following this timeout. A clock source is required for free timeout detection, even in a slave-only implementation. 24.4. Using the SMBus       m en de d  Byte-wise serial data transfers Clock signal generation on SCL (Master Mode only) and SDA data synchronization Timeout/bus error recognition, as defined by the SMB0CF configuration register START/STOP timing, detection, and generation Bus arbitration Interrupt generation Status information Optional hardware recognition of slave address and automatic acknowledgement of address/data fo r  N ew D The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting control for serial transfers; higher level protocol is determined by user software. The SMBus interface provides the following application-independent features: SMBus interrupts are generated for each data byte or slave address that is transferred. When hardware acknowledgement is disabled, the point at which the interrupt is generated depends on whether the hardware is acting as a data transmitter or receiver. When a transmitter (i.e., sending address/data, receiving an ACK), this interrupt is generated after the ACK cycle so that software may read the received ACK value; when receiving data (i.e., receiving address/data, sending an ACK), this interrupt is generated before the ACK cycle so that software may define the outgoing ACK value. If hardware acknowledgement is enabled, these interrupts are always generated after the ACK cycle. See Section 24.5 for more details on transmission sequences. om Interrupts are also generated to indicate the beginning of a transfer when a master (START generated), or the end of a transfer when a slave (STOP detected). Software should read the SMB0CN (SMBus Control register) to find the cause of the SMBus interrupt. The SMB0CN register is described in Section 24.4.2; Table 24.5 provides a quick SMB0CN decoding reference. N ot R ec 24.4.1. SMBus Configuration Register The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes, select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the INH bit. With slave events inhibited, the SMBus interface will still monitor the SCL and SDA pins; however, the interface will NACK all received addresses and will not generate any slave interrupts. When the INH bit is set, all slave events will be inhibited following the next START (interrupts will continue for the duration of the current transfer). 197 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 Table 24.1. SMBus Clock Source Selection SMBCS0 0 1 0 1 SMBus Clock Source Timer 0 Overflow Timer 1 Overflow Timer 2 High Byte Overflow Timer 2 Low Byte Overflow es ig ns SMBCS1 0 0 1 1 N ew D The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or when the Free Timeout detection is enabled. When operating as a master, overflows from the selected source determine the absolute minimum SCL low and high times as defined in Equation 24.1. Note that the selected clock source may be shared by other peripherals so long as the timer is left running at all times. For example, Timer 1 overflows may generate the SMBus and UART baud rates simultaneously. Timer configuration is covered in Section “28. Timers” on page 246. 1 T HighMin = T LowMin = -----------------------------------------------f ClockSourceOverflow fo r Equation 24.1. Minimum SCL High and Low Times m en de d The selected clock source should be configured to establish the minimum SCL High and Low times as per Equation 24.1. When the interface is operating as a master (and SCL is not driven or extended by any other devices on the bus), the typical SMBus bit rate is approximated by Equation 24.2. f ClockSourceOverflow BitRate = ----------------------------------------------3 Equation 24.2. Typical SMBus Bit Rate N ot R ec om Figure 24.4 shows the typical SCL generation described by Equation 24.2. Notice that THIGH is typically twice as large as TLOW. The actual SCL output may vary due to other devices on the bus (SCL may be extended low by slower slave devices, or driven low by contending master devices). The bit rate when operating as a master will never exceed the limits defined by equation Equation 24.1. Figure 24.4. Typical SMBus SCL Generation Rev. 1.3 198 C8051T620/1/6/7 & C8051T320/1/2/3 Table 24.2. Minimum SDA Setup and Hold Times 1 Minimum SDA Hold Time 3 system clocks D 0 Minimum SDA Setup Time Tlow – 4 system clocks or 1 system clock + s/w delay* 11 system clocks 12 system clocks N ew EXTHOLD es ig ns Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA setup time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high. The minimum SDA hold time defines the absolute minimum time that the current SDA value remains stable after SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 24.2 shows the minimum setup and hold times for the two EXTHOLD settings. Setup and hold time extensions are typically necessary when SYSCLK is above 10 MHz. Note: Setup Time for ACK bit transmissions and the MSB of all data transfers. When using software acknowledgement, the s/w delay occurs between the time SMB0DAT or ACK is written and when SI is cleared. Note that if SI is cleared in the same write that defines the outgoing ACK value, s/w delay is zero. fo r With the SMBTOE bit set, Timer 3 should be configured to overflow after 25 ms in order to detect SCL low timeouts (see Section “24.3.4. SCL Low Timeout” on page 196). The SMBus interface will force Timer 3 to reload while SCL is high, and allow Timer 3 to count when SCL is low. The Timer 3 interrupt service routine should be used to reset SMBus communication by disabling and re-enabling the SMBus. N ot R ec om m en de d SMBus Free Timeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see Figure 24.4). 199 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 Bit 7 6 5 Name ENSMB INH BUSY Type R/W R/W R R/W R/W R/W Reset 0 0 0 0 0 0 EXTHOLD SMBTOE SFR Address = 0xC1 Bit Name 5 BUSY 4 EXTHOLD 3 SMBTOE 2 SMBFTE Function SMBCS[1:0] R/W 0 0 SMBus Enable. This bit enables the SMBus interface when set to 1. When enabled, the interface constantly monitors the SDA and SCL pins. N ew INH SMBFTE 0 SMBus Slave Inhibit. When this bit is set to logic 1, the SMBus does not generate an interrupt when slave events occur. This effectively removes the SMBus slave from the bus. Master Mode interrupts are not affected. fo r 6 1 SMBus Busy Indicator. This bit is set to logic 1 by hardware when a transfer is in progress. It is cleared to logic 0 when a STOP or free-timeout is sensed. m en de d ENSMB 2 SMBus Setup and Hold Time Extension Enable. This bit controls the SDA setup and hold times according to Table 24.2. 0: SDA Extended Setup and Hold Times disabled. 1: SDA Extended Setup and Hold Times enabled. SMBus SCL Timeout Detection Enable. This bit enables SCL low timeout detection. If set to logic 1, the SMBus forces Timer 3 to reload while SCL is high and allows Timer 3 to count when SCL goes low. If Timer 3 is configured to Split Mode, only the High Byte of the timer is held in reload while SCL is high. Timer 3 should be programmed to generate interrupts at 25 ms, and the Timer 3 interrupt service routine should reset SMBus communication. ec om 7 3 D 4 es ig ns SFR Definition 24.1. SMB0CF: SMBus Clock/Configuration SMBus Free Timeout Detection Enable. When this bit is set to logic 1, the bus will be considered free if SCL and SDA remain high for more than 10 SMBus clock source periods. N ot R 1:0 SMBCS[1:0] SMBus Clock Source Selection. These two bits select the SMBus clock source, which is used to generate the SMBus bit rate. The selected device should be configured according to Equation 24.1. 00: Timer 0 Overflow 01: Timer 1 Overflow 10: Timer 2 High Byte Overflow 11: Timer 2 Low Byte Overflow Rev. 1.3 200 C8051T620/1/6/7 & C8051T320/1/2/3 es ig ns 24.4.2. SMB0CN Control Register SMB0CN is used to control the interface and to provide status information (see SFR Definition 24.2). The higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to jump to service routines. MASTER indicates whether a device is the master or slave during the current transfer. TXMODE indicates whether the device is transmitting or receiving data for the current byte. D STA and STO indicate that a START and/or STOP has been detected or generated since the last SMBus interrupt. STA and STO are also used to generate START and STOP conditions when operating as a master. Writing a 1 to STA will cause the SMBus interface to enter Master Mode and generate a START when the bus becomes free (STA is not cleared by hardware after the START is generated). Writing a 1 to STO while in Master Mode will cause the interface to generate a STOP and end the current transfer after the next ACK cycle. If STO and STA are both set (while in Master Mode), a STOP followed by a START will be generated. N ew The ARBLOST bit indicates that the interface has lost an arbitration. This may occur anytime the interface is transmitting (master or slave). A lost arbitration while operating as a slave indicates a bus error condition. ARBLOST is cleared by hardware each time SI is cleared. The SI bit (SMBus Interrupt Flag) is set at the beginning and end of each transfer, after each byte frame, or when an arbitration is lost; see Table 24.3 for more details. fo r Important Note About the SI Bit: The SMBus interface is stalled while SI is set; thus SCL is held low, and the bus is stalled until software clears SI. m en de d 24.4.2.1. Software ACK Generation When the EHACK bit in register SMB0ADM is cleared to 0, the firmware on the device must detect incoming slave addresses and ACK or NACK the slave address and incoming data bytes. As a receiver, writing the ACK bit defines the outgoing ACK value; as a transmitter, reading the ACK bit indicates the value received during the last ACK cycle. ACKRQ is set each time a byte is received, indicating that an outgoing ACK value is needed. When ACKRQ is set, software should write the desired outgoing value to the ACK bit before clearing SI. A NACK will be generated if software does not write the ACK bit before clearing SI. SDA will reflect the defined ACK value immediately following a write to the ACK bit; however SCL will remain low until SI is cleared. If a received slave address is not acknowledged, further slave events will be ignored until the next START is detected. ec om 24.4.2.2. Hardware ACK Generation When the EHACK bit in register SMB0ADM is set to 1, automatic slave address recognition and ACK generation is enabled. More detail about automatic slave address recognition can be found in Section 24.4.3. As a receiver, the value currently specified by the ACK bit will be automatically sent on the bus during the ACK cycle of an incoming data byte. As a transmitter, reading the ACK bit indicates the value received on the last ACK cycle. The ACKRQ bit is not used when hardware ACK generation is enabled. If a received slave address is NACKed by hardware, further slave events will be ignored until the next START is detected, and no interrupt will be generated. N ot R Table 24.3 lists all sources for hardware changes to the SMB0CN bits. Refer to Table 24.5 for SMBus status decoding using the SMB0CN register. 201 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 3 2 Name MASTER TXMODE STA STO ACKRQ ARBLOST Type R R R/W R/W R R Reset 0 0 0 0 0 0 SFR Address = 0xC0; Bit-Addressable Bit Name Description Read 1 0 ACK SI R/W R/W 0 0 D Bit es ig ns SFR Definition 24.2. SMB0CN: SMBus Control Write MASTER SMBus Master/Slave Indicator. This read-only bit indicates when the SMBus is operating as a master. 0: SMBus operating in slave mode. 1: SMBus operating in master mode. N/A 6 TXMODE SMBus Transmit Mode Indicator. This read-only bit indicates when the SMBus is operating as a transmitter. 0: SMBus in Receiver Mode. 1: SMBus in Transmitter Mode. N/A 0: No Start generated. 1: When Configured as a Master, initiates a START or repeated START. 0: No STOP condition is transmitted. 1: When configured as a Master, causes a STOP condition to be transmitted after the next ACK cycle. Cleared by Hardware. N/A fo r N ew 7 STA SMBus Start Flag. 4 STO SMBus Stop Flag. 0: No Start or repeated Start detected. 1: Start or repeated Start detected. 0: No Stop condition detected. 1: Stop condition detected (if in Slave Mode) or pending (if in Master Mode). 3 ACKRQ SMBus Acknowledge Request. 0: No Ack requested 1: ACK requested om ARBLOST SMBus Arbitration Lost Indicator. ec 2 m en de d 5 ACK R 1 N ot 0 SI SMBus Acknowledge. 0: No arbitration error. 1: Arbitration Lost N/A 0: NACK received. 1: ACK received. 0: Send NACK 1: Send ACK SMBus Interrupt Flag. 0: No interrupt pending This bit is set by hardware 1: Interrupt Pending under the conditions listed in Table 15.3. SI must be cleared by software. While SI is set, SCL is held low and the SMBus is stalled. Rev. 1.3 0: Clear interrupt, and initiate next state machine event. 1: Force interrupt. 202 C8051T620/1/6/7 & C8051T320/1/2/3 Table 24.3. Sources for Hardware Changes to SMB0CN    ACKRQ    ACK     SI A START followed by an address byte is received. A STOP is detected while addressed as a slave. Arbitration is lost due to a detected STOP. A byte has been received and an ACK response value is needed (only when hardware ACK is not enabled). A repeated START is detected as a MASTER when STA is low (unwanted repeated START). SCL is sensed low while attempting to generate a STOP or repeated START condition. SDA is sensed low while transmitting a 1 (excluding ACK bits). The incoming ACK value is low (ACKNOWLEDGE). A START has been generated. Lost arbitration. A byte has been transmitted and an ACK/NACK received. A byte has been received. A START or repeated START followed by a slave address + R/W has been received. A STOP has been received.   A pending STOP is generated.   After each ACK cycle.  Each time SI is cleared.   The incoming ACK value is high (NOT ACKNOWLEDGE). Must be cleared by software. om   es ig ns   N ew  STO ARBLOST  fo r STA START is generated. SMB0DAT is written before the start of an SMBus frame. Cleared by Hardware When: A STOP is generated. Arbitration is lost. A START is detected. Arbitration is lost. SMB0DAT is not written before the start of an SMBus frame. Must be cleared by software.    TXMODE Set by Hardware When: A START is generated. m en de d MASTER  D Bit  N ot R ec 24.4.3. Hardware Slave Address Recognition The SMBus hardware has the capability to automatically recognize incoming slave addresses and send an ACK without software intervention. Automatic slave address recognition is enabled by setting the EHACK bit in register SMB0ADM to 1. This will enable both automatic slave address recognition and automatic hardware ACK generation for received bytes (as a master or slave). More detail on automatic hardware ACK generation can be found in Section 24.4.2.2. The registers used to define which address(es) are recognized by the hardware are the SMBus Slave Address register (SFR Definition 24.3) and the SMBus Slave Address Mask register (SFR Definition 24.4). A single address or range of addresses (including the General Call Address 0x00) can be specified using these two registers. The most-significant seven bits of the two registers are used to define which addresses will be ACKed. A 1 in bit positions of the slave address mask SLVM[6:0] enable a comparison between the received slave address and the hardware’s slave address SLV[6:0] for those bits. A 0 in a bit of the slave address mask means that bit will be treated as a “don’t care” for comparison purposes. 203 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 es ig ns In this case, either a 1 or a 0 value are acceptable on the incoming slave address. Additionally, if the GC bit in register SMB0ADR is set to 1, hardware will recognize the General Call Address (0x00). Table 24.4 shows some example parameter settings and the slave addresses that will be recognized by hardware under those conditions. Table 24.4. Hardware Address Recognition Examples (EHACK = 1) GC bit Slave Addresses Recognized by Hardware 0 1 0 1 0 0x34 0x34, 0x00 (General Call) 0x34, 0x35 0x34, 0x35, 0x00 (General Call) 0x70, 0x74, 0x78, 0x7C D Slave Address Mask SLVM[6:0] 0x7F 0x7F 0x7E 0x7E 0x73 N ew Hardware Slave Address SLV[6:0] 0x34 0x34 0x34 0x34 0x70 SFR Definition 24.3. SMB0ADR: SMBus Slave Address 7 6 5 4 3 2 1 fo r Bit 0 Name SLV[6:0] GC Type R/W R/W 0 0 0 m en de d 0 Reset SFR Address = 0xC7 Bit Name SLV[6:0] 0 GC 0 0 0 Function SMBus Hardware Slave Address. Defines the SMBus Slave Address(es) for automatic hardware acknowledgement. Only address bits which have a 1 in the corresponding bit position in SLVM[6:0] are checked against the incoming address. This allows multiple addresses to be recognized. General Call Address Enable. When hardware address recognition is enabled (EHACK = 1), this bit will determine whether the General Call Address (0x00) is also recognized by hardware. 0: General Call Address is ignored. 1: General Call Address is recognized. N ot R ec om 7:1 0 Rev. 1.3 204 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 Name SLVM[6:0] Type R/W 1 Reset 1 1 1 SFR Address = 0xCF Bit Name 3 2 1 0 EHACK R/W 1 Function 1 1 0 D Bit es ig ns SFR Definition 24.4. SMB0ADM: SMBus Slave Address Mask SLVM[6:0] SMBus Slave Address Mask. Defines which bits of register SMB0ADR are compared with an incoming address byte, and which bits are ignored. Any bit set to 1 in SLVM[6:0] enables comparisons with the corresponding bit in SLV[6:0]. Bits set to 0 are ignored (can be either 0 or 1 in the incoming address). 0 EHACK Hardware Acknowledge Enable. Enables hardware acknowledgement of slave address and received data bytes. 0: Firmware must manually acknowledge all incoming address and data bytes. 1: Automatic Slave Address Recognition and Hardware Acknowledge is Enabled. N ot R ec om m en de d fo r N ew 7:1 205 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 es ig ns 24.4.4. Data Register The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software may safely read or write to the data register when the SI flag is set. Software should not attempt to access the SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic 0, as the interface may be in the process of shifting a byte of data into or out of the register. D Data in SMB0DAT is always shifted out MSB first. After a byte has been received, the first bit of received data is located at the MSB of SMB0DAT. While data is being shifted out, data on the bus is simultaneously being shifted in. SMB0DAT always contains the last data byte present on the bus. In the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data or address in SMB0DAT. Bit 7 6 5 4 N ew SFR Definition 24.5. SMB0DAT: SMBus Data 3 Name SMB0DAT[7:0] Type R/W 0 SFR Address = 0xC2 Bit Name 0 0 0 fo r 0 Reset 2 1 0 0 0 0 Function N ot R ec om m en de d 7:0 SMB0DAT[7:0] SMBus Data. The SMB0DAT register contains a byte of data to be transmitted on the SMBus serial interface or a byte that has just been received on the SMBus serial interface. The CPU can read from or write to this register whenever the SI serial interrupt flag (SMB0CN.0) is set to logic 1. The serial data in the register remains stable as long as the SI flag is set. When the SI flag is not set, the system may be in the process of shifting data in/out and the CPU should not attempt to access this register. Rev. 1.3 206 C8051T620/1/6/7 & C8051T320/1/2/3 24.5. SMBus Transfer Modes es ig ns The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or Slave Receiver. The SMBus interface enters Master Mode any time a START is generated, and remains in Master Mode until it loses an arbitration or generates a STOP. An SMBus interrupt is generated at the end of all SMBus byte frames. Note that the position of the ACK interrupt when operating as a receiver depends on whether hardware ACK generation is enabled. As a receiver, the interrupt for an ACK occurs before the ACK with hardware ACK generation disabled, and after the ACK when hardware ACK generation is enabled. As a transmitter, interrupts occur after the ACK, regardless of whether hardware ACK generation is enabled or not. om m en de d fo r N ew D 24.5.1. Write Sequence (Master) During a write sequence, an SMBus master writes data to a slave device. The master in this transfer will be a transmitter during the address byte, and a transmitter during all data bytes. The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the data direction bit. In this case the data direction bit (R/W) will be logic 0 (WRITE). The master then transmits one or more bytes of serial data. After each byte is transmitted, an acknowledge bit is generated by the slave. The transfer is ended when the STO bit is set and a STOP is generated. Note that the interface will switch to Master Receiver Mode if SMB0DAT is not written following a Master Transmitter interrupt. Figure 24.5 shows a typical master write sequence. Two transmit data bytes are shown, though any number of bytes may be transmitted. Notice that all of the “data byte transferred” interrupts occur after the ACK cycle in this mode, regardless of whether hardware ACK generation is enabled. N ot R ec Figure 24.5. Typical Master Write Sequence 207 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 es ig ns 24.5.2. Read Sequence (Master) During a read sequence, an SMBus master reads data from a slave device. The master in this transfer will be a transmitter during the address byte, and a receiver during all data bytes. The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the data direction bit. In this case the data direction bit (R/W) will be logic 1 (READ). Serial data is then received from the slave on SDA while the SMBus outputs the serial clock. The slave transmits one or more bytes of serial data. If hardware ACK generation is disabled, the ACKRQ is set to 1 and an interrupt is generated after each received byte. Software must write the ACK bit at that time to ACK or NACK the received byte. D With hardware ACK generation enabled, the SMBus hardware will automatically generate the ACK/NACK, and then post the interrupt. It is important to note that the appropriate ACK or NACK value should be set up by the software prior to receiving the byte when hardware ACK generation is enabled. om m en de d fo r N ew Writing a 1 to the ACK bit generates an ACK; writing a 0 generates a NACK. Software should write a 0 to the ACK bit for the last data transfer, to transmit a NACK. The interface exits Master Receiver Mode after the STO bit is set and a STOP is generated. The interface will switch to Master Transmitter Mode if SMB0DAT is written while an active Master Receiver. Figure 24.6 shows a typical master read sequence. Two received data bytes are shown, though any number of bytes may be received. Notice that the ‘data byte transferred’ interrupts occur at different places in the sequence, depending on whether hardware ACK generation is enabled. The interrupt occurs before the ACK with hardware ACK generation disabled, and after the ACK when hardware ACK generation is enabled. N ot R ec Figure 24.6. Typical Master Read Sequence Rev. 1.3 208 C8051T620/1/6/7 & C8051T320/1/2/3 es ig ns 24.5.3. Write Sequence (Slave) During a write sequence, an SMBus master writes data to a slave device. The slave in this transfer will be a receiver during the address byte, and a receiver during all data bytes. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode when a START followed by a slave address and direction bit (WRITE in this case) is received. If hardware ACK generation is disabled, upon entering Slave Receiver Mode, an interrupt is generated and the ACKRQ bit is set. The software must respond to the received slave address with an ACK, or ignore the received slave address with a NACK. If hardware ACK generation is enabled, the hardware will apply the ACK for a slave address which matches the criteria set up by SMB0ADR and SMB0ADM. The interrupt will occur after the ACK cycle. D If the received slave address is ignored (by software or hardware), slave interrupts will be inhibited until the next START is detected. If the received slave address is acknowledged, zero or more data bytes are received. N ew If hardware ACK generation is disabled, the ACKRQ is set to 1 and an interrupt is generated after each received byte. Software must write the ACK bit at that time to ACK or NACK the received byte. With hardware ACK generation enabled, the SMBus hardware will automatically generate the ACK/NACK, and then post the interrupt. It is important to note that the appropriate ACK or NACK value should be set up by the software prior to receiving the byte when hardware ACK generation is enabled. Figure 24.7. Typical Slave Write Sequence N ot R ec om m en de d fo r The interface exits Slave Receiver Mode after receiving a STOP. Note that the interface will switch to Slave Transmitter Mode if SMB0DAT is written while an active Slave Receiver. Figure 24.7 shows a typical slave write sequence. Two received data bytes are shown, though any number of bytes may be received. Notice that the ‘data byte transferred’ interrupts occur at different places in the sequence, depending on whether hardware ACK generation is enabled. The interrupt occurs before the ACK with hardware ACK generation disabled, and after the ACK when hardware ACK generation is enabled. 209 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 es ig ns 24.5.4. Read Sequence (Slave) During a read sequence, an SMBus master reads data from a slave device. The slave in this transfer will be a receiver during the address byte, and a transmitter during all data bytes. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START followed by a slave address and direction bit (READ in this case) is received. If hardware ACK generation is disabled, upon entering Slave Receiver Mode, an interrupt is generated and the ACKRQ bit is set. The software must respond to the received slave address with an ACK, or ignore the received slave address with a NACK. If hardware ACK generation is enabled, the hardware will apply the ACK for a slave address which matches the criteria set up by SMB0ADR and SMB0ADM. The interrupt will occur after the ACK cycle. ec om m en de d fo r N ew D If the received slave address is ignored (by software or hardware), slave interrupts will be inhibited until the next START is detected. If the received slave address is acknowledged, zero or more data bytes are transmitted. If the received slave address is acknowledged, data should be written to SMB0DAT to be transmitted. The interface enters slave transmitter mode, and transmits one or more bytes of data. After each byte is transmitted, the master sends an acknowledge bit; if the acknowledge bit is an ACK, SMB0DAT should be written with the next data byte. If the acknowledge bit is a NACK, SMB0DAT should not be written to before SI is cleared (an error condition may be generated if SMB0DAT is written following a received NACK while in slave transmitter mode). The interface exits slave transmitter mode after receiving a STOP. Note that the interface will switch to slave receiver mode if SMB0DAT is not written following a Slave Transmitter interrupt. Figure 24.8 shows a typical slave read sequence. Two transmitted data bytes are shown, though any number of bytes may be transmitted. Notice that all of the “data byte transferred” interrupts occur after the ACK cycle in this mode, regardless of whether hardware ACK generation is enabled. Figure 24.8. Typical Slave Read Sequence 24.6. SMBus Status Decoding N ot R The current SMBus status can be easily decoded using the SMB0CN register. The appropriate actions to take in response to an SMBus event depend on whether hardware slave address recognition and ACK generation is enabled or disabled. Table 24.5 describes the typical actions when hardware slave address recognition and ACK generation is disabled. Table 24.6 describes the typical actions when hardware slave address recognition and ACK generation is enabled. In the tables, STATUS VECTOR refers to the four upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. The shown response options are only the typical responses; application-specific procedures are allowed as long as they conform to the SMBus specification. Highlighted responses are allowed by hardware but do not conform to the SMBus specification. Rev. 1.3 210 C8051T620/1/6/7 & C8051T320/1/2/3 0 0 ACK 0 1110 0 1 X — Load next data byte into SMB0DAT. 0 0 X 1100 End transfer with STOP. 0 1 X — A master data or address byte End transfer with STOP and start 1 1 was transmitted; ACK another transfer. received. Send repeated START. 1 1 X — 0 X 1110 A master data byte was received; ACK requested. om 1 R 1100 0 X 0 X ec 1000 0 X 1 N ew A master data or address byte Set STA to restart transfer. 0 was transmitted; NACK Abort transfer. received. Switch to Master Receiver Mode 0 (clear SI without writing new data to SMB0DAT). 0 X 1000 Acknowledge received byte; Read SMB0DAT. 0 0 1 1000 Send NACK to indicate last byte, 0 and send STOP. 1 0 — Send NACK to indicate last byte, 1 and send STOP followed by START. 1 0 1110 Send ACK followed by repeated START. 1 0 1 1110 Send NACK to indicate last byte, 1 and send repeated START. 0 0 1110 Send ACK and switch to Master Transmitter Mode (write to SMB0DAT before clearing SI). 0 0 1 1100 Send NACK and switch to Master Transmitter Mode (write to SMB0DAT before clearing SI). 0 0 0 1100 m en de d 0 0 D Load slave address + R/W into SMB0DAT. fo r 1100 N ot 211 A master START was generated. ACK ARBLOST 0 X STO ACKRQ 0 Typical Response Options STA Status Vector Mode Master Transmitter Master Receiver 1110 Current SMbus State es ig ns Values to Write Values Read Next Status Vector Expected Table 24.5. SMBus Status Decoding With Hardware ACK Generation Disabled (EHACK = 0) Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 ACK 0 0 0 A slave byte was transmitted; No action required (expecting NACK received. STOP condition). 0 0 1 A slave byte was transmitted; Load SMB0DAT with next data ACK received. byte to transmit. 0 0 X 0100 0 1 X A Slave byte was transmitted; No action required (expecting error detected. Master to end transfer). 0 0 X 0001 0 0 X 0 0 1 0000 If Read, Load SMB0DAT with 0 data byte; ACK received address 0 1 0100 NACK received address. 0 0 0 — If Write, Acknowledge received address 0 0 1 0000 If Read, Load SMB0DAT with 0 Lost arbitration as master; data byte; ACK received address 1 X slave address + R/W received; ACK requested. NACK received address. 0 0 1 0100 0 0 — 1 0 0 1110 0 0 X — Lost arbitration while attempt- No action required (transfer ing a STOP. complete/aborted). 0 0 0 — Acknowledge received byte; Read SMB0DAT. 0 0 1 0000 NACK received byte. 0 0 0 — 0 0 X — 1 0 X 1110 Abort failed transfer. 0 0 X — 1110 1 Reschedule failed transfer; NACK received address. A STOP was detected while 0 X addressed as a Slave Transmitter or Slave Receiver. 1 1 X om 0 ec 0001 1 R 0000 STA STO 0 0 X 0001 fo r A slave address + R/W was received; ACK requested. If Write, Acknowledge received address m en de d 0 X 0010 Slave Receiver N ew An illegal STOP or bus error 0 X X was detected while a Slave Clear STO. Transmission was in progress. 1 A slave byte was received; 0 X ACK requested. — Clear STO. 0010 0 1 X Lost arbitration while attempt- Abort failed transfer. ing a repeated START. Reschedule failed transfer. 0001 0 1 X Lost arbitration due to a detected STOP. Reschedule failed transfer. 1 0 X 0000 1 1 X Lost arbitration while transmit- Abort failed transfer. ting a data byte as master. Reschedule failed transfer. 0 0 0 — 1 0 0 1110 N ot Bus Error Condition Typical Response Options D Current SMbus State ACK ARBLOST 0101 ACKRQ Status Vector Mode Slave Transmitter 0100 es ig ns Values to Write Values Read Next Status Vector Expected Table 24.5. SMBus Status Decoding With Hardware ACK Generation Disabled (EHACK = 0) (Continued) Rev. 1.3 212 C8051T620/1/6/7 & C8051T320/1/2/3 0 0 ACK R D 1110 0 1 X — Load next data byte into SMB0DAT. 0 0 X 1100 End transfer with STOP. 0 1 X — End transfer with STOP and start 1 A master data or address byte another transfer. 1 was transmitted; ACK Send repeated START. 1 received. Switch to Master Receiver Mode 0 (clear SI without writing new data to SMB0DAT). Set ACK for initial data byte. 1 X — 0 X 1110 0 1 1000 1 A master data byte was received; ACK sent. 1000 0 0 1100 0 X om 0 0 X 1 N ew A master data or address byte Set STA to restart transfer. 0 was transmitted; NACK Abort transfer. received. ec Master Receiver 0 0 fo r 0 N ot Load slave address + R/W into SMB0DAT. m en de d 1100 0 213 A master START was generated. ACK ARBLOST 0 X STO ACKRQ 0 Typical Response Options STA Status Vector Mode Master Transmitter 1110 Current SMbus State es ig ns Values to Write Values Read Next Status Vector Expected Table 24.6. SMBus Status Decoding With Hardware ACK Generation Enabled (EHACK = 1) A master data byte was 0 received; NACK sent (last byte). Set ACK for next data byte; Read SMB0DAT. 0 0 1 1000 Set NACK to indicate next data byte as the last data byte; Read SMB0DAT. 0 0 0 1000 Initiate repeated START. 1 0 0 1110 Switch to Master Transmitter 0 Mode (write to SMB0DAT before clearing SI). 0 X 1100 Read SMB0DAT; send STOP. 0 1 0 — Read SMB0DAT; Send STOP followed by START. 1 1 0 1110 Initiate repeated START. 1 0 0 1110 0 X 1100 Switch to Master Transmitter 0 Mode (write to SMB0DAT before clearing SI). Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 ACK 0 0 0 A slave byte was transmitted; No action required (expecting NACK received. STOP condition). 0 0 1 A slave byte was transmitted; Load SMB0DAT with next data ACK received. byte to transmit. 0 0 X 0100 0 1 X A Slave byte was transmitted; No action required (expecting error detected. Master to end transfer). 0 0 X 0001 0 0 X If Write, Set ACK for first data byte. 0 0 If Read, Load SMB0DAT with data byte 0 0 X 0100 If Write, Set ACK for first data byte. 0 0 0 0 X 0100 1 0 X 1110 0 0 X — Lost arbitration while attempt- No action required (transfer ing a STOP. complete/aborted). 0 0 0 — Set ACK for next data byte; Read SMB0DAT. 0 0 1 0000 Set NACK for next data byte; Read SMB0DAT. 0 0 0 0000 0 0 X — 1 0 X 1110 Abort failed transfer. 0 0 X — 0 X 0 N ew m en de d 0010 A slave address + R/W was received; ACK sent. fo r An illegal STOP or bus error 0 X X was detected while a Slave Clear STO. Transmission was in progress. 0 Lost arbitration as master; 1 X slave address + R/W received; If Read, Load SMB0DAT with ACK sent. data byte Reschedule failed transfer 0 A STOP was detected while 0 X addressed as a Slave Transmitter or Slave Receiver. 0 1 X 0001 om Slave Receiver 0 0 X A slave byte was received. STO 0 0 X 0001 1 1 — 0000 0000 Clear STO. 0010 0 1 X Lost arbitration while attempt- Abort failed transfer. ing a repeated START. Reschedule failed transfer. 0001 0 1 X Lost arbitration due to a detected STOP. Reschedule failed transfer. 1 0 X 1110 0000 0 1 X Lost arbitration while transmit- Abort failed transfer. ting a data byte as master. Reschedule failed transfer. 0 0 X — 1 0 X 1110 N ot Bus Error Condition R ec 0000 STA Typical Response Options D Current SMbus State ACK ARBLOST 0101 ACKRQ Status Vector Mode Slave Transmitter 0100 es ig ns Values to Write Values Read Next Status Vector Expected Table 24.6. SMBus Status Decoding With Hardware ACK Generation Enabled (EHACK = 1) (Continued) Rev. 1.3 214 C8051T620/1/6/7 & C8051T320/1/2/3 25. UART0 es ig ns UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in Section “25.1. Enhanced Baud Rate Generation” on page 216). Received data buffering allows UART0 to start reception of a second incoming data byte before software has finished reading the previous data byte. D UART0 has two associated SFRs: Serial Control Register 0 (SCON0) and Serial Data Buffer 0 (SBUF0). The single SBUF0 location provides access to both transmit and receive registers. Writes to SBUF0 always access the Transmit register. Reads of SBUF0 always access the buffered Receive register; it is not possible to read data from the Transmit register. N ot R ec om m en de d fo r N ew With UART0 interrupts enabled, an interrupt is generated each time a transmit is completed (TI0 is set in SCON0), or a data byte has been received (RI0 is set in SCON0). The UART0 interrupt flags are not cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually by software, allowing software to determine the cause of the UART0 interrupt (transmit complete or receive complete). Figure 25.1. UART0 Block Diagram Rev. 1.3 215 C8051T620/1/6/7 & C8051T320/1/2/3 25.1. Enhanced Baud Rate Generation fo r N ew D es ig ns The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 25.2), which is not useraccessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates. The RX Timer runs when Timer 1 is enabled, and uses the same reload value (TH1). However, an RX Timer reload is forced when a START condition is detected on the RX pin. This allows a receive to begin any time a START is detected, independent of the TX Timer state. m en de d Figure 25.2. UART0 Baud Rate Logic Timer 1 should be configured for Mode 2, 8-bit auto-reload (see Section “28.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload” on page 249). The Timer 1 reload value should be set so that overflows will occur at two times the desired UART baud rate frequency. Note that Timer 1 may be clocked by one of six sources: SYSCLK, SYSCLK/4, SYSCLK/12, SYSCLK/48, the external oscillator clock/8, or an external input T1. For any given Timer 1 clock source, the UART0 baud rate is determined by Equation 25.1-A and Equation 25.1-B. om A) ec B) UARTBaudRate = 1---  T1_Overflow_Rate 2 T1 CLK T1_Overflow_Rate = ------------------------256 – TH1 Equation 25.1. UART0 Baud Rate N ot R Where T1CLK is the frequency of the clock supplied to Timer 1, and T1H is the high byte of Timer 1 (reload value). Timer 1 clock frequency is selected as described in Section “28. Timers” on page 246. A quick reference for typical baud rates and system clock frequencies is given in Table 25.1 through Table 25.2. The internal oscillator may still generate the system clock when the external oscillator is driving Timer 1. 216 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 25.2. Operational Modes N ew D es ig ns UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown in Figure 25.3. Figure 25.3. UART Interconnect Diagram fo r 25.2.1. 8-Bit UART 8-Bit UART mode uses a total of 10 bits per data byte: one start bit, eight data bits (LSB first), and one stop bit. Data are transmitted LSB first from the TX0 pin and received at the RX0 pin. On receive, the eight data bits are stored in SBUF0 and the stop bit goes into RB80 (SCON0.2). m en de d Data transmission begins when software writes a data byte to the SBUF0 register. The TI0 Transmit Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to logic 1. After the stop bit is received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met: RI0 must be logic 0, and if MCE0 is logic 1, the stop bit must be logic 1. In the event of a receive data overrun, the first received 8 bits are latched into the SBUF0 receive register and the following overrun data bits are lost. Figure 25.4. 8-Bit UART Timing Diagram N ot R ec om If these conditions are met, the eight bits of data is stored in SBUF0, the stop bit is stored in RB80 and the RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not be set. An interrupt will occur if enabled when either TI0 or RI0 is set. Rev. 1.3 217 C8051T620/1/6/7 & C8051T320/1/2/3 es ig ns 25.2.2. 9-Bit UART 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programmable ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80 (SCON0.3), which is assigned by user software. It can be assigned the value of the parity flag (bit P in register PSW) for error detection, or used in multiprocessor communications. On receive, the ninth data bit goes into RB80 (SCON0.2) and the stop bit is ignored. fo r N ew D Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI0 Transmit Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to 1. After the stop bit is received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met: (1) RI0 must be logic 0, and (2) if MCE0 is logic 1, the 9th bit must be logic 1 (when MCE0 is logic 0, the state of the ninth data bit is unimportant). If these conditions are met, the eight bits of data are stored in SBUF0, the ninth bit is stored in RB80, and the RI0 flag is set to 1. If the above conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not be set to 1. A UART0 interrupt will occur if enabled when either TI0 or RI0 is set to 1. N ot R ec om m en de d Figure 25.5. 9-Bit UART Timing Diagram 218 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 25.3. Multiprocessor Communications es ig ns 9-Bit UART mode supports multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or more slaves, it first sends an address byte to select the target(s). An address byte differs from a data byte in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0. D Setting the MCE0 bit (SCON0.5) of a slave processor configures its UART such that when a stop bit is received, the UART will generate an interrupt only if the ninth bit is logic 1 (RB80 = 1) signifying an address byte has been received. In the UART interrupt handler, software will compare the received address with the slave's own assigned 8-bit address. If the addresses match, the slave will clear its MCE0 bit to enable interrupts on the reception of the following data byte(s). Slaves that weren't addressed leave their MCE0 bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the data. Once the entire message is received, the addressed slave resets its MCE0 bit to ignore all transmissions until it receives the next address byte. m en de d fo r N ew Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. The master processor can be configured to receive all transmissions or a protocol can be implemented such that the master/slave role is temporarily reversed to enable half-duplex transmission between the original master and slave(s). N ot R ec om Figure 25.6. UART Multi-Processor Mode Interconnect Diagram Rev. 1.3 219 C8051T620/1/6/7 & C8051T320/1/2/3 6 Name S0MODE Type R/W Reset 0 5 4 3 2 MCE0 REN0 TB80 RB80 R R/W R/W R/W R/W 1 0 0 0 0 SFR Address = 0x98; Bit-Addressable Bit Name 7 Function S0MODE Serial Port 0 Operation Mode. Selects the UART0 Operation Mode. 0: 8-bit UART with Variable Baud Rate. 1: 9-bit UART with Variable Baud Rate. 0 TI0 RI0 R/W R/W 0 0 6 Unused 5 MCE0 Multiprocessor Communication Enable. The function of this bit is dependent on the Serial Port 0 Operation Mode: Mode 0: Checks for valid stop bit. 0: Logic level of stop bit is ignored. 1: RI0 will only be activated if stop bit is logic level 1. Mode 1: Multiprocessor Communications Enable. 0: Logic level of ninth bit is ignored. 1: RI0 is set and an interrupt is generated only when the ninth bit is logic 1. 4 REN0 Receive Enable. 0: UART0 reception disabled. 1: UART0 reception enabled. 3 TB80 Ninth Transmission Bit. The logic level of this bit will be sent as the ninth transmission bit in 9-bit UART Mode (Mode 1). Unused in 8-bit mode (Mode 0). 2 RB80 om m en de d fo r Read = 1b, Write = Don’t Care. 1 D 7 N ew Bit es ig ns SFR Definition 25.1. SCON0: Serial Port 0 Control ec Ninth Receive Bit. RB80 is assigned the value of the STOP bit in Mode 0; it is assigned the value of the 9th data bit in Mode 1. TI0 R 1 N ot 0 220 RI0 Transmit Interrupt Flag. Set by hardware when a byte of data has been transmitted by UART0 (after the 8th bit in 8-bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When the UART0 interrupt is enabled, setting this bit causes the CPU to vector to the UART0 interrupt service routine. This bit must be cleared manually by software. Receive Interrupt Flag. Set to 1 by hardware when a byte of data has been received by UART0 (set at the STOP bit sampling time). When the UART0 interrupt is enabled, setting this bit to 1 causes the CPU to vector to the UART0 interrupt service routine. This bit must be cleared manually by software. Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 3 Name SBUF0[7:0] Type R/W 0 Reset 0 0 0 SFR Address = 0x99 Bit Name Function 0 1 0 0 0 SBUF0[7:0] Serial Data Buffer Bits 7–0 (MSB–LSB). This SFR accesses two registers; a transmit shift register and a receive latch register. When data is written to SBUF0, it goes to the transmit shift register and is held for serial transmission. Writing a byte to SBUF0 initiates the transmission. A read of SBUF0 returns the contents of the receive latch. N ot R ec om m en de d fo r N ew 7:0 0 2 D Bit es ig ns SFR Definition 25.2. SBUF0: Serial (UART0) Port Data Buffer Rev. 1.3 221 C8051T620/1/6/7 & C8051T320/1/2/3 Frequency: 24.5 MHz –0.32% –0.32% 0.15% –0.32% 0.15% –0.32% –0.32% 0.15% 106 212 426 848 1704 2544 10176 20448 SYSCLK SYSCLK SYSCLK SYSCLK/4 SYSCLK/12 SYSCLK/12 SYSCLK/48 SYSCLK/48 SCA1–SCA0 (pre-scale select)1 XX2 XX XX 01 00 00 10 10 T1M1 Timer 1 Reload Value (hex) 1 1 1 0 0 0 0 0 0xCB 0x96 0x2B 0x96 0xB9 0x96 0x96 0x2B T1M1 Timer 1 Reload Value (hex) 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0xD0 0xA0 0x40 0xE0 0xC0 0xA0 0xA0 0x40 0xFA 0xF4 0xE8 0xD0 0xA0 0x70 D 230400 115200 57600 28800 14400 9600 2400 1200 Oscillator Timer Clock Divide Source Factor N ew Baud Rate % Error SYSCLK from Internal Osc. Target Baud Rate (bps) es ig ns Table 25.1. Timer Settings for Standard Baud Rates Using The Internal 24.5 MHz Oscillator fo r Notes: 1. SCA1–SCA0 and T1M bit definitions can be found in Section 28.1. 2. X = Don’t care. Table 25.2. Timer Settings for Standard Baud Rates Using an External 22.1184 MHz Oscillator m en de d Baud Rate % Error 230400 115200 57600 28800 14400 9600 2400 1200 230400 115200 57600 28800 14400 9600 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% om Target Baud Rate (bps) R ec SYSCLK from Internal Osc. SYSCLK from External Osc. Frequency: 22.1184 MHz Oscillator Timer Clock Divide Source Factor 96 192 384 768 1536 2304 9216 18432 96 192 384 768 1536 2304 SYSCLK SYSCLK SYSCLK SYSCLK / 12 SYSCLK / 12 SYSCLK / 12 SYSCLK / 48 SYSCLK / 48 EXTCLK / 8 EXTCLK / 8 EXTCLK / 8 EXTCLK / 8 EXTCLK / 8 EXTCLK / 8 SCA1–SCA0 (pre-scale select)1 XX2 XX XX 00 00 00 10 10 11 11 11 11 11 11 N ot Notes: 1. SCA1–SCA0 and T1M bit definitions can be found in Section 28.1. 2. X = Don’t care. 222 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 26. UART1 es ig ns UART1 is an asynchronous, full duplex serial port offering a variety of data formatting options. A dedicated baud rate generator with a 16-bit timer and selectable prescaler is included, which can generate a wide range of baud rates (details in Section “26.1. Baud Rate Generator” on page 223). A received data FIFO allows UART1 to receive up to three data bytes before data is lost and an overflow occurs. D UART1 has six associated SFRs. Three are used for the Baud Rate Generator (SBCON1, SBRLH1, and SBRLL1), two are used for data formatting, control, and status functions (SCON1, SMOD1), and one is used to send and receive data (SBUF1). The single SBUF1 location provides access to both the transmit holding register and the receive FIFO. Writes to SBUF1 always access the Transmit Holding Register. Reads of SBUF1 always access the first byte of the Receive FIFO; it is not possible to read data from the Transmit Holding Register. Figure 26.1. UART1 Block Diagram ec om m en de d fo r N ew With UART1 interrupts enabled, an interrupt is generated each time a transmit is completed (TI1 is set in SCON1), or a data byte has been received (RI1 is set in SCON1). The UART1 interrupt flags are not cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually by software, allowing software to determine the cause of the UART1 interrupt (transmit complete or receive complete). Note that if additional bytes are available in the Receive FIFO, the RI1 bit cannot be cleared by software. 26.1. Baud Rate Generator R The UART1 baud rate is generated by a dedicated 16-bit timer which runs from the controller’s core clock (SYSCLK), and has prescaler options of 1, 4, 12, or 48. The timer and prescaler options combined allow for a wide selection of baud rates over many SYSCLK frequencies. N ot The baud rate generator is configured using three registers: SBCON1, SBRLH1, and SBRLL1. The UART1 Baud Rate Generator Control Register (SBCON1, SFR Definition ) enables or disables the baud rate generator, and selects the prescaler value for the timer. The baud rate generator must be enabled for UART1 to function. Registers SBRLH1 and SBRLL1 contain a 16-bit reload value for the dedicated 16-bit timer. The internal timer counts up from the reload value on every clock tick. On timer overflows (0xFFFF to 0x0000), the timer is reloaded. For reliable UART operation, it is recommended that the UART baud rate is not configured for baud rates faster than SYSCLK/16. The baud rate for UART1 is defined in Equation 26.1. Rev. 1.3 223 C8051T620/1/6/7 & C8051T320/1/2/3 Equation 26.1. UART1 Baud Rate es ig ns SYSCLK 1 1 Baud Rate = ---------------------------------------------------------------------------  ---  --------------------- 65536 – (SBRLH1:SBRLL1)  2 Prescaler A quick reference for typical baud rates and system clock frequencies is given in Table 26.1. Table 26.1. Baud Rate Generator Settings for Standard Baud Rates 0.16% 0.16% 0.16% 0.16% 0.08% 0.0% 0.0% 0.0% 0.16% 0.16% 0.16% 0.08% 0.04% 0.0% 0.0% 0.0% 0.16% 0.16% 0.08% 0.04% 0.02% 0.0% 0.0% 0.0% R ec om SYSCLK = 24 MHz SYSCLK = 48 MHz N ot 224 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 Reload Value in SBRLH1:SBRLL1 D 230769 115385 57692 28846 14388 9600 2400 1200 230769 115385 57692 28777 14406 9600 2400 1200 230769 115385 57554 28812 14397 9600 2400 1200 SB1PS[1:0] (Prescaler Bits) N ew 230400 115200 57600 28800 14400 9600 2400 1200 230400 115200 57600 28800 14400 9600 2400 1200 230400 115200 57600 28800 14400 9600 2400 1200 Oscillator Divide Factor 52 104 208 416 834 1250 5000 10000 104 208 416 834 1666 2500 10000 20000 208 416 834 1666 3334 5000 20000 40000 fo r Baud Rate Error m en de d Actual Baud Rate (bps) SYSCLK = 12 MHz Target Baud Rate (bps) Rev. 1.3 0xFFE6 0xFFCC 0xFF98 0xFF30 0xFE5F 0xFD8F 0xF63C 0xEC78 0xFFCC 0xFF98 0xFF30 0xFE5F 0xFCBF 0xFB1E 0xEC78 0xD8F0 0xFF98 0xFF30 0xFE5F 0xFCBF 0xF97D 0xF63C 0xD8F0 0xB1E0 C8051T620/1/6/7 & C8051T320/1/2/3 26.2. Data Format fo r N ew D es ig ns UART1 has a number of available options for data formatting. Data transfers begin with a start bit (logic low), followed by the data bits (sent LSB-first), a parity or extra bit (if selected), and end with one or two stop bits (logic high). The data length is variable between 5 and 8 bits. A parity bit can be appended to the data, and automatically generated and detected by hardware for even, odd, mark, or space parity. The stop bit length is selectable between short (1 bit time) and long (1.5 or 2 bit times), and a multi-processor communication mode is available for implementing networked UART buses. All of the data formatting options can be configured using the SMOD1 register, shown in SFR Definition . Figure 26.2 shows the timing for a UART1 transaction without parity or an extra bit enabled. Figure 26.3 shows the timing for a UART1 transaction with parity enabled (PE1 = 1). Figure 26.4 is an example of a UART1 transaction when the extra bit is enabled (XBE1 = 1). Note that the extra bit feature is not available when parity is enabled, and the second stop bit is only an option for data lengths of 6, 7, or 8 bits. Figure 26.3. UART1 Timing With Parity N ot R ec om m en de d Figure 26.2. UART1 Timing Without Parity or Extra Bit Figure 26.4. UART1 Timing With Extra Bit Rev. 1.3 225 C8051T620/1/6/7 & C8051T320/1/2/3 26.3. Configuration and Operation es ig ns UART1 provides standard asynchronous, full duplex communication. It can operate in a point-to-point serial communications application, or as a node on a multi-processor serial interface. To operate in a pointto-point application, where there are only two devices on the serial bus, the MCE1 bit in SMOD1 should be cleared to 0. For operation as part of a multi-processor communications bus, the MCE1 and XBE1 bits should both be set to 1. In both types of applications, data is transmitted from the microcontroller on the TX1 pin, and received on the RX1 pin. The TX1 and RX1 pins are configured using the crossbar and the Port I/O registers, as detailed in Section “22. Port Input/Output” on page 138. m en de d fo r N ew D In typical UART communications, The transmit (TX) output of one device is connected to the receive (RX) input of the other device, either directly or through a bus transceiver, as shown in Figure 26.5. Figure 26.5. Typical UART Interconnect Diagram om 26.3.1. Data Transmission Data transmission is double-buffered, and begins when software writes a data byte to the SBUF1 register. Writing to SBUF1 places data in the Transmit Holding Register, and the Transmit Holding Register Empty flag (THRE1) will be cleared to 0. If the UARTs shift register is empty (i.e. no transmission is in progress) the data will be placed in the shift register, and the THRE1 bit will be set to 1. If a transmission is in progress, the data will remain in the Transmit Holding Register until the current transmission is complete. The TI1 Transmit Interrupt Flag (SCON1.1) will be set at the end of any transmission (the beginning of the stopbit time). If enabled, an interrupt will occur when TI1 is set. R ec If the extra bit function is enabled (XBE1 = 1) and the parity function is disabled (PE1 = 0), the value of the TBX1 (SCON1.3) bit will be sent in the extra bit position. When the parity function is enabled (PE1 = 1), hardware will generate the parity bit according to the selected parity type (selected with S1PT[1:0]), and append it to the data field. Note: when parity is enabled, the extra bit function is not available. N ot 26.3.2. Data Reception Data reception can begin any time after the REN1 Receive Enable bit (SCON1.4) is set to logic 1. After the stop bit is received, the data byte will be stored in the receive FIFO if the following conditions are met: the receive FIFO (3 bytes deep) must not be full, and the stop bit(s) must be logic 1. In the event that the receive FIFO is full, the incoming byte will be lost, and a Receive FIFO Overrun Error will be generated (OVR1 in register SCON1 will be set to logic 1). If the stop bit(s) were logic 0, the incoming data will not be stored in the receive FIFO. If the reception conditions are met, the data is stored in the receive FIFO, and the RI1 flag will be set. Note: when MCE1 = 1, RI1 will only be set if the extra bit was equal to 1. Data can be read from the receive FIFO by reading the SBUF1 register. 226 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 N ew D es ig ns The SBUF1 register represents the oldest byte in the FIFO. After SBUF1 is read, the next byte in the FIFO is immediately loaded into SBUF1, and space is made available in the FIFO for another incoming byte. If enabled, an interrupt will occur when RI1 is set. RI1 can only be cleared to '0' by software when there is no more information in the FIFO. The recommended procedure to empty the FIFO contents is: 1. Clear RI1 to '0' 2. Read SBUF1 3. Check RI1, and repeat at Step 1 if RI1 is set to '1'. If the extra bit function is enabled (XBE1 = 1) and the parity function is disabled (PE1 = 0), the extra bit for the oldest byte in the FIFO can be read from the RBX1 bit (SCON1.2). If the extra bit function is not enabled, the value of the stop bit for the oldest FIFO byte will be presented in RBX1. When the parity function is enabled (PE1 = 1), hardware will check the received parity bit against the selected parity type (selected with S1PT[1:0]) when receiving data. If a byte with parity error is received, the PERR1 flag will be set to 1. This flag must be cleared by software. Note: when parity is enabled, the extra bit function is not available. 26.3.3. Multiprocessor Communications UART1 supports multiprocessor communication between a master processor and one or more slave processors by special use of the extra data bit. When a master processor wants to transmit to one or more slaves, it first sends an address byte to select the target(s). An address byte differs from a data byte in that its extra bit is logic 1; in a data byte, the extra bit is always set to logic 0. m en de d fo r Setting the MCE1 bit (SMOD1.7) of a slave processor configures its UART such that when a stop bit is received, the UART will generate an interrupt only if the extra bit is logic 1 (RBX1 = 1) signifying an address byte has been received. In the UART interrupt handler, software will compare the received address with the slave's own assigned address. If the addresses match, the slave will clear its MCE1 bit to enable interrupts on the reception of the following data byte(s). Slaves that weren't addressed leave their MCE1 bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the data. Once the entire message is received, the addressed slave resets its MCE1 bit to ignore all transmissions until it receives the next address byte. N ot R ec om Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. The master processor can be configured to receive all transmissions or a protocol can be implemented such that the master/slave role is temporarily reversed to enable half-duplex transmission between the original master and slave(s). Figure 26.6. UART Multi-Processor Mode Interconnect Diagram Rev. 1.3 227 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 3 2 Name OVR1 PERR1 THRE1 REN1 TBX1 RBX1 Type R/W R/W R R/W R/W R/W Reset 0 0 1 0 0 0 SFR Address = 0xD2 Bit Name Function 1 0 TI1 RI1 R/W R/W 0 0 D Bit es ig ns SFR Definition 26.1. SCON1: UART1 Control OVR1 Receive FIFO Overrun Flag. This bit indicates a receive FIFO overrun condition, where an incoming character is discarded due to a full FIFO. This bit must be cleared to 0 by software. 0: Receive FIFO Overrun has not occurred. 1: Receive FIFO Overrun has occurred. 6 PERR1 Parity Error Flag. When parity is enabled, this bit indicates that a parity error has occurred. It is set to 1 when the parity of the oldest byte in the FIFO does not match the selected Parity Type. This bit must be cleared to 0 by software. 0: Parity Error has not occurred. 1: Parity Error has occurred. 5 THRE1 Transmit Holding Register Empty Flag. 0: Transmit Holding Register not Empty - do not write to SBUF1. 1: Transmit Holding Register Empty - it is safe to write to SBUF1. 4 REN1 Receive Enable. This bit enables/disables the UART receiver. When disabled, bytes can still be read from the receive FIFO. 0: UART1 reception disabled. 1: UART1 reception enabled. 3 TBX1 Extra Transmission Bit. The logic level of this bit will be assigned to the extra transmission bit when XBE1 = 1. This bit is not used when Parity is enabled. 2 RBX1 om m en de d fo r N ew 7 ec Extra Receive Bit. RBX1 is assigned the value of the extra bit when XBE1 = 1. If XBE1 is cleared to 0, RBX1 is assigned the logic level of the first stop bit. This bit is not valid when Parity is enabled. TI1 R 1 N ot 0 228 RI1 Transmit Interrupt Flag. Set to a 1 by hardware after data has been transmitted at the beginning of the STOP bit. When the UART1 interrupt is enabled, setting this bit causes the CPU to vector to the UART1 interrupt service routine. This bit must be cleared manually by software. Receive Interrupt Flag. Set to 1 by hardware when a byte of data has been received by UART1 (set at the STOP bit sampling time). When the UART1 interrupt is enabled, setting this bit to 1 causes the CPU to vector to the UART1 interrupt service routine. This bit must be cleared manually by software. Note that RI1 will remain set to '1' as long as there is still data in the UART FIFO. After the last byte has been shifted from the FIFO to SBUF1, RI1 can be cleared. Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 Name MCE1 S1PT[1:0] PE1 Type R/W R/W R/W Reset 0 0 0 4 0 SFR Address = 0xE5 Bit Name 4 3:2 S1DL[1:0] XBE1 SBL1 R/W R/W R/W 0 0 1 Function 1 N ew fo r Parity Enable. This bit activates hardware parity generation and checking. The parity type is selected by bits S1PT1-0 when parity is enabled. 0: Hardware parity is disabled. 1: Hardware parity is enabled. S1DL[1:0] Data Length. 00: 5-bit data 01: 6-bit data 10: 7-bit data 11: 8-bit data XBE1 Extra Bit Enable. When enabled, the value of TBX1 will be appended to the data field. 0: Extra Bit Disabled. 1: Extra Bit Enabled. ec 1 0 Multiprocessor Communication Enable. 0: RI will be activated if stop bit(s) are 1. 1: RI will be activated if stop bit(s) and extra bit are 1 (extra bit must be enabled using XBE1). Note: This function is not available when hardware parity is enabled. S1PT[1:0] Parity Type Bits. 00: Odd 01: Even 10: Mark 11: Space PE1 1 m en de d 6:5 MCE1 2 om 7 3 D Bit es ig ns SFR Definition 26.2. SMOD1: UART1 Mode SBL1 N ot R 0 Stop Bit Length. 0: Short - Stop bit is active for one bit time. 1: Long - Stop bit is active for two bit times (data length = 6, 7, or 8 bits), or 1.5 bit times (data length = 5 bits). Rev. 1.3 229 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 3 Name SBUF1[7:0] Type R/W 0 SFR Address = 0xD3 Bit Name 0 0 Description Writing a byte to SBUF1 initiates the transmission. When data is written to SBUF1, it first goes to the Transmit Holding Register, where it is held for serial transmission. When the transmit shift register is available, data is transferred into the shift register, and SBUF1 may be written again. m en de d om ec R N ot 230 0 Write fo r 7:0 SBUF1[7:0 Serial Data Buffer Bits. ] This SFR is used to both send data from the UART and to read received data from the UART1 receive FIFO. 0 Rev. 1.3 1 0 0 0 Read Reading SBUF1 retrieves data from the receive FIFO. When read, the oldest byte in the receive FIFO is returned, and removed from the FIFO. Up to three bytes may be held in the FIFO. If there are additional bytes available in the FIFO, the RI1 bit will remain at logic 1, even after being cleared by software. N ew 0 Reset 2 D Bit es ig ns SFR Definition 26.3. SBUF1: UART1 Data Buffer C8051T620/1/6/7 & C8051T320/1/2/3 Bit 7 Name Reserved 6 5 4 3 2 SB1RUN Reserved Reserved Reserved Reserved R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 SFR Address = 0xAC Bit Name Reserved SB1RUN 0 SB1PS[1:0] R/W 0 0 Function Read = 0b. Must Write 0b. N ew 7 6 1 D Type es ig ns SFR Definition 26.4. SBCON1: UART1 Baud Rate Generator Control Baud Rate Generator Enable. 0: Baud Rate Generator is disabled. UART1 will not function. 1: Baud Rate Generator is enabled. m en de d fo r 5:2 Reserved Read = 0000b. Must Write 0000b. 1:0 SB1PS[1:0] Baud Rate Prescaler Select. 00: Prescaler = 12 01: Prescaler = 4 10: Prescaler = 48 11: Prescaler = 1 SFR Definition 26.5. SBRLH1: UART1 Baud Rate Generator High Byte Bit 7 5 4 3 2 1 0 0 0 0 SBRLH1[7:0] Name R/W om Type Reset 6 0 0 0 0 SFR Address = 0xB5 Bit Name 0 ec Function N ot R 7:0 SBRLH1[7:0] UART1 Baud Rate Reload High Bits. High Byte of reload value for UART1 Baud Rate Generator. Rev. 1.3 231 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 3 Name SBRLL1[7:0] Type R/W 0 Reset 0 0 0 SFR Address = 0xB4 Bit Name 0 Function 2 0 N ot R ec om m en de d fo r N ew 7:0 SBRLL1[7:0] UART1 Baud Rate Reload Low Bits. Low Byte of reload value for UART1 Baud Rate Generator. 232 Rev. 1.3 1 0 0 0 D Bit es ig ns SFR Definition 26.6. SBRLL1: UART1 Baud Rate Generator Low Byte C8051T620/1/6/7 & C8051T320/1/2/3 27. Enhanced Serial Peripheral Interface (SPI0) N ot R ec om m en de d fo r N ew D es ig ns The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input to select SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can also be configured as a chip-select output in master mode, or disabled for 3-wire operation. Additional general purpose port I/O pins can be used to select multiple slave devices in master mode. Figure 27.1. SPI Block Diagram Rev. 1.3 233 C8051T620/1/6/7 & C8051T320/1/2/3 27.1. Signal Descriptions The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below. es ig ns 27.1.1. Master Out, Slave In (MOSI) The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It is used to serially transfer data from the master to the slave. This signal is an output when SPI0 is operating as a master and an input when SPI0 is operating as a slave. Data is transferred most-significant bit first. When configured as a master, MOSI is driven by the MSB of the shift register in both 3- and 4-wire mode. N ew D 27.1.2. Master In, Slave Out (MISO) The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device. It is used to serially transfer data from the slave to the master. This signal is an input when SPI0 is operating as a master and an output when SPI0 is operating as a slave. Data is transferred most-significant bit first. The MISO pin is placed in a high-impedance state when the SPI module is disabled and when the SPI operates in 4-wire mode as a slave that is not selected. When acting as a slave in 3-wire mode, MISO is always driven by the MSB of the shift register. fo r 27.1.3. Serial Clock (SCK) The serial clock (SCK) signal is an output from the master device and an input to slave devices. It is used to synchronize the transfer of data between the master and slave on the MOSI and MISO lines. SPI0 generates this signal when operating as a master. The SCK signal is ignored by a SPI slave when the slave is not selected (NSS = 1) in 4-wire slave mode. m en de d 27.1.4. Slave Select (NSS) The function of the slave-select (NSS) signal is dependent on the setting of the NSSMD1 and NSSMD0 bits in the SPI0CN register. There are three possible modes that can be selected with these bits: N ot R ec om 1. NSSMD[1:0] = 00: 3-Wire Master or 3-Wire Slave Mode: SPI0 operates in 3-wire mode, and NSS is disabled. When operating as a slave device, SPI0 is always selected in 3-wire mode. Since no select signal is present, SPI0 must be the only slave on the bus in 3-wire mode. This is intended for point-topoint communication between a master and one slave. 2. NSSMD[1:0] = 01: 4-Wire Slave or Multi-Master Mode: SPI0 operates in 4-wire mode, and NSS is enabled as an input. When operating as a slave, NSS selects the SPI0 device. When operating as a master, a 1-to-0 transition of the NSS signal disables the master function of SPI0 so that multiple master devices can be used on the same SPI bus. 3. NSSMD[1:0] = 1x: 4-Wire Master Mode: SPI0 operates in 4-wire mode, and NSS is enabled as an output. The setting of NSSMD0 determines what logic level the NSS pin will output. This configuration should only be used when operating SPI0 as a master device. See Figure 27.2, Figure 27.3, and Figure 27.4 for typical connection diagrams of the various operational modes. Note that the setting of NSSMD bits affects the pinout of the device. When in 3-wire master or 3-wire slave mode, the NSS pin will not be mapped by the crossbar. In all other modes, the NSS signal will be mapped to a pin on the device. See Section “22. Port Input/Output” on page 138 for general purpose port I/O and crossbar information. 234 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 27.2. SPI0 Master Mode Operation es ig ns A SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by setting the Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data register (SPI0DAT) when in master mode writes to the transmit buffer. If the SPI shift register is empty, the byte in the transmit buffer is moved to the shift register, and a data transfer begins. The SPI0 master immediately shifts out the data serially on the MOSI line while providing the serial clock on SCK. D The SPIF (SPI0CN.7) flag is set to logic 1 at the end of the transfer. If interrupts are enabled, an interrupt request is generated when the SPIF flag is set. While the SPI0 master transfers data to a slave on the MOSI line, the addressed SPI slave device simultaneously transfers the contents of its shift register to the SPI master on the MISO line in a full-duplex operation. Therefore, the SPIF flag serves as both a transmitcomplete and receive-data-ready flag. The data byte received from the slave is transferred MSB-first into the master's shift register. When a byte is fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by reading SPI0DAT. fo r N ew When configured as a master, SPI0 can operate in one of three different modes: multi-master mode, 3-wire single-master mode, and 4-wire single-master mode. The default, multi-master mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In this mode, NSS is an input to the device, and is used to disable the master SPI0 when another master is accessing the bus. When NSS is pulled low in this mode, MSTEN (SPI0CN.6) and SPIEN (SPI0CN.0) are set to 0 to disable the SPI master device, and a Mode Fault is generated (MODF, SPI0CN.5 = 1). Mode Fault will generate an interrupt if enabled. SPI0 must be manually re-enabled in software under these circumstances. In multi-master systems, devices will typically default to being slave devices while they are not acting as the system master device. In multi-master mode, slave devices can be addressed individually (if needed) using general-purpose I/O pins. Figure 27.2 shows a connection diagram between two master devices in multiple-master mode. m en de d 3-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. In this mode, NSS is not used, and is not mapped to an external port pin through the crossbar. Any slave devices that must be addressed in this mode should be selected using general-purpose I/O pins. Figure 27.3 shows a connection diagram between a master device in 3-wire master mode and a slave device. Figure 27.2. Multiple-Master Mode Connection Diagram N ot R ec om 4-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 1. In this mode, NSS is configured as an output pin, and can be used as a slave-select signal for a single SPI device. In this mode, the output value of NSS is controlled (in software) with the bit NSSMD0 (SPI0CN.2). Additional slave devices can be addressed using general-purpose I/O pins. Figure 27.4 shows a connection diagram for a master device in 4-wire master mode and two slave devices. Figure 27.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram Rev. 1.3 235 N ew D es ig ns C8051T620/1/6/7 & C8051T320/1/2/3 Figure 27.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram fo r 27.3. SPI0 Slave Mode Operation m en de d When SPI0 is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK signal. A bit counter in the SPI0 logic counts SCK edges. When 8 bits have been shifted through the shift register, the SPIF flag is set to logic 1, and the byte is copied into the receive buffer. Data is read from the receive buffer by reading SPI0DAT. A slave device cannot initiate transfers. Data to be transferred to the master device is pre-loaded into the shift register by writing to SPI0DAT. Writes to SPI0DAT are doublebuffered, and are placed in the transmit buffer first. If the shift register is empty, the contents of the transmit buffer will immediately be transferred into the shift register. When the shift register already contains data, the SPI will load the shift register with the transmit buffer’s contents after the last SCK edge of the next (or current) SPI transfer. om When configured as a slave, SPI0 can be configured for 4-wire or 3-wire operation. The default, 4-wire slave mode, is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In 4-wire mode, the NSS signal is routed to a port pin and configured as a digital input. SPI0 is enabled when NSS is logic 0, and disabled when NSS is logic 1. The bit counter is reset on a falling edge of NSS. Note that the NSS signal must be driven low at least 2 system clocks before the first active edge of SCK for each byte transfer. Figure 27.4 shows a connection diagram between two slave devices in 4-wire slave mode and a master device. N ot R ec 3-wire slave mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. NSS is not used in this mode, and is not mapped to an external port pin through the crossbar. Since there is no way of uniquely addressing the device in 3-wire slave mode, SPI0 must be the only slave device present on the bus. It is important to note that in 3-wire slave mode there is no external means of resetting the bit counter that determines when a full byte has been received. The bit counter can only be reset by disabling and reenabling SPI0 with the SPIEN bit. Figure 27.3 shows a connection diagram between a slave device in 3wire slave mode and a master device. 236 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 27.4. SPI0 Interrupt Sources es ig ns When SPI0 interrupts are enabled, the following four flags will generate an interrupt when they are set to logic 1: All of the following bits must be cleared by software.   D  The SPI Interrupt Flag, SPIF (SPI0CN.7) is set to logic 1 at the end of each byte transfer. This flag can occur in all SPI0 modes. The Write Collision Flag, WCOL (SPI0CN.6) is set to logic 1 if a write to SPI0DAT is attempted when the transmit buffer has not been emptied to the SPI shift register. When this occurs, the write to SPI0DAT will be ignored, and the transmit buffer will not be written.This flag can occur in all SPI0 modes. The Mode Fault Flag MODF (SPI0CN.5) is set to logic 1 when SPI0 is configured as a master, and for multi-master mode and the NSS pin is pulled low. When a Mode Fault occurs, the MSTEN and SPIEN bits in SPI0CN are set to logic 0 to disable SPI0 and allow another master device to access the bus. The Receive Overrun Flag RXOVRN (SPI0CN.4) is set to logic 1 when configured as a slave, and a transfer is completed and the receive buffer still holds an unread byte from a previous transfer. The new byte is not transferred to the receive buffer, allowing the previously received data byte to be read. The data byte which caused the overrun is lost. N ew  27.5. Serial Clock Phase and Polarity m en de d fo r Four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases (edge used to latch the data). The CKPOL bit (SPI0CFG.4) selects between an active-high or active-low clock. Both master and slave devices must be configured to use the same clock phase and polarity. SPI0 should be disabled (by clearing the SPIEN bit, SPI0CN.0) when changing the clock phase or polarity. The clock and data line relationships for master mode are shown in Figure 27.5. For slave mode, the clock and data relationships are shown in Figure 27.6 and Figure 27.7. Note that CKPHA should be set to 0 on both the master and slave SPI when communicating between two Silicon Labs C8051 devices. N ot R ec om The SPI0 Clock Rate Register (SPI0CKR) as shown in SFR Definition 27.3 controls the master mode serial clock frequency. This register is ignored when operating in slave mode. When the SPI is configured as a master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency or 12.5 MHz, whichever is slower. When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the system clock frequency, provided that the master issues SCK, NSS (in 4wire slave mode), and the serial input data synchronously with the slave’s system clock. If the master issues SCK, NSS, and the serial input data asynchronously, the maximum data transfer rate (bits/sec) must be less than 1/10 the system clock frequency. In the special case where the master only wants to transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the SPI slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. This is provided that the master issues SCK, NSS, and the serial input data synchronously with the slave’s system clock. Rev. 1.3 237 fo r N ew D es ig ns C8051T620/1/6/7 & C8051T320/1/2/3 Figure 27.6. Slave Mode Data/Clock Timing (CKPHA = 0) N ot R ec om m en de d Figure 27.5. Master Mode Data/Clock Timing 238 Rev. 1.3 N ew D es ig ns C8051T620/1/6/7 & C8051T320/1/2/3 27.6. SPI Special Function Registers fo r Figure 27.7. Slave Mode Data/Clock Timing (CKPHA = 1) N ot R ec om m en de d SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate Register. The four special function registers related to the operation of the SPI0 Bus are described in the following figures. Rev. 1.3 239 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 3 2 Name SPIBSY MSTEN CKPHA CKPOL SLVSEL Type R R/W R/W R/W Reset 0 0 0 0 SFR Address = 0xA1 Bit Name 1 0 NSSIN SRMT RXBMT R R R R 0 1 1 1 SPIBSY SPI Busy. This bit is set to logic 1 when a SPI transfer is in progress (master or slave mode). 6 MSTEN Master Mode Enable. 0: Disable master mode. Operate in slave mode. 1: Enable master mode. Operate as a master. 5 CKPHA SPI0 Clock Phase. 0: Data centered on first edge of SCK period.* 1: Data centered on second edge of SCK period.* 4 CKPOL SPI0 Clock Polarity. 0: SCK line low in idle state. 1: SCK line high in idle state. 3 SLVSEL 2 NSSIN 1 R ec SRMT N ot 0 RXBMT m en de d fo r N ew 7 om Function D Bit es ig ns SFR Definition 27.1. SPI0CFG: SPI0 Configuration Slave Selected Flag. This bit is set to logic 1 whenever the NSS pin is low indicating SPI0 is the selected slave. It is cleared to logic 0 when NSS is high (slave not selected). This bit does not indicate the instantaneous value at the NSS pin, but rather a de-glitched version of the pin input. NSS Instantaneous Pin Input. This bit mimics the instantaneous value that is present on the NSS port pin at the time that the register is read. This input is not de-glitched. Shift Register Empty (valid in slave mode only). This bit will be set to logic 1 when all data has been transferred in/out of the shift register, and there is no new information available to read from the transmit buffer or write to the receive buffer. It returns to logic 0 when a data byte is transferred to the shift register from the transmit buffer or by a transition on SCK. SRMT = 1 when in Master Mode. Receive Buffer Empty (valid in slave mode only). This bit will be set to logic 1 when the receive buffer has been read and contains no new information. If there is new information available in the receive buffer that has not been read, this bit will return to logic 0. RXBMT = 1 when in Master Mode. Note: In slave mode, data on MOSI is sampled in the center of each data bit. In master mode, data on MISO is sampled one SYSCLK before the end of each data bit, to provide maximum settling time for the slave device. See Table 27.1 for timing parameters. 240 Rev. 1.3 C8051T620/1/6/7 & C8051T320/1/2/3 7 6 5 4 Name SPIF WCOL MODF RXOVRN Type R/W R/W R/W R/W Reset 0 0 0 0 SFR Address = 0xF8; Bit-Addressable Bit Name 3 2 1 0 NSSMD[1:0] TXBMT SPIEN R/W R R/W 1 0 0 1 Function D Bit es ig ns SFR Definition 27.2. SPI0CN: SPI0 Control SPIF SPI0 Interrupt Flag. This bit is set to logic 1 by hardware at the end of a data transfer. If SPI interrupts are enabled, an interrupt will be generated. This bit is not automatically cleared by hardware, and must be cleared by software. 6 WCOL Write Collision Flag. This bit is set to logic 1 if a write to SPI0DAT is attempted when TXBMT is 0. When this occurs, the write to SPI0DAT will be ignored, and the transmit buffer will not be written. If SPI interrupts are enabled, an interrupt will be generated. This bit is not automatically cleared by hardware, and must be cleared by software. 5 MODF Mode Fault Flag. This bit is set to logic 1 by hardware when a master mode collision is detected (NSS is low, MSTEN = 1, and NSSMD[1:0] = 01). If SPI interrupts are enabled, an interrupt will be generated. This bit is not automatically cleared by hardware, and must be cleared by software. 4 RXOVRN m en de d fo r N ew 7 Receive Overrun Flag (valid in slave mode only). NSSMD[1:0] R ec 3:2 om This bit is set to logic 1 by hardware when the receive buffer still holds unread data from a previous transfer and the last bit of the current transfer is shifted into the SPI0 shift register. If SPI interrupts are enabled, an interrupt will be generated. This bit is not automatically cleared by hardware, and must be cleared by software. N ot 1 0 Slave Select Mode. Selects between the following NSS operation modes: (See Section 27.2 and Section 27.3). 00: 3-Wire Slave or 3-Wire Master Mode. NSS signal is not routed to a port pin. 01: 4-Wire Slave or Multi-Master Mode (Default). NSS is an input to the device. 1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from the device and will assume the value of NSSMD0. TXBMT Transmit Buffer Empty. This bit will be set to logic 0 when new data has been written to the transmit buffer. When data in the transmit buffer is transferred to the SPI shift register, this bit will be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer. SPIEN SPI0 Enable. 0: SPI disabled. 1: SPI enabled. Rev. 1.3 241 C8051T620/1/6/7 & C8051T320/1/2/3 6 5 4 Name SCR[7:0] Type R/W 0 Reset 0 0 0 SFR Address = 0xA2 Bit Name 7:0 SCR[7:0] 3 2 0 0 1 0 0 0 D 7 Function SPI0 Clock Rate. These bits determine the frequency of the SCK output when the SPI0 module is configured for master mode operation. The SCK clock frequency is a divided version of the system clock, and is given in the following equation, where SYSCLK is the system clock frequency and SPI0CKR is the 8-bit value held in the SPI0CKR register. m en de d for 0