C8051T610-GQR

C8051T610/1/2/3/4/5/6/7 Mixed-Signal Byte-Programmable EPROM MCU Analog Peripherals - 10-Bit ADC (‘T610/1/2/3/6 only) • • • • Programmable hysteresis and response time Configurable as interrupt sources Configurable as reset source (Comparator 0) Low current ( 2.2 V Voltage on RST or any Port I/O Pin (except VPP during programming) with VDD < 2.2 V respect to GND –0.3 –0.3 — — 5.8 VDD + 3.6 V V Voltage on VPP with respect to GND during a programming operation VDD > 2.4 V –0.3 — 7.0 V Duration of High-voltage on VPP pin (cumulative) VPP > (VDD + 3.6 V) — — 10 s Voltage on VDD with respect to GND Regulator in Normal Mode Regulator in Bypass Mode –0.3 –0.3 — — 4.2 1.98 V V — — 500 mA — — 100 mA Maximum Total current through VDD and GND m en de d Maximum output current sunk by RST or any Port pin D Min N ew Conditions fo r Parameter es ig ns 7. Electrical Characteristics N ot R ec om Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Rev 1.1 31 C8051T610/1/2/3/4/5/6/7 7.2. Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Conditions Min Typ es ig ns Table 7.2. Global Electrical Characteristics Max Units 3.6 1.9 V V 8.8 — 8.9 — mA mA mA mA Regulator in Normal Mode Regulator in Bypass Mode 1.8 1.7 3.0 1.8 Digital Supply Current with CPU Active VDD = 1.8 V, Clock = 25 MHz VDD = 1.8 V, Clock = 1 MHz VDD = 3.0 V, Clock = 25 MHz VDD = 3.0 V, Clock = 1 MHz — — — — 6.2 2.7 7 2.9 Digital Supply Current with CPU Inactive (not accessing EPROM) VDD = 1.8 V, Clock = 25 MHz VDD = 1.8 V, Clock = 1 MHz VDD = 3.0 V, Clock = 25 MHz VDD = 3.0 V, Clock = 1 MHz — — — — 2.2 0.41 2.3 0.42 3 — 3.1 — mA mA mA mA Digital Supply Current (shutdown) Oscillator not running (stop mode), Internal Regulator Off — 4 — µA Oscillator not running (stop or suspend mode), Internal Regulator On — 400 — µA — 1.5 — V –40 — +85 °C 0 — 25 MHz Tsysl (SYSCLK low time) 18 — — ns Tsysh (SYSCLK high time) 18 — — ns N ew fo r m en de d Digital Supply RAM Data Retention Voltage Specified Operating Temperature Range (Note 2) om SYSCLK (system clock frequency) N ot R ec Notes: 1. Analog performance is not guaranteed when VDD is below 1.8 V. 2. SYSCLK must be at least 32 kHz to enable debugging. 32 D Supply Voltage (Note 1) Rev 1.1 C8051T610/1/2/3/4/5/6/7 Min Typ Max Units VDD - 0.2 VDD - 0.1 — — — — 0.7 x VDD — -1 — — — VDD - 0.4 — — 0.6 — — — 25 — — — 0.4 0.1 — — 0.6 1 50 V V V V V V V V µA µA Min Typ Max Units — — 0.6 V RST Input High Voltage 0.75 x VDD — — V RST Input Low Voltage — — 0.6 VDD — 25 50 µA VDD POR Ramp Time — — 1 ms VDD Monitor Threshold (VRST) 1.7 1.75 1.8 V 500 625 750 µs — — 60 µs 15 — — µs — 50 — µs — 20 30 µA Output High Voltage IOH = –3 mA, Port I/O push-pull IOH = –10 µA, Port I/O push-pull IOH = –10 mA, Port I/O push-pull Output Low Voltage IOL = 8.5 mA IOL = 10 µA IOL = 25 mA Input High Voltage Input Low Voltage Input Leakage Weak Pullup Off Current Weak Pullup On, VIN = 0 V Table 7.4. Reset Electrical Characteristics –40 to +85 °C unless otherwise specified. Parameter Conditions IOL = 8.5 mA, VDD = 1.8 V to 3.6 V m en de d RST Output Low Voltage RST Input Pullup Current RST = 0.0 V Time from last system clock rising edge to reset initiation Reset Time Delay Delay between release of any reset source and code execution at location 0x0000 om Missing Clock Detector Timeout ec Minimum RST Low Time to Generate a System Reset VDD Monitor Turn-on Time VDD = VRST - 0.1 V N ot R VDD Monitor Supply Current D Conditions N ew Parameters fo r VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. es ig ns Table 7.3. Port I/O DC Electrical Characteristics Rev 1.1 33 C8051T610/1/2/3/4/5/6/7 Table 7.5. Internal Voltage Regulator Electrical Characteristics Conditions Input Voltage Range Bias Current Normal Mode Min Typ Max Units 1.8 — 3.6 V — 30 50 µA D Parameter es ig ns –40 to +85 °C unless otherwise specified. Table 7.6. EPROM Electrical Characteristics Conditions EPROM Size C8051T610/1/6/7 EPROM Size C8051T612/3/4/5 Write Cycle Time (per Byte)2 Date Code 0935 and Later Date Code prior to 0935 Typ Max Units 163841 — — bytes 8192 — — bytes 105 155 205 µs 5.75 6.0 6.25 V 6.25 6.325 6.5 V fo r Programming Voltage (VPP)3 Min N ew Parameter m en de d Notes: 1. 512 bytes at location 0x3E00 to 0x3FFF are not available for program storage. 2. The EPROM write cycle time is adjustable as part of the EPROM write sequence detailed in Section 17.1.1. The EEPROM timing listed is for date code 1119 and later. For date codes prior to 1119, the guidance in Section 17.1.1 will produce write times that are twice as long. 3. Refer to device errata for details. Table 7.7. Internal High-Frequency Oscillator Electrical Characteristics VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified. Use factory-calibrated settings. Parameter Conditions Min Typ Max Units IFCN = 11b 24 24.5 25 MHz Oscillator Supply Current (from VDD) 25 °C, VDD = 3.0 V, OSCICN.7 = 1 — 450 700 µA Power Supply Variance Constant Temperature — ±0.02 — %/V Temperature Variance Constant Supply — ±20 — ppm/°C N ot R ec om Oscillator Frequency 34 Rev 1.1 C8051T610/1/2/3/4/5/6/7 Table 7.8. ADC0 Electrical Characteristics Parameter Conditions Min Typ — — –2 –2 — 10 ±0.5 ±0.5 0 0 45 Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale Error Offset Temperature Coefficient Guaranteed Monotonic Max Units ±1 ±1 2 2 — bits LSB LSB LSB LSB ppm/°C D DC Accuracy es ig ns VDD = 3.0 V, VREF = 2.40 V (REFSL=0), –40 to +85 °C unless otherwise specified. Signal-to-Noise Plus Distortion Total Harmonic Distortion Spurious-Free Dynamic Range 56 — — 60 72 –75 — — — dB dB dB — 13 11 300 2.0 — — — — — — — 8.33 — — — — 500 MHz clocks clocks ns µs ksps 1x Gain 0.5x Gain 0 — — — — 5 3 5 VREF — — — V pF pF kΩ Operating Mode, 200 ksps — 600 900 µA — –70 — dB Up to the 5th harmonic Throughput Rate Analog Inputs m en de d Track/Hold Acquisition Time 10-bit Mode 8-bit Mode VDD >= 2.0 V VDD < 2.0 V fo r Conversion Rate SAR Conversion Clock Conversion Time in SAR Clocks ADC Input Voltage Range Sampling Capacitance N ew Dynamic performance (10 kHz sine-wave single-ended input, 1 dB below Full Scale, 200 ksps) Input Multiplexer Impedance Power Specifications N ot R ec om Power Supply Current (VDD supplied to ADC0) Power Supply Rejection Rev 1.1 35 C8051T610/1/2/3/4/5/6/7 Table 7.9. Temperature Sensor Electrical Characteristics Parameter Conditions Linearity Slope Slope Error* Offset Offset Error* Temp = 0 °C Temp = 0 °C Min Typ — — — — — ±0.5 3.49 ±40 930 ±12 Parameter Conditions Input Voltage Range Sample Rate = 500 ksps; VREF = 2.5 V N ot R ec om m en de d fo r Input Current N ew Table 7.10. Voltage Reference Electrical Characteristics VDD = 3.0 V; –40 to +85 °C unless otherwise specified. 36 Rev 1.1 Max Units — — — — — °C mV/°C µV/°C mV mV D Note: Represents one standard deviation from the mean. es ig ns VDD = 3.0 V, –40 to +85 °C unless otherwise specified. Min Typ Max Units 0 — VDD V — 12 — µA C8051T610/1/2/3/4/5/6/7 Table 7.11. Comparator Electrical Characteristics Parameter Conditions Min Typ es ig ns VDD = 3.0 V, –40 to +85 °C unless otherwise noted. Max Units Response Time: Mode 0, Vcm* = 1.5 V CP0+ – CP0– = 100 mV — 240 CP0+ – CP0– = –100 mV — 240 Response Time: Mode 1, Vcm* = 1.5 V CP0+ – CP0– = 100 mV — 400 CP0+ – CP0– = –100 mV — 400 Response Time: Mode 2, Vcm* = 1.5 V CP0+ – CP0– = 100 mV — 650 CP0+ – CP0– = –100 mV — 1100 — ns Response Time: Mode 3, Vcm* = 1.5 V CP0+ – CP0– = 100 mV — 2000 — ns CP0+ – CP0– = –100 mV — 5500 — ns — 1 4 mV/V — 0 1 mV 2 5 8 mV 6 10 14 mV ns ns — ns — ns D — N ew Common-Mode Rejection Ratio — — ns CP0HYP1–0 = 00 Positive Hysteresis 2 CP0HYP1–0 = 01 Positive Hysteresis 3 CP0HYP1–0 = 10 Positive Hysteresis 4 CP0HYP1–0 = 11 12 20 28 mV Negative Hysteresis 1 CP0HYN1–0 = 00 — 0 1 mV Negative Hysteresis 2 CP0HYN1–0 = 01 2 5 8 mV Negative Hysteresis 3 CP0HYN1–0 = 10 6 10 14 mV Negative Hysteresis 4 CP0HYN1–0 = 11 m en de d fo r Positive Hysteresis 1 12 20 28 mV Inverting or Non-Inverting Input Voltage Range –0.25 — VDD + 0.25 V Input Offset Voltage –7.5 — 7.5 mV Power Supply Rejection — 0.5 — mV/V Powerup Time — 10 — µs Mode 0 — 26 50 µA Mode 1 — 10 20 µA Mode 2 — 3 6 µA Mode 3 — 0.5 2 µA Power Specifications ec om Supply Current at DC N ot R Note: Vcm is the common-mode voltage on CP0+ and CP0–. Rev 1.1 37 C8051T610/1/2/3/4/5/6/7 7.3. Typical Performance Curves es ig ns 8.0 7.0 6.0 VDD > 1.8 V VDD = 1.8 V D IDD (mA) 5.0 4.0 N ew 3.0 2.0 0.0 0 5 10 fo r 1.0 15 20 25 SYSCLK (MHz) m en de d Figure 7.1. Normal Mode Digital Supply Current vs. Frequency (MPCE = 1) 2.5 om VDD > 1.8 V 1.5 VDD = 1.8 V ec IDD (mA) 2.0 R 1.0 N ot 0.5 0.0 0 5 10 15 20 SYSCLK (MHz) Figure 7.2. Idle Mode Digital Supply Current vs. Frequency (MPCE = 1) 38 Rev 1.1 25 C8051T610/1/2/3/4/5/6/7 8. 10-Bit ADC (ADC0, C8051T610/1/2/3/6 only) AD0CM2 AD0CM1 AD0CM0 N ew AD0EN AD0TM AD0INT AD0BUSY AD0WINT ADC0CN VDD X1 or X0.5 AIN 10-Bit SAR SYSCLK REF AD0SC2 AD0SC1 AD0SC0 AD0LJST AD08BE AMP0GN0 AD0SC4 AD0SC3 ec om AMP0GN0 AD0BUSY (W) Timer 0 Overflow Timer 2 Overflow Timer 1 Overflow CNVSTR Input Timer 3 Overflow ADC0LTH ADC0LTL ADC0CF ADC0GTH ADC0GTL AD0WINT 32 Window Compare Logic Figure 8.1. ADC0 Functional Block Diagram N ot R 000 001 010 011 100 101 ADC0H ADC ADC0L m en de d fo r Start Conversion From AMUX0 D es ig ns ADC0 on the C8051T610/1/2/3/6 is a 500 ksps, 10-bit successive-approximation-register (SAR) ADC with integrated track-and-hold, a gain stage programmable to 1x or 0.5x, and a programmable window detector. The ADC is fully configurable under software control via Special Function Registers. The ADC may be configured to measure various different signals using the analog multiplexer described in Section “8.5. ADC0 Analog Multiplexer (C8051T610/1/2/3/6 only)” on page 49. The voltage reference for the ADC is selected as described in Section “10. Voltage Reference Options” on page 54. The ADC0 subsystem is enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1. The ADC0 subsystem is in low power shutdown when this bit is logic 0. Rev 1.1 39 C8051T610/1/2/3/4/5/6/7 8.1. Output Code Formatting es ig ns The ADC measures the input voltage with reference to GND. The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code from the ADC at the completion of each conversion. Data can be right-justified or left-justified, depending on the setting of the AD0LJST bit. Conversion codes are represented as 10-bit unsigned integers. Inputs are measured from 0 to VREF x 1023/1024. Example codes are shown below for both right-justified and left-justified data. Unused bits in the ADC0H and ADC0L registers are set to 0. Right-Justified ADC0H:ADC0L (AD0LJST = 0) Left-Justified ADC0H:ADC0L (AD0LJST = 1) VREF x 1023/1024 VREF x 512/1024 VREF x 256/1024 0 0x03FF 0x0200 0x0100 0x0000 0xFFC0 0x8000 0x4000 0x0000 N ew D Input Voltage 8.2. 8-Bit Mode 8.3. Modes of Operation fo r Setting the ADC08BE bit in register ADC0CF to 1 will put the ADC in 8-bit mode. In 8-bit mode, only the 8 MSBs of data are converted, and the ADC0H register holds the results. The AD0LJST bit is ignored for 8bit mode. 8-bit conversions take two fewer SAR clock cycles than 10-bit conversions, so the conversion is completed faster, and a 500 ksps sampling rate can be achieved with a slower SAR clock. m en de d ADC0 has a maximum conversion speed of 500 ksps. The ADC0 conversion clock is a divided version of the system clock, determined by the AD0SC bits in the ADC0CF register. 8.3.1. Starting a Conversion A conversion can be initiated in one of six ways, depending on the programmed states of the ADC0 Start of Conversion Mode bits (AD0CM2–0) in register ADC0CN. Conversions may be initiated by one of the following: 1. Writing a 1 to the AD0BUSY bit of register ADC0CN 2. A Timer 0 overflow (i.e., timed continuous conversions) om 3. A Timer 2 overflow 4. A Timer 1 overflow 5. A rising edge on the CNVSTR input signal ec 6. A Timer 3 overflow N ot R Writing a 1 to AD0BUSY provides software control of ADC0 whereby conversions are performed "ondemand". During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conversion is complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt flag (AD0INT). Note: When polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT) should be used. Converted data is available in the ADC0 data registers, ADC0H:ADC0L, when bit AD0INT is logic 1. Note that when Timer 2 or Timer 3 overflows are used as the conversion source, Low Byte overflows are used if Timer 2/3 is in 8-bit mode; High byte overflows are used if Timer 2/3 is in 16-bit mode. See Section “25. Timers” on page 170 for timer configuration. Important Note About Using CNVSTR: The CNVSTR input pin also functions as a Port I/O pin. When the CNVSTR input is used as the ADC0 conversion source, the associated pin should be skipped by the Digital Crossbar. See Section “21. Port Input/Output” on page 113 for details on Port I/O configuration. 40 Rev 1.1 C8051T610/1/2/3/4/5/6/7 8.3.2. Tracking Modes es ig ns The AD0TM bit in register ADC0CN enables "delayed conversions", and will delay the actual conversion start by three SAR clock cycles, during which time the ADC will continue to track the input. If AD0TM is left at logic 0, a conversion will begin immediately, without the extra tracking time. For internal start-of-conversion sources, the ADC will track anytime it is not performing a conversion. When the CNVSTR signal is used to initiate conversions, ADC0 will track either when AD0TM is logic 1, or when AD0TM is logic 0 and CNVSTR is held low. See Figure 8.2 for track and convert timing details. Delayed conversion mode is useful when AMUX settings are frequently changed, due to the settling time requirements described in Section “8.3.3. Settling Time Requirements” on page 42. D A. ADC Timing for External Trigger Source N ew CNVSTR (AD0CM[2:0]=1xx) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15* 16 17 SAR Clocks AD0TM=1 Convert Track fo r Track *Conversion Ends at rising edge of 15th clock in 8-bit Mode 1 2 3 4 5 6 7 8 9 10 11 12* 13 14 m en de d SAR Clocks AD0TM=0 N/C Track Convert N/C *Conversion Ends at rising edge of 12th clock in 8-bit Mode B. ADC Timing for Internal Trigger Source Write '1' to AD0BUSY, Timer 0, Timer 2, Timer 1 Overflow (AD0CM[2:0]=000, 001, 010, 011) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15* 16 17 om SAR Clocks N ot R ec AD0TM=1 Track Convert Track *Conversion Ends at rising edge of 15th clock in 8-bit Mode 1 2 3 4 5 6 7 8 9 10 11 12* 13 14 SAR Clocks AD0TM=0 Track Convert Track th *Conversion Ends at rising edge of 12 clock in 8-bit Mode Figure 8.2. 10-Bit ADC Track and Conversion Example Timing Rev 1.1 41 C8051T610/1/2/3/4/5/6/7 8.3.3. Settling Time Requirements es ig ns A minimum tracking time is required before each conversion to ensure that an accurate conversion is performed. This tracking time is determined by any series impedance, including the AMUX0 resistance, the the ADC0 sampling capacitance, and the accuracy required for the conversion. Note that in delayed tracking mode, three SAR clocks are used for tracking at the start of every conversion. For many applications, these three SAR clocks will meet the minimum tracking time requirements. D Figure 8.3 shows the equivalent ADC0 input circuit. The required ADC0 settling time for a given settling accuracy (SA) may be approximated by Equation 8.1. See Table 7.8 for ADC0 minimum settling time requirements as well as the mux impedance and sampling capacitor values. n N ew 2 t = ln  ------- × R TOTAL C SAMPLE  SA Equation 8.1. ADC0 Settling Time Requirements m en de d MUX Select fo r Where: SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB) t is the required settling time in seconds RTOTAL is the sum of the AMUX0 resistance and any external source resistance. n is the ADC resolution in bits (10). Input Pin RMUX CSAMPLE om RCInput= RMUX * CSAMPLE Figure 8.3. ADC0 Equivalent Input Circuits N ot R ec Note: See electrical specification tables for RMUX and CSAMPLE parameters. 42 Rev 1.1 C8051T610/1/2/3/4/5/6/7 Bit 7 6 5 4 3 2 es ig ns SFR Definition 8.1. ADC0CF: ADC0 Configuration 1 0 Name AD0SC[4:0] AD0LJST AD08BE AMP0GN0 Type R/W R/W R/W R/W 0 1 1 1 1 SFR Address = 0xBC Bit Name 0 Function AD0SC[4:0] ADC0 SAR Conversion Clock Period Bits. N ew 7:3 1 D 1 Reset SAR Conversion clock is derived from system clock by the following equation, where AD0SC refers to the 5-bit value held in bits AD0SC4–0. SAR Conversion clock requirements are given in the ADC specification table. fo r SYSCLK AD0SC = ----------------------- – 1 CLK SAR Note: If the Memory Power Controller is enabled (MPCE = '1'), AD0SC must be set to at least "00001" for proper ADC operation. 2 AD0LJST ADC0 Left Justify Select. m en de d 0: Data in ADC0H:ADC0L registers are right-justified. 1: Data in ADC0H:ADC0L registers are left-justified. Note: The AD0LJST bit is only valid for 10-bit mode (AD08BE = 0). 1 AD08BE 8-Bit Mode Enable. 0: ADC operates in 10-bit mode (normal). 1: ADC operates in 8-bit mode. Note: When AD08BE is set to 1, the AD0LJST bit is ignored. 0 AMP0GN0 ADC Gain Control Bit. N ot R ec om 0: Gain = 0.5 1: Gain = 1 Rev 1.1 43 C8051T610/1/2/3/4/5/6/7 7 6 5 4 3 Name ADC0H[7:0] Type R/W 0 Reset 0 0 0 0 SFR Address = 0xBE Bit Name 2 0 1 0 0 0 D Bit es ig ns SFR Definition 8.2. ADC0H: ADC0 Data Word MSB Function N ew 7:0 ADC0H[7:0] ADC0 Data Word High-Order Bits. For AD0LJST = 0: Bits 7–2 will read 000000b. Bits 1–0 are the upper 2 bits of the 10bit ADC0 Data Word. For AD0LJST = 1: Bits 7–0 are the most-significant bits of the 10-bit ADC0 Data Word. fo r Note: In 8-bit mode AD0LJST is ignored, and ADC0H holds the 8-bit data word. Bit 7 m en de d SFR Definition 8.3. ADC0L: ADC0 Data Word LSB 6 5 4 2 1 0 0 0 0 ADC0L[7:0] Name R/W Type 0 Reset 0 0 0 SFR Address = 0xBD Bit Name 0 Function om ADC0L[7:0] ADC0 Data Word Low-Order Bits. For AD0LJST = 0: Bits 7–0 are the lower 8 bits of the 10-bit Data Word. For AD0LJST = 1: Bits 7–6 are the lower 2 bits of the 10-bit Data Word. Bits 5–0 will read 000000b. ec 7:0 3 N ot R Note: In 8-bit mode AD0LJST is ignored, and ADC0L will read back 00000000b. 44 Rev 1.1 C8051T610/1/2/3/4/5/6/7 Bit 7 6 5 4 Name AD0EN AD0TM AD0INT Type R/W R/W R/W R/W R/W Reset 0 0 0 0 0 1 ADC0 Enable Bit. AD0CM[2:0] R/W 0 0 0 D Function 0 N ew AD0EN 2 AD0BUSY AD0WINT SFR Address = 0xE8; Bit-Addressable Bit Name 7 3 es ig ns SFR Definition 8.4. ADC0CN: ADC0 Control 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ADC0 Enabled. ADC0 is active and ready for data conversions. 6 AD0TM ADC0 Track Mode Bit. 5 AD0INT m en de d fo r 0: Normal Track Mode: When ADC0 is enabled, tracking is continuous unless a conversion is in progress. Conversion begins immediately on start-of-conversion event, as defined by AD0CM[2:0]. 1: Delayed Track Mode: When ADC0 is enabled, input is tracked when a conversion is not in progress. A start-of-conversion signal initiates three SAR clocks of additional tracking, and then begins the conversion. ADC0 Conversion Complete Interrupt Flag. 0: ADC0 has not completed a data conversion since AD0INT was last cleared. 1: ADC0 has completed a data conversion. 3 AD0BUSY AD0WINT ADC0 Busy Bit. Read: Write: 0: ADC0 conversion is not in progress. 1: ADC0 conversion is in progress. 0: No Effect. 1: Initiates ADC0 Conversion if AD0CM[2:0] = 000b ADC0 Window Compare Interrupt Flag. om 4 ec 0: ADC0 Window Comparison Data match has not occurred since this flag was last cleared. 1: ADC0 Window Comparison Data match has occurred. N ot R 2:0 AD0CM[2:0] ADC0 Start of Conversion Mode Select. 000: ADC0 start-of-conversion source is write of 1 to AD0BUSY. 001: ADC0 start-of-conversion source is overflow of Timer 0. 010: ADC0 start-of-conversion source is overflow of Timer 2. 011: ADC0 start-of-conversion source is overflow of Timer 1. 100: ADC0 start-of-conversion source is rising edge of external CNVSTR. 101: ADC0 start-of-conversion source is overflow of Timer 3. 11x: Reserved. Rev 1.1 45 C8051T610/1/2/3/4/5/6/7 8.4. Programmable Window Detector D es ig ns The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-programmed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system response times. The window detector interrupt flag (AD0WINT in register ADC0CN) can also be used in polled mode. The ADC0 Greater-Than (ADC0GTH, ADC0GTL) and Less-Than (ADC0LTH, ADC0LTL) registers hold the comparison values. The window detector flag can be programmed to indicate when measured data is inside or outside of the user-programmed limits, depending on the contents of the ADC0 Less-Than and ADC0 Greater-Than registers. Bit 7 6 5 4 N ew SFR Definition 8.5. ADC0GTH: ADC0 Greater-Than Data High Byte 3 Name ADC0GTH[7:0] Type R/W 1 1 1 1 1 0 1 1 1 2 1 0 1 1 1 fo r 1 Reset 2 SFR Address = 0xC4 Bit Name Function m en de d 7:0 ADC0GTH[7:0] ADC0 Greater-Than Data Word High-Order Bits. SFR Definition 8.6. ADC0GTL: ADC0 Greater-Than Data Low Byte Bit 7 6 5 4 ADC0GTL[7:0] Name R/W Reset om Type 1 1 1 1 SFR Address = 0xC3 Bit Name ec ADC0GTL[7:0] ADC0 Greater-Than Data Word Low-Order Bits. N ot 46 1 Function R 7:0 3 Rev 1.1 C8051T610/1/2/3/4/5/6/7 7 6 5 4 3 Name ADC0LTH[7:0] Type R/W 0 Reset 0 0 0 0 SFR Address = 0xC6 Bit Name 0 1 0 0 0 Function ADC0LTH[7:0] ADC0 Less-Than Data Word High-Order Bits. N ew 7:0 2 D Bit es ig ns SFR Definition 8.7. ADC0LTH: ADC0 Less-Than Data High Byte SFR Definition 8.8. ADC0LTL: ADC0 Less-Than Data Low Byte 7 6 5 4 3 fo r Bit Name ADC0LTL[7:0] Type R/W 0 0 0 m en de d 0 Reset SFR Address = 0xC5 Bit Name 1 0 0 0 0 Function ADC0LTL[7:0] ADC0 Less-Than Data Word Low-Order Bits. N ot R ec om 7:0 0 2 Rev 1.1 47 C8051T610/1/2/3/4/5/6/7 8.4.1. Window Detector Example ADC0H:ADC0L D es ig ns Figure 8.4 shows two example window comparisons for right-justified data, with ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). The input voltage can range from 0 to VREF x (1023/1024) with respect to GND, and is represented by a 10-bit unsigned integer value. In the left example, an AD0WINT interrupt will be generated if the ADC0 conversion word (ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL (if 0x0040 < ADC0H:ADC0L < 0x0080). In the right example, and AD0WINT interrupt will be generated if the ADC0 conversion word is outside of the range defined by the ADC0GT and ADC0LT registers (if ADC0H:ADC0L < 0x0040 or ADC0H:ADC0L > 0x0080). Figure 8.5 shows an example using left-justified data with the same comparison values. ADC0H:ADC0L Input Voltage (AIN - GND) VREF x (1023/ 1024) N ew Input Voltage (AIN - GND) VREF x (1023/ 1024) 0x03FF AD0WINT not affected 0x0081 0x0080 0x007F VREF x (128/1024) 0x0080 0x007F AD0WINT=1 VREF x (64/1024) 0x0041 0x0040 AD0WINT=1 0x0081 ADC0LTH:ADC0LTL fo r VREF x (128/1024) 0x03FF ADC0GTH:ADC0GTL VREF x (64/1024) m en de d 0x003F 0x0041 0x0040 ADC0GTH:ADC0GTL AD0WINT not affected ADC0LTH:ADC0LTL 0x003F AD0WINT=1 AD0WINT not affected 0x0000 0 0 0x0000 Figure 8.4. ADC Window Compare Example: Right-Justified Data ADC0H:ADC0L Input Voltage (AIN - GND) ADC0H:ADC0L Input Voltage (AIN - GND) 0xFFC0 om VREF x (1023/ 1024) VREF x (1023/ 1024) AD0WINT not affected AD0WINT=1 ec 0x2040 VREF x (128/1024) 0x2000 0x2040 ADC0LTH:ADC0LTL VREF x (128/1024) R 0x1FC0 N ot 0x1000 0x2000 0x1FC0 AD0WINT=1 0x1040 VREF x (64/1024) 0xFFC0 0x1040 ADC0GTH:ADC0GTL VREF x (64/1024) 0x0FC0 0x1000 ADC0GTH:ADC0GTL AD0WINT not affected ADC0LTH:ADC0LTL 0x0FC0 AD0WINT=1 AD0WINT not affected 0 0x0000 0 0x0000 Figure 8.5. ADC Window Compare Example: Left-Justified Data 48 Rev 1.1 C8051T610/1/2/3/4/5/6/7 8.5. ADC0 Analog Multiplexer (C8051T610/1/2/3/6 only) es ig ns ADC0 on the C8051T610/1/2/3/6 uses an analog input multiplexer to select the positive input to the ADC. Any of the following may be selected as the positive input: Port 1, 2 and 3 I/O pins, the on-chip temperature sensor, or the positive power supply (VDD). The ADC0 input channel is selected in the AMX0P register described in SFR Definition 8.9. fo r P1.0 AMUX ADC0 m en de d Note: Not all pins exist on all packages. See the AMX0P selection table for details on which pins are available for selection. D N ew AMX0P4 AMX0P3 AMX0P2 AMX0P1 AMX0P0 AMX0P P3.4 Temp Sensor VDD Figure 8.6. ADC0 Multiplexer Block Diagram N ot R ec om Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be configured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for analog input, set to 0 the corresponding bit in register PnMDIN. To force the Crossbar to skip a Port pin, set to 1 the corresponding bit in register PnSKIP. See Section “21. Port Input/Output” on page 113 for more Port I/O configuration details. Rev 1.1 49 C8051T610/1/2/3/4/5/6/7 Bit 7 6 5 4 3 2 Type R R R Reset 0 0 0 R/W 1 SFR Address = 0xBB Bit Name 1 1 Function om ec R N ot 50 Rev 1.1 0 1 1 Available on Packages LQFP-32, QFN-28, QFN-24 LQFP-32, QFN-28, QFN-24 LQFP-32, QFN-28, QFN-24 LQFP-32, QFN-28, QFN-24 LQFP-32, QFN-28, QFN-24 LQFP-32, QFN-28, QFN-24 LQFP-32, QFN-28 LQFP-32, QFN-28 LQFP-32, QFN-28, QFN-24 LQFP-32, QFN-28, QFN-24 LQFP-32, QFN-28, QFN-24 LQFP-32, QFN-28, QFN-24 LQFP-32, QFN-28, QFN-24 LQFP-32, QFN-28, QFN-24 LQFP-32, QFN-28 LQFP-32, QFN-28 LQFP-32, QFN-28, QFN-24 LQFP-32 LQFP-32 LQFP-32 LQFP-32 N/A LQFP-32, QFN-28, QFN-24 LQFP-32, QFN-28, QFN-24 fo r Channel P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 No Input Selected Temp Sensor VDD m en de d Setting 00000: 00001: 00010: 00011: 00100: 00101: 00110: 00111: 01000: 01001: 01010: 01011: 01100: 01101: 01110: 01111: 10000: 10001: 10010: 10011: 10100: 10101-11101: 11110: 11111: N ew 7:5 Unused Unused. Read = 000b; Write = Don’t Care. 4:0 AMX0P[4:0] AMUX0 Positive Input Selection. 1 D AMX0P[4:0] Name es ig ns SFR Definition 8.9. AMX0P: AMUX0 Positive Channel Select C8051T610/1/2/3/4/5/6/7 9. Temperature Sensor (C8051T610/1/2/3/6 only) N ew VTEMP = (Slope x TempC) + Offset D es ig ns An on-chip temperature sensor is included on the C8051T610/1/2/3/6 which can be directly accessed via the ADC multiplexer. To use the ADC to measure the temperature sensor, the ADC mux channel should be configured to connect to the temperature sensor. The temperature sensor transfer function is shown in Figure 9.1. The output voltage (VTEMP) is the positive ADC input when the ADC multiplexer is set correctly. The TEMPE bit in register REF0CN enables/disables the temperature sensor, as described in SFR Definition 10.1. While disabled, the temperature sensor defaults to a high impedance state and any ADC measurements performed on the sensor will result in meaningless data. Refer to Table 7.9 for the slope and offset parameters of the temperature sensor. TempC = (VTEMP - Offset) / Slope fo r Voltage Slope (V / deg C) om m en de d Offset (V at 0 Celsius) Temperature ec Figure 9.1. Temperature Sensor Transfer Function 9.1. Calibration N ot R The uncalibrated temperature sensor output is extremely linear and suitable for relative temperature measurements (see Table 7.9 on page 36 for specifications). For absolute temperature measurements, offset and/or gain calibration is recommended. A single-point offset measurement of the temperature sensor is performed on each device during production test. The registers TOFFH and TOFFL, shown in SFR Definition 9.1 and SFR Definition 9.2 represent the output of the ADC when reading the temperature sensor at 0 degrees Celsius, and using the internal regulator as a voltage reference. Figure 9.2 shows the typical temperature sensor error assuming a 1-point calibration at 0 °C. Parameters that affect ADC measurement, in particular the voltage reference value, will also affect temperature measurement. Rev 1.1 51 C8051T610/1/2/3/4/5/6/7 5.00 4.00 4.00 es ig ns 5.00 3.00 3.00 2.00 1.00 0.00 -40.00 -20.00 0.00 20.00 40.00 D 1.00 60.00 80.00 N ew Error (degrees C) 2.00 -1.00 -2.00 fo r -3.00 -4.00 m en de d -5.00 Temperature (degrees C) N ot R ec om Figure 9.2. Temperature Sensor Error with 1-Point Calibration at 0 Celsius 52 Rev 1.1 0.00 -1.00 -2.00 -3.00 -4.00 -5.00 C8051T610/1/2/3/4/5/6/7 7 6 5 4 3 2 Varies Varies Name TOFF[9:2] Type R/W Varies Reset Varies Varies Varies SFR Address = 0x86 Bit Name TOFF[9:2] 0 Varies Varies Function Temperature Sensor Offset High Order Bits. N ew 7:0 1 D Bit es ig ns SFR Definition 9.1. TOFFH: Temperature Offset Measurement High Byte fo r The temperature sensor offset registers represent the output of the ADC when measuring the temperature sensor at 0 °C, with the voltage reference set to the internal regulator. The temperature sensor offset information is left-justified. One LSB of this measurement is equivalent to one LSB of the ADC output under the measurement conditions. Bit 7 m en de d SFR Definition 9.2. TOFFL: Temperature Offset Measurement Low Byte 6 Name TOFF[1:0] Type R/W Varies Reset Varies 5 4 3 2 1 0 R R R R R R 0 0 0 0 0 0 SFR Address = 0x85 Bit Name TOFF[1:0] Temperature Sensor Offset Low Order Bits. om 7:6 Function ec The temperature sensor offset registers represent the output of the ADC when measuring the temperature sensor at 0 °C, with the voltage reference set to the internal regulator. The temperature sensor offset information is left-justified. One LSB of this measurement is equivalent to one LSB of the ADC output under the measurement conditions. Unused Unused. Read = 000000b; Write = Don’t Care. N ot R 5:0 Rev 1.1 53 C8051T610/1/2/3/4/5/6/7 10. Voltage Reference Options es ig ns The Voltage reference multiplexer for the ADC is configurable to use an externally connected voltage reference, the unregulated power supply voltage (VDD), or the regulated 1.8 V internal supply (see Figure 10.1). The REFSL bit in the Reference Control register (REF0CN, SFR Definition 10.1) selects the reference source for the ADC. For an external source, REFSL should be set to 0 to select the VREF pin. To use VDD as the reference source, REFSL should be set to 1. To override this selection and use the internal regulator as the reference source, the REGOVR bit can be set to 1. The electrical specifications for the voltage reference circuit are given in Section “7. Electrical Characteristics” on page 31. fo r REGOVR REFSL TEMPE REF0CN N ew D Important Note about the VREF Pin: When using an external voltage reference, the VREF pin should be configured as an analog pin and skipped by the Digital Crossbar. Refer to Section “21. Port Input/Output” on page 113 for the location of the VREF pin, as well as details of how to configure the pin in analog mode and to be skipped by the crossbar. R1 External Voltage Reference Circuit m en de d VDD VREF GND 0.1μF To Analog Mux 0 VREF (to ADC) 1 Internal Regulator om 4.7μF Temp Sensor 0 VDD + EN 1 REGOVR Recommended Bypass Capacitors N ot R ec Figure 10.1. Voltage Reference Functional Block Diagram Rev 1.1 54 C8051T610/1/2/3/4/5/6/7 7 6 5 Name 4 3 2 REGOVR REFSL TEMPE Type R R R R/W R/W R/W Reset 0 0 0 0 0 0 SFR Address = 0xD1 Bit Name 4 Unused Unused. Read = 000b; Write = Don’t Care. REGOVR Regulator Reference Override. N ew 7:5 Function 1 0 R R 0 0 D Bit es ig ns SFR Definition 10.1. REF0CN: Reference Control 3 REFSL Voltage Reference Select. fo r This bit “overrides” the REFSL bit, and allows the internal regulator to be used as a reference source. 0: The voltage reference source is selected by the REFSL bit. 1: The internal regulator is used as the voltage reference. 2 TEMPE m en de d This bit selects the ADCs voltage reference. 0: VREF pin used as voltage reference. 1: VDD used as voltage reference. Temperature Sensor Enable Bit. 0: Internal Temperature Sensor off. 1: Internal Temperature Sensor on. Unused Unused. Read = 00b; Write = Don’t Care. N ot R ec om 1:0 55 Rev 1.1 C8051T610/1/2/3/4/5/6/7 11. Voltage Regulator (REG0) es ig ns C8051T610/1/2/3/4/5/6/7 devices include an internal voltage regulator (REG0) to regulate the internal core supply to 1.8 V from a VDD supply of 1.8 to 3.6 V. Two power-saving modes are built into the regulator to help reduce current consumption in low-power applications. These modes are accessed through the REG0CN register (SFR Definition 11.1). Electrical characteristics for the on-chip regulator are specified in Table 7.5 on page 34 D If an external regulator is used to power the device, the internal regulator may be put into bypass mode using the BYPASS bit. The internal regulator should never be placed in bypass mode unless an external 1.8 V regulator is used to supply VDD. Doing so could cause permanent damage to the device. N ot R ec om m en de d fo r N ew Under default conditions, when the device enters STOP mode the internal regulator will remain on. This allows any enabled reset source to generate a reset for the device and bring the device out of STOP mode. For additional power savings, the STOPCF bit can be used to shut down the regulator and the internal power network of the device when the part enters STOP mode. When STOPCF is set to 1, the RST pin or a full power cycle of the device are the only methods of generating a reset. Rev 1.1 56 C8051T610/1/2/3/4/5/6/7 Bit 7 6 5 4 Name STOPCF BYPASS Type R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 2 1 0 MPCE Function R/W 0 0 N ew STOPCF Stop Mode Configuration. R/W D SFR Address = 0xC7 Bit Name 7 3 es ig ns SFR Definition 11.1. REG0CN: Voltage Regulator Control 6 BYPASS Bypass Internal Regulator. fo r This bit configures the regulator’s behavior when the device enters STOP mode. 0: Regulator is still active in STOP mode. Any enabled reset source will reset the device. 1: Regulator is shut down in STOP mode. Only the RST pin or power cycle can reset the device. 5:1 0 m en de d This bit places the regulator in bypass mode, turning off the regulator, and allowing the core to run directly from the VDD supply pin. 0: Normal Mode—Regulator is on. 1: Bypass Mode—Regulator is off, and the microcontroller core operates directly from the VDD supply voltage. IMPORTANT: Bypass mode is for use with an external regulator as the supply voltage only. Never place the regulator in bypass mode when the VDD supply voltage is greater than the specifications given in Table 7.1 on page 31. Doing so may cause permanent damage to the device. Reserved Reserved. Must Write 00000b. MPCE Memory Power Controller Enable. Note: If an external clock source is used with the Memory Power Controller enabled, and the clock frequency changes from slow ( 2.0 MHz), the EPROM power will turn on, and up to 20 clocks may be "skipped" to ensure that the EPROM power is stable before reading memory. N ot R ec om This bit can help the system save power at slower system clock frequencies (about 2.0 MHz or less) by automatically shutting down the EPROM memory between clocks when information is not being fetched from the EPROM memory. 0: Normal Mode—Memory power controller disabled (EPROM memory is always on). 1: Low Power Mode—Memory power controller enabled (EPROM memory turns on/off as needed). 57 Rev 1.1 C8051T610/1/2/3/4/5/6/7 12. Comparator0 and Comparator1 es ig ns C8051T610/1/2/3/4/5/6/7 devices include two on-chip programmable voltage comparators: Comparator0 is shown in Figure 12.1, Comparator1 is shown in Figure 12.2. The two comparators operate identically with the following exceptions: (1) Their input selections differ as described in Section “12.1. Comparator Multiplexers” on page 65; (2) Comparator0 can be used as a reset source. N ew D The Comparators offer programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0 or CP1), or an asynchronous “raw” output (CP0A or CP1A). The asynchronous signals are available even when the system clock is not active. This allows the Comparators to operate and generate an output with the device in STOP mode. When assigned to a Port pin, the Comparator outputs may be configured as open drain or push-pull (see Section “21.4. Port I/O Initialization” on page 121). Comparator0 may also be used as a reset source (see Section “19.5. Comparator0 Reset” on page 104). The Comparator inputs are selected by the comparator input multiplexers, as detailed in Section “12.1. Comparator Multiplexers” on page 65. CPT0CN m en de d fo r CP0EN CP0OUT CP0RIF CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 VDD CP0 + + Comparator Input Mux CP0 - D - SET CLR Q Q CP0 D SET CLR Q Q Crossbar om (SYNCHRONIZER) CPT0MD ec R CP0FIE CP0RIE CP0MD1 CP0MD0 N ot CP0A GND Reset Decision Tree CP0RIF CP0FIF 0 CP0EN EA 1 0 0 0 1 1 CP0 Interrupt 1 Figure 12.1. Comparator0 Functional Block Diagram Rev 1.1 58 C8051T610/1/2/3/4/5/6/7 CPT1CN es ig ns CP1EN CP1FIF CP1OUT CP1RIF CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0 D VDD CP1 + + CP1 - CP1 D - SET CLR Q D Q SET Q N ew Comparator Input Mux CLR Q Crossbar (SYNCHRONIZER) GND CP1RIF 0 1 m en de d CP1FIE CP1RIE CP1MD1 CP1MD0 fo r CPT1MD CP1FIF 0 CP1EN EA 0 0 1 1 CP1A CP1 Interrupt 1 Figure 12.2. Comparator1 Functional Block Diagram om The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin. When routed to a Port pin, the Comparator output is available asynchronous or synchronous to the system clock; the asynchronous output is available even in STOP mode (with no system clock active). When disabled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state, and the power supply to the comparator is turned off. See Section “21.3. Priority Crossbar Decoder” on page 117 for details on configuring Comparator outputs via the digital Crossbar. Comparator inputs can be externally driven from –0.25 V to (VDD) + 0.25 V without damage or upset. The complete Comparator electrical specifications are given in Section “7. Electrical Characteristics” on page 31. N ot R ec The Comparator response time may be configured in software via the CPTnMD registers (see SFR Definition 12.2 and SFR Definition 12.4). Selecting a longer response time reduces the Comparator supply current. 59 Rev 1.1 C8051T610/1/2/3/4/5/6/7 VIN- CPn+ CPn- + CPn _ OUT es ig ns VIN+ CIRCUIT CONFIGURATION Positive Hysteresis Voltage (Programmed with CPnHYP Bits) D VIN- INPUTS Negative Hysteresis Voltage (Programmed by CPnHYN Bits) N ew VIN+ VOH VOL fo r OUTPUT Negative Hysteresis Disabled Maximum Positive Hysteresis m en de d Positive Hysteresis Disabled Maximum Negative Hysteresis Figure 12.3. Comparator Hysteresis Plot The Comparator hysteresis is software-programmable via its Comparator Control register CPTnCN (for n = 0 or 1). The user can program both the amount of hysteresis voltage (referred to the input voltage) and the positive and negative-going symmetry of this hysteresis around the threshold voltage. om The Comparator hysteresis is programmed using Bits3–0 in the Comparator Control Register CPTnCN (shown in SFR Definition 12.1). The amount of negative hysteresis voltage is determined by the settings of the CPnHYN bits. Settings of 20, 10 or 5 mV of nominal negative hysteresis can be programmed, or negative hysteresis can be disabled. In a similar way, the amount of positive hysteresis is determined by the setting the CPnHYP bits. R ec Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Interrupt enable and priority control, see Section “16.1. MCU Interrupt Sources and Vectors” on page 86). The CPnFIF flag is set to logic 1 upon a Comparator falling-edge occurrence, and the CPnRIF flag is set to logic 1 upon the Comparator rising-edge occurrence. Once set, these bits remain set until cleared by software. The Comparator rising-edge interrupt mask is enabled by setting CPnRIE to a logic 1. The Comparator falling-edge interrupt mask is enabled by setting CPnFIE to a logic 1. N ot The output state of the Comparator can be obtained at any time by reading the CPnOUT bit. The Comparator is enabled by setting the CPnEN bit to logic 1, and is disabled by clearing this bit to logic 0. Note that false rising edges and falling edges can be detected when the comparator is first powered on or if changes are made to the hysteresis or response time control bits. Therefore, it is recommended that the rising-edge and falling-edge flags be explicitly cleared to logic 0 a short time after the comparator is enabled or its mode bits have been changed. Rev 1.1 60 C8051T610/1/2/3/4/5/6/7 Bit 7 6 5 4 Name CP0EN CP0OUT CP0RIF CP0FIF CP0HYP[1:0] Type R/W R R/W R/W R/W Reset 0 0 0 0 CP0EN 0 Function Comparator0 Enable Bit. 0: Comparator0 Disabled. 1: Comparator0 Enabled. 6 CP0OUT Comparator0 Output State Flag. 5 0 CP0HYN[1:0] R/W 0 0 0 fo r 0: Voltage on CP0+ < CP0–. 1: Voltage on CP0+ > CP0–. 1 N ew 7 2 D SFR Address = 0x9B Bit Name 3 es ig ns SFR Definition 12.1. CPT0CN: Comparator0 Control CP0RIF Comparator0 Rising-Edge Flag. Must be cleared by software. 4 CP0FIF m en de d 0: No Comparator0 Rising Edge has occurred since this flag was last cleared. 1: Comparator0 Rising Edge has occurred. Comparator0 Falling-Edge Flag. Must be cleared by software. 0: No Comparator0 Falling-Edge has occurred since this flag was last cleared. 1: Comparator0 Falling-Edge has occurred. 3:2 CP0HYP[1:0] Comparator0 Positive Hysteresis Control Bits. 00: Positive Hysteresis Disabled. 01: Positive Hysteresis = 5 mV. 10: Positive Hysteresis = 10 mV. 11: Positive Hysteresis = 20 mV. 00: Negative Hysteresis Disabled. 01: Negative Hysteresis = 5 mV. 10: Negative Hysteresis = 10 mV. 11: Negative Hysteresis = 20 mV. N ot R ec om 1:0 CP0HYN[1:0] Comparator0 Negative Hysteresis Control Bits. 61 Rev 1.1 C8051T610/1/2/3/4/5/6/7 7 6 Name 5 4 CP0RIE CP0FIE 3 2 R R R/W R/W R R Reset 0 0 0 0 0 0 Function Unused Unused. Read = 00b, Write = Don’t Care. 5 CP0RIE Comparator0 Rising-Edge Interrupt Enable. 0: Comparator0 Rising-edge interrupt disabled. 1: Comparator0 Rising-edge interrupt enabled. 4 CP0FIE Comparator0 Falling-Edge Interrupt Enable. 0: Comparator0 Falling-edge interrupt disabled. 1: Comparator0 Falling-edge interrupt enabled. 3:2 Unused Unused. Read = 00b, Write = don’t care. R/W 1 0 fo r N ew 7:6 CP0MD[1:0] Comparator0 Mode Select. These bits affect the response time and power consumption for Comparator0. 00: Mode 0 (Fastest Response Time, Highest Power Consumption) 01: Mode 1 10: Mode 2 11: Mode 3 (Slowest Response Time, Lowest Power Consumption) N ot R ec om m en de d 1:0 0 CP0MD[1:0] Type SFR Address = 0x9D Bit Name 1 D Bit es ig ns SFR Definition 12.2. CPT0MD: Comparator0 Mode Selection Rev 1.1 62 C8051T610/1/2/3/4/5/6/7 Bit 7 6 5 4 Name CP1EN CP1OUT CP1RIF CP1FIF CP1HYP[1:0] Type R/W R R/W R/W R/W Reset 0 0 0 0 CP1EN 0 Function Comparator1 Enable Bit. 0: Comparator1 Disabled. 1: Comparator1 Enabled. 6 CP1OUT Comparator1 Output State Flag. 5 0 CP1HYN[1:0] R/W 0 0 0 fo r 0: Voltage on CP1+ < CP0–. 1: Voltage on CP1+ > CP0–. 1 N ew 7 2 D SFR Address = 0x9A Bit Name 3 es ig ns SFR Definition 12.3. CPT1CN: Comparator1 Control CP1RIF Comparator1 Rising-Edge Flag. Must be cleared by software. 4 CP1FIF m en de d 0: No Comparator1 Rising Edge has occurred since this flag was last cleared. 1: Comparator1 Rising Edge has occurred. Comparator1 Falling-Edge Flag. Must be cleared by software. 0: No Comparator1 Falling-Edge has occurred since this flag was last cleared. 1: Comparator1 Falling-Edge has occurred. 3:2 CP1HYP[1:0] Comparator1 Positive Hysteresis Control Bits. 00: Positive Hysteresis Disabled. 01: Positive Hysteresis = 5 mV. 10: Positive Hysteresis = 10 mV. 11: Positive Hysteresis = 20 mV. 00: Negative Hysteresis Disabled. 01: Negative Hysteresis = 5 mV. 10: Negative Hysteresis = 10 mV. 11: Negative Hysteresis = 20 mV. N ot R ec om 1:0 CP1HYN[1:0] Comparator1 Negative Hysteresis Control Bits. 63 Rev 1.1 C8051T610/1/2/3/4/5/6/7 7 6 Name 5 4 CP1RIE CP1FIE 3 2 R R R/W R/W R R Reset 0 0 0 0 0 0 Function Unused Unused. Read = 00b, Write = Don’t Care. 5 CP1RIE Comparator1 Rising-Edge Interrupt Enable. 0: Comparator1 Rising-edge interrupt disabled. 1: Comparator1 Rising-edge interrupt enabled. 4 CP1FIE Comparator1 Falling-Edge Interrupt Enable. 0: Comparator1 Falling-edge interrupt disabled. 1: Comparator1 Falling-edge interrupt enabled. 3:2 Unused Unused. Read = 00b, Write = don’t care. R/W 1 0 fo r N ew 7:6 CP1MD[1:0] Comparator1 Mode Select. These bits affect the response time and power consumption for Comparator1. 00: Mode 0 (Fastest Response Time, Highest Power Consumption) 01: Mode 1 10: Mode 2 11: Mode 3 (Slowest Response Time, Lowest Power Consumption) N ot R ec om m en de d 1:0 0 CP1MD[1:0] Type SFR Address = 0x9C Bit Name 1 D Bit es ig ns SFR Definition 12.4. CPT1MD: Comparator1 Mode Selection Rev 1.1 64 C8051T610/1/2/3/4/5/6/7 12.1. Comparator Multiplexers CP1 - - + - P1.3 P1.7 P2.3 P2.7 m en de d CMX0P1 CMX0P0 CMX0N0 CMX0N1 GND GND CPT1MX om CPT0MX VDD CMX1P0 P1.1 P1.5 P2.1 P2.5 CP1 + CMX1P1 CP0 - + CMX1N1 CMX1N0 CP0 + P1.2 P1.6 P2.2 P2.6 N ew VDD fo r P1.0 P1.4 P2.0 P2.4 D es ig ns C8051T610/1/2/3/4/5/6/7 devices include analog input multiplexers to connect Port I/O pins to the comparator inputs. The Comparator0 inputs are selected in the CPT0MX register (SFR Definition 12.5). The CMX0P1–CMX0P0 bits select the Comparator0 positive input; the CMX0N1–CMX0N0 bits select the Comparator0 negative input. Likewise, the Comparator1 inputs are selected in the CPT1MX register (SFR Definition 12.6). Important Note About Comparator Inputs: The Port pins selected as comparator inputs should be configured as analog inputs in their associated Port configuration register, and configured to be skipped by the Crossbar (for details on Port configuration, see Section “21.5. Special Function Registers for Accessing and Configuring Port I/O” on page 124). N ot R ec Figure 12.4. Comparator Input Multiplexer Block Diagram Rev 1.1 65 C8051T610/1/2/3/4/5/6/7 7 6 5 4 Type R R Reset 0 0 0 0 R R 0 0 Function 00: P1.1 01: P1.5 10: P2.1 11: P2.5 Unused, Read = 00b; Write = Don’t Care N ot R ec om m en de d fo r Unused CMX0P[1:0] Comparator0 Positive Input MUX Selection. P1.0 P1.4 P2.0 P2.4 Rev 1.1 0 R/W 0 N ew Unused Unused, Read = 00b; Write = Don’t Care CMX0N[1:0] Comparator0 Negative Input MUX Selection. 00: 01: 10: 11: 66 1 CMX0P[1:0] R/W SFR Address = 0x9F Bit Name 3:2 1:0 2 CMX0N[1:0] Name 7:6 5:4 3 D Bit es ig ns SFR Definition 12.5. CPT0MX: Comparator0 MUX Selection 0 C8051T610/1/2/3/4/5/6/7 7 6 5 4 Type R R Reset 0 0 0 0 R R 0 0 Function 0 0 N ew Unused. Read = 00b, Write = Don’t Care R/W CMX0N[1:0] Comparator1 Negative Input MUX Selection. Unused 00: P1.3 01: P1.7 10: P2.3 11: P2.7 Unused. Read = 00b, Write = Don’t Care CMX0P[1:0] Comparator1 Positive Input MUX Selection. m en de d 1:0 0 fo r 3:2 Unused 1 CMX1P[1:0] R/W SFR Address = 0x9E Bit Name 5:4 2 CMX1N[1:0] Name 7:6 3 D Bit es ig ns SFR Definition 12.6. CPT1MX: Comparator1 MUX Selection P1.2 01: P1.6 10: P2.1 11: P2.6 N ot R ec om 00: Rev 1.1 67 C8051T610/1/2/3/4/5/6/7 13. CIP-51 Microcontroller es ig ns The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has a superset of all the peripherals included with a standard 8051. The CIP-51 also includes on-chip debug hardware (see description in Section 27), and interfaces directly with the analog and digital subsystems providing a complete data acquisition or control-system solution in a single integrated circuit. l Reset l 25 Compatible with MCS-51 Instruction Set MIPS Peak Throughput with 25 MHz Clock l 0 to 25 MHz Clock Frequency l Extended Interrupt Handler l Power Input Management Modes l On-chip Debug Logic l Program and Data Memory Security N ew l Fully D The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals and functions to extend its capability (see Figure 13.1 for a block diagram). The CIP-51 includes the following features: m en de d fo r Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more than eight system clock cycles. D8 D8 ACCUMULATOR STACK POINTER TMP2 PSW D8 D8 ALU SRAM om DATA BUS SFR_ADDRESS BUFFER D8 D8 DATA POINTER D8 SFR BUS INTERFACE SFR_CONTROL SFR_WRITE_DATA SFR_READ_DATA ec PC INCREMENTER DATA BUS R N ot SRAM ADDRESS REGISTER D8 TMP1 D8 DATA BUS B REGISTER D8 D8 D8 DATA BUS PROGRAM COUNTER (PC) PRGM. ADDRESS REG. MEM_ADDRESS D8 MEM_CONTROL A16 MEMORY INTERFACE MEM_WRITE_DATA MEM_READ_DATA PIPELINE RESET D8 CONTROL LOGIC SYSTEM_IRQs CLOCK D8 STOP IDLE POWER CONTROL REGISTER INTERRUPT INTERFACE EMULATION_IRQ D8 Figure 13.1. CIP-51 Block Diagram Rev 1.1 68 C8051T610/1/2/3/4/5/6/7 es ig ns With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execution time. Clocks to Execute 1 2 2/3 3 3/4 4 4/5 5 8 Number of Instructions 26 50 5 14 7 3 1 2 1 13.1. Instruction Set N ew D The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruction set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51 instructions are the binary and functional equivalent of their MCS-51™ counterparts, including opcodes, addressing modes and effect on PSW flags. However, instruction timing is different than that of the standard 8051. 13.1.1. Instruction and CPU Timing fo r In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based solely on clock cycle timing. All instruction timings are specified in terms of clock cycles. N ot R ec om m en de d Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock cycles as there are program bytes in the instruction. Conditional branch instructions take one less clock cycle to complete when the branch is not taken as opposed to when the branch is taken. Table 13.1 is the CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock cycles for each instruction. 69 Rev 1.1 C8051T610/1/2/3/4/5/6/7 Table 13.1. CIP-51 Instruction Set Summary Bytes Arithmetic Operations fo r N ew Add register to A Add direct byte to A Add indirect RAM to A Add immediate to A Add register to A with carry Add direct byte to A with carry Add indirect RAM to A with carry Add immediate to A with carry Subtract register from A with borrow Subtract direct byte from A with borrow Subtract indirect RAM from A with borrow Subtract immediate from A with borrow Increment A Increment register Increment direct byte Increment indirect RAM Decrement A Decrement register Decrement direct byte Decrement indirect RAM Increment Data Pointer Multiply A and B Divide A by B Decimal adjust A m en de d ADD A, Rn ADD A, direct ADD A, @Ri ADD A, #data ADDC A, Rn ADDC A, direct ADDC A, @Ri ADDC A, #data SUBB A, Rn SUBB A, direct SUBB A, @Ri SUBB A, #data INC A INC Rn INC direct INC @Ri DEC A DEC Rn DEC direct DEC @Ri INC DPTR MUL AB DIV AB DA A Clock Cycles es ig ns Description 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 2 1 1 1 1 1 1 2 2 2 1 2 2 2 1 2 2 2 1 1 2 2 1 1 2 2 1 4 8 1 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 1 2 2 2 2 3 1 2 2 2 2 3 1 2 2 2 2 D Mnemonic Logical Operations N ot R ec om ANL A, Rn ANL A, direct ANL A, @Ri ANL A, #data ANL direct, A ANL direct, #data ORL A, Rn ORL A, direct ORL A, @Ri ORL A, #data ORL direct, A ORL direct, #data XRL A, Rn XRL A, direct XRL A, @Ri XRL A, #data XRL direct, A AND Register to A AND direct byte to A AND indirect RAM to A AND immediate to A AND A to direct byte AND immediate to direct byte OR Register to A OR direct byte to A OR indirect RAM to A OR immediate to A OR A to direct byte OR immediate to direct byte Exclusive-OR Register to A Exclusive-OR direct byte to A Exclusive-OR indirect RAM to A Exclusive-OR immediate to A Exclusive-OR A to direct byte Rev 1.1 70 C8051T610/1/2/3/4/5/6/7 Table 13.1. CIP-51 Instruction Set Summary (Continued) Description Bytes XRL direct, #data CLR A CPL A RL A RLC A RR A RRC A SWAP A Exclusive-OR immediate to direct byte Clear A Complement A Rotate A left Rotate A left through Carry Rotate A right Rotate A right through Carry Swap nibbles of A 3 1 1 1 1 1 1 1 Move Register to A Move direct byte to A Move indirect RAM to A Move immediate to A Move A to Register Move direct byte to Register Move immediate to Register Move A to direct byte Move Register to direct byte Move direct byte to direct byte Move indirect RAM to direct byte Move immediate to direct byte Move A to indirect RAM Move direct byte to indirect RAM Move immediate to indirect RAM Load DPTR with 16-bit constant Move code byte relative DPTR to A Move code byte relative PC to A Move external data (8-bit address) to A Move A to external data (8-bit address) Move external data (16-bit address) to A Move A to external data (16-bit address) Push direct byte onto stack Pop direct byte from stack Exchange Register with A Exchange direct byte with A Exchange indirect RAM with A Exchange low nibble of indirect RAM with A 1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1 1 2 2 2 1 2 2 2 2 3 2 3 2 2 2 3 3 3 3 3 3 3 2 2 1 2 2 2 Clear Carry Clear direct bit Set Carry Set direct bit Complement Carry Complement direct bit 1 2 1 2 1 2 1 2 1 2 1 2 N ew fo r m en de d om ec R D 3 1 1 1 1 1 1 1 Data Transfer MOV A, Rn MOV A, direct MOV A, @Ri MOV A, #data MOV Rn, A MOV Rn, direct MOV Rn, #data MOV direct, A MOV direct, Rn MOV direct, direct MOV direct, @Ri MOV direct, #data MOV @Ri, A MOV @Ri, direct MOV @Ri, #data MOV DPTR, #data16 MOVC A, @A+DPTR MOVC A, @A+PC MOVX A, @Ri MOVX @Ri, A MOVX A, @DPTR MOVX @DPTR, A PUSH direct POP direct XCH A, Rn XCH A, direct XCH A, @Ri XCHD A, @Ri Clock Cycles es ig ns Mnemonic N ot Boolean Manipulation CLR C CLR bit SETB C SETB bit CPL C CPL bit 71 Rev 1.1 C8051T610/1/2/3/4/5/6/7 Table 13.1. CIP-51 Instruction Set Summary (Continued) ANL C, bit ANL C, /bit ORL C, bit ORL C, /bit MOV C, bit MOV bit, C JC rel JNC rel JB bit, rel JNB bit, rel JBC bit, rel AND direct bit to Carry AND complement of direct bit to Carry OR direct bit to carry OR complement of direct bit to Carry Move direct bit to Carry Move Carry to direct bit Jump if Carry is set Jump if Carry is not set Jump if direct bit is set Jump if direct bit is not set Jump if direct bit is set and clear bit Program Branching CJNE @Ri, #data, rel fo r 2 2 2 2 2 2 2 2 3 3 3 2 2 2 2 2 2 2/3 2/3 3/4 3/4 3/4 2 3 1 1 2 3 2 1 2 2 3 3 3 3 4 5 5 3 4 3 3 2/3 2/3 4/5 3/4 3/4 3 4/5 2 3 1 2/3 3/4 1 N ot R ec om DJNZ Rn, rel DJNZ direct, rel NOP Absolute subroutine call Long subroutine call Return from subroutine Return from interrupt Absolute jump Long jump Short jump (relative address) Jump indirect relative to DPTR Jump if A equals zero Jump if A does not equal zero Compare direct byte to A and jump if not equal Compare immediate to A and jump if not equal Compare immediate to Register and jump if not equal Compare immediate to indirect and jump if not equal Decrement Register and jump if not zero Decrement direct byte and jump if not zero No operation m en de d ACALL addr11 LCALL addr16 RET RETI AJMP addr11 LJMP addr16 SJMP rel JMP @A+DPTR JZ rel JNZ rel CJNE A, direct, rel CJNE A, #data, rel CJNE Rn, #data, rel Clock Cycles es ig ns Bytes D Description N ew Mnemonic Rev 1.1 72 C8051T610/1/2/3/4/5/6/7 Rn - Register R0–R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. es ig ns Notes on Registers, Operands and Addressing Modes: D rel - 8-bit, signed (twos complement) offset relative to the first byte of the following instruction. Used by SJMP and all conditional jumps. N ew direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location (0x00– 0x7F) or an SFR (0x80–0xFF). #data - 8-bit constant #data16 - 16-bit constant bit - Direct-accessed bit in Data RAM or SFR fo r addr11 - 11-bit destination address used by ACALL and AJMP. The destination must be within the same 2 kB page of program memory as the first byte of the following instruction. m en de d addr16 - 16-bit destination address used by LCALL and LJMP. The destination may be anywhere within the 8 kB program memory space. N ot R ec om There is one unused opcode (0xA5) that performs the same function as NOP. All mnemonics copyrighted © Intel Corporation 1980. 73 Rev 1.1 C8051T610/1/2/3/4/5/6/7 13.2. CIP-51 Register Descriptions SFR Definition 13.1. DPL: Data Pointer Low Byte Bit 7 6 5 4 3 DPL[7:0] Type R/W 0 Reset 0 0 0 0 0 0 3 2 1 0 0 0 0 0 Function Data Pointer Low. fo r DPL[7:0] 0 0 SFR Address = 0x82 Bit Name 7:0 1 N ew Name 2 D es ig ns Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should always be written to the value indicated in the SFR description. Future product versions may use these bits to implement new features in which case the reset value of the bit will be the indicated value, selecting the feature's default state. Detailed descriptions of the remaining SFRs are included in the sections of the data sheet associated with their corresponding system function. m en de d The DPL register is the low byte of the 16-bit DPTR. SFR Definition 13.2. DPH: Data Pointer High Byte Bit 7 6 5 4 DPH[7:0] Name R/W Type 0 0 0 0 om Reset SFR Address = 0x83 Bit Name DPH[7:0] Data Pointer High. ec 7:0 Function N ot R The DPH register is the high byte of the 16-bit DPTR. Rev 1.1 74 C8051T610/1/2/3/4/5/6/7 7 6 5 4 Name SP[7:0] Type R/W 0 Reset 0 0 0 SFR Address = 0x81 Bit Name SP[7:0] 2 0 1 1 0 1 1 Function Stack Pointer. N ew 7:0 3 D Bit es ig ns SFR Definition 13.3. SP: Stack Pointer The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented before every PUSH operation. The SP register defaults to 0x07 after reset. Bit 7 6 5 fo r SFR Definition 13.4. ACC: Accumulator 4 2 1 0 0 0 0 0 ACC[7:0] m en de d Name R/W Type 0 Reset 0 0 0 SFR Address = 0xE0; Bit-Addressable Bit Name 7:0 3 ACC[7:0] Function Accumulator. om This register is the accumulator for arithmetic operations. ec SFR Definition 13.5. B: B Register 7 6 5 4 Name B[7:0] R Bit R/W Type N ot Reset 0 0 0 0 SFR Address = 0xF0; Bit-Addressable Bit Name 7:0 B[7:0] 3 2 1 0 0 0 0 0 Function B Register. This register serves as a second accumulator for certain arithmetic operations. 75 Rev 1.1 C8051T610/1/2/3/4/5/6/7 7 6 5 4 3 Name CY AC F0 RS[1:0] OV Type R/W R/W R/W R/W R/W Reset 0 0 0 0 SFR Address = 0xD0; Bit-Addressable Bit Name CY Function Carry Flag. 0 1 0 F1 PARITY R/W R 0 0 N ew 7 0 2 D Bit es ig ns SFR Definition 13.6. PSW: Program Status Word This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow (subtraction). It is cleared to logic 0 by all other arithmetic operations. 6 AC Auxiliary Carry Flag. 5 F0 User Flag 0. fo r This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow from (subtraction) the high order nibble. It is cleared to logic 0 by all other arithmetic operations. This is a bit-addressable, general purpose flag for use under software control. RS[1:0] Register Bank Select. m en de d 4:3 These bits select which register bank is used during register accesses. 00: Bank 0, Addresses 0x00-0x07 01: Bank 1, Addresses 0x08-0x0F 10: Bank 2, Addresses 0x10-0x17 11: Bank 3, Addresses 0x18-0x1F 2 OV Overflow Flag. This bit is set to 1 under the following circumstances: ADD, ADDC, or SUBB instruction causes a sign-change overflow. MUL instruction results in an overflow (result is greater than 255). l A DIV instruction causes a divide-by-zero condition. om l An lA ec The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other cases. 1 F1 User Flag 1. R This is a bit-addressable, general purpose flag for use under software control. N ot 0 PARITY Parity Flag. This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum is even. Rev 1.1 76 C8051T610/1/2/3/4/5/6/7 14. Memory Organization C8051T610/1/6/7 CODE MEMORY DATA MEMORY (RAM) INTERNAL DATA ADDRESS SPACE Upper 128 RAM (Indirect Addressing Only) N ew 0x80 0x7F (Direct and Indirect Addressing) 16k Bytes EPROM 0x30 0x2F Bit Addressable 0x20 0x1F General Purpose Registers 0x00 EXTERNAL DATA ADDRESS SPACE m en de d C8051T612/3/4/5 CODE MEMORY Lower 128 RAM (Direct and Indirect Addressing) fo r 0x0000 Special Function Register's (Direct Addressing Only) D 0xFF RESERVED 0x3E00 0x3DFF es ig ns The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space but are accessed via different instruction types. The memory organization of the C8051T610/1/2/3/4/5/6/7 device family is shown in Figure 14.1 0xFFFF RESERVED Same 1024 bytes as from 0x0000 to 0x03FF, wrapped on 1024-byte boundaries 0x2000 0x1FFF 0x0400 0x03FF 0x0000 XRAM - 1024 Bytes (accessable using MOVX instruction) Figure 14.1. Memory Map N ot R ec 0x0000 om 8k Bytes EPROM Rev 1.1 77 C8051T610/1/2/3/4/5/6/7 14.1. Program Memory Security Byte 0x3FFF Reserved 0x3FFE 0x3E00 0x3DFF Security Byte 0x3FFF D C8051T612/3/4/5 0x3FFE N ew C8051T610/1/6/7 es ig ns The CIP-51 core has a 64 kB program memory space. The C8051T610/1/6/7 implements 15872 bytes of this program memory space as in-system, Byte-Programmable EPROM, organized in a contiguous block from addresses 0x0000 to 0x3FFF. Note that 512 bytes (0x3E00 – 0x3FFF) of this memory are reserved for factory use and are not available for user program storage. The C8051T612/3/4/5 implements 8192 bytes of EPROM program memory space. Figure 14.2 shows the program memory maps for C8051T610/1/2/3/4/5/6/7 devices. Reserved fo r 15872 Bytes EPROM Memory 0x2000 0x1FFF m en de d 8192 Bytes EPROM Memory 0x0000 0x0000 Figure 14.2. Program Memory Map Program memory is read-only from within firmware. Individual program memory bytes can be read using the MOVC instruction. This facilitates the use of EPROM space for constant storage. 14.2. Data Memory om The C8051T610/1/2/3/4/5/6/7 device family includes 1280 bytes of RAM data memory. 256 bytes of this memory is mapped into the internal RAM space of the 8051. 1024 bytes of this memory is on-chip “external” memory. The data memory map is shown in Figure 14.1 for reference. 14.2.1. Internal RAM R ec There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or as 128 bit locations accessible with the direct addressing mode. N ot The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the same address space as the Special Function Registers (SFR) but is physically separate from the SFR space. The addressing mode used by an instruction when accessing locations above 0x7F determines whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the upper 128 bytes of data memory. Figure 14.1 illustrates the data memory organization of the C8051T610/1/2/3/4/5/6/7. 78 Rev 1.1 C8051T610/1/2/3/4/5/6/7 14.2.1.1. General Purpose Registers es ig ns The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of general-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1 (PSW.4), select the active register bank (see description of the PSW in SFR Definition 13.6). This allows fast context switching when entering subroutines and interrupt service routines. Indirect addressing modes use registers R0 and R1 as index registers. 14.2.1.2. Bit Addressable Locations N ew D In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from 0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address 0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by the type of instruction used (bit source or destination operands as opposed to a byte source or destination). The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where XX is the byte address and B is the bit position within the byte. For example, the instruction: MOV C, 22.3h moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag. fo r 14.2.1.3. Stack m en de d A programmer's stack can be located anywhere in the 256-byte data memory. The stack area is designated using the Stack Pointer (SP) SFR. The SP will point to the last location used. The next value pushed on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to location 0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the first register (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be initialized to a location in the data memory not being used for data storage. The stack depth can extend up to 256 bytes. 14.2.2. External RAM om There are 1024 bytes of on-chip RAM mapped into the external data memory space. All of these address locations may be accessed using the external move instruction (MOVX) and the data pointer (DPTR), or using MOVX indirect addressing mode. If the MOVX instruction is used with an 8-bit address operand (such as @R1), then the high byte of the 16-bit address is provided by the External Memory Interface Control Register (EMI0CN as shown in SFR Definition 14.1). N ot R ec For a 16-bit MOVX operation (@DPTR), the upper 7 bits of the 16-bit external data memory address word are "don't cares". As a result, the 1024-byte RAM is mapped modulo style over the entire 64 k external data memory address range. For example, the XRAM byte at address 0x0000 is shadowed at addresses 0x0400, 0x0800, 0x0C00, 0x1000, etc. This is a useful feature when performing a linear memory fill, as the address pointer doesn't have to be reset when reaching the RAM block boundary. Rev 1.1 79 C8051T610/1/2/3/4/5/6/7 Bit 7 6 5 4 3 2 es ig ns SFR Definition 14.1. EMI0CN: External Memory Interface Control 1 0 PGSEL Type R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 SFR Address = 0xAA Bit Name Function 0 N ew 7:2 Unused Unused. Read = 000000b; Write = Don’t Care 1:0 PGSEL[1:0] XRAM Page Select. R/W 0 D Name N ot R ec om m en de d fo r The EMI0CN register provides the high byte of the 16-bit external data memory address when using an 8-bit MOVX command, effectively selecting a 256-byte page of RAM. Since the upper (unused) bits of the register are always zero, the PGSEL bits determine which page of XRAM is accessed. For Example: If EMI0CN = 0x01, addresses 0x0100 through 0x01FF will be accessed. 80 Rev 1.1 C8051T610/1/2/3/4/5/6/7 15. Special Function Registers es ig ns The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the C8051T610/1/2/3/4/5/6/7's resources and peripherals. The CIP-51 controller core duplicates the SFRs found in a typical 8051 implementation as well as implementing additional SFRs used to configure and access the sub-systems unique to the C8051T610/1/2/3/4/5/6/7. This allows the addition of new functionality while retaining compatibility with the MCS-51™ instruction set. Table 15.1 lists the SFRs implemented in the C8051T610/1/2/3/4/5/6/7 device family. N ew D The SFR registers are accessed anytime the direct addressing mode is used to access memory locations from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are bitaddressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate effect and should be avoided. Refer to the corresponding pages of the data sheet, as indicated in Table 15.2, for a detailed description of each register. Table 15.1. Special Function Register (SFR) Memory Map om m en de d fo r SPI0CN PCA0L PCA0H PCA0CPL0 PCA0CPH0 PCA0CPL4 PCA0CPH4 VDM0CN B P0MDIN P1MDIN P2MDIN P3MDIN EIP1 ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 PCA0CPL3 PCA0CPH3 RSTSRC ACC XBR0 XBR1 IT01CF EIE1 PCA0CN PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 PCA0CPM3 PCA0CPM4 PSW REF0CN P0SKIP P1SKIP P2SKIP TMR2CN TMR2RLL TMR2RLH TMR2L TMR2H SMB0CN SMB0CF SMB0DAT ADC0GTL ADC0GTH ADC0LTL ADC0LTH REG0CN IP AMX0P ADC0CF ADC0L ADC0H P3 OSCXCN OSCICN OSCICL IE CLKSEL EMI0CN P2 SPI0CFG SPI0CKR SPI0DAT P0MDOUT P1MDOUT P2MDOUT P3MDOUT SCON0 SBUF0 CPT1CN CPT0CN CPT1MD CPT0MD CPT1MX CPT0MX P1 TMR3CN TMR3RLL TMR3RLH TMR3L TMR3H TCON TMOD TL0 TL1 TH0 TH1 CKCON P0 SP DPL DPH TOFFL TOFFH PCON 0(8) 1(9) 2(A) 3(B) 4(C) 5(D) 6(E) 7(F) (bit addressable) N ot R ec F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 Rev 1.1 81 C8051T610/1/2/3/4/5/6/7 Table 15.2. Special Function Registers Register Address Description es ig ns SFRs are listed in alphabetical order. All undefined SFR locations are reserved Page ACC 0xE0 Accumulator ADC0CF 0xBC ADC0 Configuration ADC0CN 0xE8 ADC0 Control ADC0GTH 0xC4 ADC0 Greater-Than Compare High ADC0GTL 0xC3 ADC0 Greater-Than Compare Low ADC0H 0xBE ADC0 High ADC0L 0xBD ADC0 Low ADC0LTH 0xC6 ADC0 Less-Than Compare Word High 47 ADC0LTL 0xC5 ADC0 Less-Than Compare Word Low 47 AMX0P 0xBB AMUX0 Positive Channel Select 50 B 0xF0 B Register 75 CKCON 0x8E Clock Control CLKSEL 0xA9 Clock Select CPT0CN 0x9B Comparator0 Control 61 CPT0MD 0x9D Comparator0 Mode Selection 62 CPT0MX 0x9F Comparator0 MUX Selection 66 CPT1CN 0x9A Comparator1 Control 63 CPT1MD 0x9C Comparator1 Mode Selection 64 CPT1MX 0x9E Comparator1 MUX Selection 67 DPH 0x83 Data Pointer High 74 DPL 0x82 Data Pointer Low 74 EIE1 0xE6 Extended Interrupt Enable 1 90 0xF6 Extended Interrupt Priority 1 91 0xAA External Memory Interface Control 80 0xA8 Interrupt Enable 88 IP 0xB8 Interrupt Priority 89 IT01CF 0xE4 INT0/INT1 Configuration 93 OSCICL 0xB3 Internal Oscillator Calibration 108 OSCICN 0xB2 Internal Oscillator Control 109 OSCXCN 0xB1 External Oscillator Control 111 P0 0x80 Port 0 Latch 124 P0MDIN 0xF1 Port 0 Input Mode Configuration 125 P0MDOUT 0xA4 Port 0 Output Mode Configuration 125 EMI0CN N ot R 82 43 45 46 D 46 N ew fo r m en de d ec IE om EIP1 75 Rev 1.1 44 44 171 107 C8051T610/1/2/3/4/5/6/7 Table 15.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Address Description Page es ig ns Register P0SKIP 0xD4 Port 0 Skip 126 P1 0x90 Port 1 Latch P1MDIN 0xF2 Port 1 Input Mode Configuration P1MDOUT 0xA5 Port 1 Output Mode Configuration P1SKIP 0xD5 Port 1 Skip P2 0xA0 Port 2 Latch P2MDIN 0xF3 Port 2 Input Mode Configuration P2MDOUT 0xA6 Port 2 Output Mode Configuration 129 P2SKIP 0xD6 Port 2 Skip 130 P3 0xB0 Port 3 Latch P3MDIN 0xF4 Port 3 Input Mode Configuration 131 P3MDOUT 0xA7 Port 3 Output Mode Configuration 131 PCA0CN 0xD8 PCA Control PCA0CPH0 0xFC PCA Capture 0 High 207 PCA0CPH1 0xEA PCA Capture 1 High 207 PCA0CPH2 0xEC PCA Capture 2 High PCA0CPH3 0xEE PCA Capture 3 High 207 PCA0CPH4 0xFE PCA Capture 4 High 207 PCA0CPL0 0xFB PCA Capture 0 Low 207 PCA0CPL1 0xE9 PCA Capture 1 Low 207 PCA0CPL2 0xEB PCA Capture 2 Low 207 PCA0CPL3 0xED PCA Capture 3 Low 207 126 127 127 128 129 130 203 207 PCA0CPL4 0xFD PCA Capture 4 Low 207 PCA0CPM0 0xDA PCA Module 0 Mode Register 205 PCA0CPM1 0xDB PCA Module 1 Mode Register 205 ec om m en de d fo r N ew D 128 0xDC PCA Module 2 Mode Register 205 PCA0CPM3 0xDD PCA Module 3 Mode Register 205 PCA0CPM4 0xDE PCA Module 4 Mode Register 205 PCA0H 0xFA PCA Counter High 206 PCA0L 0xF9 PCA Counter Low 206 PCA0MD 0xD9 PCA Mode 204 PCON 0x87 Power Control 99 PSW 0xD0 Program Status Word 76 REF0CN 0xD1 Voltage Reference Control 55 N ot R PCA0CPM2 Rev 1.1 83 C8051T610/1/2/3/4/5/6/7 Table 15.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Address Description Page es ig ns Register REG0CN 0xC7 Voltage Regulator Control 57 RSTSRC 0xEF Reset Source Configuration/Status SBUF0 0x99 UART0 Data Buffer SCON0 0x98 UART0 Control SMB0CF 0xC1 SMBus Configuration SMB0CN 0xC0 SMBus Control SMB0DAT 0xC2 SMBus Data SP 0x81 Stack Pointer SPI0CFG 0xA1 SPI Configuration SPI0CKR 0xA2 SPI Clock Rate Control SPI0CN 0xF8 SPI Control SPI0DAT 0xA3 SPI Data TCON 0x88 Timer/Counter Control 176 TH0 0x8C Timer/Counter 0 High 179 TH1 0x8D Timer/Counter 1 High 179 TL0 0x8A Timer/Counter 0 Low 178 TL1 0x8B Timer/Counter 1 Low 178 TMOD 0x89 Timer/Counter Mode 177 TMR2CN 0xC8 Timer/Counter 2 Control 182 TMR2H 0xCD Timer/Counter 2 High 184 TMR2L 0xCC Timer/Counter 2 Low 183 TMR2RLH 0xCB Timer/Counter 2 Reload High 183 155 154 fo r N ew D 138 m en de d om 105 140 142 75 164 166 165 166 0xCA Timer/Counter 2 Reload Low 183 TMR3CN 0x91 Timer/Counter 3Control 187 TMR3H 0x95 Timer/Counter 3 High 189 TMR3L 0x94 Timer/Counter 3Low 188 TMR3RLH 0x93 Timer/Counter 3 Reload High 188 TMR3RLL R 0x92 Timer/Counter 3 Reload Low 188 TOFFH 0x86 Temperature Sensor Offset Measurement High 53 N ot ec TMR2RLL TOFFL 0x85 Temperature Sensor Offset Measurement Low 53 VDM0CN 0xFF VDD Monitor Control 103 XBR0 0xE1 Port I/O Crossbar Control 0 122 XBR1 0xE2 Port I/O Crossbar Control 1 123 84 Rev 1.1 C8051T610/1/2/3/4/5/6/7 16. Interrupts es ig ns The C8051T610/1/2/3/4/5/6/7 includes an extended interrupt system supporting a total of 14 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and external input pins varies according to the specific version of the device. Each interrupt source has one or more associated interrupt-pending flag(s) located in an SFR. When a peripheral or external source meets a valid interrupt condition, the associated interrupt-pending flag is set to logic 1. N ew D If interrupts are enabled for the source, an interrupt request is generated when the interrupt-pending flag is set. As soon as execution of the current instruction is complete, the CPU generates an LCALL to a predetermined address to begin execution of an interrupt service routine (ISR). Each ISR must end with an RETI instruction, which returns program execution to the next instruction that would have been executed if the interrupt request had not occurred. If interrupts are not enabled, the interrupt-pending flag is ignored by the hardware and program execution continues as normal. (The interrupt-pending flag is set to logic 1 regardless of the interrupt's enable/disable state.) Each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in an SFR (IE–EIE1). However, interrupts must first be globally enabled by setting the EA bit (IE.7) to logic 1 before the individual interrupt enables are recognized. Setting the EA bit to logic 0 disables all interrupt sources regardless of the individual interrupt-enable settings. fo r Note: Any instruction that clears a bit to disable an interrupt should be immediately followed by an instruction that has two or more opcode bytes. Using EA (global interrupt enable) as an example: m en de d // in 'C': EA = 0; // clear EA bit. EA = 0; // this is a dummy instruction with two-byte opcode. ; in assembly: CLR EA ; clear EA bit. CLR EA ; this is a dummy instruction with two-byte opcode. For example, if an interrupt is posted during the execution phase of a "CLR EA" opcode (or any instruction which clears a bit to disable an interrupt source), and the instruction is followed by a single-cycle instruction, the interrupt may be taken. However, a read of the enable bit will return a '0' inside the interrupt service routine. When the bit-clearing opcode is followed by a multi-cycle instruction, the interrupt will not be taken. N ot R ec om Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR. However, most are not cleared by the hardware and must be cleared by software before returning from the ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI) instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after the completion of the next instruction. Rev 1.1 85 C8051T610/1/2/3/4/5/6/7 16.1. MCU Interrupt Sources and Vectors es ig ns The C8051T610/1/2/3/4/5/6/7 MCUs support 14 interrupt sources. Software can simulate an interrupt by setting any interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated and the CPU will vector to the ISR address associated with the interrupt-pending flag. MCU interrupt sources, associated vector addresses, priority order and control bits are summarized in Table 16.1. Refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). 16.1.1. Interrupt Priorities N ew D Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP or EIP1) used to configure its priority level. Low priority is the default. If two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is used to arbitrate, given in Table 16.1. 16.1.2. Interrupt Latency N ot R ec om m en de d fo r Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5 system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the ISR. If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL is made to service the pending interrupt. Therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is performing an RETI instruction followed by a DIV as the next instruction. In this case, the response time is 18 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the RETI, 8 clock cycles to complete the DIV instruction and 4 clock cycles to execute the LCALL to the ISR. If the CPU is executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the current ISR completes, including the RETI and following instruction. 86 Rev 1.1 C8051T610/1/2/3/4/5/6/7 Interrupt Vector Priority Order Pending Flag Reset 0x0000 Top None External Interrupt 0 (INT0) Timer 0 Overflow External Interrupt 1 (INT1) Timer 1 Overflow UART0 0x0003 0 IE0 (TCON.1) N/A N/A Always Always Enabled Highest Y Y EX0 (IE.0) PX0 (IP.0) 0x000B 0x0013 1 2 TF0 (TCON.5) IE1 (TCON.3) Y Y Y Y ET0 (IE.1) PT0 (IP.1) EX1 (IE.2) PX1 (IP.2) 0x001B 0x0023 3 4 Y Y Y N ET1 (IE.3) PT1 (IP.3) ES0 (IE.4) PS0 (IP.4) Timer 2 Overflow 0x002B 5 Y N ET2 (IE.5) PT2 (IP.5) SPI0 0x0033 6 TF1 (TCON.7) RI0 (SCON0.0) TI0 (SCON0.1) TF2H (TMR2CN.7) TF2L (TMR2CN.6) SPIF (SPI0CN.7) WCOL (SPI0CN.6) MODF (SPI0CN.5) RXOVRN (SPI0CN.4) SI (SMB0CN.0) Y N ESPI0 (IE.6) Y N 7 0x0043 0x004B 8 9 0x0053 10 0x005B 11 om RESERVED ADC0 Window Compare ADC0 Conversion Complete Programmable Counter Array 0x003B 0x0063 12 Comparator1 0x006B 13 Timer 3 Overflow 0x0073 14 R ec Comparator0 Priority Control D es ig ns Enable Flag N ew fo r m en de d SMB0 Cleared by HW? Interrupt Source Bit addressable? Table 16.1. Interrupt Summary N/A AD0WINT (ADC0CN.3) AD0INT (ADC0CN.5) ESMB0 (EIE1.0) N/A N/A N/A Y N EWADC0 (EIE1.2) Y N EADC0 (EIE1.3) Y N EPCA0 (EIE1.4) CF (PCA0CN.7) CCFn (PCA0CN.n) COVF (PCA0PWM.6) CP0FIF (CPT0CN.4) N CP0RIF (CPT0CN.5) CP1FIF (CPT1CN.4) N CP1RIF (CPT1CN.5) TF3H (TMR3CN.7) N TF3L (TMR3CN.6) N N N ECP0 (EIE1.5) ECP1 (EIE1.6) ET3 (EIE1.7) PSPI0 (IP.6) PSMB0 (EIP1.0) N/A PWADC0 (EIP1.2) PADC0 (EIP1.3) PPCA0 (EIP1.4) PCP0 (EIP1.5) PCP1 (EIP1.6) PT3 (EIP1.7) N ot 16.2. Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described in this section. Refer to the data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). Rev 1.1 87 C8051T610/1/2/3/4/5/6/7 7 6 5 4 3 2 Name EA ESPI0 ET2 ES0 ET1 EX1 Type R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 SFR Address = 0xA8; Bit-Addressable Bit Name Function EA 6 ESPI0 5 ET2 Enable Timer 2 Interrupt. This bit sets the masking of the Timer 2 interrupt. 0: Disable Timer 2 interrupt. 1: Enable interrupt requests generated by the TF2L or TF2H flags. 4 ES0 Enable UART0 Interrupt. This bit sets the masking of the UART0 interrupt. 0: Disable UART0 interrupt. 1: Enable UART0 interrupt. 3 ET1 Enable Timer 1 Interrupt. This bit sets the masking of the Timer 1 interrupt. 0: Disable all Timer 1 interrupt. 1: Enable interrupt requests generated by the TF1 flag. 2 EX1 88 ET0 EX0 R/W R/W 0 0 Enable All Interrupts. Globally enables/disables all interrupts. It overrides individual interrupt mask settings. 0: Disable all interrupt sources. 1: Enable each interrupt according to its individual mask setting. om m en de d fo r Enable Serial Peripheral Interface (SPI0) Interrupt. This bit sets the masking of the SPI0 interrupts. 0: Disable all SPI0 interrupts. 1: Enable interrupt requests generated by SPI0. Enable External Interrupt 1. This bit sets the masking of External Interrupt 1. 0: Disable external interrupt 1. 1: Enable interrupt requests generated by the /INT1 input. ec R N ot 0 0 N ew 7 1 1 D Bit es ig ns SFR Definition 16.1. IE: Interrupt Enable ET0 Enable Timer 0 Interrupt. This bit sets the masking of the Timer 0 interrupt. 0: Disable all Timer 0 interrupt. 1: Enable interrupt requests generated by the TF0 flag. EX0 Enable External Interrupt 0. This bit sets the masking of External Interrupt 0. 0: Disable external interrupt 0. 1: Enable interrupt requests generated by the INT0 input. Rev 1.1 C8051T610/1/2/3/4/5/6/7 7 Name 6 5 4 3 2 PSPI0 PT2 PS0 PT1 PX1 Type R R/W R/W R/W R/W R/W Reset 1 0 0 0 0 0 SFR Address = 0xB8; Bit-Addressable Bit Name Function Unused Unused. Read = 1, Write = Don't Care. 6 PSPI0 5 PT2 Timer 2 Interrupt Priority Control. This bit sets the priority of the Timer 2 interrupt. 0: Timer 2 interrupt set to low priority level. 1: Timer 2 interrupt set to high priority level. 4 PS0 UART0 Interrupt Priority Control. This bit sets the priority of the UART0 interrupt. 0: UART0 interrupt set to low priority level. 1: UART0 interrupt set to high priority level. 3 PT1 Timer 1 Interrupt Priority Control. This bit sets the priority of the Timer 1 interrupt. 0: Timer 1 interrupt set to low priority level. 1: Timer 1 interrupt set to high priority level. 2 PX1 External Interrupt 1 Priority Control. This bit sets the priority of the External Interrupt 1 interrupt. 0: External Interrupt 1 set to low priority level. 1: External Interrupt 1 set to high priority level. 0 PT0 PX0 R/W R/W 0 0 N ew 7 1 D Bit es ig ns SFR Definition 16.2. IP: Interrupt Priority ec om m en de d fo r Serial Peripheral Interface (SPI0) Interrupt Priority Control. This bit sets the priority of the SPI0 interrupt. 0: SPI0 interrupt set to low priority level. 1: SPI0 interrupt set to high priority level. PT0 R 1 N ot 0 PX0 Timer 0 Interrupt Priority Control. This bit sets the priority of the Timer 0 interrupt. 0: Timer 0 interrupt set to low priority level. 1: Timer 0 interrupt set to high priority level. External Interrupt 0 Priority Control. This bit sets the priority of the External Interrupt 0 interrupt. 0: External Interrupt 0 set to low priority level. 1: External Interrupt 0 set to high priority level. Rev 1.1 89 C8051T610/1/2/3/4/5/6/7 7 6 5 4 3 2 Name ET3 ECP1 ECP0 EPCA0 EADC0 Type R/W R/W R/W R/W Reset 0 0 0 0 SFR Address = 0xE6 Bit Name 1 0 EWADC0 Reserved ESMB0 R/W R/W R/W R/W 0 0 0 0 Function ET3 Enable Timer 3 Interrupt. This bit sets the masking of the Timer 3 interrupt. 0: Disable Timer 3 interrupts. 1: Enable interrupt requests generated by the TF3L or TF3H flags. 6 ECP1 Enable Comparator1 (CP1) Interrupt. This bit sets the masking of the CP1 interrupt. 0: Disable CP1 interrupts. 1: Enable interrupt requests generated by the CP1RIF or CP1FIF flags. 5 ECP0 Enable Comparator0 (CP0) Interrupt. This bit sets the masking of the CP0 interrupt. 0: Disable CP0 interrupts. 1: Enable interrupt requests generated by the CP0RIF or CP0FIF flags. 4 EPCA0 Enable Programmable Counter Array (PCA0) Interrupt. This bit sets the masking of the PCA0 interrupts. 0: Disable all PCA0 interrupts. 1: Enable interrupt requests generated by PCA0. 3 EADC0 Enable ADC0 Conversion Complete Interrupt. This bit sets the masking of the ADC0 Conversion Complete interrupt. 0: Disable ADC0 Conversion Complete interrupt. 1: Enable interrupt requests generated by the AD0INT flag. om m en de d fo r N ew 7 EWADC0 Enable Window Comparison ADC0 Interrupt. This bit sets the masking of ADC0 Window Comparison interrupt. 0: Disable ADC0 Window Comparison interrupt. 1: Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT). R ec 2 1 N ot 0 90 D Bit es ig ns SFR Definition 16.3. EIE1: Extended Interrupt Enable 1 Reserved Reserved. Must Write 0. ESMB0 Enable SMBus (SMB0) Interrupt. This bit sets the masking of the SMB0 interrupt. 0: Disable all SMB0 interrupts. 1: Enable interrupt requests generated by SMB0. Rev 1.1 C8051T610/1/2/3/4/5/6/7 7 6 5 4 3 2 Name PT3 PCP1 PCP0 PPCA0 PADC0 Type R/W R/W R/W R/W Reset 0 0 0 0 SFR Address = 0xF6 Bit Name 1 0 PWADC0 Reserved PSMB0 R/W R/W R/W R/W 0 0 0 0 Function D Bit es ig ns SFR Definition 16.4. EIP1: Extended Interrupt Priority 1 PT3 Timer 3 Interrupt Priority Control. This bit sets the priority of the Timer 3 interrupt. 0: Timer 3 interrupts set to low priority level. 1: Timer 3 interrupts set to high priority level. 6 PCP1 Comparator1 (CP1) Interrupt Priority Control. This bit sets the priority of the CP1 interrupt. 0: CP1 interrupt set to low priority level. 1: CP1 interrupt set to high priority level. 5 PCP0 Comparator0 (CP0) Interrupt Priority Control. This bit sets the priority of the CP0 interrupt. 0: CP0 interrupt set to low priority level. 1: CP0 interrupt set to high priority level. 4 PPCA0 Programmable Counter Array (PCA0) Interrupt Priority Control. This bit sets the priority of the PCA0 interrupt. 0: PCA0 interrupt set to low priority level. 1: PCA0 interrupt set to high priority level. 3 PADC0 ADC0 Conversion Complete Interrupt Priority Control. This bit sets the priority of the ADC0 Conversion Complete interrupt. 0: ADC0 Conversion Complete interrupt set to low priority level. 1: ADC0 Conversion Complete interrupt set to high priority level. fo r m en de d om PWADC0 ADC0 Window Comparator Interrupt Priority Control. This bit sets the priority of the ADC0 Window interrupt. 0: ADC0 Window interrupt set to low priority level. 1: ADC0 Window interrupt set to high priority level. R ec 2 N ew 7 1 N ot 0 Reserved Reserved. Must Write 0. PSMB0 SMBus (SMB0) Interrupt Priority Control. This bit sets the priority of the SMB0 interrupt. 0: SMB0 interrupt set to low priority level. 1: SMB0 interrupt set to high priority level. Rev 1.1 91 C8051T610/1/2/3/4/5/6/7 16.3. External Interrupts INT0 and INT1 es ig ns The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level sensitive. The IN0PL (INT0 Polarity) and IN1PL (INT1 Polarity) bits in the IT01CF register select active high or active low; the IT0 and IT1 bits in TCON (Section “25.1. Timer 0 and Timer 1” on page 172) select level or edge sensitive. The table below lists the possible configurations. IN0PL /INT0 Interrupt IT1 IN1PL /INT1 Interrupt 1 1 0 0 0 1 0 1 Active low, edge sensitive Active high, edge sensitive Active low, level sensitive Active high, level sensitive 1 1 0 0 0 1 0 1 Active low, edge sensitive Active high, edge sensitive Active low, level sensitive Active high, level sensitive D IT0 N ew INT0 and INT1 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 16.5). Note that INT0 and INT0 Port pin assignments are independent of any Crossbar assignments. INT0 and INT1 will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin via the Crossbar. To assign a Port pin only to INT0 and/or INT1, configure the Crossbar to skip the selected pin(s). This is accomplished by setting the associated bit in register XBR0 (see Section “21.3. Priority Crossbar Decoder” on page 117 for complete details on configuring the Crossbar). N ot R ec om m en de d fo r IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the INT0 and INT1 external interrupts, respectively. If an INT0 or INT1 external interrupt is configured as edge-sensitive, the corresponding interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inactive. The external interrupt source must hold the input active until the interrupt request is recognized. It must then deactivate the interrupt request before execution of the ISR completes or another interrupt request will be generated. 92 Rev 1.1 C8051T610/1/2/3/4/5/6/7 Bit 7 Name IN1PL IN1SL[2:0] IN0PL IN0SL[2:0] Type R/W R/W R/W R/W Reset 0 0 5 0 4 3 0 0 SFR Address = 0xE4 Name 7 IN1PL INT1 Polarity. 0: /INT1 input is active low. 1: /INT1 input is active high. 0 0 1 IN1SL[2:0] INT1 Port Pin Selection Bits. These bits select which Port pin is assigned to /INT1. Note that this pin assignment is independent of the Crossbar; /INT1 will monitor the assigned Port pin without disturbing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar will not assign the Port pin to a peripheral if it is configured to skip the selected pin. 000: Select P0.0 001: Select P0.1 010: Select P0.2 011: Select P0.3 100: Select P0.4 101: Select P0.5 110: Select P0.6 111: Select P0.7 INT0 Polarity. 0: /INT0 input is active low. 1: /INT0 input is active high. IN0SL[2:0] INT0 Port Pin Selection Bits. These bits select which Port pin is assigned to /INT0. Note that this pin assignment is independent of the Crossbar; /INT0 will monitor the assigned Port pin without disturbing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar will not assign the Port pin to a peripheral if it is configured to skip the selected pin. 000: Select P0.0 001: Select P0.1 010: Select P0.2 011: Select P0.3 100: Select P0.4 101: Select P0.5 110: Select P0.6 111: Select P0.7 N ot R ec 2:0 IN0PL om 3 m en de d fo r 6:4 Function 0 1 N ew Bit 2 D 6 es ig ns SFR Definition 16.5. IT01CF: INT0/INT1 Configuration Rev 1.1 93 C8051T610/1/2/3/4/5/6/7 17. EPROM Memory es ig ns Electrically programmable read-only memory (EPROM) is included on-chip for program code storage. The EPROM memory can be programmed via the C2 debug and programming interface when a special programming voltage is applied to the VPP pin. Each location in EPROM memory is programmable only once (i.e., non-erasable). Table 7.6 on page 34 shows the EPROM specifications. 17.1. Programming and Reading the EPROM Memory 17.1.1. EPROM Write Procedure 1. Reset the device using the RST pin. 2. Wait at least 20 µs before sending the first C2 command. N ew D Reading and writing the EPROM memory is accomplished through the C2 programming and debug interface. When creating hardware to program the EPROM, it is necessary to follow the programming steps listed below. Refer to the “C2 Interface Specification” available at http://www.silabs.com for details on communicating via the C2 interface. Section “27. C2 Interface” on page 208 has information about C2 register addresses for the C8051T610/1/2/3/4/5/6/7. 3. Place the device in core reset: Write 0x04 to the DEVCTL register. 4. Set the device to program mode (1st step): Write 0x40 to the EPCTL register. fo r 5. Set the device to program mode (2nd step): Write 0x4A to the EPCTL register. Note: Prior to date code 1119, 0x58 should be written to EPCTL. 6. Apply the VPP programming Voltage. m en de d 7. Write the first EPROM address for programming to EPADDRH and EPADDRL. 8. Write a data byte to EPDAT. EPADDRH:L will increment by 1 after this write. 9. Use a C2 Address Read command to poll for write completion. 10.(Optional) Check the ERROR bit in register EPSTAT and abort the programming operation if necessary. 11. If programming is not finished, return to Step 8 to write the next address in sequence, or return to Step 7 to program a new address. 12.Remove the VPP programming Voltage. 13.Remove program mode (1st step): Write 0x40 to the EPCTL register. 14.Remove program mode (2nd step): Write 0x00 to the EPCTL register. om 15.Reset the device: Write 0x02 and then 0x00 to the DEVCTL register. N ot R ec Important Note: There is a finite amount of time which VPP can be applied without damaging the device, which is cumulative over the life of the device. Refer to Table 7.1 on page 31 for the VPP timing specification. Rev 1.1 94 C8051T610/1/2/3/4/5/6/7 17.1.2. EPROM Read Procedure 1. Reset the device using the /RST pin. 3. Place the device in core reset: Write 0x04 to the DEVCTL register. 4. Write 0x00 to the EPCTL register. 5. Write the first EPROM address for reading to EPADDRH and EPADDRL. 6. Read a data byte from EPDAT. EPADDRH:L will increment by 1 after this read. es ig ns 2. Wait at least 20 µs before sending the first C2 command. 7. (Optional) Check the ERROR bit in register EPSTAT and abort the memory read operation if necessary. 9. Remove read mode (1st step): Write 0x40 to the EPCTL register. N ew 10.Remove read mode (2nd step): Write 0x00 to the EPCTL register. D 8. If reading is not finished, return to Step 6 to read the next address in sequence, or return to Step 5 to select a new address. 11. Reset the device: Write 0x02 and then 0x00 to the DEVCTL register. 17.2. Security Options fo r The C8051T610/1/2/3/4/5/6/7 devices provide security options to prevent unauthorized viewing of proprietary program code and constants. A security byte in EPROM address space can be used to lock the program memory from being read or written across the C2 interface. When read, the RDLOCK and WRLOCK bits in register EPSTAT will indicate the lock status of the location currently addressed by EPADDR. Table 17.1 shows the security byte decoding. See Section “14. Memory Organization” on page 77 for the security byte location and EPROM memory map. m en de d Important Note: Once the security byte has been written, there are no means of unlocking the device. Locking memory from write access should be performed only after all other code has been successfully programmed to memory. Table 17.1. Security Byte Decoding Bits 7–4 Write Lock: Clearing any of these bits to logic 0 prevents all code memory from being written across the C2 interface. Read Lock: Clearing any of these bits to logic 0 prevents all code memory from being read across the C2 interface. N ot R ec om 3–0 Description 95 Rev 1.1 C8051T610/1/2/3/4/5/6/7 17.3. Program Memory CRC es ig ns A CRC engine is included on-chip which provides a means of verifying EPROM contents once the device has been programmed. The CRC engine is available for EPROM verification even if the device is fully read and write locked, allowing for verification of code contents at any time. D The CRC engine is operated through the C2 debug and programming interface, and performs 16-bit CRCs on individual 256-Byte blocks of program memory, or a 32-bit CRC the entire memory space. To prevent hacking and extrapolation of security-locked source code, the CRC engine will only allow CRCs to be performed on contiguous 256-Byte blocks beginning on 256-Byte boundaries (lowest 8-bits of address are 0x00). For example, the CRC engine can perform a CRC for locations 0x0400 through 0x04FF, but it cannot perform a CRC for locations 0x0401 through 0x0500, or on block sizes smaller or larger than 256 bytes. N ew 17.3.1. Performing 32-bit CRCs on Full EPROM Content A 32-bit CRC on the entire EPROM space is initiated by writing to the CRC1 byte over the C2 interface. The CRC calculation begins at address 0x0000 and ends at the end of user EPROM space. The EPBusy bit in register C2ADD will be set during the CRC operation, and cleared once the operation is complete. The 32-bit results will be available in the CRC3-0 registers. CRC3 is the MSB, and CRC0 is the LSB. The polynomial used for the 32-bit CRC calculation is 0x04C11DB7. fo r Note: If a 16-bit CRC has been performed since the last device reset, a device reset should be initiated before performing a 32-bit CRC operation. 17.3.2. Performing 16-bit CRCs on 256-Byte EPROM Blocks N ot R ec om m en de d A 16-bit CRC of individual 256-byte blocks of EPROM can be initiated by writing to the CRC0 byte over the C2 interface. The value written to CRC0 is the high byte of the beginning address for the CRC. For example, if CRC0 is written to 0x02, the CRC will be performed on the 256-bytes beginning at address 0x0200, and ending at address 0x2FF. The EPBusy bit in register C2ADD will be set during the CRC operation, and cleared once the operation is complete. The 16-bit results will be available in the CRC1-0 registers. CRC1 is the MSB, and CRC0 is the LSB. The polynomial for the 16-bit CRC calculation is 0x1021 Rev 1.1 96 C8051T610/1/2/3/4/5/6/7 18. Power Management Modes D es ig ns The C8051T610/1/2/3/4/5/6/7 devices have two software programmable power management modes: idle, and stop. Idle mode halts the CPU while leaving the peripherals and clocks active. In stop mode, the CPU is halted, all interrupts and timers (except the missing clock detector) are inactive, and the internal oscillator is stopped (analog peripherals remain in their selected states; the external oscillator is not affected). Since clocks are running in idle mode, power consumption is dependent upon the system clock frequency and the number of peripherals left in active mode before entering Idle. Stop mode consumes the least power because the majority of the device is shut down with no clocks active. SFR Definition 18.1 describes the Power Control Register (PCON) used to control the C8051T610/1/2/3/4/5/6/7's stop and idle power management modes. N ew Although the C8051T610/1/2/3/4/5/6/7 has idle and stop modes available, more control over the device power can be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral can be disabled when not in use and placed in low power mode. Digital peripherals, such as timers or serial buses, draw little power when they are not in use. 18.1. Idle Mode fo r Setting the Idle Mode Select bit (PCON.0) causes the hardware to halt the CPU and enter idle mode as soon as the instruction that sets the bit completes execution. All internal registers and memory maintain their original data. All analog and digital peripherals can remain active during idle mode. m en de d Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume operation. The pending interrupt will be serviced and the next instruction to be executed after the return from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit. If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence and begins program execution at address 0x0000. If the instruction following the write of the IDLE bit is a single-byte instruction and an interrupt occurs during the execution phase of the instruction that sets the IDLE bit, the CPU may not wake from idle mode when a future interrupt occurs. Therefore, instructions that set the IDLE bit should be followed by an instruction that has two or more opcode bytes, for example: om // in ‘C’: PCON |= 0x01; PCON = PCON; ec ; in assembly: ORL PCON, #01h MOV PCON, PCON // set IDLE bit // ... followed by a 3-cycle dummy instruction ; set IDLE bit ; ... followed by a 3-cycle dummy instruction N ot R If enabled, the watchdog timer (WDT) will eventually cause an internal watchdog reset and thereby terminate the idle mode. This feature protects the system from an unintended permanent shutdown in the event of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by software prior to entering the idle mode if the WDT was initially configured to allow this operation. This provides the opportunity for additional power savings, allowing the system to remain in the idle mode indefinitely, waiting for an external stimulus to wake up the system. Refer to Section “19.6. PCA Watchdog Timer Reset” on page 104 for more information on the use and configuration of the WDT. Rev 1.1 97 C8051T610/1/2/3/4/5/6/7 18.2. Stop Mode es ig ns Setting the Stop Mode Select bit (PCON.1) causes the controller core to enter stop mode as soon as the instruction that sets the bit completes execution. In stop mode the internal oscillator, CPU, and all digital peripherals are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral (including the external oscillator circuit) may be shut down individually prior to entering stop mode. Stop mode can only be terminated by an internal or external reset. On reset, the device performs the normal reset sequence and begins program execution at address 0x0000. D If enabled, the missing clock detector will cause an internal reset and thereby terminate the stop mode. The missing clock detector should be disabled if the CPU is to be put to in stop mode for longer than the MCD timeout. N ot R ec om m en de d fo r N ew By default, when in stop mode the internal regulator is still active. However, the regulator can be configured to shut down while in stop mode to save power. To shut down the regulator in stop mode, the STOPCF bit in register REG0CN should be set to 1 prior to setting the STOP bit (see SFR Definition 11.1). If the regulator is shut down using the STOPCF bit, only the RST pin or a full power cycle are capable of resetting the device. 98 Rev 1.1 C8051T610/1/2/3/4/5/6/7 7 6 5 4 Name GF[5:0] Type R/W 0 Reset 0 0 0 SFR Address = 0x87 Bit Name GF[5:0] 0 Function General Purpose Flags 5–0. 2 0 1 0 STOP IDLE R/W R/W 0 0 N ew 7:2 3 D Bit es ig ns SFR Definition 18.1. PCON: Power Control These are general purpose flags for use under software control. STOP Stop Mode Select. Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0. 1: CPU goes into Stop mode (internal oscillator stopped). 0 IDLE Idle Mode Select. Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0. 1: CPU goes into Idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, Serial Ports, and Analog Peripherals are still active.) N ot R ec om m en de d fo r 1 Rev 1.1 99 C8051T610/1/2/3/4/5/6/7 19. Reset Sources es ig ns Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur:  CIP-51 halts program execution Special Function Registers (SFRs) are initialized to their defined reset values  External Port pins are forced to a known state  Interrupts and timers are disabled All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal data memory are unaffected during a reset; any previously stored data is preserved. However, since the stack pointer SFR is reset, the stack is effectively lost, even though the data on the stack is not altered. D  N ew The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled during and after the reset. For VDD Monitor and power-on resets, the RST pin is driven low until the device exits the reset state. fo r On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the internal oscillator. The Watchdog Timer is enabled with the system clock divided by 12 as its clock source. Program execution begins at location 0x0000. m en de d VDD Power On Reset Supply Monitor Px.x + - Comparator 0 om EN ec N ot R EXTCLK RST PCA WDT Reset Funnel (Software Reset) SWRSF Illegal EPROM Operation EN MCD Enable Low Frequency Oscillator External Oscillator Drive (wired-OR) C0RSEF Missing Clock Detector (oneshot) Internal Oscillator '0' Enable + - System Clock Clock Select WDT Enable Px.x CIP-51 Microcontroller Core System Reset Extended Interrupt Handler Figure 19.1. Reset Sources Rev 1.1 100 C8051T610/1/2/3/4/5/6/7 19.1. Power-On Reset es ig ns During power-up, the device is held in a reset state and the RST pin is driven low until VDD settles above VRST. A delay occurs before the device is released from reset; the delay decreases as the VDD ramp time increases (VDD ramp time is defined as how fast VDD ramps from 0 V to VRST). Figure 19.2. plots the power-on and VDD monitor event timing. The maximum VDD ramp time is 1 ms; slower ramp times may cause the device to be released from reset before VDD reaches the VRST level. For ramp times less than 1 ms, the power-on reset delay (TPORDelay) is typically less than 0.3 ms. Supply Voltage N ew D On exit from a power-on or VDD monitor reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other resets). Since all resets cause program execution to begin at the same location (0x0000) software can read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data memory should be assumed to be undefined after a power-on reset. The VDD monitor is enabled following a power-on reset. m en de d VD D fo r VRST VDD RST om Logic HIGH t TPORDelay N ot R ec Logic LOW 101 VDD Monitor Reset Power-On Reset Figure 19.2. Power-On and VDD Monitor Reset Timing Rev 1.1 C8051T610/1/2/3/4/5/6/7 19.2. Power-Fail Reset/VDD Monitor D es ig ns When a power-down transition or power irregularity causes VDD to drop below VRST, the power supply monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 19.2). When VDD returns to a level above VRST, the CIP-51 will be released from the reset state. Note that even though internal data memory contents are not altered by the power-fail reset, it is impossible to determine if VDD dropped below the level required for data retention. If the PORSF flag reads 1, the data may no longer be valid. The VDD monitor is enabled after power-on resets. Its defined state (enabled/disabled) is not altered by any other reset source. For example, if the VDD monitor is disabled by code and a software reset is performed, the VDD monitor will still be disabled after the reset. 1. Enable the VDD monitor (VDMEN bit in VDM0CN = 1). N ew Important Note: If the VDD monitor is being turned on from a disabled state, it should be enabled before it is selected as a reset source. Selecting the VDD monitor as a reset source before it is enabled and stabilized may cause a system reset. In some applications, this reset may be undesirable. If this is not desirable in the application, a delay should be introduced between enabling the monitor and selecting it as a reset source. The procedure for enabling the VDD monitor and configuring it as a reset source from a disabled state is shown below: fo r 2. If necessary, wait for the VDD monitor to stabilize (see Table 7.4 for the VDD Monitor turn-on time). 3. Select the VDD monitor as a reset source (PORSF bit in RSTSRC = 1). N ot R ec om m en de d See Figure 19.2 for VDD monitor timing; note that the power-on-reset delay is not incurred after a VDD monitor reset. See Table 7.4 for complete electrical characteristics of the VDD monitor. Rev 1.1 102 C8051T610/1/2/3/4/5/6/7 7 6 5 4 3 2 Name VDMEN VDDSTAT Type R/W R R R R R Reset Varies Varies 0 0 0 0 SFR Address = 0xFF Bit Name VDMEN VDD Monitor Enable. 0 R R 0 0 N ew 7 Function 1 D Bit es ig ns SFR Definition 19.1. VDM0CN: VDD Monitor Control VDDSTAT VDD Status. m en de d 6 fo r This bit turns the VDD monitor circuit on/off. The VDD Monitor cannot generate system resets until it is also selected as a reset source in register RSTSRC (SFR Definition 19.2). Selecting the VDD monitor as a reset source before it has stabilized may generate a system reset. In systems where this reset would be undesirable, a delay should be introduced between enabling the VDD Monitor and selecting it as a reset source. See Table 7.4 for the minimum VDD Monitor turn-on time. 0: VDD Monitor Disabled. 1: VDD Monitor Enabled. This bit indicates the current power supply status (VDD Monitor output). 0: VDD is at or below the VDD monitor threshold. 1: VDD is above the VDD monitor threshold. 5:0 Unused Unused. Read = 000000b; Write = Don’t care. 19.3. External Reset om The external RST pin provides a means for external circuitry to force the device into a reset state. Asserting an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST pin may be necessary to avoid erroneous noise-induced resets. See Table 7.4 for complete RST pin specifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset. ec 19.4. Missing Clock Detector Reset N ot R The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system clock remains high or low for more than the missing clock detector timeout, the one-shot will generate a reset. After a MCD reset, the MCDRSF flag (RSTSRC.2) will read 1, signifying the MCD as the reset source; otherwise, this bit reads 0. Writing a 1 to the MCDRSF bit enables the Missing Clock Detector; writing a 0 disables it. The state of the RST pin is unaffected by this reset. 103 Rev 1.1 C8051T610/1/2/3/4/5/6/7 19.5. Comparator0 Reset es ig ns Comparator0 can be configured as a reset source by writing a 1 to the C0RSEF flag (RSTSRC.5). Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-inverting input voltage (on CP0+) is less than the inverting input voltage (on CP0-), the device is put into the reset state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read 1 signifying Comparator0 as the reset source; otherwise, this bit reads 0. The state of the RST pin is unaffected by this reset. 19.6. PCA Watchdog Timer Reset N ew D The programmable watchdog timer (WDT) function of the programmable counter array (PCA) can be used to prevent software from running out of control during a system malfunction. The PCA WDT function can be enabled or disabled by software as described in Section “26.4. Watchdog Timer Mode” on page 200; the WDT is enabled and clocked by SYSCLK/12 following any reset. If a system malfunction prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is set to 1. The state of the RST pin is unaffected by this reset. 19.7. EPROM Error Reset fo r If an EPROM read or write targets an illegal address, a system reset is generated. This may occur due to any of the following:  m en de d Programming hardware attempts to write or read an EPROM location which is above the user code space address limit.  An EPROM read from firmware is attempted above user code space. This occurs when a MOVC operation is attempted above the user code space address limit.  A Program read is attempted above user code space. This occurs when user code attempts to branch to an address above the user code space address limit. The MEMERR bit (RSTSRC.6) is set following an EPROM error reset. The state of the RST pin is unaffected by this reset. 19.8. Software Reset N ot R ec om Software may force a reset by writing a 1 to the SWRSF bit (RSTSRC.4). The SWRSF bit will read 1 following a software forced reset. The state of the RST pin is unaffected by this reset. Rev 1.1 104 C8051T610/1/2/3/4/5/6/7 Bit 7 Name 6 5 4 3 2 MEMERR C0RSEF SWRSF WDTRSF 1 0 MCDRSF PORSF PINRSF R/W R Varies Varies R R R/W R/W R R/W Reset 0 Varies Varies Varies Varies Varies Unused Unused. Write Don’t care. Read 0 N ew 7 Description D Type SFR Address = 0xEF Bit Name es ig ns SFR Definition 19.2. RSTSRC: Reset Source MEMERR EPROM Error Reset Flag. N/A 5 C0RSEF Comparator0 Reset Enable and Flag. Writing a 1 enables Comparator0 as a reset source (active-low). Set to 1 if Comparator0 caused the last reset. 4 SWRSF Writing a 1 forces a system reset. Set to 1 if last reset was caused by a write to SWRSF. m en de d Software Reset Force and Flag. fo r 6 3 WDTRSF Watchdog Timer Reset Flag. N/A 2 MCDRSF Missing Clock Detector Enable and Flag. Writing a 1 enables the Power-On/VDD Monitor Reset Flag, and VDD monitor VDD monitor as a reset source. Reset Enable. Writing 1 to this bit before the VDD monitor is enabled and stabilized may cause a system reset. Set to 1 anytime a poweron or VDD monitor reset occurs. When set to 1 all other RSTSRC flags are indeterminate. HW Pin Reset Flag. Set to 1 if RST pin caused the last reset. om PORSF R PINRSF N/A N ot 0 Note: Do not use read-modify-write operations on this register 105 Set to 1 if Watchdog Timer overflow caused the last reset. Writing a 1 enables the Set to 1 if Missing Clock Missing Clock Detector. Detector timeout caused The MCD triggers a reset the last reset. if a missing clock condition is detected. ec 1 Set to 1 if EPROM read/write error caused the last reset. Rev 1.1 C8051T610/1/2/3/4/5/6/7 20. Oscillators and Clock Selection EXTCLK EN C Mode D OSC CLKSL0 XFCN2 XFCN1 XFCN0 XOSCMD2 XOSCMD1 XOSCMD0 OSCXCN CLKSEL Figure 20.1. Oscillator Options ec om CMOS Mode EXTCLK Input Circuit EXTCLK SYSCLK m en de d EXTCLK n fo r Programmable Internal Clock Generator N ew RC Mode VDD IFCN1 IFCN0 OSCICN IOSCEN IFRDY OSCICL es ig ns C8051T610/1/2/3/4/5/6/7 devices include a programmable internal high-frequency oscillator and an external oscillator drive circuit. The internal high-frequency oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as shown in Figure 20.1. The system clock can be sourced by the external oscillator circuit or the internal oscillator. The internal oscillator also offers a selectable postscaling feature. 20.1. System Clock Selection N ot R The CLKSL0 bit in register CLKSEL selects which oscillator source is used as the system clock. CLKSL0 must be set to 1 for the system clock to run from the external oscillator; however the external oscillator may still clock certain peripherals (timers, PCA) when the internal oscillator is selected as the system clock. The system clock may be switched on-the-fly between the internal oscillator and external oscillator, so long as the selected clock source is enabled and running. The internal high-frequency oscillator requires little start-up time and may be selected as the system clock immediately following the register write which enables the oscillator. The external RC and C modes also typically require no startup time. Rev 1.1 106 C8051T610/1/2/3/4/5/6/7 Bit 7 6 5 4 3 2 es ig ns SFR Definition 20.1. CLKSEL: Clock Select 1 0 CLKSL0 Type R R R R R R Reset 0 0 0 0 0 0 SFR Address = 0xA9 Bit Name Function Unused Unused. Read = 0000000b; Write = Don’t Care 0 CLKSL0 System Clock Source Select Bit. N ew 7:1 R R/W 0 0 D Name N ot R ec om m en de d fo r 0: SYSCLK derived from the Internal High-Frequency Oscillator and scaled per the IFCN bits in register OSCICN. 1: SYSCLK derived from the External Oscillator circuit. 107 Rev 1.1 C8051T610/1/2/3/4/5/6/7 20.2. Programmable Internal High-Frequency (H-F) Oscillator es ig ns All C8051T610/1/2/3/4/5/6/7 devices include a programmable internal high-frequency oscillator that defaults as the system clock after a system reset. The internal oscillator period can be adjusted via the OSCICL register as defined by SFR Definition 20.2. On C8051T610/1/2/3/4/5/6/7 devices, OSCICL is factory calibrated to obtain a 24.5 MHz base frequency. D The system clock may be derived from the programmed internal oscillator divided by 1, 2, 4, or 8, as defined by the IFCN bits in register OSCICN. The divide value defaults to 8 following a reset. Bit 7 6 5 4 3 2 1 0 Varies Varies Varies OSCICL[6:0] Name R Reset 0 R/W Varies Varies Varies Varies fo r Type SFR Address = 0xB3 Bit Name Function Unused Unused. Read = 0; Write = Don’t Care OSCICL[6:0] Internal Oscillator Calibration Bits. m en de d 7 6:0 N ew SFR Definition 20.2. OSCICL: Internal H-F Oscillator Calibration N ot R ec om These bits determine the internal oscillator period. When set to 0000000b, the H-F oscillator operates at its fastest setting. When set to 1111111b, the H-F oscillator operates at its slowest setting. The reset value is factory calibrated to generate an internal oscillator frequency of 24.5 MHz. Rev 1.1 108 C8051T610/1/2/3/4/5/6/7 Bit 7 6 5 4 Name IOSCEN IFRDY Type R/W R R R R R Reset 1 1 0 0 0 0 Internal H-F Oscillator Enable Bit. IFRDY R/W 0 Internal H-F Oscillator Frequency Ready Flag. Unused 1:0 IFCN[1:0] fo r 0: Internal H-F Oscillator is not running at programmed frequency. 1: Internal H-F Oscillator is running at programmed frequency. 5:2 Unused. Read = 0000b; Write = Don’t Care Internal H-F Oscillator Frequency Divider Control Bits. N ot R ec om m en de d 00: SYSCLK derived from Internal H-F Oscillator divided by 8. 01: SYSCLK derived from Internal H-F Oscillator divided by 4. 10: SYSCLK derived from Internal H-F Oscillator divided by 2. 11: SYSCLK derived from Internal H-F Oscillator divided by 1. 109 0 D Function 0: Internal H-F Oscillator Disabled. 1: Internal H-F Oscillator Enabled. 6 1 N ew IOSCEN 2 IFCN[1:0] SFR Address = 0xB2 Bit Name 7 3 es ig ns SFR Definition 20.3. OSCICN: Internal H-F Oscillator Control Rev 1.1 0 C8051T610/1/2/3/4/5/6/7 20.3. External Oscillator Drive Circuit es ig ns The external oscillator circuit may drive an external capacitor or RC network. A CMOS clock may also provide a clock input. In RC, capacitor, or CMOS clock configuration, the clock source should be wired to the EXTCLK pin as shown in Figure 20.1. The type of external oscillator must be selected in the OSCXCN register, and the frequency control bits (XFCN) must be selected appropriately (see SFR Definition 20.4). N ot R ec om m en de d fo r N ew D Important Note on External Oscillator Usage: Port pins must be configured when using the external oscillator circuit. When the external oscillator drive circuit is enabled in capacitor, RC, or CMOS clock mode, Port pin P0.3 is used as EXTCLK. The Port I/O Crossbar should be configured to skip the Port pin used by the oscillator circuit; see Section “21.3. Priority Crossbar Decoder” on page 117 for Crossbar configuration. Additionally, when using the external oscillator circuit in capacitor or RC mode, the associated Port pin should be configured as an analog input. In CMOS clock mode, the associated pin should be configured as a digital input. See Section “21.4. Port I/O Initialization” on page 121 for details on Port input mode selection. Rev 1.1 110 C8051T610/1/2/3/4/5/6/7 Bit 7 6 5 4 1 Reset 0 R/W 0 0 R 0 SFR Address = 0xB1 Bit Name Unused R/W 0 0 Function Read = 0b; Write = Don’t Care XOSCMD[2:0] External Oscillator Mode Select. 0 D R 2:0 XFCN[2:0] Read = 0b; Write = Don’t Care External Oscillator Frequency Control Bits. m en de d Unused fo r 00x: External Oscillator circuit off. 010: External CMOS Clock Mode. 011: External CMOS Clock Mode with divide by 2 stage. 100: RC Oscillator Mode with divide by 2 stage. 101: Capacitor Oscillator Mode with divide by 2 stage. 11x: Reserved. 3 Set according to the desired frequency range for RC mode. Set according to the desired K Factor for C mode. RC Mode C Mode 000 f ≤ 25 kHz K Factor = 0.87 001 25 kHz < f ≤ 50 kHz K Factor = 2.6 010 50 kHz < f ≤ 100 kHz K Factor = 7.7 011 100 kHz < f ≤ 200 kHz K Factor = 22 100 200 kHz < f ≤ 400 kHz K Factor = 65 101 400 kHz < f ≤ 800 kHz K Factor = 180 110 800 kHz < f ≤ 1.6 MHz K Factor = 664 111 1.6 MHz < f ≤ 3.2 MHz K Factor = 1590 R ec om XFCN N ot 111 0 XFCN[2:0] N ew Type 6:4 2 XOSCMD[2:0] Name 7 3 es ig ns SFR Definition 20.4. OSCXCN: External Oscillator Control Rev 1.1 0 C8051T610/1/2/3/4/5/6/7 20.3.1. External RC Example Equation 20.1. RC Mode Oscillator Frequency D 3 f = 1.23 × 10 ⁄ ( R × C ) es ig ns If an RC network is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 20.1, “RC Mode”. The capacitor should be no greater than 100 pF; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To determine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, first select the RC network value to produce the desired frequency of oscillation, according to Equation 20.1, where f = the frequency of oscillation in MHz, C = the capacitor value in pF, and R = the pull-up resistor value in kΩ. N ew For example: If the frequency desired is 100 kHz, let R = 246 kΩ and C = 50 pF: f = 1.23( 103 ) / RC = 1.23 ( 103 ) / [ 246 x 50 ] = 0.1 MHz = 100 kHz Referring to the table in SFR Definition 20.4, the required XFCN setting is 010b. 20.3.2. External Capacitor Example m en de d fo r If a capacitor is used as an external oscillator for the MCU, the circuit should be configured as shown in Figure 20.1, “C Mode”. The capacitor should be no greater than 100 pF; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To determine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, select the capacitor to be used and find the frequency of oscillation according to Equation 20.2, where f = the frequency of oscillation in MHz, C = the capacitor value in pF, and VDD = the MCU power supply in Volts. Equation 20.2. C Mode Oscillator Frequency f = ( KF ) ⁄ ( C × V DD ) For example: Assume VDD = 3.0 V and f = 150 kHz: om f = KF / (C x VDD) 0.150 MHz = KF / (C x 3.0) ec Since the frequency of roughly 150 kHz is desired, select the K Factor from the table in SFR Definition 20.4 (OSCXCN) as KF = 22: R 0.150 MHz = 22 / (C x 3.0) C x 3.0 = 22 / 0.150 MHz C = 146.6 / 3.0 pF = 48.8 pF N ot Therefore, the XFCN value to use in this example is 011b and C = 50 pF. Rev 1.1 112 C8051T610/1/2/3/4/5/6/7 21. Port Input/Output es ig ns Digital and analog resources are available through 29 I/O pins organized as three byte-wide ports and one 5-bit-wide port on the C8051T610/2/4. The C8051T611/3/5 devices have 25 I/O pins available, organized as three byte-wide ports and one 1-bit-wide port. The C8051T616/7 have 21 I/O pins available on a single byte-wide port, two 6-bit-wide ports, and a 1-bit-wide port. D Port pins can be defined as general-purpose I/O (GPIO), assigned to one of the internal digital resources, or assigned to an analog function as shown in Figure 21.3. Port pin P3.0 is shared with the C2 Interface Data signal (C2D). The designer has complete control over which functions are assigned, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder. Note that the state of a Port I/O pin can always be read in the corresponding Port latch, regardless of the Crossbar settings. N ew The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder (Figure 21.3, Figure 21.4, and Figure 21.5). The registers XBR0 and XBR1, defined in SFR Definition 21.1 and SFR Definition 21.2, are used to select internal digital functions. fo r All Port I/O pins are 5 V tolerant (refer to Figure 21.2 for the Port cell circuit). The Port I/O cells are configured as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1,2,3). Complete Electrical Specifications for Port I/O are given in Table 7.3 on page 33. m en de d XBR0, XBR1, PnSKIP Registers External Interrupts EX0 and EX1 PnMDOUT, PnMDIN Registers Priority Decoder Highest Priority UART (Internal Digital Signals) CP0, CP1 Outputs om ec P0.0 P1 I/O Cells P1.0 P2 I/O Cells P2.0 P3 I/O Cells P3.0 P0.7 Digital Crossbar 4 4 SYSCLK 6 T0, T1 4 P1.7 P2.7 2 8 P0 8 5 (P0.0-P0.7) P3.4 8 (Port Latches) R P0 I/O Cells 2 SMBus PCA N ot 8 4 SPI Lowest Priority 2 P1 (P1.0-P1.7) 4 (P2.0-P2.3) P2 To Analog Peripherals 4 (P2.4-P2.7) 5 P3 (P3.0-P3.4) Figure 21.1. Port I/O Functional Block Diagram Rev 1.1 113 C8051T610/1/2/3/4/5/6/7 21.1. Port I/O Modes of Operation es ig ns Port pins use the Port I/O cell shown in Figure 21.2. Each Port I/O cell can be configured by software for analog I/O or digital I/O using the PnMDIN registers. On reset, all Port I/O cells default to a high impedance state with weak pull-ups enabled until the Crossbar is enabled (XBARE = 1). 21.1.1. Port Pins Configured for Analog I/O D Any pins to be used as Comparator or ADC input, external oscillator input/output, or VREF should be configured for analog I/O (PnMDIN.n = 1). When a pin is configured for analog I/O, its weak pullup, digital driver, and digital receiver are disabled. Port pins configured for analog I/O will always read back a value of 0. N ew Configuring pins as analog I/O saves power and isolates the Port pin from digital interference. Port pins configured as digital inputs may still be used by analog peripherals; however, this practice is not recommended and may result in measurement errors. 21.1.2. Port Pins Configured For Digital I/O fo r Any pins to be used by digital peripherals (UART, SPI, SMBus, etc.), external digital event capture functions, or as GPIO should be configured as digital I/O (PnMDIN.n = 1). For digital I/O pins, one of two output modes (push-pull or open-drain) must be selected using the PnMDOUT registers. m en de d Push-pull outputs (PnMDOUT.n = 1) drive the Port pad to the VDD or GND supply rails based on the output logic value of the Port pin. Open-drain outputs have the high side driver disabled; therefore, they only drive the Port pad to GND when the output logic value is 0 and become high impedance inputs (both high low drivers turned off) when the output logic value is 1. N ot R ec om When a digital I/O cell is placed in the high impedance state, a weak pull-up transistor pulls the Port pad to the VDD supply voltage to ensure the digital input is at a defined logic state. Weak pull-ups are disabled when the I/O cell is driven to GND to minimize power consumption and may be globally disabled by setting WEAKPUD to 1. The user should ensure that digital I/O are always internally or externally pulled or driven to a valid logic state to minimize power consumption. Port pins configured for digital I/O always read back the logic state of the Port pad, regardless of the output logic value of the Port pin. 114 Rev 1.1 C8051T610/1/2/3/4/5/6/7 PxMDOUT.x (1 for push-pull) (0 for open-drain) VDD XBARE (Crossbar Enable) es ig ns WEAKPUD (Weak Pull-Up Disable) VDD (WEAK) PxMDIN.x (1 for digital) (0 for analog) To/From Analog Peripheral N ew GND D PORT PAD Px.x – Output Logic Value (Port Latch or Crossbar) Px.x – Input Logic Value (Reads 0 when pin is configured as an analog I/O) 21.1.3. Interfacing Port I/O to 5V Logic fo r Figure 21.2. Port I/O Cell Block Diagram m en de d All Port I/O configured for digital, open-drain operation are capable of interfacing to digital logic operating at a supply voltage higher than VDD and less than 5.25 V. An external pullup resistor to the higher supply voltage on output pins is typically required for most systems. N ot R ec om Important Notes: The absolute maximum voltage of any Port I/O pin should be limited to VDD + 3.6V. When interfacing to systems with supply voltages higher than 3.6V, care must be taken to limit the voltage on I/O pins when the VDD supply to the device is not present. In a multi-voltage interface, the external pullup resistor should be sized to allow a current of at least 150 µA to flow into the Port pin when the supply voltage is between (VDD + 0.6 V) and (VDD + 1.0 V). Once the Port pin voltage increases beyond this range, the current flowing into the Port pin is minimal. Rev 1.1 115 C8051T610/1/2/3/4/5/6/7 21.2. Assigning Port I/O Pins to Analog and Digital Functions es ig ns Port I/O pins can be assigned to various analog, digital, and external interrupt functions. The Port pins assigned to analog functions should be configured for analog I/O, and Port pins assigned to digital or external interrupt functions should be configured for digital I/O. 21.2.1. Assigning Port I/O Pins to Analog Functions D Table 21.1 shows all available analog functions that require Port I/O assignments. Port pins selected for these analog functions should have their corresponding bit in PnSKIP set to 1. This reserves the pin for use by the analog function and does not allow it to be claimed by the Crossbar. Table 21.1 shows the potential mapping of Port I/O to each analog function. Table 21.1. Port I/O Assignment for Analog Functions Potentially Assignable Port Pins SFR(s) used for Assignment P1.0–P3.4 AMX0P, PnSKIP P1.0–P2.7 CPT0MX, CPT1MX, PnSKIP P0.0 REF0CN, PnSKIP P0.3 OSCXCN, PnSKIP N ew Analog Function ADC Input Voltage Reference (VREF0) External Oscillator in RC or C Mode (EXTCLK) fo r Comparator Inputs m en de d 21.2.2. Assigning Port I/O Pins to Digital Functions Any Port pins not assigned to analog functions may be assigned to digital functions or used as GPIO. Most digital functions rely on the Crossbar for pin assignment; however, some digital functions bypass the Crossbar in a manner similar to the analog functions listed above. Port pins used by these digital functions and any Port pins selected for use as GPIO should have their corresponding bit in PnSKIP set to 1. Table 21.2 shows all available digital functions and the potential mapping of Port I/O to each digital function. Table 21.2. Port I/O Assignment for Digital Functions om Digital Function R ec UART0, SPI0, SMBus, CP0, CP0A, CP1, CP1A, SYSCLK, PCA0 (CEX0-4 and ECI), T0 or T1. Any Port pin available for assignment by the Crossbar. This includes P0.0 - P2.3 pins which have their PnSKIP bit set to 0. Note: The Crossbar will always assign UART0 pins to P0.4 and P0.5. P0.0–P3.4 N ot Any pin used for GPIO Potentially Assignable Port Pins 116 Rev 1.1 SFR(s) used for Assignment XBR0, XBR1 PnSKIP C8051T610/1/2/3/4/5/6/7 21.2.3. Assigning Port I/O Pins to INT0 or INT1 external interrupts es ig ns INT0 and INT1 can be used to trigger an interrupt on any Port 0 I/O pin. These functions do not require dedicated pins, meaning that they can function on both GPIO pins (PnSKIP = 1) and pins in use by the crossbar (PnSKIP = 0). INT0 and INT1 cannot be used on pins configured for analog I/O. Table 21.3 shows the available external digital event capture functions. Table 21.3. Port I/O Assignment for INT0 and INT1 Functions Potentially Assignable Port Pins P0.0–P0.7 External Interrupt 1 (INT1) P0.0–P0.7 IT01CF IT01CF N ew External Interrupt 0 (INT0) SFR(s) used for Assignment D Digital Function 21.3. Priority Crossbar Decoder fo r The Priority Crossbar Decoder (Figure 21.3) assigns a priority to each I/O function, starting at the top with UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that resource (excluding UART0, which is always at pins 4 and 5). If a Port pin is assigned, the Crossbar skips that pin when assigning the next selected resource. Additionally, the Crossbar will skip Port pins whose associated bits in the PnSKIP registers are set. The PnSKIP registers allow software to skip Port pins that are to be used for analog input, dedicated functions, or GPIO. m en de d Important Note on Crossbar Configuration: If a Port pin is claimed by a peripheral without use of the Crossbar, its corresponding PnSKIP bit should be set. This applies to P0.0 if VREF is used, P0.3 if the external oscillator circuit is enabled, P0.6 if the ADC is configured to use the external conversion start signal (CNVSTR), and any selected ADC or Comparator inputs. The Crossbar skips selected pins as if they were already assigned, and moves to the next unassigned pin. Figure 21.3 shows the potential pin assigments available to the crossbar peripherals. Figure 21.4 and Figure 21.5 show two example crossbar configurations, with and without skipping pins. om Registers XBR0 and XBR1 are used to assign the digital I/O resources to the physical I/O Port pins. Note that when a peripheral is selected, the crossbar assigns all pins for that peripheral. UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned to P0.4; UART RX0 is always assigned to P0.5. Standard Port I/Os appear contiguously after the prioritized functions have been assigned. N ot R ec Important Note: The SPI can be operated in either 3-wire or 4-wire modes, pending the state of the NSSMD1–NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not be routed to a Port pin. Rev 1.1 117 C8051T610/1/2/3/4/5/6/7 Port P0 P1 P2 es ig ns CNVSTR EXTCLK TX0 RX0 SCK D MISO N ew MOSI NSS* SDA SCL CP0 CP0A fo r CP1 CP1A CEX1 CEX2 CEX3 CEX4 ECI T0 T1 m en de d SYSCLK CEX0 x x om Pin Skip 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x Settings P0SKIP P1SKIP P2SKIP Signals Unavailable to Crossbar Special Function Signals VREF Pin Number 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Pins P0.0-P2.3 are capable of being assigned to crossbar peripherals. ec The crossbar peripherals are assigned in priority order from top to bottom, according to this diagram. R These boxes represent Port pins which can potentially be assigned to a peripheral. N ot Special Function Signals are not assigned by the crossbar. When these signals are enabled, the Crossbar should be manually configured to skip the corresponding port pins. Pins can be “skipped” by setting the corresponding bit in PnSKIP to ‘1’. * NSS is only pinned out when the SPI is in 4-wire mode. Figure 21.3. Priority Crossbar Decoder Potential Pin Assignments 118 Rev 1.1 C8051T610/1/2/3/4/5/6/7 es ig ns CNVSTR EXTCLK D TX0 RX0 SCK N ew MISO MOSI NSS* SDA SCL CP0 CEX2 CEX3 CEX4 ECI T0 T1 m en de d SYSCLK CEX0 CEX1 fo r CP0A CP1 CP1A Signals Unavailable to Crossbar Special Function Signals VREF Port P0 P1 P2 Pin Number 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 om Pin Skip 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x Settings P0SKIP P1SKIP P2SKIP ec In this example, the crossbar is configured to assign the UART TX0 and RX0 signals, the SMBus signals, and the SYSCLK signal. Note that the SMBus signals are assigned as a pair, and there are no pins skipped using the XBR0 register. N ot R These boxes represent the port pins which are used by the peripherals in this configuration. 1st TX0 is assigned to P0.4 2nd RX0 is assigned to P0.5 3rd SDA and SCL are assigned to P0.0 and P0.1, respectively. 4th SYSCLK is assigned to P0.2 All unassigned pins can be used as GPIO or for other non-crossbar functions. Figure 21.4. Priority Crossbar Decoder Example 1 - No Skipped Pins Rev 1.1 119 C8051T610/1/2/3/4/5/6/7 es ig ns EXTCLK P0.3 Skipped CNVSTR VREF Special Function Signals P0.0 Skipped Port P0 P1 P2 Pin Number 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 TX0 RX0 SCK CP0A CP1 CEX0 CEX1 CEX2 CEX3 CEX4 ECI T0 T1 m en de d CP1A SYSCLK fo r SCL CP0 N ew NSS* SDA x x om Pin Skip 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x Settings P0SKIP P1SKIP P2SKIP Signals Unavailable to Crossbar D MISO MOSI ec In this example, the crossbar is configured to assign the UART TX0 and RX0 signals, the SMBus signals, and the SYSCLK signal. Note that the SMBus signals are assigned as a pair. Additionally, pins P0.0 and P0.3 are configured to be skipped using the XBR0 register. N ot R These boxes represent the port pins which are used by the peripherals in this configuration. 1st TX0 is assigned to P0.4 2nd RX0 is assigned to P0.5 3rd SDA and SCL are assigned to P0.2 and P0.3, respectively. 4th SYSCLK is assigned to P0.6 All unassigned pins, including those skipped by XBR0 can be used as GPIO or for other noncrossbar functions. Figure 21.5. Priority Crossbar Decoder Example 2 - Skipping Pins 120 Rev 1.1 C8051T610/1/2/3/4/5/6/7 21.4. Port I/O Initialization Port I/O initialization consists of the following steps: es ig ns 1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN). 2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port Output Mode register (PnMDOUT). Pins used as input should be set to open-drain. 3. Select any pins to be skipped by the I/O Crossbar using the Port Skip registers (PnSKIP). 4. Assign Port pins to desired peripherals. D 5. Enable the Crossbar (XBARE = 1). N ew All Port pins must be configured as either analog or digital inputs. Any pins to be used as Comparator or ADC inputs should be configured as an analog inputs. When a pin is configured as an analog input, its weak pullup, digital driver, and digital receiver are disabled. This process saves power and reduces noise on the analog input. Pins configured as digital inputs may still be used by analog peripherals; however this practice is not recommended. fo r Additionally, all analog input pins should be configured to be skipped by the Crossbar (accomplished by setting the associated bits in PnSKIP). Port input mode is set in the PnMDIN register, where a 1 indicates a digital input, and a 0 indicates an analog input. All pins default to digital inputs on reset. See SFR Definition 21.4 for the PnMDIN register details. m en de d The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMDOUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is required even for the digital resources selected in the XBRn registers, and is not automatic. The only exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the PnMDOUT settings. When the WEAKPUD bit in XBR1 is 0, a weak pullup is enabled for all Port I/O configured as open-drain. WEAKPUD does not affect the push-pull Port I/O. Furthermore, the weak pullup is turned off on an output that is driving a 0 to avoid unnecessary power dissipation. om Registers XBR0 and XBR1 must be loaded with the appropriate values to select the digital I/O functions required by the design. Setting the XBARE bit in XBR1 to 1 enables the Crossbar. Until the Crossbar is enabled, the external pins remain as standard Port I/O (in input mode), regardless of the XBRn Register settings. For given XBRn Register settings, one can determine the I/O pin-out using the Priority Decode Table; as an alternative, the Configuration Wizard utility available at the Silicon Labs web site will determine the Port I/O pin-assignments based on the XBRn register settings. N ot R ec The Crossbar must be enabled to use Port pins as standard Port I/O in output mode. Port output drivers are disabled while the Crossbar is disabled. Rev 1.1 121 C8051T610/1/2/3/4/5/6/7 7 6 5 4 3 2 Name CP1AE CP1E CP0AE CP0E SYSCKE Type R/W R/W R/W R/W Reset 0 0 0 0 SFR Address = 0xE1 Bit Name CP1AE 0 SMB0E SPI0E URT0E R/W R/W R/W R/W 0 0 0 0 Function Comparator1 Asynchronous Output Enable. N ew 7 1 D Bit es ig ns SFR Definition 21.1. XBR0: Port I/O Crossbar Register 0 0: Asynchronous CP1 unavailable at Port pin. 1: Asynchronous CP1 routed to Port pin. 6 CP1E Comparator1 Output Enable. 5 CP0AE fo r 0: CP1 unavailable at Port pin. 1: CP1 routed to Port pin. Comparator0 Asynchronous Output Enable. 4 CP0E m en de d 0: Asynchronous CP0 unavailable at Port pin. 1: Asynchronous CP0 routed to Port pin. Comparator0 Output Enable. 0: CP0 unavailable at Port pin. 1: CP0 routed to Port pin. 3 SYSCKE /SYSCLK Output Enable. 0: /SYSCLK unavailable at Port pin. 1: /SYSCLK output routed to Port pin. 2 SMB0E SMBus I/O Enable. 1 om 0: SMBus I/O unavailable at Port pins. 1: SMBus I/O routed to Port pins. SPI0E SPI I/O Enable. ec 0: SPI I/O unavailable at Port pins. 1: SPI I/O routed to Port pins. Note that the SPI can be assigned either 3 or 4 GPIO pins. URT0E UART I/O Output Enable. 0: UART I/O unavailable at Port pin. 1: UART TX0, RX0 routed to Port pins P0.4 and P0.5. N ot R 0 122 Rev 1.1 C8051T610/1/2/3/4/5/6/7 7 Name WEAKPUD 6 5 4 3 XBARE T1E T0E ECIE 2 R/W R/W R/W R/W R/W R Reset 0 0 0 0 0 0 WEAKPUD Port I/O Weak Pullup Disable. R/W R/W 0 0 N ew 7 Function 0 PCA0ME[1:0] Type SFR Address = 0xE2 Bit Name 1 D Bit es ig ns SFR Definition 21.2. XBR1: Port I/O Crossbar Register 1 0: Weak Pullups enabled (except for Ports whose I/O are configured for analog mode). 1: Weak Pullups disabled. XBARE Crossbar Enable. 0: Crossbar disabled. 1: Crossbar enabled. 5 T1E T1 Enable. fo r 6 4 T0E m en de d 0: T1 unavailable at Port pin. 1: T1 routed to Port pin. T0 Enable. 0: T0 unavailable at Port pin. 1: T0 routed to Port pin. 3 ECIE PCA0 External Counter Input Enable. 0: ECI unavailable at Port pin. 1: ECI routed to Port pin. Unused Unused. Read = 0b; Write = Don’t Care. om 2 00: All PCA I/O unavailable at Port pins. 01: CEX0 routed to Port pin. 10: CEX0, CEX1 routed to Port pins. 11: CEX0, CEX1, CEX2 routed to Port pins. N ot R ec 1:0 PCA0ME[1:0] PCA Module I/O Enable Bits. Rev 1.1 123 C8051T610/1/2/3/4/5/6/7 21.5. Special Function Registers for Accessing and Configuring Port I/O es ig ns All Port I/O are accessed through corresponding special function registers (SFRs) that are both byte addressable and bit addressable. When writing to a Port, the value written to the SFR is latched to maintain the output data value at each pin. When reading, the logic levels of the Port's input pins are returned regardless of the XBRn settings (i.e., even when the pin is assigned to another signal by the Crossbar, the Port register can always read its corresponding Port I/O pin). The exception to this is the execution of the read-modify-write instructions that target a Port Latch register as the destination. The read-modify-write instructions when operating on a Port SFR are the following: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ and MOV, CLR or SETB, when the destination is an individual bit in a Port SFR. For these instructions, the value of the latch register (not the pin) is read, modified, and written back to the SFR. N ew D Each Port has a corresponding PnSKIP register which allows its individual Port pins to be assigned to digital functions or skipped by the Crossbar. All Port pins used for analog functions, GPIO, or dedicated digital functions such as the EMIF should have their PnSKIP bit set to 1. The Port input mode of the I/O pins is defined using the Port Input Mode registers (PnMDIN). Each Port cell can be configured for analog or digital I/O. This selection is required even for the digital resources selected in the XBRn registers, and is not automatic. m en de d fo r The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMDOUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is required even for the digital resources selected in the XBRn registers, and is not automatic. The only exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the PnMDOUT settings. SFR Definition 21.3. P0: Port 0 Bit 7 5 4 1 om 1 1 1 ec SFR Address = 0x80; Bit-Addressable Bit Name Description 1 0 1 1 1 1 R P0[7:0] Port 0 Data. Sets the Port latch logic value or reads the Port pin logic state in Port cells configured for digital I/O. Write 0: Set output latch to logic LOW. 1: Set output latch to logic HIGH. N ot 124 2 R/W Type 7:0 3 P0[7:0] Name Reset 6 Rev 1.1 Read 0: P0.n Port pin is logic LOW. 1: P0.n Port pin is logic HIGH. C8051T610/1/2/3/4/5/6/7 7 6 5 4 3 Name P0MDIN[7:0] Type R/W 1 Reset 1 1 1 1 SFR Address = 0xF1 Bit Name P0MDIN[7:0] 1 1 0 1 1 Function Analog Configuration Bits for P0.7–P0.0 (respectively). N ew 7:0 2 D Bit es ig ns SFR Definition 21.4. P0MDIN: Port 0 Input Mode fo r Port pins configured for analog mode have their weak pullup, digital driver, and digital receiver disabled. 0: Corresponding P0.n pin is configured for analog mode. 1: Corresponding P0.n pin is not configured for analog mode. SFR Definition 21.5. P0MDOUT: Port 0 Output Mode 7 6 5 4 m en de d Bit 3 2 1 0 0 0 0 P0MDOUT[7:0] Name R/W Type 0 Reset 0 0 0 SFR Address = 0xA4 Bit Name 0 Function om 7:0 P0MDOUT[7:0] Output Configuration Bits for P0.7–P0.0 (respectively). N ot R ec These bits are ignored if the corresponding bit in register P0MDIN is logic 0. 0: Corresponding P0.n pin is open-drain. 1: Corresponding P0.n pin is push-pull. Rev 1.1 125 C8051T610/1/2/3/4/5/6/7 7 6 5 4 3 Name P0SKIP[7:0] Type R/W 0 Reset 0 0 0 0 SFR Address = 0xD4 Bit Name P0SKIP[7:0] 0 1 0 0 0 Function Port 0 Crossbar Skip Enable Bits. N ew 7:0 2 D Bit es ig ns SFR Definition 21.6. P0SKIP: Port 0 Skip SFR Definition 21.7. P1: Port 1 7 6 5 4 m en de d Bit fo r These bits select Port 0 pins to be skipped by the Crossbar Decoder. Port pins used for analog, special functions or GPIO should be skipped by the Crossbar. 0: Corresponding P0.n pin is not skipped by the Crossbar. 1: Corresponding P0.n pin is skipped by the Crossbar. 2 1 0 1 1 1 1 P1[7:0] Name R/W Type 1 Reset 1 1 1 SFR Address = 0x90; Bit-Addressable Bit Name Description P1[7:0] Port 1 Data. om 7:0 3 0: Set output latch to logic LOW. 1: Set output latch to logic HIGH. ec Sets the Port latch logic value or reads the Port pin logic state in Port cells configured for digital I/O. Write Read 0: P1.n Port pin is logic LOW. 1: P1.n Port pin is logic HIGH. N ot R Note: P1.6 and P1.7 are not connected to external pins on the C8051T616/7 devices. 126 Rev 1.1 C8051T610/1/2/3/4/5/6/7 7 6 5 4 3 Name P1MDIN[7:0] Type R/W 1 Reset 1 1 1 1 SFR Address = 0xF2 Bit Name P1MDIN[7:0] 1 1 0 1 1 Function Analog Configuration Bits for P1.7–P1.0 (respectively). N ew 7:0 2 D Bit es ig ns SFR Definition 21.8. P1MDIN: Port 1 Input Mode Port pins configured for analog mode have their weak pullup, digital driver, and digital receiver disabled. 0: Corresponding P1.n pin is configured for analog mode. 1: Corresponding P1.n pin is not configured for analog mode. fo r Note: P1.6 and P1.7 are not connected to external pins on the C8051T616/7 devices. Bit 7 m en de d SFR Definition 21.9. P1MDOUT: Port 1 Output Mode 6 5 4 3 2 1 0 0 0 0 P1MDOUT[7:0] Name R/W Type 0 Reset 0 0 0 Function om SFR Address = 0xA5 Bit Name 0 ec 7:0 P1MDOUT[7:0] Output Configuration Bits for P1.7–P1.0 (respectively). These bits are ignored if the corresponding bit in register P1MDIN is logic 0. 0: Corresponding P1.n pin is open-drain. 1: Corresponding P1.n pin is push-pull. N ot R Note: P1.6 and P1.7 are not connected to external pins on the C8051T616/7 devices. Rev 1.1 127 C8051T610/1/2/3/4/5/6/7 7 6 5 4 3 Name P1SKIP[7:0] Type R/W 0 Reset 0 0 0 0 SFR Address = 0xD5 Bit Name P1SKIP[7:0] 0 1 0 0 0 Function Port 1 Crossbar Skip Enable Bits. N ew 7:0 2 D Bit es ig ns SFR Definition 21.10. P1SKIP: Port 1 Skip These bits select Port 1 pins to be skipped by the Crossbar Decoder. Port pins used for analog, special functions or GPIO should be skipped by the Crossbar. 0: Corresponding P1.n pin is not skipped by the Crossbar. 1: Corresponding P1.n pin is skipped by the Crossbar. fo r Note: P1.6 and P1.7 are not connected to external pins on the C8051T616/7 devices. When writing code for the C8051T616/7, P1SKIP[6:7] should be set to 11b to skip these two pins on the crossbar. Bit 7 m en de d SFR Definition 21.11. P2: Port 2 6 5 4 2 1 0 1 1 1 1 P2[7:0] Name R/W Type 1 Reset 1 1 1 om SFR Address = 0xA0; Bit-Addressable Bit Name Description 7:0 3 P2[7:0] Port 2 Data. ec Sets the Port latch logic value or reads the Port pin logic state in Port cells configured for digital I/O. Write 0: Set output latch to logic LOW. 1: Set output latch to logic HIGH. Read 0: P2.n Port pin is logic LOW. 1: P2.n Port pin is logic HIGH. N ot R Note: P2.6 and P2.7 are not connected to external pins on the C8051T616/7 devices. 128 Rev 1.1 C8051T610/1/2/3/4/5/6/7 7 6 5 4 3 Name P2MDIN[7:0] Type R/W 1 Reset 1 1 1 1 SFR Address = 0xF3 Bit Name P2MDIN[7:0] 1 1 0 1 1 Function Analog Configuration Bits for P2.7–P2.0 (respectively). N ew 7:0 2 D Bit es ig ns SFR Definition 21.12. P2MDIN: Port 2 Input Mode Port pins configured for analog mode have their weak pullup, digital driver, and digital receiver disabled. 0: Corresponding P2.n pin is configured for analog mode. 1: Corresponding P2.n pin is not configured for analog mode. fo r Note: P2.6 and P2.7 are not connected to external pins on the C8051T616/7 devices. Bit 7 m en de d SFR Definition 21.13. P2MDOUT: Port 2 Output Mode 6 5 4 3 2 1 0 0 0 0 P2MDOUT[7:0] Name R/W Type 0 Reset 0 0 0 Function om SFR Address = 0xA6 Bit Name 0 7:0 P2MDOUT[7:0] Output Configuration Bits for P2.7–P2.0 (respectively). ec 0: Corresponding P2.n pin is open-drain. 1: Corresponding P2.n pin is push-pull. N ot R Note: P2.6 and P2.7 are not connected to external pins on the C8051T616/7 devices. Rev 1.1 129 C8051T610/1/2/3/4/5/6/7 Bit 7 6 5 4 3 2 Name es ig ns SFR Definition 21.14. P2SKIP: Port 2 Skip 1 0 P2SKIP[3:0] R 0 0 0 0 SFR Address = 0xD6 Bit Name 7:4 Unused 3:0 P2SKIP[3:0] 0 0 0 0 Function Unused. Read = 0000b; Write = Don’t Care. N ew Reset R/W D Type Port 2 Crossbar Skip Enable Bits. fo r These bits select Port 2 pins to be skipped by the Crossbar Decoder. Port pins used for analog, special functions or GPIO should be skipped by the Crossbar. 0: Corresponding P2.n pin is not skipped by the Crossbar. 1: Corresponding P2.n pin is skipped by the Crossbar. Note: Only P2.0-P2.3 are associated with the crossbar. Bit 7 Name Type R Reset 0 m en de d SFR Definition 21.15. P3: Port 3 6 5 R R 0 0 4 1 Unused. Read = 000b; Write = Don’t Care. 4:0 P3[4:0] Port 3 Data. ec 1 Write Unused R 1 0 1 1 R/W 7:5 Sets the Port latch logic value or reads the Port pin logic state in Port cells configured for digital I/O. 2 P3[4:0] 1 SFR Address = 0xB0; Bit-Addressable Bit Name Description om 3 0: Set output latch to logic LOW. 1: Set output latch to logic HIGH. Read 0: P3.n Port pin is logic LOW. 1: P3.n Port pin is logic HIGH. N ot Note: P3.1-P3.4 are not connected to external pins on the C8051T611/3/5 and C8051T616/7 devices. 130 Rev 1.1 C8051T610/1/2/3/4/5/6/7 Bit 7 6 5 4 3 2 Name P3MDIN[4:0] Type R/W 0 0 1 SFR Address = 0xF4 Bit Name Unused 4:0 P3MDIN[4:0] 1 0 1 1 Function Unused. Read = 000b; Write = Don’t Care. N ew 7:5 1 1 D 0 Reset es ig ns SFR Definition 21.16. P3MDIN: Port 3 Input Mode Analog Configuration Bits for P3.4–P3.0 (respectively). fo r Port pins configured for analog mode have their weak pullup, digital driver, and digital receiver disabled. 0: Corresponding P3.n pin is configured for analog mode. 1: Corresponding P3.n pin is not configured for analog mode. Note: P3.1-P3.4 are not connected to external pins on the C8051T611/3/5 and C8051T616/7 devices. Bit 7 Name Type 0 Reset m en de d SFR Definition 21.17. P3MDOUT: Port 3 Output Mode 6 0 5 0 4 0 om SFR Address = 0xA7 Bit Name 3 2 1 0 0 0 P3MDOUT[4:0] R/W 0 0 Function ec 7:5 Unused Unused. Read = 000b; Write = Don’t Care. 4:0 P3MDOUT[4:0] Output Configuration Bits for P3.4–P3.0 (respectively). 0: Corresponding P3.n pin is open-drain. 1: Corresponding P3.n pin is push-pull. N ot R Note: P3.1-P3.4 are not connected to external pins on the C8051T611/3/5 and C8051T616/7 devices. Rev 1.1 131 C8051T610/1/2/3/4/5/6/7 22. SMBus es ig ns The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specification, version 1.1, and compatible with the I2C serial bus. Reads and writes to the interface by the system controller are byte oriented with the SMBus interface autonomously controlling the serial transfer of the data. Data can be transferred at up to 1/20th of the system clock as a master or slave (this can be faster than allowed by the SMBus specification, depending on the system clock used). A method of extending the clock-low duration is available to accommodate devices with different speed capabilities on the same bus. fo r SMB0CF E I B E S S S S N N U XMMMM S H S T B B B B M Y H T F C C B OO T S S L E E 1 0 D 00 T0 Overflow 01 T1 Overflow 10 TMR2H Overflow 11 TMR2L Overflow m en de d SMB0CN M T S S A A A S A X T T C RC I SMAOK B K T O R L E D QO R E S T N ew D The SMBus interface may operate as a master and/or slave, and may function on a bus with multiple masters. The SMBus provides control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration logic, and START/STOP control and generation. A block diagram of the SMBus peripheral and the associated SFRs is shown in Figure 22.1. SMBUS CONTROL LOGIC Arbitration SCL Synchronization SCL Generation (Master Mode) SDA Control IRQ Generation Data Path Control C R O S S B A R N SDA Control SMB0DAT 7 6 5 4 3 2 1 0 Port I/O SDA FILTER N R N ot SCL FILTER SCL Control ec om Interrupt Request Figure 22.1. SMBus Block Diagram Rev 1.1 132 C8051T610/1/2/3/4/5/6/7 22.1. Supporting Documents 1. The I2C-Bus and How to Use It (including specifications), Philips Semiconductor. 2. The I2C-Bus Specification—Version 2.0, Philips Semiconductor. 3. System Management Bus Specification—Version 1.1, SBS Implementers Forum. 22.2. SMBus Configuration es ig ns It is assumed the reader is familiar with or has access to the following supporting documents: VDD = 3V Slave Device 1 m en de d Master Device VDD = 5V fo r VDD = 5V N ew D Figure 22.2 shows a typical SMBus configuration. The SMBus specification allows any recessive voltage between 3.0 V and 5.0 V; different devices on the bus may operate at different voltage levels. The bi-directional SCL (serial clock) and SDA (serial data) lines must be connected to a positive power supply voltage through a pullup resistor or similar circuit. Every device connected to the bus must have an open-drain or open-collector output for both the SCL and SDA lines, so that both are pulled high (recessive state) when the bus is free. The maximum number of devices on the bus is limited only by the requirement that the rise and fall times on the bus not exceed 300 ns and 1000 ns, respectively. VDD = 3V Slave Device 2 SDA SCL Figure 22.2. Typical SMBus Configuration om 22.3. SMBus Operation R ec Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver (WRITE), and data transfers from an addressed slave transmitter to a master receiver (READ). The master device initiates both types of data transfers and provides the serial clock pulses on SCL. The SMBus interface may operate as a master or a slave, and multiple master devices on the same bus are supported. If two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme is employed with a single master always winning the arbitration. Note that it is not necessary to specify one device as the Master in a system; any device who transmits a START and a slave address becomes the master for the duration of that transfer. N ot A typical SMBus transaction consists of a START condition followed by an address byte (Bits7–1: 7-bit slave address; Bit0: R/W direction bit), one or more bytes of data, and a STOP condition. Bytes that are received (by a master or slave) are acknowledged (ACK) with a low SDA during a high SCL (see Figure 22.3). If the receiving device does not ACK, the transmitting device will read a NACK (not acknowledge), which is a high SDA during a high SCL. The direction bit (R/W) occupies the least-significant bit position of the address byte. The direction bit is set to logic 1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation. 133 Rev 1.1 C8051T610/1/2/3/4/5/6/7 SCL SDA START SLA5-0 Slave Address + R/W R/W D7 ACK D6-0 N ew SLA6 D es ig ns All transactions are initiated by a master, with one or more addressed slave devices as the target. The master generates the START condition and then transmits the slave address and direction bit. If the transaction is a WRITE operation from the master to the slave, the master transmits the data a byte at a time waiting for an ACK from the slave at the end of each byte. For READ operations, the slave transmits the data waiting for an ACK from the master at the end of each byte. At the end of the data transfer, the master generates a STOP condition to terminate the transaction and free the bus. Figure 22.3 illustrates a typical SMBus transaction. Data Byte NACK STOP Figure 22.3. SMBus Transaction fo r 22.3.1. Transmitter Vs. Receiver 22.3.2. Arbitration m en de d On the SMBus communications interface, a device is the “transmitter” when it is sending an address or data byte to another device on the bus. A device is a “receiver” when an address or data byte is being sent to it from another device on the bus. The transmitter controls the SDA line during the address or data byte. After each byte of address or data information is sent by the transmitter, the receiver sends an ACK or NACK bit during the ACK phase of the transfer, during which time the receiver controls the SDA line. om A master may start a transfer only if the bus is free. The bus is free after a STOP condition or after the SCL and SDA lines remain high for a specified time (see Section “22.3.5. SCL High (SMBus Free) Timeout” on page 135). In the event that two or more devices attempt to begin a transfer at the same time, an arbitration scheme is employed to force one master to give up the bus. The master devices continue transmitting until one attempts a HIGH while the other transmits a LOW. Since the bus is open-drain, the bus will be pulled LOW. The master attempting the HIGH will detect a LOW SDA and lose the arbitration. The winning master continues its transmission without interruption; the losing master becomes a slave and receives the rest of the transfer if addressed. This arbitration scheme is non-destructive: one device always wins, and no data is lost. ec 22.3.3. Clock Low Extension R SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line LOW to extend the clock low period, effectively decreasing the serial clock frequency. N ot 22.3.4. SCL Low Timeout If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore, the master cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than 25 ms as a “timeout” condition. Devices that have detected the timeout condition must reset the communication no later than 10 ms after detecting the timeout condition. Rev 1.1 134 C8051T610/1/2/3/4/5/6/7 es ig ns When the SMBTOE bit in SMB0CF is set, Timer 3 is used to detect SCL low timeouts. Timer 3 is forced to reload when SCL is high, and allowed to count when SCL is low. With Timer 3 enabled and configured to overflow after 25 ms (and SMBTOE set), the Timer 3 interrupt service routine can be used to reset (disable and re-enable) the SMBus in the event of an SCL low timeout. 22.3.5. SCL High (SMBus Free) Timeout D The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 µs, the bus is designated as free. When the SMBFTE bit in SMB0CF is set, the bus will be considered free if SCL and SDA remain high for more than 10 SMBus clock source periods (as defined by the timer configured for the SMBus clock source). If the SMBus is waiting to generate a Master START, the START will be generated following this timeout. A clock source is required for free timeout detection, even in a slave-only implementation. N ew 22.4. Using the SMBus The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting control for serial transfers; higher level protocol is determined by user software. The SMBus interface provides the following application-independent features:      Byte-wise serial data transfers Clock signal generation on SCL (Master Mode only) and SDA data synchronization Timeout/bus error recognition, as defined by the SMB0CF configuration register START/STOP timing, detection, and generation Bus arbitration Interrupt generation Status information fo r  m en de d  SMBus interrupts are generated for each data byte or slave address that is transferred. When a transmitter (i.e., sending address/data, receiving an ACK), this interrupt is generated after the ACK cycle so that software may read the received ACK value; when receiving data (i.e., receiving address/data, sending an ACK), this interrupt is generated before the ACK cycle so that software may define the outgoing ACK value. See Section 22.5 for more details on transmission sequences. om Interrupts are also generated to indicate the beginning of a transfer when a master (START generated), or the end of a transfer when a slave (STOP detected). Software should read the SMB0CN (SMBus Control register) to find the cause of the SMBus interrupt. The SMB0CN register is described in Section 22.4.2; Table 22.4 provides a quick SMB0CN decoding reference. ec 22.4.1. SMBus Configuration Register N ot R The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes, select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the INH bit. With slave events inhibited, the SMBus interface will still monitor the SCL and SDA pins; however, the interface will NACK all received addresses and will not generate any slave interrupts. When the INH bit is set, all slave events will be inhibited following the next START (interrupts will continue for the duration of the current transfer). 135 Rev 1.1 C8051T610/1/2/3/4/5/6/7 SMBCS1 SMBCS0 SMBus Clock Source 0 0 1 1 0 1 0 1 Timer 0 Overflow Timer 1 Overflow Timer 2 High Byte Overflow Timer 2 Low Byte Overflow es ig ns Table 22.1. SMBus Clock Source Selection N ew D The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or when the Free Timeout detection is enabled. When operating as a master, overflows from the selected source determine the absolute minimum SCL low and high times as defined in Equation 22.1. Note that the selected clock source may be shared by other peripherals so long as the timer is left running at all times. For example, Timer 1 overflows may generate the SMBus and UART baud rates simultaneously. Timer configuration is covered in Section “25. Timers” on page 170. 1 T HighMin = T LowMin = ---------------------------------------------f ClockSourceOverflow fo r Equation 22.1. Minimum SCL High and Low Times m en de d The selected clock source should be configured to establish the minimum SCL High and Low times as per Equation 22.1. When the interface is operating as a master (and SCL is not driven or extended by any other devices on the bus), the typical SMBus bit rate is approximated by Equation 22.2. f ClockSourceOverflow BitRate = ---------------------------------------------3 Equation 22.2. Typical SMBus Bit Rate ec om Figure 22.4 shows the typical SCL generation described by Equation 22.2. Notice that THIGH is typically twice as large as TLOW. The actual SCL output may vary due to other devices on the bus (SCL may be extended low by slower slave devices, or driven low by contending master devices). The bit rate when operating as a master will never exceed the limits defined by equation Equation 22.1. R Timer Source Overflows N ot SCL TLow SCL High Timeout THigh Figure 22.4. Typical SMBus SCL Generation Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA setup time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high. The minimum SDA hold time defines the absolute minimum time that the current SDA value remains stable Rev 1.1 136 C8051T610/1/2/3/4/5/6/7 Table 22.2. Minimum SDA Setup and Hold Times Minimum SDA Setup Time Tlow – 4 system clocks or 1 system clock + s/w delay* 11 system clocks 0 1 Minimum SDA Hold Time 3 system clocks 12 system clocks D EXTHOLD es ig ns after SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 22.2 shows the minimum setup and hold times for the two EXTHOLD settings. Setup and hold time extensions are typically necessary when SYSCLK is above 10 MHz. N ew Note: Setup Time for ACK bit transmissions and the MSB of all data transfers. When using software acknowledgement, the s/w delay occurs between the time SMB0DAT or ACK is written and when SI is cleared. Note that if SI is cleared in the same write that defines the outgoing ACK value, s/w delay is zero. fo r With the SMBTOE bit set, Timer 3 should be configured to overflow after 25 ms in order to detect SCL low timeouts (see Section “22.3.4. SCL Low Timeout” on page 134). The SMBus interface will force Timer 3 to reload while SCL is high, and allow Timer 3 to count when SCL is low. The Timer 3 interrupt service routine should be used to reset SMBus communication by disabling and re-enabling the SMBus. N ot R ec om m en de d SMBus Free Timeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see Figure 22.4). 137 Rev 1.1 C8051T610/1/2/3/4/5/6/7 Bit 7 6 5 Name ENSMB INH BUSY Type R/W R/W R R/W R/W R/W Reset 0 0 0 0 0 0 EXTHOLD SMBTOE SFR Address = 0xC1 Bit Name ENSMB 2 1 SMBFTE Function SMBus Enable. 0 SMBCS[1:0] R/W 0 0 N ew 7 3 D 4 es ig ns SFR Definition 22.1. SMB0CF: SMBus Clock/Configuration This bit enables the SMBus interface when set to 1. When enabled, the interface constantly monitors the SDA and SCL pins. 6 INH SMBus Slave Inhibit. 5 BUSY SMBus Busy Indicator. fo r When this bit is set to logic 1, the SMBus does not generate an interrupt when slave events occur. This effectively removes the SMBus slave from the bus. Master Mode interrupts are not affected. 4 EXTHOLD m en de d This bit is set to logic 1 by hardware when a transfer is in progress. It is cleared to logic 0 when a STOP or free-timeout is sensed. SMBus Setup and Hold Time Extension Enable. This bit controls the SDA setup and hold times according to Table 22.2. 0: SDA Extended Setup and Hold Times disabled. 1: SDA Extended Setup and Hold Times enabled. 3 SMBTOE SMBus SCL Timeout Detection Enable. SMBFTE ec 2 om This bit enables SCL low timeout detection. If set to logic 1, the SMBus forces Timer 3 to reload while SCL is high and allows Timer 3 to count when SCL goes low. If Timer 3 is configured to Split Mode, only the High Byte of the timer is held in reload while SCL is high. Timer 3 should be programmed to generate interrupts at 25 ms, and the Timer 3 interrupt service routine should reset SMBus communication. SMBus Free Timeout Detection Enable. When this bit is set to logic 1, the bus will be considered free if SCL and SDA remain high for more than 10 SMBus clock source periods. N ot R 1:0 SMBCS[1:0] SMBus Clock Source Selection. These two bits select the SMBus clock source, which is used to generate the SMBus bit rate. The selected device should be configured according to Equation 22.1. 00: Timer 0 Overflow 01: Timer 1 Overflow 10: Timer 2 High Byte Overflow 11: Timer 2 Low Byte Overflow Rev 1.1 138 C8051T610/1/2/3/4/5/6/7 22.4.2. SMB0CN Control Register es ig ns SMB0CN is used to control the interface and to provide status information (see SFR Definition 22.2). The higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to jump to service routines. MASTER indicates whether a device is the master or slave during the current transfer. TXMODE indicates whether the device is transmitting or receiving data for the current byte. D STA and STO indicate that a START and/or STOP has been detected or generated since the last SMBus interrupt. STA and STO are also used to generate START and STOP conditions when operating as a master. Writing a 1 to STA will cause the SMBus interface to enter Master Mode and generate a START when the bus becomes free (STA is not cleared by hardware after the START is generated). Writing a 1 to STO while in Master Mode will cause the interface to generate a STOP and end the current transfer after the next ACK cycle. If STO and STA are both set (while in Master Mode), a STOP followed by a START will be generated. fo r N ew As a receiver, writing the ACK bit defines the outgoing ACK value; as a transmitter, reading the ACK bit indicates the value received on the last ACK cycle. ACKRQ is set each time a byte is received, indicating that an outgoing ACK value is needed. When ACKRQ is set, software should write the desired outgoing value to the ACK bit before clearing SI. A NACK will be generated if software does not write the ACK bit before clearing SI. SDA will reflect the defined ACK value immediately following a write to the ACK bit; however SCL will remain low until SI is cleared. If a received slave address is not acknowledged, further slave events will be ignored until the next START is detected. m en de d The ARBLOST bit indicates that the interface has lost an arbitration. This may occur anytime the interface is transmitting (master or slave). A lost arbitration while operating as a slave indicates a bus error condition. ARBLOST is cleared by hardware each time SI is cleared. The SI bit (SMBus Interrupt Flag) is set at the beginning and end of each transfer, after each byte frame, or when an arbitration is lost; see Table 22.3 for more details. Important Note About the SI Bit: The SMBus interface is stalled while SI is set; thus SCL is held low, and the bus is stalled until software clears SI. N ot R ec om Table 22.3 lists all sources for hardware changes to the SMB0CN bits. Refer to Table 22.4 for SMBus status decoding using the SMB0CN register. 139 Rev 1.1 C8051T610/1/2/3/4/5/6/7 7 6 5 4 3 2 Name MASTER TXMODE STA STO ACKRQ ARBLOST Type R R R/W R/W R R Reset 0 0 0 0 0 0 SFR Address = 0xC0; Bit-Addressable Bit Name Description Read 1 0 ACK SI R/W R/W 0 0 D Bit es ig ns SFR Definition 22.2. SMB0CN: SMBus Control Write MASTER SMBus Master/Slave Indicator. This read-only bit indicates when the SMBus is operating as a master. 0: SMBus operating in slave mode. 1: SMBus operating in master mode. N/A 6 TXMODE SMBus Transmit Mode Indicator. This read-only bit indicates when the SMBus is operating as a transmitter. 0: SMBus in Receiver Mode. 1: SMBus in Transmitter Mode. N/A 0: No Start or repeated Start detected. 1: Start or repeated Start detected. 0: No Start generated. 1: When Configured as a Master, initiates a START or repeated START. 0: No Stop condition detected. 1: Stop condition detected (if in Slave Mode) or pending (if in Master Mode). 0: No STOP condition is transmitted. 1: When configured as a Master, causes a STOP condition to be transmitted after the next ACK cycle. Cleared by Hardware. 0: No Ack requested 1: ACK requested N/A 0: No arbitration error. 1: Arbitration Lost N/A 0: NACK received. 1: ACK received. 0: Send NACK 1: Send ACK SMBus Start Flag. 4 STO SMBus Stop Flag. 3 ACKRQ om SMBus Acknowledge Request. ARBLOST SMBus Arbitration Lost Indicator. ec 2 ACK R 1 N ot 0 SI fo r STA m en de d 5 N ew 7 SMBus Acknowledge. SMBus Interrupt Flag. 0: No interrupt pending This bit is set by hardware 1: Interrupt Pending under the conditions listed in Table 15.3. SI must be cleared by software. While SI is set, SCL is held low and the SMBus is stalled. Rev 1.1 0: Clear interrupt, and initiate next state machine event. 1: Force interrupt. 140 C8051T610/1/2/3/4/5/6/7 Table 22.3. Sources for Hardware Changes to SMB0CN Set by Hardware When: TXMODE STA  A START is generated.   START is generated. SMB0DAT is written before the start of an SMBus frame.  A START followed by an address byte is received.  Must be cleared by software. A STOP is detected while addressed as a slave.  Arbitration is lost due to a detected STOP.  A pending STOP is generated.   After each ACK cycle. A repeated START is detected as a MASTER when STA is low (unwanted repeated START).  SCL is sensed low while attempting to generate a STOP or repeated START condition.  SDA is sensed low while transmitting a 1 (excluding ACK bits).  Each time SI is cleared.  The incoming ACK value is low (ACKNOWLEDGE).  The incoming ACK value is high (NOT ACKNOWLEDGE).  A START has been generated. Lost arbitration. A byte has been transmitted and an ACK/NACK received. A byte has been received. A START or repeated START followed by a slave address + R/W has been received. A STOP has been received.  Must be cleared by software.   A STOP is generated.  Arbitration is lost. STO ACKRQ A byte has been received and an ACK response value is needed (only when hardware ACK is not enabled). ACK  SI om  m en de d ARBLOST fo r   ec  N ot R  141 N ew  A START is detected. Arbitration is lost.  SMB0DAT is not written before the start of an SMBus frame.  D MASTER Cleared by Hardware When: es ig ns Bit Rev 1.1 C8051T610/1/2/3/4/5/6/7 22.4.3. Data Register es ig ns The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software may safely read or write to the data register when the SI flag is set. Software should not attempt to access the SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic 0, as the interface may be in the process of shifting a byte of data into or out of the register. SFR Definition 22.3. SMB0DAT: SMBus Data Bit 7 6 5 4 N ew D Data in SMB0DAT is always shifted out MSB first. After a byte has been received, the first bit of received data is located at the MSB of SMB0DAT. While data is being shifted out, data on the bus is simultaneously being shifted in. SMB0DAT always contains the last data byte present on the bus. In the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data or address in SMB0DAT. 3 SMB0DAT[7:0] Type R/W 0 Reset 0 0 m en de d SFR Address = 0xC2 Bit Name 0 fo r Name 0 2 1 0 0 0 0 Function 7:0 SMB0DAT[7:0] SMBus Data. N ot R ec om The SMB0DAT register contains a byte of data to be transmitted on the SMBus serial interface or a byte that has just been received on the SMBus serial interface. The CPU can read from or write to this register whenever the SI serial interrupt flag (SMB0CN.0) is set to logic 1. The serial data in the register remains stable as long as the SI flag is set. When the SI flag is not set, the system may be in the process of shifting data in/out and the CPU should not attempt to access this register. Rev 1.1 142 C8051T610/1/2/3/4/5/6/7 22.5. SMBus Transfer Modes es ig ns The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or Slave Receiver. The SMBus interface enters Master Mode any time a START is generated, and remains in Master Mode until it loses an arbitration or generates a STOP. An SMBus interrupt is generated at the end of all SMBus byte frames. As a receiver, the interrupt for an ACK occurs before the ACK. As a transmitter, interrupts occur after the ACK. 22.5.1. Write Sequence (Master) SLA W A Data Byte m en de d S fo r N ew D During a write sequence, an SMBus master writes data to a slave device. The master in this transfer will be a transmitter during the address byte, and a transmitter during all data bytes. The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the data direction bit. In this case the data direction bit (R/W) will be logic 0 (WRITE). The master then transmits one or more bytes of serial data. After each byte is transmitted, an acknowledge bit is generated by the slave. The transfer is ended when the STO bit is set and a STOP is generated. Note that the interface will switch to Master Receiver Mode if SMB0DAT is not written following a Master Transmitter interrupt. Figure 22.5 shows a typical master write sequence. Two transmit data bytes are shown, though any number of bytes may be transmitted. Notice that all of the “data byte transferred” interrupts occur after the ACK cycle in this mode. A Data Byte A Interrupt Locations Received by SMBus Interface om Transmitted by SMBus Interface S = START P = STOP A = ACK W = WRITE SLA = Slave Address N ot R ec Figure 22.5. Typical Master Write Sequence 143 Rev 1.1 P C8051T610/1/2/3/4/5/6/7 22.5.2. Read Sequence (Master) es ig ns During a read sequence, an SMBus master reads data from a slave device. The master in this transfer will be a transmitter during the address byte, and a receiver during all data bytes. The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the data direction bit. In this case the data direction bit (R/W) will be logic 1 (READ). Serial data is then received from the slave on SDA while the SMBus outputs the serial clock. The slave transmits one or more bytes of serial data. The ACKRQ bit is set to 1 and an interrupt is generated after each received byte. Software must write the ACK bit at that time to ACK or NACK the received byte. S SLA R A fo r N ew D Writing a 1 to the ACK bit generates an ACK; writing a 0 generates a NACK. Software should write a 0 to the ACK bit for the last data transfer, to transmit a NACK. The interface exits Master Receiver Mode after the STO bit is set and a STOP is generated. The interface will switch to Master Transmitter Mode if SMB0DAT is written while an active Master Receiver. Figure 22.6 shows a typical master read sequence. Two received data bytes are shown, though any number of bytes may be received. Notice that the ‘data byte transferred’ interrupts occur before the ACK. Data Byte A Data Byte N P m en de d Interrupt Locations Received by SMBus Interface Transmitted by SMBus Interface S = START P = STOP A = ACK N = NACK R = READ SLA = Slave Address N ot R ec om Figure 22.6. Typical Master Read Sequence Rev 1.1 144 C8051T610/1/2/3/4/5/6/7 22.5.3. Write Sequence (Slave) es ig ns During a write sequence, an SMBus master writes data to a slave device. The slave in this transfer will be a receiver during the address byte, and a receiver during all data bytes. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode when a START followed by a slave address and direction bit (WRITE in this case) is received. Upon entering Slave Receiver Mode, an interrupt is generated and the ACKRQ bit is set. The software must respond to the received slave address with an ACK, or ignore the received slave address with a NACK. D If the received slave address is ignored by software (by NACKing the address), slave interrupts will be inhibited until the next START is detected. If the received slave address is acknowledged, zero or more data bytes are received. N ew The ACKRQ bit is set to 1 and an interrupt is generated after each received byte. Software must write the ACK bit at that time to ACK or NACK the received byte. SLA W A Data Byte A m en de d S fo r The interface exits Slave Receiver Mode after receiving a STOP. Note that the interface will switch to Slave Transmitter Mode if SMB0DAT is written while an active Slave Receiver. Figure 22.7 shows a typical slave write sequence. Two received data bytes are shown, though any number of bytes may be received. Notice that the ‘data byte transferred’ interrupts occur before the ACK. Data Byte A Interrupt Locations Received by SMBus Interface om Transmitted by SMBus Interface S = START P = STOP A = ACK W = WRITE SLA = Slave Address N ot R ec Figure 22.7. Typical Slave Write Sequence 145 Rev 1.1 P C8051T610/1/2/3/4/5/6/7 22.5.4. Read Sequence (Slave) es ig ns During a read sequence, an SMBus master reads data from a slave device. The slave in this transfer will be a receiver during the address byte, and a transmitter during all data bytes. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START followed by a slave address and direction bit (READ in this case) is received. Upon entering Slave Receiver Mode, an interrupt is generated and the ACKRQ bit is set. The software must respond to the received slave address with an ACK, or ignore the received slave address with a NACK. SLA R A Data Byte A m en de d S fo r N ew D If the received slave address is ignored by software (by NACKing the address), slave interrupts will be inhibited until the next START is detected. If the received slave address is acknowledged, zero or more data bytes are transmitted. If the received slave address is acknowledged, data should be written to SMB0DAT to be transmitted. The interface enters slave transmitter mode, and transmits one or more bytes of data. After each byte is transmitted, the master sends an acknowledge bit; if the acknowledge bit is an ACK, SMB0DAT should be written with the next data byte. If the acknowledge bit is a NACK, SMB0DAT should not be written to before SI is cleared (an error condition may be generated if SMB0DAT is written following a received NACK while in slave transmitter mode). The interface exits slave transmitter mode after receiving a STOP. Note that the interface will switch to slave receiver mode if SMB0DAT is not written following a Slave Transmitter interrupt. Figure 22.8 shows a typical slave read sequence. Two transmitted data bytes are shown, though any number of bytes may be transmitted. Notice that all of the “data byte transferred” interrupts occur after the ACK cycle in this mode. Data Byte N P Interrupt Locations Received by SMBus Interface om Transmitted by SMBus Interface S = START P = STOP N = NACK R = READ SLA = Slave Address Figure 22.8. Typical Slave Read Sequence ec 22.6. SMBus Status Decoding N ot R The current SMBus status can be easily decoded using the SMB0CN register. Table 22.4 describes the typical actions taken by firmware on each condition. In the table, STATUS VECTOR refers to the four upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. The shown response options are only the typical responses; application-specific procedures are allowed as long as they conform to the SMBus specification. Highlighted responses are allowed by hardware but do not conform to the SMBus specification. Rev 1.1 146 C8051T610/1/2/3/4/5/6/7 0 0 ACK D 0 X 0 X 1110 0 1 X — Load next data byte into SMB0DAT. 0 0 X 1100 End transfer with STOP. 0 1 X — A master data or address byte End transfer with STOP and start 1 1 was transmitted; ACK another transfer. received. Send repeated START. 1 1 X — 0 X 1110 Switch to Master Receiver Mode 0 (clear SI without writing new data to SMB0DAT). 0 X 1000 Acknowledge received byte; Read SMB0DAT. 0 0 1 1000 Send NACK to indicate last byte, 0 and send STOP. 1 0 — Send NACK to indicate last byte, 1 and send STOP followed by START. 1 0 1110 Send ACK followed by repeated START. 1 0 1 1110 Send NACK to indicate last byte, 1 and send repeated START. 0 0 1110 Send ACK and switch to Master Transmitter Mode (write to SMB0DAT before clearing SI). 0 0 1 1100 Send NACK and switch to Master Transmitter Mode (write to SMB0DAT before clearing SI). 0 0 0 1100 m en de d 1 0 X A master data byte was received; ACK requested. R ec om 1000 1100 1 N ot 147 0 fo r 0 A master data or address byte Set STA to restart transfer. 0 was transmitted; NACK Abort transfer. received. N ew 1100 Load slave address + R/W into SMB0DAT. ACK 0 A master START was generated. STO 0 X es ig ns ARBLOST 0 Typical Response Options STA ACKRQ Vector Status Mode Master Receiver Master Transmitter 1110 Current SMbus State Vector Expected Values to Write Values Read Next Status Table 22.4. SMBus Status Decoding Rev 1.1 C8051T610/1/2/3/4/5/6/7 ACK 0 A slave byte was transmitted; No action required (expecting NACK received. STOP condition). 0 0 1 0 1 X es ig ns ARBLOST 0 STA STO 0 X 0001 A slave byte was transmitted; Load SMB0DAT with next data ACK received. byte to transmit. 0 0 X 0100 A Slave byte was transmitted; No action required (expecting error detected. Master to end transfer). 0 0 X 0001 0 0 X — 0 0 1 0000 If Read, Load SMB0DAT with 0 data byte; ACK received address 0 1 0100 NACK received address. 0 0 0 — 0 0 1 0000 If Read, Load SMB0DAT with 0 Lost arbitration as master; data byte; ACK received address 1 X slave address + R/W received; ACK requested. NACK received address. 0 0 1 0100 0 0 — 1 0 0 1110 0 0 X — Lost arbitration while attempt- No action required (transfer ing a STOP. complete/aborted). 0 0 0 — Acknowledge received byte; Read SMB0DAT. 0 0 1 0000 NACK received byte. 0 0 0 — 0 0 X — 1 0 X 1110 Abort failed transfer. 0 0 X — 1110 D 0 An illegal STOP or bus error 0 X X was detected while a Slave Clear STO. Transmission was in progress. m en de d A slave address + R/W was received; ACK requested. If Write, Acknowledge received address 0010 Slave Receiver 0 X fo r If Write, Acknowledge received address 1 1 Reschedule failed transfer; NACK received address. A STOP was detected while 0 X addressed as a Slave Transmitter or Slave Receiver. om 0 0001 1 X ec 1 1 A slave byte was received; 0 X ACK requested. Clear STO. 0 1 X Lost arbitration while attempt- Abort failed transfer. ing a repeated START. Reschedule failed transfer. 0001 0 1 X Lost arbitration due to a detected STOP. Reschedule failed transfer. 1 0 X 0 0 — 1 1 X Lost arbitration while transmit- Abort failed transfer. ting a data byte as master. Reschedule failed transfer. 0 0000 1 0 0 1110 0010 N ot Bus Error Condition R 0000 ACK Typical Response Options N ew 0101 ACKRQ Vector Status Mode Slave Transmitter 0100 0 Current SMbus State Vector Expected Values to Write Values Read Next Status Table 22.4. SMBus Status Decoding Rev 1.1 148 C8051T610/1/2/3/4/5/6/7 23. UART0 es ig ns UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in Section “23.1. Enhanced Baud Rate Generation” on page 150). Received data buffering allows UART0 to start reception of a second incoming data byte before software has finished reading the previous data byte. D UART0 has two associated SFRs: Serial Control Register 0 (SCON0) and Serial Data Buffer 0 (SBUF0). The single SBUF0 location provides access to both transmit and receive registers. Writes to SBUF0 always access the Transmit register. Reads of SBUF0 always access the buffered Receive register; it is not possible to read data from the Transmit register. N ew With UART0 interrupts enabled, an interrupt is generated each time a transmit is completed (TI0 is set in SCON0), or a data byte has been received (RI0 is set in SCON0). The UART0 interrupt flags are not cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually by software, allowing software to determine the cause of the UART0 interrupt (transmit complete or receive complete). fo r SFR Bus Write to SBUF TB8 SBUF (TX Shift) m en de d SET D Q TX CLR Crossbar Zero Detector Stop Bit Shift Start Data Tx Control Tx Clock Send Tx IRQ SCON MCE REN TB8 RB8 TI RI SMODE TI N ot Serial Port Interrupt Port I/O RI Rx IRQ Rx Clock Rx Control Start Shift 0x1FF RB8 Load SBUF Input Shift Register (9 bits) R ec om UART Baud Rate Generator Load SBUF SBUF (RX Latch) Read SBUF SFR Bus RX Crossbar Figure 23.1. UART0 Block Diagram Rev 1.1 149 C8051T610/1/2/3/4/5/6/7 23.1. Enhanced Baud Rate Generation Overflow TH1 fo r Start Detected TX Clock Overflow 2 RX Clock m en de d RX Timer 2 N ew TL1 UART D Timer 1 es ig ns The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 23.2), which is not useraccessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates. The RX Timer runs when Timer 1 is enabled, and uses the same reload value (TH1). However, an RX Timer reload is forced when a START condition is detected on the RX pin. This allows a receive to begin any time a START is detected, independent of the TX Timer state. Figure 23.2. UART0 Baud Rate Logic R ec om Timer 1 should be configured for Mode 2, 8-bit auto-reload (see Section “25.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload” on page 174). The Timer 1 reload value should be set so that overflows will occur at two times the desired UART baud rate frequency. Note that Timer 1 may be clocked by one of six sources: SYSCLK, SYSCLK/4, SYSCLK/12, SYSCLK/48, the external oscillator clock/8, or an external input T1. For any given Timer 1 clock source, the UART0 baud rate is determined by Equation 23.1-A and Equation 23.1-B. A) 1 UartBaudRate = --- × T1_Overflow_Rate 2 B) T1 CLK T1_Overflow_Rate = -------------------------256 – TH1 Equation 23.1. UART0 Baud Rate N ot Where T1CLK is the frequency of the clock supplied to Timer 1, and T1H is the high byte of Timer 1 (reload value). Timer 1 clock frequency is selected as described in Section “25. Timers” on page 170. A quick reference for typical baud rates and system clock frequencies is given in Table 23.1 through Table 23.2. The internal oscillator may still generate the system clock when the external oscillator is driving Timer 1. 150 Rev 1.1 C8051T610/1/2/3/4/5/6/7 23.2. Operational Modes TX RS-232 LEVEL XLTR RS-232 RX C8051xxxx N ew D OR es ig ns UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown in Figure 23.3. TX TX MCU C8051xxxx RX RX Figure 23.3. UART Interconnect Diagram fo r 23.2.1. 8-Bit UART m en de d 8-Bit UART mode uses a total of 10 bits per data byte: one start bit, eight data bits (LSB first), and one stop bit. Data are transmitted LSB first from the TX0 pin and received at the RX0 pin. On receive, the eight data bits are stored in SBUF0 and the stop bit goes into RB80 (SCON0.2). Data transmission begins when software writes a data byte to the SBUF0 register. The TI0 Transmit Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to logic 1. After the stop bit is received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met: RI0 must be logic 0, and if MCE0 is logic 1, the stop bit must be logic 1. In the event of a receive data overrun, the first received 8 bits are latched into the SBUF0 receive register and the following overrun data bits are lost. ec om If these conditions are met, the eight bits of data is stored in SBUF0, the stop bit is stored in RB80 and the RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not be set. An interrupt will occur if enabled when either TI0 or RI0 is set. MARK SPACE START BIT D0 D1 D2 D3 D4 D5 D6 D7 STOP BIT R BIT TIMES N ot BIT SAMPLING Figure 23.4. 8-Bit UART Timing Diagram Rev 1.1 151 C8051T610/1/2/3/4/5/6/7 23.2.2. 9-Bit UART es ig ns 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programmable ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80 (SCON0.3), which is assigned by user software. It can be assigned the value of the parity flag (bit P in register PSW) for error detection, or used in multiprocessor communications. On receive, the ninth data bit goes into RB80 (SCON0.2) and the stop bit is ignored. MARK START BIT SPACE D0 D1 D3 D4 D5 D6 fo r BIT TIMES D2 N ew D Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI0 Transmit Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to 1. After the stop bit is received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met: (1) RI0 must be logic 0, and (2) if MCE0 is logic 1, the 9th bit must be logic 1 (when MCE0 is logic 0, the state of the ninth data bit is unimportant). If these conditions are met, the eight bits of data are stored in SBUF0, the ninth bit is stored in RB80, and the RI0 flag is set to 1. If the above conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not be set to 1. A UART0 interrupt will occur if enabled when either TI0 or RI0 is set to 1. BIT SAMPLING N ot R ec om m en de d Figure 23.5. 9-Bit UART Timing Diagram 152 Rev 1.1 D7 D8 STOP BIT C8051T610/1/2/3/4/5/6/7 23.3. Multiprocessor Communications es ig ns 9-Bit UART mode supports multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or more slaves, it first sends an address byte to select the target(s). An address byte differs from a data byte in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0. N ew D Setting the MCE0 bit (SCON0.5) of a slave processor configures its UART such that when a stop bit is received, the UART will generate an interrupt only if the ninth bit is logic 1 (RB80 = 1) signifying an address byte has been received. In the UART interrupt handler, software will compare the received address with the slave's own assigned 8-bit address. If the addresses match, the slave will clear its MCE0 bit to enable interrupts on the reception of the following data byte(s). Slaves that weren't addressed leave their MCE0 bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the data. Once the entire message is received, the addressed slave resets its MCE0 bit to ignore all transmissions until it receives the next address byte. fo r Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. The master processor can be configured to receive all transmissions or a protocol can be implemented such that the master/slave role is temporarily reversed to enable half-duplex transmission between the original master and slave(s). RX Slave Device Slave Device m en de d Master Device TX RX TX RX Slave Device V+ TX RX TX N ot R ec om Figure 23.6. UART Multi-Processor Mode Interconnect Diagram Rev 1.1 153 C8051T610/1/2/3/4/5/6/7 6 Name S0MODE Type R/W Reset 0 5 4 3 2 MCE0 REN0 TB80 RB80 R R/W R/W R/W R/W 1 0 0 0 0 SFR Address = 0x98; Bit-Addressable Bit Name 7 Function S0MODE Serial Port 0 Operation Mode. Selects the UART0 Operation Mode. 0: 8-bit UART with Variable Baud Rate. 1: 9-bit UART with Variable Baud Rate. Unused 5 MCE0 Unused. Read = 1b, Write = Don’t Care. Multiprocessor Communication Enable. 0 TI0 RI0 R/W R/W 0 0 fo r 6 1 D 7 N ew Bit es ig ns SFR Definition 23.1. SCON0: Serial Port 0 Control m en de d The function of this bit is dependent on the Serial Port 0 Operation Mode: Mode 0: Checks for valid stop bit. 0: Logic level of stop bit is ignored. 1: RI0 will only be activated if stop bit is logic level 1. Mode 1: Multiprocessor Communications Enable. 0: Logic level of ninth bit is ignored. 1: RI0 is set and an interrupt is generated only when the ninth bit is logic 1. 4 REN0 Receive Enable. 0: UART0 reception disabled. 1: UART0 reception enabled. 3 TB80 Ninth Transmission Bit. 2 om The logic level of this bit will be sent as the ninth transmission bit in 9-bit UART Mode (Mode 1). Unused in 8-bit mode (Mode 0). RB80 Ninth Receive Bit. ec RB80 is assigned the value of the STOP bit in Mode 0; it is assigned the value of the 9th data bit in Mode 1. TI0 N ot R 1 0 154 RI0 Transmit Interrupt Flag. Set by hardware when a byte of data has been transmitted by UART0 (after the 8th bit in 8-bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When the UART0 interrupt is enabled, setting this bit causes the CPU to vector to the UART0 interrupt service routine. This bit must be cleared manually by software. Receive Interrupt Flag. Set to 1 by hardware when a byte of data has been received by UART0 (set at the STOP bit sampling time). When the UART0 interrupt is enabled, setting this bit to 1 causes the CPU to vector to the UART0 interrupt service routine. This bit must be cleared manually by software. Rev 1.1 C8051T610/1/2/3/4/5/6/7 7 6 5 4 3 Name SBUF0[7:0] Type R/W 0 Reset 0 0 0 SFR Address = 0x99 Bit Name Function SBUF0[7:0] Serial Data Buffer Bits 7–0 (MSB–LSB). 0 1 0 0 0 N ew 7:0 0 2 D Bit es ig ns SFR Definition 23.2. SBUF0: Serial (UART0) Port Data Buffer N ot R ec om m en de d fo r This SFR accesses two registers; a transmit shift register and a receive latch register. When data is written to SBUF0, it goes to the transmit shift register and is held for serial transmission. Writing a byte to SBUF0 initiates the transmission. A read of SBUF0 returns the contents of the receive latch. Rev 1.1 155 C8051T610/1/2/3/4/5/6/7 230400 115200 57600 28800 14400 9600 2400 1200 –0.32% –0.32% 0.15% –0.32% 0.15% –0.32% –0.32% 0.15% Oscillator Timer Clock Divide Source Factor 106 212 426 848 1704 2544 10176 20448 T1M1 Timer 1 Reload Value (hex) 1 1 1 0 0 0 0 0 0xCB 0x96 0x2B 0x96 0xB9 0x96 0x96 0x2B SCA1–SCA0 (pre-scale select)1 T1M1 Timer 1 Reload Value (hex) XX2 XX XX 00 00 00 10 10 11 11 11 11 11 11 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0xD0 0xA0 0x40 0xE0 0xC0 0xA0 0xA0 0x40 0xFA 0xF4 0xE8 0xD0 0xA0 0x70 SCA1–SCA0 (pre-scale select)1 XX2 XX XX 01 00 00 10 10 SYSCLK SYSCLK SYSCLK SYSCLK/4 SYSCLK/12 SYSCLK/12 SYSCLK/48 SYSCLK/48 D Baud Rate % Error N ew Target Baud Rate (bps) Internal Osc. SYSCLK from Frequency: 24.5 MHz es ig ns Table 23.1. Timer Settings for Standard Baud Rates Using The Internal 24.5 MHz Oscillator fo r Notes: 1. SCA1–SCA0 and T1M bit definitions can be found in Section 25.1. 2. X = Don’t care. Table 23.2. Timer Settings for Standard Baud Rates Using an External 22.1184 MHz Oscillator m en de d Baud Rate % Error 230400 115200 57600 28800 14400 9600 2400 1200 230400 115200 57600 28800 14400 9600 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% om External Osc. Internal Osc. Target Baud Rate (bps) Oscillator Timer Clock Divide Source Factor 96 192 384 768 1536 2304 9216 18432 96 192 384 768 1536 2304 SYSCLK SYSCLK SYSCLK SYSCLK / 12 SYSCLK / 12 SYSCLK / 12 SYSCLK / 48 SYSCLK / 48 EXTCLK / 8 EXTCLK / 8 EXTCLK / 8 EXTCLK / 8 EXTCLK / 8 EXTCLK / 8 N ot R ec SYSCLK from SYSCLK from Frequency: 22.1184 MHz Notes: 1. SCA1–SCA0 and T1M bit definitions can be found in Section 25.1. 2. X = Don’t care. 156 Rev 1.1 C8051T610/1/2/3/4/5/6/7 24. Enhanced Serial Peripheral Interface (SPI0) es ig ns The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input to select SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can also be configured as a chip-select output in master mode, or disabled for 3-wire operation. Additional general purpose port I/O pins can be used to select multiple slave devices in master mode. SPIF WCOL MODF RXOVRN NSSMD1 NSSMD0 TXBMT SPIEN fo r Clock Divide Logic SYSCLK SPI0CN N ew SPI0CFG SPIBSY MSTEN CKPHA CKPOL SLVSEL NSSIN SRMT RXBMT SCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCR1 SCR0 SPI0CKR D SFR Bus m en de d SPI CONTROL LOGIC Data Path Control SPI IRQ Pin Interface Control MOSI Tx Data SPI0DAT SCK N ot R ec om Transmit Data Buffer Shift Register Rx Data 7 6 5 4 3 2 1 0 Receive Data Buffer Pin Control Logic MISO C R O S S B A R Port I/O NSS Read SPI0DAT Write SPI0DAT SFR Bus Figure 24.1. SPI Block Diagram Rev 1.1 157 C8051T610/1/2/3/4/5/6/7 24.1. Signal Descriptions The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below. es ig ns 24.1.1. Master Out, Slave In (MOSI) The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It is used to serially transfer data from the master to the slave. This signal is an output when SPI0 is operating as a master and an input when SPI0 is operating as a slave. Data is transferred most-significant bit first. When configured as a master, MOSI is driven by the MSB of the shift register in both 3- and 4-wire mode. D 24.1.2. Master In, Slave Out (MISO) N ew The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device. It is used to serially transfer data from the slave to the master. This signal is an input when SPI0 is operating as a master and an output when SPI0 is operating as a slave. Data is transferred most-significant bit first. The MISO pin is placed in a high-impedance state when the SPI module is disabled and when the SPI operates in 4-wire mode as a slave that is not selected. When acting as a slave in 3-wire mode, MISO is always driven by the MSB of the shift register. 24.1.3. Serial Clock (SCK) m en de d fo r The serial clock (SCK) signal is an output from the master device and an input to slave devices. It is used to synchronize the transfer of data between the master and slave on the MOSI and MISO lines. SPI0 generates this signal when operating as a master. The SCK signal is ignored by a SPI slave when the slave is not selected (NSS = 1) in 4-wire slave mode. 24.1.4. Slave Select (NSS) The function of the slave-select (NSS) signal is dependent on the setting of the NSSMD1 and NSSMD0 bits in the SPI0CN register. There are three possible modes that can be selected with these bits: 1. NSSMD[1:0] = 00: 3-Wire Master or 3-Wire Slave Mode: SPI0 operates in 3-wire mode, and NSS is disabled. When operating as a slave device, SPI0 is always selected in 3-wire mode. Since no select signal is present, SPI0 must be the only slave on the bus in 3-wire mode. This is intended for point-topoint communication between a master and one slave. om 2. NSSMD[1:0] = 01: 4-Wire Slave or Multi-Master Mode: SPI0 operates in 4-wire mode, and NSS is enabled as an input. When operating as a slave, NSS selects the SPI0 device. When operating as a master, a 1-to-0 transition of the NSS signal disables the master function of SPI0 so that multiple master devices can be used on the same SPI bus. R ec 3. NSSMD[1:0] = 1x: 4-Wire Master Mode: SPI0 operates in 4-wire mode, and NSS is enabled as an output. The setting of NSSMD0 determines what logic level the NSS pin will output. This configuration should only be used when operating SPI0 as a master device. N ot See Figure 24.2, Figure 24.3, and Figure 24.4 for typical connection diagrams of the various operational modes. Note that the setting of NSSMD bits affects the pinout of the device. When in 3-wire master or 3-wire slave mode, the NSS pin will not be mapped by the crossbar. In all other modes, the NSS signal will be mapped to a pin on the device. See Section “21. Port Input/Output” on page 113 for general purpose port I/O and crossbar information. 158 Rev 1.1 C8051T610/1/2/3/4/5/6/7 24.2. SPI0 Master Mode Operation D es ig ns A SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by setting the Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data register (SPI0DAT) when in master mode writes to the transmit buffer. If the SPI shift register is empty, the byte in the transmit buffer is moved to the shift register, and a data transfer begins. The SPI0 master immediately shifts out the data serially on the MOSI line while providing the serial clock on SCK. The SPIF (SPI0CN.7) flag is set to logic 1 at the end of the transfer. If interrupts are enabled, an interrupt request is generated when the SPIF flag is set. While the SPI0 master transfers data to a slave on the MOSI line, the addressed SPI slave device simultaneously transfers the contents of its shift register to the SPI master on the MISO line in a full-duplex operation. Therefore, the SPIF flag serves as both a transmit-complete and receive-data-ready flag. The data byte received from the slave is transferred MSB-first into the master's shift register. When a byte is fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by reading SPI0DAT. m en de d fo r N ew When configured as a master, SPI0 can operate in one of three different modes: multi-master mode, 3-wire single-master mode, and 4-wire single-master mode. The default, multi-master mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In this mode, NSS is an input to the device, and is used to disable the master SPI0 when another master is accessing the bus. When NSS is pulled low in this mode, MSTEN (SPI0CN.6) and SPIEN (SPI0CN.0) are set to 0 to disable the SPI master device, and a Mode Fault is generated (MODF, SPI0CN.5 = 1). Mode Fault will generate an interrupt if enabled. SPI0 must be manually re-enabled in software under these circumstances. In multi-master systems, devices will typically default to being slave devices while they are not acting as the system master device. In multi-master mode, slave devices can be addressed individually (if needed) using general-purpose I/O pins. Figure 24.2 shows a connection diagram between two master devices in multiple-master mode. 3-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. In this mode, NSS is not used, and is not mapped to an external port pin through the crossbar. Any slave devices that must be addressed in this mode should be selected using general-purpose I/O pins. Figure 24.3 shows a connection diagram between a master device in 3-wire master mode and a slave device. N ot R ec om 4-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 1. In this mode, NSS is configured as an output pin, and can be used as a slave-select signal for a single SPI device. In this mode, the output value of NSS is controlled (in software) with the bit NSSMD0 (SPI0CN.2). Additional slave devices can be addressed using general-purpose I/O pins. Figure 24.4 shows a connection diagram for a master device in 4-wire master mode and two slave devices. Master Device 1 NSS GPIO MISO MISO MOSI MOSI SCK SCK GPIO NSS Master Device 2 Figure 24.2. Multiple-Master Mode Connection Diagram Rev 1.1 159 Master Device MISO MISO MOSI MOSI SCK SCK Slave Device es ig ns C8051T610/1/2/3/4/5/6/7 Master Device MISO MISO MOSI MOSI SCK SCK NSS NSS Slave Device fo r GPIO N ew D Figure 24.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram m en de d MISO MOSI Slave Device SCK NSS Figure 24.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram 24.3. SPI0 Slave Mode Operation N ot R ec om When SPI0 is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK signal. A bit counter in the SPI0 logic counts SCK edges. When 8 bits have been shifted through the shift register, the SPIF flag is set to logic 1, and the byte is copied into the receive buffer. Data is read from the receive buffer by reading SPI0DAT. A slave device cannot initiate transfers. Data to be transferred to the master device is pre-loaded into the shift register by writing to SPI0DAT. Writes to SPI0DAT are doublebuffered, and are placed in the transmit buffer first. If the shift register is empty, the contents of the transmit buffer will immediately be transferred into the shift register. When the shift register already contains data, the SPI will load the shift register with the transmit buffer’s contents after the last SCK edge of the next (or current) SPI transfer. When configured as a slave, SPI0 can be configured for 4-wire or 3-wire operation. The default, 4-wire slave mode, is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In 4-wire mode, the NSS signal is routed to a port pin and configured as a digital input. SPI0 is enabled when NSS is logic 0, and disabled when NSS is logic 1. The bit counter is reset on a falling edge of NSS. Note that the NSS signal must be driven low at least 2 system clocks before the first active edge of SCK for each byte transfer. Figure 24.4 shows a connection diagram between two slave devices in 4-wire slave mode and a master device. 160 Rev 1.1 C8051T610/1/2/3/4/5/6/7 es ig ns 3-wire slave mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. NSS is not used in this mode, and is not mapped to an external port pin through the crossbar. Since there is no way of uniquely addressing the device in 3-wire slave mode, SPI0 must be the only slave device present on the bus. It is important to note that in 3-wire slave mode there is no external means of resetting the bit counter that determines when a full byte has been received. The bit counter can only be reset by disabling and reenabling SPI0 with the SPIEN bit. Figure 24.3 shows a connection diagram between a slave device in 3wire slave mode and a master device. 24.4. SPI0 Interrupt Sources D When SPI0 interrupts are enabled, the following four flags will generate an interrupt when they are set to logic 1: All of the following bits must be cleared by software.  m en de d fo r N ew The SPI Interrupt Flag, SPIF (SPI0CN.7) is set to logic 1 at the end of each byte transfer. This flag can occur in all SPI0 modes.  The Write Collision Flag, WCOL (SPI0CN.6) is set to logic 1 if a write to SPI0DAT is attempted when the transmit buffer has not been emptied to the SPI shift register. When this occurs, the write to SPI0DAT will be ignored, and the transmit buffer will not be written.This flag can occur in all SPI0 modes.  The Mode Fault Flag MODF (SPI0CN.5) is set to logic 1 when SPI0 is configured as a master, and for multi-master mode and the NSS pin is pulled low. When a Mode Fault occurs, the MSTEN and SPIEN bits in SPI0CN are set to logic 0 to disable SPI0 and allow another master device to access the bus.  The Receive Overrun Flag RXOVRN (SPI0CN.4) is set to logic 1 when configured as a slave, and a transfer is completed and the receive buffer still holds an unread byte from a previous transfer. The new byte is not transferred to the receive buffer, allowing the previously received data byte to be read. The data byte which caused the overrun is lost. 24.5. Serial Clock Phase and Polarity om Four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases (edge used to latch the data). The CKPOL bit (SPI0CFG.4) selects between an active-high or active-low clock. Both master and slave devices must be configured to use the same clock phase and polarity. SPI0 should be disabled (by clearing the SPIEN bit, SPI0CN.0) when changing the clock phase or polarity. The clock and data line relationships for master mode are shown in Figure 24.5. For slave mode, the clock and data relationships are shown in Figure 24.6 and Figure 24.7. Note that CKPHA should be set to 0 on both the master and slave SPI when communicating between two Silicon Labs C8051 devices. N ot R ec The SPI0 Clock Rate Register (SPI0CKR) as shown in SFR Definition 24.3 controls the master mode serial clock frequency. This register is ignored when operating in slave mode. When the SPI is configured as a master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency or 12.5 MHz, whichever is slower. When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the system clock frequency, provided that the master issues SCK, NSS (in 4wire slave mode), and the serial input data synchronously with the slave’s system clock. If the master issues SCK, NSS, and the serial input data asynchronously, the maximum data transfer rate (bits/sec) must be less than 1/10 the system clock frequency. In the special case where the master only wants to transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the SPI slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. This is provided that the master issues SCK, NSS, and the serial input data synchronously with the slave’s system clock. Rev 1.1 161 C8051T610/1/2/3/4/5/6/7 es ig ns SCK (CKPOL=0, CKPHA=0) SCK (CKPOL=0, CKPHA=1) D SCK (CKPOL=1, CKPHA=0) MISO/MOSI MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 fo r NSS (Must Remain High in Multi-Master Mode) N ew SCK (CKPOL=1, CKPHA=1) SCK (CKPOL=0, CKPHA=0) SCK (CKPOL=1, CKPHA=0) MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ec MISO MSB om MOSI m en de d Figure 24.5. Master Mode Data/Clock Timing Figure 24.6. Slave Mode Data/Clock Timing (CKPHA = 0) N ot R NSS (4-Wire Mode) 162 Rev 1.1 C8051T610/1/2/3/4/5/6/7 MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 MISO MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 1 Bit 0 N ew MOSI D SCK (CKPOL=1, CKPHA=1) es ig ns SCK (CKPOL=0, CKPHA=1) NSS (4-Wire Mode) 24.6. SPI Special Function Registers fo r Figure 24.7. Slave Mode Data/Clock Timing (CKPHA = 1) N ot R ec om m en de d SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate Register. The four special function registers related to the operation of the SPI0 Bus are described in the following figures. Rev 1.1 163 C8051T610/1/2/3/4/5/6/7 7 6 5 4 3 2 Name SPIBSY MSTEN CKPHA CKPOL SLVSEL Type R R/W R/W R/W Reset 0 0 0 0 SFR Address = 0xA1 Bit Name SPIBSY 0 NSSIN SRMT RXBMT R R R R 0 1 1 1 Function SPI Busy. N ew 7 1 D Bit es ig ns SFR Definition 24.1. SPI0CFG: SPI0 Configuration This bit is set to logic 1 when a SPI transfer is in progress (master or slave mode). 6 MSTEN Master Mode Enable. 5 CKPHA SPI0 Clock Phase. fo r 0: Disable master mode. Operate in slave mode. 1: Enable master mode. Operate as a master. 0: Data centered on first edge of SCK period.* 1: Data centered on second edge of SCK period.* CKPOL SPI0 Clock Polarity. m en de d 4 0: SCK line low in idle state. 1: SCK line high in idle state. 3 SLVSEL Slave Selected Flag. This bit is set to logic 1 whenever the NSS pin is low indicating SPI0 is the selected slave. It is cleared to logic 0 when NSS is high (slave not selected). This bit does not indicate the instantaneous value at the NSS pin, but rather a de-glitched version of the pin input. 2 NSSIN NSS Instantaneous Pin Input. SRMT R ec 1 om This bit mimics the instantaneous value that is present on the NSS port pin at the time that the register is read. This input is not de-glitched. N ot 0 RXBMT Shift Register Empty (valid in slave mode only). This bit will be set to logic 1 when all data has been transferred in/out of the shift register, and there is no new information available to read from the transmit buffer or write to the receive buffer. It returns to logic 0 when a data byte is transferred to the shift register from the transmit buffer or by a transition on SCK. SRMT = 1 when in Master Mode. Receive Buffer Empty (valid in slave mode only). This bit will be set to logic 1 when the receive buffer has been read and contains no new information. If there is new information available in the receive buffer that has not been read, this bit will return to logic 0. RXBMT = 1 when in Master Mode. Note: In slave mode, data on MOSI is sampled in the center of each data bit. In master mode, data on MISO is sampled one SYSCLK before the end of each data bit, to provide maximum settling time for the slave device. See Table 24.1 for timing parameters. 164 Rev 1.1 C8051T610/1/2/3/4/5/6/7 7 6 5 4 Name SPIF WCOL MODF RXOVRN Type R/W R/W R/W R/W Reset 0 0 0 0 SFR Address = 0xF8; Bit-Addressable Bit Name SPIF 2 1 0 NSSMD[1:0] TXBMT SPIEN R/W R R/W 1 0 0 1 Function SPI0 Interrupt Flag. N ew 7 3 D Bit es ig ns SFR Definition 24.2. SPI0CN: SPI0 Control This bit is set to logic 1 by hardware at the end of a data transfer. If SPI interrupts are enabled, an interrupt will be generated. This bit is not automatically cleared by hardware, and must be cleared by software. 6 WCOL Write Collision Flag. MODF Mode Fault Flag. m en de d 5 fo r This bit is set to logic 1 if a write to SPI0DAT is attempted when TXBMT is 0. When this occurs, the write to SPI0DAT will be ignored, and the transmit buffer will not be written. If SPI interrupts are enabled, an interrupt will be generated. This bit is not automatically cleared by hardware, and must be cleared by software. This bit is set to logic 1 by hardware when a master mode collision is detected (NSS is low, MSTEN = 1, and NSSMD[1:0] = 01). If SPI interrupts are enabled, an interrupt will be generated. This bit is not automatically cleared by hardware, and must be cleared by software. 4 RXOVRN Receive Overrun Flag (valid in slave mode only). NSSMD[1:0] R ec 3:2 om This bit is set to logic 1 by hardware when the receive buffer still holds unread data from a previous transfer and the last bit of the current transfer is shifted into the SPI0 shift register. If SPI interrupts are enabled, an interrupt will be generated. This bit is not automatically cleared by hardware, and must be cleared by software. N ot 1 0 TXBMT Slave Select Mode. Selects between the following NSS operation modes: (See Section 24.2 and Section 24.3). 00: 3-Wire Slave or 3-Wire Master Mode. NSS signal is not routed to a port pin. 01: 4-Wire Slave or Multi-Master Mode (Default). NSS is an input to the device. 1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from the device and will assume the value of NSSMD0. Transmit Buffer Empty. This bit will be set to logic 0 when new data has been written to the transmit buffer. When data in the transmit buffer is transferred to the SPI shift register, this bit will be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer. SPIEN SPI0 Enable. 0: SPI disabled. 1: SPI enabled. Rev 1.1 165 C8051T610/1/2/3/4/5/6/7 7 6 5 4 Name SCR[7:0] Type R/W 0 Reset 0 0 0 SFR Address = 0xA2 Bit Name SCR[7:0] 2 0 0 1 0 0 0 Function SPI0 Clock Rate. N ew 7:0 3 D Bit es ig ns SFR Definition 24.3. SPI0CKR: SPI0 Clock Rate These bits determine the frequency of the SCK output when the SPI0 module is configured for master mode operation. The SCK clock frequency is a divided version of the system clock, and is given in the following equation, where SYSCLK is the system clock frequency and SPI0CKR is the 8-bit value held in the SPI0CKR register. m en de d for 0