CY28329ZXC

CY28329 133 MHz Spread Spectrum Clock Synthesizer/Driver with Differential CPU Outputs Features Benefits • Multiple output clocks at different frequencies • Motherboard clock generator — Four pairs of differential CPU outputs, up to 133 MHz — Support Multiple CPUs and a chipset — Ten synchronous PCI clocks, three free-running — Support for PCI slots and chipset — Six 3V66 clocks — Supports AGP and Hub Link — Two 48-MHz clocks — Supports USB host controller and graphic controller — One reference clock at 14.318 MHz — Supports ISA slots and I/O chip — One VCH clock • Enables reduction of EMI and overall system cost • Spread Spectrum clocking (down spread) • Enables ACPI compliant designs • Power-down features (PCI_STOP#, PD#) • Supports up to four CPU clock frequencies • Three Select inputs (Mode select & IC Frequency Select) • Enables ATE and “bed of nails” testing • Widely available, standard package enables lower cost • OE and Test Mode support • 56-pin SSOP package and 56-pin TSSOP package Logic Block Diagram Pin Configurations SSOP and TSSOP Top View XTAL OSC X1 X2 VDD_REF PWR 1 56 REF XTAL_IN 2 55 S1 XTAL_OUT 3 54 CPU3 GND_REF 4 53 CPU3# PCI_F0 5 52 CPU0 PCI_F1 6 51 CPU0# PCI_F2 7 50 VDD_CPU VDD_PCI 8 49 CPU1 GND_PCI 9 48 CPU1# PCI0 10 47 GND_CPU VDD_PCI PCI_F[0:2] PCI1 11 46 VDD_CPU PCI2 45 CPU2 PCI0:6 PCI3 12 13 44 CPU2# VDD_PCI 14 43 MULT0 GND_PCI PCI4 15 42 IREF 16 41 PCI5 PCI6 VDD_3V66 17 40 GND_IREF S2 18 39 19 38 PLL Ref Freq PLL 1 Divider Network Mult0 S1:2 VTTPWRGD# VDD_CPU CPU[0:3] PWR Gate CPU[0:3]# PWR Stop Clock Control PCI_STOP# /2 PD# VDD_3V66 PWR 3V66_0 PWR 3V66_[2:]4/ 66BUFF0:2 3V66_5/ 66IN PLL 2 VDD_48MHz PWR USB (48MHz) DOT (48MHz) VCH_CLK/ 3V66_1 USB GND_3V66 20 37 DOT VDD_ 48 MHz 66BUFF0/3V66_2 21 36 GND_ 48 MHz 66BUFF1/3V66_3 22 35 66BUFF2/3V66_4 66IN/3V66_5 23 34 3V66_1/VCH PCI_STOP# 24 25 33 3V66_0 32 VDD_3V66 26 31 GND_3V66 27 30 28 29 SCLK SDATA PD# VDD_CORE GND_CORE VTTPWRGD# SDATA SCLK CY28329 VDD_REF REF SMBus Logic ....................... Document #: 38-07040 Rev. *E Page 1 of 16 400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com CY28329 Pin Description Name Pins Description REF 56 3.3V 14.318 MHz clock output XTAL_IN 2 14.318 MHz crystal input XTAL_OUT 3 14.318 MHz crystal input CPU, CPU [0:3]# 44, 45, 48, 49, 51, 52, 53, 54 Differential CPU clock outputs 3V66_0 33 3.3V 66 MHz clock output 3V66_1/VCH 35 3.3V selectable through SMBus to be 66 MHz or 48 MHz 66IN/3V66_5 24 66 MHz input to buffered 66BUFF and PCI or 66 MHz clock from internal VCO 66BUFF [0:2] /3V66 [2:4] 21, 22, 23 66 MHz buffered outputs from 66Input or 66 MHz clocks from internal VCO PCI_F [0:2] 5, 6, 7, 33 MHz clocks divided down from 66Input or divided down from 3V66 PCI [0:6] 10, 11, 12, 13, 16, PCI clock outputs divided down from 66Input or divided down from 3V66 17, 18 USB 39 Fixed 48 MHz clock output DOT 38 Fixed 48 MHz clock output S2 40 Special 3.3V 3-level input for Mode selection S1 55 3.3V LVTTL inputs for CPU frequency selection IREF 42 A precision resistor is attached to this pin which is connected to the internal current reference MULT0 43 3.3V LVTTL input for selecting the current multiplier for the CPU outputs PD# 25 3.3V LVTTL input for Power_Down# (active LOW). Do not add any decoupling capacitors. Use an external 1.0-K pull-up resistor. PCI_STOP# 34 3.3V LVTTL input for PCI_STOP# (active LOW) VTTPWRGD# 28 3.3V LVTTL input is a level-sensitive strobe used to determine when S[1:2] and MULT0 inputs are valid and OK to be sampled (Active LOW). Once VTTPWRGD# is sampled LOW, the status of this output will be ignored. SDATA 29 SMBus-compatible SDATA SCLK 30 SMBus-compatible Sclk VDD_REF, VDD_PCI, VDD_3V66, VDD_48 MHz, VDD_CPU 1, 8, 14, 19, 32, 37, 46, 50 3.3V power supply for outputs VDD_CORE 26 3.3V power supply for PLL GND_REF, GND_PCI, GND_3V66, GND_IREF, VDD_CPU 4, 9, 15, 20, 31, 36, 41, 47 Ground for outputs GND_CORE 27 Ground for PLL .......................Document #: 38-07040 Rev. *E Page 2 of 16 CY28329 Function Table[1] S2 CPU (MHz) S1 3V66[0:1]( MHz) 66BUFF[0:2]/ 3V66[2:4] (MHz) 66IN/3V66_5 (MHz) PCI_F/PCI (MHz) USB/DOT (MHz) REF0(MHz) Notes 1 0 100 MHz 66 MHz 66IN 66-MHz Input 66IN/2 14.318 MHz 48 MHz 2, 3, 4 1 1 133 MHz 66 MHz 66IN 66-MHz Input 66IN/2 14.318 MHz 48 MHz 2, 3, 4 0 0 100 MHz 66 MHz 66 MHz 66-MHz Input 33 MHz 14.318 MHz 48 MHz 2, 3, 4 0 1 133 MHz 66 MHz 66 MHz 66-MHz Input 33 MHz 14.318 MHz 48 MHz 2, 3, 4 Mid 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 5, 6 Mid 1 TCLK/2 TCLK/4 TCLK/4 TCLK/4 TCLK/8 TCLK TCLK/2 1, 6 Swing Select Functions Mult0 Board Target Trace/Term Z Reference R, IREF = VDD/(3*Rr) Output Current VOH @ Z, 0 50 ohm Rr = 221 1%, IREF = 5.00 mA IOH = 4*Iref 1.0V @ 50 1 50 ohm Rr = 475 1%, IREF = 2.32 mA IOH = 6*Iref 0.7V @ 50 Clock Driver Impedances Impedance Buffer Name VDD Range CPU, CPU# Buffer Type Min. (Ohm) Typ. (Ohm) Type X1 REF 3.135–3.465 Max. (Ohm) 50 Type 3 20 40 60 PCI, 3V66, 66BUFF 3.135–3.465 Type 5 12 30 55 USB 3.135–3.465 Type 3A 12 30 55 DOT 3.135–3.465 Type 3B 12 30 55 Clock Enable Configuration PD# PCI_STOP# CPU CPU# 3V66 66BUFF PCI_F PCI USB/DOT VCOS/OSC 0 X IREF*2 FLOAT LOW LOW LOW LOW LOW OFF 1 0 ON ON ON ON ON OFF ON ON 1 1 ON ON ON ON ON ON ON ON Notes: 1. TCLK is a test clock driven in on the XTALIN input in test mode. 2. “Normal” mode of operation. 3. Range of reference frequency allowed is min. = 14.316 nominal = 14.31818 MHz, max. = 14.32 MHz. 4. Frequency accuracy of 48 MHz must be +167 PPM to match USB default. 5. Required for board level “bed of nails” testing. 6. Mid is defined a Voltage level between 1.0V and 1.8V for 3 level input functionality. Low is below 0.8V. High is above 2.0V. .......................Document #: 38-07040 Rev. *E Page 3 of 16 CY28329 Serial Data Interface (SMBus) A Block write begins with a slave address and a WRITE condition. The R/W bit is used by the SMBus controller as a data direction bit. A zero indicates a WRITE condition to the clock device. The slave receiver address is 11010010 (D2h). To enhance the flexibility and function of the clock synthesizer, a two-signal SMBus interface is provided according to SMBus specification. Through the Serial Data Interface, various device functions such as individual clock output buffers, etc. can be individually enabled or disabled. CY28329 support both block read and block write operations. A command code of 0000 0000 (00h) and the byte count bytes are required for any transfer. After the command code, the core logic issues a byte count, which describes number of additional bytes required for the transfer, not including the command code and byte count bytes. For example, if the host has 20 data bytes to send, the first byte would be the number 20 (14h), followed by the 20 bytes of data. The byte count byte is required to be a minimum of 1 byte and a maximum of 32 bytes It may not be 0. Figure 1 shows an example of a block write. The registers associated with the Serial Data Interface initializes to its default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. A transfer is considered valid after the acknowledge bit corresponding to the byte count is read by the controller. Data Protocol The clock driver serial protocol accepts only Block Writes from the controller. The bytes must be accessed in sequential order from lowest to highest byte, (most significant bit first) with the ability to stop after any complete byte has been transferred. Indexed bytes are not allowed. Start Slave Address bit 1 1 0 1 0 0 1 0 1 bit 7 bits R/W 0/1 1 A Command Code A Byte Count = A 00000000 N 1 8 bits 1 8 bits 1 Data Byte 0 A 8 bits 1 ... Data Byte N-1 A 8 bits Stop bit 1 1 bit From Master to Slave From Slave to Master Figure 1. An Example of a Block Write Data Byte Configuration Map Data Byte 0: Control Register (0 = Enable, 1 = Disable) Bit Affected Pin# Name Bit 7 5, 6, 7, 10, 11, 12, 13, 16, 17, 18, 33, 35 PCI [0:6] CPU[3:0] 3V66[1:0] Bit 6 – – Bit 5 35 3V66_1/VCH Bit 4 – – Bit 3 10, 11, 12, 13, 16, 17, 18 PCI [6:0] Bit 2 40 S2 Bit 1 55 S1 Bit 0 – – Description Spread Spectrum Enable 0 = Spread Off, 1 = Spread On Reserved, set = 0 VCH Select 66 MHz/48 MHz 0 = 66 MHz, 1 = 48 MHz Reserved Type Power On Default R/W 0 R 0 R/W 0 R 1 R/W 1 S2 Reflects the value of the S2 pin sampled on Power-up R HW S1 Reflects the value of the S1 pin sampled on Power-up R HW Reserved R 1 PCI_STOP#, 0 = stopped, 1 = running (Does not affect PCI_F [2:0] pins) .......................Document #: 38-07040 Rev. *E Page 4 of 16 CY28329 Data Byte 1: Bit Pin# Name Bit 7 – Bit 6 53, 54 CPU3 CPU3# Bit 5 – Bit 4 Bit 3 Description CPU Mult0 Value Type Power On Default R HW CPU3 Output Enable 1 = Enabled; 0 = Disabled R/W 1 – Reserved, set = 0 R/W 0 – – Reserved, set = 0 R/W 0 – – Reserved, set = 0 R/W 0 Bit 2 44, 45 CPU2 CPU2# CPU2 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 1 48, 49 CPU1 CPU1# CPU1Output Enable 1 = Enabled; 0= Disabled R/W 1 Bit 0 51, 52 CPU0 CPU0# CPU0 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Pin# Name Type Power On Default Data Byte 2: Bit Pin Description Bit 7 – – R 0 Bit 6 18 PCI6 PCI6 Output Enable 1 = Enabled; 0 = Disabled Reserved, set = 0 R/W 1 Bit 5 17 PCI5 PCI5 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 4 16 PCI4 PCI4 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 3 13 PCI3 PCI3 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 2 12 PCI2 PCI2 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 1 11 PCI1 PCI1 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 0 10 PCI0 PCI0 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Pin# Name Type Power On Default Bit 7 38 DOT DOT 48 MHz Output Enable, 1 = enabled, 0 = disabled R/W 1 Bit 6 39 USB USB 48 MHz Output Enable, 1 = enabled, 0 = disabled R/W 1 Bit 5 7 PCI_F2 Allow control of PCI_F2 with assertion of PCI_STOP# 0 = Free running; 1 = Stopped with PCI_STOP# R/W 0 Bit 4 6 PCI_F1 Allow control of PCI_F1 with assertion of PCI_STOP# 0 = Free running; 1 = Stopped with PCI_STOP# R/W 0 Bit 3 5 PCI_F0 Allow control of PCI_F0 with assertion of PCI_STOP# 0 = Free running; 1 = Stopped with PCI_STOP# R/W 0 Bit 2 7 PCI_F2 PCI_F2 Output Enable, 1 = enabled, 0 = disabled R/W 1 Bit 1 6 PCI_F1 PCI_F1Output Enable, 1 = enabled, 0 = disabled R/W 1 Bit 0 5 PCI_F0 PCI_F0 Output Enable, 1 = enabled, 0 = disabled R/W 1 Data Byte 3: Bit Pin Description .......................Document #: 38-07040 Rev. *E Page 5 of 16 CY28329 Data Byte 4: Bit Pin# Name Pin Description Type Power On Default Bit 7 – Reserved, set = 0 R 0 Bit 6 – Reserved, set = 0 R 0 Bit 5 33 3V66_0 3V66_0 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 4 35 3V66_1/VCH 3V66_1/VCH Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 3 24 66IN/3V66_5 3V66_5 Output Enable 1 = Enable; 0 = Disable Note: This bit should be used when pin 24 is configured as 3V66_5 output. do not clear this bit when pin 24 is configured as 66IN input. R/W 1 Bit 2 23 66BUFF2 66-MHz Buffered 2 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 1 22 66BUFF1 66-MHz Buffered 1 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 0 21 66BUFF0 66-MHz Buffered 0 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Type Power On Default R 0 Data Byte 5: Bit Pin# Name Bit 7 Reserved, set = 0 Bit 6 Bit 5 Pin Description R 0 Tpd 66IN to 66BUFF propagation delay control Reserved, set = 0 R/W 0 R/W 0 DOT DOT edge rate control R/W 0 R/W 0 USB USB edge rate control R/W 0 R/W 0 21,22,23 66BUFF [2:0] 38 39 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 6: Vendor ID Bit Description Type Power On Default Bit 7 Revision Code Bit 3 R 0 Bit 6 Revision Code Bit 2 R 0 Bit 5 Revision Code Bit 1 R 0 Bit 4 Revision Code Bit 0 R 0 Bit 3 Vendor ID Bit 3 R 1 Bit 2 Vendor ID Bit 2 R 0 Bit 1 Vendor ID Bit 1 R 0 Bit 0 Vendor ID Bit 0 R 0 .......................Document #: 38-07040 Rev. *E Page 6 of 16 CY28329 Absolute Maximum Conditions Storage Temperature (Non-Condensing) ....–65°C to +150°C (Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage..................................................–0.5 to +7.0V Max. Soldering Temperature (10 sec.) ...................... +260°C Junction Temperature................................................ +150°C Package Power Dissipation.............................................. 1W Static Discharge Voltage ........................................................ (per MIL-STD-883, Method 3015) ............................ > 2000V over which electrical parameters are guaranteed[7] Input Voltage............................................ –0.5V to VDD + 0.5 Operating Conditions Parameter Description Min. Max. Unit 3.135 3.465 V 0 VDD_REF, VDD_PCI,VDD_CORE, VDD_3V66, VDD_48 MHz, VDD_CPU, 3.3V Supply Voltages TA Operating Temperature, Ambient 70 C Cin Input Pin Capacitance 5 pF CXTAL XTAL Pin Capacitance 22.5 pF CL Max. Capacitive Load on USBCLK, REF PCICLK, 3V66 f(REF) Reference Frequency, Oscillator Nominal Value pF 20 30 14.318 14.318 MHz DC Electrical Specifications Over the Operating Range Parameter Description Test Conditions Min. Max. Unit VIH High-level Input Voltage VIL Low-level Input Voltage Except Crystal Pads VOH High-level Output Voltage USB, REF, 3V66 IOH = –1 mA 2.4 V PCI IOH = –1 mA 2.4 V USB, REF, 3V66 IOL = 1 mA 0.4 V PCI IOL = 1 mA 0.55 V –5 5 mA –5 5 mA VOL Low-level Output Voltage Except Crystal Pads. Threshold voltage for crystal pads = VDD/2 2.0 0.8 IIH Input High Current 0 < VIN < VDD IIL Input Low Current 0 < VIN < VDD IOH High-level Output Current CPU For IOH =6*IRef Configuration Type X1, VOH = 0.65V REF, DOT, USB Type 3, VOH = 1.00V 12.9 Type X1, VOH = 0.74V Type 5, VOH = 1.00V Low-level Output Current REF, DOT, USB Type 3, VOL = 1.95V –23 –33 –33 29 Type 3, VOL = 0.4V 3V66, PCI Type 5, VOL =1.95 V Output Leakage Current IDD3 mA 27 30 Type 5, VOL = 0.4V IOZ mA 14.9 Type 5, VOH = 3.135V IOL V –29 Type 3, VOH = 3.135V 3V66, DOT, PCI V Three-state 38 10 mA 360 mA IDDPD3 3.3V Power Supply Current VDD_CORE/VDD3.3 = 3.465V, FCPU = 133 MHz 3.3V Shutdown Current VDD_CORE/VDD3.3 = 3.465V and @ IREF = 2.32 mA 25 mA IDDPD3 3.3V Shutdown Current 45 mA VDD_CORE/VDD3.3 = 3.465V and @ IREF = 5.0 mA Note: 7. Multiple Supplies: the voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. .......................Document #: 38-07040 Rev. *E Page 7 of 16 CY28329 Switching Characteristics Over the Operating Range[8] Parameter Output Description Cycle[9] Test Conditions Min. Max. Unit Measured at 1.5V 45 55 % t1 All Output Duty t2 CPU Rise Time Measured differential waveform from –0.35V to +0.35V 175 700 ns t2 USB, REF, DOT Rising Edge Rate Between 0.4V and 2.4V 0.5 2.0 ns t2 PCI, 3V66 Rising Edge Rate Between 0.4V and 2.4V 1.0 4.0 V/ns t3 CPU Fall Time Measured differential waveform from –0.35V to +0.35V 175 700 ps t3 USB, REF, DOT Falling Edge Rate Between 2.4V and 0.4V 0.5 2.0 ns t3 PCI, 3V66 Falling Edge Rate Between 2.4V and 0.4V 1.0 4.0 V/ns t4 CPU CPU-CPU Skew Measured at Crossover 150 ps t5 3V66 [0:1] 3V66-3V66 Skew Measured at 1.5V 500 ps t5 66BUFF[0:2] 66BUFF-66BUFF Skew Measured at 1.5V 175 ps t6 PCI PCI-PCI Skew Measured at 1.5V t7 3V66, PCI 3V66-PCI Clock Skew 3V66 leads. Measured at 1.5V t8 CPU Cycle-Cycle Clock Jitter t9 3V66 t9 500 ps 3.5 ns Measured at Crossover t8 = t8A – t8B With all outputs running 150 ps Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 250 ps USB, DOT Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 350 ps t9 PCI Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 500 ps t9 REF Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B t10 ALL POR timing Measured at 1.5V[10, 11] CPU Rise/Fall Matching Measured with test loads[12, 13] 1.5 1.0 1000 ps 4.0 ms 235 mV loads[13] 0.92 1.45 V Voh CPU High-level Output Voltage including overshoot Measured with test Vol CPU Low-level Output Voltage including undershoot Measured with test loads[13] –0.2 0.35 V Vcrossover CPU Crossover Voltage Measured with test loads[13] 0.250 0.550 V Notes: 8. All parameters specified with loaded outputs. 9. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V. 10. POR starts when VDD reaches 1.5V. 11. All PULL-UPs must ramp at the same rate as VDD. 12. Determined as a fraction of 2*(Trp – Trn)/(Trp +Trn) Where Trp is a rising edge and Trn is an intersecting falling edge. 13. The test load is Rs = 33.2, Rp = 49.9 in test circuit. .......................Document #: 38-07040 Rev. *E Page 8 of 16 CY28329 Definition and Application of VTTPWRGD# Signal Vtt VRM8.5 CPU VTTPWRGD# BSEL0 BSEL1 3.3V 3.3V 3.3V NPN VTTPWRGD# CLOCK S0 10K 10K GMCH GENERATOR S1 .......................Document #: 38-07040 Rev. *E Page 9 of 16 10K 10K CY28329 Switching Waveforms Duty Cycle Timing (Single-Ended Output) t1B t1A Duty Cycle Timing (CPU Differential Output) t1B t1A All Outputs Rise/Fall Time VDD OUTPUT 0V t3 t2 CPU-CPU Clock Skew Host_b Host Host_b Host t4 3V66-3V66 Clock Skew 3V66 3V66 t5 PCI-PCI Clock Skew PCI PCI t6 ..................... Document #: 38-07040 Rev. *E Page 10 of 16 CY28329 Switching Waveforms (continued) 3V66-PCI Clock Skew 3V66 PCI t7 CPU Clock Cycle-Cycle Jitter t8A t8B Host_b Host Cycle-Cycle Clock Jitter t9A t9B CLK VDD and POR Timing 1.5V VDD 1.5V POR t10 ..................... Document #: 38-07040 Rev. *E Page 11 of 16 CY28329 VTTPWRGD# Timing Diagrams GND VRM 5/12V PWR_GD VID [3:0] BSEL [1:0] VTTPWRGD FROM VRM VCC CPU CORE VTTPWRGD 0.2–0.3 ms Wait for Sample delay VTTPWRGD# BSELS VCC CLOCK GEN State 1 State 0 CLOCK STATE State 2 State 3 OFF ON CLOCK VCO OFF ON CLOCK OUTPUTS Figure 2. CPU Power BEFORE Clock Power GND VRM 5/12V PWRGD VID [3:0] BSEL [1:0] PWRGD FROM VRM PWRGD# FROM NPN VCC CPU CORE VTTPWRGD 0.2–0.3 ms delay VCC CLOCK GEN CLOCK STATE State 0 Wait for VTTPWRGD# State 1 Sample BSELS State 2 State 3 OFF ON CLOCK VCO OFF ON CLOCK OUTPUTS Figure 3. CPU Power AFTER Clock Power ..................... Document #: 38-07040 Rev. *E Page 12 of 16 CY28329 PD# Assertion 66BUFF PCI Power Down Rest of Generator PCI_F (APIC) PD# CPU CPU# 3V66 UNDEF 66IN USB REF PD# Deassertion