CY28346ZI-2

CY28346-2 Clock Synthesizer with Differential CPU Outputs Features • Compliant with Intel® CK 408 Mobile Clock Synthesizer specifications • Spread Spectrum electromagnetic interference (EMI) reduction • 3.3V power supply • Dial-a-Frequency features • 3 differential CPU clocks • Dial-a-dB™ features • 10 copies of PCI clocks • Extended operating temperature range, 0C to 85C • 5/6 copies of 3V66 clocks • 56-pin TSSOP packages • SMBus support with Read Back capabilities Table 1. Frequency Table[1] S2 S1 S0 CPU (0:2) 3V66 66BUFF(0:2)/ 3V66(0:4) 66IN/ 3V66-5 PCIF/PCI REF USB/ DOT 1 0 0 66M 66M 66IN 66-MHz clock input 66IN/2 14.318M 48M 1 0 1 100M 66M 66IN 66-MHz clock input 66IN/2 14.318M 48M 1 1 0 200M 66M 66IN 66-MHz clock input 66IN/2 14.318M 48M 1 1 1 133M 66M 66IN 66-MHz clock input 66IN/2 14.318M 48M 0 0 0 66M 66M 66M 66M 33 M 14.318M 48M 0 0 1 100M 66M 66M 66M 33 M 14.318M 48M 0 1 0 200M 66M 66M 66M 33 M 14.318M 48M 0 1 1 133M 66M 66M 66M 33 M 14.318M 48M M 0 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z M 0 1 TCLK/2 TCLK/4 TCLK/4 TCLK/4 TCLK/8 TCLK TCLK/2 Block Diagram Pin Configuration XIN XOUT REF CPUT(0:2) CPUC(0:2) PLL1 CPU_STP# IREF VSSIREF 3V66_1/VCH MULT0 VTT_PWRGD# /2 PCI_STP# PCI(0:6) PCI_F(0:2) PLL2 48M_USB 48M_DOT PD# SDATA SCLK WD Logic I2C Logic 66B[0:2]/3V66[2:4] VDDA Power Up Logic 66IN/3V66-5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 CY28346-2 3V66_0 S(0:2) VDD XIN XOUT VSS PCIF0 PCIF1 PCIF2 VDD VSS PCI0 PCI1 PCI2 PCI3 VDD VSS PCI4 PCI5 PCI6 VDD VSS 66B0/3V66_2 66B1/3V66_3 66B2/3V66_4 66IN/3V66_5 PD# VDDA VSSA VTT_PWRGD# 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 REF S1 S0 CPU_STP# CPUT0 CPUC0 VDD CPUT1 CPUC1 VSS VDD CPUT2 CPUC2 MULT0 IREF VSSIREF S2 48M_USB 48M_DOT VDD VSS 3V66_1/VCH PCI_STP# 3V66_0 VDD VSS SCLK SDATA Note: 1. TCLK is a test clock driven on the XTAL_IN input during test mode. M = driven to a level between 1.0V and 1.8V. If the S2 pin is at a M level during power-up, a 0 state will be latched into the devices internal state register. ........................ Document #: 38-07509 Rev. *B Page 1 of 19 400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com CY28346-2 Pin Description Pin Name PWR I/O Description 2 XIN VDD I Oscillator Buffer Input. Connect to a crystal or to an external clock. 3 XOUT VDD O Oscillator Buffer Output. Connect to a crystal. Do not connect when an external clock is applied at XIN. VDD O Differential host output clock pairs. See Table 1 for frequencies and functionality. VDDP O PCI clock outputs. Are synchronous to 66IN or 3V66 clock. See Table 1. 52, 51, 49, 48, CPUT(0:2), 45, 44 CPUC(0:2) 10, 11, 12, 13, PCI(0:6) 16, 17, 18 5, 6, 7 PCIF (0:2) VDD O 33-MHz PCI clocks, which are 2 copies of 66IN or 3V66 clocks, may be free running (not stopped when PCI_STP# is asserted LOW) or may be stoppable depending on the programming of SMBus register Byte3, Bits (3:5). 56 REF VDD O Buffered output copy of the device’s XIN clock. 42 IREF VDD I Current reference programming input for CPU buffers. A resistor is connected between this pin and VSSIREF. 28 VTT_PWRGD# VDD I Qualifying input that latches S(0:2) and MULT0. When this input is at a logic low, the S(0:2) and MULT0 are latched. 39 48M_USB VDD48 O Fixed 48-MHz USB clock outputs. 38 48M_DOT VDD48 O Fixed 48-MHZ DOT clock outputs. 33 3V66_0 VDD O 3.3V 66-MHz fixed frequency clock. 35 3V66_1/VCH VDD O 3.3V clock selectable with SMBus byte0, Bit5, when Byte5, Bit5. When Byte 0 Bit 5 is at a logic 1, then this pin is a 48M output clock. When byte0, Bit5 is a logic 0, then this is a 66M output clock (default). 25 PD# VDD I PU This pin is a power-down mode pin. A logic LOW level causes the device to enter a power-down state. All internal logic is turned off except for the SMBus logic. All output buffers are stopped. 43 MULT0 VDD I PU Programming input selection for CPU clock current multiplier. 55, 54 S(0,1) I I Frequency select inputs. See Table 1 29 SDATA I I Serial data input. Conforms to the SMBus specification of a Slave Receive/Transmit device. It is an input when receiving data. It is an open drain output when acknowledging or transmitting data. 30 SCLK I I Serial clock input. Conforms to the SMBus specification. 40 S2 VDD I T Frequency select input. See Table 1. This is a Tri-level input that is driven HIGH, LOW, or driven to a intermediate level. 34 PCI_STP# VDD I PU PCI clock disable input. When asserted LOW, PCI (0:6) clocks are synchronously disabled in a LOW state. This pin does not effect PCIF (0:2) clocks’ outputs if they are programmed to be PCIF clocks via the device’s SMBus interface. 53 CPU_STP# VDD I PU CPU clock disable input. When asserted LOW, CPUT (0:2) clocks are synchronously disabled in a HIGH state and CPUC(0:2) clocks are synchronously disabled in a LOW state. 24 66IN/3V66_5 VDD I/O Input connection for 66CLK(0:2) output clock buffers if S2 = 1, or output clock for fixed 66-MHz clock if S2 = 0. See Table 1. 21, 22, 23 66B(0:2)/ 3V66(2:4) VDD O 3.3V clock outputs. These clocks are buffered copies of the 66IN clock or fixed at 66 MHz. See Table 1. 1, 8, 14, 19, 32, VDD 37, 46, 50 – PWR 3.3V power supply. 4, 9, 15, 20, 27, VSS 31, 36, 47 – PWR Common ground. ........................ Document #: 38-07509 Rev. *B Page 2 of 19 CY28346-2 Pin Description (continued) Pin Name PWR I/O Description 41 VSSIREF – PWR Current reference programming input for CPU buffers. A resistor is connected between this pin and IREF. This pin should also be returned to device VSS. 26 VDDA – PWR Analog power input. Used for PLL and internal analog circuits. It is also specifically used to detect and determine when power is at an acceptable level to enable the device to operate. Serial Data Interface Data Protocol To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. The clock driver serial protocol accepts block write and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. The block write and block read protocol is outlined in Table 2. The slave receiver address is 11010010 (D2h). Table 2. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 Description Start Slave address – 7 bits 9 Write = 0 10 Acknowledge from slave 11:18 19 20:27 28 29:36 37 38:45 46 Command Code – 8 bit ‘00000000’ stands for block operation Acknowledge from slave Byte Count – 8 bits Acknowledge from slave Block Read Protocol Bit 1 2:8 9 10 11:18 19 20 21:27 Description Start Slave address – 7 bits Write = 0 Acknowledge from slave Command Code – 8 bit ‘00000000’ stands for block operation Acknowledge from slave Repeat start Slave address – 7 bits Data byte 1 – 8 bits 28 Read = 1 Acknowledge from slave 29 Acknowledge from slave Data byte 2 – 8 bits Acknowledge from slave 30:37 38 .... ...................... .... Data Byte (N–1) –8 bits 47 .... Acknowledge from slave 48:55 .... Data Byte N –8 bits 56 .... Acknowledge from slave .... Data bytes from slave/Acknowledge .... Stop .... Data byte N from slave – 8 bits .... Not Acknowledge .... Stop ........................ Document #: 38-07509 Rev. *B Page 3 of 19 39:46 Byte count from slave – 8 bits Acknowledge Data byte from slave – 8 bits Acknowledge Data byte from slave – 8 bits Acknowledge CY28346-2 Byte 0: CPU Clock Register Bit @Pup 7 Name Description 0 Spread Spectrum Enable, 0 = Spread Off, 1 = Spread On. This is a Read and Write control bit. 6 0 CPU clock Power-down Mode Select. 0 = Drive CPUT(0:2) to 4 or 6 IREF and drive CPUC(0:2) to low when PD# is asserted LOW. 1 = Three-state all CPU outputs. This is only applicable when PD# is LOW. It is not applicable to CPU_STP#. 5 0 4 Pin 53 3 Pin 34 2 Pin 40 Frequency Select Bit 2. Reflects the value of SEL2 (pin 40). This bit is Read-only. 1 Pin 55 Frequency Select Bit 1. Reflects the value of SEL1 (pin 55). This bit is Read-only. 0 Pin 54 Frequency Select Bit 0. Reflects the value of SEL0 (pin 54). This bit is Read-only. 3V66_1/VCH 3V66_1/VCH frequency Select, 0 = 66M selected, 1 = 48M selected This is a Read and Write control bit. CPUT,CPUC CPU_STP#. Reflects the current value of the external CPU_STP# (pin 53) This bit is Read-only. PCI Reflects the current value of the internal PCI_STP# function when read. Internally PCI_STP# is a logical AND function of the internal SMBus register bit and the external PCI_STP# pin. Byte 1: CPU Clock Register Bit @Pup 7 Pin 43 Name MULT0 Description MULT0 (Pin 43) Value. This bit is Read-only. Controls functionality of CPUT/C(0:2) outputs when CPU_STP# is asserted. 0 = Drive CPUT(0:2) to 4 or 6 IREF and drive CPUC(0:2) to low when CPU_STP# asserted LOW. 1 = Three-state all CPU CPU_STP# outputs. This bit will override Byte0, Bit6 such that even if it is a 0, when PD# goes low the CPU outputs will be three-stated. 6 0 5 0 CPUT2 CPUC2 Controls CPU2 functionality when CPU_STP# is asserted LOW 1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW This is a Read and Write control bit. 4 0 CPUT1 CPUC1 Controls CPU1 functionality when CPU_STP# is asserted LOW 1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW This is a Read and Write control bit. 3 0 CPUT0 CPUC0 Controls CPUT0 functionality when CPU_STP# is asserted LOW 1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW This is a Read and Write control bit. 2 1 CPUT2 CPUC2 CPUT/C2 Output Control, 1 = enabled, 0 = disable HIGH and CPUC2 disables LOW This is a Read and Write control bit. 1 1 CPUT1 CPUC1 CPUT/C1 Output Control, 1 = enabled, 0 = disable HIGH and CPUC1 disables LOW This is a Read and Write control bit. 0 1 CPUT0 CPUC0 CPUT/C0 Output Control, 1 = enabled, 0 = disable HIGH and CPUC0 disables LOW This is a Read and Write control bit. Byte 2: PCI Clock Control Register (all bits are read and write functional) Bit @Pup Name Description 7 0 REF REF Output Control. 0 = high strength, 1 = low strength 6 1 PCI6 PCI6 Output Control. 1 = enabled, 0 = forced LOW 5 1 PCI5 PCI5 Output Control. 1 = enabled, 0 = forced LOW 4 1 PCI4 PCI4 Output Control. 1 = enabled, 0 = forced LOW 3 1 PCI3 PCI3 Output Control. 1 = enabled, 0 = forced LOW 2 1 PCI2 PCI2 Output Control. 1 = enabled, 0 = forced LOW 1 1 PCI1 PCI1 Output Control. 1 = enabled, 0 = forced LOW 0 1 PCI0 PCI0 Output Control. 1 = enabled, 0 = forced LOW ........................ Document #: 38-07509 Rev. *B Page 4 of 19 CY28346-2 Byte 3: PCIF Clock and 48M Control Register (all bits are read and write functional) Bit @Pup Name Description 7 1 48M_DOT 48M_DOT Output Control,1 = enabled, 0 = forced LOW 6 1 48M_USB 48M_USB Output Control,1 = enabled, 0 = forced LOW 5 0 PCIF2 PCI_STP#, control of PCIF2. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW 4 0 PCIF1 PCI_STP#, control of PCIF1. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW 3 0 PCIF0 PCI_STP#, control of PCIF0. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW 2 1 PCIF2 PCIF2 Output Control. 1=running, 0=forced LOW 1 1 PCIF1 PCIF1 Output Control. 1= running, 0=forced LOW 0 1 PCIF0 PCIF0 Output Control. 1= running, 0=forced LOW Byte 4: DRCG Control Register(all bits are read and write functional) Bit @Pup Name Description 7 0 SS2 Spread Spectrum control bit (0 = down spread, 1 = center spread) 6 0 Reserved 5 1 3V66_0 4 1 3V66_1/VCH 3 1 3V66_5 2 1 66B2/3V66_4 66B2/3V66_4 Output Enabled. 1 = enabled, 0 = disabled 1 1 66B1/3V66_3 66B1/3V66_3 Output Enabled. 1 = enabled, 0 = disabled 0 1 66B0/3V66_2 66B0/3V66_2 Output Enabled. 1 = enabled, 0 = disabled 3V66_0 Output Enabled. 1 = enabled, 0 = disabled 3V66_1/VCH Output Enable. 1 = enabled, 0 = disabled 3V66_5 Output Enable. 1 = enabled, 0 = disabled Byte 5: Clock Control Register (all bits are read and write functional) Bit @Pup Name Description 7 0 SS1 Spread Spectrum control bit 6 1 SS0 Spread Spectrum control bit 5 0 66IN to 66M delay Control MSB 4 0 66IN to 66M delay Control LSB 3 0 Reserved 2 0 48M_DOT edge rate control. When set to 1, the edge is slowed by 15%. 1 0 Reserved 0 0 USB edge rate control. When set to 1, the edge is slowed by 15% Byte 6: Silicon Signature Register[2] (all bits are read-only) Bit @Pup 7 0 6 0 5 0 4 1 3 0 2 0 1 1 0 1 Name Description Vendor Code, 011 = IMI Note: 2. When writing to this register the device will acknowledge the write operation, but the data itself will be ignored. ........................ Document #: 38-07509 Rev. *B Page 5 of 19 CY28346-2 Byte 7: Watchdog Time Stamp Register Bit @Pup Name Description 7 0 Reserved 6 0 Reserved 5 0 Reserved 4 0 Reserved 3 0 Reserved 2 0 Reserved 1 0 Reserved 0 0 Reserved Byte 8: Dial-a-Frequency Control Register N (all bits are read and write functional) Bit @Pup 7 0 Name N7, MSB Description 6 0 N6 5 0 N5 4 0 N4 3 0 N3 2 0 N2 1 0 N3 0 0 N0, LSB Byte 9: Dial-a-Frequency Control Register R (all bits are read and write functional) Bit @Pup 7 0 Name R6 MSB Description 6 0 R5 5 0 R4 4 0 R3 3 0 R2 2 0 R1 1 0 R0, LSB 0 0 R and N register load gate 0 = gate closed (data is latched), 1 = gate open (data is loading from SMBus registers into R and N) Dial-a-Frequency Feature Dial-a-dB Features SMBus Dial-a-Frequency feature is available in this device via Byte8 and Byte9. See our App Note AN-0025 for details on our Dial-a-Frequency feature. SMBus Dial-a-dB feature is available in this device via Byte8 and Byte9. P is a large value PLL constant that depends on the frequency selection achieved through the hardware selectors (S1, S0). P value may be determined from Table 3. Table 3. P Value S(1:0) P 00 32005333 01 48008000 10 96016000 11 64010667 ........................ Document #: 38-07509 Rev. *B Page 6 of 19 Spread Spectrum Clock Generation (SSCG) Spread Spectrum is a modulation technique used to minimizing EMI radiation generated by repetitive digital signals. A clock presents the greatest EMI energy at the center frequency it is generating. Spread Spectrum distributes this energy over a specific and controlled frequency bandwidth therefore causing the average energy at any one point in this band to decrease in value. This technique is achieved by modulating the clock away from its resting frequency by a certain percentage (which also determines the amount of EMI reduction). In this device, Spread Spectrum is enabled by setting specific register bits in the SMBus control Bytes. Table 4 is a listing of the modes and percentages of Spread Spectrum modulation that this device incorporates. CY28346-2 Configured as DRCG (66M), SMBus Byte0, Bit 5 = ‘0’ Table 4. Spread Spectrum The default condition for this pin is to power up in a 66M operation. In 66M operation this output is SSCG capable and when spreading is turned on, this clock will be modulated. SS2 SS1 SS0 Spread Mode Spread% 0 0 0 Down +0.00, –0.25 0 0 1 Down +0.00, –0.50 Configured as VCH (48M), SMBus Byte0, Bit 5 = ‘1’ 0 1 0 Down +0.00, –0.75 In this mode, the output is configured as a 48-MHz non-spread spectrum output. This output is phase aligned with the other 48M outputs (USB and DOT), to within 1 ns pin-to-pin skew. The switching of 3V66_1/VCH into VCH mode occurs at system power on. When the SMBus Bit 5 of Byte 0 is programmed from a ‘0’ to a ‘1’, the 3V66_1/VCH output may glitch while transitioning to 48M output mode. 0 1 1 Down +0.00, –1.00 1 0 0 Center +0.13, –0.13 1 0 1 Center +0.25, –0.25 1 1 0 Center +0.37, –0.37 1 1 1 Center +0.50, –1.50 Special Functions PCIF and IOAPIC Clock Outputs The PCIF clock outputs are intended to be used, if required, for systems IOAPIC clock functionality. ANY two of the PCIF clock outputs can be used as IOAPIC 33-MHz clock outputs. They are 3.3V outputs will be divided down via a simple resistive voltage divider to meet specific system IOAPIC clock voltage requirements. In the event these clocks are not required, then these clocks can be used as general PCI clocks or disabled via the assertion of the PCI_STP# pin. 3V66_1/VCH Clock Output The 3V66_1/VCH pin has a dual functionality that is selectable via SMBus. PD# (Power-down) Clarification The PD# (Power-down) pin is used to shut off ALL clocks prior to shutting off power to the device. PD# is an asynchronous active LOW input. This signal is synchronized internally to the device powering down the clock synthesizer. PD# is an asynchronous function for powering up the system. When PD# is low, all clocks are driven to a LOW value and held there and the VCO and PLLs are also powered down. All clocks are shut down in a synchronous manner so has not to cause glitches while transitioning to the low ‘stopped’ state. PD#—Assertion When PD# is sampled LOW by two consecutive rising edges of the CPUC clock, then on the next HIGH-to-LOW transition of PCIF, the PCIF clock is stopped LOW. On the next HIGH-to-LOW transition of 66Buff, the 66Buff clock is stopped LOW. From this time, each clock will stop LOW on its next HIGH-to-LOW transition, except the CPUT clock. The CPU clocks are held with the CPUT clock pin driven HIGH with a value of 2 x Iref, and CPUC undriven. After the last clock has stopped, the rest of the generator will be shut down. 66Buff PCIF PW RDW N# CPU 133MHz CPU# 133MHz 3V66 66In USB 48MHz REF 14.318MHz Figure 1. Power-down Assertion Timing Waveforms—Buffered Mode ........................ Document #: 38-07509 Rev. *B Page 7 of 19 CY28346-2 PW RDW N# C P U T 133M H z C P U C 133M H z P C I 33M H z A G P 66M H z U S B 48M H z R E F 1 4 .3 1 8 M H z D D R T 133M H z D D R C 133M H z S D R A M 133M H z Figure 2. Power-down Assertion Timing Waveforms—Unbuffered Mode PD# Deassertion The power-up latency between PD# rising to a valid logic ‘1’ level and the starting of all clocks is less than 3.0 ms. 30uS min 400uS max 0.25mS Sample Inputs straps VDDA = 2.0V Wait for