CY284108ZXC

CY284108 Clock Generator for Intel®Blackford and Bayshore Chipsets Features • Low-voltage frequency select input • I2C™ support with readback capabilities • Compliant with Intel CK410B • Supports Intel Pentium-4 and Xeon CPUs • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • Selectable CPU frequencies • 3.3V power supply • Four differential CPU clock pairs • 56-pin SSOP and TSSOP packages • Five 100 MHz Differential SRC clock pairs • Two buffered Reference Clocks @ 14.31818 MHz • One 48 MHz USB clock CPU SRC PCI REF USB x4 x5 x7 x2 x1 • Seven 33 MHz PCI clocks Block Diagram XIN XOUT CPU_STP# PCI_STP# XTAL OSC PLL1 Pin Configuration VDD_REF REF[0:1] PLL Ref Freq Divider Network VDD_CPU CPUT[0:3], CPUC[0:3], VDD_SRC SRCT[0:4], SRCC[0:4] FS_[C:A] VTT_PWRGD# IREF VDD_PCI PCI[0:3] PD VDD_48 MHz PLL2 SDATA SCLK USB_48 I2C Logic ........................ Document #: 38-07713 Rev. *B Page 1 of 16 400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1+(512) 416-9669 CY284108 VDD_PCIF PCIF[0:2] VDD_PCI VSS_PCI PCI_0 PCI_1 PCI_2 PCI_3 VSS_PCI VDD_PCI PCIF_0 PCIF_1 PCIF_2 VDD_48 USB_48 VSS_48 VDD_SRC SRCT0 SRCC0 SRCC1 SRCT1 VSS_SRC SRCT2 SRCC2 SRCC3 SRCT3 VDD_SRC SRCT4 SRCC4 VDD_SRC 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 FSC/TEST_SEL REF0 REF1 VDD_REF X1 X2 VSS_REF FSB/TEST_MODE FS_A VDD_CPU CPUT0 CPUC0 VDD_CPU CPUT1 CPUC1 VSS_CPU CPUT2 CPUC2 VDD_CPU CPUT3 CPUC3 VDDA VSSA IREF NC VTTPWRGD#**/PD SDATA SCLK www.silabs.com CY284108 Pin Description Name Pin Number Type X1 52 I X2 51 O, SE Description 14.18 MHz crystal input 14.18 MHz crystal output REF[1:0] 55, 54 O, SE 14.18 MHz reference clock PCI[3:0] 6,5,4,3 O, SE 33 MHz clocks PCIF[2:0] 11,10,9 O,SE 33 MHz free running clock. Is not disabled via Software PCI_STOP. USB_48 13 O, SE Fixed 48 MHz USB clock output CPU[T/C][3:0] 37,36;40,39; 43,42;46,45 O, DIF Differential CPU clock outputs SRC[T/C][4:0] 26,27;24,23; 21,22;19,18; 16,17 O, DIF Differential serial reference clocks. SRC[T/C]4 is recommended for SATA. FS_A 48 I 3.3V-tolerant input for CPU frequency selection. Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. FS_B/TEST_MODE 49 I 3.3V-tolerant inputs for CPU frequency selection/selects REF/N or Hi-Z when in test mode. Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. At VTTPWRGD# asserted low (see page 10 for diagram), this pin is sampled to determine test mode functionality 0 = Hi-Z 1 = REF/N FS_C/TEST_SEL 56 I 3.3V-tolerant inputs for CPU frequency selection/selects test mode if pulled to 3.3V when VTT_PWRGD# is asserted low (seepage 10 for diagram). Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications IREF 33 I A precision resistor is attached to this pin, which is connected to the internal current reference VTT_PWRGD#/PD 31 I, PD DF3.3V LVTTL input is a level sensitive strobe used to latch the FS_A, FS_B, FS_C/TEST_SEL inputs. After VTT_PWRGD# (active low) assertion, this pin becomes a realtime input for asserting power down (active high). See page 10 for diagram. SCLK 29 I SDATA 30 I/O SMBus-compatible SCLOCK VDD_REF 53 PWR 3.3V power supply for outputs VSS_REF 50 GND Ground for outputs VDD_PCI 1,8 PWR 3.3V power supply for outputs VSS_PCI 2,7 GND Ground for outputs VDD_48 12 PWR 3.3V power supply for outputs VSS_48 14 GND Differential CPU clock outputs VDD_SRC 15,25,28 PWR 3.3V power supply for outputs VSS_SRC 20 GND Ground for outputs VDD_CPU 38,44,47 PWR 3.3V power supply for outputs VSS_CPU 41 GND Ground for outputs VDD_A 35 PWR 3.3V power supply for outputs VSS_A 34 GND Ground for outputs NC 32 – SMBus-compatible SDATA No Connection ........................ Document #: 38-07713 Rev. *B Page 2 of 16 CY284108 Table 1. CPU Frequency Select Tables Frequency Select Pins (FS_[C:A]) Host clock frequency selection is achieved by applying the appropriate logic levels to FS_A, FS_B, FS_C inputs prior to VTT_PWRGD# assertion (as seen by the clock synthesizer). Upon VTT_PWRGD# being sampled low by the clock chip (indicating processor VTT voltage is stable), the clock chip samples the FS_A, FS_B, and FS_C input values. For all logic levels of FS_A, FS_B, and FS_C, VTT_PWRGD# employs a one-shot functionality in that once a valid low on VTT_PWRGD# has been sampled, all further VTT_PWRGD#, FS_A, FS_B, and FS_C transitions will be ignored, except in test mode. FS_C is a three level input, when sampled at a voltage greater than 2.0V by VTTPWRGD#, the device will enter test mode as selected by the voltage level on the FS_B input. Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 2. The block write and block read protocol is outlined in Table 3 while Table 4 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Table 2. Command Code Definition Bit 7 (6:0) Description 0 = Block read or block write operation, 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000' ........................ Document #: 38-07713 Rev. *B Page 3 of 16 CY284108 Table 3. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 Description Start Block Read Protocol Bit 1 Slave address – 7 bits 8:2 Description Start Slave address – 7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 Command Code – 8 bits 18:11 Command Code – 8 bits 19 Acknowledge from slave 19 Acknowledge from slave Byte Count – 8 bits (Skip this step if I2C_EN bit set) 20 Repeat start 27:20 28 36:29 37 45:38 Acknowledge from slave Data byte 1 – 8 bits Acknowledge from slave Data byte 2 – 8 bits 46 Acknowledge from slave .... Data Byte /Slave Acknowledges .... Data Byte N –8 bits .... Acknowledge from slave .... Stop 27:21 Slave address – 7 bits 28 Read = 1 29 Acknowledge from slave 37:30 38 46:39 47 55:48 Byte Count from slave – 8 bits Acknowledge Data byte 1 from slave – 8 bits Acknowledge Data byte 2 from slave – 8 bits 56 Acknowledge .... Data bytes from slave / Acknowledge .... Data Byte N from slave – 8 bits .... NOT Acknowledge .... Stop Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 Description Start Slave address – 7 bits Byte Read Protocol Bit 1 8:2 Description Start Slave address – 7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 Command Code – 8 bits 18:11 Command Code – 8 bits 19 Acknowledge from slave 19 Acknowledge from slave 27:20 Data byte – 8 bits 28 Acknowledge from slave 29 Stop 20 27:21 Repeated start Slave address – 7 bits 28 Read 29 Acknowledge from slave 37:30 Data from slave – 8 bits 38 NOT Acknowledge 39 Stop Control Registers ........................ Document #: 38-07713 Rev. *B Page 4 of 16 CY284108 Byte 0: Control Register 0 Bit @Pup Name Description 7 1 RESERVED RESERVED 6 1 RESERVED RESERVED 5 1 RESERVED RESERVED 4 1 SRC[T/C]4 SRC[T/C]4 Output Enable 0 = Disable (Tri-state), 1 = Enable 3 1 SRC[T/C]3 SRC[T/C]3 Output Enable 0 = Disable (Tri-state), 1 = Enable 2 1 SRC[T/C]2 SRC[T/C]2 Output Enable 0 = Disable (Tri-state), 1 = Enable 1 1 SRC[T/C]1 SRC[T/C]1 Output Enable 0 = Disable (Tri-state), 1 = Enable 0 1 SRC[T/C]0 SRC[T/C]0 Output Enable 0 = Disable (Tri-state), 1 = Enable Byte 1: Control Register 1 Bit @Pup Name 7 1 REF1 REF1 Output Enable 0 = Disable, 1 = Enable Description 6 1 REF0 REF0 Output Enable 0 = Disable, 1 = Enable 5 1 CPU[T/C]3 CPU[T/C]3 Output Enable 0 = Disable (Tri-state), 1 = Enable 4 1 CPU[T/C]2 CPU[T/C]2 Output Enable 0 = Disable (Tri-state), 1 = Enable 3 1 RESERVED 2 1 CPU[T/C]1 CPU[T/C]1 Output Enable 0 = Disable (Tri-state), 1 = Enable 1 1 CPU[T/C]0 CPU[T/C]0 Output Enable 0 = Disable (Tri-state), 1 = Enable 0 0 CPU SRC PCIF PCI RESERVED PLL1 Spread Spectrum Enable 0 = Spread off, 1 = Spread on Byte 2: Control Register 2 Bit @Pup Name 7 1 PCI3 PCI3 Output Enable 0 = Disable, 1 = Enable Description 6 1 PCI2 PCI2 Output Enable 0 = Disable, 1 = Enable 5 1 PCI1 PCI1 Output Enable 0 = Disable, 1 = Enable 4 1 PCI0 PCI0 Output Enable 0 = Disable, 1 = Enable 3 1 PCIF2 PCIF2 Output Enable 0 = Disable, 1 = Enable 2 1 PCIF1 PCIF1 Output Enable 0 = Disable, 1 = Enable 1 1 PCIF0 PCIF0 Output Enable 0 = Disable, 1 = Enable ........................ Document #: 38-07713 Rev. *B Page 5 of 16 CY284108 Byte 2: Control Register 2 (continued) Bit @Pup Name 0 1 USB48 Description USB_48 Output Enable 0 = Disable, 1 = Enable Byte 3: Control Register 3 Bit @Pup Name Description 7 0 PCIF2 Allow control of PCIF2 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with SW PCI_STP# 6 0 PCIF1 Allow control of PCIF1 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with SW PCI_STP# 5 0 PCIF0 Allow control of PCIF0 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with SW PCI_STP# 4 0 SRC[T/C]4 Allow control of SRC[T/C]4 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 3 0 SRC[T/C]3 Allow control of SRC[T/C]3 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 2 0 SRC[T/C]2 Allow control of SRC[T/C]2 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 1 0 SRC[T/C]1 Allow control of SRC[T/C]1 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 0 0 SRC[T/C]0 Allow control of SRC[T/C]0 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Byte 4: Control Register 4 Bit @Pup Name 7 0 CPU[T/C]3 CPU[T/C]3 PD drive mode 0 = Driven in power down, 1 = Tri-state Description 6 0 CPU[T/C]2 CPU[T/C]2 PD drive mode 0 = Driven in power down, 1 = Tri-state 5 0 CPU[T/C]1 CPU[T/C]1 PD drive mode 0 = Driven in power down, 1 = Tri-state 4 0 CPU[T/C]0 CPU[T/C]0 PD drive mode 0 = Driven in power down, 1 = Tri-state 3 0 RESERVED RESERVED 2 0 RESERVED RESERVED 1 0 RESERVED RESERVED 0 0 RESERVED RESERVED Byte 5: Control Register 5 Bit @Pup Name 7 0 RESERVED Description 6 0 SRC[T/C][4:0] PCI_STP# Stoppable SRC[T/C][4:0] drive mode upon PCI_STP# assertion drive mode 0 = Driven in PCI_STOP#, 1 = Tri-state 5 0 SRC[T/C][4:0] PWRDWN SRC[T/C][4:0] PWRDWN drive mode Drive mode 0 = Driven in power down, 1 = Tri-state 4 0 RESERVED RESERVED, Set = 0 3 0 RESERVED RESERVED 2 0 RESERVED RESERVED 1 0 RESERVED RESERVED RESERVED ........................ Document #: 38-07713 Rev. *B Page 6 of 16 CY284108 Byte 5: Control Register 5 (continued) Bit @Pup Name 0 0 RESERVED Description RESERVED Byte 6: Control Register 6 Bit @Pup Name 7 0 TEST_SEL Description 6 0 TEST_MODE 5 0 RESERVED 4 1 REF 3 1 PCI_Stop Control 2 HW FS_C FS_C Reflects the value of the FS_C pin sampled on power up 0 = FS_C was low during VTT_PWRGD# assertion 1 HW FS_B FS_B Reflects the value of the FS_B pin sampled on power up 0 = FS_B was low during VTT_PWRGD# assertion 0 HW FS_A FS_A Reflects the value of the FS_A pin sampled on power up 0 = FS_A was low during VTT_PWRGD# assertion REF/N or Tri-state Select 0 = Tri-state, 1 = REF/N Clock Test Clock Mode Entry Control 0 = Normal operation, 1 = REF/N or Tri-state mode RESERVED, Set = 0 REF Output Drive Strength 0 = Low, 1 = High SW PCI_STP# Function 0 = SW PCI_STP# assert, 1 = SW PCI_STP# deassert When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will be stopped in a synchronous manner with no short pulses. When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will resume in a synchronous manner with no short pulses. Byte 7: Vendor ID Bit @Pup Name 7 0 Revision Code Bit 3 Revision Code Bit 3 Description 6 0 Revision Code Bit 2 Revision Code Bit 2 5 0 Revision Code Bit 1 Revision Code Bit 1 4 0 Revision Code Bit 0 Revision Code Bit 0 3 1 Vendor ID Bit 3 Vendor ID Bit 3 2 0 Vendor ID Bit 2 Vendor ID Bit 2 1 0 Vendor ID Bit 1 Vendor ID Bit 1 0 0 Vendor ID Bit 0 Vendor ID Bit 0 ........................ Document #: 38-07713 Rev. *B Page 7 of 16 CY284108 Table 5. Crystal Recommendations Frequency (Fund) Cut Loading Load Cap Drive (max.) Shunt Cap (max.) Motional (max.) Tolerance (max.) Stability (max.) Aging (max.) 14.31818 MHz AT Parallel 0.1 mW 5 pF 0.016 pF 35 ppm 30 ppm 5 ppm 20 pF The CY284108 requires a parallel resonance crystal. Substituting a series resonance crystal will cause the CY284108 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. Clock Chip Ci2 Ci1 Pin 3 to 6p Crystal Loading Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance the crystal will see must be considered to calculate the appropriate capacitive loading (CL). Figure shows a typical crystal configuration using the two trim capacitors. An important clarification for the following discussion is that the trim capacitors are in series with the crystal not parallel. It is a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. This is not true. X2 X1 Cs1 Cs2 Trace 2.8 pF XTAL Ce1 Ce2 Trim 33 pF Figure 3. Crystal Loading Example Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Load Capacitance (each side) Ce = 2 * CL – (Cs + Ci) Total Capacitance (as seen by the crystal) CLe Figure 1. Crystal Capacitive Clarification Calculating Load Capacitors In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides. Figure 2. ........................ Document #: 38-07713 Rev. *B Page 8 of 16 = 1 1 ( Ce1 + Cs1 + Ci1 + 1 Ce2 + Cs2 + Ci2 ) CL....................................................Crystal load capacitance CLe......................................... Actual loading seen by crystal using standard value trim capacitors Ce..................................................... External trim capacitors Cs .............................................. Stray capacitance (terraced) Ci ...........................................................Internal capacitance (lead frame, bond wires etc.) PD (Power-down) Clarification The VTT_PWRGD# /PD pin is a dual-function pin. During initial power up, the pin functions as VTT_PWRGD#. Once VTT_PWRGD# has been sampled low by the clock chip, the pin assumes PD functionality. The PD pin is an asynchronous active HIGH input used to shut off all clocks cleanly prior to shutting off power to the device. This signal is synchronized internal to the device prior to powering down the clock synthesizer. PD is also an asynchronous input for powering up the system. When PD is asserted high, drive all clocks to a low value and hold prior to turning off the VCOs and the crystal oscillator. CY284108 PD (Power-down) Assertion When PD is sampled high by two consecutive rising edges of CPUC, all single-ended outputs will be held low on their next high to low transition and differential clocks must held high or tri-stated (depending on the state of the control register drive mode bit) on the next diff clock# high to low transition within 4 clock periods. When the SMBus PD drive mode bit corresponding to the differential (CPU and SRC) clock output of interest is programmed to ‘0’, the clock outputs are held with “Diff clock” pin driven high at 2 x Iref, and “Diff clock#” tri-state. If the control register PD drive mode bit corresponding to the output of interest is programmed to “1”, then both the “Diff clock” and the “Diff clock#” are tri-state. Note that Figure 4 shows CPUT = 133 MHz and PD drive mode = ‘1’ for all differential outputs. This diagram and description is applicable to valid CPU frequencies 100, 133, 166, 200, 266, 333, and 400 MHz. In the event that PD mode is desired as the initial power-on state, PD must be asserted high in less than 10 s after asserting Vtt_PwrGd#. PD Deassertion The power-up latency is less than 1.8 ms. This is the time from the deassertion of the PD pin or the ramping of the power supply until the time that stable clocks are output from the clock chip. All differential outputs stopped in a three-state condition resulting from power down will be driven high in less than 300 s of PD deassertion to a voltage greater than 200 mV. After the clock chip’s internal PLL is powered up and locked, all outputs will be enabled within a few clock cycles of each other. Figure 5 is an example showing the relationship of clocks coming up. PD CPUT, 133 MHz CPUC, 133 MHz SRCT 100 MHz SRCC 100 MHz USB, 48 MHz PCI, 33 MHz REF Figure 4. Power-down Assertion Timing Waveform Tstable 0.25 ms VTT_PWRGD# = Low Sample Inputs straps VDD_A = 2.0V Wait for