CY28410OXC

CY28410 Clock Generator for Intel®Grantsdale Chipset Features • 33 MHz PCI clock • Low-voltage frequency select input • Compliant with Intel CK410 • I2C support with readback capabilities • Supports Intel P4 and Tejas CPU • Selectable CPU frequencies • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • Differential CPU clock pairs • 3.3V power supply • 100 MHz differential SRC clocks • 56-pin SSOP and TSSOP packages • 96 MHz differential dot clock • 48 MHz USB clocks CPU SRC PCI REF DOT96 USB_48 x2 / x3 x6 / x7 x9 x1 x1 x1 Block Diagram XIN XOUT XTAL OSC PLL1 FS_[C:A] VTT_PWRGD# IREF PLL2 SDATA SCLK I2C Logic VDD_REF REF PLL Ref Freq Divider Network VDD_PCI VSS_PCI PCI3 VDD_CPU PCI4 CPUT[0:1], CPUC[0:1], CPU(T/C)2_ITP] PCI5 VDD_SRC VSS_PCI SRCT[1:6], SRCC[1:6] VDD_PCI PCIF0/ITP_EN PCIF1 PCIF2 VDD_PCI VDD_48 PCI[0:5] USB_48 VDD_PCIF PCIF[0:2] VSS_48 DOT96T DOT96C VDD_48 MHz FS_B/TEST_MODE DOT96T VTT_PWRGD#/PD DOT96C FS_A USB_48 SRCT1 SRCC1 VDD_SRC SRCT2 SRCC2 SRCT3 SRCC3 SRC4-SATAT SRC4_SATAC VDD_SRC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 CY28410 PD Pin Configuration 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 PCI2 PCI1 PCI0 FS_C/TEST_SEL REF VSS_REF XIN XOUT VDD_REF SDATA SCLK VSS_CPU CPUT0 CPUC0 VDD_CPU CPUT1 CPUC1 IREF VSSA VDDA CPUT2_ITP/SRCT7 CPUC2_ITP/SRCC7 VDD_SRC SRCT6 SRCC6 SRCT5 SRCC5 VSS_SRC 56 SSOP/TSSOP ........................ Document #: 38-07593 Rev. *C Page 1 of 17 400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com CY28410 Pin Definitions Pin No. Name Type Description 44,43,41,40 CPUT/C 36,35 CPUT2_ITP/SRCT7, O, DIF Selectable Differential CPU or SRC clock output. CPUC2_ITP/SRCC7 ITP_EN = 0 @ VTT_PWRGD# assertion = SRC7 ITP_EN = 1 @ VTT_PWRGD# assertion = CPU2 O, DIF Differential CPU clock outputs. 14,15 DOT96T, DOT96C 18 FS_A I 3.3V tolerant input for CPU frequency selection. Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. 16 FS_B/TEST_MODE I 3.3V tolerant input for CPU frequency selection. Selects Ref/N or Hi-Z when in test mode 0 = Hi-Z,1 = Ref/N Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. 53 FS_C/TEST_SEL I 3.3V tolerant input for CPU frequency selection. Selects test mode if pulled to VIHFS_C when VTT_PWRGD# is asserted low. Refer to DC Electrical Specifications table for VILFS_C,VIMFS_C,VIHFS_C specifications. 39 IREF I A Precision resistor is attached to this pin, which is connected to the internal current reference. 54,55,56,3,4,5 PCI O, DIF Fixed 96-MHz clock output. O, SE 33-MHz clocks. 9,10 PCIF O, SE 33-MHz clocks. 8 PCIF0/ITP_EN I/O, SE 33-MHz clock/CPU2 select (sampled on the VTT_PWRGD# assertion). 1 = CPU2_ITP, 0 = SRC7 52 REF O, SE Reference clock. 3.3V 14.318 MHz clock output. 46 SCLK I 47 SDATA I/O 26,27 SRC4_SATAT, SRC4_SATAC SMBus-compatible SCLOCK. SMBus-compatible SDATA. O, DIF Differential serial reference clock. recommended output for SATA. 19,20,22,23,2 SRCT/C 4,25,31,30,33, 32 O, DIF Differential serial reference clocks. 12 USB_48 I/O, SE Fixed 48 MHz clock output. 11 VDD_48 PWR 3.3V power supply for outputs. 42 VDD_CPU PWR 3.3V power supply for outputs. 1,7 VDD_PCI PWR 3.3V power supply for outputs. 48 VDD_REF PWR 3.3V power supply for outputs. 21,28,34 VDD_SRC PWR 3.3V power supply for outputs. 37 VDDA PWR 3.3V power supply for PLL. 13 VSS_48 GND Ground for outputs. 45 VSS_CPU GND Ground for outputs. 2,6 VSS_PCI GND Ground for outputs. 51 VSS_REF GND Ground for outputs. 29 VSS_SRC GND Ground for outputs. 38 VSSA GND Ground for PLL. 17 VTT_PWRGD#/PD I, PU 3.3V LVTTL input is a level sensitive strobe used to latch the USB_48/FS_A, FS_B, FS_C/TEST_SEL and PCIF0/ITP_EN inputs. After VTT_PWRGD# (active low) assertion, this pin becomes a realtime input for asserting power-down (active high) 50 XIN 49 XOUT I 14.318-MHz Crystal Input O, SE 14.318-MHz Crystal Output ........................Document #: 38-07593 Rev. *C Page 2 of 17 CY28410 Frequency Select Pins (FS_A, FS_B and FS_C) Host clock frequency selection is achieved by applying the appropriate logic levels to FS_A, FS_B, FS_C inputs prior to VTT_PWRGD# assertion (as seen by the clock synthesizer). Upon VTT_PWRGD# being sampled low by the clock chip (indicating processor VTT voltage is stable), the clock chip samples the FS_A, FS_B and FS_C input values. For all logic levels of FS_A, FS_B and FS_C, VTT_PWRGD# employs a one-shot functionality in that once a valid low on VTT_PWRGD# has been sampled, all further VTT_PWRGD#, FS_A, FS_B and FS_C transitions will be ignored, except in test mode. Table 1. Frequency Select Table FS_A, FS_B and FS_C FS_C FS_B FS_A CPU SRC PCIF/PCI REF0 DOT96 USB MID 0 1 100 MHz 100 MHz 33 MHz 14.318 MHz 96 MHz 48 MHz 0 0 1 133 MHz 100 MHz 33 MHz 14.318 MHz 96 MHz 48 MHz 0 1 0 200 MHz 100 MHz 33 MHz 14.318 MHz 96 MHz 48 MHz 0 0 0 266 MHz 100 MHz 33 MHz 14.318 MHz 96 MHz 48 MHz 1 0 x Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 1 1 0 REF/2 REF/8 REF/24 REF REF REF 1 1 1 REF/2 REF/8 REF/24 REF REF REF Serial Data Interface Data Protocol To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions. The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 2. The block write and block read protocol is outlined in Table 3 while Table 4 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Table 2. Command Code Definition Bit 7 (6:0) Description 0 = Block read or block write operation, 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000' Table 3. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 Description Start Slave address – 7 bits Block Read Protocol Bit 1 8:2 Description Start Slave address – 7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 Command Code – 8 bits 18:11 Command Code – 8 bits 19 Acknowledge from slave 19 Acknowledge from slave Byte Count – 8 bits (Skip this step if I2C_EN bit set) 20 Repeat start 27:20 28 36:29 37 45:38 Acknowledge from slave Data byte 1 – 8 bits Acknowledge from slave Data byte 2 – 8 bits ........................Document #: 38-07593 Rev. *C Page 3 of 17 27:21 Slave address – 7 bits 28 Read = 1 29 Acknowledge from slave 37:30 Byte Count from slave – 8 bits CY28410 Table 3. Block Read and Block Write Protocol (continued) Block Write Protocol Bit 46 Block Read Protocol Description Bit Acknowledge from slave .... Data Byte /Slave Acknowledges .... Data Byte N –8 bits .... Acknowledge from slave .... Stop 38 46:39 47 55:48 Description Acknowledge Data byte 1 from slave – 8 bits Acknowledge Data byte 2 from slave – 8 bits 56 Acknowledge .... Data bytes from slave / Acknowledge .... Data Byte N from slave – 8 bits .... NOT Acknowledge .... Stop Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 Byte Read Protocol Description Bit Start 1 Slave address – 7 bits 8:2 Description Start Slave address – 7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 Command Code – 8 bits 18:11 Command Code – 8 bits 19 Acknowledge from slave 19 Acknowledge from slave 27:20 Data byte – 8 bits 20 28 Acknowledge from slave 29 Stop 27:21 Repeated start Slave address – 7 bits 28 Read 29 Acknowledge from slave 37:30 Data from slave – 8 bits 38 NOT Acknowledge 39 Stop Control Registers Byte 0:Control Register 0 Bit @Pup Name 7 1 CPUT2_ITP/SRCT7 CPUC2_ITP/SRCC7 Description 6 1 SRC[T/C]6 SRC[T/C]6 Output Enable 0 = Disable (Hi-Z), 1 = Enable 5 1 SRC[T/C]5 SRC[T/C]5 Output Enable 0 = Disable (Hi-Z), 1 = Enable 4 1 SRC[T/C]4 SRC[T/C]4 Output Enable 0 = Disable (Hi-Z), 1 = Enable 3 1 SRC[T/C]3 SRC[T/C]3 Output Enable 0 = Disable (Hi-Z), 1 = Enable 2 1 SRC[T/C]2 SRC[T/C]2 Output Enable 0 = Disable (Hi-Z), 1 = Enable 1 1 SRC[T/C]1 SRC[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enable 0 1 Reserved Reserved, Set = 1 CPU[T/C]2_ITP/SRC[T/C]7 Output Enable 0 = Disable (Hi-Z), 1 = Enable ........................Document #: 38-07593 Rev. *C Page 4 of 17 CY28410 Byte 1: Control Register 1 Bit @Pup Name Description 7 1 PCIF0 6 1 DOT_96T/C 5 1 USB_48 4 1 REF 3 0 Reserved Reserved 2 1 CPU[T/C]1 CPU[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enabled 1 1 CPU[T/C]0 CPU[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enabled 0 0 CPUT/C SRCT/C PCIF PCI PCIF0 Output Enable 0 = Disabled, 1 = Enabled DOT_96 MHz Output Enable 0 = Disable (Hi-Z), 1 = Enabled USB_48 MHz Output Enable 0 = Disabled, 1 = Enabled REF Output Enable 0 = Disabled, 1 = Enabled Spread Spectrum Enable 0 = Spread off, 1 = Spread on Byte 2: Control Register 2 Bit @Pup Name Description 7 1 PCI5 PCI5 Output Enable 0 = Disabled, 1 = Enabled 6 1 PCI4 PCI4 Output Enable 0 = Disabled, 1 = Enabled 5 1 PCI3 PCI3 Output Enable 0 = Disabled, 1 = Enabled 4 1 PCI2 PCI2 Output Enable 0 = Disabled, 1 = Enabled 3 1 PCI1 PCI1 Output Enable 0 = Disabled, 1 = Enabled 2 1 PCI0 PCI0 Output Enable 0 = Disabled, 1 = Enabled 1 1 PCIF2 PCIF2 Output Enable 0 = Disabled, 1 = Enabled 0 1 PCIF1 PCIF1 Output Enable 0 = Disabled, 1 = Enabled Byte 3: Control Register 3 Bit @Pup Name Description 7 0 SRC7 Allow control of SRC[T/C]7 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with SW PCI_STP# 6 0 SRC6 Allow control of SRC[T/C]6 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with SW PCI_STP# 5 0 SRC5 Allow control of SRC[T/C]5 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with SW PCI_STP# 4 0 SRC4 Allow control of SRC[T/C]4 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with SW PCI_STP# 3 0 SRC3 Allow control of SRC[T/C]3 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with SW PCI_STP# 2 0 SRC2 Allow control of SRC[T/C]2 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with SW PCI_STP# ........................Document #: 38-07593 Rev. *C Page 5 of 17 CY28410 Byte 3: Control Register 3 (continued) Bit @Pup Name 1 0 SRC1 0 0 Reserved Description Allow control of SRC[T/C]1 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with SW PCI_STP# Reserved, Set = 0 Byte 4: Control Register 4 Bit @Pup Name Description 7 0 Reserved 6 0 DOT96[T/C] 5 0 PCIF2 Allow control of PCIF2 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with SW PCI_STP# 4 0 PCIF1 Allow control of PCIF1 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with SW PCI_STP# 3 0 PCIF0 Allow control of PCIF0 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with SW PCI_STP# 2 1 Reserved Reserved, Set = 1 1 1 Reserved Reserved, Set = 1 0 1 Reserved Reserved, Set = 1 Reserved, Set = 0 DOT_PWRDWN Drive Mode 0 = Driven in PWRDWN, 1 = Hi-Z Byte 5: Control Register 5 Bit @Pup Name Description 7 0 SRC[T/C][7:0] 6 0 Reserved Reserved, Set = 0 5 0 Reserved Reserved, Set = 0 4 0 Reserved Reserved, Set = 0 3 0 SRC[T/C][7:0] SRC[T/C] PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted 2 0 CPU[T/C]2 CPU[T/C]2 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted 1 0 CPU[T/C]1 CPU[T/C]1 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted 0 0 CPU[T/C]0 CPU[T/C]0 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted SRC[T/C] Stop Drive Mode 0 = Driven when SW PCI_STP# asserted,1 = Hi-Z when PCI_STP# asserted Byte 6: Control Register 6 Bit @Pup 7 0 Name REF/N or Hi-Z Select 1 = REF/N Clock, 0 = Hi-Z Description 6 0 Test Clock Mode Entry Control 1 = REF/N or Hi-Z mode, 0 = Normal operation 5 0 Reserved 4 1 REF 3 1 PCIF, SRC, PCI Reserved, Set = 0 REF Output Drive Strength 0 = Low, 1 = High SW PCI_STP# Function 0=SW PCI_STP assert, 1 = SW PCI_STP deassert When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will be stopped in a synchronous manner with no short pulses. When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will resume in a synchronous manner with no short pulses. ........................Document #: 38-07593 Rev. *C Page 6 of 17 CY28410 Byte 6: Control Register 6 (continued) Bit @Pup Name Description 2 Externally selected CPUT/C FS_C. Reflects the value of the FS_C pin sampled on power-up 0 = FS_C was low during VTT_PWRGD# assertion 1 Externally selected CPUT/C FS_B. Reflects the value of the FS_B pin sampled on power-up 0 = FS_B was low during VTT_PWRGD# assertion 0 Externally selected CPUT/C FS_A. Reflects the value of the FS_A pin sampled on power-up 0 = FS_A was low during VTT_PWRGD# assertion Byte 7: Vendor ID Bit @Pup 7 0 Revision Code Bit 3 Name Revision Code Bit 3 Description 6 0 Revision Code Bit 2 Revision Code Bit 2 5 1 Revision Code Bit 1 Revision Code Bit 1 4 0 Revision Code Bit 0 Revision Code Bit 0 3 1 Vendor ID Bit 3 Vendor ID Bit 3 2 0 Vendor ID Bit 2 Vendor ID Bit 2 1 0 Vendor ID Bit 1 Vendor ID Bit 1 0 0 Vendor ID Bit 0 Vendor ID Bit 0 Crystal Recommendations Crystal Loading The CY28410 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28410 to operate at the wrong frequency and \violate the ppm specification. For most applications there is a 300ppm frequency shift between series and parallel crystals due to incorrect loading. Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance the crystal will see must be considered to calculate the appropriate capacitive loading (CL). The following diagram shows a typical crystal configuration using the two trim capacitors. An important clarification for the following discussion is that the trim capacitors are in series with the crystal not parallel. It’s a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. This is not true. Table 5. Crystal Recommendations Frequency (Fund) Cut Loading Load Cap Drive (max.) Shunt Cap (max.) Motional (max.) Tolerance (max.) Stability (max.) Aging (max.) 14.31818 MHz AT Parallel 0.1 mW 5 pF 0.016 pF 35 ppm 30 ppm 5 ppm 20 pF ........................Document #: 38-07593 Rev. *C Page 7 of 17 CY28410 Figure 1. Crystal Capacitive Clarification Calculating Load Capacitors In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides. Clock Chip Ci2 Ci1 Pin 3 to 6p X2 X1 Cs1 Cs2 Trace 2.8pF XTAL Ce1 Ce2 Trim 33pF Figure 2. Crystal Loading Example As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This mean the total capacitance on each side of the crystal must be twice the specified load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors(Ce1,Ce2) should be calculated to provide equal capacitance loading on both sides. Use the following formulas to calculate the trim capacitor values fro Ce1 and Ce2. ........................Document #: 38-07593 Rev. *C Page 8 of 17 Load Capacitance (each side) Ce = 2 * CL – (Cs + Ci) Total Capacitance (as seen by the crystal) CLe = 1 1 ( Ce1 + Cs1 + Ci1 + 1 Ce2 + Cs2 + Ci2 ) CY28410 CL ................................................... Crystal load capacitance CLe .........................................Actual loading seen by crystal using standard value trim capacitors Ce .....................................................External trim capacitors Cs ............................................. Stray capacitance (terraced) Ci .......................................................... Internal capacitance (lead frame, bond wires etc.) PD (Power-down) Clarification The VTT_PWRGD# /PD pin is a dual function pin. During initial power-up, the pin functions as VTT_PWRGD#. Once VTT_PWRGD# has been sampled low by the clock chip, the pin assumes PD functionality. The PD pin is an asynchronous active high input used to shut off all clocks cleanly prior to shutting off power to the device. This signal is synchronized internal to the device prior to powering down the clock synthesizer. PD is also an asynchronous input for powering up the system. When PD is asserted high, all clocks are driven to a low value and held prior to turning off the VCOs and the crystal oscillator. PD (Power-down) – Assertion When PD is sampled high by two consecutive rising edges of CPUC, all single-ended outputs will be held low on their next high to low transition and differential clocks must be held high or Hi-Z (depending on the state of the control register drive mode bit) on the next diff clock# high to low transition within 4 clock periods. When the SMBus PD drive mode bit corresponding to the differential (CPU, SRC, and DOT) clock output of interest is programmed to ‘0’, the clock output must be held with “Diff clock” pin driven high at 2 x Iref, and “Diff clock#” tristate. If the control register PD drive mode bit corresponding to the output of interest is programmed to “1”, then both the “Diff clock” and the “Diff clock#” are Hi-Z. Note the example below shows CPUT = 133 MHz and PD drive mode = ‘1’ for all differential outputs. This diagram and description is applicable to valid CPU frequencies 100,133,166,200,266,333, and 400 MHz. In the event that PD mode is desired as the initial power-on state, PD must be asserted high in less than 10 uS after asserting VTT_PWRGD#. PD Deassertion The power-up latency is less than 1.8 ms. This is the time from the deassertion of the PD pin or the ramping of the power supply until the time that stable clocks are output from the clock chip. All differential outputs stopped in a three-state condition resulting from power-down must be driven high in less than 300 s of PD deassertion to a voltage greater than 200 mV. After the clock chip’s internal PLL is powered up and locked, all outputs are enabled within a few clock cycles of each other. Below is an example showing the relationship of clocks coming up. PD CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz DOT96T DOT96C PCI, 33 MHz REF Figure 3. Power-down Assertion Timing Waveform ........................Document #: 38-07593 Rev. *C Page 9 of 17 CY28410 Tstable 0.25m S VTT_PW R G D# = Low S am ple Inputs straps VDD _A = 2.0V W ait for