CY28442-2
Clock Generator for Intel®Alviso Chipset
Features
• 96 /100 MHz Spreadable differential clock.
• 33 MHz PCI clock
• Compliant to Intel CK410M
• Low-voltage frequency select input
• Supports Intel Pentium-M CPU
• I2C support with readback capabilities
• Selectable CPU frequencies
• Differential CPU clock pairs
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 100 MHz differential SRC clocks
• 3.3V power supply
• 96 MHz differential dot clock
• 56-pin TSSOP package
• 48 MHz USB clocks
• SRC clocks independently stoppable through
CLKREQ#[A:B]
CPU
SRC
PCI
REF
DOT96
USB_48
x2 / x3
x5/6
x6
x2
x2
x1
Block Diagram
XIN
XOUT
Pin Configuration
14.318MHz
Crystal
PCI_STP#
PLL1
CPU
CPU_STP#
CLKREQ[A:B]#
PLL Reference
Divider
VDD_REF
REF
IREF
VDD_CPU
CPUT
CPUC
VDD_CPU
CPUT_ITP/SRCT7
CPUC_ITP/SRCC7
FS_[C:A]
PCI
VDD_PCI
PCIF
PLL2
96MSS
Divider
PLL3
FIXED
Divider
VDD_48MHz
96_100_SSCT
96_100_SSCC
VDD_48MHz
DOT96T
DOT96C
VDD_48
USB
VTTPWR_GD#/PD
SDATA
SCLK
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PCI2/SEL_CLKREQ**
PCI_STP#
CPU_STP#
FS_C(TEST_SEL)/REF0
REF1
VSSA2
XIN
XOUT
VDDA2
SDATA
SCLK
VSS_CPU
CPUT0
CPUC0
VDD_CPU
CPUT1
CPUC1
IREF
VSSA
VDDA
CPU2T_ITP/SRCT7
CPU2C_ITP/SRCC7
VDD_SRC_ITP
CLKREQA#/SRCT6
CLKREQB#/SRCC6
SRCT5
SRCC5
VSS_SRC
56 pin TSSOP/SSOP
I2C
Logic
....................... Document #: 38-07691 Rev. *B Page 1 of 19
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
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CY28442-2
VDD_SRC
SRCT[1:5]
CPUC[1:5]
VDD_PCI
VDD_REF
VSS_REF
PCI3
PCI4
PCI5
VSS_PCI
VDD_PCI
ITP_EN/PCIF0
**96_100_SEL/PCIF1
VTTPWRGD#/PD
VDD_48
FS_A/48M_0
VSS_48
DOT96T
DOT96C
FS_B/TESTMODE
96_100_SSCT
96_100_SSCC
SRCT1
SRCC1
VDD_SRC
SRCT2
SRCC2
SRCT3
SRCC3
SRCT4_SATA
SRCC4_SATA
VDD_SRC
1+(512) 416-9669
www.silabs.com
CY28442-2
Pin Definitions
Pin No.
Name
Type
Description
1
VDD_REF
PWR
3.3V power supply for output
2
VSS_REF
GND
Ground for outputs.
33,32
CLKREQA#/SRCT6, I/O, PU 3.3V LVTTL input for enabling assigned SRC clock (active LOW) or 100-MHz
CLKREQB#,SRCC6
Serial Reference Clock.
Selectable through CLKREQA# defaults to enable/disable SRCT/C4, CLKREQB#
defaults to enable/disable SRCT/C5. Assignment can be changed via SMBUS
register Byte 8.
7
VDD_PCI
PWR
3.3V power supply for outputs.
Ground for outputs.
6
VSS_PCI
GND
3,4,5
PCI
O, SE 33 MHz clock
8
ITP_EN/PCIF0
I/O, SE 3.3V LVTTL input to enable SRC7 or CPU2_ITP/33-MHz clock output.
(sampled on the VTT_PWRGD# assertion).
1 = CPU2_ITP, 0 = SRC7
9
PCIF1/96_100_SEL
I/O, 33 MHz clock/3.3V-tolerant input for 96_100M frequency selection
PD,SE (sampled on the VTT_PWRGD# assertion).
1 = 100 MHz, 0 = 96 MHz
10
VTT_PWRGD#/PD
I, PU
PWR
11
VDD_48
12
FS_A/48_M0
13
VSS_48
14,15
DOT96T, DOT96C
16
FS_B/TEST_MODE
17,18
96_100_SSC
19,20,22,23, SRCT/C
24,25,30,31
I/O
GND
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A,
FS_B, FS_C and ITP_EN, 96MSS_SRC_SEL inputs, SEL_CLKREQ. After
VTT_PWRGD# (active LOW) assertion, this pin becomes a real-time input for
asserting power-down (active HIGH).
3.3V power supply for outputs.
3.3V-tolerant input for CPU frequency selection/fixed 48-MHz clock output.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
Ground for outputs.
O, DIF Fixed 96 MHz clock output.
I
3.3V-tolerant input for CPU frequency selection. Selects Ref/N or Tri-state
when in test mode
0 = Tri-state, 1 = Ref/N
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
O,DIF Differential 96 /100 MHz SS clock for flat-panel display
O, DIF 100 MHz Differential serial reference clocks.
21,28
VDD_SRC
PWR
3.3V power supply for outputs.
34
VDD_SRC_ITP
PWR
3.3V power supply for outputs.
26,27
SRC4_SATAT,
SRC4_SATAC
29
VSS_SRC
36,35
CPUT2_ITP/SRCT7, O, DIF Selectable differential CPU or SRC clock output.
CPUC2_ITP/SRCC7
ITP_EN = 0 @ VTT_PWRGD# assertion = SRC7
ITP_EN = 1 @ VTT_PWRGD# assertion = CPU2
O, DIF Differential serial reference clock. Recommended output for SATA.
GND
Ground for outputs.
37
VDDA
PWR
3.3V power supply for PLL.
38
VSSA
GND
Ground for PLL.
39
IREF
I
42
VDD_CPU
44,43,41,40
CPUT/C
PWR
A precision resistor is attached to this pin, which is connected to the internal
current reference.
3.3V power supply for outputs.
O, DIF Differential CPU clock outputs.
45
VSS_CPU
46
SCLK
GND
I
47
SDATA
I/O
Ground for outputs.
SMBus-compatible SCLOCK.
SMBus-compatible SDATA.
.......................Document #: 38-07691 Rev. *B Page 2 of 19
CY28442-2
Pin Definitions (continued)
Pin No.
48
Name
Type
Description
VDDA2
PWR
49
XOUT
O, SE 14.318 MHz crystal output.
50
XIN
I
GND
3.3V power supply for PLL2
14.318 MHz crystal input.
51
VSSA2
52
REF1
O
Ground for PLL2.
Fixed 14.318 MHz clock output.
53
FS_C_TEST_SEL/
REF0
I/O
3.3V-tolerant input for CPU frequency selection/fixed 14.318 clock output.
Selects test mode if pulled to greater than 1.8V when VTT_PWRGD# is asserted
LOW.
Refer to DC Electrical Specifications table for VIL_FS,VIH_FS specifications.
54
CPU_STP#
I, PU
3.3V LVTTL input for CPU_STP# active LOW.
55
PCI_STP#
I, PU
3.3V LVTTL input for PCI_STP# active LOW.
56
PCI2/SEL_CLKREQ I/O, PD 3.3V-tolerant input for CLKREQ pin selection/fixed 33-MHz clock output.
(sampled on the VTT_PWRGD# assertion).
1= pins 32,33 function as clk request pins, 0= pins 32,33 function as SRC outputs.
Table 1. Frequency Select Table FS_A, FS_B, and FS_C
FS_C
FS_B
FS_A
CPU
SRC
PCIF/PCI
REF0
DOT96
USB
1
0
1
100 MHz
100 MHz
33 MHz
14.318 MHz
96 MHz
48 MHz
0
0
1
133 MHz
100 MHz
33 MHz
14.318 MHz
96 MHz
48 MHz
0
1
1
166 MHz
100 MHz
33 MHz
14.318 MHz
96 MHz
48 MHz
0
1
0
200 MHz
100 MHz
33 MHz
14.318 MHz
96 MHz
48 MHz
Frequency Select Pins (FS_A, FS_B, and FS_C)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A, FS_B, FS_C inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled LOW by the clock chip
(indicating processor VTT voltage is stable), the clock chip
samples the FS_A, FS_B, and FS_C input values. For all logic
levels of FS_A, FS_B, and FS_C, VTT_PWRGD# employs a
one-shot functionality in that once a valid LOW on
VTT_PWRGD# has been sampled, all further VTT_PWRGD#,
FS_A, FS_B, and FS_C transitions will be ignored, except in
test mode.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 2.
The block write and block read protocol is outlined in Table 3
while Table 4 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Table 2. Command Code Definition
Bit
7
(6:0)
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
.......................Document #: 38-07691 Rev. *B Page 3 of 19
CY28442-2
Table 3. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
Description
Start
Block Read Protocol
Bit
1
Slave address – 7 bits
8:2
Description
Start
Slave address – 7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
18:11
Command Code – 8 bits
18:11
Command Code – 8 bits
19
Acknowledge from slave
19
Acknowledge from slave
27:20
28
36:29
37
45:38
46
Byte Count – 8 bits
20
Acknowledge from slave
27:21
Repeat start
Slave address – 7 bits
Data byte 1 – 8 bits
28
Read = 1
Acknowledge from slave
29
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
....
Data Byte /Slave Acknowledges
....
Data Byte N – 8 bits
....
Acknowledge from slave
....
Stop
37:30
38
46:39
47
55:48
Byte Count from slave – 8 bits
Acknowledge
Data byte 1 from slave – 8 bits
Acknowledge
Data byte 2 from slave – 8 bits
56
Acknowledge
....
Data bytes from slave / Acknowledge
....
Data Byte N from slave – 8 bits
....
NOT Acknowledge
....
Stop
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
9
Description
Start
Slave address – 7 bits
Write
Byte Read Protocol
Bit
1
8:2
9
Description
Start
Slave address – 7 bits
Write
10
Acknowledge from slave
10
Acknowledge from slave
18:11
Command Code – 8 bits
18:11
Command Code – 8 bits
19
Acknowledge from slave
19
Acknowledge from slave
Data byte – 8 bits
20
Repeated start
27:20
28
Acknowledge from slave
29
Stop
.......................Document #: 38-07691 Rev. *B Page 4 of 19
27:21
28
Slave address – 7 bits
Read
29
Acknowledge from slave
37:30
Data from slave – 8 bits
38
NOT Acknowledge
39
Stop
CY28442-2
Control Registers
Byte 0: Control Register 0
Bit
7
@Pup
1
6
1
Name
CPUT2_ITP/SRCT7
CPUC2_ITP/SRCC7
SRC[T/C]6
5
1
SRC[T/C]5
4
1
SRC[T/C]4
3
1
SRC[T/C]3
2
1
SRC[T/C]2
1
1
SRC[T/C]1
0
1
RESERVED
Description
CPU[T/C]2_ITP/SRC[T/C]7 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]6 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]5 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]4 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]3 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]2 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enable
RESERVED
Byte 1: Control Register 1
Bit
7
@Pup
1
Name
PCIF0
6
1
DOT_96T/C
5
1
USB_48
4
1
REF0
3
1
REF1
2
1
CPU[T/C]1
1
1
CPU[T/C]0
0
0
CPU
Description
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
DOT_96 MHz Output Enable
0 = Disable (Tri-state), 1 = Enabled
USB_48 MHz Output Enable
0 = Disabled, 1 = Enabled
REF0 Output Enable
0 = Disabled, 1 = Enabled
REF1 Output Enable
0 = Disabled, 1 = Enabled
CPU[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enabled
CPU[T/C]0 Output Enable
0 = Disable (Tri-state), 1 = Enabled
PLL1 (CPU PLL) Spread Spectrum Enable
0 = Spread off, 1 = Spread on
Byte 2: Control Register 2
Bit
7
@Pup
1
Name
PCI5
6
1
PCI4
5
1
PCI3
4
1
PCI2
3
2
1
0
1
1
1
1
Reserved
Reserved
Reserved
PCIF1
Description
PCI5 Output Enable
0 = Disabled, 1 = Enabled
PCI4 Output Enable
0 = Disabled, 1 = Enabled
PCI3 Output Enable
0 = Disabled, 1 = Enabled
PCI2 Output Enable
0 = Disabled, 1 = Enabled
Reserved, Set = 1
Reserved, Set = 1
Reserved, Set = 1
PCIF1 Output Enable
0 = Disabled, 1 = Enabled
.......................Document #: 38-07691 Rev. *B Page 5 of 19
CY28442-2
Byte 3: Control Register 3
Bit
7
@Pup
0
Name
SRC7
6
0
SRC6
5
0
SRC5
4
0
SRC4
3
0
SRC3
2
0
SRC2
1
0
SRC1
0
0
RESERVED
Description
Allow control of SRC[T/C]7 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]6 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]5 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]4 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]3 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]2 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]1 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
RESERVED
Byte 4: Control Register 4
Bit
7
@Pup
0
Name
96_100_SSC
6
0
DOT96T/C
5
4
0
0
RESERVED
PCIF1
3
0
PCIF0
2
1
CPU[T/C]2
1
1
CPU[T/C]1
0
1
CPU[T/C]0
Description
96_100_SSC Drive Mode
0 = Driven in PWRDWN, 1 = Tri-state
DOT_PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Tri-state
RESERVED
Allow control of PCIF1 with assertion of SW and HW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of PCIF0 with assertion of SW and HW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of CPU[T/C]2 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Allow control of CPU[T/C]1 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Allow control of CPU[T/C]0 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Byte 5: Control Register 5
Bit
7
@Pup
0
Name
SRC[T/C]
6
0
CPU[T/C]2
5
0
CPU[T/C]1
4
0
CPU[T/C]0
3
0
SRC[T/C][7:1]
2
0
CPU[T/C]2
1
0
CPU[T/C]1
Description
SRC[T/C] Stop Drive Mode
0 = Driven when PCI_STP# asserted,1 = Tri-state when PCI_STP#
asserted
CPU[T/C]2 Stop Drive Mode
0 = Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP#
asserted
CPU[T/C]1 Stop Drive Mode
0 = Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP#
asserted
CPU[T/C]0 Stop Drive Mode
0 = Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP#
asserted
SRC[T/C] PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Tri-state when PD asserted
CPU[T/C]2 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Tri-state when PD asserted
CPU[T/C]1 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Tri-state when PD asserted
.......................Document #: 38-07691 Rev. *B Page 6 of 19
CY28442-2
Byte 5: Control Register 5 (continued)
Bit
0
@Pup
0
Name
CPU[T/C]0
Description
CPU[T/C]0 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Tri-state when PD asserted
Byte 6: Control Register 6
Bit
7
@Pup
0
6
0
5
4
0
1
3
1
2
HW
1
HW
0
HW
Name
TEST_SEL
Description
REF/N or Tri-state Select
0 = Tri-state, 1 = REF/N Clock
TEST_MODE
Test Clock Mode Entry Control
0 = Normal operation, 1 = REF/N or Tri-state mode,
RESERVED
RESERVED
REF
REF Output Drive Strength
0 = Low, 1 = High
PCI, PCIF and SRC clock SW PCI_STP Function
outputs except those set 0=SW PCI_STP assert, 1= SW PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
to free running
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
FS_C
FS_C Reflects the value of the FS_C pin sampled on power-up
0 = FS_C was low during VTT_PWRGD# assertion
FS_B
FS_B Reflects the value of the FS_B pin sampled on power-up
0 = FS_B was low during VTT_PWRGD# assertion
FS_A
FS_A Reflects the value of the FS_A pin sampled on power-up
0 = FS_A was low during VTT_PWRGD# assertion
Byte 7: Vendor ID
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
1
0
0
0
Name
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Description
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Byte 8: Control Register 8
7
Bit
@Pup
0
Name
CLKREQ#B
6
1
CLKREQ#B
5
0
CLKREQ#B
4
0
CLKREQ#B
3
2
0
1
RESERVED
CLKREQ#A
Description
SRC[T/C]7CLKREQ#B control
1 = SRC[T/C]7 stoppable by CLKREQ#B pin
0 = SRC[T/C]7 not controlled by CLKREQ#B pin
SRC[T/C]5 CLKREQ#B control
1 = SRC[T/C]5 stoppable by CLKREQ#B pin
0 = SRC[T/C]5 not controlled by CLKREQ#B pin
SRC[T/C]3 CLKREQ#B control
1 = SRC[T/C]3 stoppable by CLKREQ#B pin
0 = SRC[T/C]3 not controlled by CLKREQ#B pin
SRC[T/C]1 CLKREQ#B control
1 = SRC[T/C]1 stoppable by CLKREQ#B pin
0 = SRC[T/C]1 not controlled by CLKREQ#B pin
RESERVED
SRC[T/C]4 CLKREQ#A control
1 = SRC[T/C]4 stoppable by CLKREQ#A pin
0 = SRC[T/C]4 not controlled by CLKREQ#A pin
.......................Document #: 38-07691 Rev. *B Page 7 of 19
CY28442-2
Byte 8: Control Register 8 (continued)
1
Bit
@Pup
0
Name
CLKREQ#A
0
0
RESERVED
Description
SRC[T/C]2 CLKREQ#A control
1 = SRC[T/C]2 stoppable by CLKREQ#A pin
0 = SRC[T/C]2 not controlled by CLKREQ#A pin
RESERVED
Byte 9: Control Register 9
7
6
5
4
Bit
@Pup
0
0
0
0
Name
S3
S2
S1
S0
3
2
1
1
96_100 SEL
96_100 Enable
1
1
96_100 SS Enable
0
0
96_100 SW HW
Description
96_100_SSC Spread Spectrum Selection table:
S[3:0] SS%
‘0000’ = –0.8%(Default value)
‘0001’ = –1.0%
‘0010’ = –1.25%
‘0011’ = –1.5%
‘0100’ = –1.75%
‘0101’ = –2.0%
‘0110’ = –2.5%
‘0111’ = –0.5%
‘1000’ = ±0.25%
‘1001’ = ±0.4%
‘1010’ = ±0.5%
‘1011’ = ±0.6%
‘1100’ = ±0.8%
‘1101’ = ±1.0%
‘1110’ = ±1.25%
‘1111’ = ±1.5%
Software select 96_100_SSC output frequency, 0 = 96 MHz, 1 = 100 MHz.
96_100_SSC Enable, 0 = Disable, 1 = Enable.
96_100_SSC Spread spectrum enable. 0 = Disable, 1 = Enable.
Select output frequency of 96_100_SSC via software or hardware
0 = Hardware, 1 = Software.
Byte 10: Control Register 10
7
6
Bit
@Pup
0
0
Name
RESERVED
CLKREQ#B
5
0
CLKREQ#B
4
3
0
0
RESERVED
CLKREQ#A
2
0
CLKREQ#A
1
0
CLKREQ#A
0
0
CLKREQ#A
Description
RESERVED
SRC[T/C]4 CLKREQ#B control
1 = SRC[T/C]4 stoppable by CLKREQ#B pin
0 = SRC[T/C]4not controlled by CLKREQ#B pin
SRC[T/C]2 CLKREQ#B control
1 = SRC[T/C]2 stoppable by CLKREQ#B pin
0 = SRC[T/C]2 not controlled by CLKREQ#B pin
RESERVED
SRC[T/C]7CLKREQ#A control
1 = SRC[T/C]7 stoppable by CLKREQ#A pin
0 = SRC[T/C]7 not controlled by CLKREQ#A pin
SRC[T/C]5 CLKREQ#A control
1 = SRC[T/C]5 stoppable by CLKREQ#A pin
0 = SRC[T/C]5 not controlled by CLKREQ#A pin
SRC[T/C]3 CLKREQ#A control
1 = SRC[T/C]3 stoppable by CLKREQ#A pin
0 = SRC[T/C]3 not controlled by CLKREQ#A pin
SRC[T/C]1 CLKREQ#A control
1 = SRC[T/C]1 stoppable by CLKREQ#A pin
0 = SRC[T/C]1 not controlled by CLKREQ#A pin
.......................Document #: 38-07691 Rev. *B Page 8 of 19
CY28442-2
Table 5. Crystal Recommendations
Frequency
(Fund)
Cut
Loading Load Cap
Drive
(max.)
Shunt Cap
(max.)
Motional
(max.)
Tolerance
(max.)
Stability
(max.)
Aging
(max.)
14.31818 MHz
AT
Parallel
0.1 mW
5 pF
0.016 pF
35 ppm
30 ppm
5 ppm
20 pF
The CY28442-2 requires a Parallel Resonance Crystal.
Substituting a series resonance crystal will cause the
CY28442-2 to operate at the wrong frequency and violate the
ppm specification. For most applications there is a 300-ppm
frequency shift between series and parallel crystals due to
incorrect loading.
.
Clock Chip
Ci2
Ci1
Pin
3 to 6p
Crystal Loading
Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appropriate capacitive loading (CL).
X2
X1
Cs1
Cs2
Trace
2.8pF
Figure 1 shows a typical crystal configuration using the two
trim capacitors. An important clarification for the following
discussion is that the trim capacitors are in series with the
crystal not parallel. It’s a common misconception that load
capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
XTAL
Ce1
Ce2
Trim
33pF
Figure 2. Crystal Loading Example
As mentioned previously, the capacitance on each side of the
crystal is in series with the crystal. This mean the total capacitance on each side of the crystal must be twice the specified
load capacitance (CL). While the capacitance on each side of
the crystal is in series with the crystal, trim capacitors
(Ce1,Ce2) should be calculated to provide equal capacitance
loading on both sides.
Figure 1. Crystal Capacitive Clarification
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
Load Capacitance (each side)
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
Ce = 2 * CL – (Cs + Ci)
Total Capacitance (as seen by the crystal)
CLe
=
1
1
( Ce1 + Cs1
+ Ci1 +
1
Ce2 + Cs2 + Ci2
)
CL....................................................Crystal load capacitance
CLe......................................... Actual loading seen by crystal
using standard value trim capacitors
Ce..................................................... External trim capacitors
Cs .............................................. Stray capacitance (terraced)
Ci ...........................................................Internal capacitance
(lead frame, bond wires etc.)
CLK_REQ[0:1]# Description
The CLKREQ#[A:B] signals are active LOW inputs used for
clean enabling and disabling selected SRC outputs. The
outputs controlled by CLKREQ#[A:B] are determined by the
settings in register byte 8. The CLKREQ# signal is a
de-bounced signal in that it’s state must remain unchanged
during two consecutive rising edges of SRCC to be recognized
as a valid assertion or deassertion. (The assertion and
deassertion of this signal is absolutely asynchronous).
.......................Document #: 38-07691 Rev. *B Page 9 of 19
CY28442-2
CLKREQ#X
SRCT(free running)
SRCC(free running)
SRCT(stoppable)
SRCT(stoppable)
Figure 3. CLK_REQ#[A:B] Deassertion/Assertion Waveform
CLK_REQ[A:B]# Assertion (CLKREQ# -> LOW)
All differential outputs that were stopped are to resume normal
operation in a glitch-free manner. The maximum latency from
the assertion to active outputs is between 2 and 6 SRC clock
periods (2 clocks are shown) with all SRC outputs resuming
simultaneously. All stopped SRC outputs must be driven high
within 10 ns of CLKREQ#[1:0] deassertion to a voltage greater
than 200 mV.
CLK_REQ[A:B]# Deassertion (CLKREQ# -> HIGH)
The impact of deasserting the CLKREQ#[A:B] pins is that all
SRC outputs that are set in the control registers to stoppable
via deassertion of CLKREQ#[A:B] are to be stopped after their
next transition. The final state of all stopped DIF signals is
LOW, both SRCT clock and SRCC clock outputs will not be
driven.
PD (Power-down) Clarification
The VTT_PWRGD# /PD pin is a dual-function pin. During
initial power-up, the pin functions as VTT_PWRGD#. Once
VTT_PWRGD# has been sampled LOW by the clock chip, the
pin assumes PD functionality. The PD pin is an asynchronous
active HIGH input used to shut off all clocks cleanly prior to
shutting off power to the device. This signal is synchronized
internal to the device prior to powering down the clock synthesizer. PD is also an asynchronous input for powering up the
system. When PD is asserted HIGH, all clocks need to be
driven to a LOW value and held prior to turning off the VCOs
and the crystal oscillator.
PD (Power-down) Assertion
When PD is sampled HIGH by two consecutive rising edges
of CPUC, all single-ended outputs will be held LOW on their
next HIGH-to-LOW transition and differential clocks must held
high or tri-stated (depending on the state of the control register
drive mode bit) on the next diff clock# HIGH-to-LOW transition
within 4 clock periods. When the SMBus PD drive mode bit
corresponding to the differential (CPU, SRC, and DOT) clock
output of interest is programmed to ‘0’, the clock output are
held with “Diff clock” pin driven HIGH at 2 x Iref, and “Diff
clock#” tri-state. If the control register PD drive mode bit corresponding to the output of interest is programmed to “1”, then
both the “Diff clock” and the “Diff clock#” are tri-state. Note the
example below shows CPUT = 133 MHz and PD drive mode
= ‘1’ for all differential outputs. This diagram and description is
applicable to valid CPU frequencies 100, 133, 166, 200, 266,
333, and 400 MHz. In the event that PD mode is desired as
the initial power-on state, PD must be asserted HIGH in less
than 10 s after asserting Vtt_PwrGd#.
PD
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
USB, 48MHz
DOT96T
DOT96C
PCI, 33 MHz
REF
Figure 4. Power-down Assertion Timing Waveform
..................... Document #: 38-07691 Rev. *B Page 10 of 19
CY28442-2
PD Deassertion
CPU_STP# Assertion
The power-up latency is less than 1.8 ms. This is the time from
the deassertion of the PD pin or the ramping of the power
supply until the time that stable clocks are output from the
clock chip. All differential outputs stopped in a three-state
condition resulting from power down will be driven high in less
than 300 s of PD deassertion to a voltage greater than
200 mV. After the clock chip’s internal PLL is powered up and
locked, all outputs will be enabled within a few clock cycles of
each other. Below is an example showing the relationship of
clocks coming up.
The CPU_STP# signal is an active LOW input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
set with the SMBus configuration to be stoppable via assertion
of CPU_STP# will be stopped within two–six CPU clock
periods after being sampled by two rising edges of the internal
CPUC clock. The final states of the stopped CPU signals are
CPUT = HIGH and CPUC = LOW. There is no change to the
output drive current values during the stopped state. The
CPUT is driven HIGH with a current value equal to 6 x (Iref),
and the CPUC signal will be tri-stated.
Tstable
200mV
Figure 7. CPU_STP# Deassertion Waveform
1.8mS
CPU_STOP#
PD
CPUT(Free Running
CPUC(Free Running
CPUT(Stoppable)
CPUC(Stoppable)
DOT96T
DOT96C
Figure 8. CPU_STP#= Driven, CPU_PD = Driven, DOT_PD = Driven
1.8mS
CPU_STOP#
PD
CPUT(Free Running)
CPUC(Free Running)
CPUT(Stoppable)
CPUC(Stoppable)
DOT96T
DOT96C
Figure 9. CPU_STP# = Tri-state, CPU_PD = Tri-state, DOT_PD = Tri-state
..................... Document #: 38-07691 Rev. *B Page 12 of 19
CY28442-2
PCI_STP# Assertion
PCI_STP# Deassertion
The PCI_STP# signal is an active LOW input used for
synchronous stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
time for capturing PCI_STP# going LOW is 10 ns (tSU). (See
Figure 10.) The PCIF clocks will not be affected by this pin if
their corresponding control bit in the SMBus register is set to
allow them to be free-running.
The deassertion of the PCI_STP# signal will cause all PCI and
stoppable PCIF clocks to resume running in a synchronous
manner within two PCI clock periods after PCI_STP# transitions to a high level.
Tsu
PCI_STP#
PCI_F
PCI
SRC 100MHz
Figure 10. PCI_STP# Assertion Waveform
Tsu
Tdrive_SRC
PCI_STP#
PCI_F
PCI
SRC 100MHz
Figure 11. PCI_STP# Deassertion Waveform
FS_A, FS_B,FS_C
VTT_PW RGD#
PW RGD_VRM
0.2-0.3mS
Delay
VDD Clock Gen
Clock State
Clock Outputs
Clock VCO
State 0
W ait for
VTT_PW RGD#
State 1
State 2
Off
Off
Device is not affected,
VTT_PW RGD# is ignored
Sample Sels
State 3
On
On
Figure 12. VTT_PWRGD# Timing Diagram
..................... Document #: 38-07691 Rev. *B Page 13 of 19
CY28442-2
S2
S1
VTT_PWRGD# = Low
Delay
>0.25mS
Sample
Inputs straps
VDD_A = 2.0V
Wait for
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