CY28445LFXC-5

CY28445-5 Clock Generator for Intel®Calistoga Chipset Features • 33 MHz PCI clock • Buffered 14.318 MHz Reference Clock • Compliant to Intel® CK410M • Low-voltage frequency select input • Selectable CPU frequencies • I2C support with readback capabilities • Differential CPU clock pairs • 100 MHz differential SRC clocks • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • 96 MHz differential dot clock • 3.3V power supply • 27 MHz Spread and Non-spread video clock • 68-pin QFN (MLF) package • 48 MHz USB clock • SRC clocks independently stoppable through CLKREQ# CPU SRC PCI REF DOT96 USB_48M LCD100M 27M x2 / x3 x8/9/10 x7 x2 x1 x1 x1 x2 • 96/100 MHz Spreadable differential video clock. Block Diagram SEL_CLKREQ PCI_STP# CPU PLL CPU_STP# CLKREQ# PLL Reference Divider Pin Configuration VDD REF IREF VDD CPUT[0:1] CPUC[0:1] VDD CPUT2_ITP/SRCT10 CPUC2_ITP/SRCC10 ITP_SEL FS[C:A] VDD SRCT[1:8] SRCC[1:8] VDD PCI[1:5] VDD_PCI PCIF[0:1] VDD LVDS PLL Divider SRCT0/100MT_SST SRCC0/100MC_SST VDD 27M- Spread FCTSEL[0:1] 27MHz PLL Divider Fixed PLL Divider VDD48 27M- non Spread VTT_PWRGD#/PD SDATA SCLK I2C Logic PCIF0 / ITP_SEL VDD_PCI VSS_PCI PCI5 / FCTSEL1 PCI4 PCI3 VSS_PCI VDD_PCI CLKREQ#_5 CLKREQ#_3 PCI2 PCI1 PCI_STP# CPU_STP# REF0 / FSC REF1 / FCTSEL0 VSS_REF XOUT 14.318MHz Crystal 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 PCIF1 VTT_PWRGD# / PD VDD48 48M/FSA VSS48 DOT96T / 27MHz non spread DOT96C/ 27MHz spread FSB CLKREQ#_1 SRCT_0 / LCD100MT SRCC_0 / LCD100MC VDD_SRC SRCT_1 SRCC_1 SRCT_2 SRCC_2 VDD_SRC VDD48 DOT96T DOT96C VDD48 48M ........................Document #: 38-07739 Rev *C Page 1 of 25 400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 CY28445-5 XIN XOUT VDD_REF SDATA SCLK VSS_CPU CPUT0 CPUC0 VDD_CPU CPUT1 CPUC1 IREF VSSA VDDA CPUT2_ITP / SRCT_10 CPUC2_ITP / SRCC_10 VDD_SRC 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 SRCT_3 SRCC_3 CLKREQ#_4 SRCT_4 SRCC_4 SRCT_5 SRCC_5 CLKREQ#_6 SRCT_6 SRCC_6 VDD_SRC SRCT_7 SRCC_7 VSS_SRC SRCC_8 SRCT_8 CLKREQ#_8 XIN 1+(512) 416-9669 www.silabs.com CY28445-5 Pin Descriptions Pin No. Name Type Description 1 PCIF1 O, SE 33 MHz clock output 2 VTT_PWRGD#/PD I, PD PWR 3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS[C:A], ITP_SEL, FCTSEL[1:0], SEL_CLKREQ#. After VTT_PWRGD# (active LOW) assertion, this pin becomes a real-time input for asserting power-down (active HIGH). 3 VDD48 4 FSA/48M 5 VSS48 6, 7 O, DIF Fixed 96 MHz differential clock output / Single ended 27 MHz clock outputs. DOT96T/27M_non When configured for 27 MHz, only the clock on pin 7contains spread. spread Selected via FCTSEL[0:1] at VTT_PWRGD# assertion. DOT96C/27M_Spread 8 FSB I/O GND I 3.3V power supply. 3.3V-tolerant input for CPU frequency selection / Fixed 48 MHz clock output. Refer to DC Electrical Specification Table for Vil_FS and Vih_FS specifications. Ground. 3.3V-tolerant input for CPU frequency selection. Refer to DC Electrical Specification Table for Vil_FS and Vih_FS specifications 9, 20, 25, 34, CLKREQ#[1], [3:6], [8] 59, 60 I, PU 10, 11 O,DIF 100 MHz differential serial reference clock output / 100 MHz LVDS differential clock output. Selected via FCTSEL[0:1] at VTT_PWRGD# assertion SRC[T/C]0/ LCD100M[T/C] 12, 17, 28, 35 VDD_SRC PWR 3.3V LVTTL input for enabling assigned SRC clock (active LOW) 3.3V power supply 13,14, 15, 16, 18, 19, 21, 22, 23, 24, 26, 27, 29, 30, 32, 33, SRC[T/C][1:8] 31 VSS_SRC 36, 37 CPUT2_ITP/SRCT10, O, DIF Selectable differential CPU / SRC clock output. CPUC2_ITP/SRCC10 ITP_EN = 0 @ VTT_PWRGD# assertion = SRC10 (default) ITP_EN = 1@ VTT_PWRGD# assertion =CPU2_ITP 38 VDDA PWR 3.3V power supply for PLL. 39 VSSA GND Ground for PLL. 40 IREF I 41, 42, 44, 45 CPU[T/C][0:1] O, DIF 100 MHz differential serial reference clock outputs. GND Ground. A precision resistor is attached to this pin, which is connected to the internal current reference. O, DIF Differential CPU clock outputs. 43 VDD_CPU PWR 3.3V power supply 46 VSS_CPU GND Ground 47 SCLK 48 SDATA I SMBus-compatible SCLOCK. 49 VDD_REF PWR 50 XOUT O, SE 14.318 MHz crystal output. 51 XIN I/O, OD SMBus-compatible SDATA. I 3.3V power supply 14.318 MHz crystal input. ....................... Document #: 38-07739 Rev *C Page 2 of 25 CY28445-5 Pin Descriptions (continued) Pin No. 53 Name REF1/FCTSEL0 Type Description I/O, SE Fixed 14.318 MHz clock output / 3.3V LVTTL input for selecting for pin 6, 7 PD (DOT96[T/C], 27M-non-spread and Spread) and pin 10,11 (SRC[T/C]0 or 100M[T/C]_SST) (sampled on the VTT_PWRGD# assertion). FCTSEL1 FCTSEL0 PIN 6 PIN 7 PIN 10 0 0 DOT96T DOT96C 100MT_SST 100MC_SST 0 1 DOT96T DOT96C SRCT0 SRCC0 1 0 27M_non spread 27M_Spread SRCT0 SRCC0 1 1 OFF Low SRCC0 TBD 54 REF0/FSC I/O 55 CPU_STP# I, PU 3.3V LVTTL input for CPU_STP# active LOW. 56 PCI_STP# I, PU 3.3V LVTTL input for PCI_STP# active LOW. SRCT0 PIN 11 Fixed 14.318 MHz clock output / 3.3V-tolerant input for CPU frequency selection. Refer to DC Electrical Specification Table for VilFS_C, VimFS_C and VihFS_C specifications 57, 58, 63, 64 PCI[1:4] O, SE 33 MHz clock outputs. 61, 67 VDD_PCI PWR 3.3V power supply 62, 66 VSS_PCI GND Ground 65 PCI5/FCTSEL1 O, SE 33 MHz clock output / 3.3V LVTTL input for selecting for pin 6, 7 PD (DOT96[T/C], 27M-non-spread and Spread) and pin10,11 (SRC[T/C]0 or 100M[T/C]_SST) (sampled on the VTT_PWRGD# assertion). FCTSEL1 FCTSEL0 PIN 6 68 PCIF0/ITP_SEL PIN 7 PIN 10 0 0 DOT96T DOT96C 100MT_SST 100MC_SST 0 1 DOT96T DOT96C SRCT0 SRCC0 1 0 27M_non spread 27M_Spread SRCT0 SRCC0 1 1 OFF Low SRCC0 TBD SRCT0 PIN 11 I/O, SE 33 MHz clock output / 3.3V LVTTL input to enable SRC[T/C]10 or CPU[T/C]2_ITP on pin 36, 37. (sampled on the VTT_PWRGD# assertion). 0 = SRC10 (default) 1 = CPU2_ITP, Table 1. Frequency Select Table FSA, FSB and FSC FSC FSB FSA CPU SRC PCIF/PCI 27MHz REF0 DOT96 USB 1 0 1 100 MHz 100 MHz 33 MHz 27 MHz 14.318 MHz 96 MHz 48 MHz 0 0 1 133 MHz 100 MHz 33 MHz 27 MHz 14.318 MHz 96 MHz 48 MHz 0 1 1 166 MHz 100 MHz 33 MHz 27 MHz 14.318 MHz 96 MHz 48 MHz 0 1 0 200 MHz 100 MHz 33 MHz 27 MHz 14.318 MHz 96 MHz 48 MHz Frequency Select Pins (FSA, FSB, and FSC) Serial Data Interface Host clock frequency selection is achieved by applying the appropriate logic levels to FSA, FSB, FSC inputs prior to VTT_PWRGD# assertion (as seen by the clock synthesizer). Upon VTT_PWRGD# being sampled low by the clock chip (indicating processor VTT voltage is stable), the clock chip samples the FSA, FSB, and FSC input values. For all logic levels of FSA, FSB, and FSC, VTT_PWRGD# employs a one-shot functionality in that once a valid low on VTT_PWRGD# has been sampled, all further VTT_PWRGD#, FSA, FSB, and FSC transitions will be ignored, except in test mode. To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions. ....................... Document #: 38-07739 Rev *C Page 3 of 25 CY28445-5 Data Protocol The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the Table 2. Command Code Definition Bit 7 (6:0) system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 2. The block write and block read protocol is outlined in Table 3 while Table 4 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Description 0 = Block read or block write operation, 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000' Table 3. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 Description Start Slave address – 7 bits Block Read Protocol Bit 1 8:2 Description Start Slave address – 7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 Command Code – 8 bits 18:11 Command Code – 8 bits 19 Acknowledge from slave 19 Acknowledge from slave Byte Count – 8 bits (Skip this step if I2C_EN bit set) 20 Repeat start 27:20 28 36:29 37 45:38 Acknowledge from slave Data byte 1 – 8 bits Acknowledge from slave Data byte 2 – 8 bits 46 Acknowledge from slave .... Data Byte /Slave Acknowledges .... Data Byte N – 8 bits .... Acknowledge from slave .... Stop ....................... Document #: 38-07739 Rev *C Page 4 of 25 27:21 Slave address – 7 bits 28 Read = 1 29 Acknowledge from slave 37:30 38 46:39 47 55:48 Byte Count from slave – 8 bits Acknowledge Data byte 1 from slave – 8 bits Acknowledge Data byte 2 from slave – 8 bits 56 Acknowledge .... Data bytes from slave / Acknowledge .... Data Byte N from slave – 8 bits .... NOT Acknowledge .... Stop CY28445-5 Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 9 Byte Read Protocol Description Bit Start 1 Slave address – 7 bits 8:2 Write 9 Description Start Slave address – 7 bits Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 Command Code – 8 bits 18:11 Command Code – 8 bits 19 Acknowledge from slave 19 Acknowledge from slave Data byte – 8 bits 20 Repeated start 27:20 28 Acknowledge from slave 29 Stop 27:21 28 Slave address – 7 bits Read 29 Acknowledge from slave 37:30 Data from slave – 8 bits 38 NOT Acknowledge 39 Stop Control Registers Byte 0: Control Register 0 Bit @Pup Name Description 7 1 SRC[T/C]7 SRC[T/C]7 Output Enable 0 = Disable (Tri-state), 1 = Enable 6 1 SRC[T/C]6 SRC[T/C]6 Output Enable 0 = Disable (Tri-state), 1 = Enable 5 1 SRC[T/C]5 SRC[T/C]5 Output Enable 0 = Disable (Tri-state), 1 = Enable 4 1 SRC[T/C]4 SRC[T/C]4 Output Enable 0 = Disable (Tri-state), 1 = Enable 3 1 SRC[T/C]3 SRC[T/C]3 Output Enable 0 = Disable (Tri-state), 1 = Enable 2 1 SRC[T/C]2 SRC[T/C]2 Output Enable 0 = Disable (Tri-state), 1 = Enable 1 1 SRC[T/C]1 SRC[T/C]1 Output Enable 0 = Disable (Tri-state), 1 = Enable 0 1 SRC[T/C]0 /LCD100M[T/C] SRC[T/C]0 /LCD100M[T/C] Output Enable 0 = Disable (Hi-Z), 1 = Enable Byte 1: Control Register 1 Bit @Pup 7 1 PCIF0 Name PCIF0 Output Enable 0 = Disabled, 1 = Enabled Description 6 1 27M_nss / DOT_96[T/C] 27M_nss and DOT_96 MHz Output Enable 0 = Disable (Tri-state), 1 = Enabled 5 1 USB_48MHz USB_48M MHz Output Enable 0 = Disabled, 1 = Enabled 4 1 REF0 REF0 Output Enable 0 = Disabled, 1 = Enabled 3 1 REF1 REF1 Output Enable 0 = Disabled, 1 = Enabled ....................... Document #: 38-07739 Rev *C Page 5 of 25 CY28445-5 Byte 1: Control Register 1 (continued) Bit @Pup Name Description 2 1 CPU[T/C]1 CPU[T/C]1 Output Enable 0 = Disable (Tri-state), 1 = Enabled 1 1 CPU[T/C]0 CPU[T/C]0 Output Enable 0 = Disable (Tri-state), 1 = Enabled 0 0 CPU PLL1 (CPU PLL) Spread Spectrum Enable 0 = Spread off, 1 = Spread on Byte 2: Control Register 2 Bit @Pup 7 1 PCI5 Name PCI5 Output Enable 0 = Disabled, 1 = Enabled Description 6 1 PCI4 PCI4 Output Enable 0 = Disabled, 1 = Enabled 5 1 PCI3 PCI3 Output Enable 0 = Disabled, 1 = Enabled 4 1 PCI2 PCI2 Output Enable 0 = Disabled, 1 = Enabled 3 1 PCI1 PCI1 Output Enable 0 = Disabled, 1 = Enabled 2 1 RESERVED RESERVED 1 1 CPU[T/C]2 CPU[T/C]2 Output Enable 0 = Disabled (Hi-Z), 1 = Enabled 0 1 PCIF1 PCIF1 Output Enable 0 = Disabled, 1 = Enabled Byte 3: Control Register 3 Bit @Pup 7 0 SRC7 Name Allow control of SRC[T/C]7 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Description 6 0 SRC6 Allow control of SRC[T/C]6 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 5 0 SRC5 Allow control of SRC[T/C]5 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 4 0 SRC4 Allow control of SRC[T/C]4 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 3 0 SRC3 Allow control of SRC[T/C]3 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 2 0 SRC2 Allow control of SRC[T/C]2 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 1 0 SRC1 Allow control of SRC[T/C]1 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 0 0 SRC0 Allow control of SRC[T/C]0 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# ....................... Document #: 38-07739 Rev *C Page 6 of 25 CY28445-5 Byte 4: Control Register 4 Bit @Pup Name Description 7 0 LCD100M[T/C] LCD100M[T/C] PWRDWN Drive Mode 0 = Driven in PWRDWN, 1 = Tri-state 6 0 DOT96[T/C] DOT PWRDWN Drive Mode 0 = Driven in PWRDWN, 1 = Tri-state 5 0 SRC[T/C] SRC[T/C] Stop Drive Mode when CLKREQ# asserted 0 = Driven, 1 = Tri-state 4 0 PCIF1 Allow control of PCIF1 with assertion of SW and HW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 3 0 PCIF0 Allow control of PCIF0 with assertion of SW and HW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 2 1 CPU[T/C]2 Allow control of CPU[T/C]2 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# 1 1 CPU[T/C]1 Allow control of CPU[T/C]1 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# 0 1 CPU[T/C]0 Allow control of CPU[T/C]0 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# Byte 5: Control Register 5 Bit @Pup 7 0 SRC[T/C] Name SRC[T/C] Stop Drive Mode 0 = Driven when PCI_STP# asserted,1 = Tri-state when PCI_STP# asserted Description 6 0 CPU[T/C]2 CPU[T/C]2 Stop Drive Mode 0 = Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP# asserted 5 0 CPU[T/C]1 CPU[T/C]1 Stop Drive Mode 0 = Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP# asserted 4 0 CPU[T/C]0 CPU[T/C]0 Stop Drive Mode 0 = Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP# asserted 3 0 SRC[T/C] SRC[T/C] PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Tri-state when PD asserted 2 0 CPU[T/C]2 CPU[T/C]2 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Tri-state when PD asserted 1 0 CPU[T/C]1 CPU[T/C]1 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Tri-state when PD asserted 0 0 CPU[T/C]0 CPU[T/C]0 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Tri-state when PD asserted Byte 6: Control Register 6 Bit @Pup Name Description 7 0 TEST_SEL REF/N or Tri-state Select 0 = Tri-state, 1 = REF/N Clock 6 0 TEST_MODE Test Clock Mode Entry Control 0 = Normal operation, 1 = REF/N or Tri-state mode, 5 1 REF1 REF0 Output Drive Strength 0 = Low, 1 = High 4 1 REF0 REF0 Output Drive Strength 0 = Low, 1 = High ....................... Document #: 38-07739 Rev *C Page 7 of 25 CY28445-5 Byte 6: Control Register 6 (continued) Bit @Pup Name Description 3 1 2 HW FSC FSC Reflects the value of the FSC pin sampled on power-up 0 = FSC was low during VTT_PWRGD# assertion 1 HW FSB FSB Reflects the value of the FSB pin sampled on power-up 0 = FSB was low during VTT_PWRGD# assertion 0 HW FSA FSA Reflects the value of the FSA pin sampled on power-up 0 = FSA was low during VTT_PWRGD# assertion PCI, PCIF and SRC clock SW PCI_STP Function outputs except those set 0 = SW PCI_STP assert, 1 = SW PCI_STP deassert to free running When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will be stopped in a synchronous manner with no short pulses. When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will resume in a synchronous manner with no short pulses. Byte 7: Vendor ID Bit @Pup Name Description 7 0 Revision Code Bit 3 Revision Code Bit 3 6 0 Revision Code Bit 2 Revision Code Bit 2 5 0 Revision Code Bit 1 Revision Code Bit 1 4 1 Revision Code Bit 0 Revision Code Bit 0 3 1 Vendor ID Bit 3 Vendor ID Bit 3 2 0 Vendor ID Bit 2 Vendor ID Bit 2 1 0 Vendor ID Bit 1 Vendor ID Bit 1 0 0 Vendor ID Bit 0 Vendor ID Bit 0 Byte 8: Control Register 8 Bit @Pup Name Description 7 0 CPU_SS 0: –0.5% (Peak to peak) 1: –1.0% (Peak to peak) 6 0 CPU-DWN_SS 0: Down Spread 1: Center Spread 5 0 RESERVED RESERVED, Set = 0 4 0 RESERVED RESERVED, Set = 0 3 0 RESERVED RESERVED, Set = 0 2 1 48M 48-MHz Output Drive Strength 0 = Low, 1 = High 1 1 PCI1 33-MHz Output Drive Strength 0 = Low, 1 = High 0 1 PCIF0 33-MHz Output Drive Strength 0 = Low, 1 = High ....................... Document #: 38-07739 Rev *C Page 8 of 25 CY28445-5 Byte 9: Control Register 9 Bit @Pup Name Description 7 0 S3 27_96_100_SSC Spread Spectrum Selection table: S[3:0] SS% ‘0000’ = –0.45%(Default value) ‘0001’ = –0.9% ‘0010’ = –1.45% ‘0011’ = –1.9% ‘0100’ = ±0.225% ‘0101’ = ±0.45% ‘0110’ = ±0.725% ‘0111’ = ±0.95% ‘1000’ = –0.34% ‘1001’ = –0.68% ‘1010’ = –1.09% ‘1011’ = –1.425% ‘1100’ = ±0.17% ‘1101’ = ±0.34% ‘1110’ = ±0.545% ‘1111’ = ±0.712% 6 0 S2 5 0 S1 4 0 S0 3 1 RESERVED RESERVED, Set = 1 2 1 27_M Spread 27_MHz Spread Output Enable 0 = Disable (Hi-Z), 1 = Enable. 1 1 27M_SS / LCD100M SS Enable 0 0 PCIF1 27M_SS / LCD100M Spread Spectrum Enable. 0 = Disable, 1 = Enable. 33-MHz Output Drive Strength 0 = Low, 1 = High Byte 10: Control Register 10 Bit @Pup Name Description 7 1 SRC[T/C]10 SRC[T/C]10 Output Enable 0 = Disable (Hi-Z), 1 = Enable 6 1 RESERVED RESERVED 5 1 RESERVED RESERVED 4 1 SRC[T/C]8 SRC[T/C]8 Output Enable 0 = Disable (Hi-Z), 1 = Enable 3 0 RESERVED RESERVED 2 0 SRC[T/C]10 Allow control of SRC[T/C]10 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 1 0 RESERVED RESERVED 0 0 SRC[T/C]8 Allow control of SRC[T/C]8 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Byte 11: Control Register 11 Bit @Pup Name Description 7 0 RESERVED RESERVED Set = 0 6 HW RESERVED RESERVED 5 HW RESERVED RESERVED 4 HW RESERVED RESERVED 3 0 27M spread and non-spread output drive strength 27M (Spread and Non-spread) Output Drive Strength 0 = Low, 1 = High ....................... Document #: 38-07739 Rev *C Page 9 of 25 CY28445-5 Byte 11: Control Register 11 Bit @Pup Name Description 2 0 RESERVED RESERVED Set = 0 1 0 RESERVED RESERVED Set = 0 0 HW RESERVED RESERVED Byte 12: Control Register 12 Bit @Pup Name Description 7 0 RESERVED RESERVED 6 0 CLKREQ#8 CLKREQ#8 Input Enable 0 = Disable 1 = Enable 5 0 RESERVED RESERVED 4 0 CLKREQ#6 CLKREQ#6 Input Enable 0 = Disable 1 = Enable 3 0 CLKREQ#5 CLKREQ#5 Input Enable 0 = Disable 1 = Enable 2 0 CLKREQ#4 CLKREQ#4 Input Enable 0 = Disable 1 = Enable 1 0 CLKREQ#3 CLKREQ#3 Input Enable 0 = Disable 1 = Enable 0 0 RESERVED RESERVED Byte 13: Control Register 13 Bit @Pup Name Description 7 0 CLKREQ#1 CLKREQ#1 Input Enable 0 = Disable 1 = Enable 6 1 LCDCLK Speed LCD 96/100 MHz clock speed selection 0 = 96 MHz, 1 = 100 MHz 5 1 RESERVED RESERVED 4 1 RESERVED RESERVED 3 1 PCI5 PCI5 (Spread and Non-spread) Output Drive Strength 0 = Low, 1 = High 2 1 PCI4 PCI4 (Spread and Non-spread) Output Drive Strength 0 = Low, 1 = High 1 1 PCI3 PCI3 (Spread and Non-spread) Output Drive Strength 0 = Low, 1 = High 0 1 PCI2 PCI2 (Spread and Non-spread) Output Drive Strength 0 = Low, 1 = High Byte 14: Control Register 14 Bit @Pup Name Description 7 1 RESERVED RESERVED 6 0 RESERVED RESERVED 5 0 RESERVED RESERVED 4 0 RESERVED RESERVED 3 0 RESERVED RESERVED 2 0 RESERVED RESERVED 1 0 RESERVED RESERVED ..................... Document #: 38-07739 Rev *C Page 10 of 25 CY28445-5 Byte 14: Control Register 14 (continued) Bit 0 @Pup 0 Name RESERVED Description RESERVED Byte 15: Control Register 15 Bit @Pup Name Description 7 1 CLKREQ#8 SRC[T/C]8 Control 0 = SRC[T/C]8 not stoppable by CLKREQ#8 1 = SRC[T/C]8 stoppable by CLKREQ#8 6 0 CLKREQ#8 SRC[T/C]7 Control 0 = SRC[T/C]7 not stoppable by CLKREQ#8 1 = SRC[T/C]7 stoppable by CLKREQ#8 5 0 CLKREQ#8 SRC[T/C]6 Control 0 = SRC[T/C]6 not stoppable by CLKREQ#8 1 = SRC[T/C]6 stoppable by CLKREQ#8 4 0 CLKREQ#8 SRC[T/C]5 Control 0 = SRC[T/C]5 not stoppable by CLKREQ#8 1 = SRC[T/C]5 stoppable by CLKREQ#8 3 0 CLKREQ#8 SRC[T/C]4 Control 0 = SRC[T/C]4 not stoppable by CLKREQ#8 1 = SRC[T/C]4 stoppable by CLKREQ#8 2 0 CLKREQ#8 SRC[T/C]3 Control 0 = SRC[T/C]3 not stoppable by CLKREQ#8 1 = SRC[T/C]3 stoppable by CLKREQ#8 1 0 CLKREQ#8 SRC[T/C]2 Control 0 = SRC[T/C]2 not stoppable by CLKREQ#8 1 = SRC[T/C]2 stoppable by CLKREQ#8 0 0 CLKREQ#8 SRC[T/C]1 Control 0 = SRC[T/C1 not stoppable by CLKREQ#8 1 = SRC[T/C]1 stoppable by CLKREQ#8 Byte 16: Control Register 16 Bit @Pup Name Description 7 0 CLKREQ#5 SRC[T/C]8 Control 0 = SRC[T/C]8 not stoppable by CLKREQ#5 1 = SRC[T/C]8 stoppable by CLKREQ#5 6 0 CLKREQ#5 SRC[T/C]7 Control 0 = SRC[T/C]7 not stoppable by CLKREQ#5 1 = SRC[T/C]7 stoppable by CLKREQ#5 5 0 CLKREQ#5 SRC[T/C]6 Control 0 = SRC[T/C]6 not stoppable by CLKREQ#5 1= SRC[T/C]6 stoppable by CLKREQ#5 4 1 CLKREQ#5 SRC[T/C]5 Control 0 = SRC[T/C]5 not stoppable by CLKREQ#5 1= SRC[T/C]5 stoppable by CLKREQ#5 3 0 CLKREQ#5 SRC[T/C]4 Control 0 = SRC[T/C]4 not stoppable by CLKREQ#5 1 = SRC[T/C]4 stoppable by CLKREQ#5 2 0 CLKREQ#5 SRC[T/C]3 Control 0 = SRC[T/C]3 not stoppable by CLKREQ#5 1 = SRC[T/C]3 stoppable by CLKREQ#5 1 0 CLKREQ#5 SRC[T/C]2 Control 0 = SRC[T/C]2 not stoppable by CLKREQ#5 1 = SRC[T/C]2 stoppable by CLKREQ#5 ......................Document #: 38-07739 Rev *C Page 11 of 25 CY28445-5 Byte 16: Control Register 16 (continued) Bit 0 @Pup 0 Name CLKREQ#5 Description SRC[T/C]1 Control 0 = SRC[T/C]1 not stoppable by CLKREQ#5 1 = SRC[T/C]1 stoppable by CLKREQ#5 Byte 17: Control Register 17 Bit @Pup Name Description 7 0 CLKREQ#4 SRC[T/C]8 Control 0 = SRC[T/C]8 not stoppable by CLKREQ#4 1 = SRC[T/C]8 stoppable by CLKREQ#4 6 0 CLKREQ#4 SRC[T/C]7 Control 0 = SRC[T/C]7 not stoppable by CLKREQ#4 1 = SRC[T/C]7 stoppable by CLKREQ#4 5 0 CLKREQ#4 SRC[T/C]6 Control 0 = SRC[T/C]6 not stoppable by CLKREQ#4 1 = SRC[T/C]6 stoppable by CLKREQ#4 4 0 CLKREQ#4 SRC[T/C]5 Control 0 = SRC[T/C]5 not stoppable by CLKREQ#4 1 = SRC[T/C]5 stoppable by CLKREQ#4 3 1 CLKREQ#4 SRC[T/C]4 Control 0 = SRC[T/C]4 not stoppable by CLKREQ#4 1 = SRC[T/C]4 stoppable by CLKREQ#4 2 0 CLKREQ#4 SRC[T/C]3 Control 0 = SRC[T/C]3 not stoppable by CLKREQ#4 1 = SRC[T/C]3 stoppable by CLKREQ#4 1 0 CLKREQ#4 SRC[T/C]2 Control 0 = SRC[T/C]2 not stoppable by CLKREQ#4 1 = SRC[T/C]2 stoppable by CLKREQ#4 0 0 CLKREQ#4 SRC[T/C]1 Control 0 = SRC[T/C]1 not stoppable by CLKREQ#4 1 = SRC[T/C]1 stoppable by CLKREQ#4 Byte 18: Control Register 18 Bit @Pup Name Description 7 0 CLKREQ#3 SRC[T/C]8 Control 0 = SRC[T/C]8 not stoppable by CLKREQ#3 1 = SRC[T/C]8 stoppable by CLKREQ#3 6 0 CLKREQ#3 SRC[T/C]7 Control 0 = SRC[T/C]7 not stoppable by CLKREQ#3 1 = SRC[T/C]7 stoppable by CLKREQ#3 5 0 CLKREQ#3 SRC[T/C]6 Control 0 = SRC[T/C]6 not stoppable by CLKREQ#3 1 = SRC[T/C]6 stoppable by CLKREQ#3 4 0 CLKREQ#3 SRC[T/C]5 Control 0 = SRC[T/C]5 not stoppable by CLKREQ#3 1 = SRC[T/C]5 stoppable by CLKREQ#3 3 0 CLKREQ#3 SRC[T/C]4 Control 0 = SRC[T/C]4 not stoppable by CLKREQ#3 1 = SRC[T/C]4 stoppable by CLKREQ#3 2 1 CLKREQ#3 SRC[T/C]3 Control 0 = SRC[T/C]3 not stoppable by CLKREQ#3 1 = SRC[T/C]3 stoppable by CLKREQ#3 ..................... Document #: 38-07739 Rev *C Page 12 of 25 CY28445-5 Byte 18: Control Register 18 (continued) Bit @Pup Name Description 1 0 CLKREQ#3 SRC[T/C]2 Control 0 = SRC[T/C]2 not stoppable by CLKREQ#3 1 = SRC[T/C]2 stoppable by CLKREQ#3 0 0 CLKREQ#3 SRC[T/C]1 Control 0 = SRC[T/C]1 not stoppable by CLKREQ#3 1 = SRC[T/C]1 stoppable by CLKREQ#3 Byte 19: Control Register 19 Bit @Pup Name Description 7 0 CLKREQ#1 SRC[T/C]8 Control 0 = SRC[T/C]8 not stoppable by CLKREQ#1 1 = SRC[T/C]8 stoppable by CLKREQ#1 6 0 CLKREQ#1 SRC[T/C]7 Control 0 = SRC[T/C]7 not stoppable by CLKREQ#1 1 = SRC[T/C]7 stoppable by CLKREQ#1 5 0 CLKREQ#1 SRC[T/C]6 Control 0 = SRC[T/C]6 not stoppable by CLKREQ#1 1= SRC[T/C]6 stoppable by CLKREQ#1 4 0 CLKREQ#1 SRC[T/C]5 Control 0 = SRC[T/C]5 not stoppable by CLKREQ#1 1 = SRC[T/C]5 stoppable by CLKREQ#1 3 0 CLKREQ#1 SRC[T/C]4 Control 0 = SRC[T/C]4 not stoppable by CLKREQ#1 1 = SRC[T/C]4 stoppable by CLKREQ#1 2 0 CLKREQ#1 SRC[T/C]3 Control 0 = SRC[T/C]3 not stoppable by CLKREQ#1 1 = SRC[T/C]3 stoppable by CLKREQ#1 1 0 CLKREQ#1 SRC[T/C]2 Control 0 = SRC[T/C]2 not stoppable by CLKREQ#1 1 = SRC[T/C]2 stoppable by CLKREQ#1 0 1 CLKREQ#1 SRC[T/C]1 Control 0 = SRC[T/C]1 not stoppable by CLKREQ#1 1 = SRC[T/C]1 stoppable by CLKREQ#1 Table 5. Crystal Recommendations Frequency (Fund) Cut Loading Load Cap Drive (max.) Shunt Cap (max.) Motional (max.) Tolerance (max.) Stability (max.) Aging (max.) 14.31818 MHz AT Parallel 0.1 mW 5 pF 0.016 pF 35 ppm 30 ppm 5 ppm 20 pF The CY28445-5 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28445-5 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. ..................... Document #: 38-07739 Rev *C Page 13 of 25 CY28445-5 Crystal Loading C lock C hip Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance the crystal will see must be considered to calculate the appropriate capacitive loading (CL). Figure 1 shows a typical crystal configuration using the two trim capacitors. An important clarification for the following discussion is that the trim capacitors are in series with the crystal not parallel. It’s a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. This is not true. Ci2 C i1 Pin 3 to 6p X2 X1 Cs1 Cs2 Trace 2.8 pF XTAL Ce1 C e2 Trim 33 pF Figure 2. Crystal Loading Example Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Figure 1. Crystal Capacitive Clarification Load Capacitance (each side) Ce = 2 * CL – (Cs + Ci) Calculating Load Capacitors In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides. Total Capacitance (as seen by the crystal) CLe = 1 1 ( Ce1 + Cs1 + Ci1 + 1 Ce2 + Cs2 + Ci2 ) CL....................................................Crystal load capacitance CLe......................................... Actual loading seen by crystal using standard value trim capacitors Ce..................................................... External trim capacitors Cs .............................................. Stray capacitance (terraced) Ci ...........................................................Internal capacitance (lead frame, bond wires etc.) CLKREQ# Description The CLKREQ# signals are active LOW inputs used for clean enabling and disabling selected SRC outputs. The outputs controlled by CLKREQ# are determined by the settings in register byte 8. The CLKREQ# signal is a de-bounced signal in that it’s state must remain unchanged during two consecutive rising edges of SRCC to be recognized as a valid assertion or deassertion. (The assertion and deassertion of this signal is absolutely asynchronous.). CLKREQ#X SRCT(free running) SRCC(free running) SRCT(stoppable) SRCT(stoppable) Figure 3. CLK_REQ# Deassertion/Assertion Waveform ..................... Document #: 38-07739 Rev *C Page 14 of 25 CY28445-5 CLKREQ# Assertion (CLKREQ# -> LOW) PD Assertion All differential outputs that were stopped are to resume normal operation in a glitch free manner. The maximum latency from the assertion to active outputs is between 2–6 SRC clock periods (2 clocks are shown) with all SRC outputs resuming simultaneously. All stopped SRC outputs must be driven high within 10 ns of CLKREQ# deassertion to a voltage greater than 200 mV. When PD is sampled high by two consecutive rising edges of CPUC, all single-ended outputs will be held low on their next high to low transition and differential clocks must held high or tri-stated (depending on the state of the control register drive mode bit) on the next diff clock# high to low transition within 4 clock periods. When the SMBus PD drive mode bit corresponding to the differential (CPU, SRC, and DOT) clock output of interest is programmed to ‘0’, the clock output are held with “Diff clock” pin driven high at 2 x Iref, and “Diff clock#” tristate. If the control register PD drive mode bit corresponding to the output of interest is programmed to “1”, then both the “Diff clock” and the “Diff clock#” are tri-state. Note the example below shows CPUT = 133 MHz and PD drive mode = ‘1’ for all differential outputs. This diagram and description is applicable to valid CPU frequencies 100, 133, 166, and 200 MHz. In the event that PD mode is desired as the initial power-on state, PD must be asserted high in less than 10 s after asserting Vtt_PwrGd#. It should be noted that 96_100_SSC will follow the DOT waveform is selected for 96 MHz and the SRC waveform when in 100-MHz mode. CLKREQ# Deassertion (CLKREQ# -> HIGH) The impact of deasserting the CLKREQ# pins is all SRC outputs that are set in the control registers to stoppable via deassertion of CLKREQ# are to be stopped after their next transition. The final state of all stopped DIF signals is low, both SRCT clock and SRCC clock outputs will not be driven.PD (Power-down) Clarification The VTT_PWRGD# /PD pin is a dual-function pin. During initial power-up, the pin functions as VTT_PWRGD#. Once VTT_PWRGD# has been sampled low by the clock chip, the pin assumes PD functionality. The PD pin is an asynchronous active high input used to shut off all clocks cleanly prior to shutting off power to the device. This signal is synchronized internal to the device prior to powering down the clock synthesizer. PD is also an asynchronous input for powering up the system. When PD is asserted high, all clocks need to be driven to a low value and held prior to turning off the VCOs and the crystal oscillator. PD C PU T , 133M H z C PU C , 133M H z SR C T 100M H z SR C C 100M H z U SB, 48M H z D O T 96T D O T 96C PC I, 33 M H z R EF Figure 4. PD Assertion Timing Waveform PD Deassertion The power-up latency is less than 1.8 ms. This is the time from the deassertion of the PD pin or the ramping of the power supply until the time that stable clocks are output from the clock chip. All differential outputs stopped in a three-state condition resulting from power down will be driven high in less than 300 s of PD deassertion to a voltage greater than ..................... Document #: 38-07739 Rev *C Page 15 of 25 200 mV. After the clock chip’s internal PLL is powered up and locked, all outputs will be enabled within a few clock cycles of each other. Below is an example showing the relationship of clocks coming up. It should be noted that 96_100_SSC will follow the DOT waveform is selected for 96 MHz and the SRC waveform when in 100-MHz mode. CY28445-5 Tstable 200 mV Figure 7. CPU_STP# Deassertion Waveform ..................... Document #: 38-07739 Rev *C Page 16 of 25 CY28445-5 1.8 ms CPU_STOP# PD CPUT(Free Running CPUC(Free Running CPUT(Stoppable) CPUC(Stoppable) DOT96T DOT96C Figure 8. CPU_STP#= Driven, CPU_PD = Driven, DOT_PD = Driven 1.8 ms CPU_STOP# PD CPUT(Free Running) CPUC(Free Running) CPUT(Stoppable) CPUC(Stoppable) DOT96T DOT96C Figure 9. CPU_STP# = Tri-state, CPU_PD = Tri-state, DOT_PD = Tri-state PCI_STP# Assertion The PCI_STP# signal is an active LOW input used for synchronous stopping and starting the PCI outputs while the rest of the clock generator continues to function. The set-up time for capturing PCI_STP# going LOW is 10 ns (tSU). (See Figure 10.) The PCIF clocks will not be affected by this pin if their corresponding control bit in the SMBus register is set to allow them to be free running. Tsu PCI_STP# PCI_F PCI SRC 100MHz Figure 10. PCI STP# Assertion Waveform ..................... Document #: 38-07739 Rev *C Page 17 of 25 CY28445-5 Tdrive_SRC Tsu PCI_STP# PCI_F PCI SRC 100MHz Figure 11. PCI_STP# Deassertion Waveform FS_A, FS_B,FS_C VTT_PW RGD# PW RGD_VRM 0.2-0.3mS Delay VDD Clock Gen State 0 Clock State W ait for VTT_PW RGD# State 1 State 2 Off Clock Outputs State 3 On On Off Clock VCO Device is not affected, VTT_PW RGD# is ignored Sample Sels Figure 12. VTTPWRGD# Timing Diagram S2 S1 Delay >0.25mS VTT_PWRGD# = Low Sample Inputs straps VDD_A = 2.0V Wait for