CY28447LFXC

CY28447 Clock Generator for Intel®Calistoga Chipset Features • 33-MHz PCI clocks • Buffered Reference Clock 14.318MHz • Compliant to Intel® CK410M • Low-voltage frequency select inputs • Selectable CPU frequencies • I2C support with readback capabilities • Differential CPU clock pairs • 100-MHz differential SRC clocks • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • 96-MHz differential dot clock • 3.3V power supply • 27-MHz Spread and Non-spread video clock • 72-pin QFN package • 48-MHz USB clock • SRC clocks independently stoppable through CLKREQ#[1:9] CPU SRC PCI REF DOT96 USB_48M LCD 27M x2 / x3 x9/11 x5 x2 x1 x1 x1 x2 • 96/100-MHz spreadable differential video clock Block Diagram SEL_CLKREQ PCI_STP# CPU PLL CPU_STP# CLKREQ[1:9]# PLL Reference Divider VDD REF[1:0] IREF VDD CPUT[0:1] CPUC[0:1] VDD CPUT2_ITP/SRCT10 CPUC2_ITP/SRCC10 ITP_SEL VDD SRCT(1:9]) SRCC(1:9]) FS[C:A] VDD PCI[1:4] VDD_PCI LVDS PLL Divider PCIF0 VDD SRCT0/100MT_SST SRCC0/100MC_SST VDD48 27MSpread FCTSEL1 Fixed PLL Divider CLKREQ9# CLKREQ8# SRCT_8 SRCC_8 VSS_SRC SRCC_7 SRCT_7 VDD_SRC SRCC_6 SRCT_6 CLKREQ6# SCRC_5 SRCT_5 SCRC_4 SRCT_4 CLKREQ4# SRCC_3 SRCT_3 14.318MHz Crystal 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 VDD_SRC SRCC_9 SRCT_9 VSS_SRC CPUC2_ITP / SRCC_10 CPUT2_ITP / SRCT_10 VDDA VSSA IREF CPUC1 CPUT1 VDD_CPU CPUC0 CPUT0 VSS_CPU SCLK SDATA VDD_REF VDD48 DOT96T DOT96C VDD48 48M 27M PLL VTT_PWRGD#/PD SDATA SCLK Divider VDD48 27MNon-spread I2C Logic .........................Document #: 38-07724 Rev *C Page 1 of 22 400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1 54 2 53 3 52 4 51 5 50 6 49 7 48 8 47 CY28447 9 46 10 45 11 44 12 43 13 42 14 41 15 40 16 39 17 38 18 37 VDD_SRC SRCC_2 SRCT_2 SRCC_1 SRCT_1 VDD_SRC SRCC_0 / LCD100MC SRCT_0 / LCD100MT CLKREQ1# FSB/TEST_MODE DOT96C / 27M_SS DOT96T / 27M_NSS VSS_48 48M / FSA VDD_48 VTT_PWRGD# / PD CLKREQ7# PCIF0/ITP_SEL 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 XOUT XIN VSS_REF REF1 REF0 / FSC_TEST_SEL CPU_STP# PCI_STP# CLKREQ2# PCI1 CLKREQ3# CLKREQ5# VDD_PCI VSS_PCI PCI2 PCI3 PCI4 / FCTSEL1 VSS_PCI VDD_PCI XIN XOUT Pin Configuration 1+(512) 416-9669 www.silabs.com CY28447 Pin Description Pin No. Name 1, 49, 54, 65 VDD_SRC Type PWR Description 3.3V power supply for outputs. 2, 3, 50, 51, 52, 53, 55, 56, 58, 59, 60, 61, 63, 64, 66, 67, 69, 70 SRCT/C[1:9] O, DIF 100-MHz Differential serial reference clocks. 4, 68 VSS_SRC 5, 6 CPUT2_ITP/SRCT10, O, DIF Selectable differential CPU or SRC clock output. CPUC2_ITP/SRCC10 ITP_SEL = 0 @ VTT_PWRGD# assertion = SRC10 ITP_SEL = 1 @ VTT_PWRGD# assertion = CPU2 7 VDDA PWR 3.3V power supply for PLL. 8 VSSA GND Ground for PLL. 9 IREF I GND Ground for outputs. A precision resistor is attached to this pin which is connected to the internal current reference. 10, 11, 13, 14 CPUT/C[0:1] O, DIF Differential CPU clock outputs. 12 VDD_CPU PWR 3.3V power supply for outputs. 15 VSS_CPU GND Ground for outputs. 16 SCLK 17 SDATA I SMBus-compatible SCLOCK. I/O, OD SMBus-compatible SDATA. 18 VDD_REF PWR 19 XOUT O, SE 14.318-MHz crystal output. I 3.3V power supply for outputs. 20 XIN 21 VSS_REF 22 REF1 23 REF0/FSC_TESTSEL I/O,PD Fixed 14.318 clock output / 3.3V-tolerant input for CPU frequency selection/Selects test mode if pulled to VIMFS_C when VTT_PWRGD# is asserted LOW. Refer to DC Electrical Specifications table for VILFS_C,VIMFS_C,VIHFS_C specifications. GND O 14.318-MHz crystal input. Ground for outputs. Fixed 14.318-MHz clock output. 24 CPU_STP# I, PU 3.3V LVTTL input for CPU_STP# active LOW. 25 PCI_STP# I, PU 3.3V LVTTL input for PCI_STP# active LOW. 26, 28, 29, 38, 46, 57, 62, 71, 72 CLKREQ[1:9]# I, PU 3.3V LVTTL input for enabling assigned SRC clock (active LOW). 27, 32, 33 PCI[1:3] O, SE 33-MHz clock outputs 30, 36 VDD_PCI PWR 3.3V power supply for outputs. 31, 35 VSS_PCI GND Ground for outputs. 34 PCI4/FCTSEL1 I/O, PD 33-MHz clock output / 3.3V LVTTL input for selecting pins 47,48 (SRC[T/C]0, 100M[T/C]) and pins 43,44 (DOT96[T/C] and 27M Spread and Non-spread) (sampled on the VTT_PWRGD# assertion). FCTS E L1 P in 43 37 ITP_SEL/PCIF0 P in 44 P in 47 P in 48 0 DOT96T DOT96C 96/100M_T 96/100M_C 1 27M_NSS 27M_SS SRCT0 SRCC0 I/O, PD, 3.3V LVTTL input to enable SRC10 or CPU2_ITP / 33-MHz clock output. SE (sampled on the VTT_PWRGD# assertion). 1 = CPU2_ITP, 0 = SRC10 ........................ Document #: 38-07724 Rev *C Page 2 of 22 CY28447 Pin Description (continued) Type Description 39 Pin No. VTT_PWRGD#/PD Name I, PD 3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FSA, FSB, FSC, FCTSEL1, and ITP_SEL. After VTT_PWRGD# (active LOW) assertion, this pin becomes a real-time input for asserting power down (active HIGH). 40 VDD_48 PWR 3.3V power supply for outputs. 41 48M/FSA I/O 42 VSS_48 GND 43, 44 DOT96T/ 27M_NSS DOT96C/ 27M_SS 45 FSB/TEST_MODE 47, 48 SRC[T/C]0/ LCD100M[T/C] Fixed 48-MHz clock output / 3.3V-tolerant input for CPU frequency selection Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. Ground for outputs. O, DIF Fixed 96-MHz clock output or 27 Mhz Spread and Non-spread output Selected via FCTSEL1 at VTTPWRGD# assertion. I 3.3V-tolerant input for CPU frequency selection. Selects Ref/N or Tri-state when in test mode 0 = Tri-state, 1 = Ref/N Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. O,DIF 100-MHz differential serial reference clock output / Differential 96/100-MHz SS clock for flat-panel display Selected via FCTSEL1 at VTTPWRGD# assertion. Frequency Select Pins (FSA, FSB, and FSC) initialize to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions. Host clock frequency selection is achieved by applying the appropriate logic levels to FSA, FSB, FSC inputs prior to VTT_PWRGD# assertion (as seen by the clock synthesizer). Upon VTT_PWRGD# being sampled LOW by the clock chip (indicating processor VTT voltage is stable), the clock chip samples the FSA, FSB, and FSC input values. For all logic levels of FSA, FSB, and FSC, VTT_PWRGD# employs a one-shot functionality in that once a valid LOW on VTT_PWRGD# has been sampled, all further VTT_PWRGD#, FSA, FSB, and FSC transitions will be ignored, except in test mode. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 2. Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface The block write and block read protocol is outlined in Table 3 while Table 4 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h) Table 1. Frequency Select Table FSA, FSB, and FSC[1] FSC FSB FSA CPU SRC PCIF/PCI 27MHz REF0 DOT96 USB 1 0 1 100 MHz 100 MHz 33 MHz 27 MHz 14.318 MHz 96 MHz 48 MHz 0 0 1 133 MHz 100 MHz 33 MHz 27 MHz 14.318 MHz 96 MHz 48 MHz 0 1 1 166 MHz 100 MHz 33 MHz 27 MHz 14.318 MHz 96 MHz 48 MHz 0 1 0 200 MHz 100 MHz 33 MHz 27 MHz 14.318 MHz 96 MHz 48 MHz . Table 2. Command Code Definition Bit 7 (6:0) Description 0 = Block read or block write operation, 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000' Note: 1. 27-MHz and 96-MHz can not be output at the same time. ........................ Document #: 38-07724 Rev *C Page 3 of 22 CY28447 Table 3. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 9 Description Start Block Read Protocol Bit 1 Slave address – 7 bits Write 8:2 9 Description Start Slave address – 7 bits Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 Command Code – 8 bits 18:11 Command Code – 8 bits 19 Acknowledge from slave 19 Acknowledge from slave Byte Count – 8 bits (Skip this step if I2C_EN bit set) 20 Repeat start 27:20 28 36:29 37 45:38 Acknowledge from slave 27:21 Slave address – 7 bits Data byte 1 – 8 bits 28 Read = 1 Acknowledge from slave 29 Acknowledge from slave Data byte 2 – 8 bits 46 Acknowledge from slave .... Data Byte/Slave Acknowledges .... Data Byte N – 8 bits .... Acknowledge from slave .... Stop 37:30 38 46:39 47 55:48 Byte Count from slave – 8 bits Acknowledge Data byte 1 from slave – 8 bits Acknowledge Data byte 2 from slave – 8 bits 56 Acknowledge .... Data bytes from slave / Acknowledge .... Data Byte N from slave – 8 bits .... NOT Acknowledge .... Stop Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 Description Start Slave address – 7 bits Byte Read Protocol Bit 1 8:2 Description Start Slave address – 7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 Command Code – 8 bits 18:11 Command Code – 8 bits 19 Acknowledge from slave 19 Acknowledge from slave 27:20 Data byte – 8 bits 28 Acknowledge from slave 29 Stop ........................ Document #: 38-07724 Rev *C Page 4 of 22 20 27:21 Repeated start Slave address – 7 bits 28 Read 29 Acknowledge from slave 37:30 Data from slave – 8 bits 38 NOT Acknowledge 39 Stop CY28447 Control Registers Byte 0: Control Register 0 Bit 7 @Pup 1 Name SRC[T/C]7 6 1 SRC[T/C]6 5 1 SRC[T/C]5 4 1 SRC[T/C]4 3 1 SRC[T/C]3 2 1 SRC[T/C]2 1 1 SRC[T/C]1 0 1 SRC[T/C]0 /LCD_96_100M[T/C] Description SRC[T/C]7 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]6 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]5 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]4 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]3 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]2 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]1 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]0 / LCD_96_100M[T/C] Output Enable 0 = Disable (Hi-Z), 1 = Enable Byte 1: Control Register 1 Bit @Pup Name 7 1 PCIF0 Description 6 1 5 1 USB_48MHz 4 1 REF0 REF0 Output Enable 0 = Disabled, 1 = Enabled 3 1 REF1 REF1 Output Enable 0 = Disabled, 1 = Enabled 2 1 CPU[T/C]1 CPU[T/C]1 Output Enable 0 = Disable (Tri-state), 1 = Enabled 1 1 CPU[T/C]0 CPU[T/C]0 Output Enable 0 = Disable (Tri-state), 1 = Enabled 0 0 CPU, SRC, PCI, PCIF Spread Enable PCIF0 Output Enable 0 = Disabled, 1 = Enabled 27M NSS / DOT_96[T/C] 27M Non-spread and DOT_96 MHz Output Enable 0 = Disable (Tri-state), 1 = Enabled USB_48M MHz Output Enable 0 = Disabled, 1 = Enabled PLL1 (CPU PLL) Spread Spectrum Enable 0 = Spread off, 1 = Spread on Byte 2: Control Register 2 Bit @Pup Name Description 7 1 PCI4 PCI4 Output Enable 0 = Disabled, 1 = Enabled 6 1 PCI3 PCI3 Output Enable 0 = Disabled, 1 = Enabled 5 1 PCI2 PCI2 Output Enable 0 = Disabled, 1 = Enabled 4 1 PCI1 PCI1 Output Enable 0 = Disabled, 1 = Enabled 3 1 Reserved Reserved, Set = 1 2 1 Reserved Reserved, Set = 1 1 1 CPU[T/C]2 CPU[T/C]2 Output Enable 0 = Disabled (Hi-Z), 1 = Enabled 0 1 Reserved Reserved, Set = 1 ........................ Document #: 38-07724 Rev *C Page 5 of 22 CY28447 Byte 3: Control Register 3 Bit @Pup Name Description 7 0 SRC7 Allow control of SRC[T/C]7 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 6 0 SRC6 Allow control of SRC[T/C]6 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 5 0 SRC5 Allow control of SRC[T/C]5 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 4 0 SRC4 Allow control of SRC[T/C]4 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 3 0 SRC3 Allow control of SRC[T/C]3 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 2 0 SRC2 Allow control of SRC[T/C]2 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 1 0 SRC1 Allow control of SRC[T/C]1 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 0 0 SRC0 Allow control of SRC[T/C]0 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Byte 4: Control Register 4 Bit @Pup Name 7 0 LCD_96_100M[T/C] Description 6 0 DOT96[T/C] DOT PWRDWN Drive Mode 0 = Driven in PWRDWN, 1 = Tri-state 5 0 RESERVED RESERVED, Set = 0 4 0 RESERVED 3 0 PCIF0 2 1 CPU[T/C]2 Allow control of CPU[T/C]2 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# 1 1 CPU[T/C]1 Allow control of CPU[T/C]1 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# 0 1 CPU[T/C]0 Allow control of CPU[T/C]0 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# LCD_96_100M[T/C] PWRDWN Drive Mode 0 = Driven in PWRDWN, 1 = Tri-state RESERVED, Set = 0 Allow control of PCIF0 with assertion of SW and HW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Byte 5: Control Register 5 Bit @Pup Name 7 0 SRC[T/C] SRC[T/C] Stop Drive Mode 0 = Driven when PCI_STP# asserted,1 = Tri-state when PCI_STP# asserted Description 6 0 CPU[T/C]2 CPU[T/C]2 Stop Drive Mode 0 = Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP# asserted 5 0 CPU[T/C]1 CPU[T/C]1 Stop Drive Mode 0 = Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP# asserted 4 0 CPU[T/C]0 CPU[T/C]0 Stop Drive Mode 0 = Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP# asserted 3 0 SRC[T/C][9:1] SRC[T/C][9:1] PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Tri-state when PD asserted 2 0 CPU[T/C]2 CPU[T/C]2 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Tri-state when PD asserted ........................ Document #: 38-07724 Rev *C Page 6 of 22 CY28447 Byte 5: Control Register 5 (continued) Bit @Pup Name Description 1 0 CPU[T/C]1 CPU[T/C]1 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Tri-state when PD asserted 0 0 CPU[T/C]0 CPU[T/C]0 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Tri-state when PD asserted Byte 6: Control Register 6 Bit @Pup Name 7 0 TEST_SEL Description 6 0 TEST_MODE 5 1 REF1 REF1 Output Drive Strength 0 = Low, 1 = High 4 1 REF0 REF0 Output Drive Strength 0 = Low, 1 = High 3 1 2 HW FSC FSC Reflects the value of the FSC pin sampled on power up 0 = FSC was low during VTT_PWRGD# assertion 1 HW FSB FSB Reflects the value of the FSB pin sampled on power up 0 = FSB was low during VTT_PWRGD# assertion 0 HW FSA FSA Reflects the value of the FSA pin sampled on power up 0 = FSA was low during VTT_PWRGD# assertion REF/N or Tri-state Select 0 = Tri-state, 1 = REF/N Clock Test Clock Mode Entry Control 0 = Normal operation, 1 = REF/N or Tri-state mode, PCI, PCIF and SRC clock SW PCI_STP Function outputs except those set 0=SW PCI_STP assert, 1= SW PCI_STP deassert to free running When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will be stopped in a synchronous manner with no short pulses. When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will resume in a synchronous manner with no short pulses. Byte 7: Vendor ID @Pup Name 7 Bit 0 Revision Code Bit 3 Revision Code Bit 3 Description 6 0 Revision Code Bit 2 Revision Code Bit 2 5 0 Revision Code Bit 1 Revision Code Bit 1 4 1 Revision Code Bit 0 Revision Code Bit 0 3 1 Vendor ID Bit 3 Vendor ID Bit 3 2 0 Vendor ID Bit 2 Vendor ID Bit 2 1 0 Vendor ID Bit 1 Vendor ID Bit 1 0 0 Vendor ID Bit 0 Vendor ID Bit 0 Byte 8: Control Register 8 Bit @Pup Name 7 0 RESERVED RESERVED, Set = 0 6 0 RESERVED RESERVED, Set = 0 5 0 RESERVED RESERVED, Set = 0 4 0 RESERVED RESERVED, Set = 0 RESERVED, Set = 0 3 0 RESERVED 2 1 USB_48M 1 1 RESERVED 0 1 PCIF0 Description USB_48MHz Output Drive Strength 0= Low, 1= High RESERVED, Set = 1 PCIF0 Output Drive Strength 0 = Low, 1 = High ........................ Document #: 38-07724 Rev *C Page 7 of 22 CY28447 Byte 9: Control Register 9 @Pup Name 7 Bit 0 RESERVED 6 0 RESERVED 5 0 S1 4 0 S0 3 1 RESERVED 2 1 27M_SS 1 1 0 0 Description RESERVED RESERVED 27M_SS / LCD 96_100M SS Spread Spectrum Selection table: S[1:0] SS% ‘00’ = –0.5%(Default value) ‘01’ = –1.0% ‘10’ = –1.5% ‘11’ = –2.0% RESERVED, Set = 1 27M Spread Output Enable 0 = Disable (Tri-state), 1 = Enabled 27M_SS Spread Enable 27M_SS Spread spectrum enable. 0 = Disable, 1 = Enable. RESERVED RESERVED set = 0 Byte 10: Control Register 10 @Pup Name 7 Bit 1 RESERVED RESERVED, Set = 1 Description 6 1 RESERVED RESERVED, Set = 1 5 1 SRC[T/C]9 SRC[T/C]9 Output Enable 0 = Disable (Hi-Z), 1 = Enable 4 1 SRC[T/C]8 SRC[T/C]8 Output Enable 0 = Disable (Hi-Z), 1 = Enable 3 0 RESERVED RESERVED, Set = 0 2 0 SRC[T/C]10 Allow control of SRC[T/C]10 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 1 0 SRC[T/C]9 Allow control of SRC[T/C]9 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 0 0 SRC[T/C]8 Allow control of SRC[T/C]8 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Byte 11: Control Register 11 @Pup Name 7 Bit 0 RESERVED RESERVED Description 6 HW RESERVED RESERVED 5 HW RESERVED RESERVED 4 HW RESERVED RESERVED 3 0 27M_SS / 27M_NSS 2 0 RESERVED RESERVED 1 0 RESERVED RESERVED Set = 0 0 HW RESERVED RESERVED 27-MHz (spread and non-spread) Output Drive Strength 0 = Low, 1 = High ........................ Document #: 38-07724 Rev *C Page 8 of 22 CY28447 Byte 12: Control Register 12 Bit @Pup Name Description 7 0 CLKREQ#9 CLKREQ#9 Input Enable 0 = Disable 1 = Enable 6 0 CLKREQ#8 CLKREQ#8 Input Enable 0 = Disable 1 = Enable 5 0 CLKREQ#7 CLKREQ#7 Input Enable 0 = Disable 1 = Enable 4 0 CLKREQ#6 CLKREQ#6 Input Enable 0 = Disable 1 = Enable 3 0 CLKREQ#5 CLKREQ#5 Input Enable 0 = Disable 1 = Enable 2 0 CLKREQ#4 CLKREQ#4 Input Enable 0 = Disable 1 = Enable 1 0 CLKREQ#3 CLKREQ#3 Input Enable 0 = Disable 1 = Enable 0 0 CLKREQ#2 CLKREQ#2 Input Enable 0 = Disable 1 = Enable Byte 13: Control Register 13 Bit @Pup Name Description 7 0 CLKREQ#1 6 1 LCD 96_100M Clock Speed 5 1 RESERVED RESERVED, Set = 1 4 1 RESERVED RESERVED, Set = 1 3 1 PCI4 PCI4 (Spread and Non-spread) Output Drive Strength 0 = Low, 1 = High 2 1 PCI3 PCI3 (Spread and Non-spread) Output Drive Strength 0 = Low, 1 = High 1 1 PCI2 PCI2 (Spread and Non-spread) Output Drive Strength 0 = Low, 1 = High 0 1 PCI1 PCI1 (Spread and Non-spread) Output Drive Strength 0 = Low, 1 = High CLKREQ#1 Input Enable 0 = Disable 1 = Enable LCD 96_100M Clock Speed 0 = 96 MHz 1 = 100 MHz Table 5. Crystal Recommendations Frequency (Fund) Cut Loading Load Cap Drive (max.) Shunt Cap (max.) Motional (max.) Tolerance (max.) Stability (max.) Aging (max.) 14.31818 MHz AT Parallel 0.1 mW 5 pF 0.016 pF 35 ppm 30 ppm 5 ppm 20 pF The CY28447 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28447 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. Crystal Loading Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance ........................ Document #: 38-07724 Rev *C Page 9 of 22 the crystal will see must be considered to calculate the appropriate capacitive loading (CL). Figure 1 shows a typical crystal configuration using the two trim capacitors. An important clarification for the following discussion is that the trim capacitors are in series with the crystal not parallel. It’s a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. This is not true. CY28447 (Ce1,Ce2) should be calculated to provide equal capacitance loading on both sides. Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Load Capacitance (each side) Ce = 2 * CL – (Cs + Ci) Total Capacitance (as seen by the crystal) Figure 1. Crystal Capacitive Clarification Calculating Load Capacitors In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides. Clock Chip Ci2 Ci1 Pin 3 to 6p Cs1 X2 X1 XTAL Ce2 = 1 1 ( Ce1 + Cs1 + Ci1 + 1 Ce2 + Cs2 + Ci2 ) CL....................................................Crystal load capacitance CLe......................................... Actual loading seen by crystal using standard value trim capacitors Ce..................................................... External trim capacitors Cs .............................................. Stray capacitance (terraced) Ci ...........................................................Internal capacitance (lead frame, bond wires etc.) CLK_REQ# Description The CLKREQ# signals are active LOW inputs used for clean enabling and disabling selected SRC outputs. The outputs controlled by CLKREQ# are determined by the settings in register byte 8. The CLKREQ# signal is a de-bounced signal in that it’s state must remain unchanged during two consecutive rising edges of SRCC to be recognized as a valid assertion or deassertion. (The assertion and deassertion of this signal is absolutely asynchronous.) CLK_REQ[1:9]# Assertion (CLKREQ# -> LOW) Cs2 Trace 2.8 pF Ce1 CLe Trim 33 pF Figure 2. Crystal Loading Example As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors All differential outputs that were stopped are to resume normal operation in a glitch-free manner. The maximum latency from the assertion to active outputs is between 2 and 6 SRC clock periods (2 clocks are shown) with all SRC outputs resuming simultaneously. All stopped SRC outputs must be driven HIGH within 10 ns of CLKREQ# deassertion to a voltage greater than 200 mV. CLK_REQ[1:9]# Deassertion (CLKREQ# -> HIGH) The impact of deasserting the CLKREQ# pins is that all SRC outputs that are set in the control registers to stoppable via deassertion of CLKREQ# are to be stopped after their next transition. The final state of all stopped DIF signals is LOW, both SRCT clock and SRCC clock outputs will not be driven. CLKREQ#X SRCT(free running) SRCC(free running) SRCT(stoppable) SRCT(stoppable) Figure 3. CLK_REQ#[1:9] Deassertion/Assertion Waveform ...................... Document #: 38-07724 Rev *C Page 10 of 22 CY28447 PD (Power-down) Clarification The VTT_PWRGD# /PD pin is a dual-function pin. During initial power-up, the pin functions as VTT_PWRGD#. Once VTT_PWRGD# has been sampled LOW by the clock chip, the pin assumes PD functionality. The PD pin is an asynchronous active HIGH input used to shut off all clocks cleanly prior to shutting off power to the device. This signal is synchronized internal to the device prior to powering down the clock synthesizer. PD is also an asynchronous input for powering up the system. When PD is asserted HIGH, all clocks need to be driven to a LOW value and held prior to turning off the VCOs and the crystal oscillator. PD (Power-down) Assertion When PD is sampled HIGH by two consecutive rising edges of CPUC, all single-ended outputs will be held LOW on their next HIGH-to-LOW transition and differential clocks must be held HIGH or tri-stated (depending on the state of the control register drive mode bit) on the next diff clock# HIGH-to-LOW transition within 4 clock periods. When the SMBus PD drive mode bit corresponding to the differential (CPU, SRC, and DOT) clock output of interest is programmed to ‘0’, the clock outputs are held with “Diff clock” pin driven HIGH at 2 x Iref, and “Diff clock#” tri-state. If the control register PD drive mode bit corresponding to the output of interest is programmed to “1”, then both the “Diff clock” and the “Diff clock#” are tri-state. Note that Figure 4 shows CPUT = 133 MHz and PD drive mode = ‘1’ for all differential outputs. This diagram and description is applicable to valid CPU frequencies 100, 133, 166, and 200 MHz. In the event that PD mode is desired as the initial power-on state, PD must be asserted HIGH in less than 10 s after asserting Vtt_PwrGd#. It should be noted that 96_100_SSC will follow the DOT waveform is selected for 96 MHz and the SRC waveform when in 100-MHz mode. PD Deassertion The power-up latency is less than 1.8 ms. This is the time from the deassertion of the PD pin or the ramping of the power supply until the time that stable clocks are output from the clock chip. All differential outputs stopped in a three-state condition resulting from power down will be driven high in less than 300 s of PD deassertion to a voltage greater than 200 mV. After the clock chip’s internal PLL is powered up and locked, all outputs will be enabled within a few clock cycles of each other. Figure 5 is an example showing the relationship of clocks coming up. It should be noted that 96_100_SSC will follow the DOT waveform is selected for 96 MHz and the SRC waveform when in 100-MHz mode. PD CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz DOT96T DOT96C PCI, 33 MHz REF Figure 4. Power-down Assertion Timing Waveform Tstable 200 mV Figure 7. CPU_STP# Deassertion Waveform 1.8 ms CPU_STOP# PD CPUT(Free Running CPUC(Free Running CPUT(Stoppable) CPUC(Stoppable) DOT96T DOT96C Figure 8. CPU_STP# = Driven, CPU_PD = Driven, DOT_PD = Driven ...................... Document #: 38-07724 Rev *C Page 12 of 22 CY28447 1.8mS CPU_STOP# PD CPUT(Free Running) CPUC(Free Running) CPUT(Stoppable) CPUC(Stoppable) DOT96T DOT96C Figure 9. CPU_STP# = Tri-state, CPU_PD = Tri-state, DOT_PD = Tri-state PCI_STP# Assertion The PCI_STP# signal is an active LOW input used for synchronous stopping and starting the PCI outputs while the rest of the clock generator continues to function. The set-up time for capturing PCI_STP# going LOW is 10 ns (tSU). (See Figure 10.) The PCIF clocks will not be affected by this pin if their corresponding control bit in the SMBus register is set to allow them to be free running. Tsu PCI_STP# PCI_F PCI SRC 100MHz Figure 10. PCI_STP# Assertion Waveform ...................... Document #: 38-07724 Rev *C Page 13 of 22 CY28447 PCI_STP# Deassertion The deassertion of the PCI_STP# signal will cause all PCI and stoppable PCIF clocks to resume running in a synchronous manner within two PCI clock periods after PCI_STP# transitions to a HIGH level. Tdrive_SRC Tsu PCI_STP# PCI_F PCI SRC 100MHz Figure 11. PCI_STP# Deassertion Waveform FS_A, FS_B,FS_C VTT_PW RGD# PW RGD_VRM 0.2-0.3mS Delay VDD Clock Gen State 0 Clock State W ait for VTT_PW RGD# State 1 State 2 Off Clock Outputs State 3 On On Off Clock VCO Device is not affected, VTT_PW RGD# is ignored Sample Sels Figure 12. VTT_PWRGD# Timing Diagram S2 S1 Delay >0.25mS VTT_PWRGD# = Low Sample Inputs straps VDD_A = 2.0V Wait for