CY28508OXCT

CY28508 333 MHz Low-Voltage Differential SSCG Features • Cypress Spread Spectrum for best electromagnetic interference (EMI) reduction • Supports HSTL-compatible differential outputs using recommended termination scheme • Three differential pairs of clocks • From 112.5 MHz to 225.0 MHz and from 166.6 MHz to 333.3-MHz output frequency • Two selectable I2C addresses • Block and byte mode I2C operation programmable registers • Smooth-Track frequency target slew rates as low as 100 KHz/usec in /2 mode and 70 KHz/usec in /3 mode • 2.5V output operation • 28-pin SSOP package Pin Configuration Block Diagram XIN XOUT 14.31818MHz XTAL REF 2.5V M0 N0 M1 N1 CPUT0 PLL CPUC0 OD FSEL CPUT1 CPUC1 SCLK CPUT2 SDATA Control Logic ADDRSEL CPUC2 REF VDDX XIN XOUT VSSX FSEL VDDC VSSC ADDRSEL LOCK SDATA SCLK VDD CPU_STOP# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CY28508 • Dual • I2C register programmable options • 3.3V core operation • One REF 14.318 MHz clock Dial-a-Frequency® • Four center-spread settings 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDDQ CPUT0 CPUC0 VSSQ VDDQ CPUT1 CPUC1 VSSQ VDDQ CPUT2 CPUC2 VSSQ VDDA VSSA CPU_STOP# LOCK ........................ Document #: 38-07534 Rev. *F Page 1 of 13 400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com CY28508 Pin Description [1] Pin Name Type Power Description 1 REF O VDDX Reference Clock. 3.3V 14.318-Mz clock output. 3 XIN I VDDX Crystal Connection or External Reference Frequency Input. This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. 4 XOUT O VDDX Crystal Connection. Connection for an external 14.318-MHz crystal output. 27, 23, 19 CPUT[0:2] O VDDQ CPUT Clock Outputs: Differential True CPU clock outputs. 26, 22, 18 CPUC[0:2] O VDDQ CPUC Clock Outputs: Differential Complementary CPU clock outputs. 6 FSEL I, PU VDD 250K 3.3V LVTTL input for CPU frequency selection. 0 = M&N register set 0, 1 = M&N register set 1. 11 SDATA I/O VDD I2C-compatible SDATA. 12 SCLK I VDD I2C-compatible SCLOCK. 14 CPU_STOP# I, PU VDD 250K CPU stop. 1 = CPUT/C running, 0 = CPUT stopped synchronously low and CPUC stopped synchronously high. REF remains running. 9 ADDRSEL I, PD VDD 250K I2C address selection. 0 = D2, 1 = D4. 10 LOCK Open Drain It is recommended that an external 10K resistor is connected to this pin. With this resistor, 1 = Signifies the VCO has locked onto the target frequency. 0 = Not locked to the designated M&N register pair target frequency. 16 VDDA PWR 3.3V power supply for analog PLL. 15 VSSA GND Ground for analog PLL. VDD 28, 24, 20 VDDQ PWR 2.5V power supply for output buffers. 25, 21, 17 VSSQ GND Ground for output buffers. 2 VDDX PWR 3.3V power supply for oscillator. 5 VSSX GND Ground for oscillator. 7 VDDC PWR 3.3V power supply for core. 8 VSSC GND Ground for core. 13 VDD PWR 3.3V power supply. Serial Data Interface Data Protocol To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting upon power-up, and therefore use of this interface is optional. The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individual indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 1. The block write and block read protocol is outlined in Table 2 while Table 3 outlines the corresponding byte write and byte read protocol. The Byte Count value returned is 09h. The slave receiver address is either D2 or D4, depending on the state of the ADDRSEL pin. Note: 1. Throughout this document logic 0 and logic 1 state signals are referenced. As a clarification it should be understood that 1 = high and 0 = low voltage levels. These levels are defined in the DC Electrical Specifications of this data sheet. ........................ Document #: 38-07534 Rev. *F Page 2 of 13 CY28508 Table 1. Command Code Definition Bit 7 (6:0) Description 0 = Block read or block write operation 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be ‘0000000’ Table 2. Block Read and Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 .... .... .... .... Block Write Protocol Description Start Slave address – 7 bits Write = 0 Acknowledge from slave Command Code – 8 bits ‘00000000’ stands for block operation Acknowledge from slave Byte Count from master – 8 bits Acknowledge from slave Data byte 0 from master – 8 bits Acknowledge from slave Data byte 1 from master – 8 bits Acknowledge from slave Data bytes from master/Acknowledge Data Byte N – 8 bits Acknowledge from slave Stop Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39:46 47 48:55 56 .... .... .... .... Block Read Protocol Description Start Slave address – 7 bits Write = 0 Acknowledge from slave Command Code – 8 bits ‘00000000’ stands for block operation Acknowledge from slave Repeat start Slave address – 7 bits Read = 1 Acknowledge from slave Byte count from slave – 8 bits Acknowledge Data byte 0 from slave – 8 bits Acknowledge Data byte 1 from slave – 8 bits Acknowledge Data bytes from slave/Acknowledge Data byte N from slave – 8 bits Not Acknowledge Stop Table 3. Byte Read and Byte Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29 Byte Write Protocol Description Start Slave address – 7 bits Write = 0 Acknowledge from slave Command Code – 8 bits ‘1xxxxxxx’ stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte from master – 8 bits Acknowledge from slave Stop ........................ Document #: 38-07534 Rev. *F Page 3 of 13 Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39 Byte Read Protocol Description Start Slave address – 7 bits Write = 0 Acknowledge from slave Command Code – 8 bits ‘1xxxxxxx’ stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address – 7 bits Read = 1 Acknowledge from slave Data byte from slave – 8 bits Not Acknowledge Stop CY28508 Serial Control Registers Byte 0 : CPU Control Register Bit @Pup Name 7 HW LOCK Description 6 0 SS_ENABLE 5 0 SST1 Select spread percentage 1. See Table 4 4 1 SST0 Select spread percentage 0. See Table 4 3 1 REF REF Output Enable 0 = Disabled (three-stated)), 1 = Enabled 2 1 CPUT/C2 CPU2 Output Enable 0 = Disabled (three-stated), 1 = Enabled 1 1 CPUT/C1 CPU1 Output Enable 0 = Disabled (three-stated), 1 = Enabled 0 1 CPUT/C0 CPU0 Output Enable 0 = Disabled (three-stated), 1 = Enabled Lock Detect: 0 = not at final frequency, 1 = VCO locked (read-only). 0 = disabled, 1 = enabled. Table 4. Spread Spectrum Table SST1 SST0 % Spread 0 0 0.125% Center spread Lexmark profile 0 1 0.25% Center spread Lexmark profile 1 0 0.5% Center spread Lexmark profile 1 1 0.5% Center spread Linear profile Glitch-free operation for both enabling and disabling Spread Spectrum. To achieve down spread operation, reprogram the N register to drop the frequency by half the spread amount. Byte 1: Dial-a-Frequency Control Register N0 [default = 112.35 MHz, N = 43d, ODSEL = 1] Bit @Pup Description 7 0 Test Mode: 0 = normal operation, 1 = phase-locked loop (PLL) bypass mode, when OD = 3 then /3, when OD = 2 then /2. 6 0 N6, most significant bit (MSB). 5 1 N5 4 0 N4 3 1 N3 2 0 N2 1 1 N1 0 1 N0, least significant bit (LSB). Byte 2: Dial-a-Frequency Control Register M0 [default = 112.35MHz, M = 49d, ODSEL = 1] Bit @Pup Description 7 0 The charge pump current value during Smooth-Track can be programmed to normal mode (2xICP) by setting this bit to “1.” The default value of “0” (1xICP) will program the charge pump current to half of normal and will reduce the bandwidth and hence the slew rate. 6 Pin 6 5 1 M5 MSB 4 1 M4 3 0 M3 2 0 M2 1 0 M1 0 1 M0, LSB FSEL operational status, whether HW or SW. 0 = M&N0, 1 = M&N1 (read only). ........................ Document #: 38-07534 Rev. *F Page 4 of 13 CY28508 Byte 3: Dial-a-Frequency Control Register N1 [default = 224.70 MHz, N = 86d, ODSEL = 1] Bit @Pup Description 7 0 Reserved, set = 0. 6 1 N6, MSB 5 0 N5 4 1 N4 3 0 N3 2 1 N2 1 1 N1 0 0 N0, LSB Byte 4: Dial-a-Frequency Control Register M1 [default = 224.70 MHz, M = 49d, ODSEL = 1] Bit @Pup 7 1 Reserved, set = 1. Description 6 1 SWODSEL: Output divider select. 0 = /2, 1 = /3. Changing the output divider causes large instantaneous changes in the CPU pulse width and should only be changed before system operation is to occur. 5 1 M5 MSB. 4 1 M4 3 0 M3 2 0 M2 1 0 M1 0 1 M0, LSB. Byte 5: Dial-a-Frequency Control Register N2 – Only Bit 7 is Used by the CY28508 Bit @Pup Description 7 0 UP/DN pulse width limit. During Smooth-Track, the bandwidth hence the slew rate is controlled through limiting the pulse width of the UP/DN pulse outputs of the phase detector going to the charge pump. The default is 0 = 20 ns and can be programmed to 1 = 40 ns, which will increase the slew rate. 6 0 Reserved, set = 0. 5 1 Reserved, set = 1. 4 1 Reserved, set = 1. 3 0 Reserved, set = 0. 2 0 Reserved, set = 0. 1 0 Reserved, set = 0. 0 0 Reserved, set = 0. Byte 6: Dial-a-Frequency Control Register M2 – Only Bits 6 and 7 are Used by the CY28508 Bit @Pup Description 7 1 FSEL Control: 1 = HW FSEL, 0 = SW FSEL 6 1 SW FSEL: 0 = SW MN0 select, 1 = SW MN1 select. Only valid when B6b7 = 0. 5 1 Reserved, set = 1. 4 1 Reserved, set = 1. 3 0 Reserved, set = 0. 2 0 Reserved, set = 0. 1 0 Reserved, set = 0. 0 0 Reserved, set = 0. ........................ Document #: 38-07534 Rev. *F Page 5 of 13 CY28508 Byte 7: Dial-a-Frequency Control Register N3 - Only bit 7 is used by the CY28508 Bit @Pup Description 7 1 Ns Setting. Ns is the total step time index during Smooth-Track for each increment or decrement during Smooth-Track. The default is 1 = 2048 and if you program a 0 = 1024, the step time will be half of this value. 6 1 Reserved, set = 0. 5 0 Reserved, set = 1. 4 0 Reserved, set = 1. 3 0 Reserved, set = 0. 2 0 Reserved, set = 0. 1 0 Reserved, set = 0. 0 0 Reserved, set = 0. Byte 8: Dial-a-Frequency Control Register M3, Only bit 7 is used by the CY28508 Bit @Pup Description 7 1 ICP Tracking. In the default mode (= 1) the ICP current increases and the VCO frequency increase to maintain constant bandwidth. If you program a “0,” then the ICP current will stay constant. 6 0 Reserved, set = 0. 5 1 Reserved, set = 1. 4 1 Reserved, set = 1. 3 0 Reserved, set = 0. 2 0 Reserved, set = 0. 1 0 Reserved, set = 0. 0 0 Reserved, set = 0. Dial-a-Frequency Feature Dial-a-frequency gives the designer direct access to the reference divider (M) and the feedback divider (N) of the internal PLL. VCO = (XTAL x 26.823) x (N/ M). Output Frequency = VCO/Output Divider. The VCO operating range is between 333 MHz and 675 MHz. The user must not program N and M values that would result in a VCO frequency outside of this specified range. Hardware Switching of Dial-a-Frequency Registers The architectural design of the HW Smooth-Track feature allows the system designer to configure two DAF registers that are selected via an FSEL input pin to select the desired final frequency. This slew rate control is defined as Smooth-Track and is used for all frequency change values programmed into the two DAF registers. There exists a LOCK output signal, which will activate when the final frequency is achieved by the VCO. For Ns = 2048 and M = 48, each step takes 492 s such that to increment 40 steps would take 19.7 ms. Spread Spectrum Modulation Rate Fmodulation (KHz) = 1500.25/M. The profile of the modulation is tuned for M = 48, such that deviations from this value could affect the Lexmark profile. ........................ Document #: 38-07534 Rev. *F Page 6 of 13 CY28508 SMBus DAF-N0 Latch Byte N0 W rite SMBus DAF-M0 Byte M0 W rite N Register SMBus DAF-N1 Latch Byte N1 W rite M Register SMBus DAF-M1 Byte M1 W rite FSEL Figure 1. Dial-a-Frequency Register Switching and Synchronizer Circuitry This circuitry is designed to present simultaneous M&N values to the VCO when writing to the I2C lines. If not for this delay in writing the N register value, the VCO would use a new N value and an old M value and would go to an indeterminate frequency until the next I2C byte was written. Crystal Recommendations configuration using the two trim capacitors. An important clarification for the following discussion is that the trim capacitors are in series with the crystal not parallel. It’s a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. The CY28508 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28508 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. Crystal Loading Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance the crystal will see must be considered to calculate the appropriate capacitive loading (CL). Figure 2 shows a typical crystal Figure 2. Crystal Capacitive Clarification Table 5. Crystal Recommendations Frequency (Fund) Cut Loading Load Cap Drive (max.) Shunt Cap (max.) Motional (max.) Tolerance (max.) Stability (max.) Aging (max.) 14.31818 MHz AT Parallel 0.1 mW 5 pF 0.016 pF 50 ppm 50 ppm 5 ppm 20 pF ........................ Document #: 38-07534 Rev. *F Page 7 of 13 CY28508 Calculating Load Capacitors Ce2) should be calculated to provide equal capacitive loading on both sides. In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides. Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Load Capacitance (each side) Ce = 2 * CL - (Cs + Ci) Total Capacitance (as seen by the crystal) CLe Clock Chip 1 1 ( Ce1 + Cs1 + Ci1 + 1 Ce2 + Cs2 + Ci2 ) CL....................................................Crystal load capacitance Ci2 Ci1 = Pin 3 to 6p CLe......................................... Actual loading seen by crystal using standard value trim capacitors Ce..................................................... External trim capacitors Cs ........................................... Stray capacitance (trace, etc.) X2 X1 Cs1 Cs2 Ci ........... Internal capacitance (lead frame, bond wires, etc.) Trace 2.8pF XTAL Ce1 Ce2 Trim 33pF Figure 3. Crystal Loading Example As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This mean the total capacitance on each side of the crystal must be twice the specified load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1, VD D _ALL CPU_STOP# Clarification The CPU_STOP# signal is an active LOW input used for synchronous stopping and starting of the CPU output clocks while the rest of the clock generator continues to function. The REF output is not affected by the CPU_STOP# signal. CPU_STOP# Assertion When CPU_STOP# pin is asserted, all CPUT/C outputs will be stopped after being sampled by two rising edges of the CPUT clocks. The final state of the stopped CPU signals is CPUT = LOW and CPU0C = HIGH. 2 .0 V CPUT CPUC LO C K REF < 1 .2 m s e c Figure 4. Power-up Signal Timing ........................ Document #: 38-07534 Rev. *F Page 8 of 13 CY28508 CPU_STOP# CPUT (internal) CPUC CPUT CPUC Figure 5. CPU_STOP# Assertion Waveform CPU_STOP# Deassertion The deassertion of the CPU_STOP# signal will cause all CPUT/C outputs that were stopped to resume normal operation in a synchronous manner. Synchronous manner meaning that no short or stretched clock pulses will be produces when the clock resumes. The maximum latency from the deassertion to active outputs is no more than two CPUC clock cycles. CPU_STOP# CPUT CPUC CPUT (internal) CPUC Figure 6. CPU_STOP# Deassertion Waveform ........................ Document #: 38-07534 Rev. *F Page 9 of 13 CY28508 Absolute Maximum Conditions[2] Parameter Description Condition Min. Max. Unit –0.5 5.5 V VDD, VDDC, 3.3V Supply Voltage VDDA, VDDX Maximum functional voltage VDDQ Analog Supply Voltage Maximum functional voltage –0.5 5.5 V VIN Input Voltage Relative to V SS –0.5 VDD + 0.5 V –65 150 °C 0 70 °C 150 °C – V TS Temperature, Storage Non-functional TA Temperature, Operating Ambient Functional TJ Temperature, Junction Functional ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 ØJC Dissipation, Junction to Case Mil-Spec 883E Method 1012.1 42 °C/W ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) 118 °C/W UL–94 Flammability Rating At 1/8 in. V–0 MSL Moisture Sensitivity Level 2000 1 DC Electrical Specifications Parameter Description Condition Min. Typ. Max. Unit 3.135 3.300 3.465 V 2.375 2.500 2.625 V 1.0 Vdc VDD, VDDA, 3.3 Operating Voltage VDDX, VDDC 3.3 ± 5% VDDQ 2.5 Operating Voltage 2.5 ± 5% VIL Input Low Voltage VIL for all inputs except XIN VIH Input High Voltage VIH for all inputs except XIN 2.0 IILC Input Leakage Current Except for internal pull-up or pull-down resistors –5 IIL Input Low Current (@VIL = VSS) For internal pull-up resistors 9 IIH Input High Current (@VIL =VDD) For internal pull-down resistors –9 IOLI2C I2C Sink Current VOL Output Low Voltage REF output VOH Output High Voltage REF output 2.4 VOLC Output Low Voltage CPU At load measurement point with recommended termination. See Figure 7. 0.0 0.4 Vdc VOHC Output High Voltage CPU At load measurement point with recommended termination. See Figure 7. 0.6 1.6 Vdc VXIH Xin High Voltage 0.7VDDX VDDX V VXIL Xin Low Voltage 0 0.3VDDX V 10 µA 5 pF IOZ Three-state leakage Current CIN Input Pin Capacitance Vdc 5 µA µA µA mA 0.4 Vdc Vdc For all pins including XIN COUT Output Pin Capacitance 6 pF LIN Input Pin Inductance 7 nH ZOUT Output Impedance of CPU Clock IDD3A Power supply current for all 3.3V VDDs Output is 224.7 MHz with VCO running 666.6 MHz with all three buffers enabled and loaded 80 100 mA IDD3B Power supply current for all 3.3V VDDs Output is 224.7 MHz with VCO running with VDDs with two buffers enabled and 666.6 MHz loaded 78 100 mA IDD3C Power supply current for all 3.3V VDDs Output is 224.7 MHz with VCO running with one buffer enabled and loaded 666.6 MHz 77 100 mA Both rising and falling  18 Note: 2. Multiple Sequence: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. ...................... Document #: 38-07534 Rev. *F Page 10 of 13 CY28508 DC Electrical Specifications (continued) Parameter Description Condition Min. Typ. Max. Unit 8 10 mA Power supply current for all 2.5V VDDs Output is 224.7 MHz with VCO running with three buffers enabled and loaded 666.6 MHz 180 225 mA IDD2B Power supply current for all 2.5V VDDs Output is 224.7 MHz with VCO running with two buffers enabled and loaded 666.6 MHz 124 155 mA IDD2C Power supply current for all 2.5V VDDs Output is 224.7 MHz with VCO running with one buffer enabled and loaded 666.6 MHz 70 90 mA IDD2D Power supply current for all 2.5V VDDs Output is 224.7 MHz with VCO running with all buffers disabled 666.6 MHz 7 10 mA IDDR Power supply additional current for all Output is 14.31818 MHz with VCO 3.3V VDDs for loaded REF only running 666.6 MHz IDD2A AC Electrical Specifications Parameter Description Condition Min. Typ. Max. Unit Crystal TDC Xin Duty Cycle Measured at VDDX/2 TPERIOD Xin Period Measured at VDDX/2. The VCO frequency must remain within its operating range. 45 55 52.4 69.841 87.3 % ns REF Output TDC REF Duty Cycle TRISE/TFALL REF Rise and Fall Times TCCJ REF Cycle to Cycle Jitter Measured at 1.5V, 15-pF lumped load. 45 Measured from 0.4V to 2.4V, 15-pF lumped load. 1 50 Measured at 1.5V, 15-pF lumped load. 55 % 4 ns 1000 ps 2 ns 55 % 500 ps 100 ps 135 ps LOCK Output TFALL Lock Fall Time Measured from 2.4V to 0.4V, 10-pF lumped load and 10K pull-up. 0.5 Measured at 0.62V at measuring point. See Figure 7. 45 Measured from 0.3V to 0.9V. See Figure 7. 150 CPU Outputs TDC CPUT/C Duty Cycle TRISE/TFALL CPUT/C Rise and Fall Times TSKEW CPUT/C to CPUT/C Clock Skew Measured at 0.62V at measuring point. See Figure 7. TCCJ CPUT/C Cycle to Cycle Jitter Measured at 0.62V at measuring point. See Figure 7. VDIF Differential Voltage Swing At load measuring point. See Figures 7 and 8. 50 1.24 VOX Crossing Point Voltage At load measuring point. See Figures 7 and 8. 0.4 FVCO VCO Operating Frequency Over voltage, temperature and process 333 TXS Power-on Hold Off Outputs will be as shown in Figure 6 0.62 1.5 0.9 V 675 MHz 1.2 ms Table 6. Slew Rate Settings Output Divider = /3 (Measured over 10 s) M N Range Typ. Max. Slew Rate (kHz/S) Worst-Corner Max Slew Rate (kHz/S) ICP B2b7 Ns B7b7 Variable ICP B8b7 49 43-65 55 100 x1 2048 1 49 65-86 75 140 x1 2048 or 1024 1 49 43-86 45 70 x1 2048 0 Table 7. Slew Rate Settings Output Divider = /2 (Measured over 10 s) M N Range Typ. Max. Slew Rate (kHz/S) Worst-Corner Max Slew Rate (kHz/S) ICP B2b7 Ns B7b7 Variable ICP B8b7 49 43-65 80 150 x1 2048 1 49 65-86 120 200 x1 2048 or 1024 1 49 43-86 65 100 x1 2048 0 ...................... Document #: 38-07534 Rev. *F Page 11 of 13 CY28508  T PCB  Measurement Point CPUT 8 inches   5pF T PCB  Measurement Point CPUC  VDDQ 2.5V V 8 inches Figure 7. Output Test Loading OHC V V 5pF V D IF V SSQ SS Figure 8. CPU Signaling ...................... Document #: 38-07534 Rev. *F Page 12 of 13 OX CY28508 Ordering Information Part Number CY28508OC CY28508OCT Package Type Product Flow 28-pin SSOP Commercial, 0° to 70°C 28-pin SSOP – Tape and Reel Commercial, 0° to 70°C Lead- Free CY28508OXC CY28508OCXT 28-pin SSOP Commercial, 0° to 70°C 28-pin SSOP – Tape and Reel Commercial, 0° to 70°C Package Drawing and Dimensions 28-lead (5.3 mm) Shrunk Small Outline Package O28 ...................... Document #: 38-07534 Rev. *F Page 13 of 13 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. 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