CY505YC64DT
Clock Generator for Intel®Broadwater Chipset
Features
• Compliant to Intel® CK505
• Low-voltage frequency select input
• I2C support with readback capabilities
• Selectable CPU frequencies
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• Differential CPU clock pairs
• 3.3V Power supply/0.7V for Diff IOs
• 100 MHz Differential SRC clocks
• 64-pin TSSOP package
• 100 MHz Differential LCD clock
• 96 MHz Differential Dot clock
Table 1. Output Configuration Table
• 48 MHz USB clocks
CPU
SRC
• 33 MHz PCI clock
x2/x3
x8/12
PCI REF DOT96 USB_48M
x6
x1
x1
x1
LCD
x1
• 25 MHz PATA clock
• Buffered Reference Clock 14.318 MHz
Block Diagram
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CY505YC64DT
PCI_0/OE#_0/2_A
VDD_PCI
PCI_1/OE#_1/4_A
PCI_2/TME
PCI_3/ FSD*
PCI_4/ SRC5_EN
PCIF_0/ ITP_EN
VSS_PCI
VDD_48
USB_48/ FSA
VSS_48
VDD_IO
SRCT0/DOT96T
SRCC0/DOT96C
VSS_IO
VDD_PLL3
SRCT1/LCDT_100/25M
SRCC1/LCDC_100
VSS_PLL3
VDD_PLL3_IO
SRCT2_SATAT
SRCC2_SATAC
VSS_SRC
SRCT3/OE#_0/2_B
SRCC3/OE#_1/4_B
VDD_SRC_IO
SRCT4
SRCC4
VSS_SRC
SRCT9
SRCC9
SRCC11/OE#_9
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SCLK
SDATA
REF0/FSC/TEST_SEL
VDD_REF
XTAL_IN
XTAL_OUT
VSS_REF
FSB/TEST_MODE
CK_PWRGD/PWRDWN#
VDD_CPU
CPUT0
CPUC0
VSS_CPU
CPUT1
CPUC1
VDD_CPU_IO
IO_VOUT
SRCT8/ CPU2_ITPT
SRCC8/ CPU2_ITPC
VDD_SRC_IO
SRCT7/OE#_8
SRCC7/OE#_6
VSS_SRC
SRCT6
SRCC6
VDD_SRC
SRCT5/ PCI_STOP#
SRCC5/ CPU_STOP#
VDD_SRC_IO
SRCC10
SRCT10
SRCT11/OE#_10
* Internal Pull-Down
...................... Document #: 001-03543 Rev *E Page 1 of 24
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
www.silabs.com
CY505YC64D
Pin Definitions
Pin No.
Name
1
PCI_0/OE#_0/2_A
Type
Description
I/O, SE 33 MHz clock/3.3V OE# Input mappable via I2C to control either SRC 0 or
SRC 2. Default PCI0
2
VDD_PCI
3
PCI_1/OE#_1/4_A
I/O, SE 33 MHz clock/3.3V OE# Input mappable via I2C to control either SRC 1 or
SRC 4. Default PCI1.
PWR
4
PCI_2/TME
I/O, SE 3.3V tolerance input for overclocking enable pin 33 MHz clock.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
5
PCI_3/FSD
I/O, SE, 3.3V tolerant input for CPU frequency selection/33 MHz clock.
PD
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
6
PCI_4/SRC5_SEL
I/O, SE 3.3V tolerant input to enable SRC5/33 MHz clock output.
(sampled on the CK_PWRGD assertion)
1 = SRC5, 0 = CPU_STOP#
7
PCIF_0/ITP_EN
I/O, SE 3.3V LVTTL input to enable SRC8 or CPU2_ITP/33 MHz clock output.
PD
(sampled on the CK_PWRGD assertion)
1 = CPU2_ITP, 0 = SRC8
8
VSS_PCI
GND
9
VDD_48
PWR
10
USB_48/FSA
11
VSS_48
GND
Ground for outputs.
12
VDD_IO
PWR
0.7V Power supply for outputs.
13, 14
SRCT0/DOT96T
SRCC0/DOT96C
15
VSS_IO
GND
Ground for PLL2.
16
VDD_PLL3
PWR
3.3V Power supply for PLL3
17, 18
SRCT1/LCDT_100/25M
SRCC1/LCDC_100
I/O
3.3V Power supply for PCI PLL.
Ground for outputs.
3.3V Power supply for outputs and PLL.
3.3V tolerant input for CPU frequency selection/fixed 48 MHz clock output.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
O, DIF 100 MHz Differential serial reference clocks/Fixed 96 MHz clock output.
Selected via I2C default is SRC0.
O, DIF, 100 MHz Differential serial reference clocks/100 MHz LCD video clock/25 MHz
SE
SATA clock. Default LCD
19
VSS_PLL3
GND
Ground for PLL3.
20
VDD_PLL3_IO
PWR
0.7V Power supply for PLL3 outputs.
21, 22
SRCT/C[2]/SATA
23
VSS_SRC
24, 25
SRCT3/OE#_0/2_B
SRCC3/OE#_1/4_B
26
VDD_SRC_IO
27, 28
SRCT/C[4]
29
VSS_SRC
30, 31
SRCT/C[9]
33, 32
SRCT11/OE#_10
SRCC11/OE#_9
34, 35, SRCT/C[10]
36
VDD_SRC_IO
38, 37
SRCT5/PCI_STOP#
SRCC5/CPU_STOP#
39
VDD_SRC
O, DIF 100 MHz Differential serial reference clocks.
GND
I/O,
Dif
PWR
Ground for outputs.
100-MHz Differential serial reference clocks/3.3V OE#_0/2_B, input,
mappable via I2C to control either SRC 0 or SRC 2/3.3V OE#_1/4_B input,
mappable via I2C to control either SRC 1 or SRC 4. Default SRC3
0.7V power supply for SRC outputs.
O, DIF 100 MHz Differential serial reference clocks.
GND
Ground for outputs.
O, DIF 100 MHz Differential serial reference clocks.
I/O,
Dif
100 MHz Differential serial reference clocks/3.3V OE#9 Input controlling
SRC9/3.3V OE#10 Input controlling SRC10. Default SRC11.
O, DIF 100 MHz Differential serial reference clocks.
PWR
I/O,
Dif
PWR
0.7V Power supply for SRC outputs.
3.3V tolerant input for stopping PCI and SRC outputs/3.3V tolerant input for
stopping CPU outputs/100 MHz Differential serial reference clocks. Default
SRC5
3.3V Power supply for SRC PLL.
......................Document #: 001-03543 Rev *E Page 2 of 24
CY505YC64D
Pin Definitions (continued)
Pin No.
Name
41, 40 SRCT/C[6]
Type
Description
O, DIF 100 MHz Differential serial reference clocks.
42
VSS_SRC
44, 43
SRCT7/OE#_8
SRCC7/OE#_6
I/O,
Dif
45
VDD_SRC_IO
PWR
47, 46
SRCT8/CPUT2_ITPT,
SRCC8/CPUC2_ITPC
48
IO_VOUT
49
VDD_CPU_IO
51, 50
CPUT/C[1]
52
VSS_CPU
54, 53 CPUT/C[0]
GND
Ground for outputs.
100 MHz Differential serial reference clocks/3.3V OE#8 Input controlling
SRC8/3.3V OE#6 Input controlling SRC6. Default SRC7.
0.7V power supply for SRC outputs.
O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 @ CK_PWRGD
assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
O
Integrated Linear Regulator Control.
PWR
0.7V Power supply for CPU outputs.
O, DIF Differential CPU clock outputs. Note: CPU1 is the iAMT clock and is on in that
mode.
GND
Ground for outputs.
O, DIF Differential CPU clock outputs. Note: CPU1 is the iAMT clock and is on in that
mode.
55
VDD_CPU
56
CK_PWRGD/PWRDWN#
PWR
I
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A,
FS_B, FS_C, FS_D, SRC5_SEL, and ITP_EN.
After CK_PWRGD (active HIGH) assertion, this pin becomes a real-time input
for asserting power down (active LOW).
57
FSB/TEST_MODE
I
3.3V tolerant input for CPU frequency selection.
Selects Ref/N or Tri-state when in test mode
0 = Tri-state, 1 = Ref/N.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
58
VSS_REF
GND
59
XOUT
O, SE 14.318 MHz Crystal output.
I
3.3V Power supply for CPU PLL.
Ground for outputs.
60
XIN
61
VDD_REF
62
REF0/FSC/TEST_SEL
I/O
3.3V tolerant input for CPU frequency selection/fixed 14.318 clock output.
Selects test mode if pulled to VIHFS_C when CK_PWRGD is asserted HIGH.
Refer to DC Electrical Specifications table for VILFS_C, VIMFS_C, VIHFS_C specifications.
63
SMB_DATA
I/O
SMBus compatible SDATA.
64
SMB_CLK
I
PWR
14.318 MHz Crystal input.
3.3V Power supply for outputs and also maintains SMBUS registers during
power-down.
SMBus compatible SCLOCK.
......................Document #: 001-03543 Rev *E Page 3 of 24
CY505YC64D
Frequency Select Pin (FSA, FSB, FSC, and FSD)
To achieve host clock frequency selection, apply the appropriate logic levels to FS_A, FS_B, FS_C, and FS_D inputs
before VTT_PWRGD# assertion (as seen by the clock synthesizer). When VTT_PWRGD# is sampled LOW by the clock
chip (indicating processor VTT voltage is stable), the clock
chip samples the FS_A, FS_B, FS_C, and FS_D input values.
For all logic levels of FS_A, FS_B, FS_C, FS_D, and FS_E,
VTT_PWRGD# employs a one-shot functionality, in that once
a valid LOW on VTT_PWRGD# has been sampled, all further
VTT_PWRGD#, FS_A, FS_B, FS_C, and FS_D transitions will
be ignored, except in test mode.
Frequency Select Pin (FSA, FSB, FSC, and FSD)
Input Conditions
Output Frequency
FSD
FSC
FSB
FSA
FSEL_3
FSEL_2
FSEL_1
FSEL_0
CPU
(MHz)
SRC
(MHz)
SATA
(MHz)
DOT96
(MHz)
USB
(MHz)
PCI
(MHz)
REF
(MHz)
0
1
0
1
100
100
100
96
48
33.3
14.318
0
0
0
1
133
100
100
96
48
33.3
14.318
0
0
1
1
166
100
100
96
48
33.3
14.318
0
0
1
0
200
100
100
96
48
33.3
14.318
0
0
0
0
266
100
100
96
48
33.3
14.318
0
1
0
0
333
100
100
96
48
33.3
14.318
0
1
1
0
400
100
100
96
48
33.3
14.318
0
1
1
1
200
100
100
96
48
33.4
14.318
1
1
0
1
100.9
100
100
96
48
33.3
14.318
1
0
0
1
133.9
100
100
96
48
33.3
14.318
1
0
1
1
166.9
100
100
96
48
33.3
14.318
1
0
1
0
200.9
100
100
96
48
33.3
14.318
1
0
0
0
266.9
100
100
96
48
33.3
14.318
1
1
0
0
333.9
100
100
96
48
33.3
14.318
1
1
1
0
400.9
100
100
96
48
33.3
14.318
1
1
1
1
200.9
100
100
96
48
33.3
14.318
Serial Data Interface
Data Protocol
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 2.
The block write and block read protocol is outlined in Table 3
while Table 4 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h)
.
Table 2. Command Code Definition
Bit
7
(6:0)
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
......................Document #: 001-03543 Rev *E Page 4 of 24
CY505YC64D
Table 3. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
Description
Start
Block Read Protocol
Bit
1
Slave address–7 bits
8:2
Description
Start
Slave address–7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
18:11
19
27:20
28
36:29
37
45:38
Command Code–8 bits
18:11
Command Code–8 bits
Acknowledge from slave
19
Acknowledge from slave
Byte Count–8 bits
(Skip this step if I2C_EN bit set)
20
Repeat start
Acknowledge from slave
Data byte 1–8 bits
Acknowledge from slave
Data byte 2–8 bits
27:21
Read = 1
29
Acknowledge from slave
37:30
46
Acknowledge from slave
....
Data Byte/Slave Acknowledges
....
Data Byte N–8 bits
....
Acknowledge from slave
....
Stop
Slave address–7 bits
28
38
46:39
47
55:48
Byte Count from slave–8 bits
Acknowledge
Data byte 1 from slave–8 bits
Acknowledge
Data byte 2 from slave–8 bits
56
Acknowledge
....
Data bytes from slave/Acknowledge
....
Data Byte N from slave–8 bits
....
NOT Acknowledge
....
Stop
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
Description
Start
Byte Read Protocol
Bit
1
Slave address–7 bits
8:2
Description
Start
Slave address–7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
18:11
19
27:20
Command Code–8 bits
Acknowledge from slave
Data byte–8 bits
18:11
19
20
28
Acknowledge from slave
29
Stop
27:21
Command Code–8 bits
Acknowledge from slave
Repeated start
Slave address–7 bits
28
Read
29
Acknowledge from slave
37:30
Data from slave–8 bits
38
NOT Acknowledge
39
Stop
Control Registers
Byte 0: Control Register 0
Bit
@Pup
Name
......................Document #: 001-03543 Rev *E Page 5 of 24
Description
CY505YC64D
Byte 0: Control Register 0
7
HW pin
FS_C
CPU Frequency Select Bit, set by HW
6
HW pin
FS_B
CPU Frequency Select Bit, set by HW
5
HW pin
FS_A
CPU Frequency Select Bit, set by HW
4
0
iAMT_EN
3
0
RESERVED
2
0
SRC_SEL
Select source for SRC clock,
0 = SRC_MAIN = PLL1, PLL3_CFB Table applies
1 = SRC_MAIN = PLL3, PLL3_CFB Table does not apply
1
0
SATA_SEL
Select source of SATA clock
0 = SATA SRC_MAIN, 1= SATA PLL2
0
1
PD_Restore
Save Config. In powerdown
0 = Config. Cleared, 1 = Config. Saved
Set via SMBus or by combination of PWRDWN, CPU_STP, and PCI_STP
0 = Legacy Mode, 1 = iAMT Enabled
RESERVED
Byte 1: Control Register 1
Bit
@Pup
7
0
SRC0_SEL
6
0
PLL1_SS_DC
Select for down or center SS,
0 = Down spread, 1 = Center spread
5
0
PLL3_SS_DC
Select for down or center SS,
0 = Down spread, 1 = Center spread
4
0
PLL3_CFB3
Bit 4:1 only apply when SRC_SEL=0
3
0
PLL3_CFB2
2
0
PLL3_CFB1
1
1
PLL3_CFB0
0
1
Name
PCI_SEL
Description
Select for SRC0 or DOT96, 0 = SRC0, 1 = DOT96
0000 = PLL3 Disable Default
0001 = 100 MHz 0.5% SSC Stby
0010 = 100 MHz 0.5% SSC
0011 = 100 MHz 1.0% SSC
0100 = 100 MHz 1.5% SSC
0101 = 100 MHz 2.0% SSC
0110 = RESERVED
0111 = RESERVED
1000 = RESERVED
1001 = RESERVED
1010 = RESERVED
1011 = RESERVED
1100 = 25 MHz, 3.3V
1101 = RESERVED
1110 = RESERVED
1111 = RESERVED
PLL3 OFF, SRC1 = SRC_MAIN
PLL3 ON, SRC1 = SRC_MAIN
Only SRC1 sourced from PLL3
Only SRC1 sourced from PLL3
Only SRC1 sourced from PLL3
Only SRC1 sourced from PLL3
Enabled through Byte 8 Bit 1
Select PCI Clock source from PLL1 or SRC_MAIN
0 = PLL1, 1 = SRC_MAIN
Byte 2: Control Register 2
Bit
@Pup
Name
Description
7
1
REF
Output enable for REF
0 = Output Disabled, 1 = Output Enabled
6
1
USB
Output enable for USB
0 = Output Disabled, 1 = Output Enabled
5
1
PCIF_0
Output enable for PCIF_0
0 = Output Disabled, 1 = Output Enabled
4
1
PCI4
Output enable for PCI4, 0 = Output Disabled, 1 = Output Enabled
3
1
PCI3
Output enable for PCI3, 0 = Output Disabled, 1 = Output Enabled
2
1
PCI2
Output enable for PCI2, 0 = Output Disabled, 1 = Output Enabled
......................Document #: 001-03543 Rev *E Page 6 of 24
CY505YC64D
Byte 2: Control Register 2 (continued)
Bit
@Pup
Name
Description
1
1
PCI1
Output enable for PCI1, 0 = Output Disabled, 1 = Output Enabled
0
1
PCI0
Output enable for PCI0, 0 = Output Disabled, 1 = Output Enabled
Byte 3: Control Register 3
Bit
@Pup
Name
Description
7
1
SRC[T/C]11
Output enable for SRC11, 0 = Output Disabled, 1 = Output Enabled
6
1
SRC[T/C]10
Output enable for SRC10, 0 = Output Disabled, 1 = Output Enabled
5
1
SRC[T/C]9
Output enable for SRC9, 0 = Output Disabled, 1 = Output Enabled
4
1
SRC[T/C]8/ITP_OE
3
1
SRC[T/C]7
Output enable for SRC7, 0 = Output Disabled, 1 = Output Enabled
2
1
SRC[T/C]6
Output enable for SRC6, 0 = Output Disabled, 1 = Output Enabled
1
1
SRC[T/C]5
Output enable for SRC5, 0 = Output Disabled, 1 = Output Enabled
0
1
SRC[T/C]4
Output enable for SRC4, 0 = Output Disabled, 1 = Output Enabled
Output enable for SRC8 or ITP, 0 = Output Disabled, 1 = Output Enabled
Byte 4: Control Register 4
Bit
@Pup
Name
7
1
SRC[T/C]3
Description
6
1
SRC[T/C]2/SATA
5
1
SRC[T/C]1
4
1
SRC[T/C]0/DOT96[T/C]
3
1
CPU[T/C]1
Output enable for CPU1, 0 = Output Disabled, 1 = Output Enabled
2
1
CPU[T/C]0
Output enable for CPU0, 0 = Output Disabled, 1 = Output Enabled
1
1
PLL1_SS_EN
Enable PLL1’s spread modulation,
0 = Spread Disabled 1 = Spread Enabled
0
1
PLL3_SS_EN
Enable PLL3’s spread modulation
0 = Spread Disabled, 1 = Spread Enabled
Output enable for SRC3, 0 = Output Disabled, 1 = Output Enabled
Output enable for SATA/SRC2, 0 = Output Disabled, 1 = Output Enabled
Output enable for SRC, 0 = Output Disabled, 1 = Output Enabled
Output enable for SRC0/DOT96
0 = Output Disabled, 1 = Output Enabled
Byte 5: Control Register 5
Bit
@Pup
Name
Description
7
0
OE#_0/2_EN_A
Enable OE#_0/2 (clk req)
0 = Disabled OE#_0/2, 1 = Enabled OE#_0/2,
6
0
OE#_0/2_SEL_A
Set OE#_0/2 SRC0 or SRC2
0 = OE#_0/2SRC0, 1 = OE#_0/2SRC2
5
0
OE#_1/4_EN_A
Enable OE#_1/4 (clk req)
0 = Disabled OE#_1/4, 1 = Enabled OE#_1/4,
4
0
OE#_1/4_SEL_A
Set OE#_1/4 SRC1 or SRC4
0 = OE#_1/4SRC1, 1 = OE#_1/4SRC4
3
0
OE#_0/2_EN_B
Enable OE#_0/2 (clk req)
0 = Disabled OE#_0/2 1 = Enabled OE#_0/2
2
0
OE#_0/2_SEL_B
Set OE#_0/2 SRC0 or SRC2
0 = OE#_0/2SRC0, 1 = OE#_0/2SRC2
1
0
OE#_1/4_EN_B
Enable OE#_1/4 (clk req)
0 = Disabled OE#_1/4, 1 = Enabled OE#_1/4,
0
0
OE#_1/4_SEL_B
Set OE#_1/4 SRC1 or SRC4
0 = OE#_1/4SRC1, 1 = OE#_1/4SRC4
......................Document #: 001-03543 Rev *E Page 7 of 24
CY505YC64D
Byte 6: Control Register 6
Bit
@Pup
Name
7
0
OE#_6_EN
Enable OE#_6 (clk req) SRC6
Description
6
0
OE#_8_EN
Enable OE#_8 (clk req) SRC8
5
0
OE#_9_EN
Enable OE#_9 (clk req) SRC9
4
0
OE#_10_EN
Enable OE#_10 (clk req) SRC10
3
0
RESERVED
RESERVED
2
0
RESERVED
RESERVED
1
0
LCD_100_STP_CTRL
If set, LCD_100 stop with PCI_STOP#
0 = free running, 1 = PCI_STOP# stoppable
0
0
SRC_STP_CTRL
If set, SRCs stop with PCI_STOP#
0 = free running, 1 = PCI_STOP# stoppable
Byte 7: Vendor ID
Bit
@Pup
Name
7
0
Rev Code Bit 3
Revision Code Bit 3
Description
6
0
Rev Code Bit 2
Revision Code Bit 2
5
1
Rev Code Bit 1
Revision Code Bit 1
4
1
Rev Code Bit 0
Revision Code Bit 0
3
1
Vendor ID bit 3
Vendor ID Bit 3
2
0
Vendor ID bit 2
Vendor ID Bit 2
1
0
Vendor ID bit 1
Vendor ID Bit 1
0
0
Vendor ID bit 0
Vendor ID Bit 0
Byte 8: Control Register 8
Bit
@Pup
Name
7
0
Device_ID3
7
0
Device_ID2
5
0
Device_ID1
4
1
Device_ID0
3
0
RESERVED
RESERVED
2
0
RESERVED
RESERVED
1
0
25 MHz
0
0
RESERVED
Description
0000 = CK505 Yellow Cover Device, 56-pin TSSOP
0001 = CK505 Yellow Cover Device, 64-pin TSSOP
0010 = CK505 Yellow Cover Device, 48-pin QFN (reserved)
0011 = CK505 Yellow Cover Device, 56-pin QFN (reserved)
0100 = CK505 Yellow Cover Device, 64-pin QFN (reserved)
0101 = CK505 Yellow Cover Device, 72-pin QFN (reserved)
0110 = CK505 Yellow Cover Device, 48-pin SSOP (reserved)
0111 = CK505 Yellow Cover Device, 48-pin SSOP (reserved)
1000 = Reserved
1001 = Reserved
1010 = Reserved
1011 = Reserved
1100 = Reserved
1101 = Reserved
1110 = Reserved
1111 = Reserved
Output enable for 25 MHz, 0 = Output Disabled, 1 = Output Enabled
RESERVED
Byte 9 Control Register 9
Bit
@Pup
Name
......................Document #: 001-03543 Rev *E Page 8 of 24
Description
CY505YC64D
Byte 9 Control Register 9
7
0
PCIF_0_with PCI_STOP# Allows control of PCIF_0 with assertion of PCI_STOP#
0 = Free running PCIF, 1 = Stopped with PCI_STOP#
6
HW_Pin
5
1
REF drive strength
REF drive strength, 0 = Low 1x, 1 = High 2x
4
0
TEST_MODE_SEL
Mode select either REF/N or tri-state
0 = All output tri-state, 1 = All output REF/N
3
0
TEST_MODE_ENTRY
2
1
IO_VOUT2
1
0
IO_VOUT1
0
1
IO_VOUT0
TME_STRAP
Trusted mode enable strap status, 0 = normal, 1 = no overclocking
Allow entry into test mode
0=Normal operation, 1=Enter test mode
IO_VOUT[2,1,0]
000 = 0.3V
001 = 0.4V
010 = 0.5V
011 = 0.6V
100 = 0.7V
101 = 0.8V, Default
110 = 0.9V
111 = 1.0V
Byte 10 Control Register 10
Bit
@Pup
Name
Description
7
0
RESERVED
RESERVED
6
0
RESERVED
RESERVED
5
0
RESERVED
RESERVED
4
0
RESERVED
RESERVED
3
0
RESERVED
RESERVED
2
0
RESERVED
RESERVED
1
0
RESERVED
RESERVED
0
0
RESERVED
RESERVED
Byte 11 Control Register 11
Bit
@Pup
Name
7
0
RESERVED
RESERVED
Description
6
0
RESERVED
RESERVED
5
0
RESERVED
RESERVED
4
0
RESERVED
RESERVED
3
0
RESERVED
RESERVED
2
0
RESERVED
RESERVED
1
0
RESERVED
RESERVED
0
0
RESERVED
RESERVED
Byte 12 Byte Count
Bit
@Pup
Name
7
0
RESERVED
Description
6
0
RESERVED
5
0
BC5
Byte count
4
0
BC4
Byte count
3
1
BC3
Byte count
2
1
BC2
Byte count
RESERVED
RESERVED
......................Document #: 001-03543 Rev *E Page 9 of 24
CY505YC64D
Byte 12 Byte Count (continued)
Bit
@Pup
Name
Description
1
0
BC1
Byte count
0
1
BC0
Byte count
Byte 13 Control Register 13
Bit
@Pup
Name
Description
7
1
USB drive strength
USB drive strength, 0 = Low, 1= High
6
1
PCI/PCIF drive strength
PCI drive strength, 0 = Low, 1 = High
5
0
PLL1_Spread
Select percentage of spread for PLL1, 0 = 0.5%, 1=1%
4
1
SATA_SS_EN
Enable SATA spread modulation,
0 = Spread Disabled 1 = Spread Enabled
3
1
CPU[T/C]2
Allow control of CPU2 with assertion of CPU_STOP#
0 = Free running, 1 = Stopped with CPU_STOP#
2
1
CPU[T/C]1
Allow control of CPU1 with assertion of CPU_STOP#
0 = Free running, 1 = Stopped with CPU_STOP#
1
1
CPU[T/C]0
Allow control of CPU0 with assertion of CPU_STOP#
0 = Free running, 1 = Stopped with CPU_STOP#
0
1
SW_PCI
SW PCI_STP# Function
0 = SW PCI_STP assert, 1 = SW PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
Byte 14 Control Register 14
Bit
@Pup
Name
Description
7
0
CPU_DAF_N7
6
0
CPU_DAF_N6
5
0
CPU_DAF_N5
4
0
CPU_DAF_N4
3
0
CPU_DAF_N3
If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and
CPU_DAF_M[6:0] will be used to determine the CPU output frequency. The
setting of the FS_Override bit determines the frequency ratio for CPU and
other output clocks. When it is cleared, the same frequency ratio stated in
the Latched FS[D:A] register will be used. When it is set, the frequency ratio
stated in the FSEL[3:0] register will be used
2
0
CPU_DAF_N2
1
0
CPU_DAF_N1
0
0
CPU_DAF_N0
Byte 15 Control Register 15
Bit
@Pup
Name
Description
7
0
CPU_DAF_N8
See Byte 14 for description
6
0
CPU_DAF_M6
5
0
CPU_DAF_M5
4
0
CPU_DAF_M4
3
0
CPU_DAF_M3
2
0
CPU_DAF_M2
If Prog_CPU_EN is set, the values programmed are in CPU_FSEL_N[8:0]
and CPU_FSEL_M[6:0] will be used to determine the CPU output
frequency. The setting of the FS_Override bit determines the frequency
ratio for CPU and other output clocks. When it is cleared, the same
frequency ratio stated in the Latched FS[D:A] register will be used. When it
is set, the frequency ratio stated in the FSEL[3:0] register will be used
1
0
CPU_DAF_M1
0
0
CPU_DAF_M0
....................Document #: 001-03543 Rev *E Page 10 of 24
CY505YC64D
Byte 16 Control Register 16
Bit
@Pup
Name
7
0
PCI-E_N7
PCI-E Dial-A-Frequency™ Bit N7
Description
6
0
PCI-E_N6
PCI-E Dial-A-Frequency Bit N6
5
0
PCI-E_N5
PCI-E Dial-A-Frequency Bit N5
4
0
PCI-E_N4
PCI-E Dial-A-Frequency Bit N4
3
0
PCI-E_N3
PCI-E Dial-A-Frequency Bit N3
2
0
PCI-E_N2
PCI-E Dial-A-Frequency Bit N2
1
0
PCI-E_N1
PCI-E Dial-A-Frequency Bit N1
0
0
PCI-E_N0
PCI-E Dial-A-Frequency Bit N0
Byte 17 Control Register 17
Bit
@Pup
Name
7
0
SMSW_EN
Description
6
0
SMSW_SEL
Smooth switch select, 0 = CPU_PLL, 1 = SRC_PLL
5
0
RESERVED
RESERVED
4
0
Prog_PCI-E_EN
Programmable PCI-E frequency enable, 0 = Disabled, 1= Enabled
3
0
Prog_CPU_EN
Programmable CPU frequency enable, 0 = Disabled, 1= Enabled
2
0
FS_D
1
0
RESERVED
RESERVED
0
0
RESERVED
RESERVED
Enable Smooth Switching, 0 = Disabled, 1= Enabled
CPU Frequency Select Bit, reflect value of FSD in latches open state
Table 5. Crystal Recommendations
Frequency
(Fund)
Cut
Loading Load Cap
Drive
(max.)
Shunt Cap
(max.)
Motional
(max.)
Tolerance
(max.)
Stability
(max.)
Aging
(max.)
14.31818 MHz
AT
Parallel
0.1 mW
5 pF
0.016 pF
35 ppm
30 ppm
5 ppm
20 pF
The CY505YC64DT requires a parallel resonance crystal.
Substituting a series resonance crystal causes the
CY505YC64DT to operate at the wrong frequency and violate
the ppm specification. For most applications there is a
300-ppm frequency shift between series and parallel crystals
due to incorrect loading.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance
the crystal sees must be considered to calculate the appropriate capacitive loading (CL).
Figure 1 shows a typical crystal configuration using the two
trim capacitors. An important clarification for the following
discussion is that the trim capacitors are in series with the
crystal not parallel. The common misconception that load
capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal is
not true.
....................Document #: 001-03543 Rev *E Page 11 of 24
Figure 1. Crystal Capacitive Clarification
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
CY505YC64D
Associated Register Bits
CPU_DAF Enable – This bit enables CPU DAF mode. By
default, it is not set. When set, the operating frequency is
determined by the values entered into the CPU_DAF_N
register. Note that the CPU_DAF_N and M register must
contain valid values before CPU_DAF is set. Default = 0, (No
DAF).
C lock C hip
Ci2
C i1
Pin
3 to 6p
X2
X1
Cs1
CPU_DAF_N – There are nine bits (for 512 values) to linearly
change the CPU frequency (limited by VCO range). Default =
0, (0000). The allowable values for N are detailed in the
Frequency Select Table.
Cs2
Trace
2.8 pF
XTAL
Ce1
C e2
SRC_DAF Enable – This bit enables SRC DAF mode. By
default, it is not set. When set, the operating frequency is
determined by the values entered into the SRC_DAF_N
register. Note that the SRC_DAF_N register must contain valid
values before SRC_DAF is set. Default = 0, (No DAF).
Trim
33 pF
Figure 2. Crystal Loading Example
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
Load Capacitance (each side)
Ce = 2 * CL – (Cs + Ci)
=
1
1
( Ce1 + Cs1
+ Ci1 +
1
Ce2 + Cs2 + Ci2
SRC_DAF_N – There are nine bits (for 512 values) to linearly
change the CPU frequency (limited by VCO range). Default =
0, (0000). The allowable values for N are detailed in the
Frequency Select Table.
Smooth Switching
Total Capacitance (as seen by the crystal)
CLe
CPU DAF M – There are 7 bits (for 128 values) to linearly
change the CPU frequency (limited by VCO range). Default =
0, the allowable values for M are detailed in the Frequency
Select Table.
)
CL ................................................... Crystal load capacitance
CLe .........................................Actual loading seen by crystal
using standard value trim capacitors
Ce .....................................................External trim capacitors
Cs ............................................. Stray capacitance (terraced)
Ci .......................................................... Internal capacitance
(lead frame, bond wires etc.)
Dial-A-Frequency (CPU & PCIEX)
This feature allows users to over-clock their systems by slowly
stepping up the CPU or SRC frequency. When the programmable output frequency feature is enabled, the CPU and SRC
frequencies are determined by the following equation:
Fcpu = G * N/M or Fcpu=G2 * N, where G2 = G/M.
‘N’ and ‘M’ are the values programmed in Programmable
Frequency Select N-Value Register and M-Value Register,
respectively. ‘G’ stands for the PLL Gear Constant, which is
determined by the programmed value of FS[E:A]. See
Frequency Table for the Gear Constant for each Frequency
selection. The PCI Express only allows user control of the N
register, the M value is fixed and documented in the Frequency
Select Table.
In this mode, the user writes the desired N and M value into
the DAF I2C registers. The user cannot change only the M
value and must change both the M and the N values at the
same time, if they require a change to the M value. The user
may change only the required N value.
....................Document #: 001-03543 Rev *E Page 12 of 24
The device contains 1 smooth switch circuit that is shared by
the CPU PLL and SRC PLL. The smooth switch circuit ensures
that when the output frequency changes by overclocking, the
transition from the old frequency to the new frequency is a
slow, smooth transition containing no glitches. The rate of
change of output frequency when using the smooth switch
circuit is less than 1 MHz/0.667 s. The frequency overshoot
and undershoot is less than 2%.
The Smooth Switch circuit can be assigned as auto or manual.
In Auto mode, clock generator will assign smooth switch
automatically when the PLL does overclocking. For manual
mode, the smooth switch circuit can be assigned to either PLL
via SMBus. By default the smooth switch circuit is set to auto
mode. Either PLL can still be over-clocked when it does not
have control of the smooth switch circuit but it is not
guaranteed to transition to the new frequency without large
frequency glitches.
It is not recommended to enable over-clocking and change the
N values of both PLLs in the same SMBUS block write and use
smooth switch mechanism on spread spectrum on/off.
PD# Clarification
The CK_PWRGD/PD# pin is a dual-function pin. During initial
power-up, the pin functions as CK_PWRGD. Once
CK_PWRGD has been sampled HIGH by the clock chip, the
pin assumes PD# functionality. The PD# pin is an
asynchronous active LOW input used to shut off all clocks
cleanly prior to shutting off power to the device. This signal is
synchronized internal to the device prior to powering down the
clock synthesizer. PD# is also an asynchronous input for
powering up the system. When PD# is asserted LOW, all
clocks need to be driven to a LOW value and held prior to
turning off the VCOs and the crystal oscillator.
CY505YC64D
PD Assertion
When PS is sampled HIGH by two consecutive rising edges of
CPUC, all single-ended outputs will be held LOW on their next
HIGH-to-LOW transition and differential clocks must held
LOW. In the event that PD mode is desired as the initial
power-on state, PD must be asserted HIGH in less than 10 s
after asserting CK_PWRGD.
PD#
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
USB, 48MHz
DOT96T
DOT96C
PCI, 33 MHz
REF
Figure 3. PD Assertion Timing Waveform
PD# Deassertion
The power-up latency is less than 1.8 ms. This is the time from
the deassertion of the PD# pin or the ramping of the power
supply until the time that stable clocks are output from the
clock chip. All differential outputs stopped in a three-state
condition resulting from power down will be driven high in less
than 300 s of PD# deassertion to a voltage greater than
200 mV. After the clock chip’s internal PLL is powered up and
locked, all outputs will be enabled within a few clock cycles of
each other. Below is an example showing the relationship of
clocks coming up.
Tstable
200 mV
CPU_STP# Deassertion Waveform
1.8mS
CPU_STOP#
PD#
CPUT(Free Running
CPUC(Free Running
CPUT(Stoppable)
CPUC(Stoppable)
DOT96T
DOT96C
CPU_STP# = Driven, CPU_PD = Driven, DOT_PD = Driven
....................Document #: 001-03543 Rev *E Page 14 of 24
CY505YC64D
1.8mS
CPU_STOP#
PD#
CPUT(Free Running)
CPUC(Free Running)
CPUT(Stoppable)
CPUC(Stoppable)
DOT96T
DOT96C
CPU_STP# = Tri-state, CPU_PD = Tri-state, DOT_PD = Tri-state
PCI_STP# Assertion
The PCI_STP# signal is an active LOW input used to synchronously stop and start the PCI outputs while the rest of the clock
generator continues to function. The set-up time for capturing
PCI_STP# going LOW is 10 ns (tSU). (See Figure 5.) The PCIF
clocks will not be affected by this pin if their corresponding
control bit in the SMBus register is set to allow them to be free
running.
T su
P C I_S T P #
P C I_F
PCI
S R C 100M H z
Figure 5. PCI_STP# Assertion Waveform
PCI_STP# Deassertion
The deassertion of the PCI_STP# signal causes all PCI and
stoppable PCIF clocks to resume running in a synchronous
manner within two PCI clock periods after PCI_STP# transitions to a HIGH level.
Tsu
Tdrive_SRC
PCI_STP#
PCI_F
PCI
SRC 100MHz
Figure 6. PCI_STP# Deassertion Waveform
....................Document #: 001-03543 Rev *E Page 15 of 24
CY505YC64D
F S _ A , F S _ B ,F S _C ,F S _ D
CK_PW R G D
PW RG D_VRM
0 .2 -0 .3m S
D ela y
V D D C lo ck G e n
C loc k S tate
C loc k O utp u ts
C loc k V C O
S ta te 0
W ait fo r
V T T _P W R G D #
S ta te 1
D e vice is no t a ffe c te d ,
V T T _P W R G D # is ig no re d
S a m ple S e ls
S ta te 2
O ff
S ta te 3
On
On
O ff
Figure 7. CK_PWRGD Timing Diagram
.
Table 6. Output Driver Status during PCI-STOP# and CPU-STOP#
PCI_STOP# Asserted
Single-ended Clocks Stoppable
Differential Clocks
CPU_STOP# Asserted
Driven Low
Running
Non Stoppable
Running
Running
Stoppable
Clock Drive High
Clock Drive High
Clock# Driven Low
Clock# Driven Low
Running
Running
Non Stoppable
SMBus OE Disabled
Driven Low
Clock Driven Low
Table 7. Output Driver Status
All Single-ended Clocks
All Differential Clocks except CPU1
CPU1
w/o Strap
w/Strap
Clock
Clock#
Clock
Clock#
Latches Open State
Low
Hi-Z
Low
Low
Low
Low
Powerdown
Low
Low
Low
Low
Low
Low
M1
Low
Low
Low
Low
Running
Running
PD_RESTORE
If a ‘0’ is set for Byte 0 bit 0 then, upon assertion of PWRDWN#
LOW, the CY505 will initiate a full reset. The results of this will
be that the clock chip will emulate a cold power on start and
go to the ‘Latches Open’ state. If the PD_RESTORE bit is set
to a ‘1’ then the configuration is stored upon PWRDWN#
asserted LOW. Note that if the iAMT bit, Byte 0 bit 3, is set to
a ‘1’ then the PD_RESTORE bit must be ignored. In other
words, in Intel iAMT mode, PWRDWN# reset is not allowed.
....................Document #: 001-03543 Rev *E Page 16 of 24
CY505YC64D
Figure 8. Clock Generator Power-up/Run State Diagram
0XXXXX
BSEL's loaded serially
See Clock Off
to M 1 transition
for details
Latches
Open
M1
iAM T M ode
10XX1X
11XX1X
11XX0X
iAM T_EN Bit=0
via CK505
M0
Norm al
Operation
1000XX
10XX00
10XX01
11XX01
Pow er Dow n
1101XX
1111XX
CPU STOP
1100XX 1101XX
1100XX
1111XX
CPU & PCI STOP
1110XX 1101XX
1110XX 1100XX
Clock OFF
0XXXXX
1110XX
1111XX
Bit 5
VDD_MAIN
Bit 4
CKPW RGD/
PW RDW N
PCI STOP
Bit 3
Bit 2
Bit 1
Bit 0
CPU_STOP#
PCI_STOP#
iAMT_EN
PD_RESTORE
....................Document #: 001-03543 Rev *E Page 17 of 24
CY505YC64D
Absolute Maximum Conditions
Parameter
Description
Condition
Min.
Max.
Unit
VDD
Core Supply Voltage
–0.5
4.6
V
VDD_A
Analog Supply Voltage
–0.5
4.6
V
VDD_IO
IO Supply Voltage
1.5
V
VIN
Input Voltage
Relative to VSS
–0.5
4.6
VDC
TS
Temperature, Storage
Non-functional
–65
150
°C
TA
Temperature, Operating Ambient
Functional
0
85
°C
TJ
Temperature, Junction
Functional
–
150
°C
ØJC
Dissipation, Junction to Case
Mil-STD-883E Method 1012.1
–
20
°C/W
ØJA
Dissipation, Junction to Ambient
JEDEC (JESD 51)
–
60
°C/W
ESDHBM
ESD Protection (Human Body Model) MIL-STD-883, Method 3015
2000
–
V
UL-94
Flammability Rating
MSL
Moisture Sensitivity Level
At 1/8 in.
V–0
1
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter
Description
VDD core
3.3V Operating Voltage
Condition
3.3 ± 5%
Min.
Max.
Unit
3.135
3.465
V
VIH
3.3V Input High Voltage (SE)
2.0
VDD + 0.3
V
VIL
3.3V Input Low Voltage (SE)
VSS–0.3
0.8
V
VIHI2C
Input High Voltage
SDATA, SCLK
2.2
–
V
VILI2C
Input Low Voltage
SDATA, SCLK
–
1.0
V
VIH_FS
FS_[A,B] Input High Voltage
0.7
1.5
V
VIL_FS
FS_[A,B] Input Low Voltage
VSS–0.3
0.35
V
VIHFS_C_TEST
FS_C Input High Voltage
VIMFS_C_NORMAL FS_C Input Middle Voltage
2
VDD + 0.3
V
0.7
1.5
V
VILFS_C_NORMAL
FS_C Input Low Voltage
VSS–0.3
0.35
V
IIH
Input High Leakage Current
except internal pull-down resistors,
0 < VIN < VDD
–
5
A
IIL
Input Low Leakage Current
except internal pull-up resistors,
0 < VIN < VDD
–5
–
A
VOH
3.3V Output High Voltage (SE)
IOH = –1 mA
2.4
–
V
IOL = 1 mA
V
VOL
3.3V Output Low Voltage (SE)
–
0.4
VDD IO
Low Voltage IO Supply Voltage
0.72
0.88
VOH
3.3V Input High Voltage (DIFF)
0.70
0.90
V
VOL
3.3V Input Low Voltage (DIFF)
0.40
V
IOZ
High-impedance Output Current
–10
10
A
CIN
Input Pin Capacitance
1.5
5
pF
COUT
Output Pin Capacitance
LIN
Pin Inductance
VXIH
Xin High Voltage
VXIL
Xin Low Voltage
IDD3.3V
Dynamic Supply Current
....................Document #: 001-03543 Rev *E Page 18 of 24
6
pF
7
nH
0.7VDD
VDD
V
0
0.3VDD
V
–
250
mA
–
CY505YC64D
AC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
47.5
52.5
%
69.841
71.0
ns
–
10.0
ns
Crystal
TDC
XIN Duty Cycle
The device will operate reliably with
input duty cycles up to 30/70 but the
REF clock duty cycle will not be within
specification
TPERIOD
XIN Period
When XIN is driven from an external
clock source
TR/TF
XIN Rise and Fall Times
Measured between 0.3VDD and 0.7VDD
TCCJ
XIN Cycle to Cycle Jitter
As an average over 1-s duration
LACC
Long-term Accuracy
–
500
ps
–
300
ppm
%
CPU at 0.7V
TDC
CPUT and CPUC Duty Cycle
Measured at 0V differential @ 0.1s
45
55
TPERIOD
100 MHz CPUT and CPUC Period
Measured at 0V differential @ 0.1s
9.99900
10.0100
ns
TPERIOD
133 MHz CPUT and CPUC Period
Measured at 0V differential @ 0.1s
7.49925
7.50075
ns
TPERIOD
166 MHz CPUT and CPUC Period
Measured at 0V differential @ 0.1s
5.99940
6.00060
ns
TPERIOD
200 MHz CPUT and CPUC Period
Measured at 0V differential @ 0.1s
4.99950
5.00050
ns
TPERIOD
266 MHz CPUT and CPUC Period
Measured at 0V differential @ 0.1s
3.74963
3.75038
ns
TPERIOD
333 MHz CPUT and CPUC Period
Measured at 0V differential @ 0.1s
2.99970
3.00030
ns
TPERIOD
400 MHz CPUT and CPUC Period
Measured at 0V differential @ 0.1s
2.49975
2.50025
ns
TPERIODSS
100 MHz CPUT and CPUC Period, SSC
Measured at 0V differential @ 0.1s
9.99900
10.0100
ns
TPERIODSS
133 MHz CPUT and CPUC Period, SSC
Measured at 0V differential @ 0.1s
7.49925
7.50075
ns
TPERIODSS
166 MHz CPUT and CPUC Period, SSC
Measured at 0V differential @ 0.1s
5.99940
6.00060
ns
TPERIODSS
200 MHz CPUT and CPUC Period, SSC
Measured at 0V differential @ 0.1s
4.99950
5.00050
ns
TPERIODSS
266 MHz CPUT and CPUC Period, SSC
Measured at 0V differential @ 0.1s
3.74963
3.75038
ns
TPERIODSS
333 MHz CPUT and CPUC Period, SSC
Measured at 0V differential @ 0.1s
2.99970
3.00030
ns
TPERIODSS
400 MHz CPUT and CPUC Period, SSC
Measured at 0V differential @ 0.1s
2.49975
2.50025
ns
TPERIODAbs
100 MHz CPUT and CPUC Absolute period
Measured at 0V differential @ 1 clock
9.91400
10.0860
ns
TPERIODAbs
133 MHz CPUT and CPUC Absolute period
Measured at 0V differential @ 1 clock
7.41425
7.58575
ns
TPERIODAbs
166 MHz CPUT and CPUC Absolute period
Measured at 0V differential @ 1 clock
5.91440
6.08560
ns
TPERIODAbs
200 MHz CPUT and CPUC Absolute period
Measured at 0V differential @ 1 clock
4.91450
5.08550
ns
TPERIODAbs
266 MHz CPUT and CPUC Absolute period
Measured at 0V differential @ 1 clock
3.66463
3.83538
ns
TPERIODAbs
333 MHz CPUT and CPUC Absolute period
Measured at 0V differential @ 1 clock
2.91470
3.08530
ns
TPERIODAbs
400 MHz CPUT and CPUC Absolute period
Measured at 0V differential @ 1 clock
2.41475
2.58525
ns
TPERIODSSAbs 100 MHz CPUT and CPUC Absolute period, SSC Measured at 0V differential @ 1 clock
9.91400
10.1363
ns
TPERIODSSAbs 133 MHz CPUT and CPUC Absolute period, SSC Measured at 0V differential @ 1 clock
7.41425
7.62345
ns
TPERIODSSAbs 166 MHz CPUT and CPUC Absolute period, SSC Measured at 0V differential @ 1 clock
5.91440
6.11576
ns
TPERIODSSAbs 200 MHz CPUT and CPUC Absolute period, SSC Measured at 0V differential @ 1 clock
4.91450
5.11063
ns
TPERIODSSAbs 266 MHz CPUT and CPUC Absolute period, SSC Measured at 0V differential @ 1 clock
3.66463
3.85422
ns
TPERIODSSAbs 333 MHz CPUT and CPUC Absolute period, SSC Measured at 0V differential @ 1 clock
2.91470
3.10038
ns
TPERIODSSAbs 400 MHz CPUT and CPUC Absolute period, SSC Measured at 0V differential @ 1 clock
2.41475
2.59782
ns
TCCJ
CPUT/C Cycle to Cycle Jitter
Measured at 0V differential
–
85
ps
TCCJ2
CPU2_ITP Cycle to Cycle Jitter
Measured at 0V differential
–
125
ps
LACC
Long-term Accuracy
Measured at 0V differential
–
100
ppm
TSKEW2
CPU2_ITP to CPU0 Clock Skew
Measured at 0V differential
–
150
ps
TR/TF
CPUT and CPUC Rise and Fall Time
Measured differentially from ±150 mV
2.5
8
V/ns
....................Document #: 001-03543 Rev *E Page 19 of 24
CY505YC64D
AC Electrical Specifications (continued)
Parameter
Description
Condition
Min.
Max.
Unit
Measured single-endedly from ±75 mV
–
20
%
1.15
V
TRFM
Rise/Fall Matching
VHIGH
Voltage High
VLOW
Voltage Low
–0.3
–
V
VOX
Crossing Point Voltage at 0.7V Swing
245
550
mV
45
55
%
SRC
TDC
SRCT and SRCC Duty Cycle
Measured at 0V differential
TPERIOD
100 MHz SRCT and SRCC Period
Measured at 0V differential @ 0.1s
9.99900
10.0010
ns
TPERIODSS
100 MHz SRCT and SRCC Period, SSC
Measured at 0V differential @ 0.1s
9.99900
10.0010
ns
TPERIODAbs
100 MHz SRCT and SRCC Absolute Period
Measured at 0V differential @ 1 clock
9.87400
10.1260
ns
TPERIODSSAbs 100 MHz SRCT and SRCC Absolute Period,
SSC
Measured at 0V differential @ 1 clock
9.87400
10.1763
ns
TSKEW(window) Any SRCT/C to SRCT/C Clock Skew from the
Measured at 0V differential
–
3.0
ns
earliest bank to the latest bank
TCCJ
SRCT/C Cycle to Cycle Jitter
Measured at 0V differential
–
125
ps
LACC
SRCT/C Long Term Accuracy
Measured at 0V differential
–
100
ppm
TR/TF
SRCT and SRCC Rise and Fall Time
Measured differentially from ±150 mV
2.5
8
V/ns
TRFM
Rise/Fall Matching
Measured single-endedly from ±75 mV
–
20
%
VHIGH
Voltage High
1.15
V
VLOW
Voltage Low
–0.3
–
V
VOX
Crossing Point Voltage at 0.7V Swing
250
550
mV
DOT
TDC
DOT96T and DOT96C Duty Cycle
Measured at 0V differential
45
55
%
TPERIOD
DOT96T and DOT96C Period
Measured at 0V differential @ 0.1s
10.4156
10.4177
ns
TPERIODAbs
DOT96T and DOT96C Absolute Period
Measured at 0V differential @ 0.1s
10.1656
10.6677
ns
TCCJ
DOT96T/C Cycle to Cycle Jitter
Measured at 0V differential @ 1 clock
–
250
ps
LACC
DOT96T/C Long Term Accuracy
Measured at 0V differential @ 1 clock
–
300
ppm
TR/TF
DOT96T and DOT96C Rise and Fall Time
Measured differentially from ±150 mV
2.5
8
V/ns
TRFM
Rise/Fall Matching
Measured single-endedly from ±75 mV
–
20
%
VHIGH
Voltage High
1.15
V
VLOW
Voltage Low
–0.3
–
V
VOX
Crossing Point Voltage at 0.7V Swing
300
550
mV
45
55
%
LCD_100_SSC
TDC
SSCT and SSCC Duty Cycle
Measured at 0V differential
TPERIOD
100 MHz SSCT and SSCC Period
Measured at 0V differential @ 0.1s
9.99900
10.0010
ns
TPERIODSS
100 MHz SSCT and SSCC Period, SSC
Measured at 0V differential @ 0.1s
9.99900
10.0010
ns
TPERIODAbs
100 MHz SSCT and SSCC Absolute Period
Measured at 0V differential @ 1 clock
9.87400
10.1260
ns
TPERIODSSAbs 100 MHz SRCT and SRCC Absolute Period, Measured at 0V differential @ 1 clock
9.87400
10.1763
ns
–
250
ps
SSC
TCCJ
SSCT/C Cycle to Cycle Jitter
Measured at 0V differential
LACC
SSCT/C Long Term Accuracy
Measured at 0V differential
–
300
ppm
TR/TF
SSCT and SSCC Rise and Fall Time
Measured differentially from ±150 mV
2.5
8
V/ns
TRFM
Rise/Fall Matching
Measured single-endedly from ±75 mV
–
20
%
VHIGH
Voltage High
1.15
V
VLOW
Voltage Low
–0.3
–
V
VOX
Crossing Point Voltage at 0.7V Swing
300
550
mV
....................Document #: 001-03543 Rev *E Page 20 of 24
CY505YC64D
AC Electrical Specifications (continued)
Parameter
Description
Condition
Min.
Max.
Unit
45
55
%
PCI/PCIF
TDC
PCI Duty Cycle
Measurement at 1.5V
TPERIOD
Spread Disabled PCIF/PCI Period
Measurement at 1.5V
29.99100 30.00900
ns
TPERIODSS
Spread Enabled PCIF/PCI Period, SSC
Measurement at 1.5V
29.99100 30.15980
ns
TPERIODAbs
Spread Disabled PCIF/PCI Period
Measurement at 1.5V
29.49100 30.50900
ns
TPERIODSSAbs Spread Enabled PCIF/PCI Period, SSC
Measurement at 1.5V
29.49100 30.65980
ns
THIGH
PCIF and PCI high time
Measurement at 2.4V
12.0
–
ns
TLOW
PCIF and PCI low time
Measurement at 0.4V
12.0
–
ns
TR/TF
PCIF/PCI rising and falling Edge Rate
Measured between 0.8V and 2.0V
1.0
4.0
V/ns
TSKEW
Any PCI clock to Any PCI clock Skew
Measurement at 1.5V
–
1000
ps
TCCJ
PCIF and PCI Cycle to Cycle Jitter
Measurement at 1.5V
–
500
ps
LACC
PCIF/PCI Long Term Accuracy
Measurement at 1.5V
–
300
ppm
TDC
Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
Period
Measurement at 1.5V
20.83125 20.83542
ns
TPERIODAbs
Absolute Period
Measurement at 1.5V
20.48125 21.18542
ns
THIGH
48_M High time
Measurement at 2.4V
8.094
10.036
ns
TLOW
48_M Low time
Measurement at 0.4V
7.694
9.836
ns
TR/TF
Rising and Falling Edge Rate
Measured between 0.8V and 2.0V
1.0
5.0
V/ns
TCCJ
Cycle to Cycle Jitter
Measurement at 1.5V
–
350
ps
LACC
48M Long Term Accuracy
Measurement at 1.5V
–
300
ppm
TDC
Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
Period
Measurement at 1.5V
39.996
40.004
ns
THIGH
25_M High time
Measurement at 2V
12
ns
TLOW
25_M Low time
Measurement at 0.8V
12
ns
TR/TF
Rising and Falling Edge Rate
Measured between 0.8V and 2.0V
1.0
4.0
V/ns
TCCJ
Cycle to Cycle Jitter
Measurement at 1.5V
–
500
ps
LACC
25M Long Term Accuracy
Measurement at 1.5V
–
50
ppm
Measurement at 1.5V @ 10 s
–
500
ppm
45
55
%
48_M
25_M
TLTJ @ 10 s 25M Long Term Jitter @ 10 s
REF
TDC
REF Duty Cycle
Measurement at 1.5V
TPERIOD
REF Period
Measurement at 1.5V
69.82033 69.86224
ns
TPERIODAbs
REF Absolute Period
Measurement at 1.5V
68.82033 70.86224
ns
TR/TF
REF Rising and Falling Edge Rate
Measured between 0.8V and 2.0V
1.0
5.0
V/ns
TSKEW
REF Clock to REF Clock
Measurement at 1.5V
–
500
ps
TCCJ
REF Cycle to Cycle Jitter
Measurement at 1.5V
–
1000
ps
LACC
Long Term Accuracy
Measurement at 1.5V
–
300
ppm
–
1.8
ms
10.0
–
ns
ENABLE/DISABLE and SET-UP
TSTABLE
Clock Stabilization from Power-up
TSS
Stopclock Set-up Time
....................Document #: 001-03543 Rev *E Page 21 of 24
CY505YC64D
Test and Measurement Set-up
For PCI Single-ended Signals and Reference
The following diagram shows the test load configurations for the single-ended PCI, USB, and REF output signals.
L1
22
50
PCI/USB
Measurement
Point
L2
L1 = 0.5", L2 = 8"
4 pF
Measurement
Point
50
L1
22
L2
4 pF
Figure 9. Single-ended PCI and USB Double Load Configuration
L1
15
L2
50
REF
L1
L1
15
15
L2
50
L2
50
Measurement
Point
4 pF
Measurement
Point
4 pF
Measurement
Point
4 pF
Figure 10. Single-ended REF Triple Load Configuration
Figure 11. Single-ended Output Signals (for AC Parameters Measurement)
....................Document #: 001-03543 Rev *E Page 22 of 24
CY505YC64D
For CPU, SRC, and DOT96 Signals and Reference
The following diagram shows the test load configuration for the differential CPU and SRC outputs.
OUT+
L1
33
L2
50
Measurement
Point
2 pF
L1 = 0.5", L2 = 7"
OUT-
L1
33
L2
50
Measurement
Point
2 pF
Figure 12. 0.7V Differential Load Configuration
Figure 13. Differential Measurement for Differential Output Signals (for AC Parameters Measuremement
Figure 14. Single-ended Measurement for Differential Output Signals (for AC Parameters Measurement)
....................Document #: 001-03543 Rev *E Page 23 of 24
CY505YC64
Ordering Information
Part Number
Package Type
Product Flow
Lead-free
CY505YC64DT
64-pin TSSOP
Commercial, 0 to 85C
CY505YC64DTT
64-pin TSSOP–Tape and Reel
Commercial, 0 to 85C
Package Diagram
64-Lead Thin Shrunk Small Outline Package (6 mm x 17 mm) Z64
32
1
DIMENSIONS IN MM MIN.
MAX.
REFERENCE JEDEC MO-153
8.00[0.315]
8.20[0.322]
PART #
6.00[0.236]
6.20[0.244]
STANDARD PKG.
ZZ6424
LEAD FREE PKG.
64
33
16.90[0.665]
17.10[0.673]
1.10[0.043]
MAX.
GAUGE PLANE
0.25[0.010]
0.20[0.008]
0.85[0.033]
0.95[0.037]
Z6424
0.50[0.020]
BSC
0.17[0.006]
0.27[0.010]
0.05[0.002]
0.15[0.006]
0°-8°
SEATING
PLANE
0.50[0.020]
0.75[0.027]
0.10[0.004]
0.20[0.008]
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the
use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or
parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
....................Document #: 001-03543 Rev *E Page 24 of 24
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