CYW150
440BX AGPset Spread Spectrum Frequency Synthesizer
Features
Table 1. Mode Input Table
Mode
0
1
• Maximized electromagnetic interference (EMI)
suppression using Cypress’s Spread Spectrum
technology
• Single-chip system frequency synthesizer for Intel®
440BX AGPset
• Three copies of CPU output
Table 2. Pin Selectable Frequency
VDDQ3: ..................................................................... 3.3V±5%
FS3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
VDDQ2: ..................................................................... 2.5V±5%
0
• Seven copies of PCI output
• One 48 MHz output for USB/one 24 MHz for SIO
• Two buffered reference outputs
• Two IOAPIC outputs
• 17 SDRAM outputs provide support for four DIMMs
• Supports frequencies up to 150 MHz
• SMBus interface for programming
• Power management control inputs
Key Specifications
CPU Cycle-to-Cycle Jitter: .......................................... 250 ps
CPU to CPU Output Skew: ......................................... 175 ps
PCI to PCI Output Skew:............................................. 500 ps
SDRAMIN to SDRAM0:15 Delay:.......................... 3.7 ns typ.
Pin 3
PCI_STOP#
REF0
Input Address
FS2 FS1 FS0
1
1
1
1
1
0
1
0
1
1
0
0
0
1
1
0
1
0
0
0
1
0
0
0
1
1
1
1
1
0
1
0
1
1
0
0
0
1
1
0
1
0
0
0
1
0
0
CPU_F, 1:2
(MHz)
133.3
124
150
140
105
110
115
120
100
133.3
112
103
66.8
83.3
75
PCI_F, 0:5
(MHz)
33.3 (CPU/4)
31 (CPU/4)
37.5 (CPU/4)
35 (CPU/4)
35 (CPU/3)
36.7 (CPU/3)
38.3 (CPU/3)
40 (CPU/3)
33.3 (CPU/3)
44.43 (CPU/3)
37.3 (CPU/3)
34.3 (CPU/3)
33.4 (CPU/2)
41.7 (CPU/2)
37.5 (CPU/2)
124
41.3 (CPU/3)
0
SDRAM0:15 (leads) to SDRAM_F Skew: ............. 0.4 ns typ.
Logic Block Diagram
Pin Configuration[1]
VDDQ3
REF0/(PCI_STOP#)
X1
X2
REF1/FS2
XTAL
OSC
PLL Ref Freq
Stop
Clock
Control
I/O Pin
Control
IOAPIC0
VDDQ2
CPU_F
Stop
Clock
Control
PLL 1
÷2,3,4
CPU1
CPU2
VDDQ3
PCI_F/MODE
PCI0/FS3
Stop
Clock
Control
PCI1
PCI2
PCI3
SDATA
SCLK
SMBus
Logic
PCI4
PCI5
VDDQ3
48MHz/FS1
PLL2
SDRAMIN
Stop
Clock
Control
24MHz/FS0
VDDQ3
SDRAM0:15
16 SDRAM_F
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
CYW150
CLK_STOP#
VDDQ2
IOAPIC_F
VDDQ3
REF1/FS2
REF0/(PCI_STOP#)
GND
X1
X2
VDDQ3
PCI_F/MODE
PCI0/FS3
GND
PCI1
PCI2
PCI3
PCI4
VDDQ3
PCI5
SDRAMIN
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
GND
SDRAM15
SDRAM14
GND
SDATA
SCLK
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDQ2
IOAPIC0
IOAPIC_F
GND
CPU_F
CPU1
VDDQ2
CPU2
GND
CLK_STOP#
SDRAM_F
VDDQ3
SDRAM0
SDRAM1
GND
SDRAM2
SDRAM3
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
GND
SDRAM12
SDRAM13
VDDQ3
24MHz/FS0
48MHz/FS1
Note:
1. 1.Internal pull-up resistors should not be relied upon for setting I/O pins HIGH. Pin function
with parentheses determined by MODE pin resistor strapping. Unlike other I/O pins, input
FS3 has an internal pull-down resistor.
........................ Document #: 38-07177 Rev. *B Page 1 of 14
400 West Cesar Chavez, Austin, TX 78701
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1+(512) 416-9669
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CYW150
Pin Definitions
Pin
Type
Pin Description
O CPU Outputs 1 and 2: Frequency is set by the FS0:3 inputs or through serial input interface,
see Table 2 and Table 6. These outputs are affected by the CLK_STOP# input.
CPU_F
52
O Free-Running CPU Output: Frequency is set by the FS0:3 inputs or through serial input
interface, see Table 2 and Table 6. This output is not affected by the CLK_STOP# input.
PCI1:5
11, 12, 13,
O PCI Outputs 1 through 5: Frequency is set by the FS0:3 inputs or through serial input
14, 16
interface, see Table 2 and Table 6. These outputs are affected by the PCI_STOP# input.
PCI0/FS3
9
I/O PCI Output/Frequency Select Input: As an output, frequency is set by the FS0:3 inputs or
through serial input interface, see Table 2 and Table 6. This output is affected by the
PCI_STOP# input. When an input, latches data selecting the frequency of the CPU and PCI outputs.
PCI_F/MODE
8
I/O Free Running PCI Output: Frequency is set by the FS0:3 inputs or through serial input
interface, see Table 2 and Table 6. This output is not affected by the PCI_STOP# input. When
an input, selects function of pin 3 as described in Table 1.
CLK_STOP#
47
I
CLK_STOP# Input: When brought LOW, affected outputs are stopped LOW after completing
a full clock cycle (2–3 CPU clock latency). When brought HIGH, affected outputs start
beginning with a full clock cycle (2–3 CPU clock latency).
IOAPIC_F
54
O Free-running IOAPIC Output: This output is a buffered version of the reference input which
is not affected by the CPU_STOP# logic input. Its swing is set by voltage applied to VDDQ2.
IOAPIC0
55
O IOAPIC Output: Provides 14.318 MHz fixed frequency. The output voltage swing is set by
voltage applied to VDDQ2. This output is disabled when CLK_STOP# is set LOW.
48MHz/FS1
29
I/O 48 MHz Output: 48 MHz is provided in normal operation. In standard systems, this output can
be used as the reference for the Universal Serial Bus. Upon power up, FS1 input will be
latched, setting output frequencies as described in Table 2.
24MHz/FS0
30
I/O 24 MHz Output: 24 MHz is provided in normal operation. In standard systems, this output can
be used as the clock input for a Super I/O chip. Upon power up, FS0 input will be latched,
setting output frequencies as described in Table 2.
REF1/FS2
2
I/O Reference Output: 14.318 MHz is provided in normal operation. Upon power-up, FS2 input
will be latched, setting output frequencies as described in Table 2.
REF0
3
I/O Fixed 14.318 MHz Output 0 or PCI_STOP# Pin: Function determined by MODE pin. The
(PCI_STOP#)
PCI_STOP# input enables the PCI 0:5 outputs when HIGH and causes them to remain at logic
0 when LOW. The PCI_STOP signal is latched on the rising edge of PCI_F. Its effects take
place on the next PCI_F clock cycle. As an output, this pin provides a fixed clock signal equal
in frequency to the reference signal provided at the X1/X2 pins (14.318 MHz).
SDRAMIN
17
I
Buffered Input Pin: The signal provided to this input pin is buffered to 17 outputs
(SDRAM0:15, SDRAM_F).
SDRAM0:15
44, 43,
O Buffered Outputs: These sixteen dedicated outputs provide copies of the signal provided at
41, 40,
the SDRAMIN input. The swing is set by VDDQ3, and they are deactivated when CLK_STOP#
39, 38,
input is set LOW.
36, 35,
22, 21,
19, 18,
33, 32,
25, 24
SDRAM_F
46
O Free-Running Buffered Output: This output provides a single copy of the SDRAMIN input.
The swing is set by VDDQ3; this signal is unaffected by the CLK_STOP# input.
SCLK
28
I
Clock pin for SMBus circuitry.
SDATA
27
I/O Data pin for SMBus circuitry.
X1
5
I
Crystal Connection or External Reference Frequency Input: This pin has dual functions.
It can be used as an external 14.318 MHz crystal connection or as an external reference
frequency input.
X2
6
I
Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an
external reference, this pin must be left unconnected.
VDDQ3
1, 7, 15,
P Power Connection: Power supply for core logic, PLL circuitry, SDRAM output buffers, PCI
20, 31,
output buffers, reference output buffers, and 48 MHz/24 MHz output buffers. Connect to 3.3V.
37, 45
Pin Name
CPU1:2
Pin No.
51, 49
........................ Document #: 38-07177 Rev. *B Page 2 of 14
CYW150
Pin Definitions (continued)
Pin Name
VDDQ2
GND
Pin
Type
Pin Description
P Power Connection: Power supply for IOAPIC and CPU output buffers. Connect to 2.5V or
3.3V.
4, 10, 23,
G Ground Connections: Connect all ground pins to the common system ground plane.
26, 34,
42, 48, 53
Pin No.
50, 56
Overview
The CYW150 was designed as a single-chip alternative to the
standard two-chip Intel 440BX AGPset clock solution. It
provides sufficient outputs to support most single-processor,
four SDRAM DIMM designs.
Functional Description
I/O Pin Operation
Pins 2, 8, 9, 29, and 30 are dual-purpose l/O pins. Upon
power-up these pins act as logic inputs, allowing the determination of assigned device functions. A short time after
power-up, the logic state of each pin is latched and the pins
become clock outputs. This feature reduces device pin count
by combining clock outputs with input select pins.
An external 10-k “strapping” resistor is connected between
the l/O pin and ground or VDD. Connection to ground sets a
latch to “0,” connection to VDD sets a latch to “1.” Figure 1 and
Figure 2 show two suggested methods for strapping resistor
connections.
Upon CYW150 power-up, the first 2 ms of operation are used
for input logic selection. During this period, the five I/O pins (2,
8, 9, 29, 30) are three-stated, allowing the output strapping
resistor on the l/O pins to pull the pins and their associated
capacitive clock load to either a logic HIGH or LOW state. At
the end of the 2-ms period, the established logic “0” or “1”
condition of the l/O pin is latched. Next the output buffer is
enabled, converting the l/O pins into operating clock outputs.
The 2-ms timer starts when VDD reaches 2.0V. The input bits
can only be reset by turning VDD off and then back on again.
It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive
impedance of clock output (< 40, nominal) is minimally
affected by the 10-k strap to ground or VDD. As with the
series termination resistor, the output strapping resistor should
be placed as close to the l/O pin as possible in order to keep
the interconnecting trace short. The trace from the resistor to
ground or VDD should be kept less than two inches in length
to minimize system noise coupling during input logic sampling.
When the clock outputs are enabled following the 2-ms input
period, the corresponding specified output frequency is
delivered on the pins, assuming that VDD has stabilized. If VDD
has not yet reached full value, output frequency initially may
be below target but will increase to target once VDD voltage
has stabilized. In either case, a short output clock cycle may
be produced from the CPU clock outputs when the outputs are
enabled.
VDD
10 k
(Load Option 1)
CYW150
Power-on
Reset
Timer
Output Strapping Resistor
Series Termination Resistor
Clock Load
Output
Buffer
Hold
Output
Low
Output Three-state
Q
10 k
(Load Option 0)
D
Data
Latch
Figure 1. Input Logic Selection Through Resistor Load Option
........................ Document #: 38-07177 Rev. *B Page 3 of 14
CYW150
Jumper Options
Output Strapping Resistor
VDD
10 k
CYW150
Power-on
Reset
Timer
Series Termination Resistor
Q
Resistor Value R
Hold
Output
Low
Output Three-state
Clock Load
R
Output
Buffer
D
Data
Latch
Figure 2. Input Logic Selection Through Jumper Option
Spread Spectrum Generator
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced.
This effect is depicted in Figure 3.
The output clock is modulated with a waveform depicted in
Figure 4. This waveform, as discussed in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions” by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is specified in Table 6. Figure 4
details the Cypress spreading pattern. Cypress does offer
options with more spread and greater EMI reduction. Contact
your local Sales representative for details on these devices.
As shown in Figure 3, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is
dB = 6.5 + 9*log10(P) + 9*log10(F)
Spread Spectrum clocking is activated or deactivated by
selecting the appropriate values for bits 1–0 in data byte 0 of
the SMBus data stream. Refer to Table 7 for more details.
5 dB/div
Typical Clock
Amplitude (dB)
SSFTG
–1.0
–0.5%
–SS%
0
Frequency Span (MHz)
+0.5%
+SS%
+1.0
Figure 3. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
........................ Document #: 38-07177 Rev. *B Page 4 of 14
CYW150
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
FREQUENCY
MAX
MIN
Figure 4. Typical Modulation Profile
Serial Data Interface
The CYW150 features a two-pin, serial data interface that can
be used to configure internal register settings that control
particular device functions. Upon power-up, the CYW150
initializes with default register settings, therefore the use of this
serial data interface is optional. The serial interface is
write-only (to the clock chip) and is the dedicated function of
device pins SDATA and SCLOCK. In motherboard applications, SDATA and SCLOCK are typically driven by two logic
outputs of the chipset. If needed, clock device register
changes are normally made upon system initialization. The
interface can also be used during system operation for power
management functions. Table 3 summarizes the control
functions of the serial data interface.
Operation
Data is written to the CYW150 in eleven bytes of eight bits
each. Bytes are written in the order shown in Table 4.
Table 3. Serial Data Interface Control Functions Summary
Control Function
Description
Common Application
Clock Output Disable Any individual clock output(s) can be disabled.
Disabled outputs are actively held LOW.
Unused outputs are disabled to reduce EMI and
system power. Examples are clock outputs to
unused PCI slots.
CPU Clock
Provides CPU/PCI frequency selections through
Frequency Selection software. Frequency is changed in a smooth and
controlled fashion.
For alternate microprocessors and power
management options. Smooth frequency transition
allows CPU frequency change under normal system
operation.
Spread Spectrum
Enabling
Enables or disables spread spectrum clocking.
For EMI reduction.
Output Three-state
Puts clock output into a high-impedance state.
Production PCB testing.
Test Mode
All clock outputs toggle in relation to X1 input,
internal PLL is bypassed. Refer to Table 5.
Production PCB testing.
(Reserved)
Reserved function for future device revision or
production device testing.
No user application. Register bit must be written as
0.
Table 4. Byte Writing Sequence
Byte
Sequence
Byte Name
Bit Sequence
Byte Description
1
Slave Address 11010010
Commands the CYW150 to accept the bits in Data Bytes 0–7 for internal register
configuration. Since other devices may exist on the same common serial data bus,
it is necessary to have a specific slave address for each potential receiver. The
slave receiver address for the CYW150 is 11010010. Register setting will not be
made if the Slave Address is not correct (or is for an alternate slave receiver).
2
Command
Code
Don’t Care
Unused by the CYW150, therefore bit values are ignored (“Don’t Care”). This byte
must be included in the data write sequence to maintain proper byte allocation. The
Command Code Byte is part of the standard serial communication protocol and
may be used when writing to another addressed slave receiver on the serial data
bus.
3
Byte Count
Don’t Care
Unused by the CYW150, therefore bit values are ignored (“Don’t Care”). This byte
must be included in the data write sequence to maintain proper byte allocation. The
Byte Count Byte is part of the standard serial communication protocol and may be
used when writing to another addressed slave receiver on the serial data bus.
........................ Document #: 38-07177 Rev. *B Page 5 of 14
CYW150
Table 4. Byte Writing Sequence (continued)
Byte
Sequence
Byte Name
4
Data Byte 0
5
Data Byte 1
6
Data Byte 2
7
Data Byte 3
8
Data Byte 4
9
Data Byte 5
10
Data Byte 6
11
Data Byte 7
Bit Sequence
Byte Description
Refer to Table 5 The data bits in Data Bytes 0–5 set internal CYW150 registers that control device
operation. The data bits are only accepted when the Address Byte bit sequence is
11010010, as noted above. For description of bit control functions, refer to Table 5,
Data Byte Serial Configuration Map.
Don’t Care
Unused by the CYW150, therefore bit values are ignored (Don’t Care).
Writing Data Bytes
Each bit in Data Bytes 0–7 control a particular device function
except for the “reserved” bits which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit 7.
Table 5 gives the bit formats for registers located in Data Bytes
0–7.
Table 6 details additional frequency selections that are
available through the serial data interface.
Table 7 details the select functions for Byte 0, bits 1 and 0.
Table 5. Data Bytes 0–5 Serial Configuration Map
Affected Pin
Bit(s)
Pin No.
Bit Control
Pin Name
Control Function
0
1
Default
–
0
Data Byte 0
7
–
–
(Reserved)
6
–
–
SEL_2
See Table 6
0
5
–
–
SEL_1
See Table 6
0
4
–
–
SEL_0
See Table 6
0
3
–
–
Frequency Table Selection
2
–
–
SEL3
1–0
–
–
7
–
–
–
–
–
0
6
–
–
–
–
–
0
5
–
–
–
–
–
0
4
–
–
–
–
–
0
3
46
SDRAM_F
Clock Output Disable
Low
Active
1
2
49
CPU2
Clock Output Disable
Low
Active
1
1
51
CPU1
Clock Output Disable
Low
Active
1
0
52
CPU_F
Clock Output Disable
Low
Active
1
–
–
0
Bit 1
0
0
1
1
–
Frequency
Controlled by FS
(3:0) Table 2
Frequency
Controlled by SEL
(3:0) Table 6
Refer to Table 6
Bit 0
0
1
0
1
0
0
00
Function (See Table 7 for function details)
Normal Operation
(Reserved)
Spread Spectrum On
All Outputs Three-stated
Data Byte 1
Data Byte 2
7
–
–
(Reserved)
6
8
PCI_F
Clock Output Disable
Low
Active
1
5
16
PCI5
Clock Output Disable
Low
Active
1
........................ Document #: 38-07177 Rev. *B Page 6 of 14
CYW150
Table 5. Data Bytes 0–5 Serial Configuration Map (continued)
Affected Pin
Bit Control
Bit(s)
Pin No.
Pin Name
0
1
Default
4
14
PCI4
Clock Output Disable
Control Function
Low
Active
1
3
13
PCI3
Clock Output Disable
Low
Active
1
2
12
PCI2
Clock Output Disable
Low
Active
1
1
11
PCI1
Clock Output Disable
Low
Active
1
0
9
PCI0
Clock Output Disable
Low
Active
1
–
–
–
–
0
Data Byte 3
7
(Reserved)
6
–
–
–
–
0
5
29
48MHz
Clock Output Disable
(Reserved)
Low
Active
1
4
30
24MHz
Clock Output Disable
Low
Active
1
3
33, 32,
25, 24
SDRAM12:15 Clock Output Disable
Low
Active
1
2
22, 21,
19, 18
SDRAM8:11
Clock Output Disable
Low
Active
1
1
39, 38,
36, 35
SDRAM4:7
Clock Output Disable
Low
Active
1
0
44, 43,
41, 40
SDRAM0:3
Clock Output Disable
Low
Active
1
Data Byte 4
7
–
–
(Reserved)
–
–
0
6
–
–
(Reserved)
–
–
0
5
–
–
(Reserved)
–
–
0
4
–
–
(Reserved)
–
–
0
3
–
–
(Reserved)
–
–
0
2
–
–
(Reserved)
–
–
0
1
–
–
(Reserved)
–
–
0
0
–
–
(Reserved)
–
–
0
7
–
–
(Reserved)
–
–
0
6
–
–
(Reserved)
–
–
0
5
54
IOAPIC_F
Disabled
Low
Active
1
4
55
IOAPICO
Disabled
Low
Active
1
3
–
–
(Reserved)
–
–
0
2
–
–
(Reserved)
–
–
0
1
2
REF1
Clock Output Disable
Low
Active
1
0
3
REF0
Clock Output Disable
Low
Active
1
Data Byte 5
........................ Document #: 38-07177 Rev. *B Page 7 of 14
CYW150
Table 6. Frequency Selections through Serial Data Interface Data Bytes
Input Conditions
Output Frequency
Spread On
Data Byte 0, Bit 3 = 1
Bit 2
SEL_3
Bit 6
SEL_2
Bit 5
SEL_1
Bit 4
SEL_0
CPU, SDRAM
Clocks (MHz)
PCI Clocks
(MHz)
Spread Percentage
1
1
1
1
133.3
33.3 (CPU/4)
± 0.5% Center
1
1
1
0
124
31 (CPU/4)
± 0.5% Center
1
1
0
1
150
37.5 (CPU/4)
± 0.5% Center
1
1
0
0
140
35 (CPU/4)
± 0.5% Center
1
0
1
1
105
35 (CPU/3)
± 0.5% Center
1
0
1
0
110
36.7 (CPU/3)
± 0.9% Center
1
0
0
1
115
38.3 (CPU/3)
± 0.5% Center
1
0
0
0
120
40 (CPU/3)
± 0.5% Center
0
1
1
1
100
33.3 (CPU/3)
± 0.5% Center
0
1
1
0
133.3
44.43 (CPU/3)
± 0.5% Center
0
1
0
1
112
37.3 (CPU/3)
± 0.5% Center
0
1
0
0
103
34.3 (CPU/3)
± 0.5% Center
0
0
1
1
66.8
33.4 (CPU/2)
± 0.5% Center
0
0
1
0
83.3
41.7 (CPU/2)
± 0.9% Center
0
0
0
1
75
37.5 (CPU/2)
± 0.5% Center
0
0
0
0
124
41.3 (CPU/3)
± 0.5% Center
Table 7. Select Function for Data Byte 0, Bits 0:1
Input Conditions
Output Conditions
Data Byte 0
Bit 1
Bit 0
CPU_F, 1:2
PCI_F, PCI0:5
REF0:1, IOAPIC0,_F
48 MHZ
24 MHZ
Normal Operation
0
0
Note 2
Note 2
14.318 MHz
48 MHz
24 MHz
Test Mode
0
1
X1/2
CPU/(2 or 3)
X1
X1/2
X1/4
Spread Spectrum
1
0
Note 2
Note 2
14.318 MHz
48 MHz
24 MHz
Tristate
1
1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Function
Note:
2. CPU and PCI frequency selections are listed in Table 2 and Table 6.
........................ Document #: 38-07177 Rev. *B Page 8 of 14
CYW150
Absolute Maximum Ratings[3]
Stresses greater than those listed in this table may cause
permanent damage to the device. These represent a stress
rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this
specification is not implied. Maximum conditions for extended
periods may affect reliability.
Parameter
Description
Rating
Unit
–0.5 to +7.0
V
VDD, VIN
Voltage on any pin with respect to GND
TSTG
Storage Temperature
–65 to +150
°C
TB
Ambient Temperature under Bias
–55 to +125
°C
TA
Operating Temperature
0 to +70
°C
ESDPROT
Input ESD Protection
2 (min)
kV
DC Electrical Characteristics (TA = 0°C to +70°C; VDDQ3 = 3.3V ±5%; VDDQ2 = 2.5V ±5%)
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Supply Current
IDD
3.3V Supply Current
CPU_F, 1:2= 100 MHz
Outputs Loaded[4]
320
mA
IDD
2.5V Supply Current
CPU_F, 1:2= 100 MHz
Outputs Loaded[4]
40
mA
Logic Inputs
VIL
Input Low Voltage
GND – 0.3
0.8
V
2.0
VDD + 0.3
V
–25
A
VIH
Input High Voltage
IIL
Input Low Current[5]
IIH
Input High Current[5]
10
A
IIL
Input Low Current (SEL100/66#)
–5
µA
IIH
Input High Current (SEL100/66#)
+5
µA
50
mV
Clock Outputs
VOL
Output Low Voltage
IOL = 1 mA
VOH
Output High Voltage
IOH = 1 mA
VOH
Output High Voltage
CPU_F, 1:2, IOAPIC IOH = –1 mA
2.2
IOL
Output Low Current
CPU_F, 1:2
VOL = 1.25V
60
73
85
PCI_F, PCI1:5
VOL = 1.5V
IOH
Output High Current
3.1
V
V
mA
96
110
130
mA
IOAPIC0, IOAPIC_F VOL = 1.25V
72
92
110
mA
REF0:1
VOL = 1.5V
61
71
80
mA
48-MHz
VOL = 1.5V
60
70
80
mA
24-MHz
VOL = 1.5V
60
70
80
mA
SDRAM0:15, _F
VOL = 1.5V
95
110
130
CPU_F, 1:2
VOH = 1.25V
43
60
80
mA
PCI_F, PCI1:5
VOH = 1.5V
76
96
120
mA
IOAPIC
VOH = 1.25V
60
90
130
mA
REF0:1
VOH = 1.5V
50
60
72
mA
48-MHz
VOH = 1.5V
50
60
72
mA
24-MHz
VOH = 1.5V
50
60
72
mA
SDRAM0:15, _F
VOH = 1.5V
75
95
120
Notes:
3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
4. All clock outputs loaded with 6" 60 traces with 22-pF capacitors.
5. CYW150 logic inputs have internal pull-up devices (not to full CMOS level). Logic input FS3 has an internal pull-down device.
........................ Document #: 38-07177 Rev. *B Page 9 of 14
CYW150
DC Electrical Characteristics (TA = 0°C to +70°C; VDDQ3 = 3.3V ±5%; VDDQ2 = 2.5V ±5%) (continued)
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Crystal Oscillator
VTH
X1 Input threshold Voltage[6]
CLOAD
Load Capacitance, Imposed on
External Crystal[7]
CIN,X1
X1 Input Capacitance[8]
VDDQ3 = 3.3V
Pin X2 unconnected
1.65
V
14
pF
28
pF
Pin Capacitance/Inductance
CIN
Input Pin Capacitance
COUT
Output Pin Capacitance
6
pF
LIN
Input Pin Inductance
7
nH
Except X1 and X2
5
pF
AC Electrical Characteristics
TA = 0°C to +70°C; VDDQ3 = 3.3V±5%; VDDQ2 = 2.5V±5%; fXTL
= 14.31818 MHz. AC clock parameters are tested and
guaranteed over stated operating conditions using the stated
lump capacitive load at the clock output; Spread Spectrum
clocking is disabled.
CPU Clock Outputs, CPU_F, 1:2 (Lump Capacitance Test Load = 20 pF)
CPU = 66.8 MHz
Parameter
Description
Test Condition/Comments
CPU = 100 MHz
Min. Typ. Max. Min. Typ. Max. Unit
tP
Period
Measured on rising edge at 1.25
15
tH
High Time
Duration of clock cycle above 2.0V
5.2
3.0
ns
tL
Low Time
Duration of clock cycle below 0.4V
5.0
2.8
ns
tR
Output Rise Edge Rate Measured from 0.4V to 2.0V
1
4
1
4
V/ns
tF
Output Fall Edge Rate
Measured from 2.0V to 0.4V
1
4
1
4
V/ns
tD
Duty Cycle
Measured on rising and falling edge at
1.25V
45
55
45
55
%
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.25V.
Maximum difference of cycle time
between two adjacent cycles.
250
250
ps
tSK
Output Skew
Measured on rising edge at 1.25V
175
175
ps
fST
Frequency Stabilization Assumes full supply voltage reached
within 1 ms from power-up. Short cycles
from Power-up (cold
exist prior to frequency stabilization.
start)
3
3
ms
Zo
AC Output Impedance
Average value during switching
transition. Used for determining series
termination value.
15.5
10
20
10.5
ns
20
PCI Clock Outputs, PCI_F and PCI0:5 (Lump Capacitance Test Load = 30 pF)
CPU = 66.6/100 MHz
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
tP
Period
Measured on rising edge at 1.5V
tH
High Time
Duration of clock cycle above 2.4V
12.0
ns
tL
Low Time
Duration of clock cycle below 0.4V
12.0
ns
30
ns
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
1
4
V/ns
Notes:
6. X1 input threshold voltage (typical) is VDDQ3/2.
7. The CYW150 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is
14 pF; this includes typical stray capacitance of short PCB traces to crystal.
8. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
......................Document #: 38-07177 Rev. *B Page 10 of 14
1
4
V/ns
CYW150
PCI Clock Outputs, PCI_F and PCI0:5 (Lump Capacitance Test Load = 30 pF) (continued)
CPU = 66.6/100 MHz
Test Condition/Comments
Min.
tD
Parameter
Duty Cycle
Description
Measured on rising and falling edge at 1.5V
45
tJC
Jitter, Cycle-to-Cycle
tSK
Typ.
Max.
Unit
55
%
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two
adjacent cycles.
250
ps
Output Skew
Measured on rising edge at 1.5V
500
ps
tO
CPU to PCI Clock Skew
Covers all CPU/PCI outputs. Measured on
rising edge at 1.5V. CPU leads PCI output.
4
ns
fST
Frequency Stabilization
Assumes full supply voltage reached within
from Power-up (cold start) 1 ms from power-up. Short cycles exist prior
to frequency stabilization.
3
ms
Zo
AC Output Impedance
1.5
15
Average value during switching transition.
Used for determining series termination
value.
IOAPIC0 and IOAPIC_F Clock Outputs (Lump Capacitance Test Load = 20 pF)
CPU = 66.6/100 MHz
Parameter
Description
Test Condition/Comments
Min.
f
Frequency, Actual
Frequency generated by crystal oscillator
tR
Output Rise Edge Rate
Measured from 0.4V to 2.0V
tF
Output Fall Edge Rate
Measured from 2.0V to 0.4V
tD
Duty Cycle
Measured on rising and falling edge at 1.25V
fST
Frequency Stabilization
Assumes full supply voltage reached within
from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
Typ.
Max.
Unit
14.31818
MHz
1
4
V/ns
1
4
V/ns
45
55
%
1.5
ms
Average value during switching transition.
Used for determining series termination value.
15
REF0:1 Clock Outputs (Lump Capacitance Test Load = 20 pF)
CPU = 66.6/100 MHz
Parameter
Description
Test Condition/Comments
Min.
f
Frequency, Actual
Frequency generated by crystal oscillator
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
fST
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached within 1 ms from
power-up. Short cycles exist prior to frequency stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used for
determining series termination value.
Typ.
Max.
14.318
Unit
MHz
2
V/ns
0.5
2
V/ns
45
55
%
3
ms
25
SDRAM 0:15, _F Clock Outputs (Lump Capacitance Test Load = 30 pF)
CPU = 66.8 MHz
Parameter
t
Description
Test Condition/Comments
CPU = 100 MHz
Min. Typ. Max. Min. Typ.
Unit
ns
15
tH
High Time
Duration of clock cycle above 2.4V
5.2
3.0
ns
tL
Low Time
Duration of clock cycle below 0.4V
5.0
2.0
ns
tR
Output Rise Edge Rate Measured from 0.4V to 2.4V
1
4
1
4
V/ns
tF
Output Fall Edge Rate
1
4
1
4
V/ns
Measured from 2.4V to 0.4V
...................... Document #: 38-07177 Rev. *B Page 11 of 14
10
10.5
Measured on rising edge at 1.5V
P
15.5
Max.
Period
CYW150
SDRAM 0:15, _F Clock Outputs (Lump Capacitance Test Load = 30 pF) (continued)
CPU = 66.8 MHz
Parameter
Description
Test Condition/Comments
CPU = 100 MHz
Min. Typ. Max. Min. Typ.
45
55
45
Max.
Unit
55
%
250
ps
tD
Duty Cycle
Measured on rising and falling edge at
1.5V
tSK
Output Skew
Measured on rising and falling edge at
1.5V
tPD
Propagation Delay
Measured from SDRAMIN
3.7
3.7
ns
Zo
AC Output Impedance
Average value during switching
transition. Used for determining series
termination value.
15
15
250
48-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
CPU = 66.8/100 MHz
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
f
Frequency, Actual
Determined by PLL divider ratio (see m/n below)
48.008
MHz
fD
Deviation from 48 MHz
m/n
PLL Ratio
(48.008 – 48)/48
+167
ppm
(14.31818 MHz x 57/17 = 48.008 MHz)
57/17
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
2
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
0.5
2
V/ns
45
55
%
3
ms
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
fST
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached within 1 ms from
power-up. Short cycles exist prior to frequency stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used for determining series termination value.
25
24-MHz Clock Output (Lump Capacitance Test Load = 20 pF
CPU = 66.8/100 MHz
Parameter
Description
f
Frequency, Actual
Test Condition/Comments
Min.
Determined by PLL divider ratio (see m/n below)
Typ.
Max.
Unit
24.004
MHz
ppm
fD
Deviation from 24 MHz (24.004 – 24)/24
+167
m/n
PLL Ratio
57/34
tR
Output Rise Edge Rate Measured from 0.4V to 2.4V
0.5
2
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
0.5
2
V/ns
Measured on rising and falling edge at 1.5V
45
55
%
3
ms
(14.31818 MHz x 57/34 = 24.004 MHz)
tD
Duty Cycle
fST
Frequency Stabilization Assumes full supply voltage reached within 1 ms from
from Power-up (cold
power-up. Short cycles exist prior to frequency stabilistart)
zation.
Zo
AC Output Impedance
Average value during switching transition. Used for
determining series termination value.
Layout Example
......................Document #: 38-07177 Rev. *B Page 12 of 14
25
CYW150
+2.5V Supply
+3.3V Supply
FB
FB
VDDQ2
VDDQ3
0.005 mF 10 mF
C4
G
G
G
G
1
2
3
4
5
6
7
8
9
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
V
V
G
G
G
G
G
G
V
V
G
G
G
G
G
V
G
G
V
G
G
V
G
G
CYW150
G
10 mF
G
G
V
G
G
G
G
V
G
G
0.005 mf
C2
G
G
10
G
C1
C3
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
G
G
G
G
G
G
FB = Dale ILB1206 - 300 (300@ 100 MHz)
Cermaic Caps C1 & C3 = 10 – 22 µF C2 & C4 = 0.005 µF
G = VIA to GND plane layer
V =VIA to respective supply plane layer
Note: Each supply plane or strip should have a ferrite bead and capacitors
All bypass caps = 0.1F ceramic
......................Document #: 38-07177 Rev. *B Page 13 of 14
CYW150
Ordering Information
Ordering Code
Package Type
Industrial Product Flow
CYW150OXC
56-pin SSOP
Commercial, 0 to 70°C
CYW150OXCT
56-pin SSOP – Tape and Reel
Commercial, 0 to 70°C
Package Drawing and Dimensions
56-Lead Shrunk Small Outline Package O56
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the
use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or
parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
......................Document #: 38-07177 Rev. *B Page 14 of 14
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