CYW320OXC-3

W320-03 200 MHz Spread Spectrum Clock Synthesizer/Driver with Differential CPU Outputs Features Benefits • Compliant with Intel® CK-Titan Clock Synthesizer/Driver Specifications • Supports next-generation Pentium® processors using differential clock drivers • Multiple output clocks at different frequencies • Motherboard clock generator • Three pairs of differential CPU outputs, up to 200 MHz • Support Multiple CPUs and a chipset • Ten synchronous PCI clocks, three free-running • Support for PCI slots and chipset • Six 3V66 clocks • Supports AGP, DRCG reference and Hub Link • Two 48 MHz clocks • Supports USB host controller and graphic controller • One reference clock at 14.318 MHz • Supports ISA slots and I/O chip • One VCH clock • Enables reduction of electromagnetic interference (EMI) and overall system cost • Spread Spectrum clocking (down spread) • Power-down features (PCI_STOP#, CPU_STOP# PWR_DWN#) • Enables ACPI-compliant designs • Three Select inputs (Mode select & IC Frequency Select) • Enables ATE and “bed of nails” testing • Supports up to four CPU clock frequencies • Widely available, standard package enables lower cost • OE and Test Mode support • 56-pin SSOP package and 56-pin TSSOP package Logic Block Diagram Pin Configurations SSOP & TSSOP Top View XTAL OSC X1 X2 VDD_REF PWR 1 56 REF XTAL_IN 2 55 S1 XTAL_OUT 3 54 S0 GND_REF 4 53 CPU_STOP# PCI_F0 5 52 CPU0 PCI_F1 6 51 CPU#0 PCI_F2 7 50 VDD_CPU VDD_PCI 8 49 CPU1 GND_PCI 9 48 CPU#1 PCI0 10 47 GND_CPU VDD_PCI PCI_F0:2 PCI1 11 46 VDD_CPU PCI2 45 CPU2 PCI0:6 PCI3 12 13 44 CPU#2 VDD_PCI 14 43 MULT0 GND_PCI PCI4 15 42 IREF 16 41 PCI5 PCI6 VDD_3V66 17 40 GND_IREF S2 18 39 19 38 PLL Ref Freq PLL 1 S0:2 PWR_GD# CPU_STOP# Divider Network PWR Gate Stop Clock Control VDD_CPU CPU0:2 CPU#0:2 PWR Stop Clock Control PCI_STOP# /2 PWR_DWN# VDD_3V66 PWR 3V66_0 PWR 3V66_2:4/ 66BUFF0:2 PWR GND_3V66 20 37 66BUFF0/3V66_2 21 36 GND_ 48 MHz VDD_48MHz 66BUFF1/3V66_3 22 35 USB (48MHz) 66BUFF2/3V66_4 66IN/3V66_5 23 34 3V66_1/VCH PCI_STOP# 24 25 33 3V66_0 32 VDD_3V66 26 31 GND_3V66 27 30 28 29 SCLK SDATA DOT (48MHz) VCH_CLK/ 3V66_1 PWR_DWN# VDD_CORE GND_CORE PWR_GD# SDATA SCLK USB DOT VDD_ 48 MHz 3V66_5/ 66IN PLL 2 W320-03 VDD_REF REF SMBus Logic ........................ Document #: 38-07248 Rev. *C Page 1 of 16 400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com W320-03 Pin Summary Name Pins Description REF 56 3.3V 14.318 MHz clock output XTAL_IN 2 14.318 MHz crystal input XTAL_OUT 3 14.318 MHz crystal input CPU, CPU# [0:2] 44, 45, 48, 49, 51, Differential CPU clock outputs 52 3V66_0 33 3.3V 66 MHz clock output 3V66_1/VCH 35 3.3V selectable through SMBus to be 66 MHz or 48 MHz 66IN/3V66_5 24 66 MHz input to buffered 66BUFF and PCI or 66 MHz clock from internal VCO 66BUFF [2:0] /3V66 [4:2] 21, 22, 23 66 MHz buffered outputs from 66Input or 66 MHz clocks from internal VCO PCI_F [0:2] 5, 6, 7, 33 MHz clocks divided down from 66Input or divided down from 3V66 PCI [0:6] 10, 11, 12, 13, 16, PCI clock outputs divided down from 66Input or divided down from 3V66 17, 18 USB 39 Fixed 48 MHz clock output DOT 38 Fixed 48 MHz clock output S2 40 Special 3.3V 3 level input for Mode selection S1, S0 54, 55 3.3V LVTTL inputs for CPU frequency selection IREF 42 A precision resistor is attached to this pin which is connected to the internal current reference MULT0 43 3.3V LVTTL input for selecting the current multiplier for the CPU outputs PWR_DWN# 25 3.3V LVTTL input for Power_Down# (active LOW) PCI_STOP# 34 3.3V LVTTL input for PCI_STOP# (active LOW) CPU_STOP# 53 3.3V LVTTL input for CPU_STOP# (active LOW) PWRGD# 28 3.3V LVTTL input is a level sensitive strobe used to determine when S[2:0] and MULTI0 inputs are valid and OK to be sampled (Active LOW). Once PWRGD# is sampled LOW, the status of this output will be ignored. SDATA 29 SMBus compatible SDATA SCLK 30 SMBus compatible Sclk VDD_REF, VDD_PCI, 1, 8, 14, 19, 32, 46, 3.3V power supply for outputs VDD_3V66, 50 VDD_CPU VDD_48 MHz 37 3.3V power supply for 48 MHz VDD_CORE 26 3.3V power supply for PLL GND_REF, GND_PCI, 4, 9, 15, 20, 31, 36, Ground for outputs GND_3V66, 41, 47 GND_IREF, VDD_CPU GND_CORE 27 Ground for PLL ........................Document #: 38-07248 Rev. *C Page 2 of 16 W320-03 Function Table S2 S1 [1] CPU (MHz) S0 3V66[0:1] 66BUFF[0:2]/3 66IN/3V66_5 (MHz) V66[2:4] (MHz) (MHz) PCI_F/PCI (MHz) REF0(MHz) USB/DOT (MHz) Notes 1 0 0 66 MHz 66 MHz 66 IN 66 MHz Input 66 IN/2 14.318 MHz 48 MHz 2, 3, 4 1 0 1 100 MHz 66 MHz 66 IN 66 MHz Input 66 IN/2 14.318 MHz 48 MHz 2, 3, 4 1 1 0 200 MHz 66 MHz 66 IN 66 MHz Input 66 IN/2 14.318 MHz 48 MHz 2, 3, 4 1 1 1 133 MHz 66 MHz 66 IN 66 MHz Input 66 IN/2 14.318 MHz 48 MHz 2, 3, 4 0 0 0 66 MHz 66 MHz 66 MHz 66 MHz 33 MHz 14.318 MHz 48 MHz 2, 3, 4 0 0 1 100 MHz 66 MHz 66 MHz 66 MHz 33 MHz 14.318 MHz 48 MHz 2, 3, 4 0 1 0 200 MHz 66 MHz 66 MHz 66 MHz 33 MHz 14.318 MHz 48 MHz 2, 3, 4 0 1 1 133 MHz 66 MHz 66 MHz 66 MHz 33 MHz 14.318 MHz 48 MHz 2, 3, 4 Mid 0 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 1, 5 Mid 0 1 TCLK/2 TCLK/4 TCLK/4 TCLK/4 TCLK/8 TCLK TCLK/2 6, 7, 8 Mid 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved – Mid 1 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved – Swing Select Functions Mult0 Board Target Trace/Term Z Reference R, IREF = VDD/(3*Rr) Output Current VOH @ Z 0 60 Rr = 221 1%, IREF = 5.00 mA IOH = 4*IREF 1.0V @ 50 1 50 Rr = 475 1%, IREF = 2.32 mA IOH = 6*IREF 0.7V @ 50 Clock Driver Impedances Impedance Buffer Name VDD Range CPU, CPU# Buffer Type Minimum  Typical  20 40 Type X1 Maximum  50 REF 3.135–3.465 Type 3 60 PCI, 3V66, 66BUFF 3.135–3.465 Type 5 12 30 55 USB 3.135–3.465 Type 3A 12 30 55 DOT 3.135–3.465 Type 3B 12 30 55 Clock Enable Configuration PWR_DWN# CPU_STOP# PCI_STOP# CPU CPU# 3V66 66BUFF PCI_F PCI USB/DOT VCOS/ OSC 0 X X IREF*2 FLOAT LOW LOW LOW LOW LOW OFF 1 0 0 IREF*2 FLOAT ON ON ON OFF ON ON 1 0 1 IREF*2 FLOAT ON ON ON ON ON ON 1 1 0 ON ON ON ON ON OFF ON ON 1 1 1 ON ON ON ON ON ON ON ON Notes: 1. TCLK is a test clock driven in on the XTALIN input in test mode. 2. “Normal” mode of operation. 3. Range of reference frequency allowed is min. = 14.316 nominal = 14.31818 MHz, max = 14.32 MHz. 4. Frequency accuracy of 48 MHz must be +167PPM to match USB default. 5. Mid is defined a Voltage level between 1.0V and 1.8V for 3 level input functionality. Low is below 0.8V. High is above 2.0V. 6. TCLK is a test clock over driven on the XTAL_IN input during test mode. 7. Required for DC output impedance verification. 8. These modes are to use the SAME internal dividers as the CPU = 200-MHz mode. The only change is to slow down the internal VCO to allow under clock margining. ........................Document #: 38-07248 Rev. *C Page 3 of 16 W320-03 Serial Data Interface (SMBus) ability to stop after any complete byte has been transferred. Indexed bytes are not allowed. To enhance the flexibility and function of the clock synthesizer, a two signal SMBus interface is provided according to the SMBus specification. Through the Serial Data Interface (SDI), various device functions such as individual clock output buffers, etc can be individually enabled or disabled. W320-03 support both block read and block write operations. A block write begins with a slave address and a WRITE condition. The R/W bit is used by the SMBus controller as a data direction bit. A zero indicates a WRITE condition to the clock device. The slave receiver address is 11010010 (D2h). The registers associated with the SDI initialize to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. Data Protocol The clock driver serial protocol accepts only block writes from the controller. The bytes must be accessed in sequential order from lowest to highest byte, (most significant bit first) with the Start Slave Address R/W bit 1 1 0 1 0 0 1 0 0/1 A Command Code 00000000 1 bit 1 8 bits 7 bits 1 A command code of 0000 0000 (00h) and the byte count bytes are required for any transfer. After the command code, the core logic issues a byte count which describes number of additional bytes required for the transfer, not including the command code and byte count bytes. For example, if the host has 20 data bytes to send, the first byte would be the number 20 (14h), followed by the 20 bytes of data. The byte count byte is required to be a minimum of one byte and a maximum of 32 bytes It may not be 0. Figure 1 shows an example of a block write. A transfer is considered valid after the acknowledge bit corresponding to the byte count is read by the controller. A Byte Count = A Data Byte 0 A N 1 8 bits 1 8 bits ... 1 Data Byte N-1 A Stop bit 8 bits 1 1 bit From Master to Slave From Slave to Master Figure 1. An Example of a Block Write Data Byte Configuration Map Data Byte 0: Control Register (0 = Enable, 1 = Disable) Bit Affected Pin# Name Description Type Power On Default Bit 7 5, 6, 7, 10, 11, 12, 13, 16, 17, 18, 33, 35 PCI [0:6] CPU[2:0] 3V66[1:0] Spread Spectrum Enable 0 = Spread Off, 1 = Spread On R/W 0 Bit 6 – TBD TBD R 0 Bit 5 35 3V66_1/VCH VCH Select 66 MHz/48 MHz 0 = 66 MHz, 1 = 48 MHz R/W 0 Bit 4 44, 45, 48, 49, 51, 52 CPU [2:0] CPU# [2:0] CPU_STOP# Reflects the current value of the external CPU_STOP# pin R N/A Bit 3 10, 11, 12, 13, 16, 17, 18 PCI [6:0] PCI_STOP# (Does not affect PCI_F [2:0] pins) R/W N/A Bit 2 – – S2 Reflects the value of the S2 pin sampled on Power-up R N/A Bit 1 – – S1 Reflects the value of the S1 pin sampled on Power-up R N/A Bit 0 – – S0 Reflects the value of the S1 pin sampled on Power-up R N/A ........................Document #: 38-07248 Rev. *C Page 4 of 16 W320-03 Data Byte 1 Bit Bit 7 Pin# – Name N/A Description CPU Mult0 Value Type R Power On Default N/A Bit 6 – N/A TBD R 0 Bit 5 44, 45 CPU2 CPU2# Allow Control of CPU2 with assertion of CPU_STOP# 0 = Not free running; 1 = Free running R/W 0 Bit 4 48, 49 CPU1 CPU1# Allow Control of CPU1 with assertion of CPU_STOP# 0 = Not free running;1 = Free running R/W 0 Bit 3 51, 52 CPU0 CPU0# Allow Control of CPU0 with assertion of CPU_STOP# 0= Not free running; 1 = Free running R/W 0 Bit 2 44, 45 CPU2 CPU2# CPU2 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 1 48, 49 CPU1 CPU1# CPU1Output Enable 1 = Enabled; 0= Disabled R/W 1 Bit 0 51, 52 CPU0 CPU0# CPU0 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Data Byte 2 Bit Pin# Name Pin Description Type Power On Default Bit 7 – N/A N/A R 0 Bit 6 18 PCI6 PCI6 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 5 17 PCI5 PCI5 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 4 16 PCI4 PCI4 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 3 13 PCI3 PCI3 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 2 12 PCI2 PCI2 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 1 11 PCI1 PCI1 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 0 10 PCI0 PCI0 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Data Byte 3 Bit Pin# Name Pin Description Type Power On Default Bit 7 38 DOT DOT 48-MHz Output Enable R/W 1 Bit 6 39 USB USB 48-MHz Output Enable R/W 1 Bit 5 7 PCI_F2 Allow control of PCI_F2 with assertion of PCI_STOP# 0 = Free running; 1 = Stopped with PCI_STOP# R/W 0 Bit 4 6 PCI_F1 Allow control of PCI_F1 with assertion of PCI_STOP# 0 = Free running; 1 = Stopped with PCI_STOP# R/W 0 Bit 3 5 PCI_F0 Allow control of PCI_F0 with assertion of PCI_STOP# 0 = Free running; 1 = Stopped with PCI_STOP# R/W 0 Bit 2 7 PCI_F2 PCI_F2 Output Enable R/W 1 Bit 1 6 PCI_F1 PCI_F1Output Enable R/W 1 Bit 0 5 PCI_F0 PCI_F0 Output Enable R/W 1 ........................Document #: 38-07248 Rev. *C Page 5 of 16 W320-03 Data Byte 4 Bit Pin# Bit 7 -- Name TBD Pin Description Type N/A R Power On Default 0 Bit 6 -- TBD N/A R 0 Bit 5 33 3V66_0 3V66_0 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 4 35 3V66_1/VCH 3V66_1/VCH Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 3 24 66IN/3V66_5 R/W 3V66_5 Output Enable 1 = Enable; 0 = Disable NOTE: THIS BIT SHOULD BE USED WHEN PIN 24 IS CONFIGURED AS 3V66_5 OUTPUT. DO NOT CLEAR THIS BIT WHEN PIN 24 IS CONFIGURED AS 66IN INPUT. 1 Bit 2 23 66BUFF2 66-MHz Buffered 2 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 1 22 66BUFF1 66-MHz Buffered 1 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 0 21 66BUFF0 66-MHz Buffered 0 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Data Byte 5 Bit Pin# Bit 7 Name N/A Pin Description Type N/A R Power On Default 0 Bit 6 N/A N/A R 0 Bit 5 66BUFF [2:0] Tpd 66IN to 66BUFF propagation delay control R/W 0 R/W 0 DOT edge rate control R/W 0 R/W 0 USB edge rate control R/W 0 R/W 0 Bit 4 66BUFF [2:0] Bit 3 DOT Bit 2 DOT Bit 1 USB Bit 0 USB Byte 6: Vendor ID Bit Description Power On Default Type Bit 7 Revision Code Bit 3 R 0 Bit 6 Revision Code Bit 2 R 0 Bit 5 Revision Code Bit 1 R 0 Bit 4 Revision Code Bit 0 R 1 Bit 3 Vendor ID Bit 3 R 0 Bit 2 Vendor ID Bit 2 R 1 Bit 1 Vendor ID Bit 1 R 0 Bit 0 Vendor ID Bit 0 R 0 ........................Document #: 38-07248 Rev. *C Page 6 of 16 W320-03 Maximum Ratings Storage Temperature (Non-condensing)........................................–65C to +150C (Above which the useful life may be impaired. For user guidelines, not tested.) Max. Soldering Temperature (10 sec) ....................... +260C Supply Voltage..................................................–0.5 to +7.0V Input Voltage.............................................. –0.5V to VDD+0.5 Junction Temperature................................................ +150C Package Power Dissipation............................................... 1 Static Discharge Voltage (per MIL-STD-883, Method 3015) ........................... > 2000V Operating Conditions Over which Electrical Parameters are Guaranteed[9] Min. Max. Unit VDD_REF, VDD_PCI,VDD_CORE, VDD_3V66, VDD_CPU, Parameter 3.3V Supply Voltages Description 3.135 3.465 V VDD_48 MHz 48-MHz Supply Voltage 2.85 3.465 V 0 TA Operating Temperature, Ambient 70 C Cin Input Pin Capacitance 5 pF CXTAL XTAL Pin Capacitance 22.5 pF CL Max. Capacitive Load on USBCLK, REF PCICLK, 3V66 f(REF) Reference Frequency, Oscillator Nominal Value pF 20 30 14.318 14.318 MHz Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Max. Unit VIH High-level Input Voltage Except Crystal Pads. Threshold voltage for crystal pads = VDD/2 VIL Low-level Input Voltage Except Crystal Pads VOH High-level Output Voltage USB, REF, 3V66 IOH = –1 mA 2.4 V PCI IOH = –1 mA 2.4 V USB, REF, 3V66 IOL = 1 mA 0.4 V PCI IOL = 1 mA 0.55 V VOL Low-level Output Voltage 2.0 V 0.8 V IIH Input High Current 0 < VIN < VDD –5 5 mA IIL Input Low Current 0 < VIN < VDD –5 5 mA IOH High-level Output Current CPU For IOH =6*IRef Configuration REF, DOT, USB Type X1, VOH = 0.65V 12.9 Type X1, VOH = 0.74V Type 3, VOH = 1.00V –29 Type 3, VOH = 3.135V 3V66, DOT, PCI Type 5, VOH = 1.00V –23 –33 Type 5, VOH = 3.135V IOL Low-level Output Current REF, DOT, USB Type 3, VOL = 1.95V –33 29 Type 3, VOL = 0.4V 3V66, PCI Type 5, VOL =1.95 V Type 5, VOL = 0.4V IOZ Output Leakage Current IDD3 3.3V Power Supply Current VDD_CORE/VDD3.3 = 3.465V, FCPU = 133 MHz Three-state mA 14.9 mA 27 30 38 10 mA 360 mA IDDPD3 3.3V Shutdown Current VDD_CORE/VDD3.3 = 3.465V 20 Note: 9. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. mA ........................Document #: 38-07248 Rev. *C Page 7 of 16 W320-03 Switching Characteristics[10] Over the Operating Range Parameter Output Min. Max. Unit Measured at 1.5V 45 55 % USB, REF, DOT Falling Edge Rate Between 2.4V and 0.4V 0.5 2.0 ps PCI,3V66 Falling Edge Rate Between 2.4V and 0.4V 1.0 4.0 V/ns t5 3V66[0:1] 3V66-3V66 Skew Measured at 1.5V 500 ps t5 66BUFF[0:2] 66BUFF-66BUFF Skew Measured at 1.5V 175 ps t6 PCI PCI-PCI Skew Measured at 1.5V t7 3V66,PCI 3V66-PCI Clock Jitter 3V66 leads. Measured at 1.5V t9 3V66 Cycle-Cycle Clock Jitter t9 USB, DOT Cycle-Cycle Clock Jitter t9 PCI Cycle-Cycle Clock Jitter t9 REF Cycle-Cycle Clock Jitter t1 All t3 t3 Description Output Duty Cycle[11] Test Conditions 500 ps 3.5 ns Measured at 1.5V t9 = t9A – t9B 250 ps Measured at 1.5V t9 = t9A – t9B 350 ps Measured at 1.5V t9 = t9A – t9B 500 ps Measured at 1.5V t9 = t9A – t9B 1000 ps 1.5 CPU 1.0V Switching Characteristics t2 CPU RiseTime Measured differential waveform from –0.35V to +0.35V 175 467 ps t3 CPU Fall Time Measured differential waveform from –0.35V to +0.35V 175 467 ps t4 CPU CPU-CPU Skew Measured at Crossover 150 ps t8 CPU Cycle-Cycle Clock Jitter Measured at Crossover t8 = t8A – t8B 150 ps CPU Rise/Fall Matching Measured with test loads[12] 325 mV Voh CPU High-level Output Voltage including overshoot Measured with test loads[12] 0.92 1.45 V Vol CPU Low-level Output Voltage including undershoot Measured with test loads[12] –0.2 0.35 V Vcrossover CPU Crossover Voltage Measured with test loads[12] 0.51 0.76 V CPU 0.7V Switching Characteristics t2 CPU RiseTime Measured single ended waveform from 0.175V to 0.525V 175 700 ps t3 CPU Fall Time Measured single ended waveform from 0.175V to 0.525V 175 700 ps t4 CPU CPU-CPU Skew Measured at Crossover 150 ps t8 CPU Cycle-Cycle Clock Jitter Measured at Crossover t8 = t8A – t8B With all outputs running 150 ps CPU Rise/Fall Matching Measured with test loads[13, 14] 20 % 0.85 V [14] Voh CPU High-level Output Voltage including overshoot Measured with test loads Vol CPU Low-level Output Voltage including undershoot Measured with test loads[14] –0.15 Vcrossover CPU Crossover Voltage Measured with test loads[14] 0.28 Notes: 10. All parameters specified with loaded outputs. 11. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V. 12. The 1.0V test load is shown on test circuit page. 13. Determined as a fraction of 2*(Trp – Trn)/(Trp +Trn) Where Trp is a rising edge and Trp is an intersecting falling edge. 14. The 0.7V test load is Rs = 33.2, Rp = 49.9 in test circuit. ........................Document #: 38-07248 Rev. *C Page 8 of 16 V 0.43 V W320-03 Definition and Application of PWRGD# Signal Vtt VRM8.5 CPU PWRGD# BSEL0 BSEL1 3.3V 3.3V 3.3V NPN PWRGD# CLOCK S0 10K 10K GMCH GENERATOR S1 ........................Document #: 38-07248 Rev. *C Page 9 of 16 10K 10K W320-03 Switching Waveforms Duty Cycle Timing (Single Ended Output) t1B t1A Duty Cycle Timing (CPU Differential Output) t1B t1A All Outputs Rise/Fall Time VDD OUTPUT 0V t3 t2 CPU-CPU Clock Skew Host_b Host Host_b Host t4 3V66-3V66 Clock Skew 3V66 3V66 t5 PCI-PCI Clock Skew PCI PCI t6 ......................Document #: 38-07248 Rev. *C Page 10 of 16 W320-03 Switching Waveforms (continued) 3V66-PCI Clock Skew 3V66 PCI t7 CPU Clock Cycle-Cycle Jitter t8A t8B Host_b Host Cycle-Cycle Clock Jitter t9A t9B CLK PWRDWN# Assertion[15] 66BUFF PCI PCI_F (APIC) Power Down Rest of Generator PWR_DWN# CPU CPU# 3V66 66IN USB REF Note: 15. PCI_STOP# asserted LOW. ...................... Document #: 38-07248 Rev. *C Page 11 of 16 UNDEF W320-03 PWRDWN# Deassertion[15] 10-30 s min. 100-200 s max.