EFM32 Giant Gecko Series 1 Family
EFM32GG12 Family Data Sheet
The EFM32 Giant Gecko Series 1 MCUs are the world’s most
energy-friendly microcontrollers, featuring new connectivity interfaces and user interface features.
• ARM Cortex-M4 at 72 MHz
• Ultra low energy operation
• 76 µA/MHz in Energy Mode 0 (EM0)
• 1.8 μA EM2 Deep Sleep current (RTCC
running with state and RAM retention)
EFM32GG12 includes a powerful 32-bit ARM® Cortex®-M4 and provides robust security
via a unique cryptographic hardware engine supporting AES, ECC, SHA, and True Random Number Generator (TRNG). New features include an SD/MMC/SDIO controller, Octal/Quad-SPI memory controller, CAN bus controller, PDM interface, highly robust capacitive sensing, enhanced alpha blending graphics engine, and LESENSE/PCNT enhancements for smart energy meters. These features, combined with ultra-low current active
mode and short wake-up time from energy-saving modes, make EFM32GG12 microcontrollers well suited for any battery-powered application, as well as other systems requiring high performance and low-energy consumption.
• Octal/Quad-SPI memory interface w/ XIP
• SD/MMC/SDIO Host Controller
• PDM Microphone/Sensor Interface
• Dual CAN 2.0 Bus Controller
• Crystal-free low-energy USB
• Hardware cryptographic engine supports
AES, ECC, SHA, and TRNG
• Robust capacitive touch sense
Example applications:
• Smart energy meters
• Industrial and factory automation
• Home automation and security
Core / Memory
ARM CortexTM
M4 processor
with FPU and
MPU
Flash Program
Memory
RAM Memory
• Footprint compatible with select EFM32
packages
• Mid- and high-tier wearables
• IoT devices
Clock Management
ETM
High Frequency
Crystal Oscillator
High Frequency
RC Oscillator
PLL
Universal HF RC
Oscillator
Auxiliary High
Freq. RC Osc.
Debug Interface
LDMA
Controller
Low Frequency
Crystal Oscillator
Ultra Low Freq.
RC Oscillator
Low Frequency
RC Oscillator
• 5 V tolerant I/O
Energy Management
Voltage
Regulator
Voltage/Temp
Monitor
DC-DC
Converter
Power-On Reset
Brown-Out
Detector
Backup Domain
Other
CRYPTO
CRC
True Random
Number Generator
SMU
32-bit bus
Peripheral Reflex System
Serial Interfaces
I/O Ports
USART
UART
CAN
SD / MMC / SDIO
PDM
Quad-SPI
LEUSB
(crystal free)
Low Energy
UARTTM
EBI + pixel-alpha
I2C
TFT Driver
External
Interrupts
General
Purpose I/O
Pin Reset
Pin Wakeup
Timers and Triggers
Timer/Counter
Low Energy
Sensor IF
Analog Interfaces
Low Energy LCD
Controller
ADC
Low Energy Timer
Real Time Counter
VDAC
Operational
Amplifier
Pulse Counter
Watchdog Timer
Analog
Comparator
IDAC
Real Time Counter
and Calendar
CRYOTIMER
Capacitive
Sensing
Lowest power mode with peripheral operational:
EM0 - Active
EM1 - Sleep
silabs.com | Building a more connected world.
EM2 – Deep Sleep
EM3 - Stop
EM4H - Hibernate
EM4S - Shutoff
Rev. 1.0
EFM32GG12 Family Data Sheet
Feature List
1. Feature List
The EFM32GG12 highlighted features are listed below.
• ARM Cortex-M4 CPU Platform
• High performance 32-bit processor @ up to 72 MHz
• DSP instruction support and Floating Point Unit
• Memory Protection Unit
• Wake-up Interrupt Controller
• Flexible Energy Management System
• 76 μA/MHz in Active Mode (EM0)
• 1.8 μA EM2 Deep Sleep current (16 kB RAM retention and
RTCC running from LFRCO)
• Integrated DC-DC Buck Converter
• Up to 1024 kB Flash Program Memory
• Dual-bank with read-while-write support
• 192 kB RAM Data Memory
• Includes ECC (SEC-DED)
• Octal/Quad-SPI Flash Memory Interface
• Supports 3 V and 1.8 V memories
• 1/2/4/8-bit data bus
• Quad-SPI Execute In Place (XIP)
• Communication Interfaces
• Low-energy Universal Serial Bus (USB) with Device and
Host support
• Fully USB 2.0 compliant
• On-chip PHY and embedded 5 V to 3.3 V regulator
• Crystal-free Device mode operation
• Patent-pending Low-Energy Mode (LEM)
• SD/MMC/SDIO Host Controller
• SD v3.01, SDIO v3.0 and MMC v4.51
• 1/4/8-bit bus width
• Up to 2× CAN Bus Controller
• Version 2.0A and 2.0B up to 1 Mbps
• 5× Universal Synchronous/Asynchronous Receiver/Transmitter
• UART/SPI/SmartCard (ISO 7816)/IrDA/I2S/LIN
• Triple buffered full/half-duplex operation with flow control
• Ultra high speed (36 MHz) operation on one instance
• 2× Universal Asynchronous Receiver/Transmitter
• 2× Low Energy UART
• Autonomous operation with DMA in Deep Sleep Mode
• 2× I2C Interface with SMBus support
• Address recognition in EM3 Stop Mode
silabs.com | Building a more connected world.
• Up to 95 General Purpose I/O Pins
• Configurable push-pull, open-drain, pull-up/down, input filter, drive strength
• Configurable peripheral I/O locations
• 5 V tolerance on select pins
• Asynchronous external interrupts
• Output state retention and wake-up from Shutoff Mode
• Up to 12 Channel DMA Controller
• Up to 16 Channel Peripheral Reflex System (PRS) for autonomous inter-peripheral signaling
• External Bus Interface for up to 4x256 MB of external
memory mapped space
• TFT Controller with Direct Drive
• Per-pixel alpha-blending engine
• Hardware Cryptography
• AES 128/256-bit keys
• ECC B/K163, B/K233, P192, P224, P256
• SHA-1 and SHA-2 (SHA-224 and SHA-256)
• True Random Number Generator (TRNG)
• Hardware CRC Engine
• Single-cycle computation with 8/16/32-bit data and 16-bit
(programmable)/32-bit (fixed) polynomial
• Security Management Unit (SMU)
• Fine-grained access control for on-chip peripherals
• Integrated Low-energy LCD Controller with up to 8×36 segments
• Voltage boost, contrast and autonomous animation
• Patented low-energy LCD driver
• Backup Power Domain
• RTCC and retention registers in a separate power domain,
available down to energy mode EM4H
• Operation from backup battery when main power absent/
insufficient
• Ultra Low-Power Precision Analog Peripherals
• 2× 12-bit 1 Msamples/s Analog to Digital Converter (ADC)
• On-chip temperature sensor
• 2× 12-bit 500 ksamples/s Digital to Analog Converter
(VDAC)
• Digital to Analog Current Converter (IDAC)
• Up to 3× Analog Comparator (ACMP)
• Up to 4× Operational Amplifier (OPAMP)
• Robust current-based capacitive sensing with wake-ontouch (CSEN)
• Up to 83 GPIO pins are analog-capable. Flexible analog peripheral-to-pin routing via Analog Port (APORT)
• Supply Voltage Monitor
Rev. 1.0 | 2
EFM32GG12 Family Data Sheet
Feature List
• Timers/Counters
• 4× 16-bit Timer/Counter
• 3 or 4 Compare/Capture/PWM channels
• Dead-Time Insertion on two timer instances
• 2× 32-bit Timer/Counter
• 3 or 4 Compare/Capture/PWM channels
• Dead-Time Insertion on one timer instance
• 32-bit Real Time Counter and Calendar (RTCC)
• 24-bit Real Time Counter (RTC)
• 32-bit Ultra Low Energy CRYOTIMER for periodic wakeup
from any Energy Mode
• 2× 16-bit Low Energy Timer for waveform generation
• 3× 16-bit Pulse Counter with asynchronous operation
• 2× Watchdog Timer with dedicated RC oscillator
• Low Energy Sensor Interface (LESENSE)
• Autonomous sensor monitoring in Deep Sleep Mode
• Wide range of sensors supported, including LC sensors and
capacitive buttons
• Up to 16 inputs
• Ultra Efficient Power-on Reset and Brown-Out Detector
• Debug Interface
• 2-pin Serial Wire Debug interface
• 1-pin Serial Wire Viewer
• 4-pin JTAG interface
• Embedded Trace Macrocell (ETM)
silabs.com | Building a more connected world.
• Pre-Programmed Bootloader
• Wide Operating Range
• 1.8 V to 3.8 V single power supply
• Integrated DC-DC, down to 1.8 V output with up to 200 mA
load current for system
• Standard (-40 °C to 85 °C TAMB) and Extended (-40 °C to
125 °C TJ) temperature grades available
• Packages
• QFN64 (9x9 mm)
• TQFP64 (10x10 mm)
• TQFP100 (14x14 mm)
• BGA112 (10x10 mm)
• BGA120 (7x7 mm)
Rev. 1.0 | 3
EFM32GG12 Family Data Sheet
Ordering Information
2. Ordering Information
RAM
(kB)
USB
QSPI
EFM32GG12B810F1024GL120-A
1024
192
Yes
Yes
Yes
EFM32GG12B810F1024IL120-A
1024
192
Yes
Yes
Yes
EFM32GG12B830F512GL120-A
512
192
Yes
Yes
EFM32GG12B830F512IL120-A
512
192
Yes
EFM32GG12B810F1024GL112-A
1024
192
EFM32GG12B810F1024IL112-A
1024
EFM32GG12B830F512GL112-A
LCD
Flash
(kB)
SDIO
Ordering Code
DC-DC Converter
Table 2.1. Ordering Information
GPIO
Package
Temp Range
Yes
Yes
95
BGA120
-40 to +85°C
Yes
Yes
95
BGA120
-40 to +125°C
Yes
Yes
Yes
95
BGA120
-40 to +85°C
Yes
Yes
Yes
Yes
95
BGA120
-40 to +125°C
Yes
Yes
Yes
Yes
Yes
89
BGA112
-40 to +85°C
192
Yes
Yes
Yes
Yes
Yes
89
BGA112
-40 to +125°C
512
192
Yes
Yes
Yes
Yes
Yes
89
BGA112
-40 to +85°C
EFM32GG12B830F512IL112-A
512
192
Yes
Yes
Yes
Yes
Yes
89
BGA112
-40 to +125°C
EFM32GG12B810F1024GQ100-A
1024
192
Yes
Yes
Yes
Yes
Yes
81
QFP100
-40 to +85°C
EFM32GG12B810F1024IQ100-A
1024
192
Yes
Yes
Yes
Yes
Yes
81
QFP100
-40 to +125°C
EFM32GG12B830F512GQ100-A
512
192
Yes
Yes
Yes
Yes
Yes
81
QFP100
-40 to +85°C
EFM32GG12B830F512IQ100-A
512
192
Yes
Yes
Yes
Yes
Yes
81
QFP100
-40 to +125°C
EFM32GG12B810F1024GM64-A
1024
192
Yes
Yes
Yes
Yes
Yes
51
QFN64
-40 to +85°C
EFM32GG12B810F1024GQ64-A
1024
192
Yes
Yes
Yes
Yes
Yes
48
QFP64
-40 to +85°C
EFM32GG12B810F1024IM64-A
1024
192
Yes
Yes
Yes
Yes
Yes
51
QFN64
-40 to +125°C
EFM32GG12B810F1024IQ64-A
1024
192
Yes
Yes
Yes
Yes
Yes
48
QFP64
-40 to +125°C
EFM32GG12B830F512GM64-A
512
192
Yes
Yes
Yes
Yes
Yes
51
QFN64
-40 to +85°C
EFM32GG12B830F512GQ64-A
512
192
Yes
Yes
Yes
Yes
Yes
48
QFP64
-40 to +85°C
EFM32GG12B830F512IM64-A
512
192
Yes
Yes
Yes
Yes
Yes
51
QFN64
-40 to +125°C
EFM32GG12B830F512IQ64-A
512
192
Yes
Yes
Yes
Yes
Yes
48
QFP64
-40 to +125°C
EFM32GG12B510F1024GL120-A
1024
192
Yes
No
No
No
Yes
95
BGA120
-40 to +85°C
EFM32GG12B510F1024IL120-A
1024
192
Yes
No
No
No
Yes
95
BGA120
-40 to +125°C
EFM32GG12B530F512GL120-A
512
192
Yes
No
No
No
Yes
95
BGA120
-40 to +85°C
EFM32GG12B530F512IL120-A
512
192
Yes
No
No
No
Yes
95
BGA120
-40 to +125°C
EFM32GG12B510F1024GL112-A
1024
192
Yes
No
No
No
Yes
92
BGA112
-40 to +85°C
EFM32GG12B510F1024IL112-A
1024
192
Yes
No
No
No
Yes
92
BGA112
-40 to +125°C
EFM32GG12B530F512GL112-A
512
192
Yes
No
No
No
Yes
92
BGA112
-40 to +85°C
EFM32GG12B530F512IL112-A
512
192
Yes
No
No
No
Yes
92
BGA112
-40 to +125°C
EFM32GG12B510F1024GQ100-A
1024
192
Yes
No
No
No
Yes
81
QFP100
-40 to +85°C
EFM32GG12B510F1024IQ100-A
1024
192
Yes
No
No
No
Yes
81
QFP100
-40 to +125°C
silabs.com | Building a more connected world.
Rev. 1.0 | 4
EFM32GG12 Family Data Sheet
USB
QSPI
EFM32GG12B530F512GQ100-A
512
192
Yes
No
No
EFM32GG12B530F512IQ100-A
512
192
Yes
No
No
EFM32GG12B510F1024GM64-A
1024
192
Yes
No
EFM32GG12B510F1024GQ64-A
1024
192
Yes
EFM32GG12B510F1024IM64-A
1024
192
EFM32GG12B510F1024IQ64-A
1024
EFM32GG12B530F512GM64-A
LCD
RAM
(kB)
SDIO
Flash
(kB)
DC-DC Converter
Ordering Information
GPIO
Package
Temp Range
No
Yes
81
QFP100
-40 to +85°C
No
Yes
81
QFP100
-40 to +125°C
No
No
Yes
54
QFN64
-40 to +85°C
No
No
No
Yes
51
QFP64
-40 to +85°C
Yes
No
No
No
Yes
54
QFN64
-40 to +125°C
192
Yes
No
No
No
Yes
51
QFP64
-40 to +125°C
512
192
Yes
No
No
No
Yes
54
QFN64
-40 to +85°C
EFM32GG12B530F512GQ64-A
512
192
Yes
No
No
No
Yes
51
QFP64
-40 to +85°C
EFM32GG12B530F512IM64-A
512
192
Yes
No
No
No
Yes
54
QFN64
-40 to +125°C
EFM32GG12B530F512IQ64-A
512
192
Yes
No
No
No
Yes
51
QFP64
-40 to +125°C
EFM32GG12B410F1024GL120-A
1024
192
No
Yes
Yes
Yes
Yes
93
BGA120
-40 to +85°C
EFM32GG12B410F1024IL120-A
1024
192
No
Yes
Yes
Yes
Yes
93
BGA120
-40 to +125°C
EFM32GG12B430F512GL120-A
512
192
No
Yes
Yes
Yes
Yes
93
BGA120
-40 to +85°C
EFM32GG12B430F512IL120-A
512
192
No
Yes
Yes
Yes
Yes
93
BGA120
-40 to +125°C
EFM32GG12B410F1024GL112-A
1024
192
No
Yes
Yes
Yes
Yes
87
BGA112
-40 to +85°C
EFM32GG12B410F1024IL112-A
1024
192
No
Yes
Yes
Yes
Yes
87
BGA112
-40 to +125°C
EFM32GG12B430F512GL112-A
512
192
No
Yes
Yes
Yes
Yes
87
BGA112
-40 to +85°C
EFM32GG12B430F512IL112-A
512
192
No
Yes
Yes
Yes
Yes
87
BGA112
-40 to +125°C
EFM32GG12B410F1024GQ100-A
1024
192
No
Yes
Yes
Yes
Yes
83
QFP100
-40 to +85°C
EFM32GG12B410F1024IQ100-A
1024
192
No
Yes
Yes
Yes
Yes
83
QFP100
-40 to +125°C
EFM32GG12B430F512GQ100-A
512
192
No
Yes
Yes
Yes
Yes
83
QFP100
-40 to +85°C
EFM32GG12B430F512IQ100-A
512
192
No
Yes
Yes
Yes
Yes
83
QFP100
-40 to +125°C
EFM32GG12B410F1024GM64-A
1024
192
No
Yes
Yes
Yes
Yes
53
QFN64
-40 to +85°C
EFM32GG12B410F1024GQ64-A
1024
192
No
Yes
Yes
Yes
Yes
50
QFP64
-40 to +85°C
EFM32GG12B410F1024IM64-A
1024
192
No
Yes
Yes
Yes
Yes
53
QFN64
-40 to +125°C
EFM32GG12B410F1024IQ64-A
1024
192
No
Yes
Yes
Yes
Yes
50
QFP64
-40 to +125°C
EFM32GG12B430F512GM64-A
512
192
No
Yes
Yes
Yes
Yes
53
QFN64
-40 to +85°C
EFM32GG12B430F512GQ64-A
512
192
No
Yes
Yes
Yes
Yes
50
QFP64
-40 to +85°C
EFM32GG12B430F512IM64-A
512
192
No
Yes
Yes
Yes
Yes
53
QFN64
-40 to +125°C
EFM32GG12B430F512IQ64-A
512
192
No
Yes
Yes
Yes
Yes
50
QFP64
-40 to +125°C
EFM32GG12B310F1024GL112-A
1024
192
No
No
No
No
Yes
90
BGA112
-40 to +85°C
EFM32GG12B330F512GL112-A
512
192
No
No
No
No
Yes
90
BGA112
-40 to +85°C
EFM32GG12B310F1024GQ100-A
1024
192
No
No
No
No
Yes
86
QFP100
-40 to +85°C
EFM32GG12B330F512GQ100-A
512
192
No
No
No
No
Yes
86
QFP100
-40 to +85°C
Ordering Code
silabs.com | Building a more connected world.
Rev. 1.0 | 5
EFM32GG12 Family Data Sheet
RAM
(kB)
USB
QSPI
EFM32GG12B110F1024GM64-A
1024
192
No
No
No
EFM32GG12B110F1024GQ64-A
1024
192
No
No
No
EFM32GG12B110F1024IM64-A
1024
192
No
No
EFM32GG12B110F1024IQ64-A
1024
192
No
EFM32GG12B130F512GM64-A
512
192
EFM32GG12B130F512GQ64-A
512
EFM32GG12B130F512IM64-A
EFM32GG12B130F512IQ64-A
LCD
Flash
(kB)
SDIO
Ordering Code
DC-DC Converter
Ordering Information
GPIO
Package
Temp Range
No
No
56
QFN64
-40 to +85°C
No
No
53
QFP64
-40 to +85°C
No
No
No
56
QFN64
-40 to +125°C
No
No
No
No
53
QFP64
-40 to +125°C
No
No
No
No
No
56
QFN64
-40 to +85°C
192
No
No
No
No
No
53
QFP64
-40 to +85°C
512
192
No
No
No
No
No
56
QFN64
-40 to +125°C
512
192
No
No
No
No
No
53
QFP64
-40 to +125°C
EFM32 G G 1 2 B 810 F 1024 G L 120 – A R
Tape and Reel (Optional)
Revision
Pin Count
Package – M (QFN), L (BGA), Q (QFP)
Temperature Grade – G (-40 to +85 °C), I (-40 to +125 °C)
Flash Memory Size in kB
Memory Type (Flash)
Feature Set Code
Performance Grade – B (Basic)
Device Configuration
Series
Gecko
Family – G (Giant)
Energy Friendly Microcontroller 32-bit
Figure 2.1. Ordering Code Key
silabs.com | Building a more connected world.
Rev. 1.0 | 6
Table of Contents
1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Introduction .
.
.
.
.
.
.
.
11
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.11
3.2 Power . . . . . . . . . . .
3.2.1 Energy Management Unit (EMU)
3.2.2 DC-DC Converter . . . . .
3.2.3 5 V Regulator . . . . . . .
3.2.4 EM2 and EM3 Power Domains .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.12
.12
.12
.12
.13
3.3 General Purpose Input/Output (GPIO) .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.13
3.4 Clocking . . . . . . . . . .
3.4.1 Clock Management Unit (CMU) .
3.4.2 Internal and External Oscillators.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.13
.13
.14
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.14
.14
.14
.14
.14
.14
.15
.15
3.6 Communications and Other Digital Peripherals . . . . . . . . . .
3.6.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) .
3.6.2 Universal Asynchronous Receiver/Transmitter (UART) . . . . . .
3.6.3 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) .
3.6.4 Inter-Integrated Circuit Interface (I2C) . . . . . . . . . . . .
3.6.5 External Bus Interface (EBI) . . . . . . . . . . . . . . .
3.6.6 Quad-SPI Flash Controller (QSPI) . . . . . . . . . . . . .
3.6.7 SDIO Host Controller (SDIO) . . . . . . . . . . . . . . .
3.6.8 Universal Serial Bus (USB) . . . . . . . . . . . . . . .
3.6.9 Controller Area Network (CAN) . . . . . . . . . . . . . .
3.6.10 Peripheral Reflex System (PRS) . . . . . . . . . . . . .
3.6.11 Low Energy Sensor Interface (LESENSE) . . . . . . . . . .
3.6.12 Pulse Density Modulation (PDM) Interface . . . . . . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.15
.15
.15
.15
.15
.15
.16
.16
.16
.16
.16
.16
.16
3.7 Security Features . . . . . . . . . . . . . .
3.7.1 General Purpose Cyclic Redundancy Check (GPCRC)
3.7.2 Crypto Accelerator (CRYPTO) . . . . . . . .
3.7.3 True Random Number Generator (TRNG) . . . .
3.7.4 Security Management Unit (SMU) . . . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.17
.17
.17
.17
.17
3.8 Analog. . . . . . . . . . .
3.8.1 Analog Port (APORT) . . . .
3.8.2 Analog Comparator (ACMP) . .
3.8.3 Analog to Digital Converter (ADC)
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.17
.17
.17
.17
.
.
.
3.5 Counters/Timers and PWM . . . . . . . . .
3.5.1 Timer/Counter (TIMER) . . . . . . . .
3.5.2 Wide Timer/Counter (WTIMER) . . . . . .
3.5.3 Real Time Counter and Calendar (RTCC) . .
3.5.4 Low Energy Timer (LETIMER) . . . . . .
3.5.5 Ultra Low Power Wake-up Timer (CRYOTIMER)
3.5.6 Pulse Counter (PCNT) . . . . . . . . .
3.5.7 Watchdog Timer (WDOG) . . . . . . . .
silabs.com | Building a more connected world.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Rev. 1.0 | 7
3.8.4
3.8.5
3.8.6
3.8.7
3.8.8
Capacitive Sense (CSEN) . . . . . .
Digital to Analog Current Converter (IDAC)
Digital to Analog Converter (VDAC) . .
Operational Amplifiers . . . . . . .
Liquid Crystal Display Driver (LCD). . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.18
.18
.18
.18
.18
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.18
3.10 Core and Memory . . . . . . . . . . . .
3.10.1 Processor Core . . . . . . . . . . . .
3.10.2 Memory System Controller (MSC) . . . . .
3.10.3 Linked Direct Memory Access Controller (LDMA)
3.10.4 Bootloader . . . . . . . . . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.18
.18
.19
.19
.19
3.11 Memory Map .
3.9 Reset Management Unit (RMU) .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.20
3.12 Configuration Summary
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.22
4. Electrical Specifications
. . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . .24
4.1.2 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.1.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .27
4.1.4 DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.1.5 5V Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
4.1.6 Backup Supply Domain . . . . . . . . . . . . . . . . . . . . . . . . .31
4.1.7 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . .32
4.1.8 Wake Up Times . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.1.9 Brown Out Detector (BOD) . . . . . . . . . . . . . . . . . . . . . . . .40
4.1.10 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
4.1.11 Flash Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . .48
4.1.12 General-Purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . .49
4.1.13 Voltage Monitor (VMON) . . . . . . . . . . . . . . . . . . . . . . . . .51
4.1.14 Analog to Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . .52
4.1.15 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . . . .54
4.1.16 Digital to Analog Converter (VDAC) . . . . . . . . . . . . . . . . . . . . .57
4.1.17 Current Digital to Analog Converter (IDAC) . . . . . . . . . . . . . . . . . .60
4.1.18 Capacitive Sense (CSEN) . . . . . . . . . . . . . . . . . . . . . . . .62
4.1.19 Operational Amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . .64
4.1.20 LCD Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
4.1.21 Pulse Counter (PCNT) . . . . . . . . . . . . . . . . . . . . . . . . .68
4.1.22 Analog Port (APORT) . . . . . . . . . . . . . . . . . . . . . . . . . .68
4.1.23 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
4.1.24 USART SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
4.1.25 External Bus Interface (EBI) . . . . . . . . . . . . . . . . . . . . . . .75
4.1.26 Serial Data I/O Host Controller (SDIO) . . . . . . . . . . . . . . . . . . . .84
4.1.27 Quad SPI (QSPI)
. . . . . . . . . . . . . . . . . . . . . . . . . .103
4.1.28 PDM
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
.
4.2 Typical Performance Curves
. . . . . . . . . . . . . . . . . . . . . . . .108
4.2.1 Supply Current
. . . . . . . . . . . . . . . . . . . . . . . . . . 1. 09
4.2.2 DC-DC Converter
. . . . . . . . . . . . . . . . . . . . . . . . . 115
.
silabs.com | Building a more connected world.
Rev. 1.0 | 8
5. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
5.1 EFM32GG12B8xx in BGA120 Device Pinout .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 117
5.2 EFM32GG12B5xx in BGA120 Device Pinout .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 120
5.3 EFM32GG12B4xx in BGA120 Device Pinout .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 123
5.4 EFM32GG12B8xx in BGA112 Device Pinout .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 126
5.5 EFM32GG12B5xx in BGA112 Device Pinout .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 129
5.6 EFM32GG12B4xx in BGA112 Device Pinout .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 132
5.7 EFM32GG12B3xx in BGA112 Device Pinout .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 135
5.8 EFM32GG12B8xx in QFP100 Device Pinout .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 138
5.9 EFM32GG12B5xx in QFP100 Device Pinout .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 141
5.10 EFM32GG12B4xx in QFP100 Device Pinout
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 1
. 44
5.11 EFM32GG12B3xx in QFP100 Device Pinout
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 1
. 47
5.12 EFM32GG12B8xx in QFP64 Device Pinout .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 150
5.13 EFM32GG12B5xx in QFP64 Device Pinout .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 152
5.14 EFM32GG12B4xx in QFP64 Device Pinout .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 154
5.15 EFM32GG12B1xx in QFP64 Device Pinout .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 156
5.16 EFM32GG12B8xx in QFN64 Device Pinout .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 158
5.17 EFM32GG12B5xx in QFN64 Device Pinout .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 160
5.18 EFM32GG12B4xx in QFN64 Device Pinout .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 162
5.19 EFM32GG12B1xx in QFN64 Device Pinout .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 164
5.20 GPIO Functionality Table
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 166
.
.
.
.
.
5.21 Alternate Functionality Overview
.
.
5.22 Analog Port (APORT) Client Maps .
6. BGA120 Package Specifications
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 178
.
.
. 204
. . . . . . . . . . . . . . . . . . . . . . .216
6.1 BGA120 Package Dimensions .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 216
6.2 BGA120 PCB Land Pattern .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 218
.
6.3 BGA120 Package Marking .
.
.
7. BGA112 Package Specifications
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 220
. . . . . . . . . . . . . . . . . . . . . . .221
7.1 BGA112 Package Dimensions .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 221
7.2 BGA112 PCB Land Pattern .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 223
.
7.3 BGA112 Package Marking .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 225
8. TQFP100 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . 226
8.1 TQFP100 Package Dimensions
8.2 TQFP100 PCB Land Pattern
8.3 TQFP100 Package Marking
.
.
9. TQFP64 Package Specifications
9.1 TQFP64 Package Dimensions .
silabs.com | Building a more connected world.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.226
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.228
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 229
.
. . . . . . . . . . . . . . . . . . . . . . .230
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 230
Rev. 1.0 | 9
9.2 TQFP64 PCB Land Pattern .
.
9.3 TQFP64 Package Marking .
.
.
.
.
10. QFN64 Package Specifications
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 232
.
. 233
. . . . . . . . . . . . . . . . . . . . . . .234
10.1 QFN64 Package Dimensions.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 234
10.2 QFN64 PCB Land Pattern.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 236
10.3 QFN64 Package Marking .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 238
11. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
silabs.com | Building a more connected world.
Rev. 1.0 | 10
EFM32GG12 Family Data Sheet
System Overview
3. System Overview
3.1 Introduction
The Giant Gecko Series 1 product family is well suited for any battery operated application as well as other systems requiring high
performance and low energy consumption. This section gives a short introduction to the MCU system. The detailed functional description can be found in the Giant Gecko Series 1 Reference Manual.
A block diagram of the Giant Gecko Series 1 family is shown in Figure 3.1 Detailed EFM32GG12 Block Diagram on page 11. The
diagram shows a superset of features available on the family, which vary by OPN. For more information about specific device features,
consult Ordering Information.
Energy Management
VREGI
VBUS
VREGO
5V
Regulator
Backup
Domain
IOVDDn
Port I/O Configuration
BU_VIN
To
BU_STAT
BU_VOUT GPIO
Digital Peripherals
Voltage
Monitor
AVDD
DVDD
bypass
VREGVDD
VREGSW
DC-DC
Converter
IOVDDn
n=1: PD9-12,
PE8-13,
PF6-9
n=0: All other GPIO
Voltage
Regulator
DECOUPLE
LETIMER
USB
TIMER / WTIMER
CAN
CRYOTIMER
EBI
PCNT
TFT
RTC / RTCC
SDIO
USART / UART
QSPI
LEUART
CRC
Port A
Drivers
PA0-15
Port B
Drivers
PB0-15
Brown Out /
Power-On
Reset
ARM Cortex-M4 Core
I2C
LESENSE
Up to 1024 KB ISP Flash
Program Memory
CRYPTO
PDM
Port C
Drivers
PC0-15
Up to 192 KB RAM
RESETn
Reset
Management
Unit
Analog Peripherals
Port D
Drivers
PD0-15
Debug Signals
(shared w/GPIO)
Serial Wire
and ETM
Debug /
Programming
Port E
Drivers
PE0-15
Port F
Drivers
PF0-14
Clock Management
ULFRCO
AUXHFRCO
LFRCO
LFXTAL_P
HFXTAL_N
USHFRCO
LFXO
HFRCO + DPLL
HFXO
Internal
Reference
12-bit ADC
Digital Port Mapper
Op-Amp
Analog Port (APORT)
VDAC
Mux & FB
LDMA Controller
Watchdog
Timers
LFXTAL_N
HFXTAL_P
IDAC
Floating Point Unit
Input Mux
Security Management
+
-
Memory Protection Unit
TRNG
A A
H P
B B
VDD
Temp
Sense
Capacitive
Touch
+
Analog Comparator
Low-Energy LCD, up to 8x36
configuration
Figure 3.1. Detailed EFM32GG12 Block Diagram
silabs.com | Building a more connected world.
Rev. 1.0 | 11
EFM32GG12 Family Data Sheet
System Overview
3.2 Power
The EFM32GG12 has an Energy Management Unit (EMU) and efficient integrated regulators to generate internal supply voltages. Only
a single external supply voltage is required, from which all internal voltages are created. A 5 V regulator is available on some OPNs,
allowing the device to be powered directly from 5 V power sources, such as USB. An optional integrated DC-DC buck regulator can be
utilized to further reduce the current consumption. The DC-DC regulator requires one external inductor and one external capacitor.
The EFM32GG12 device family includes support for internal supply voltage scaling, as well as two different power domain groups for
peripherals. These enhancements allow for further supply current reductions and lower overall power consumption.
AVDD and VREGVDD need to be 1.8 V or higher for the MCU to operate across all conditions; however the rest of the system will
operate down to 1.62 V, including the digital supply and I/O. This means that the device is fully compatible with 1.8 V components.
Running from a sufficiently high supply, the device can use the DC-DC to regulate voltage not only for itself, but also for other PCB
components, supplying up to a total of 200 mA.
3.2.1 Energy Management Unit (EMU)
The Energy Management Unit manages transitions of energy modes in the device. Each energy mode defines which peripherals and
features are available and the amount of current the device consumes. The EMU can also be used to turn off the power to unused RAM
blocks, and it contains control registers for the DC-DC regulator and the Voltage Monitor (VMON). The VMON is used to monitor multiple supply voltages. It has multiple channels which can be programmed individually by the user to determine if a sensed supply has
fallen below a chosen threshold.
3.2.2 DC-DC Converter
The DC-DC buck converter covers a wide range of load currents and provides up to 90% efficiency in energy modes EM0, EM1, EM2
and EM3, and can supply up to 200 mA to the device and surrounding PCB components. Protection features include programmable
current limiting, short-circuit protection, and dead-time protection. The DC-DC converter may also enter bypass mode when the input
voltage is too low for efficient operation. In bypass mode, the DC-DC input supply is internally connected directly to its output through a
low resistance switch. Bypass mode also supports in-rush current limiting to prevent input supply voltage droops due to excessive output current transients.
3.2.3 5 V Regulator
A 5 V input regulator is available, allowing the device to be powered directly from 5 V power sources such as the USB VBUS line. The
regulator is available in all energy modes, and outputs 3.3 V to be used to power the USB PHY and other 3.3 V systems. Two inputs to
the regulator allow for seamless switching between local and external power sources.
silabs.com | Building a more connected world.
Rev. 1.0 | 12
EFM32GG12 Family Data Sheet
System Overview
3.2.4 EM2 and EM3 Power Domains
The EFM32GG12 has three independent peripheral power domains for use in EM2 and EM3. Two of these domains are dynamic and
can be shut down to save energy. Peripherals associated with the two dynamic power domains are listed in Table 3.1 EM2 and EM3
Peripheral Power Subdomains on page 13. If all of the peripherals in a peripheral power domain are unused, the power domain for
that group will be powered off in EM2 and EM3, reducing the overall current consumption of the device. Other EM2, EM3, and EM4capable peripherals and functions not listed in the table below reside on the primary power domain, which is always on in EM2 and
EM3.
Table 3.1. EM2 and EM3 Peripheral Power Subdomains
Peripheral Power Domain 1
Peripheral Power Domain 2
ACMP0
ACMP1
PCNT0
PCNT1
ADC0
PCNT2
LETIMER0
CSEN
LESENSE
VDAC0
APORT
LEUART0
-
LEUART1
-
LETIMER1
-
I2C0
-
I2C1
-
IDAC
-
ADC1
-
ACMP2
-
LCD
-
RTC
3.3 General Purpose Input/Output (GPIO)
EFM32GG12 has up to 95 General Purpose Input/Output pins. GPIO are organized on three independent supply rails, allowing for interface to multiple logic levels in the system simultaneously. Each GPIO pin can be individually configured as either an output or input.
More advanced configurations including open-drain, open-source, and glitch-filtering can be configured for each individual GPIO pin.
The GPIO pins can be overridden by peripheral connections, like SPI communication. Each peripheral connection can be routed to several GPIO pins on the device. The input value of a GPIO pin can be routed through the Peripheral Reflex System to other peripherals.
The GPIO subsystem supports asynchronous external pin interrupts.
3.4 Clocking
3.4.1 Clock Management Unit (CMU)
The Clock Management Unit controls oscillators and clocks in the EFM32GG12. Individual enabling and disabling of clocks to all peripherals is performed by the CMU. The CMU also controls enabling and configuration of the oscillators. A high degree of flexibility allows software to optimize energy consumption in any specific application by minimizing power dissipation in unused peripherals and
oscillators.
silabs.com | Building a more connected world.
Rev. 1.0 | 13
EFM32GG12 Family Data Sheet
System Overview
3.4.2 Internal and External Oscillators
The EFM32GG12 supports two crystal oscillators and fully integrates five RC oscillators, listed below.
• A high frequency crystal oscillator (HFXO) with integrated load capacitors, tunable in small steps, provides a precise timing reference for the MCU. Crystal frequencies in the range from 4 to 50 MHz are supported. An external clock source such as a TCXO can
also be applied to the HFXO input for improved accuracy over temperature.
• A 32.768 kHz crystal oscillator (LFXO) provides an accurate timing reference for low energy modes.
• An integrated high frequency RC oscillator (HFRCO) is available for the MCU system. The HFRCO employs fast startup at minimal
energy consumption combined with a wide frequency range. When crystal accuracy is not required, it can be operated in free-running mode at a number of factory-calibrated frequencies. A digital phase-locked loop (DPLL) feature allows the HFRCO to achieve
higher accuracy and stability by referencing other available clock sources such as LFXO and HFXO.
• An integrated auxilliary high frequency RC oscillator (AUXHFRCO) is available for timing the general-purpose ADC and the Serial
Wire Viewer port with a wide frequency range.
• An integrated universal high frequency RC oscillator (USHFRCO) is available for timing the USB, SDIO and QSPI peripherals. The
USHFRCO can be syncronized to the host's USB clock to allow the USB to operate in device mode without the additional cost of an
external crystal.
• An integrated low frequency 32.768 kHz RC oscillator (LFRCO) can be used as a timing reference in low energy modes, when crystal accuracy is not required.
• An integrated ultra-low frequency 1 kHz RC oscillator (ULFRCO) is available to provide a timing reference at the lowest energy consumption in low energy modes.
3.5 Counters/Timers and PWM
3.5.1 Timer/Counter (TIMER)
TIMER peripherals keep track of timing, count events, generate PWM outputs and trigger timed actions in other peripherals through the
PRS system. The core of each TIMER is a 16-bit counter with up to 4 compare/capture channels. Each channel is configurable in one
of three modes. In capture mode, the counter state is stored in a buffer at a selected input event. In compare mode, the channel output
reflects the comparison of the counter to a programmed threshold value. In PWM mode, the TIMER supports generation of pulse-width
modulation (PWM) outputs of arbitrary waveforms defined by the sequence of values written to the compare registers, with optional
dead-time insertion available in timer unit TIMER_0 only.
3.5.2 Wide Timer/Counter (WTIMER)
WTIMER peripherals function just as TIMER peripherals, but are 32 bits wide. They keep track of timing, count events, generate PWM
outputs and trigger timed actions in other peripherals through the PRS system. The core of each WTIMER is a 32-bit counter with up to
4 compare/capture channels. Each channel is configurable in one of three modes. In capture mode, the counter state is stored in a
buffer at a selected input event. In compare mode, the channel output reflects the comparison of the counter to a programmed threshold value. In PWM mode, the WTIMER supports generation of pulse-width modulation (PWM) outputs of arbitrary waveforms defined by
the sequence of values written to the compare registers, with optional dead-time insertion available in timer unit WTIMER_0 only.
3.5.3 Real Time Counter and Calendar (RTCC)
The Real Time Counter and Calendar (RTCC) is a 32-bit counter providing timekeeping in all energy modes. The RTCC includes a
Binary Coded Decimal (BCD) calendar mode for easy time and date keeping. The RTCC can be clocked by any of the on-board oscillators with the exception of the AUXHFRCO, and it is capable of providing system wake-up at user defined instances. The RTCC includes 128 bytes of general purpose data retention, allowing easy and convenient data storage in all energy modes down to EM4H.
3.5.4 Low Energy Timer (LETIMER)
The unique LETIMER is a 16-bit timer that is available in energy mode EM2 Deep Sleep in addition to EM1 Sleep and EM0 Active. This
allows it to be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed
while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of waveforms with minimal software intervention. The LETIMER is connected to the Real Time Counter and Calendar (RTCC), and can be configured to start counting on compare matches from the RTCC.
3.5.5 Ultra Low Power Wake-up Timer (CRYOTIMER)
The CRYOTIMER is a 32-bit counter that is capable of running in all energy modes. It can be clocked by either the 32.768 kHz crystal
oscillator (LFXO), the 32.768 kHz RC oscillator (LFRCO), or the 1 kHz RC oscillator (ULFRCO). It can provide periodic Wakeup events
and PRS signals which can be used to wake up peripherals from any energy mode. The CRYOTIMER provides a wide range of interrupt periods, facilitating flexible ultra-low energy operation.
silabs.com | Building a more connected world.
Rev. 1.0 | 14
EFM32GG12 Family Data Sheet
System Overview
3.5.6 Pulse Counter (PCNT)
The Pulse Counter (PCNT) peripheral can be used for counting pulses on a single input or to decode quadrature encoded inputs. The
clock for PCNT is selectable from either an external source on pin PCTNn_S0IN or from an internal timing reference, selectable from
among any of the internal oscillators, except the AUXHFRCO. The peripheral may operate in energy mode EM0 Active, EM1 Sleep,
EM2 Deep Sleep, and EM3 Stop.
3.5.7 Watchdog Timer (WDOG)
The watchdog timer can act both as an independent watchdog or as a watchdog synchronous with the CPU clock. It has windowed
monitoring capabilities, and can generate a reset or different interrupts depending on the failure mode of the system. The watchdog can
also monitor autonomous systems driven by PRS.
3.6 Communications and Other Digital Peripherals
3.6.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
The Universal Synchronous/Asynchronous Receiver/Transmitter is a flexible serial I/O interface. It supports full duplex asynchronous
UART communication with hardware flow control as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with devices supporting:
• ISO7816 SmartCards
• IrDA
• I2S
3.6.2 Universal Asynchronous Receiver/Transmitter (UART)
The Universal Asynchronous Receiver/Transmitter is a subset of the USART peripheral, supporting full duplex asynchronous UART
communication with hardware flow control and RS-485.
3.6.3 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART)
The unique LEUARTTM provides two-way UART communication on a strict power budget. Only a 32.768 kHz clock is needed to allow
UART communication up to 9600 baud. The LEUART includes all necessary hardware to make asynchronous serial communication
possible with a minimum of software intervention and energy consumption.
3.6.4 Inter-Integrated Circuit Interface (I2C)
The I2C interface enables communication between the MCU and a serial I2C bus. It is capable of acting as both a master and a slave
and supports multi-master buses. Standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates
from 10 kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also available, allowing implementation of an SMBus-compliant system.
The interface provided to software by the I2C peripheral allows precise timing control of the transmission process and highly automated
transfers. Automatic recognition of slave addresses is provided in active and low energy modes.
3.6.5 External Bus Interface (EBI)
The External Bus Interface provides access to external parallel interface devices. The interface is memory mapped into the address bus
of the Cortex-M4. This enables seamless access from software without manually manipulating the I/O settings each time a read or write
is performed. The data and address lines are multiplexed in order to reduce the number of pins required to interface to external devices.
Timing is adjustable to meet specifications of the external devices. The interface is limited to asynchronous devices.
The EBI contains a TFT controller which can drive a TFT via an RGB interface. The TFT controller supports programmable display and
port sizes and offers accurate control of frequency and setup and hold timing. Direct Drive is supported for TFT displays which do not
have their own frame buffer. In that case TFT Direct Drive can transfer data from either on-chip memory or from an external memory
device to the TFT at low CPU load. Automatic alpha-blending and masking is also supported for transfers through the EBI interface.
silabs.com | Building a more connected world.
Rev. 1.0 | 15
EFM32GG12 Family Data Sheet
System Overview
3.6.6 Quad-SPI Flash Controller (QSPI)
The QSPI provides access to to a wide range of flash devices with wide I/O busses. The I/O and clocking configuration is flexible and
supports many types of devices. Up to 8-bit wide interfaces are supported. The QSPI handles opcodes, status flag polling, and timing
configuration automatically.
The external flash memory is mapped directly to internal memory to allow random access to any word in the flash and direct code execution. An integrated instruction cache minimizes latency and allows efficient code execution. Execute in Place (XIP) is supported for
devices with this feature.
Large data chunks can be transferred with DMA as efficiently as possible with high throughput and minimimal bus load, utilizing an
integrated 1 kB SRAM FIFO.
3.6.7 SDIO Host Controller (SDIO)
The SDIO is an SD3.01 / SDIO3.0 / eMMC4.51-compliant Host Controller interface for transferring data to and from SD/MMC/SDIO
devices. The module conforms to the SD Host Controller Standard Specification Version 3.00. The Host Controller handles
SDIO/SD/MMC Protocol at the transmission level, packing data, adding cyclic redundancy check (CRC), Start/End bits, and checking
for transaction format correctness.
3.6.8 Universal Serial Bus (USB)
The USB is a full-speed/low-speed USB 2.0 compliant host/device controller. The USB can be used in device and host-only configurations, while a clock recovery mechanism allows crystal-less operation in device mode. The USB block supports both full speed (12
MBit/s) and low speed (1.5 MBit/s) operation. When operating as a device, a special Low Energy Mode ensures the current consumption is optimized, enabling USB communications on a strict power budget. The USB device includes an internal dedicated DescriptorBased Scatter/Gather DMA and supports up to 6 OUT endpoints and 6 IN endpoints, in addition to endpoint 0. The on-chip PHY includes internal pull-up and pull-down resistors, as well as voltage comparators for monitoring the VBUS voltage and A/B device identification using the ID line.
3.6.9 Controller Area Network (CAN)
The CAN peripheral provides support for communication at up to 1 Mbps over CAN protocol version 2.0 part A and B. It includes 32
message objects with independent identifier masks and retains message RAM in EM2. Automatic retransmittion may be disabled in
order to support Time Triggered CAN applications.
3.6.10 Peripheral Reflex System (PRS)
The Peripheral Reflex System provides a communication network between different peripherals without software involvement. Peripherals producing Reflex signals are called producers. The PRS routes Reflex signals from producers to consumer peripherals, which in
turn perform actions in response. Edge triggers and other functionality such as simple logic operations (AND, OR, NOT) can be applied
by the PRS to the signals. The PRS allows peripheral to act autonomously without waking the MCU core, saving power.
3.6.11 Low Energy Sensor Interface (LESENSE)
The Low Energy Sensor Interface LESENSETM is a highly configurable sensor interface with support for up to 16 individually configurable sensors. By controlling the analog comparators, ADC, and DAC, LESENSE is capable of supporting a wide range of sensors and
measurement schemes, and can for instance measure LC sensors, resistive sensors and capacitive sensors. LESENSE also includes a
programmable finite state machine which enables simple processing of measurement results without CPU intervention. LESENSE is
available in energy mode EM2, in addition to EM0 and EM1, making it ideal for sensor monitoring in applications with a strict energy
budget.
3.6.12 Pulse Density Modulation (PDM) Interface
The PDM module provides a serial interface and decimation filter for Pulse Density Modulation (PDM) microphones, isolated Sigmadelta ADCs, digital sensors and other PDM or sigma delta bit stream peripherals. A programmable Cascaded Integrator Comb (CIC)
filter is used to decimate the incoming bit streams. PDM supports multiple channels of stereo or mono input data and DMA transfer.
silabs.com | Building a more connected world.
Rev. 1.0 | 16
EFM32GG12 Family Data Sheet
System Overview
3.7 Security Features
3.7.1 General Purpose Cyclic Redundancy Check (GPCRC)
The GPCRC block implements a Cyclic Redundancy Check (CRC) function. It supports both 32-bit and 16-bit polynomials. The supported 32-bit polynomial is 0x04C11DB7 (IEEE 802.3), while the 16-bit polynomial can be programmed to any value, depending on the
needs of the application.
3.7.2 Crypto Accelerator (CRYPTO)
The Crypto Accelerator is a fast and energy-efficient autonomous hardware encryption and decryption accelerator. Giant Gecko Series
1 devices support AES encryption and decryption with 128- or 256-bit keys, ECC over both GF(P) and GF(2m), and SHA-1 and SHA-2
(SHA-224 and SHA-256).
Supported block cipher modes of operation for AES include: ECB, CTR, CBC, PCBC, CFB, OFB, GCM, CBC-MAC, GMAC and CCM.
Supported ECC NIST recommended curves include P-192, P-224, P-256, K-163, K-233, B-163 and B-233.
The CRYPTO peripheral allows fast processing of GCM (AES), ECC and SHA with little CPU intervention. CRYPTO also provides trigger signals for DMA read and write operations.
3.7.3 True Random Number Generator (TRNG)
The TRNG is a non-deterministic random number generator based on a full hardware solution. The TRNG is validated with NIST800-22
and AIS-31 test suites as well as being suitable for FIPS 140-2 certification (for the purposes of cryptographic key generation).
3.7.4 Security Management Unit (SMU)
The Security Management Unit (SMU) allows software to set up fine-grained security for peripheral access, which is not possible in the
Memory Protection Unit (MPU). Peripherals may be secured by hardware on an individual basis, such that only priveleged accesses to
the peripheral's register interface will be allowed. When an access fault occurs, the SMU reports the specific peripheral involved and
can optionally generate an interrupt.
3.8 Analog
3.8.1 Analog Port (APORT)
The Analog Port (APORT) is an analog interconnect matrix allowing access to many analog peripherals on a flexible selection of pins.
Each APORT bus consists of analog switches connected to a common wire. Since many clients can operate differentially, buses are
grouped by X/Y pairs.
3.8.2 Analog Comparator (ACMP)
The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is higher. Inputs are selected from among internal references and external pins. The tradeoff between response time and current consumption
is configurable by software. Two 6-bit reference dividers allow for a wide range of internally-programmable reference sources. The
ACMP can also be used to monitor the supply voltage. An interrupt can be generated when the supply falls below or rises above the
programmable threshold.
3.8.3 Analog to Digital Converter (ADC)
The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to 1 Msps. The output
sample resolution is configurable and additional resolution is possible using integrated hardware for averaging over multiple samples.
The ADC includes integrated voltage references and an integrated temperature sensor. Inputs are selectable from a wide range of
sources, including pins configurable as either single-ended or differential.
silabs.com | Building a more connected world.
Rev. 1.0 | 17
EFM32GG12 Family Data Sheet
System Overview
3.8.4 Capacitive Sense (CSEN)
The CSEN peripheral is a dedicated Capacitive Sensing block for implementing touch-sensitive user interface elements such a
switches and sliders. The CSEN peripheral uses a charge ramping measurement technique, which provides robust sensing even in
adverse conditions including radiated noise and moisture. The peripheral can be configured to take measurements on a single port pin
or scan through multiple pins and store results to memory through DMA. Several channels can also be shorted together to measure the
combined capacitance or implement wake-on-touch from very low energy modes. Hardware includes a digital accumulator and an averaging filter, as well as digital threshold comparators to reduce software overhead.
3.8.5 Digital to Analog Current Converter (IDAC)
The IDAC can source or sink a configurable constant current. This current can be driven on an output pin or routed to the selected ADC
input pin for capacitive sensing. The full-scale current is programmable between 0.05 µA and 64 µA with several ranges consisting of
various step sizes.
3.8.6 Digital to Analog Converter (VDAC)
The Digital to Analog Converter (VDAC) can convert a digital value to an analog output voltage. The VDAC is a fully differential, 500
ksps, 12-bit converter. The opamps are used in conjunction with the VDAC, to provide output buffering. One opamp is used per singleended channel, or two opamps are used to provide differential outputs. The VDAC may be used for a number of different applications
such as sensor interfaces or sound output. The VDAC can generate high-resolution analog signals while the MCU is operating at low
frequencies and with low total power consumption. Using DMA and a timer, the VDAC can be used to generate waveforms without any
CPU intervention. The VDAC is available in all energy modes down to and including EM3.
3.8.7 Operational Amplifiers
The opamps are low power amplifiers with a high degree of flexibility targeting a wide variety of standard opamp application areas, and
are available down to EM3. With flexible built-in programming for gain and interconnection they can be configured to support multiple
common opamp functions. All pins are also available externally for filter configurations. Each opamp has a rail to rail input and a rail to
rail output. They can be used in conjunction with the VDAC peripheral or in stand-alone configurations. The opamps save energy, PCB
space, and cost as compared with standalone opamps because they are integrated on-chip.
3.8.8 Liquid Crystal Display Driver (LCD)
The LCD driver is capable of driving a segmented LCD display with up to 8x36 segments. A voltage boost function enables it to provide
the LCD display with higher voltage than the supply voltage for the device. A patented charge redistribution driver can reduce the LCD
module supply current by up to 40%. In addition, an animation feature can run custom animations on the LCD display without any CPU
intervention. The LCD driver can also remain active even in Energy Mode 2 and provides a Frame Counter interrupt that can wake-up
the device on a regular basis for updating data.
3.9 Reset Management Unit (RMU)
The RMU is responsible for handling reset of the EFM32GG12. A wide range of reset sources are available, including several power
supply monitors, pin reset, software controlled reset, core lockup reset, and watchdog reset.
3.10 Core and Memory
3.10.1 Processor Core
The ARM Cortex-M processor includes a 32-bit RISC processor integrating the following features and tasks in the system:
• ARM Cortex-M4 RISC processor with FPU achieving 1.25 Dhrystone MIPS/MHz
• Memory Protection Unit (MPU) supporting up to 8 memory segments
• Embedded Trace Macrocell (ETM) for real-time trace and debug
• Up to 1024 kB flash program memory
• Dual-bank memory with read-while-write support
• Up to 192 kB RAM data memory
• Configuration and event handling of all modules
• 2-pin Serial-Wire or 4-pin JTAG debug interface
silabs.com | Building a more connected world.
Rev. 1.0 | 18
EFM32GG12 Family Data Sheet
System Overview
3.10.2 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the microcontroller. The flash memory is readable and writable
from both the Cortex-M and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code
is normally written to the main block, whereas the information block is available for special user data and flash lock bits. There is also a
read-only page in the information block containing system and device calibration data. Read and write operations are supported in energy modes EM0 Active and EM1 Sleep.
3.10.3 Linked Direct Memory Access Controller (LDMA)
The Linked Direct Memory Access (LDMA) controller allows the system to perform memory operations independently of software. This
reduces both energy consumption and software workload. The LDMA allows operations to be linked together and staged, enabling sophisticated operations to be implemented.
3.10.4 Bootloader
All devices come pre-programmed with a UART bootloader. This bootloader resides in flash and can be erased if it is not needed. More
information about the bootloader protocol and usage can be found in AN0003: UART Bootloader. Application notes can be found on the
Silicon Labs website (www.silabs.com/32bit-appnotes) or within Simplicity Studio in the [Documentation] area.
silabs.com | Building a more connected world.
Rev. 1.0 | 19
EFM32GG12 Family Data Sheet
System Overview
3.11 Memory Map
The EFM32GG12 memory map is shown in the figures below. RAM and flash sizes are for the largest memory configuration.
Figure 3.2. EFM32GG12 Memory Map — Core Peripherals and Code Space
silabs.com | Building a more connected world.
Rev. 1.0 | 20
EFM32GG12 Family Data Sheet
System Overview
Figure 3.3. EFM32GG12 Memory Map — Peripherals
silabs.com | Building a more connected world.
Rev. 1.0 | 21
EFM32GG12 Family Data Sheet
System Overview
3.12 Configuration Summary
The features of the EFM32GG12 are a subset of the feature set described in the device reference manual. The table below describes
device specific implementation of the features. Remaining peripherals support full configuration.
Table 3.2. Configuration Summary
Module
Configuration
Pin Connections
USART0
IrDA, SmartCard
US0_TX, US0_RX, US0_CLK, US0_CS
USART1
I2S, SmartCard
US1_TX, US1_RX, US1_CLK, US1_CS
USART2
IrDA, SmartCard, High-Speed
US2_TX, US2_RX, US2_CLK, US2_CS
USART3
I2S, SmartCard
US3_TX, US3_RX, US3_CLK, US3_CS
USART4
I2S, SmartCard
US4_TX, US4_RX, US4_CLK, US4_CS
TIMER0
with DTI
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1
-
TIM1_CC[3:0]
TIMER2
with DTI
TIM2_CC[2:0], TIM2_CDTI[2:0]
TIMER3
-
TIM3_CC[2:0]
WTIMER0
with DTI
WTIM0_CC[2:0], WTIM0_CDTI[2:0]
WTIMER1
-
WTIM1_CC[3:0]
silabs.com | Building a more connected world.
Rev. 1.0 | 22
EFM32GG12 Family Data Sheet
Electrical Specifications
4. Electrical Specifications
4.1 Electrical Characteristics
All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:
• Typical values are based on TAMB=25 °C and VDD= 3.3 V, by production test and/or technology characterization.
• Minimum and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature,
unless stated otherwise.
Refer to 4.1.2.1 General Operating Conditions for more details about operational supply and temperature limits.
silabs.com | Building a more connected world.
Rev. 1.0 | 23
EFM32GG12 Family Data Sheet
Electrical Specifications
4.1.1 Absolute Maximum Ratings
Stresses above those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of
the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and reliability data, see the Quality and Reliability Monitor Report at http://www.silabs.com/support/quality/pages/default.aspx.
Table 4.1. Absolute Maximum Ratings
Parameter
Symbol
Storage temperature range
Test Condition
Min
Typ
Max
Unit
TSTG
-50
—
150
°C
Voltage on supply pins other
than VREGI and VBUS
VDDMAX
-0.3
—
3.8
V
Voltage ramp rate on any
supply pin
VDDRAMPMAX
—
—
1
V / µs
DC voltage on any GPIO pin
VDIGPIN
5V tolerant GPIO pins1 2 3
-0.3
—
Min of 5.25
and IOVDD
+2
V
LCD pins3
-0.3
—
Min of 3.8
and IOVDD
+2
V
Standard GPIO pins
-0.3
—
IOVDD+0.3
V
Total current into VDD power IVDDMAX
lines
Source
—
—
200
mA
Total current into VSS
ground lines
IVSSMAX
Sink
—
—
200
mA
Current per I/O pin
IIOMAX
Sink
—
—
50
mA
Source
—
—
50
mA
Sink
—
—
200
mA
Source
—
—
200
mA
-G grade devices
-40
—
105
°C
-I grade devices
-40
—
125
°C
-0.3
—
5.5
V
Current for all I/O pins
Junction temperature
Voltage on regulator supply
pins VREGI and VBUS
IIOALLMAX
TJ
VVREGI
Note:
1. When a GPIO pin is routed to the analog block through the APORT, the maximum voltage = IOVDD.
2. Valid for IOVDD in valid operating range or when IOVDD is undriven (high-Z). If IOVDD is connected to a low-impedance source
below the valid operating range (e.g. IOVDD shorted to VSS), the pin voltage maximum is IOVDD + 0.3 V, to avoid exceeding the
maximum IO current specifications.
3. To operate above the IOVDD supply rail, over-voltage tolerance must be enabled according to the GPIO_Px_OVTDIS register.
Pins with over-voltage tolerance disabled have the same limits as Standard GPIO.
silabs.com | Building a more connected world.
Rev. 1.0 | 24
EFM32GG12 Family Data Sheet
Electrical Specifications
4.1.2 Operating Conditions
When assigning supply sources, the following requirements must be observed:
• VREGVDD must be greater than or equal to AVDD, DVDD and all IOVDD supplies.
• VREGVDD = AVDD
• DVDD ≤ AVDD
• IOVDD ≤ AVDD
silabs.com | Building a more connected world.
Rev. 1.0 | 25
EFM32GG12 Family Data Sheet
Electrical Specifications
4.1.2.1 General Operating Conditions
Table 4.2. General Operating Conditions
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Operating ambient temperature range1
TA
-G temperature grade
-40
25
85
°C
-I temperature grade
-40
25
125
°C
AVDD supply voltage2
VAVDD
1.8
3.3
3.8
V
VREGVDD operating supply
voltage2 3
VVREGVDD
DCDC in regulation
2.4
3.3
3.8
V
DCDC in bypass, 50mA load
1.8
3.3
3.8
V
DCDC not in use. DVDD externally shorted to VREGVDD
1.8
3.3
3.8
V
DCDC in bypass, T ≤ 85 °C
—
—
200
mA
DCDC in bypass, T > 85 °C
—
—
100
mA
1.62
—
VVREGVDD
V
1.62
—
VVREGVDD
V
0.75
1.0
2.75
µF
VSCALE2, MODE = WS3
—
—
72
MHz
VSCALE2, MODE = WS2
—
—
54
MHz
VSCALE2, MODE = WS1
—
—
36
MHz
VSCALE2, MODE = WS0
—
—
18
MHz
VSCALE0, MODE = WS2
—
—
20
MHz
VSCALE0, MODE = WS1
—
—
14
MHz
VSCALE0, MODE = WS0
—
—
7
MHz
VSCALE2
—
—
72
MHz
VSCALE0
—
—
20
MHz
VSCALE2
—
—
72
MHz
VSCALE0
—
—
20
MHz
VSCALE2
—
—
50
MHz
VSCALE0
—
—
20
MHz
VSCALE2
—
—
50
MHz
VSCALE0
—
—
20
MHz
VSCALE2
—
—
72
MHz
VSCALE0
—
—
20
MHz
VSCALE2
—
—
50
MHz
VSCALE0
—
—
20
MHz
VREGVDD current
DVDD operating supply voltage
IVREGVDD
VDVDD
IOVDD operating supply volt- VIOVDD
age
DECOUPLE output capacitor5 6
CDECOUPLE
HFCORECLK frequency
fCORE
HFCLK frequency
HFSRCCLK frequency
HFBUSCLK frequency
HFPERCLK frequency
HFPERBCLK frequency
HFPERCCLK frequency
fHFCLK
fHFSRCCLK
fHFBUSCLK
fHFPERCLK
fHFPERBCLK
fHFPERCCLK
silabs.com | Building a more connected world.
All IOVDD pins4
Rev. 1.0 | 26
EFM32GG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Note:
1. The maximum limit on TA may be lower due to device self-heating, which depends on the power dissipation of the specific application. TA (max) = TJ (max) - (THETAJA x PowerDissipation). Refer to the Absolute Maximum Ratings table and the Thermal
Characteristics table for TJ and THETAJA.
2. VREGVDD must be tied to AVDD. Both VREGVDD and AVDD minimum voltages must be satisfied for the part to operate.
3. The minimum voltage required in bypass mode is calculated using RBYP from the DCDC specification table. Requirements for
other loads can be calculated as VDVDD_min+ILOAD * RBYP_max.
4. When the CSEN peripheral is used with chopping enabled (CSEN_CTRL_CHOPEN = ENABLE), IOVDD must be equal to AVDD.
5. The system designer should consult the characteristic specs of the capacitor used on DECOUPLE to ensure its capacitance value stays within the specified bounds across temperature and DC bias.
6. VSCALE0 to VSCALE2 voltage change transitions occur at a rate of 10 mV / usec for approximately 20 usec. During this transition, peak currents will be dependent on the value of the DECOUPLE output capacitor, from 35 mA (with a 1 µF capacitor) to 70
mA (with a 2.7 µF capacitor).
4.1.3 Thermal Characteristics
Table 4.3. Thermal Characteristics
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Thermal resistance, QFN64
Package
THETAJA_QFN64 4-Layer PCB, Air velocity = 0 m/s
—
17.8
—
°C/W
4-Layer PCB, Air velocity = 1 m/s
—
15.4
—
°C/W
4-Layer PCB, Air velocity = 2 m/s
—
13.8
—
°C/W
4-Layer PCB, Air velocity = 0 m/s
—
33.9
—
°C/W
4-Layer PCB, Air velocity = 1 m/s
—
32.1
—
°C/W
4-Layer PCB, Air velocity = 2 m/s
—
30.1
—
°C/W
4-Layer PCB, Air velocity = 0 m/s
—
44.1
—
°C/W
4-Layer PCB, Air velocity = 1 m/s
—
37.7
—
°C/W
4-Layer PCB, Air velocity = 2 m/s
—
35.5
—
°C/W
4-Layer PCB, Air velocity = 0 m/s
—
42.0
—
°C/W
4-Layer PCB, Air velocity = 1 m/s
—
37.0
—
°C/W
4-Layer PCB, Air velocity = 2 m/s
—
35.3
—
°C/W
4-Layer PCB, Air velocity = 0 m/s
—
47.9
—
°C/W
4-Layer PCB, Air velocity = 1 m/s
—
41.8
—
°C/W
4-Layer PCB, Air velocity = 2 m/s
—
39.6
—
°C/W
Thermal resistance, TQFP64 THEPackage
TAJA_TQFP64
Thermal resistance,
TQFP100 Package
THETAJA_TQFP100
Thermal resistance, BGA112 THEPackage
TAJA_BGA112
Thermal resistance, BGA120 THEPackage
TAJA_BGA120
silabs.com | Building a more connected world.
Rev. 1.0 | 27
EFM32GG12 Family Data Sheet
Electrical Specifications
4.1.4 DC-DC Converter
Test conditions: L_DCDC=4.7 µH (Murata LQH3NPN4R7MM0L), C_DCDC=4.7 µF (Samsung CL10B475KQ8NQNC), V_DCDC_I=3.3
V, V_DCDC_O=1.8 V, I_DCDC_LOAD=50 mA, Heavy Drive configuration, F_DCDC_LN=7 MHz, unless otherwise indicated.
Table 4.4. DC-DC Converter
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Input voltage range
VDCDC_I
Bypass mode, IDCDC_LOAD = 50
mA
1.8
—
VVREGVDD_
V
Low noise (LN) mode, 1.8 V output, IDCDC_LOAD = 100 mA, or
Low power (LP) mode, 1.8 V output, IDCDC_LOAD = 10 mA
2.4
Low noise (LN) mode, 1.8 V output, IDCDC_LOAD = 200 mA
2.6
Output voltage programmable range1
VDCDC_O
Regulation DC accuracy
ACCDC
Regulation window2
WINREG
Steady-state output ripple
VR
Output voltage under/overshoot
VOV
MAX
—
VVREGVDD_
V
MAX
—
VVREGVDD_
V
MAX
1.8
—
VVREGVDD
V
Low Noise (LN) mode, 1.8 V target output
1.7
—
1.9
V
Low Power (LP) mode,
LPCMPBIASEMxx3 = 0, 1.8 V target output, IDCDC_LOAD ≤ 75 µA
1.63
—
2.2
V
Low Power (LP) mode,
LPCMPBIASEMxx3 = 3, 1.8 V target output, IDCDC_LOAD ≤ 10 mA
1.63
—
2.1
V
—
3
—
mVpp
CCM Mode (LNFORCECCM3 =
1), Load changes between 0 mA
and 100 mA
—
25
60
mV
DCM Mode (LNFORCECCM3 =
0), Load changes between 0 mA
and 10 mA
—
45
90
mV
Overshoot during LP to LN
CCM/DCM mode transitions compared to DC level in LN mode
—
200
—
mV
Undershoot during BYP/LP to LN
CCM (LNFORCECCM3 = 1) mode
transitions compared to DC level
in LN mode
—
40
—
mV
Undershoot during BYP/LP to LN
DCM (LNFORCECCM3 = 0) mode
transitions compared to DC level
in LN mode
—
100
—
mV
DC line regulation
VREG
Input changes between
VVREGVDD_MAX and 2.4 V
—
0.1
—
%
DC load regulation
IREG
Load changes between 0 mA and
100 mA in CCM mode
—
0.1
—
%
silabs.com | Building a more connected world.
Rev. 1.0 | 28
EFM32GG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Max load current
ILOAD_MAX
Low noise (LN) mode, Heavy
Drive4, T ≤ 85 °C
—
—
200
mA
Low noise (LN) mode, Heavy
Drive4, T > 85 °C
—
—
100
mA
Low noise (LN) mode, Medium
Drive4
—
—
100
mA
Low noise (LN) mode, Light
Drive4
—
—
50
mA
Low power (LP) mode,
LPCMPBIASEMxx3 = 0
—
—
75
µA
Low power (LP) mode,
LPCMPBIASEMxx3 = 3
—
—
10
mA
CDCDC
25% tolerance
1
4.7
4.7
µF
DCDC nominal output induc- LDCDC
tor
20% tolerance
4.7
4.7
4.7
µH
—
1.2
2.5
Ω
DCDC nominal output capacitor5
Resistance in Bypass mode
RBYP
Note:
1. Due to internal dropout, the DC-DC output will never be able to reach its input voltage, VVREGVDD.
2. LP mode controller is a hysteretic controller that maintains the output voltage within the specified limits.
3. LPCMPBIASEMxx refers to either LPCMPBIASEM234H in the EMU_DCDCMISCCTRL register or LPCMPBIASEM01 in the
EMU_DCDCLOEM01CFG register, depending on the energy mode.
4. Drive levels are defined by configuration of the PFETCNT and NFETCNT registers. Light Drive: PFETCNT=NFETCNT=3; Medium Drive: PFETCNT=NFETCNT=7; Heavy Drive: PFETCNT=NFETCNT=15.
5. Output voltage under/over-shoot and regulation are specified with CDCDC 4.7 µF. Different settings for DCDCLNCOMPCTRL
must be used if CDCDC is lower than 4.7 µF. See Application Note AN0948 for details.
silabs.com | Building a more connected world.
Rev. 1.0 | 29
EFM32GG12 Family Data Sheet
Electrical Specifications
4.1.5 5V Regulator
VVREGI = 5 V, VVREGO = 3.3 V, CVREGI = 10 µF, CVREGO = 4.7 µF, unless otherwise specified.
Table 4.5. 5V Regulator
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
VREGI or VBUS input voltage range
VVREGI
Regulating output
2.7
—
5.5
V
Bypass mode enabled
2.7
—
3.8
V
VREGO output voltage
VVREGO
Regulating output, 3.3 V setting1
3.1
3.3
3.5
V
EM4S open-loop output, IOUT <
100 µA
1.8
—
3.8
V
—
0.1
—
V
Voltage output step size
VVREGO_SS
Resistance in Bypass Mode
RBYP
Bypass mode enabled
—
1.2
2.5
Ω
Output current
IOUT
EM0 or EM1, VVREGI > VVREGO +
0.6 V
—
—
200
mA
EM0 or EM1, VVREGI > VVREGO +
0.3 V
—
—
100
mA
EM2, EM3, or EM4H, VVREGI >
VVREGO + 0.6 V
—
—
2
mA
EM2, EM3, or EM4H, VVREGI >
VVREGO + 0.3 V
—
—
0.5
mA
EM4S
—
—
20
µA
EM0 or EM1
—
0.10
—
mV/mA
EM2, EM3, or EM4H
—
2.5
—
mV/mA
Load regulation
LRVREGO
DC power supply rejection
PSRDC
—
40
—
dB
VREGI or VBUS bypass capacitance
CVREGI
—
10
—
µF
1
4.7
10
µF
EM0 or EM1, No load
—
29
—
µA
EM2, EM3, or EM4H, No load
—
270
—
nA
EM4S, No load
—
70
—
nA
VREGO bypass capacitance CVREGO
Supply current consumption
IVREGI
VREGI and VBUS detection
high threshold
VDET_H
0.9
1.15
—
V
VREGI and VBUS detection
low threshold
VDET_L
—
1.07
1.45
V
—
0.35
—
mA/mV
Current monitor transfer ratio IMONXF
Translation of current through
VREGO path to voltage at ADC
input
Note:
1. Output may be disturbed during DCDC mode transitions from BYPASS or OFF mode to LOWNOISE mode. Perturbation on VREGO can temporarily bring VREGO up beyond 3.5 V during these DCDC mode transitions. Refer to the EFM32GG12 Errata document, item EMU_E219 for more details.
silabs.com | Building a more connected world.
Rev. 1.0 | 30
EFM32GG12 Family Data Sheet
Electrical Specifications
4.1.6 Backup Supply Domain
Table 4.6. Backup Supply Domain
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
1.8
—
3.8
V
EMU_BUCTRL_PWRRES =
RES0
3400
3900
4400
Ω
EMU_BUCTRL_PWRRES =
RES1
1450
1800
2150
Ω
EMU_BUCTRL_PWRRES =
RES2
1000
1350
1700
Ω
EMU_BUCTRL_PWRRES =
RES3
525
815
1100
Ω
EMU_BUCTRL_VOUTRES =
STRONG
35
110
185
Ω
EMU_BUCTRL_VOUTRES =
MED
475
775
1075
Ω
EMU_BUCTRL_VOUTRES =
WEAK
5600
6500
7400
Ω
BU_VIN not powering backup domain, 25 °C
—
11
70
nA
BU_VIN powering backup domain, 25 °C 2
—
550
2500
nA
Backup supply voltage range VBU_VIN
PWRRES resistor
Output impedance between
BU_VIN and BU_VOUT 1
Supply current
RPWRRES
RBU_VOUT
IBU_VIN
Note:
1. BU_VOUT and BU_STAT signals are not available in all package configurations. Check the device pinout for availability.
2. Additional current required by backup circuitry when backup is active. Includes supply current of backup switches and backup
regulator. Does not include supply current required for backed-up circuitry.
silabs.com | Building a more connected world.
Rev. 1.0 | 31
EFM32GG12 Family Data Sheet
Electrical Specifications
4.1.7 Current Consumption
4.1.7.1 Current Consumption 3.3 V without DC-DC Converter
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = 3.3 V. T = 25 °C. DCDC is off. Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 °C.
Table 4.7. Current Consumption 3.3 V without DC-DC Converter
Parameter
Symbol
Min
Typ
Max
Unit
72 MHz HFRCO, CPU running
Prime from flash
—
113
—
µA/MHz
72 MHz HFRCO, CPU running
while loop from flash
—
112
125
µA/MHz
72 MHz HFRCO, CPU running
CoreMark loop from flash
—
128
—
µA/MHz
50 MHz crystal, CPU running
while loop from flash
—
110
—
µA/MHz
48 MHz HFRCO, CPU running
while loop from flash
—
113
130
µA/MHz
32 MHz HFRCO, CPU running
while loop from flash
—
115
—
µA/MHz
26 MHz HFRCO, CPU running
while loop from flash
—
116
135
µA/MHz
16 MHz HFRCO, CPU running
while loop from flash
—
122
—
µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
—
308
400
µA/MHz
Current consumption in EM0 IACTIVE_VS
mode with all peripherals disabled and voltage scaling
enabled
19 MHz HFRCO, CPU running
while loop from flash
—
99
—
µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
—
255
—
µA/MHz
Current consumption in EM1 IEM1
mode with all peripherals disabled
72 MHz HFRCO
—
51
57
µA/MHz
50 MHz crystal
—
49
—
µA/MHz
48 MHz HFRCO
—
51
60
µA/MHz
32 MHz HFRCO
—
54
—
µA/MHz
26 MHz HFRCO
—
55
64
µA/MHz
16 MHz HFRCO
—
60
—
µA/MHz
1 MHz HFRCO
—
246
350
µA/MHz
19 MHz HFRCO
—
49
—
µA/MHz
1 MHz HFRCO
—
204
—
µA/MHz
Current consumption in EM0 IACTIVE
mode with all peripherals disabled
Current consumption in EM1 IEM1_VS
mode with all peripherals disabled and voltage scaling
enabled
silabs.com | Building a more connected world.
Test Condition
Rev. 1.0 | 32
EFM32GG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Min
Typ
Max
Unit
Full 192 kB RAM retention and
RTCC running from LFXO
—
3.0
—
µA
Full 192 kB RAM retention and
RTCC running from LFRCO
—
3.4
—
µA
16 kB (1 bank) RAM retention and
RTCC running from LFRCO1
—
2.4
4.7
µA
Current consumption in EM3 IEM3_VS
mode, with voltage scaling
enabled
Full 192 kB RAM retention and
CRYOTIMER running from ULFRCO
—
2.7
7
µA
Current consumption in
EM4H mode, with voltage
scaling enabled
128 byte RAM retention, RTCC
running from LFXO
—
0.94
—
µA
128 byte RAM retention, CRYOTIMER running from ULFRCO
—
0.59
—
µA
128 byte RAM retention, no RTCC
—
0.59
1.15
µA
Current consumption in EM2 IEM2_VS
mode, with voltage scaling
enabled
IEM4H_VS
Test Condition
Current consumption in
EM4S mode
IEM4S
No RAM retention, no RTCC
—
0.08
0.16
µA
Current consumption of peripheral power domain 1,
with voltage scaling enabled
IPD1_VS
Additional current consumption in
EM2/3 when any peripherals on
power domain 1 are enabled2
—
0.73
—
µA
Current consumption of peripheral power domain 2,
with voltage scaling enabled
IPD2_VS
Additional current consumption in
EM2/3 when any peripherals on
power domain 2 are enabled2
—
0.32
—
µA
Note:
1. CMU_LFRCOCTRL_ENVREF = 1, CMU_LFRCOCTRL_VREFUPDATE = 1
2. Extra current consumed by power domain. Does not include current associated with the enabled peripherals. See 3.2.4 EM2 and
EM3 Power Domains for a list of the peripherals in each power domain.
silabs.com | Building a more connected world.
Rev. 1.0 | 33
EFM32GG12 Family Data Sheet
Electrical Specifications
4.1.7.2 Current Consumption 3.3 V using DC-DC Converter
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = 1.8 V DC-DC output. T = 25 °C.
Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 °C.
Table 4.8. Current Consumption 3.3 V using DC-DC Converter
Parameter
Symbol
Current consumption in EM0 IACTIVE_DCM
mode with all peripherals disabled, DCDC in Low Noise
DCM mode1
Current consumption in EM0 IACTIVE_CCM
mode with all peripherals disabled, DCDC in Low Noise
CCM mode2
silabs.com | Building a more connected world.
Test Condition
Min
Typ
Max
Unit
72 MHz HFRCO, CPU running
Prime from flash
—
76
—
µA/MHz
72 MHz HFRCO, CPU running
while loop from flash
—
75
—
µA/MHz
72 MHz HFRCO, CPU running
CoreMark loop from flash
—
85
—
µA/MHz
50 MHz crystal, CPU running
while loop from flash
—
76
—
µA/MHz
48 MHz HFRCO, CPU running
while loop from flash
—
78
—
µA/MHz
32 MHz HFRCO, CPU running
while loop from flash
—
85
—
µA/MHz
26 MHz HFRCO, CPU running
while loop from flash
—
89
—
µA/MHz
16 MHz HFRCO, CPU running
while loop from flash
—
104
—
µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
—
686
—
µA/MHz
72 MHz HFRCO, CPU running
Prime from flash
—
80
—
µA/MHz
72 MHz HFRCO, CPU running
while loop from flash
—
79
—
µA/MHz
72 MHz HFRCO, CPU running
CoreMark loop from flash
—
89
—
µA/MHz
50 MHz crystal, CPU running
while loop from flash
—
84
—
µA/MHz
48 MHz HFRCO, CPU running
while loop from flash
—
87
—
µA/MHz
32 MHz HFRCO, CPU running
while loop from flash
—
100
—
µA/MHz
26 MHz HFRCO, CPU running
while loop from flash
—
109
—
µA/MHz
16 MHz HFRCO, CPU running
while loop from flash
—
139
—
µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
—
1290
—
µA/MHz
Rev. 1.0 | 34
EFM32GG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Min
Typ
Max
Unit
32 MHz HFRCO, CPU running
while loop from flash
—
76
—
µA/MHz
26 MHz HFRCO, CPU running
while loop from flash
—
77
—
µA/MHz
16 MHz HFRCO, CPU running
while loop from flash
—
82
—
µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
—
257
—
µA/MHz
Current consumption in EM0 IACTIVE_CCM_VS
mode with all peripherals disabled and voltage scaling
enabled, DCDC in Low
Noise CCM mode2
19 MHz HFRCO, CPU running
while loop from flash
—
115
—
µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
—
1259
—
µA/MHz
Current consumption in EM0 IACTIVE_LPM_VS
mode with all peripherals disabled and voltage scaling
enabled, DCDC in LP mode3
19 MHz HFRCO, CPU running
while loop from flash
—
67
—
µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
—
214
—
µA/MHz
Current consumption in EM1 IEM1_DCM
mode with all peripherals disabled, DCDC in Low Noise
DCM mode1
72 MHz HFRCO
—
38
—
µA/MHz
50 MHz crystal
—
39
—
µA/MHz
48 MHz HFRCO
—
42
—
µA/MHz
32 MHz HFRCO
—
48
—
µA/MHz
26 MHz HFRCO
—
53
—
µA/MHz
16 MHz HFRCO
—
68
—
µA/MHz
1 MHz HFRCO
—
652
—
µA/MHz
32 MHz HFRCO
—
37
—
µA/MHz
26 MHz HFRCO
—
39
—
µA/MHz
16 MHz HFRCO
—
43
—
µA/MHz
1 MHz HFRCO
—
209
—
µA/MHz
Current consumption in EM1 IEM1_DCM_VS
mode with all peripherals disabled and voltage scaling
enabled, DCDC in Low
Noise DCM mode1
19 MHz HFRCO
—
56
—
µA/MHz
1 MHz HFRCO
—
627
—
µA/MHz
Current consumption in EM1 IEM1_LPM_VS
mode with all peripherals disabled and voltage scaling
enabled. DCDC in LP mode3
19 MHz HFRCO
—
35
—
µA/MHz
1 MHz HFRCO
—
185
—
µA/MHz
Current consumption in EM2 IEM2_VS
mode, with voltage scaling
enabled, DCDC in LP mode3
Full 192 kB RAM retention and
RTCC running from LFXO
—
2.2
—
µA
Full 192 kB RAM retention and
RTCC running from LFRCO
—
2.5
—
µA
16 kB (1 bank) RAM retention and
RTCC running from LFRCO4
—
1.8
—
µA
Full 192 kB RAM retention and
CRYOTIMER running from ULFRCO
—
1.9
—
µA
Current consumption in EM0 IACTIVE_LPM
mode with all peripherals disabled, DCDC in LP mode3
Current consumption in EM1 IEM1_LPM
mode with all peripherals disabled, DCDC in Low Power
mode3
Current consumption in EM3 IEM3_VS
mode, with voltage scaling
enabled
silabs.com | Building a more connected world.
Test Condition
Rev. 1.0 | 35
EFM32GG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current consumption in
EM4H mode, with voltage
scaling enabled
IEM4H_VS
128 byte RAM retention, RTCC
running from LFXO
—
0.86
—
µA
128 byte RAM retention, CRYOTIMER running from ULFRCO
—
0.55
—
µA
128 byte RAM retention, no RTCC
—
0.55
—
µA
No RAM retention, no RTCC
—
0.08
—
µA
Current consumption of peIPD1_VS
ripheral power domain 1,
with voltage scaling enabled,
DCDC in LP mode3
Additional current consumption in
EM2/3 when any peripherals on
power domain 1 are enabled5
—
0.76
—
µA
Current consumption of peIPD2_VS
ripheral power domain 2,
with voltage scaling enabled,
DCDC in LP mode3
Additional current consumption in
EM2/3 when any peripherals on
power domain 2 are enabled5
—
0.32
—
µA
Current consumption in
EM4S mode
IEM4S
Note:
1. DCDC Low Noise DCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=3.0 MHz (RCOBAND=0), ANASW=DVDD.
2. DCDC Low Noise CCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=6.4 MHz (RCOBAND=4), ANASW=DVDD.
3. DCDC Low Power Mode = Medium Drive, LPOSCDIV=1, LPCMPBIASEM234H=0, LPCLIMILIMSEL=1, ANASW=DVDD.
4. CMU_LFRCOCTRL_ENVREF = 1, CMU_LFRCOCTRL_VREFUPDATE = 1
5. Extra current consumed by power domain. Does not include current associated with the enabled peripherals. See 3.2.4 EM2 and
EM3 Power Domains for a list of the peripherals in each power domain.
silabs.com | Building a more connected world.
Rev. 1.0 | 36
EFM32GG12 Family Data Sheet
Electrical Specifications
4.1.7.3 Current Consumption 1.8 V without DC-DC Converter
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = 1.8 V. T = 25 °C. DCDC is off. Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 °C.
Table 4.9. Current Consumption 1.8 V without DC-DC Converter
Parameter
Symbol
Min
Typ
Max
Unit
72 MHz HFRCO, CPU running
Prime from flash
—
113
—
µA/MHz
72 MHz HFRCO, CPU running
while loop from flash
—
112
—
µA/MHz
72 MHz HFRCO, CPU running
CoreMark loop from flash
—
128
—
µA/MHz
50 MHz crystal, CPU running
while loop from flash
—
110
—
µA/MHz
48 MHz HFRCO, CPU running
while loop from flash
—
112
—
µA/MHz
32 MHz HFRCO, CPU running
while loop from flash
—
115
—
µA/MHz
26 MHz HFRCO, CPU running
while loop from flash
—
116
—
µA/MHz
16 MHz HFRCO, CPU running
while loop from flash
—
122
—
µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
—
304
—
µA/MHz
Current consumption in EM0 IACTIVE_VS
mode with all peripherals disabled and voltage scaling
enabled
19 MHz HFRCO, CPU running
while loop from flash
—
99
—
µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
—
251
—
µA/MHz
Current consumption in EM1 IEM1
mode with all peripherals disabled
72 MHz HFRCO
—
51
—
µA/MHz
50 MHz crystal
—
49
—
µA/MHz
48 MHz HFRCO
—
51
—
µA/MHz
32 MHz HFRCO
—
53
—
µA/MHz
26 MHz HFRCO
—
55
—
µA/MHz
16 MHz HFRCO
—
60
—
µA/MHz
1 MHz HFRCO
—
242
—
µA/MHz
Current consumption in EM1 IEM1_VS
mode with all peripherals disabled and voltage scaling
enabled
19 MHz HFRCO
—
49
—
µA/MHz
1 MHz HFRCO
—
201
—
µA/MHz
Current consumption in EM2 IEM2_VS
mode, with voltage scaling
enabled
Full 192 kB RAM retention and
RTCC running from LFXO
—
2.9
—
µA
Full 192 kB RAM retention and
RTCC running from LFRCO
—
3.1
—
µA
16 kB (1 bank) RAM retention and
RTCC running from LFRCO1
—
2.1
—
µA
Current consumption in EM0 IACTIVE
mode with all peripherals disabled
silabs.com | Building a more connected world.
Test Condition
Rev. 1.0 | 37
EFM32GG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current consumption in EM3 IEM3_VS
mode, with voltage scaling
enabled
Full 192 kB RAM retention and
CRYOTIMER running from ULFRCO
—
2.6
—
µA
Current consumption in
EM4H mode, with voltage
scaling enabled
128 byte RAM retention, RTCC
running from LFXO
—
0.85
—
µA
128 byte RAM retention, CRYOTIMER running from ULFRCO
—
0.48
—
µA
128 byte RAM retention, no RTCC
—
0.48
—
µA
IEM4H_VS
Current consumption in
EM4S mode
IEM4S
No RAM retention, no RTCC
—
0.06
—
µA
Current consumption of peripheral power domain 1,
with voltage scaling enabled
IPD1_VS
Additional current consumption in
EM2/3 when any peripherals on
power domain 1 are enabled2
—
0.75
—
µA
Current consumption of peripheral power domain 2,
with voltage scaling enabled
IPD2_VS
Additional current consumption in
EM2/3 when any peripherals on
power domain 2 are enabled2
—
0.32
—
µA
Note:
1. CMU_LFRCOCTRL_ENVREF = 1, CMU_LFRCOCTRL_VREFUPDATE = 1
2. Extra current consumed by power domain. Does not include current associated with the enabled peripherals. See 3.2.4 EM2 and
EM3 Power Domains for a list of the peripherals in each power domain.
silabs.com | Building a more connected world.
Rev. 1.0 | 38
EFM32GG12 Family Data Sheet
Electrical Specifications
4.1.8 Wake Up Times
Table 4.10. Wake Up Times
Parameter
Symbol
Wake up time from EM1
tEM1_WU
Wake up from EM2
tEM2_WU
Wake up from EM3
tEM3_WU
Test Condition
Min
Typ
Max
Unit
—
3
—
AHB
Clocks
Code execution from flash
—
11.4
—
µs
Code execution from RAM
—
3.8
—
µs
Code execution from flash
—
11.4
—
µs
Code execution from RAM
—
3.8
—
µs
Wake up from EM4H1
tEM4H_WU
Executing from flash
—
92
—
µs
Wake up from EM4S1
tEM4S_WU
Executing from flash
—
288
—
µs
Time from release of reset
source to first instruction execution
tRESET
Soft Pin Reset released
—
53
—
µs
Any other reset released
—
347
—
µs
Power mode scaling time
tSCALE
VSCALE0 to VSCALE2, HFCLK =
19 MHz2 3
—
31.8
—
µs
VSCALE2 to VSCALE0, HFCLK =
19 MHz4
—
4.3
—
µs
Note:
1. Time from wake up request until first instruction is executed. Wakeup results in device reset.
2. Scaling up from VSCALE0 to VSCALE2 requires approximately 30.3 µs + 28 HFCLKs.
3. VSCALE0 to VSCALE2 voltage change transitions occur at a rate of 10 mV/µs for approximately 20 µs. During this transition,
peak currents will be dependent on the value of the DECOUPLE output capacitor, from 35 mA (with a 1 µF capacitor) to 70 mA
(with a 2.7 µF capacitor).
4. Scaling down from VSCALE2 to VSCALE0 requires approximately 2.8 µs + 29 HFCLKs.
silabs.com | Building a more connected world.
Rev. 1.0 | 39
EFM32GG12 Family Data Sheet
Electrical Specifications
4.1.9 Brown Out Detector (BOD)
Table 4.11. Brown Out Detector (BOD)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
DVDD BOD threshold
VDVDDBOD
DVDD rising
—
—
1.62
V
DVDD falling (EM0/EM1)
1.35
—
—
V
DVDD falling (EM2/EM3)
1.3
—
—
V
DVDD BOD hysteresis
VDVDDBOD_HYST
—
18
—
mV
DVDD BOD response time
tDVDDBOD_DELAY Supply drops at 0.1V/µs rate
—
2.4
—
µs
AVDD BOD threshold
VAVDDBOD
—
—
1.8
V
AVDD falling (EM0/EM1)
1.62
—
—
V
AVDD falling (EM2/EM3)
1.53
—
—
V
AVDD rising
AVDD BOD hysteresis
VAVDDBOD_HYST
—
20
—
mV
AVDD BOD response time
tAVDDBOD_DELAY Supply drops at 0.1V/µs rate
—
2.4
—
µs
EM4 BOD threshold
VEM4DBOD
AVDD rising
—
—
1.7
V
AVDD falling
1.45
—
—
V
—
25
—
mV
—
300
—
µs
EM4 BOD hysteresis
VEM4BOD_HYST
EM4 BOD response time
tEM4BOD_DELAY
silabs.com | Building a more connected world.
Supply drops at 0.1V/µs rate
Rev. 1.0 | 40
EFM32GG12 Family Data Sheet
Electrical Specifications
4.1.10 Oscillators
4.1.10.1 Low-Frequency Crystal Oscillator (LFXO)
Table 4.12. Low-Frequency Crystal Oscillator (LFXO)
Parameter
Symbol
Crystal frequency
Test Condition
Min
Typ
Max
Unit
fLFXO
—
32.768
—
kHz
Supported crystal equivalent
series resistance (ESR)
ESRLFXO
—
—
70
kΩ
Supported range of crystal
load capacitance 1
CLFXO_CL
6
—
18
pF
On-chip tuning cap range 2
CLFXO_T
8
—
40
pF
On-chip tuning cap step size
SSLFXO
—
0.25
—
pF
Current consumption after
startup 3
ILFXO
ESR = 70 kOhm, CL = 7 pF,
GAIN4 = 2, AGC4 = 1
—
273
—
nA
Start- up time
tLFXO
ESR = 70 kOhm, CL = 7 pF,
GAIN4 = 2
—
308
—
ms
On each of LFXTAL_N and
LFXTAL_P pins
Note:
1. Total load capacitance as seen by the crystal.
2. The effective load capacitance seen by the crystal will be CLFXO_T /2. This is because each XTAL pin has a tuning cap and the
two caps will be seen in series by the crystal.
3. Block is supplied by AVDD if ANASW = 0, or DVDD if ANASW=1 in EMU_PWRCTRL register.
4. In CMU_LFXOCTRL register.
silabs.com | Building a more connected world.
Rev. 1.0 | 41
EFM32GG12 Family Data Sheet
Electrical Specifications
4.1.10.2 High-Frequency Crystal Oscillator (HFXO)
Table 4.13. High-Frequency Crystal Oscillator (HFXO)
Parameter
Symbol
Test Condition
Crystal frequency
fHFXO
Supported crystal equivalent
series resistance (ESR)
ESRHFXO
Nominal on-chip tuning cap
range1
CHFXO_T
On-chip tuning capacitance
step
SSHFXO
Startup time
tHFXO
Current consumption after
startup
IHFXO
Min
Typ
Max
Unit
No clock doubling
4
—
50
MHz
Clock doubler enabled
4
—
25
MHz
50 MHz crystal
—
—
50
Ω
24 MHz crystal
—
—
150
Ω
4 MHz crystal
—
—
180
Ω
On each of HFXTAL_N and
HFXTAL_P pins
8.7
—
51.7
pF
—
0.084
—
pF
50 MHz crystal, ESR = 50 Ohm,
CL = 8 pF
—
350
—
µs
24 MHz crystal, ESR = 150 Ohm,
CL = 6 pF
—
700
—
µs
4 MHz crystal, ESR = 180 Ohm,
CL = 18 pF
—
3
—
ms
50 MHz crystal
—
660
—
µA
24 MHz crystal
—
330
—
µA
4 MHz crystal
—
70
—
µA
Note:
1. The effective load capacitance seen by the crystal will be CHFXO_T /2. This is because each XTAL pin has a tuning cap and the
two caps will be seen in series by the crystal.
silabs.com | Building a more connected world.
Rev. 1.0 | 42
EFM32GG12 Family Data Sheet
Electrical Specifications
4.1.10.3 Low-Frequency RC Oscillator (LFRCO)
Table 4.14. Low-Frequency RC Oscillator (LFRCO)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Oscillation frequency
fLFRCO
ENVREF1 = 1, T ≤ 85 °C
31.3
32.768
33.6
kHz
ENVREF1 = 1, T > 85 °C
31
32.768
36.8
kHz
ENVREF1 = 0, T ≤ 85 °C
31.3
32.768
33.4
kHz
ENVREF1 = 0, T > 85 °C
30
32.768
33.6
kHz
—
500
—
µs
ENVREF = 1 in
CMU_LFRCOCTRL
—
370
—
nA
ENVREF = 0 in
CMU_LFRCOCTRL
—
520
—
nA
Startup time
tLFRCO
Current consumption 2
ILFRCO
Note:
1. In CMU_LFRCOCTRL register.
2. Block is supplied by AVDD if ANASW = 0, or DVDD if ANASW=1 in EMU_PWRCTRL register.
silabs.com | Building a more connected world.
Rev. 1.0 | 43
EFM32GG12 Family Data Sheet
Electrical Specifications
4.1.10.4 High-Frequency RC Oscillator (HFRCO)
Table 4.15. High-Frequency RC Oscillator (HFRCO)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Frequency accuracy
fHFRCO_ACC
At production calibrated frequencies, across supply voltage and
temperature
-2.5
—
2.5
%
Start-up time
tHFRCO
fHFRCO ≥ 19 MHz
—
300
—
ns
4 < fHFRCO < 19 MHz
—
1
—
µs
fHFRCO ≤ 4 MHz
—
2.5
—
µs
Maximum DPLL lock time1
tDPLL_LOCK
fREF = 32.768 kHz, fHFRCO =
39.98 MHz, N = 1219, M = 0
—
183
—
µs
Current consumption on all
supplies
IHFRCO
fHFRCO = 72 MHz
—
550
600
µA
fHFRCO = 64 MHz
—
500
550
µA
fHFRCO = 56 MHz
—
430
475
µA
fHFRCO = 48 MHz
—
380
410
µA
fHFRCO = 38 MHz
—
310
340
µA
fHFRCO = 32 MHz
—
265
280
µA
fHFRCO = 26 MHz
—
220
235
µA
fHFRCO = 19 MHz
—
180
190
µA
fHFRCO = 16 MHz
—
150
160
µA
fHFRCO = 13 MHz
—
135
140
µA
fHFRCO = 7 MHz
—
98
102
µA
fHFRCO = 4 MHz
—
38
42
µA
fHFRCO = 2 MHz
—
32
35
µA
fHFRCO = 1 MHz
—
28
30
µA
fHFRCO = 72 MHz, DPLL enabled
—
580
650
µA
fHFRCO = 40 MHz, DPLL enabled
—
500
525
µA
fHFRCO = 32 MHz, DPLL enabled
—
400
420
µA
fHFRCO = 16 MHz, DPLL enabled
—
220
235
µA
fHFRCO = 4 MHz, DPLL enabled
—
56
60
µA
fHFRCO = 1 MHz, DPLL enabled
—
35
38
µA
—
0.8
—
%
Coarse trim step size (% of
period)
SSHFRCO_COARS
E
Fine trim step size (% of period)
SSHFRCO_FINE
—
0.1
—
%
Period jitter
PJHFRCO
—
0.2
—
% RMS
silabs.com | Building a more connected world.
Rev. 1.0 | 44
EFM32GG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Frequency limits
fHFRCO_BAND
FREQRANGE = 0, FINETUNINGEN = 0
1
—
10
MHz
FREQRANGE = 3, FINETUNINGEN = 0
2
—
17
MHz
FREQRANGE = 6, FINETUNINGEN = 0
4
—
30
MHz
FREQRANGE = 7, FINETUNINGEN = 0
5
—
34
MHz
FREQRANGE = 8, FINETUNINGEN = 0
7
—
42
MHz
FREQRANGE = 10, FINETUNINGEN = 0
12
—
58
MHz
FREQRANGE = 11, FINETUNINGEN = 0
15
—
68
MHz
FREQRANGE = 12, FINETUNINGEN = 0
18
—
83
MHz
FREQRANGE = 13, FINETUNINGEN = 0
24
—
100
MHz
FREQRANGE = 14, FINETUNINGEN = 0
28
—
119
MHz
FREQRANGE = 15, FINETUNINGEN = 0
33
—
138
MHz
FREQRANGE = 16, FINETUNINGEN = 0
43
—
163
MHz
Note:
1. Maximum DPLL lock time ~= 6 x (M+1) x tREF, where tREF is the reference clock period.
silabs.com | Building a more connected world.
Rev. 1.0 | 45
EFM32GG12 Family Data Sheet
Electrical Specifications
4.1.10.5 Auxiliary High-Frequency RC Oscillator (AUXHFRCO)
Table 4.16. Auxiliary High-Frequency RC Oscillator (AUXHFRCO)
Parameter
Symbol
Test Condition
Frequency accuracy
fAUXHFRCO_ACC
Start-up time
tAUXHFRCO
Current consumption on all
supplies
Coarse trim step size (% of
period)
IAUXHFRCO
SSAUXHFR-
Min
Typ
Max
Unit
At production calibrated frequencies, across supply voltage and
temperature
-3
—
3
%
fAUXHFRCO ≥ 19 MHz
—
400
—
ns
4 < fAUXHFRCO < 19 MHz
—
1.4
—
µs
fAUXHFRCO ≤ 4 MHz
—
2.5
—
µs
fAUXHFRCO = 50 MHz
—
270
285
µA
fAUXHFRCO = 48 MHz
—
255
272
µA
fAUXHFRCO = 38 MHz
—
212
225
µA
fAUXHFRCO = 32 MHz
—
174
185
µA
fAUXHFRCO = 26 MHz
—
148
158
µA
fAUXHFRCO = 19 MHz
—
118
127
µA
fAUXHFRCO = 16 MHz
—
108
116
µA
fAUXHFRCO = 13 MHz
—
88
112
µA
fAUXHFRCO = 7 MHz
—
59
72
µA
fAUXHFRCO = 4 MHz
—
32
36
µA
fAUXHFRCO = 2 MHz
—
27
30
µA
fAUXHFRCO = 1 MHz
—
26
28
µA
—
0.8
—
%
—
0.1
—
%
—
0.2
—
% RMS
CO_COARSE
Fine trim step size (% of period)
SSAUXHFRCO_FINE
Period jitter
PJAUXHFRCO
silabs.com | Building a more connected world.
Rev. 1.0 | 46
EFM32GG12 Family Data Sheet
Electrical Specifications
4.1.10.6 USB High-Frequency RC Oscillator (USHFRCO)
Table 4.17. USB High-Frequency RC Oscillator (USHFRCO)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Frequency accuracy
fUSHFRCO_ACC
At production calibrated frequencies, across supply voltage and
temperature
-2.5
—
2.5
%
USB clock recovery enabled, Active connection as device, FINETUNINGEN1 = 1
-0.25
—
0.25
%
—
300
—
ns
fUSHFRCO = 48 MHz, FINETUNINGEN1 = 1
—
293
305
µA
fUSHFRCO = 50 MHz, FINETUNINGEN1 = 0
—
257
270
µA
fUSHFRCO = 48 MHz, FINETUNINGEN1 = 0
—
249
260
µA
fUSHFRCO = 32 MHz, FINETUNINGEN1 = 0
—
165
176
µA
fUSHFRCO = 16 MHz, FINETUNINGEN1 = 0
—
100
111
µA
—
0.2
—
% RMS
Min
Typ
Max
Unit
0.88
1
1.12
kHz
Start-up time
tUSHFRCO
Current consumption on all
supplies
IUSHFRCO
Period jitter
PJUSHFRCO
Note:
1. In the CMU_USHFRCOCTRL register.
4.1.10.7 Ultra-low Frequency RC Oscillator (ULFRCO)
Table 4.18. Ultra-low Frequency RC Oscillator (ULFRCO)
Parameter
Symbol
Oscillation frequency
fULFRCO
silabs.com | Building a more connected world.
Test Condition
Rev. 1.0 | 47
EFM32GG12 Family Data Sheet
Electrical Specifications
4.1.11 Flash Memory Characteristics1
Table 4.19. Flash Memory Characteristics1
Parameter
Symbol
Flash erase cycles before
failure
ECFLASH
Flash data retention
RETFLASH
Word (32-bit) programming
time
tW_PROG
Test Condition
Min
Typ
Max
Unit
10000
—
—
cycles
T ≤ 85 °C
10
—
—
years
T ≤ 125 °C
10
—
—
years
Burst write, 128 words, average
time per word
20
27
32
µs
Single word
59
68
80
µs
Page erase time2
tPERASE
20
27
35
ms
Mass erase time3
tMERASE
20
27
35
ms
Device erase time4 5
tDERASE
T ≤ 85 °C
—
80
95
ms
T ≤ 125 °C
—
80
100
ms
Page Erase
—
—
1.6
mA
Mass or Device Erase
—
—
1.9
mA
Erase current6
IERASE
Write current6
IWRITE
—
—
3.7
mA
Supply voltage during flash
erase and write
VFLASH
1.62
—
3.6
V
Note:
1. Flash data retention information is published in the Quarterly Quality and Reliability Report.
2. From setting the ERASEPAGE bit in MSC_WRITECMD to 1 until the BUSY bit in MSC_STATUS is cleared to 0. Internal setup
and hold times for flash control signals are included.
3. Mass erase is issued by the CPU and erases all flash.
4. Device erase is issued over the AAP interface and erases all flash, SRAM, the Lock Bit (LB) page, and the User data page Lock
Word (ULW).
5. From setting the DEVICEERASE bit in AAP_CMD to 1 until the ERASEBUSY bit in AAP_STATUS is cleared to 0. Internal setup
and hold times for flash control signals are included.
6. Measured at 25 °C.
silabs.com | Building a more connected world.
Rev. 1.0 | 48
EFM32GG12 Family Data Sheet
Electrical Specifications
4.1.12 General-Purpose I/O (GPIO)
Table 4.20. General-Purpose I/O (GPIO)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Input low voltage1
VIL
GPIO pins
—
—
IOVDD*0.3
V
Input high voltage1
VIH
GPIO pins
IOVDD*0.7
—
—
V
Output high voltage relative
to IOVDD
VOH
Sourcing 3 mA, IOVDD ≥ 3 V,
IOVDD*0.8
—
—
V
IOVDD*0.6
—
—
V
IOVDD*0.8
—
—
V
IOVDD*0.6
—
—
V
—
—
IOVDD*0.2
V
—
—
IOVDD*0.4
V
—
—
IOVDD*0.2
V
—
—
IOVDD*0.4
V
All GPIO except LFXO pins, GPIO
≤ IOVDD, T ≤ 85 °C
—
0.1
40
nA
LFXO Pins, GPIO ≤ IOVDD, T ≤
85 °C
—
0.1
60
nA
All GPIO except LFXO pins, GPIO
≤ IOVDD, T > 85 °C
—
—
150
nA
LFXO Pins, GPIO ≤ IOVDD, T >
85 °C
—
—
300
nA
IOVDD < GPIO ≤ IOVDD + 2 V
—
3.3
15
µA
30
40
65
kΩ
15
25
35
ns
DRIVESTRENGTH2 = WEAK
Sourcing 1.2 mA, IOVDD ≥ 1.62
V,
DRIVESTRENGTH2 = WEAK
Sourcing 20 mA, IOVDD ≥ 3 V,
DRIVESTRENGTH2 = STRONG
Sourcing 8 mA, IOVDD ≥ 1.62 V,
DRIVESTRENGTH2 = STRONG
Output low voltage relative to VOL
IOVDD
Sinking 3 mA, IOVDD ≥ 3 V,
DRIVESTRENGTH2 = WEAK
Sinking 1.2 mA, IOVDD ≥ 1.62 V,
DRIVESTRENGTH2 = WEAK
Sinking 20 mA, IOVDD ≥ 3 V,
DRIVESTRENGTH2 = STRONG
Sinking 8 mA, IOVDD ≥ 1.62 V,
DRIVESTRENGTH2 = STRONG
Input leakage current
IIOLEAK
Input leakage current on
5VTOL pads above IOVDD
I5VTOLLEAK
I/O pin pull-up/pull-down resistor3
RPUD
Pulse width of pulses retIOGLITCH
moved by the glitch suppression filter
silabs.com | Building a more connected world.
Rev. 1.0 | 49
EFM32GG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Output fall time, From 70%
to 30% of VIO
tIOOF
CL = 50 pF,
Min
Typ
Max
Unit
—
1.8
—
ns
—
4.5
—
ns
—
2.2
—
ns
—
7.4
—
ns
—
33 +/-10%
—
Ω
DRIVESTRENGTH2 = STRONG,
SLEWRATE2 = 0x6
CL = 50 pF,
DRIVESTRENGTH2 = WEAK,
SLEWRATE2 = 0x6
Output rise time, From 30%
to 70% of VIO
tIOOR
CL = 50 pF,
DRIVESTRENGTH2 = STRONG,
SLEWRATE = 0x62
CL = 50 pF,
DRIVESTRENGTH2 = WEAK,
SLEWRATE2 = 0x6
Required external series resistor on USB D+ and D-
RUSB
Note:
1. GPIO input threshold are proportional to the IOVDD supply, except for RESETn which is proportional to AVDD (or BU_VIN in
backup mode).
2. In GPIO_Pn_CTRL register.
3. GPIO pull-ups are referenced to the IOVDD supply, except for RESETn, which connects to AVDD (or BU_VIN in backup mode).
silabs.com | Building a more connected world.
Rev. 1.0 | 50
EFM32GG12 Family Data Sheet
Electrical Specifications
4.1.13 Voltage Monitor (VMON)
Table 4.21. Voltage Monitor (VMON)
Parameter
Symbol
Test Condition
Supply current (including
I_SENSE)
IVMON
Loading of monitored supply
ISENSE
Threshold range
VVMON_RANGE
Threshold step size
NVMON_STESP
Response time
tVMON_RES
Hysteresis
VVMON_HYST
silabs.com | Building a more connected world.
Min
Typ
Max
Unit
In EM0 or EM1, 1 active channel,
T ≤ 85 °C
—
6
11
µA
In EM0 or EM1, 1 active channel,
T > 85 °C
—
—
21
µA
In EM0 or EM1, All channels active, T ≤ 85 °C
—
15
20
µA
In EM0 or EM1, All channels active, T > 85 °C
—
—
32
µA
In EM2, EM3 or EM4, 1 channel
active and above threshold
—
62
—
nA
In EM2, EM3 or EM4, 1 channel
active and below threshold
—
62
—
nA
In EM2, EM3 or EM4, All channels
active and above threshold
—
99
—
nA
In EM2, EM3 or EM4, All channels
active and below threshold
—
99
—
nA
In EM0 or EM1
—
2
—
µA
In EM2, EM3 or EM4
—
2
—
nA
1.62
—
3.4
V
Coarse
—
200
—
mV
Fine
—
20
—
mV
Supply drops at 1V/µs rate
—
460
—
ns
—
26
—
mV
Rev. 1.0 | 51
EFM32GG12 Family Data Sheet
Electrical Specifications
4.1.14 Analog to Digital Converter (ADC)
Specified at 1 Msps, ADCCLK = 16 MHz, BIASPROG = 0, GPBIASACC = 0, unless otherwise indicated.
Table 4.22. Analog to Digital Converter (ADC)
Parameter
Symbol
Resolution
VRESOLUTION
Input voltage range1
VADCIN
Test Condition
Single ended
Differential
Input range of external refer- VADCREFIN_P
ence voltage, single ended
and differential
Min
Typ
Max
Unit
6
—
12
Bits
—
—
VFS
V
-VFS/2
—
VFS/2
V
1
—
VAVDD
V
Power supply rejection2
PSRRADC
At DC
—
80
—
dB
Analog input common mode
rejection ratio
CMRRADC
At DC
—
80
—
dB
1 Msps / 16 MHz ADCCLK, BIASPROG = 0, GPBIASACC = 1 4
—
270
350
µA
250 ksps / 4 MHz ADCCLK, BIASPROG = 6, GPBIASACC = 1 4
—
125
—
µA
62.5 ksps / 1 MHz ADCCLK, BIASPROG = 15, GPBIASACC = 1 4
—
80
—
µA
Current from all supplies, us- IADC_NORMAL_LP 35 ksps / 16 MHz ADCCLK, BIAing internal reference buffer.
SPROG = 0, GPBIASACC = 1 4
Duty-cycled operation. WAR5 ksps / 16 MHz ADCCLK BIAMUPMODE3 = NORMAL
SPROG = 0, GPBIASACC = 1 4
—
45
—
µA
—
8
—
µA
Current from all supplies, us- IADC_STANDing internal reference buffer. BY_LP
Duty-cycled operation.
AWARMUPMODE3 = KEEPINSTANDBY or KEEPINSLOWACC
125 ksps / 16 MHz ADCCLK, BIASPROG = 0, GPBIASACC = 1 4
—
105
—
µA
35 ksps / 16 MHz ADCCLK, BIASPROG = 0, GPBIASACC = 1 4
—
70
—
µA
Current from all supplies, us- IADC_CONTINUing internal reference buffer. OUS_HP
Continuous operation. WARMUPMODE3 = KEEPADCWARM
1 Msps / 16 MHz ADCCLK, BIASPROG = 0, GPBIASACC = 0 4
—
325
—
µA
250 ksps / 4 MHz ADCCLK, BIASPROG = 6, GPBIASACC = 0 4
—
175
—
µA
62.5 ksps / 1 MHz ADCCLK, BIASPROG = 15, GPBIASACC = 0 4
—
125
—
µA
Current from all supplies, us- IADC_NORMAL_HP 35 ksps / 16 MHz ADCCLK, BIAing internal reference buffer.
SPROG = 0, GPBIASACC = 0 4
Duty-cycled operation. WAR5 ksps / 16 MHz ADCCLK BIAMUPMODE3 = NORMAL
SPROG = 0, GPBIASACC = 0 4
—
85
—
µA
—
16
—
µA
Current from all supplies, us- IADC_CONTINUing internal reference buffer. OUS_LP
Continuous operation. WARMUPMODE3 = KEEPADCWARM
Current from all supplies, us- IADC_STANDing internal reference buffer. BY_HP
Duty-cycled operation.
AWARMUPMODE3 = KEEPINSTANDBY or KEEPINSLOWACC
125 ksps / 16 MHz ADCCLK, BIASPROG = 0, GPBIASACC = 0 4
—
160
—
µA
35 ksps / 16 MHz ADCCLK, BIASPROG = 0, GPBIASACC = 0 4
—
125
—
µA
Current from HFPERCLK
HFPERCLK = 16 MHz
—
180
—
µA
IADC_CLK
silabs.com | Building a more connected world.
Rev. 1.0 | 52
EFM32GG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
ADC clock frequency
Min
Typ
Max
Unit
fADCCLK
—
—
16
MHz
Throughput rate
fADCRATE
—
—
1
Msps
Conversion time5
tADCCONV
6 bit
—
7
—
cycles
8 bit
—
9
—
cycles
12 bit
—
13
—
cycles
WARMUPMODE3 = NORMAL
—
—
5
µs
WARMUPMODE3 = KEEPINSTANDBY
—
—
2
µs
WARMUPMODE3 = KEEPINSLOWACC
—
—
1
µs
Internal reference6, differential
measurement
58
67
—
dB
External reference7, differential
measurement
—
68
—
dB
Spurious-free dynamic range SFDRADC
(SFDR)
1 MSamples/s, 10 kHz full-scale
sine wave
—
75
—
dB
Differential non-linearity
(DNL)
DNLADC
12 bit resolution, No missing codes
-1
—
2
LSB
Integral non-linearity (INL),
End point method
INLADC
12 bit resolution
-6
—
6
LSB
Offset error
VADCOFFSETERR
-3
0
3
LSB
Gain error in ADC
VADCGAIN
Using internal reference
—
-0.2
3.5
%
Using external reference
—
-1
—
%
—
-1.84
—
mV/°C
Startup time of reference
generator and ADC core
SNDR at 1Msps and fIN =
10kHz
Temperature sensor slope
tADCSTART
SNDRADC
VTS_SLOPE
Test Condition
Note:
1. The absolute voltage allowed at any ADC input is dictated by the power rail supplied to on-chip circuitry, and may be lower than
the effective full scale voltage. All ADC inputs are limited to the ADC supply (AVDD or DVDD depending on
EMU_PWRCTRL_ANASW). Any ADC input routed through the APORT will further be limited by the IOVDD supply to the pin.
2. PSRR is referenced to AVDD when ANASW=0 and to DVDD when ANASW=1 in EMU_PWRCTRL.
3. In ADCn_CTRL register.
4. In ADCn_BIASPROG register.
5. Derived from ADCCLK.
6. Internal reference option used corresponds to selection 2V5 in the SINGLECTRL_REF or SCANCTRL_REF register field. The
differential input range with this configuration is ± 1.25 V. Typical value is characterized using full-scale sine wave input. Minimum
value is production-tested using sine wave input at 1.5 dB lower than full scale.
7. External reference is 1.25 V applied externally to ADCnEXTREFP, with the selection CONF in the SINGLECTRL_REF or
SCANCTRL_REF register field and VREFP in the SINGLECTRLX_VREFSEL or SCANCTRLX_VREFSEL field. The differential
input range with this configuration is ± 1.25 V.
silabs.com | Building a more connected world.
Rev. 1.0 | 53
EFM32GG12 Family Data Sheet
Electrical Specifications
4.1.15 Analog Comparator (ACMP)
Table 4.23. Analog Comparator (ACMP)
Parameter
Symbol
Test Condition
Input voltage range
VACMPIN
Supply voltage
VACMPVDD
Active current not including
voltage reference3
IACMP
Current consumption of inter- IACMPREF
nal voltage reference3
silabs.com | Building a more connected world.
Min
Typ
Max
Unit
ACMPVDD =
ACMPn_CTRL_PWRSEL 1
—
—
VACMPVDD
V
BIASPROG2 ≤ 0x10 or FULLBIAS2 = 0
1.8
—
VVREGVDD_
V
0x10 < BIASPROG2 ≤ 0x20 and
FULLBIAS2 = 1
2.1
BIASPROG2 = 1, FULLBIAS2 = 0
—
75
—
nA
BIASPROG2 = 0x10, FULLBIAS2
=0
—
350
—
nA
BIASPROG2 = 0x02, FULLBIAS2
=1
—
6.5
—
µA
BIASPROG2 = 0x20, FULLBIAS2
=1
—
65
100
µA
VLP selected as input using 2.5 V
Reference / 4 (0.625 V)
—
50
—
nA
VLP selected as input using VDD
—
20
—
nA
VBDIV selected as input using
1.25 V reference / 1
—
4.1
—
µA
VADIV selected as input using
VDD/1
—
2.4
—
µA
MAX
—
VVREGVDD_
V
MAX
Rev. 1.0 | 54
EFM32GG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Hysteresis (VCM = 1.25 V,
BIASPROG2 = 0x10, FULLBIAS2 = 1)
VACMPHYST
Comparator delay5
tACMPDELAY
Min
Typ
Max
Unit
HYSTSEL4 = HYST0
-3
0
3
mV
HYSTSEL4 = HYST1
5
18
27
mV
HYSTSEL4 = HYST2
12
33
50
mV
HYSTSEL4 = HYST3
17
46
67
mV
HYSTSEL4 = HYST4
23
57
92
mV
HYSTSEL4 = HYST5
26
68
108
mV
HYSTSEL4 = HYST6
30
79
140
mV
HYSTSEL4 = HYST7
34
90
160
mV
HYSTSEL4 = HYST8
-3
0
3
mV
HYSTSEL4 = HYST9
-27
-18
-5
mV
HYSTSEL4 = HYST10
-50
-33
-12
mV
HYSTSEL4 = HYST11
-67
-45
-17
mV
HYSTSEL4 = HYST12
-92
-57
-23
mV
HYSTSEL4 = HYST13
-108
-67
-26
mV
HYSTSEL4 = HYST14
-140
-78
-30
mV
HYSTSEL4 = HYST15
-160
-88
-34
mV
BIASPROG2 = 1, FULLBIAS2 = 0
—
30
—
µs
BIASPROG2 = 0x10, FULLBIAS2
=0
—
3.7
—
µs
BIASPROG2 = 0x02, FULLBIAS2
=1
—
360
—
ns
BIASPROG2 = 0x20, FULLBIAS2
=1
—
35
—
ns
-35
—
35
mV
Offset voltage
VACMPOFFSET
BIASPROG2 =0x10, FULLBIAS2
=1
Reference voltage
VACMPREF
Internal 1.25 V reference
1
1.25
1.47
V
Internal 2.5 V reference
1.98
2.5
2.8
V
CSRESSEL6 = 0
—
infinite
—
kΩ
CSRESSEL6 = 1
—
15
—
kΩ
CSRESSEL6 = 2
—
27
—
kΩ
CSRESSEL6 = 3
—
39
—
kΩ
CSRESSEL6 = 4
—
51
—
kΩ
CSRESSEL6 = 5
—
100
—
kΩ
CSRESSEL6 = 6
—
162
—
kΩ
CSRESSEL6 = 7
—
235
—
kΩ
Capacitive sense internal re- RCSRES
sistance
silabs.com | Building a more connected world.
Rev. 1.0 | 55
EFM32GG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Note:
1. ACMPVDD is a supply chosen by the setting in ACMPn_CTRL_PWRSEL and may be IOVDD, AVDD or DVDD.
2. In ACMPn_CTRL register.
3. The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference. IACMPTOTAL = IACMP +
IACMPREF.
4. In ACMPn_HYSTERESIS registers.
5. ± 100 mV differential drive.
6. In ACMPn_INPUTSEL register.
silabs.com | Building a more connected world.
Rev. 1.0 | 56
EFM32GG12 Family Data Sheet
Electrical Specifications
4.1.16 Digital to Analog Converter (VDAC)
DRIVESTRENGTH = 2 unless otherwise specified. Primary VDAC output.
Table 4.24. Digital to Analog Converter (VDAC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output voltage
VDACOUT
Single-Ended
0
—
VVREF
V
-VVREF
—
VVREF
V
500 ksps, 12-bit, DRIVESTRENGTH = 2, REFSEL = 4
—
402
—
µA
44.1 ksps, 12-bit, DRIVESTRENGTH = 1, REFSEL = 4
—
88
—
µA
200 Hz refresh rate, 12-bit Sample-Off mode in EM2, DRIVESTRENGTH = 2, REFSEL = 4,
SETTLETIME = 0x02, WARMUPTIME = 0x0A
—
2
—
µA
Differential1
Current consumption including references (2 channels)2
IDAC
Current from HFPERCLK3
IDAC_CLK
—
6.6
—
µA/MHz
Sample rate
SRDAC
—
—
500
ksps
DAC clock frequency
fDAC
—
—
1
MHz
Conversion time
tDACCONV
fDAC = 1MHz
2
—
—
µs
Settling time
tDACSETTLE
50% fs step settling to 5 LSB
—
2.5
—
µs
Startup time
tDACSTARTUP
Enable to 90% fs output, settling
to 10 LSB
—
—
12
µs
Output impedance
ROUT
DRIVESTRENGTH = 2, 0.4 V ≤
VOUT ≤ VOPA - 0.4 V, -8 mA <
IOUT < 8 mA, Full supply range
—
2
—
Ω
DRIVESTRENGTH = 0 or 1, 0.4 V
≤ VOUT ≤ VOPA - 0.4 V, -400 µA <
IOUT < 400 µA, Full supply range
—
2
—
Ω
DRIVESTRENGTH = 2, 0.1 V ≤
VOUT ≤ VOPA - 0.1 V, -2 mA <
IOUT < 2 mA, Full supply range
—
2
—
Ω
DRIVESTRENGTH = 0 or 1, 0.1 V
≤ VOUT ≤ VOPA - 0.1 V, -100 µA <
IOUT < 100 µA, Full supply range
—
2
—
Ω
Vout = 50% fs. DC
—
65.5
—
dB
Power supply rejection ratio4 PSRR
silabs.com | Building a more connected world.
Rev. 1.0 | 57
EFM32GG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Min
Typ
Max
Unit
500 ksps, single-ended, internal
1.25V reference
—
60.4
—
dB
500 ksps, single-ended, internal
2.5V reference
—
61.6
—
dB
500 ksps, single-ended, 3.3V
VDD reference
—
64.0
—
dB
500 ksps, differential, internal
1.25V reference
—
63.3
—
dB
500 ksps, differential, internal
2.5V reference
—
64.4
—
dB
500 ksps, differential, 3.3V VDD
reference
—
65.8
—
dB
Signal to noise and distortion SNDRDAC_BAND 500 ksps, single-ended, internal
ratio (1 kHz sine wave),
1.25V reference
Noise band limited to 22 kHz
500 ksps, single-ended, internal
2.5V reference
—
65.3
—
dB
—
66.7
—
dB
500 ksps, single-ended, 3.3V
VDD reference
—
70.0
—
dB
500 ksps, differential, internal
1.25V reference
—
67.8
—
dB
500 ksps, differential, internal
2.5V reference
—
69.0
—
dB
500 ksps, differential, 3.3V VDD
reference
—
68.5
—
dB
—
70.2
—
dB
Signal to noise and distortion SNDRDAC
ratio (1 kHz sine wave),
Noise band limited to 250
kHz
Test Condition
Total harmonic distortion
THD
Differential non-linearity5
DNLDAC
-1.25
—
1.25
LSB
Intergral non-linearity
INLDAC
-4
—
4
LSB
Offset error6
VOFFSET
T = 25 °C
-8
—
8
mV
Across operating temperature
range
-25
—
25
mV
T = 25 °C, Low-noise internal reference (REFSEL = 1V25LN or
2V5LN)
-2.5
—
2.5
%
Across operating temperature
range, Low-noise internal reference (REFSEL = 1V25LN or
2V5LN)
-3.5
—
3.5
%
—
—
75
pF
Gain error6
External load capactiance,
OUTSCALE=0
VGAIN
CLOAD
silabs.com | Building a more connected world.
Rev. 1.0 | 58
EFM32GG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Note:
1. In differential mode, the output is defined as the difference between two single-ended outputs. Absolute voltage on each output is
limited to the single-ended range.
2. Supply current specifications are for VDAC circuitry operating with static output only and do not include current required to drive
the load.
3. Current from HFPERCLK is dependent on HFPERCLK frequency. This current contributes to the total supply current used when
the clock to the DAC peripheral is enabled in the CMU.
4. PSRR calculated as 20 * log10(ΔVDD / ΔVOUT), VDAC output at 90% of full scale
5. Entire range is monotonic and has no missing codes.
6. Gain is calculated by measuring the slope from 10% to 90% of full scale. Offset is calculated by comparing actual VDAC output at
10% of full scale to ideal VDAC output at 10% of full scale with the measured gain.
silabs.com | Building a more connected world.
Rev. 1.0 | 59
EFM32GG12 Family Data Sheet
Electrical Specifications
4.1.17 Current Digital to Analog Converter (IDAC)
Table 4.25. Current Digital to Analog Converter (IDAC)
Parameter
Symbol
Number of ranges
NIDAC_RANGES
Output current
IIDAC_OUT
Linear steps within each
range
NIDAC_STEPS
Step size
SSIDAC
Total accuracy, STEPSEL1 = ACCIDAC
0x10
silabs.com | Building a more connected world.
Test Condition
Min
Typ
Max
Unit
—
4
—
ranges
RANGESEL1 = RANGE0
0.05
—
1.6
µA
RANGESEL1 = RANGE1
1.6
—
4.7
µA
RANGESEL1 = RANGE2
0.5
—
16
µA
RANGESEL1 = RANGE3
2
—
64
µA
—
32
—
steps
RANGESEL1 = RANGE0
—
50
—
nA
RANGESEL1 = RANGE1
—
100
—
nA
RANGESEL1 = RANGE2
—
500
—
nA
RANGESEL1 = RANGE3
—
2
—
µA
EM0 or EM1, AVDD=3.3 V, T = 25
°C
-3
—
3
%
EM0 or EM1, Across operating
temperature range
-18
—
22
%
EM2 or EM3, Source mode, RANGESEL1 = RANGE0, AVDD=3.3
V, T = 25 °C
—
-2.7
—
%
EM2 or EM3, Source mode, RANGESEL1 = RANGE1, AVDD=3.3
V, T = 25 °C
—
-2.5
—
%
EM2 or EM3, Source mode, RANGESEL1 = RANGE2, AVDD=3.3
V, T = 25 °C
—
-1.5
—
%
EM2 or EM3, Source mode, RANGESEL1 = RANGE3, AVDD=3.3
V, T = 25 °C
—
-1.0
—
%
EM2 or EM3, Sink mode, RANGESEL1 = RANGE0, AVDD=3.3
V, T = 25 °C
—
-1.1
—
%
EM2 or EM3, Sink mode, RANGESEL1 = RANGE1, AVDD=3.3
V, T = 25 °C
—
-1.1
—
%
EM2 or EM3, Sink mode, RANGESEL1 = RANGE2, AVDD=3.3
V, T = 25 °C
—
-0.9
—
%
EM2 or EM3, Sink mode, RANGESEL1 = RANGE3, AVDD=3.3
V, T = 25 °C
—
-0.9
—
%
Rev. 1.0 | 60
EFM32GG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Start up time
tIDAC_SU
Settling time, (output settled tIDAC_SETTLE
within 1% of steady state value),
Current consumption2
IIDAC
Output voltage compliance in ICOMP_SRC
source mode, source current
change relative to current
sourced at 0 V
Output voltage compliance in ICOMP_SINK
sink mode, sink current
change relative to current
sunk at IOVDD
Min
Typ
Max
Unit
Output within 1% of steady state
value
—
5
—
µs
Range setting is changed
—
5
—
µs
Step value is changed
—
1
—
µs
EM0 or EM1 Source mode, excluding output current, Across operating temperature range
—
11
28
µA
EM0 or EM1 Sink mode, excluding output current, Across operating temperature range
—
13
30
µA
EM2 or EM3 Source mode, excluding output current, T = 25 °C
—
0.05
—
µA
EM2 or EM3 Sink mode, excluding output current, T = 25 °C
—
0.07
—
µA
EM2 or EM3 Source mode, excluding output current, T ≥ 85 °C
—
11
—
µA
EM2 or EM3 Sink mode, excluding output current, T ≥ 85 °C
—
13
—
µA
RANGESEL1 = RANGE0, output
voltage = min(VIOVDD,
VAVDD2-100 mV)
—
0.11
—
%
RANGESEL1 = RANGE1, output
voltage = min(VIOVDD,
VAVDD2-100 mV)
—
0.06
—
%
RANGESEL1 = RANGE2, output
voltage = min(VIOVDD,
VAVDD2-150 mV)
—
0.04
—
%
RANGESEL1 = RANGE3, output
voltage = min(VIOVDD,
VAVDD2-250 mV)
—
0.03
—
%
RANGESEL1 = RANGE0, output
voltage = 100 mV
—
0.29
—
%
RANGESEL1 = RANGE1, output
voltage = 100 mV
—
0.27
—
%
RANGESEL1 = RANGE2, output
voltage = 150 mV
—
0.12
—
%
RANGESEL1 = RANGE3, output
voltage = 250 mV
—
0.03
—
%
Note:
1. In IDAC_CURPROG register.
2. The IDAC is supplied by either AVDD, DVDD, or IOVDD based on the setting of ANASW in the EMU_PWRCTRL register and
PWRSEL in the IDAC_CTRL register. Setting PWRSEL to 1 selects IOVDD. With PWRSEL cleared to 0, ANASW selects between AVDD (0) and DVDD (1).
silabs.com | Building a more connected world.
Rev. 1.0 | 61
EFM32GG12 Family Data Sheet
Electrical Specifications
4.1.18 Capacitive Sense (CSEN)
Table 4.26. Capacitive Sense (CSEN)
Parameter
Symbol
Test Condition
Single conversion time (1x
accumulation)
tCNV
Maximum external capacitive CEXTMAX
load
Min
Typ
Max
Unit
12-bit SAR Conversions
—
20.2
—
µs
16-bit SAR Conversions
—
26.4
—
µs
Delta Modulation Conversion (single comparison)
—
1.55
—
µs
IREFPROG=7 (Gain = 1x), including routing parasitics
—
68
—
pF
IREFPROG=0 (Gain = 10x), including routing parasitics
—
680
—
pF
—
1
—
kΩ
12-bit SAR conversions, 20 ms
conversion rate, IREFPROG=7
(Gain = 1x), 10 channels bonded
(total capacitance of 330 pF)1
—
326
—
nA
Delta Modulation conversions, 20
ms conversion rate, IREFPROG=7 (Gain = 1x), 10 channels bonded (total capacitance of
330 pF)1
—
226
—
nA
12-bit SAR conversions, 200 ms
conversion rate, IREFPROG=7
(Gain = 1x), 10 channels bonded
(total capacitance of 330 pF)1
—
33
—
nA
Delta Modulation conversions,
200 ms conversion rate, IREFPROG=7 (Gain = 1x), 10 channels bonded (total capacitance of
330 pF)1
—
25
—
nA
12-bit SAR conversions, 20 ms
scan rate, IREFPROG=0 (Gain =
10x), 8 samples per scan1
—
690
—
nA
Delta Modulation conversions, 20
ms scan rate, 8 comparisons per
sample (DMCR = 1, DMR = 2),
IREFPROG=0 (Gain = 10x), 8
samples per scan1
—
515
—
nA
12-bit SAR conversions, 200 ms
scan rate, IREFPROG=0 (Gain =
10x), 8 samples per scan1
—
79
—
nA
Delta Modulation conversions,
200 ms scan rate, 8 comparisons
per sample (DMCR = 1, DMR =
2), IREFPROG=0 (Gain = 10x), 8
samples per scan1
—
57
—
nA
Maximum external series im- REXTMAX
pedance
Supply current, EM2 bonded ICSEN_BOND
conversions, WARMUPMODE=NORMAL, WARMUPCNT=0
Supply current, EM2 scan
conversions, WARMUPMODE=NORMAL, WARMUPCNT=0
ICSEN_EM2
silabs.com | Building a more connected world.
Rev. 1.0 | 62
EFM32GG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Supply current, continuous
conversions, WARMUPMODE=KEEPCSENWARM
ICSEN_ACTIVE
SAR or Delta Modulation conversions of 33 pF capacitor, IREFPROG=0 (Gain = 10x), always
on
—
90.5
—
µA
HFPERCLK supply current
ICSEN_HFPERCLK Current contribution from
HFPERCLK when clock to CSEN
block is enabled.
—
2.25
—
µA/MHz
Note:
1. Current is specified with a total external capacitance of 33 pF per channel. Average current is dependent on how long the peripheral is actively sampling channels within the scan period, and scales with the number of samples acquired. Supply current for a
specific application can be estimated by multiplying the current per sample by the total number of samples per period (total_current = single_sample_current * (number_of_channels * accumulation)).
silabs.com | Building a more connected world.
Rev. 1.0 | 63
EFM32GG12 Family Data Sheet
Electrical Specifications
4.1.19 Operational Amplifier (OPAMP)
Unless otherwise indicated, specified conditions are: Non-inverting input configuration, VDD = 3.3 V, DRIVESTRENGTH = 2, MAINOUTEN = 1, CLOAD = 75 pF with OUTSCALE = 0, or CLOAD = 37.5 pF with OUTSCALE = 1. Unit gain buffer and 3X-gain connection as
specified in table footnotes1 2.
Table 4.27. Operational Amplifier (OPAMP)
Parameter
Symbol
Test Condition
Supply voltage (from AVDD)
VOPA
HCMDIS = 0, Rail-to-rail input
range
Input voltage
VIN
Min
Typ
Max
Unit
2
—
3.8
V
HCMDIS = 1
1.62
—
3.8
V
HCMDIS = 0, Rail-to-rail input
range
VVSS
—
VOPA
V
HCMDIS = 1
VVSS
—
VOPA-1.2
V
Input impedance
RIN
100
—
—
MΩ
Output voltage
VOUT
VVSS
—
VOPA
V
Load capacitance3
CLOAD
OUTSCALE = 0
—
—
75
pF
OUTSCALE = 1
—
—
37.5
pF
DRIVESTRENGTH = 2 or 3, 0.4 V
≤ VOUT ≤ VOPA - 0.4 V, -8 mA <
IOUT < 8 mA, Buffer connection,
Full supply range
—
0.25
—
Ω
DRIVESTRENGTH = 0 or 1, 0.4 V
≤ VOUT ≤ VOPA - 0.4 V, -400 µA <
IOUT < 400 µA, Buffer connection,
Full supply range
—
0.6
—
Ω
DRIVESTRENGTH = 2 or 3, 0.1 V
≤ VOUT ≤ VOPA - 0.1 V, -2 mA <
IOUT < 2 mA, Buffer connection,
Full supply range
—
0.4
—
Ω
DRIVESTRENGTH = 0 or 1, 0.1 V
≤ VOUT ≤ VOPA - 0.1 V, -100 µA <
IOUT < 100 µA, Buffer connection,
Full supply range
—
1
—
Ω
Buffer connection
0.99
1
1.01
-
3x Gain connection
2.93
2.99
3.05
-
16x Gain connection
15.07
15.7
16.33
-
DRIVESTRENGTH = 3, OUTSCALE = 0
—
580
—
µA
DRIVESTRENGTH = 2, OUTSCALE = 0
—
176
—
µA
DRIVESTRENGTH = 1, OUTSCALE = 0
—
13
—
µA
DRIVESTRENGTH = 0, OUTSCALE = 0
—
4.7
—
µA
Output impedance
Internal closed-loop gain
Active current4
ROUT
GCL
IOPA
silabs.com | Building a more connected world.
Rev. 1.0 | 64
EFM32GG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Open-loop gain
GOL
Loop unit-gain frequency5
Phase margin
Output voltage noise
UGF
PM
NOUT
silabs.com | Building a more connected world.
Min
Typ
Max
Unit
DRIVESTRENGTH = 3
—
135
—
dB
DRIVESTRENGTH = 2
—
137
—
dB
DRIVESTRENGTH = 1
—
121
—
dB
DRIVESTRENGTH = 0
—
109
—
dB
DRIVESTRENGTH = 3, Buffer
connection
—
3.38
—
MHz
DRIVESTRENGTH = 2, Buffer
connection
—
0.9
—
MHz
DRIVESTRENGTH = 1, Buffer
connection
—
132
—
kHz
DRIVESTRENGTH = 0, Buffer
connection
—
34
—
kHz
DRIVESTRENGTH = 3, 3x Gain
connection
—
2.57
—
MHz
DRIVESTRENGTH = 2, 3x Gain
connection
—
0.71
—
MHz
DRIVESTRENGTH = 1, 3x Gain
connection
—
113
—
kHz
DRIVESTRENGTH = 0, 3x Gain
connection
—
28
—
kHz
DRIVESTRENGTH = 3, Buffer
connection
—
67
—
°
DRIVESTRENGTH = 2, Buffer
connection
—
69
—
°
DRIVESTRENGTH = 1, Buffer
connection
—
63
—
°
DRIVESTRENGTH = 0, Buffer
connection
—
68
—
°
DRIVESTRENGTH = 3, Buffer
connection, 10 Hz - 10 MHz
—
146
—
µVrms
DRIVESTRENGTH = 2, Buffer
connection, 10 Hz - 10 MHz
—
163
—
µVrms
DRIVESTRENGTH = 1, Buffer
connection, 10 Hz - 1 MHz
—
170
—
µVrms
DRIVESTRENGTH = 0, Buffer
connection, 10 Hz - 1 MHz
—
176
—
µVrms
DRIVESTRENGTH = 3, 3x Gain
connection, 10 Hz - 10 MHz
—
313
—
µVrms
DRIVESTRENGTH = 2, 3x Gain
connection, 10 Hz - 10 MHz
—
271
—
µVrms
DRIVESTRENGTH = 1, 3x Gain
connection, 10 Hz - 1 MHz
—
247
—
µVrms
DRIVESTRENGTH = 0, 3x Gain
connection, 10 Hz - 1 MHz
—
245
—
µVrms
Rev. 1.0 | 65
EFM32GG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Slew rate6
SR
DRIVESTRENGTH = 3,
INCBW=17
—
4.7
—
V/µs
DRIVESTRENGTH = 3,
INCBW=0
—
1.5
—
V/µs
DRIVESTRENGTH = 2,
INCBW=17
—
1.27
—
V/µs
DRIVESTRENGTH = 2,
INCBW=0
—
0.42
—
V/µs
DRIVESTRENGTH = 1,
INCBW=17
—
0.17
—
V/µs
DRIVESTRENGTH = 1,
INCBW=0
—
0.058
—
V/µs
DRIVESTRENGTH = 0,
INCBW=17
—
0.044
—
V/µs
DRIVESTRENGTH = 0,
INCBW=0
—
0.015
—
V/µs
Startup time8
TSTART
DRIVESTRENGTH = 2
—
—
12
µs
Input offset voltage
VOSI
DRIVESTRENGTH = 2 or 3, T =
25 °C
-3
—
3
mV
DRIVESTRENGTH = 1 or 0, T =
25 °C
-3
—
3
mV
DRIVESTRENGTH = 2 or 3,
across operating temperature
range
-12
—
12
mV
DRIVESTRENGTH = 1 or 0,
across operating temperature
range
-30
—
30
mV
DC power supply rejection
ratio9
PSRRDC
Input referred
—
70
—
dB
DC common-mode rejection
ratio9
CMRRDC
Input referred
—
70
—
dB
Total harmonic distortion
THDOPA
DRIVESTRENGTH = 2, 3x Gain
connection, 1 kHz, VOUT = 0.1 V
to VOPA - 0.1 V
—
90
—
dB
DRIVESTRENGTH = 0, 3x Gain
connection, 0.1 kHz, VOUT = 0.1 V
to VOPA - 0.1 V
—
90
—
dB
silabs.com | Building a more connected world.
Rev. 1.0 | 66
EFM32GG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Note:
1. Specified configuration for Unit gain buffer configuration is: INCBW = 0, HCMDIS = 0, RESINSEL = DISABLE. VINPUT = 0.5 V,
VOUTPUT = 0.5 V.
2. Specified configuration for 3X-Gain configuration is: INCBW = 1, HCMDIS = 1, RESINSEL = VSS, VINPUT = 0.5 V, VOUTPUT = 1.5
V. Nominal voltage gain is 3.
3. If the maximum CLOAD is exceeded, an isolation resistor is required for stability. See AN0038 for more information.
4. Current into the load resistor is excluded. When the OPAMP is connected with closed-loop gain > 1, there will be extra current to
drive the resistor feedback network. The internal resistor feedback network has total resistance of 143.5 kOhm, which will cause
another ~10 µA current when the OPAMP drives 1.5 V between output and ground.
5. In unit gain connection, UGF is the gain-bandwidth product of the OPAMP. In 3x Gain connection, UGF is the gain-bandwidth
product of the OPAMP and 1/3 attenuation of the feedback network.
6. Step between 0.2V and VOPA-0.2V, 10%-90% rising/falling range.
7. When INCBW is set to 1 the OPAMP bandwidth is increased. This is allowed only when the non-inverting close-loop gain is ≥ 3,
or the OPAMP may not be stable.
8. From enable to output settled. In sample-and-off mode, RC network after OPAMP will contribute extra delay. Settling error < 1mV.
9. When HCMDIS=1 and input common mode transitions the region from VOPA-1.4V to VOPA-1V, input offset will change. PSRR
and CMRR specifications do not apply to this transition region.
4.1.20 LCD Driver
Table 4.28. LCD Driver
Parameter
Symbol
Frame rate
Min
Typ
Max
Unit
fLCDFR
30
—
100
Hz
LCD supply range1
VLCDIN
1.8
—
3.8
V
LCD output voltage range
VLCD
Current source mode, No external
LCD capacitor
2.0
—
VLCDIN-0.4
V
Step-down mode with external
LCD capacitor
2.0
—
VLCDIN
V
Charge pump mode with external
LCD capacitor
2.0
—
1.9 *
VLCDIN
V
Current source mode
—
64
—
mV
Charge pump or Step-down mode
—
43
—
mV
—
+/-4
—
%
Contrast control step size
STEPCONTRAST
Contrast control step accura- ACCCONTRAST
cy2
Test Condition
Note:
1. VLCDIN is selectable between the AVDD or DVDD supply pins, depending on EMU_PWRCTRL_ANASW.
2. Step size accuracy is measured relative to the typical step size, and typ value represents one standard deviation.
silabs.com | Building a more connected world.
Rev. 1.0 | 67
EFM32GG12 Family Data Sheet
Electrical Specifications
4.1.21 Pulse Counter (PCNT)
Table 4.29. Pulse Counter (PCNT)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Input frequency
FIN
Asynchronous Single and Quadrature Modes
—
—
20
MHz
Sampled Modes with Debounce
filter set to 0.
—
—
8
kHz
Min
Typ
Max
Unit
4.1.22 Analog Port (APORT)
Table 4.30. Analog Port (APORT)
Parameter
Symbol
Test Condition
Supply current1 2
IAPORT
Operation in EM0/EM1
—
7
—
µA
Operation in EM2/EM3
—
63
—
nA
Note:
1. Supply current increase that occurs when an analog peripheral requests access to APORT. This current is not included in reported peripheral currents. Additional peripherals requesting access to APORT do not incur further current.
2. Specified current is for continuous APORT operation. In applications where the APORT is not requested continuously (e.g. periodic ACMP requests from LESENSE in EM2), the average current requirements can be estimated by mutiplying the duty cycle of
the requests by the specified continuous current number.
silabs.com | Building a more connected world.
Rev. 1.0 | 68
EFM32GG12 Family Data Sheet
Electrical Specifications
4.1.23 I2C
4.1.23.1 I2C Standard-mode (Sm)1
Table 4.31. I2C Standard-mode (Sm)1
Parameter
Symbol
SCL clock frequency2
Test Condition
Min
Typ
Max
Unit
fSCL
0
—
100
kHz
SCL clock low time
tLOW
4.7
—
—
µs
SCL clock high time
tHIGH
4
—
—
µs
SDA set-up time
tSU_DAT
250
—
—
ns
SDA hold time3
tHD_DAT
100
—
3450
ns
Repeated START condition
set-up time
tSU_STA
4.7
—
—
µs
(Repeated) START condition tHD_STA
hold time
4
—
—
µs
STOP condition set-up time
tSU_STO
4
—
—
µs
Bus free time between a
STOP and START condition
tBUF
4.7
—
—
µs
Note:
1. For CLHR set to 0 in the I2Cn_CTRL register.
2. For the minimum HFPERCLK frequency required in Standard-mode, refer to the I2C chapter in the reference manual.
3. The maximum SDA hold time (tHD_DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
silabs.com | Building a more connected world.
Rev. 1.0 | 69
EFM32GG12 Family Data Sheet
Electrical Specifications
4.1.23.2 I2C Fast-mode (Fm)1
Table 4.32. I2C Fast-mode (Fm)1
Parameter
Symbol
SCL clock frequency2
Test Condition
Min
Typ
Max
Unit
fSCL
0
—
400
kHz
SCL clock low time
tLOW
1.3
—
—
µs
SCL clock high time
tHIGH
0.6
—
—
µs
SDA set-up time
tSU_DAT
100
—
—
ns
SDA hold time3
tHD_DAT
100
—
900
ns
Repeated START condition
set-up time
tSU_STA
0.6
—
—
µs
(Repeated) START condition tHD_STA
hold time
0.6
—
—
µs
STOP condition set-up time
tSU_STO
0.6
—
—
µs
Bus free time between a
STOP and START condition
tBUF
1.3
—
—
µs
Note:
1. For CLHR set to 1 in the I2Cn_CTRL register.
2. For the minimum HFPERCLK frequency required in Fast-mode, refer to the I2C chapter in the reference manual.
3. The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
silabs.com | Building a more connected world.
Rev. 1.0 | 70
EFM32GG12 Family Data Sheet
Electrical Specifications
4.1.23.3 I2C Fast-mode Plus (Fm+)1
Table 4.33. I2C Fast-mode Plus (Fm+)1
Parameter
Symbol
SCL clock frequency2
Test Condition
Min
Typ
Max
Unit
fSCL
0
—
1000
kHz
SCL clock low time
tLOW
0.5
—
—
µs
SCL clock high time
tHIGH
0.26
—
—
µs
SDA set-up time
tSU_DAT
50
—
—
ns
SDA hold time
tHD_DAT
100
—
—
ns
Repeated START condition
set-up time
tSU_STA
0.26
—
—
µs
(Repeated) START condition tHD_STA
hold time
0.26
—
—
µs
STOP condition set-up time
tSU_STO
0.26
—
—
µs
Bus free time between a
STOP and START condition
tBUF
0.5
—
—
µs
Note:
1. For CLHR set to 0 or 1 in the I2Cn_CTRL register.
2. For the minimum HFPERCLK frequency required in Fast-mode Plus, refer to the I2C chapter in the reference manual.
silabs.com | Building a more connected world.
Rev. 1.0 | 71
EFM32GG12 Family Data Sheet
Electrical Specifications
4.1.24 USART SPI
SPI Master Timing
Table 4.34. SPI Master Timing
Parameter
Symbol
Test Condition
SCLK period 1 2 3
tSCLK
CS to MOSI 1 2
SCLK to MOSI 1 2
MISO setup time 1 2
tCS_MO
tSCLK_MO
tSU_MI
silabs.com | Building a more connected world.
Min
Typ
Max
Unit
All USARTs except USART2
2*
tHFPERCLK
—
—
ns
USART2
2*
tHFPERBCLK
—
—
ns
USART2, location 4, IOVDD = 1.8
V
-4
—
6
ns
USART2, location 4, IOVDD = 3.0
V
-2.5
—
5
ns
USART2, location 5, IOVDD = 1.8
V
-6.5
—
7.5
ns
USART2, location 5, IOVDD = 3.0
V
-5.5
—
6
ns
All other USARTs and locations,
IOVDD = 1.8 V
-10.5
—
9
ns
All other USARTs and locations,
IOVDD = 3.0 V
-8.5
—
7.5
ns
USART2, location 4, IOVDD = 1.8
V
-1
—
6
ns
USART2, location 4, IOVDD = 3.0
V
-1
—
5.5
ns
USART2, location 5, IOVDD = 1.8
V
-3
—
4
ns
USART2, location 5, IOVDD = 3.0
V
-2.5
—
2.5
ns
All other USARTs and locations,
IOVDD = 1.8 V
-7
—
8.5
ns
All other USARTs and locations,
IOVDD = 3.0 V
-6
—
9
ns
USART2, location 4, IOVDD = 1.8
V
41
—
—
ns
USART2, location 4, IOVDD = 3.0
V
32
—
—
ns
USART2, location 5, IOVDD = 1.8
V
49
—
—
ns
USART2, location 5, IOVDD = 3.0
V
30
—
—
ns
All other USARTs and locations,
IOVDD = 1.8 V
51
—
—
ns
All other USARTs and locations,
IOVDD = 3.0 V
32
—
—
ns
Rev. 1.0 | 72
EFM32GG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
MISO hold time 1 2
tH_MI
USART2, location 4, IOVDD = 1.8
V
-12
—
—
ns
USART2, location 4, IOVDD = 3.0
V
-12
—
—
ns
USART2, location 5, IOVDD = 1.8
V
-9.5
—
—
ns
USART2, location 5, IOVDD = 3.0
V
-9.5
—
—
ns
All other USARTs and locations,
IOVDD = 1.8 V
-10.5
—
—
ns
All other USARTs and locations,
IOVDD = 3.0 V
-10.5
—
—
ns
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0).
2. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD).
3. tHFPERCLK is one period of the selected HFPERCLK.
CS
tCS_MO
tSCKL_MO
SCLK
CLKPOL = 0
tSCLK
SCLK
CLKPOL = 1
MOSI
tSU_MI
tH_MI
MISO
Figure 4.1. SPI Master Timing Diagram
silabs.com | Building a more connected world.
Rev. 1.0 | 73
EFM32GG12 Family Data Sheet
Electrical Specifications
SPI Slave Timing
Table 4.35. SPI Slave Timing
Parameter
Symbol
SCLK period 1 2 3
Test Condition
Min
Typ
Max
Unit
tSCLK
6*
tHFPERCLK
—
—
ns
SCLK high time1 2 3
tSCLK_HI
2.5 *
tHFPERCLK
—
—
ns
SCLK low time1 2 3
tSCLK_LO
2.5 *
tHFPERCLK
—
—
ns
CS active to MISO 1 2
tCS_ACT_MI
22
—
54
ns
CS disable to MISO 1 2
tCS_DIS_MI
20
—
175
ns
MOSI setup time 1 2
tSU_MO
6
—
—
ns
MOSI hold time 1 2 3
tH_MO
7
—
—
ns
SCLK to MISO 1 2 3
tSCLK_MI
17 + 1.5 *
tHFPERCLK
—
41 + 2.5 *
tHFPERCLK
ns
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0).
2. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD).
3. tHFPERCLK is one period of the selected HFPERCLK.
CS
tCS_ACT_MI
tCS_DIS_MI
SCLK
CLKPOL = 0
SCLK
CLKPOL = 1
tSCLK_HI
tSU_MO
tSCLK_LO
tSCLK
tH_MO
MOSI
tSCLK_MI
MISO
Figure 4.2. SPI Slave Timing Diagram
silabs.com | Building a more connected world.
Rev. 1.0 | 74
EFM32GG12 Family Data Sheet
Electrical Specifications
4.1.25 External Bus Interface (EBI)
EBI Write Enable Output Timing
Timing applies to both EBI_WEn and EBI_NANDWEn for all addressing modes and both polarities. All numbers are based on route
locations 0,1,2 only (with all EBI alternate functions using the same location at the same time). Timing is specified at 10% and 90% of
IOVDD, 25 pF external loading, and slew rate for all GPIO set to 6.
Table 4.36. EBI Write Enable Timing
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output hold time, from trailing EBI_WEn / EBI_NANDWEn edge to EBI_AD,
EBI_A, EBI_CSn, EBI_BLn
invalid
tOH_WEn
IOVDD ≥ 1.62 V
-22 +
(WRHOLD
* t{}HFCORECLK{})
—
—
ns
IOVDD ≥ 3.0 V
-14 +
(WRHOLD
* tHFCORECLK)
—
—
ns
IOVDD ≥ 1.62 V
-12 +
(WRSETUP *
tHFCORECLK)
—
—
ns
IOVDD ≥ 3.0 V
-10 +
(WRSETUP *
tHFCORECLK)
—
—
ns
IOVDD ≥ 1.62 V
-6 +
(MAX(1,
WRSTRB)
* tHFCORECLK)
—
—
ns
IOVDD ≥ 3.0 V
-5 +
(MAX(1,
WRSTRB)
* tHFCORECLK)
—
—
ns
Output setup time, from
EBI_AD, EBI_A, EBI_CSn,
EBI_BLn valid to leading
EBI_WEn / EBI_NANDWEn
edge1
EBI_WEn / EBI_NANDWEn
pulse width1
tOSU_WEn
tWIDTH_WEn
Note:
1. The figure shows the timing for the case that the half strobe length functionality is not used, i.e. HALFWE=0. The leading edge of
EBI_WEn can be moved to the right by setting HALFWE=1. This decreases the length of tWIDTH_WEn and increases the length of
tOSU_WEn by 1/2 * tHFCLKNODIV.
silabs.com | Building a more connected world.
Rev. 1.0 | 75
EFM32GG12 Family Data Sheet
Electrical Specifications
WRSETUP
(0, 1, 2, ...)
EBI_BL[N-1:0]
WRSTRB
(1, 2, 3, ...)
Z
EBI_BL
tOSU_WEn
EBI_A[N-1:0]
tOH_WEn
Z
EBI_A
tOSU_WEn
EBI_AD[15:0]
WRHOLD
(0, 1, 2, ...)
tOH_WEn
Z
DATA[15:0]
tOSU_WEn
tOH_WEn
tOSU_WEn
tOH_WEn
EBI_CSn
EBI_WEn
tWIDTH_WEn
Figure 4.3. EBI Write Enable Output Timing Diagram
silabs.com | Building a more connected world.
Rev. 1.0 | 76
EFM32GG12 Family Data Sheet
Electrical Specifications
EBI Address Latch Enable Output Timing
Timing applies to multiplexed addressing modes D8A24ALE and D16A16ALE for both polarities. All numbers are based on route locations 0,1,2 only (with all EBI alternate functions using the same location at the same time). Timing is specified at 10% and 90% of
IOVDD, 25 pF external loading, and slew rate for all GPIO set to 6.
Table 4.37. EBI Address Latch Enable Output Timing
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output hold time, from trailing EBI_ALE edge to
EBI_AD invalid1 2
tOH_ALEn
IOVDD ≥ 1.62 V
-22 +
(ADDRHOLD *
tHFCORECLK)
—
—
ns
IOVDD ≥ 3.0 V
-13 +
(ADDRHOLD *
tHFCORECLK)
—
—
ns
IOVDD ≥ 1.62 V
-10
—
—
ns
IOVDD ≥ 3.0 V
-9
—
—
ns
IOVDD ≥ 1.62 V
-5 +
((ADDRSETUP +
1) *
t{}HFCORECLK{})
—
—
ns
IOVDD ≥ 3.0 V
-4 +
((ADDRSETUP +
1) *
t{}HFCORECLK{})
—
—
ns
Output setup time, from
EBI_AD valid to leading
EBI_ALE edge
tOSU_ALEn
EBI_ALEn pulse width1
tWIDTH_ALEn
Note:
1. The figure shows the timing for the case that the half strobe length functionality is not used, i.e. HALFALE=0. The trailing edge of
EBI_ALEn can be moved to the left by setting HALFALE=1. This decreases the length of tWIDTH_ALEn and increases the length of
tOSU_ALEn by tHFCORECLK - 1/2 * tHFCLKNODIV.
2. The figure shows a write operation. For a multiplexed read operation the address hold time is controlled via the RDSETUP state
instead of via the ADDRHOLD state.
silabs.com | Building a more connected world.
Rev. 1.0 | 77
EFM32GG12 Family Data Sheet
Electrical Specifications
ADDRSETUP
(1, 2, 3, ...)
EBI_AD[15:0]
ADDRHOLD
(0, 1, 2, ...)
ADDR[16:1]
WRSETUP
(0, 1, 2, ...)
WRSTRB
(1, 2, 3, ...)
DATA[15:0]
WRHOLD
(0, 1, 2, ...)
Z
tWIDTH_ALEn
EBI_ALE
tWIDTH_ALEn
tOSU_ALEn
EBI_CSn
EBI_WEn
Figure 4.4. EBI Address Latch Enable Output Timing Diagram
silabs.com | Building a more connected world.
Rev. 1.0 | 78
EFM32GG12 Family Data Sheet
Electrical Specifications
EBI Read Enable Output Timing
Timing applies to both EBI_REn and EBI_NANDREn for all addressing modes and both polarities. Output timing for EBI_AD applies
only to multiplexed addressing modes D8A24ALE and D16A16ALE. All numbers are based on route locations 0,1,2 only (with all EBI
alternate functions using the same location at the same time). Timing is specified at 10% and 90% of IOVDD, 25 pF external loading,
and slew rate for all GPIO set to 6.
Table 4.38. EBI Read Enable Output Timing
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output hold time, from trailing EBI_REn / EBI_NANDREn edge to EBI_AD,
EBI_A, EBI_CSn, EBI_BLn
invalid
tOH_REn
IOVDD ≥ 1.62 V
-21 +
(RDHOLD *
tHFCORECLK)
—
—
ns
IOVDD ≥ 3.0 V
-11 +
(RDHOLD *
tHFCORECLK)
—
—
ns
IOVDD ≥ 1.62 V
-11 +
(RDSETUP
* tHFCORECLK)
—
—
ns
IOVDD ≥ 3.0 V
-10 +
(RDSETUP
* tHFCORECLK)
—
—
ns
IOVDD ≥ 1.62 V
-6 +
(MAX(1,
RDSTRB) *
tHFCORECLK)
—
—
ns
IOVDD ≥ 3.0 V
-4 +
(MAX(1,
RDSTRB) *
tHFCORECLK)
—
—
ns
Output setup time, from
EBI_AD, EBI_A, EBI_CSn,
EBI_BLn valid to leading
EBI_REn / EBI_NANDREn
edge 1
tOSU_REn
EBI_REn pulse width1 2
tWIDTH_REn
Note:
1. The figure shows the timing for the case that the half strobe length functionality is not used, i.e. HALFRE=0. The leading edge of
EBI_REn can be moved to the right by setting HALFRE=1. This decreases the length of tWIDTH_REn and increases the length of
tOSU_REn by 1/2 * tHFCLKNODIV.
2. When page mode is used, RDSTRB is replaced by RDPA for page hits.
silabs.com | Building a more connected world.
Rev. 1.0 | 79
EFM32GG12 Family Data Sheet
Electrical Specifications
RDSETUP
(0, 1, 2, ...)
EBI_BL[1:0]
RDSTRB
(1, 2, 3, ...)
EBI_BL
Z
tSU_REn
EBI_A[27:0]
tH_REn
EBI_A
Z
tH_REn
tSU_REn
EBI_AD[15:8]
RDHOLD
(0, 1, 2, ...)
ADDR[7:0]
Z
tSU_REn
tH_REn
tSU_REn
tH_REn
EBI_CSn
EBI_AD[7:0]
EBI_REn
Z
DATA[7:0]
Z
tWIDTH_REn
Figure 4.5. EBI Read Enable Output Timing Diagram
silabs.com | Building a more connected world.
Rev. 1.0 | 80
EFM32GG12 Family Data Sheet
Electrical Specifications
EBI TFT Output Timing
All numbers are based on route locations 0,1,2 only (with all EBI alternate functions using the same location at the same time). Timing
is specified at 10% and 90% of IOVDD, 25 pF external loading, and slew rate for all GPIO set to 6.
Table 4.39. EBI TFT Output Timing
Parameter
Symbol
Output hold time, EBI_DCLK tOH_DCLK
to EBI_AD invalid
Output setup time, EBI_AD
valid to EBI_DCLK
tOSU_DCLK
Test Condition
Min
Typ
Max
Unit
IOVDD ≥ 1.62 V
-19 +
(TFTHOLD
* tHFCORECLK)
—
—
ns
IOVDD ≥ 3.0 V
-10 +
(TFTHOLD
* tHFCORECLK)
—
—
ns
IOVDD ≥ 1.62 V
-12 +
(TFTSETUP *
tHFCORECLK)
—
—
ns
IOVDD ≥ 3.0 V
-11 +
(TFTSETUP *
tHFCORECLK)
—
—
ns
EBI_DCLK
tOSU_DCLK
EBI_AD
DATA[15:0]
tOH_DCLK
DATA[15:0]
DATA[15:0]
Figure 4.6. EBI TFT Output Timing
silabs.com | Building a more connected world.
Rev. 1.0 | 81
EFM32GG12 Family Data Sheet
Electrical Specifications
EBI Read Enable Timing Requirements
Timing applies to both EBI_REn and EBI_NANDREn for all addressing modes and both polarities. All numbers are based on route locations 0,1,2 only (with all EBI alternate functions using the same location at the same time). Timing is specified at 10% and 90% of
IOVDD, 25 pF external loading, and slew rate for all GPIO set to 6.
Table 4.40. EBI Read Enable Timing Requirements
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Setup time, from EBI_AD
valid to trailing EBI_REn
edge
tSU_REn
IOVDD ≥ 1.62 V
50
—
—
ns
IOVDD ≥ 3.0 V
29
—
—
ns
IOVDD ≥ 1.62 V
-9
—
—
ns
Hold time, from trailing
tH_REn
EBI_REn edge to EBI_AD invalid
RDSETUP
(0, 1, 2, ...)
EBI_A[N-1:0]
ADDR[N:1]
EBI_AD[15:0]
Z
RDSTRB
(1, 2, 3, ...)
RDHOLD
(0, 1, 2, ...)
Z
DATA[15:0]
Z
EBI_CSn
EBI_REn
tSU_REn
tH_REn
Figure 4.7. EBI Read Enable Timing Requirements
silabs.com | Building a more connected world.
Rev. 1.0 | 82
EFM32GG12 Family Data Sheet
Electrical Specifications
EBI Ready/Wait Timing Requirements
Timing applies to both EBI_REn and EBI_WEn for all addressing modes and both polarities. All numbers are based on route locations
0,1,2 only (with all EBI alternate functions using the same location at the same time). Timing is specified at 10% and 90% of IOVDD, 25
pF external loading, and slew rate for all GPIO set to 6.
Table 4.41. EBI Ready/Wait Timing Requirements
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Setup time, from EBI_ARDY
valid to trailing EBI_REn,
EBI_WEn edge
tSU_ARDY
IOVDD ≥ 1.62 V
52 + (3 *
tHFCORECLK)
—
—
ns
IOVDD ≥ 3.0 V
33 + (3 *
tHFCORECLK)
—
—
ns
IOVDD ≥ 1.62 V
-9
—
—
ns
Hold time, from trailing
EBI_REn, EBI_WEn edge to
EBI_ARDY invalid
tH_ARDY
RDSETUP
(0, 1, 2, ...)
RDSTRB
(1, 2, 3, ...)
SYNC
(3)
RDHOLD
(0, 1, 2, ...)
EBI_RDY
EBI_AD[15:0]
Z
DATA[15:0]
EBI_CSn
tSU_ARDY
EBI_REn
tH_ARDY
Figure 4.8. EBI Ready/Wait Timing Requirements
silabs.com | Building a more connected world.
Rev. 1.0 | 83
EFM32GG12 Family Data Sheet
Electrical Specifications
4.1.26 Serial Data I/O Host Controller (SDIO)
SDIO DS Mode Timing
Timing is specified for route location 0 at 3.0 V IOVDD with voltage scaling disabled. Slew rate for SD_CLK set to 6, all other GPIO set
to 6, DRIVESTRENGTH = STRONG for all pins. SDIO_CTRL_TXDLYMUXSEL = 1. Loading between 5 and 10 pF on all pins or between 10 and 40 pF on all pins.
Table 4.42. SDIO DS Mode Timing (Location 0)
Parameter
Symbol
Test Condition
Clock frequency during data
transfer
FSD_CLK
Clock low time
Clock high time
tWL
tWH
Min
Typ
Max
Unit
Using HFRCO, AUXHFRCO, or
USHFRCO
—
—
25
MHz
Using HFXO
—
—
21
MHz
Using HFRCO, AUXHFRCO, or
USHFRCO
18.3
—
—
ns
Using HFXO
18.14
—
—
ns
Using HFRCO, AUXHFRCO, or
USHFRCO
18.3
—
—
ns
Using HFXO
18.14
—
—
ns
Clock rise time
tR
1.49
—
4.86
ns
Clock fall time
tF
1.28
—
3.91
ns
Input setup time, CMD,
DAT[0:3] valid to SD_CLK
tISU
5
—
—
ns
Input hold time, SD_CLK to
CMD, DAT[0:3] change
tIH
0
—
—
ns
Output delay time, SD_CLK
to CMD, DAT[0:3] valid
tODLY
—
—
14
ns
5
—
—
ns
Min
Typ
Max
Unit
Output hold time, SD_CLK to tOH
CMD, DAT[0:3] change
Table 4.43. SDIO DS Mode Timing (Location 1)
Parameter
Symbol
Test Condition
Clock frequency during data
transfer
FSD_CLK
Using HFRCO, AUXHFRCO, or
USHFRCO
—
—
19
MHz
Using HFXO
—
—
15
MHz
Using HFRCO, AUXHFRCO, or
USHFRCO
24.1
—
—
ns
Using HFXO
23.8
—
—
ns
Using HFRCO, AUXHFRCO, or
USHFRCO
24.1
—
—
ns
Using HFXO
23.8
—
—
ns
Clock low time
Clock high time
tWL
tWH
Clock rise time
tR
1.49
—
4.86
ns
Clock fall time
tF
1.28
—
3.91
ns
silabs.com | Building a more connected world.
Rev. 1.0 | 84
EFM32GG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Input setup time, CMD,
DAT[0:3] valid to SD_CLK
Test Condition
Min
Typ
Max
Unit
tISU
5
—
—
ns
Input hold time, SD_CLK to
CMD, DAT[0:3] change
tIH
0
—
—
ns
Output delay time, SD_CLK
to CMD, DAT[0:3] valid
tODLY
—
—
19.1
ns
5
—
—
ns
Output hold time, SD_CLK to tOH
CMD, DAT[0:3] change
tWH
tWL
SD_CLK
tIH
tISU
CMD,
DAT[0:3]
Not Valid
Valid
Not Valid
Input Timing
SD_CLK
tODLY (max)
CMD,
DAT[0:3]
Not Valid
tOH (min)
Valid
Not Valid
Output Timing
Figure 4.9. SDIO DS Mode Timing
silabs.com | Building a more connected world.
Rev. 1.0 | 85
EFM32GG12 Family Data Sheet
Electrical Specifications
SDIO HS Mode Timing
Timing is specified for route location 0 at 3.0 V IOVDD with voltage scaling disabled. Slew rate for SD_CLK set to 7, all other GPIO set
to 6, DRIVESTRENGTH = STRONG for all pins. SDIO_CTRL_TXDLYMUXSEL = 0. Loading between 5 and 10 pF on all pins or between 10 and 20 pF on all pins.
Table 4.44. SDIO HS Mode Timing (Location 0)
Parameter
Symbol
Test Condition
Clock frequency during data
transfer
FSD_CLK
Clock low time
Clock high time
tWL
tWH
Min
Typ
Max
Unit
Using HFRCO, AUXHFRCO, or
USHFRCO
—
—
45
MHz
Using HFXO
—
—
45
MHz
Using HFRCO, AUXHFRCO, or
USHFRCO
10.57
—
—
ns
Using HFXO
8.66
—
—
ns
Using HFRCO, AUXHFRCO, or
USHFRCO
10.57
—
—
ns
Using HFXO
8.66
—
—
ns
Clock rise time
tR
0.83
—
3
ns
Input setup time, CMD,
DAT[0:3] valid to SD_CLK
tISU
3.2
—
—
ns
Input hold time, SD_CLK to
CMD, DAT[0:3] change
tIH
2.5
—
—
ns
Output delay time, SD_CLK
to CMD, DAT[0:3] valid
tODLY
—
—
15.3
ns
2
—
—
ns
Min
Typ
Max
Unit
Output hold time, SD_CLK to tOH
CMD, DAT[0:3] change
Table 4.45. SDIO HS Mode Timing (Location 1)
Parameter
Symbol
Test Condition
Clock frequency during data
transfer
FSD_CLK
Using HFRCO, AUXHFRCO, or
USHFRCO
—
—
35
MHz
Using HFXO
—
—
35
MHz
Using HFRCO, AUXHFRCO, or
USHFRCO
13.11
—
—
ns
Using HFXO
10.88
—
—
ns
Using HFRCO, AUXHFRCO, or
USHFRCO
13.11
—
—
ns
Using HFXO
10.88
—
—
ns
Clock low time
Clock high time
tWL
tWH
Clock rise time
tR
0.83
—
3
ns
Input setup time, CMD,
DAT[0:3] valid to SD_CLK
tISU
3.5
—
—
ns
Input hold time, SD_CLK to
CMD, DAT[0:3] change
tIH
2.5
—
—
ns
silabs.com | Building a more connected world.
Rev. 1.0 | 86
EFM32GG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Output delay time, SD_CLK
to CMD, DAT[0:3] valid
tODLY
Test Condition
Output hold time, SD_CLK to tOH
CMD, DAT[0:3] change
Min
Typ
Max
Unit
—
—
20.3
ns
2
—
—
ns
tWH
tWL
SD_CLK
tIH
tISU
CMD,
DAT[0:7]
Not Valid
Valid
Not Valid
Input Timing
SD_CLK
tODLY (max)
CMD,
DAT[0:7]
Not Valid
tOH (min)
Valid
Not Valid
Output Timing
Figure 4.10. SDIO HS Mode Timing
silabs.com | Building a more connected world.
Rev. 1.0 | 87
EFM32GG12 Family Data Sheet
Electrical Specifications
SDIO SDR Mode Timing
Timing is specified for route location 0 at 1.8 V IOVDD with voltage scaling disabled. Slew rate for SD_CLK set to 7, all other GPIO set
to 6, DRIVESTRENGTH = STRONG for all pins. SDIO_CTRL_TXDLYMUXSEL = 0. Loading between 5 and 10 pF on all pins or between 10 and 40 pF on all pins.
Table 4.46. SDIO SDR Mode Timing (Location 0)
Parameter
Symbol
Test Condition
Clock frequency during data
transfer
FSD_CLK
Clock low time
Clock high time
tWL
tWH
Min
Typ
Max
Unit
Using HFRCO, AUXHFRCO, or
USHFRCO
—
—
28
MHz
Using HFXO
—
—
28
MHz
Using HFRCO, AUXHFRCO, or
USHFRCO
16.4
—
—
ns
Using HFXO
13.61
—
—
ns
Using HFRCO, AUXHFRCO, or
USHFRCO
16.4
—
—
ns
Using HFXO
13.61
—
—
ns
1.8
—
6.56
ns
Clock rise time
tR
Input setup time, CMD,
DAT[0:3] valid to SD_CLK
tISU
5
—
—
ns
Input hold time, SD_CLK to
CMD, DAT[0:3] change
tIH
1.5
—
—
ns
Output delay time, SD_CLK
to CMD, DAT[0:3] valid
tODLY
—
—
20
ns
0.8
—
—
ns
Min
Typ
Max
Unit
Output hold time, SD_CLK to tOH
CMD, DAT[0:3] change
Table 4.47. SDIO SDR Mode Timing (Location 1)
Parameter
Symbol
Test Condition
Clock frequency during data
transfer
FSD_CLK
Using HFRCO, AUXHFRCO, or
USHFRCO
—
—
25
MHz
Using HFXO
—
—
25
MHz
Using HFRCO, AUXHFRCO, or
USHFRCO
18.36
—
—
ns
Using HFXO
15.24
—
—
ns
Using HFRCO, AUXHFRCO, or
USHFRCO
18.36
—
—
ns
Using HFXO
15.24
—
—
ns
1.8
—
6.56
ns
Clock low time
Clock high time
tWL
tWH
Clock rise time
tR
Input setup time, CMD,
DAT[0:3] valid to SD_CLK
tISU
5
—
—
ns
Input hold time, SD_CLK to
CMD, DAT[0:3] change
tIH
1.5
—
—
ns
silabs.com | Building a more connected world.
Rev. 1.0 | 88
EFM32GG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Output delay time, SD_CLK
to CMD, DAT[0:3] valid
tODLY
Test Condition
Output hold time, SD_CLK to tOH
CMD, DAT[0:3] change
Min
Typ
Max
Unit
—
—
24.3
ns
0.8
—
—
ns
tWH
tWL
SD_CLK
tIH
tISU
CMD,
DAT[0:7]
Not Valid
Valid
Not Valid
Input Timing
SD_CLK
tODLY (max)
CMD,
DAT[0:7]
Not Valid
tOH (min)
Valid
Not Valid
Output Timing
Figure 4.11. SDIO SDR Mode Timing
silabs.com | Building a more connected world.
Rev. 1.0 | 89
EFM32GG12 Family Data Sheet
Electrical Specifications
SDIO DDR Mode Timing
Timing is specified for route location 0 at 1.8 V IOVDD with voltage scaling disabled. Slew rate for SD_CLK set to 6, all other GPIO set
to 6, DRIVESTRENGTH = STRONG for all pins. SDIO_CTRL_TXDLYMUXSEL = 1. Loading between 5 and 10 pF on all pins or between 10 and 30 pF on all pins.
Table 4.48. SDIO DDR Mode Timing (Location 0)
Parameter
Symbol
Test Condition
Clock frequency during data
transfer
FSD_CLK
Clock low time
Clock high time
tWL
tWH
Min
Typ
Max
Unit
Using HFRCO, AUXHFRCO, or
USHFRCO
—
—
14
MHz
Using HFXO
—
—
11.5
MHz
Using HFRCO, AUXHFRCO, or
USHFRCO
34.5
—
—
ns
Using HFXO
34.7
—
—
ns
Using HFRCO, AUXHFRCO, or
USHFRCO
34.5
—
—
ns
Using HFXO
34.7
—
—
ns
Clock rise time
tR
1.79
—
6.56
ns
Clock fall time
tF
1.40
—
5.12
ns
Input setup time, CMD valid
to SD_CLK
tISU
6
—
—
ns
Input hold time, SD_CLK to
CMD change
tIH
1.5
—
—
ns
Output delay time, SD_CLK
to CMD valid
tODLY
—
—
21.1
ns
2
—
—
ns
Output hold time, SD_CLK to tOH
CMD change
Input setup time, DAT[0:3]
valid to SD_CLK
tISU2X
6.3
—
—
ns
Input hold time, SD_CLK to
DAT[0:3] change
tIH2X
1.5
—
—
ns
Output delay time, SD_CLK
to DAT[0:3] valid
tODLY2X
—
—
30.8
ns
2
—
—
ns
Min
Typ
Max
Unit
Output hold time, SD_CLK to tOH2X
DAT[0:3] change
Table 4.49. SDIO DDR Mode Timing (Location 1)
Parameter
Symbol
Test Condition
Clock frequency during data
transfer
FSD_CLK
Using HFRCO, AUXHFRCO, or
USHFRCO
—
—
12.5
MHz
Using HFXO
—
—
10
MHz
Using HFRCO, AUXHFRCO, or
USHFRCO
36.72
—
—
ns
Using HFXO
38.1
—
—
ns
Clock low time
tWL
silabs.com | Building a more connected world.
Rev. 1.0 | 90
EFM32GG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Clock high time
tWH
Using HFRCO, AUXHFRCO, or
USHFRCO
36.72
—
—
ns
Using HFXO
38.1
—
—
ns
Clock rise time
tR
1.79
—
6.56
ns
Clock fall time
tF
1.40
—
5.12
ns
Input setup time, CMD valid
to SD_CLK
tISU
7
—
—
ns
Input hold time, SD_CLK to
CMD change
tIH
1.5
—
—
ns
Output delay time, SD_CLK
to CMD valid
tODLY
—
—
24.81
ns
2
—
—
ns
Output hold time, SD_CLK to tOH
CMD change
Input setup time, DAT[0:3]
valid to SD_CLK
tISU2X
8.3
—
—
ns
Input hold time, SD_CLK to
DAT[0:3] change
tIH2X
1.5
—
—
ns
Output delay time, SD_CLK
to DAT[0:3] valid
tODLY2X
—
—
35.1
ns
2
—
—
ns
Output hold time, SD_CLK to tOH2X
DAT[0:3] change
tWL
tWH
SD_CLK
tISU2X tIH2X
DAT[0:3]
xxxx
Valid
tISU2X tIH2X
xxxx
Valid
xxxx
Valid
xxxx
Not Valid
xxxx
tIH
tISU
CMD
Valid
Valid
Not Valid
Input Timing
tWL
tWH
SD_CLK
DAT[0:3]
xxxx
tODLY2X (max)
tODLY2X (max)
tODLY2X (min)
tODLY2X (min)
Valid
xxxx
Valid
xxxx
Valid
Not Valid
Valid
xxxx
tOH (min)
tODLY (max)
CMD
xxxx
Valid
Not Valid
Output Timing
Figure 4.12. SDIO DDR Mode Timing
silabs.com | Building a more connected world.
Rev. 1.0 | 91
EFM32GG12 Family Data Sheet
Electrical Specifications
SDIO MMC Legacy Mode Timing
Timing is specified with voltage scaling disabled. Slew rate for SD_CLK set to 7, all other GPIO set to 6, DRIVESTRENGTH =
STRONG for all pins. SDIO_CTRL_TXDLYMUXSEL = 1. Loading between 5 and 10 pF on all pins or between 10 and 20 pF on all pins.
Table 4.50. SDIO MMC Legacy Mode Timing (Location 0)
Parameter
Symbol
Test Condition
Clock frequency during data
transfer
FSD_CLK
Clock low time
Clock high time
tWL
tWH
Min
Typ
Max
Unit
Using HFRCO, AUXHFRCO, or
USHFRCO
—
—
28
MHz
Using HFXO
—
—
28
MHz
Using HFRCO, AUXHFRCO, or
USHFRCO
16.96
—
—
ns
Using HFXO
14.28
—
—
ns
Using HFRCO, AUXHFRCO, or
USHFRCO
16.96
—
—
ns
Using HFXO
14.28
—
—
ns
Clock rise time
tR
1.8
—
5.6
ns
Input setup time, CMD,
DAT[0:7] valid to SD_CLK
tISU
4.8
—
—
ns
Input hold time, SD_CLK to
CMD, DAT[0:7] change
tIH
2.5
—
—
ns
Output delay time, SD_CLK
to CMD, DAT[0:7] valid
tODLY
—
—
18.8
ns
3
—
—
ns
Min
Typ
Max
Unit
Output hold time, SD_CLK to tOH
CMD, DAT[0:7] change
Table 4.51. SDIO MMC Legacy Mode Timing (Location 1)
Parameter
Symbol
Test Condition
Clock frequency during data
transfer
FSD_CLK
Using HFRCO, AUXHFRCO, or
USHFRCO
—
—
25
MHz
Using HFXO
—
—
25
MHz
Using HFRCO, AUXHFRCO, or
USHFRCO
18.3
—
—
ns
Using HFXO
15.2
—
—
ns
Using HFRCO, AUXHFRCO, or
USHFRCO
18.3
—
—
ns
Using HFXO
15.2
—
—
ns
Clock low time
Clock high time
tWL
tWH
Clock rise time
tR
1.8
—
5.6
ns
Input setup time, CMD,
DAT[0:7] valid to SD_CLK
tISU
4.8
—
—
ns
Input hold time, SD_CLK to
CMD, DAT[0:7] change
tIH
2.5
—
—
ns
Output delay time, SD_CLK
to CMD, DAT[0:7] valid
tODLY
—
—
23.6
ns
silabs.com | Building a more connected world.
Rev. 1.0 | 92
EFM32GG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Output hold time, SD_CLK to tOH
CMD, DAT[0:7] change
Min
Typ
Max
Unit
3
—
—
ns
tWH
tWL
SD_CLK
tIH
tISU
CMD,
DAT[0:7]
Not Valid
Valid
Not Valid
Input Timing
SD_CLK
tODLY (max)
CMD,
DAT[0:7]
Not Valid
tOH (min)
Valid
Not Valid
Output Timing
Figure 4.13. SDIO MMC Legacy Mode Timing
silabs.com | Building a more connected world.
Rev. 1.0 | 93
EFM32GG12 Family Data Sheet
Electrical Specifications
SDIO MMC SDR Mode Timing at 1.8 V
Timing is specified for route location 0 at 1.8 V IOVDD with voltage scaling disabled. Slew rate for SD_CLK set to 7, all other GPIO set
to 6, DRIVESTRENGTH = STRONG for all pins. SDIO_CTRL_TXDLYMUXSEL = 1. Loading between 5 and 10 pF on all pins or between 10 and 20 pF on all pins.
Table 4.52. SDIO MMC SDR Mode Timing (Location 0, 1.8V I/O)
Parameter
Symbol
Test Condition
Clock frequency during data
transfer
FSD_CLK
Clock low time
Clock high time
tWL
tWH
Min
Typ
Max
Unit
Using HFRCO, AUXHFRCO, or
USHFRCO
—
—
28
MHz
Using HFXO
—
—
28
MHz
Using HFRCO, AUXHFRCO, or
USHFRCO
16.96
—
—
ns
Using HFXO
14.28
—
—
ns
Using HFRCO, AUXHFRCO, or
USHFRCO
16.96
—
—
ns
Using HFXO
14.28
—
—
ns
Clock rise time
tR
1.8
—
5.6
ns
Input setup time, CMD,
DAT[0:7] valid to SD_CLK
tISU
4.8
—
—
ns
Input hold time, SD_CLK to
CMD, DAT[0:7] change
tIH
2.5
—
—
ns
Output delay time, SD_CLK
to CMD, DAT[0:7] valid
tODLY
—
—
18.8
ns
2.85
—
—
ns
Min
Typ
Max
Unit
Output hold time, SD_CLK to tOH
CMD, DAT[0:7] change
Table 4.53. SDIO MMC SDR Mode Timing (Location 1, 1.8V I/O)
Parameter
Symbol
Test Condition
Clock frequency during data
transfer
FSD_CLK
Using HFRCO, AUXHFRCO, or
USHFRCO
—
—
25
MHz
Using HFXO
—
—
25
MHz
Using HFRCO, AUXHFRCO, or
USHFRCO
18.3
—
—
ns
Using HFXO
15.2
—
—
ns
Using HFRCO, AUXHFRCO, or
USHFRCO
18.3
—
—
ns
Using HFXO
15.2
—
—
ns
Clock low time
Clock high time
tWL
tWH
Clock rise time
tR
1.8
—
5.6
ns
Input setup time, CMD,
DAT[0:7] valid to SD_CLK
tISU
4.8
—
—
ns
Input hold time, SD_CLK to
CMD, DAT[0:7] change
tIH
2.5
—
—
ns
silabs.com | Building a more connected world.
Rev. 1.0 | 94
EFM32GG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Output delay time, SD_CLK
to CMD, DAT[0:7] valid
tODLY
Test Condition
Min
Typ
Max
Unit
—
—
23.6
ns
3
—
—
ns
Output hold time, SD_CLK to tOH
CMD, DAT[0:7] change
tWH
tWL
SD_CLK
tIH
tISU
CMD,
DAT[0:7]
Not Valid
Valid
Not Valid
Input Timing
SD_CLK
tODLY (max)
CMD,
DAT[0:7]
Not Valid
tOH (min)
Valid
Not Valid
Output Timing
Figure 4.14. SDIO MMC SDR Mode Timing
silabs.com | Building a more connected world.
Rev. 1.0 | 95
EFM32GG12 Family Data Sheet
Electrical Specifications
SDIO MMC SDR Mode Timing at 3.0 V
Timing is specified for route location 0 at 3.0 V IOVDD with voltage scaling disabled. Slew rate for SD_CLK set to 7, all other GPIO set
to 6, DRIVESTRENGTH = STRONG for all pins. SDIO_CTRL_TXDLYMUXSEL = 1. Loading between 5 and 10 pF on all pins or between 10 and 20 pF on all pins.
Table 4.54. SDIO MMC SDR Mode Timing (Location 0, 3V I/O)
Parameter
Symbol
Test Condition
Clock frequency during data
transfer
FSD_CLK
Clock low time
Clock high time
tWL
tWH
Min
Typ
Max
Unit
Using HFRCO, AUXHFRCO, or
USHFRCO
—
—
49
MHz
Using HFXO
—
—
49
MHz
Using HFRCO, AUXHFRCO, or
USHFRCO
9.7
—
—
ns
Using HFXO
7.8
—
—
ns
Using HFRCO, AUXHFRCO, or
USHFRCO
9.7
—
—
ns
Using HFXO
7.8
—
—
ns
Clock rise time
tR
0.85
—
2.5
ns
Input setup time, CMD,
DAT[0:7] valid to SD_CLK
tISU
3.13
—
—
ns
Input hold time, SD_CLK to
CMD, DAT[0:7] change
tIH
2.5
—
—
ns
Output delay time, SD_CLK
to CMD, DAT[0:7] valid
tODLY
—
—
15.2
ns
3
—
—
ns
Min
Typ
Max
Unit
Output hold time, SD_CLK to tOH
CMD, DAT[0:7] change
Table 4.55. SDIO MMC SDR Mode Timing (Location 1, 3V I/O)
Parameter
Symbol
Test Condition
Clock frequency during data
transfer
FSD_CLK
Using HFRCO, AUXHFRCO, or
USHFRCO
—
—
38
MHz
Using HFXO
—
—
38
MHz
Using HFRCO, AUXHFRCO, or
USHFRCO
12
—
—
ns
Using HFXO
10
—
—
ns
Using HFRCO, AUXHFRCO, or
USHFRCO
12
—
—
ns
Using HFXO
10
—
—
ns
Clock low time
Clock high time
tWL
tWH
Clock rise time
tR
0.85
—
2.5
ns
Input setup time, CMD,
DAT[0:7] valid to SD_CLK
tISU
3.4
—
—
ns
Input hold time, SD_CLK to
CMD, DAT[0:7] change
tIH
2.5
—
—
ns
silabs.com | Building a more connected world.
Rev. 1.0 | 96
EFM32GG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Output delay time, SD_CLK
to CMD, DAT[0:7] valid
tODLY
Test Condition
Min
Typ
Max
Unit
—
—
19.83
ns
3
—
—
ns
Output hold time, SD_CLK to tOH
CMD, DAT[0:7] change
tWH
tWL
SD_CLK
tIH
tISU
CMD,
DAT[0:7]
Not Valid
Valid
Not Valid
Input Timing
SD_CLK
tODLY (max)
CMD,
DAT[0:7]
Not Valid
tOH (min)
Valid
Not Valid
Output Timing
Figure 4.15. SDIO MMC SDR Mode Timing
silabs.com | Building a more connected world.
Rev. 1.0 | 97
EFM32GG12 Family Data Sheet
Electrical Specifications
SDIO MMC DDR Mode Timing at 1.8 V
Timing is specified for route location 0 at 1.8 V IOVDD with voltage scaling disabled. Slew rate for SD_CLK set to 7, all other GPIO set
to 6, DRIVESTRENGTH = STRONG for all pins. SDIO_CTRL_TXDLYMUXSEL = 1. Loading between 5 and 10 pF on all pins or between 10 and 25 pF on all pins.
Table 4.56. SDIO MMC DDR Mode Timing (Location 0, 1.8V I/O)
Parameter
Symbol
Test Condition
Clock frequency during data
transfer
FSD_CLK
Clock low time
Clock high time
tWL
tWH
Min
Typ
Max
Unit
Using HFRCO, AUXHFRCO, or
USHFRCO
—
—
14.5
MHz
Using HFXO
—
—
12
MHz
Using HFRCO, AUXHFRCO, or
USHFRCO
31.6
—
—
ns
Using HFXO
31.2
—
—
ns
Using HFRCO, AUXHFRCO, or
USHFRCO
31.6
—
—
ns
Using HFXO
31.2
—
—
ns
Clock rise time
tR
1.79
—
5.54
ns
Clock fall time
tF
1.40
—
4.21
ns
Input setup time, CMD valid
to SD_CLK
tISU
5.7
—
—
ns
Input hold time, SD_CLK to
CMD change
tIH
2.5
—
—
ns
Output delay time, SD_CLK
to CMD valid
tODLY
—
—
19.81
ns
3
—
—
ns
Output hold time, SD_CLK to tOH
CMD change
Input setup time, DAT[0:7]
valid to SD_CLK
tISU2X
7.6
—
—
ns
Input hold time, SD_CLK to
DAT[0:7] change
tIH2X
2.5
—
—
ns
Output delay time, SD_CLK
to DAT[0:7] valid
tODLY2X
—
—
30.3
ns
3
—
—
ns
Min
Typ
Max
Unit
Output hold time, SD_CLK to tOH2X
DAT[0:7] change
Table 4.57. SDIO MMC DDR Mode Timing (Location 1, 1.8V I/O)
Parameter
Symbol
Test Condition
Clock frequency during data
transfer
FSD_CLK
Using HFRCO, AUXHFRCO, or
USHFRCO
—
—
12
MHz
Using HFXO
—
—
10
MHz
38.2
—
—
ns
38
—
—
ns
Clock low time
tWL
Using HFRCO, AUXHFRCO, or
USHFRCO
Using HFXO
silabs.com | Building a more connected world.
Rev. 1.0 | 98
EFM32GG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Clock high time
tWH
Using HFRCO, AUXHFRCO, or
USHFRCO
38.2
—
—
ns
38
—
—
ns
Using HFXO
Clock rise time
tR
1.79
—
5.54
ns
Clock fall time
tF
1.40
—
4.21
ns
Input setup time, CMD valid
to SD_CLK
tISU
7.1
—
—
ns
Input hold time, SD_CLK to
CMD change
tIH
2.5
—
—
ns
Output delay time, SD_CLK
to CMD valid
tODLY
—
—
23.87
ns
3
—
—
ns
Output hold time, SD_CLK to tOH
CMD change
Input setup time, DAT[0:7]
valid to SD_CLK
tISU2X
8.24
—
—
ns
Input hold time, SD_CLK to
DAT[0:7] change
tIH2X
2.5
—
—
ns
Output delay time, SD_CLK
to DAT[0:7] valid
tODLY2X
—
—
34.94
ns
3
—
—
ns
Output hold time, SD_CLK to tOH2X
DAT[0:7] change
tWL
tWH
SD_CLK
tISU2X tIH2X
DAT[0:7]
xxxx
Valid
tISU2X tIH2X
xxxx
Valid
xxxx
Valid
xxxx
Not Valid
xxxx
tIH
tISU
CMD
Valid
Valid
Not Valid
Input Timing
tWL
tWH
SD_CLK
DAT[0:7]
xxxx
tODLY2X (max)
tODLY2X (max)
tODLY2X (min)
tODLY2X (min)
Valid
xxxx
Valid
xxxx
Valid
Not Valid
Valid
xxxx
tOH (min)
tODLY (max)
CMD
xxxx
Valid
Not Valid
Output Timing
Figure 4.16. SDIO MMC DDR Mode Timing
silabs.com | Building a more connected world.
Rev. 1.0 | 99
EFM32GG12 Family Data Sheet
Electrical Specifications
SDIO MMC DDR Mode Timing at 3.0 V
Timing is specified for route location 0 at 3.0 V IOVDD with voltage scaling disabled. Slew rate for SD_CLK set to 7, all other GPIO set
to 6, DRIVESTRENGTH = STRONG for all pins. SDIO_CTRL_TXDLYMUXSEL = 1. Loading between 5 and 10 pF on all pins or between 10 and 25 pF on all pins.
Table 4.58. SDIO MMC DDR Mode Timing (Location 0, 3V I/O)
Parameter
Symbol
Test Condition
Clock frequency during data
transfer
FSD_CLK
Clock low time
Clock high time
tWL
tWH
Min
Typ
Max
Unit
Using HFRCO, AUXHFRCO, or
USHFRCO
—
—
16
MHz
Using HFXO
—
—
13.5
MHz
Using HFRCO, AUXHFRCO, or
USHFRCO
29.69
—
—
ns
Using HFXO
29.63
—
—
ns
Using HFRCO, AUXHFRCO, or
USHFRCO
29.69
—
—
ns
Using HFXO
29.63
—
—
ns
Clock rise time
tR
0.84
—
2.5
ns
Clock fall time
tF
0.77
—
2.2
ns
Input setup time, CMD valid
to SD_CLK
tISU
4.3
—
—
ns
Input hold time, SD_CLK to
CMD change
tIH
2.5
—
—
ns
Output delay time, SD_CLK
to CMD valid
tODLY
—
—
16.47
ns
Output hold time, SD_CLK to tOH
CMD change
3
—
—
ns
Input setup time, DAT[0:7]
valid to SD_CLK
tISU2X
6
—
—
ns
Input hold time, SD_CLK to
DAT[0:7] change
tIH2X
2.5
—
—
ns
Output delay time, SD_CLK
to DAT[0:7] valid
tODLY2X
—
—
26.6
ns
3
—
—
ns
Min
Typ
Max
Unit
Output hold time, SD_CLK to tOH2X
DAT[0:7] change
Table 4.59. SDIO MMC DDR Mode Timing (Location 1, 3V I/O)
Parameter
Symbol
Test Condition
Clock frequency during data
transfer
FSD_CLK
Using HFRCO, AUXHFRCO, or
USHFRCO
—
—
12.5
MHz
Using HFXO
—
—
11
MHz
Using HFRCO, AUXHFRCO, or
USHFRCO
36.7
—
—
ns
Using HFXO
34.6
—
—
ns
Clock low time
tWL
silabs.com | Building a more connected world.
Rev. 1.0 | 100
EFM32GG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Clock high time
tWH
Using HFRCO, AUXHFRCO, or
USHFRCO
36.7
—
—
ns
Using HFXO
34.6
—
—
ns
Clock rise time
tR
0.84
—
2.5
ns
Clock fall time
tF
0.77
—
2.2
ns
Input setup time, CMD valid
to SD_CLK
tISU
5.1
—
—
ns
Input hold time, SD_CLK to
CMD change
tIH
2.5
—
—
ns
Output delay time, SD_CLK
to CMD valid
tODLY
—
—
20.9
ns
3
—
—
ns
Output hold time, SD_CLK to tOH
CMD change
Input setup time, DAT[0:7]
valid to SD_CLK
tISU2X
6.8
—
—
ns
Input hold time, SD_CLK to
DAT[0:7] change
tIH2X
2.5
—
—
ns
Output delay time, SD_CLK
to DAT[0:7] valid
tODLY2X
—
—
31.37
ns
3
—
—
ns
Output hold time, SD_CLK to tOH2X
DAT[0:7] change
tWL
tWH
SD_CLK
tISU2X tIH2X
DAT[0:7]
xxxx
Valid
tISU2X tIH2X
xxxx
Valid
xxxx
Valid
xxxx
Not Valid
xxxx
tIH
tISU
CMD
Valid
Valid
Not Valid
Input Timing
tWL
tWH
SD_CLK
DAT[0:7]
xxxx
tODLY2X (max)
tODLY2X (max)
tODLY2X (min)
tODLY2X (min)
Valid
xxxx
Valid
xxxx
Valid
Not Valid
Valid
xxxx
tOH (min)
tODLY (max)
CMD
xxxx
Valid
Not Valid
Output Timing
Figure 4.17. SDIO MMC DDR Mode Timing
silabs.com | Building a more connected world.
Rev. 1.0 | 101
EFM32GG12 Family Data Sheet
Electrical Specifications
SDIO SPI Mode Timing
Timing is specified for route location 0 at 3.0 V IOVDD with voltage scaling disabled. Slew rate for SD_CLK set to 6, all other GPIO set
to 6, DRIVESTRENGTH = STRONG for all pins. SDIO_CTRL_TXDLYMUXSEL = 1. Loading between 5 and 10 pF on all pins or between 10 and 40 pF on all pins.
Table 4.60. SDIO SPI Mode Timing (Location 0)
Parameter
Symbol
Test Condition
Clock frequency during data
transfer
FSCLK
Clock low time
Clock high time
tWL
tWH
Min
Typ
Max
Unit
Using HFRCO, AUXHFRCO, or
USHFRCO
—
—
25
MHz
Using HFXO
—
—
21
MHz
Using HFRCO, AUXHFRCO, or
USHFRCO
18.3
—
—
ns
Using HFXO
18.14
—
—
ns
Using HFRCO, AUXHFRCO, or
USHFRCO
18.3
—
—
ns
Using HFXO
18.14
—
—
ns
Clock rise time
tR
1.49
—
4.86
ns
Clock fall time
tF
1.28
—
3.91
ns
Input setup time, MISO valid
to SCLK
tISU
5
—
—
ns
Input hold time, SCLK to MISO change
tIH
0
—
—
ns
Output delay time, SCLK to
MOSI valid
tODLY
—
—
14
ns
Output hold time, SCLK to
MOSI change
tOH
5
—
—
ns
Min
Typ
Max
Unit
Table 4.61. SDIO SPI Mode Timing (Location 1)
Parameter
Symbol
Test Condition
Clock frequency during data
transfer
FSCLK
Using HFRCO, AUXHFRCO, or
USHFRCO
—
—
19
MHz
Using HFXO
—
—
15
MHz
Using HFRCO, AUXHFRCO, or
USHFRCO
24.1
—
—
ns
Using HFXO
23.8
—
—
ns
Using HFRCO, AUXHFRCO, or
USHFRCO
24.1
—
—
ns
Using HFXO
23.8
—
—
ns
Clock low time
Clock high time
tWL
tWH
Clock rise time
tR
1.49
—
4.86
ns
Clock fall time
tF
1.28
—
3.91
ns
Input setup time, MISO valid
to SCLK
tISU
5
—
—
ns
silabs.com | Building a more connected world.
Rev. 1.0 | 102
EFM32GG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Input hold time, SCLK to MISO change
Test Condition
Min
Typ
Max
Unit
tIH
0
—
—
ns
Output delay time, SCLK to
MOSI valid
tODLY
—
—
19.1
ns
Output hold time, SCLK to
MOSI change
tOH
5
—
—
ns
tWH
tWL
SCLK
tISU
tIH
MISO
tODLY (max)
tOH (min)
MOSI
Figure 4.18. SDIO SPI Mode Timing
4.1.27 Quad SPI (QSPI)
4.1.27.1 QSPI SDR Mode
QSPI SDR Mode Timing (Location 0)
Timing is specified with voltage scaling disabled, PHY-mode, route location 0 only, TX DLL = 20, RX DLL = 45, 5-25 pF loading per
GPIO, and slew rate for all GPIO set to 6, DRIVESTRENGTH = STRONG.
Table 4.62. QSPI SDR Mode Timing (Location 0)
Parameter
Symbol
Full SCLK period
T
Output valid
Min
Typ
Max
Unit
(1/FSCLK) *
0.965
—
—
ns
tOV
—
—
T/2 - 3.0
ns
Output hold
tOH
T/2 - 21.4
—
—
ns
Input setup
tSU
25.96 - T/2
—
—
ns
Input hold
tH
T/2 - 1.0
—
—
ns
silabs.com | Building a more connected world.
Test Condition
Rev. 1.0 | 103
EFM32GG12 Family Data Sheet
Electrical Specifications
QSPI SDR Mode Timing (Optimal Conditions)
Timing is specified at IOVDD ≥ 3.0V, using internal HFRCO oscillator and with voltage scaling disabled, PHY-mode, route location 0
only, TX DLL = 17, RX DLL = 29, 5-25 pF loading per GPIO, and slew rate for all GPIO set to 6, DRIVESTRENGTH = STRONG.
Table 4.63. QSPI SDR Mode Timing (Optimized at 3.0V, Location 0)
Parameter
Symbol
Full SCLK period
T
Output valid
Min
Typ
Max
Unit
(1/FSCLK) *
0.965
—
—
ns
tOV
—
—
T/2 - 2.2
ns
Output hold
tOH
T/2 - 19.13
—
—
ns
Input setup
tSU
15.33 - T/2
—
—
ns
Input hold
tH
T/2 - 4.1
—
—
ns
silabs.com | Building a more connected world.
Test Condition
Rev. 1.0 | 104
EFM32GG12 Family Data Sheet
Electrical Specifications
QSPI SDR Mode Timing (Locations 1, 2)
Timing is specified with voltage scaling disabled, PHY-mode, route locations other than 0, TX DLL = 15, RX DLL = 47, 5-25 pF loading
per GPIO, and slew rate for all GPIO set to 6, DRIVESTRENGTH = STRONG.
Table 4.64. QSPI SDR Mode Timing (Locations 1, 2)
Parameter
Symbol
Full SCLK period
T
Output valid
Test Condition
Min
Typ
Max
Unit
(1/FSCLK) *
0.965
—
—
ns
tOV
—
—
T/2 - 2.6
ns
Output hold
tOH
T/2 - 19.26
—
—
ns
Input setup
tSU
25.47 - T/2
—
—
ns
Input hold
tH
T/2 - 0.5
—
—
ns
DQx Output Timing
tOV
SCLK
tOH
DQx
DQx Input Timing
SCLK
tSU
tH
DQx
Figure 4.19. QSPI SDR Timing Diagrams
QSPI SDR Flash Timing Example
This example uses timing values from SDR Mode Timing (Optimal Conditions) to demonstrate the calculation of allowable flash timing
using the QSPI in SDR mode.
• Using a configured SCLK frequency (FSCLK) of 40 MHz:
• The resulting minimum period, T(min) = (1/FSCLK) * 0.965 = 24.125 ns.
• Flash will see a minimum setup time of T/2 – tOV = T/2 – (T/2 – 2.2) = 2.4 ns.
• Flash will see a minimum hold time of T/2 + tOH = T/2 + (T/2 – 19.13) = T – 19.13 = 24.125 – 19.13 = 4.9 ns.
• Flash can have a maximum output valid time of T/2 – tSU = T/2 – (15.33 – T/2) = T – 15.33 = 24.125 – 15.33 = 8.8 ns.
• Flash can have a minimum output hold time of tH – T/2 = (T/2 – 4.1) – T/2 = - 4.1 ns.
silabs.com | Building a more connected world.
Rev. 1.0 | 105
EFM32GG12 Family Data Sheet
Electrical Specifications
4.1.27.2 QSPI DDR Mode
QSPI DDR Mode Timing (Location 0)
Timing is specified with voltage scaling disabled, PHY-mode, route location 0 only, TX DLL = 20, RX DLL = 52, 5-25 pF loading per
GPIO, and slew rate for all GPIO set to 6, DRIVESTRENGTH = STRONG.
Table 4.65. QSPI DDR Mode Timing (Location 0)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Half SCLK period
T/2
HFXO
(1/FSCLK) *
0.4 - 0.4
—
—
ns
HFRCO, AUXHFRCO, USHFRCO (1/FSCLK) *
0.44
—
—
ns
Output valid
tOV
—
—
T/2 - 2.3
ns
Output hold
tOH
T/2 - 18.63
—
—
ns
Input setup
tSU
14.85
—
—
ns
Input hold
tH
-2.2
—
—
ns
QSPI DDR Mode Timing (Optimal Conditions)
Timing is specified at IOVDD ≥ 3.0V, using internal HFRCO oscillator and with voltage scaling disabled, PHY-mode, route location 0
only, TX DLL = 17, RX DLL = 37, 5-25 pF loading per GPIO, and slew rate for all GPIO set to 6, DRIVESTRENGTH = STRONG.
Table 4.66. QSPI DDR Mode Timing (Optimized at 3.0V, Location 0)
Parameter
Symbol
Test Condition
Typ
Max
Unit
Half SCLK period
T/2
HFRCO, AUXHFRCO, USHFRCO (1/FSCLK) *
0.44
—
—
ns
Output valid
tOV
—
—
T/2 - 2.4
ns
Output hold
tOH
T/2 - 19.02
—
—
ns
Input setup
tSU
12.93
—
—
ns
Input hold
tH
-0.8
—
—
ns
silabs.com | Building a more connected world.
Min
Rev. 1.0 | 106
EFM32GG12 Family Data Sheet
Electrical Specifications
QSPI DDR Mode Timing (Locations 1, 2)
Timing is specified with voltage scaling disabled, PHY-mode, route locations other than 0, TX DLL = 17, RX DLL = 50, 5-25 pF loading
per GPIO, and slew rate for all GPIO set to 6, DRIVESTRENGTH = STRONG.
Table 4.67. QSPI DDR Mode Timing (Locations 1, 2)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Half SCLK period
T/2
HFXO
(1/FSCLK) *
0.4 - 0.4
—
—
ns
HFRCO, AUXHFRCO, USHFRCO (1/FSCLK) *
0.44
—
—
ns
Output valid
tOV
—
—
T/2 - 2.8
ns
Output hold
tOH
T/2 - 15.21
—
—
ns
Input setup
tSU
9.2
—
—
ns
Input hold
tH
-0.38
—
—
ns
DQx Output Timing
tOV
tOV
SCLK
tOH
tOH
DQx
DQx Input Timing
SCLK
tSU
tH
tSU
tH
DQx
Figure 4.20. QSPI DDR Timing Diagrams
QSPI DDR Flash Timing Example
This example uses timing values for DDR Mode Timing (Optimal Conditions) to demonstrate the calculation of allowable flash timing
using the QSPI in DDR mode.
• Using a configured SCLK frequency (FSCLK) of 20 MHz from the HFXO clock source:
• The resulting minimum half-period, T/2(min) = (1/FSCLK) * 0.44 = 22 ns.
• Flash will see a minimum setup time of T/2 – tOV = T/2 – (T/2 – 2.2) = 2.4 ns.
• Flash will see a minimum hold time of tOH = T/2 – 19.02 = 22 – 19.02 = 2.98 ns.
• Flash can have a maximum output valid time of T/2 – tSU = T/2 – 12.93 = 22 – 12.93 = 9.07 ns.
• Flash can have a minimum output hold time of tH = - 0.8 ns.
silabs.com | Building a more connected world.
Rev. 1.0 | 107
EFM32GG12 Family Data Sheet
Electrical Specifications
4.1.28 PDM
PDM Timing
Timing is specified for all route locations, 10 pF to 25 pF loading on PDM_CLK, and slew rate for PDM_CLK set to 7.
Table 4.68. Pulse Density Modulation (PDM) Timing
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
PDM_CLK frequency during
data transfer
FPDM_CLK
Microphone mode, VSCALE2 or
VSCALE0
—
—
4.8
MHz
Sensor mode, VSCALE2
—
—
20
MHz
Sensor mode, VSCALE0
—
—
10
MHz
47.5
—
52.5
%
PDM_CLK duty cycle
DCPDM_CLK
PDM_CLK rise time
tR
—
—
7.5
ns
PDM_CLK fall time
tF
—
—
7.5
ns
Input setup time
tISU
20
—
—
ns
Input hold time
tIH
VSCALE2
3
—
—
ns
VSCALE0
4
—
—
ns
PDM Microphone Mode
PDM_CLK
tISU
PDM_DAT0-3
L
tIH
tISU
R
tIH
L
R
L
PDM Sensor Mode
PDM_CLK
tISU
tIH
PDM_DAT0-3
Figure 4.21. PDM Timing Diagrams
4.2 Typical Performance Curves
Typical performance curves indicate typical characterized performance under the stated conditions.
silabs.com | Building a more connected world.
Rev. 1.0 | 108
EFM32GG12 Family Data Sheet
Electrical Specifications
4.2.1 Supply Current
Figure 4.22. EM0 Full Speed Active Mode Typical Supply Current vs. Temperature
silabs.com | Building a more connected world.
Rev. 1.0 | 109
EFM32GG12 Family Data Sheet
Electrical Specifications
Figure 4.23. EM0 Active Mode Typical Supply Current vs. Temperature
silabs.com | Building a more connected world.
Rev. 1.0 | 110
EFM32GG12 Family Data Sheet
Electrical Specifications
Figure 4.24. EM1 Sleep Mode Typical Supply Current vs. Temperature
Typical supply current for EM2, EM3 and EM4H using standard software libraries from Silicon Laboratories.
silabs.com | Building a more connected world.
Rev. 1.0 | 111
EFM32GG12 Family Data Sheet
Electrical Specifications
Figure 4.25. EM2, EM3, EM4H and EM4S Typical Supply Current vs. Temperature
silabs.com | Building a more connected world.
Rev. 1.0 | 112
EFM32GG12 Family Data Sheet
Electrical Specifications
Figure 4.26. EM0 and EM1 Mode Typical Supply Current vs. Supply
Typical supply current for EM2, EM3 and EM4H using standard software libraries from Silicon Laboratories.
silabs.com | Building a more connected world.
Rev. 1.0 | 113
EFM32GG12 Family Data Sheet
Electrical Specifications
Figure 4.27. EM2, EM3, EM4H and EM4S Typical Supply Current vs. Supply
silabs.com | Building a more connected world.
Rev. 1.0 | 114
EFM32GG12 Family Data Sheet
Electrical Specifications
4.2.2 DC-DC Converter
Default test conditions: CCM mode, LDCDC = 4.7 μH, CDCDC = 4.7 μF, VDCDC_I = 3.3 V, VDCDC_O = 1.8 V, FDCDC_LN = 7 MHz
Figure 4.28. DC-DC Converter Typical Performance Characteristics
silabs.com | Building a more connected world.
Rev. 1.0 | 115
EFM32GG12 Family Data Sheet
Electrical Specifications
Load Step Response in LN (CCM) mode
(Heavy Drive)
LN (CCM) and LP mode transition (load: 5mA)
DVDD
DVDD
60mV/div
offset:1.8V
20mV/div
offset:1.8V
100mA
VSW
ILOAD
1mA
2V/div
offset:1.8V
100μs/div
10μs/div
Figure 4.29. DC-DC Converter Transition Waveforms
silabs.com | Building a more connected world.
Rev. 1.0 | 116
EFM32GG12 Family Data Sheet
Pin Definitions
5. Pin Definitions
5.1 EFM32GG12B8xx in BGA120 Device Pinout
Figure 5.1. EFM32GG12B8xx in BGA120 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 5.20 GPIO Functionality Table or 5.21 Alternate Functionality Overview.
Table 5.1. EFM32GG12B8xx in BGA120 Device Pinout
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PE15
A1
GPIO
PE14
A2
GPIO
PE12
A3
GPIO
PE9
A4
GPIO
PD11
A5
GPIO
PD9
A6
GPIO
PF7
A7
GPIO
PF5
A8
GPIO
PF14
A9
GPIO (5V)
PF12
A10
GPIO (5V)
silabs.com | Building a more connected world.
Rev. 1.0 | 117
EFM32GG12 Family Data Sheet
Pin Definitions
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
VREGO
A12
Decoupling for 5 V regulator and regulator output. Power for USB PHY in
USB-enabled OPNs
GPIO (5V)
PA15
B1
GPIO
B2
GPIO
PE11
B3
GPIO
PE8
B4
GPIO
PD12
B5
GPIO
PD10
B6
GPIO
PF8
B7
GPIO
PF6
B8
GPIO
PF13
B9
GPIO (5V)
PF4
B10
GPIO
PF3
B11
GPIO
VBUS
B12
USB VBUS signal and auxiliary input to
5 V regulator.
PF10
B13
GPIO (5V)
PA1
C1
GPIO
PA0
C2
GPIO
PE10
C3
GPIO
PD13
C4
GPIO (5V)
VSS
C5
C8
H3
J3
K11
L5
L8
Ground
IOVDD1
C6
Digital IO power supply 1.
Digital IO power supply 0.
VREGI
A11
Input to 5 V regulator.
PF11
A13
PE13
PF9
C7
GPIO
IOVDD0
C9
G3
J11
K3
L4
L9
PF2
C10
GPIO
PF1
C11
GPIO (5V)
PC14
C12
GPIO (5V)
PC15
C13
GPIO (5V)
PA3
D1
GPIO
PA2
D2
GPIO
PB15
D3
GPIO (5V)
PF0
D11
GPIO (5V)
PC12
D12
GPIO (5V)
PC13
D13
GPIO (5V)
PA6
E1
GPIO
PA5
E2
GPIO
PA4
E3
GPIO
PC9
E11
GPIO (5V)
PC10
E12
GPIO (5V)
PC11
E13
GPIO (5V)
PB0
F1
GPIO
PB1
F2
GPIO
PB2
F3
GPIO
PE6
F11
GPIO
PE7
F12
GPIO
PC8
F13
GPIO (5V)
PB3
G1
GPIO
PB4
G2
GPIO
PE3
G11
GPIO
PE4
G12
GPIO
PE5
G13
GPIO
PB5
H1
GPIO
PB6
H2
GPIO
DVDD
H11
Digital power supply.
silabs.com | Building a more connected world.
Rev. 1.0 | 118
EFM32GG12 Family Data Sheet
Pin Definitions
Pin Name
Pin(s)
PE2
H12
PD14
J1
PE1
Description
GPIO
Pin Name
Pin(s)
Description
Decouple output for on-chip voltage
regulator. An external decoupling capacitor is required at this pin. This pin
should not be used to power any external circuits.
DECOUPLE
H13
GPIO (5V)
PD15
J2
GPIO (5V)
J12
GPIO (5V)
VREGVDD
J13
Voltage regulator VDD input
PC0
K1
GPIO (5V)
PC1
K2
GPIO (5V)
PE0
K12
GPIO (5V)
VREGSW
K13
DCDC regulator switching node
PC2
L1
GPIO (5V)
PC3
L2
GPIO (5V)
PA7
L3
GPIO
PB9
L6
GPIO (5V)
PB10
L7
GPIO (5V)
PD1
L10
GPIO
PC6
L11
GPIO
PC7
L12
GPIO
VREGVSS
L13
Voltage regulator VSS
PB7
M1
GPIO
PC4
M2
GPIO
PA8
M3
GPIO
PA10
M4
GPIO
PA13
M5
GPIO (5V)
PA14
M6
GPIO
RESETn
M7
Reset input, active low. This pin is internally pulled up to AVDD. To apply an
external reset source to this pin, it is required to only drive this pin low during
reset, and let the internal pull-up ensure
that reset is released.
PB12
M8
GPIO
PD0
M9
GPIO (5V)
PD2
M10
GPIO (5V)
PD3
M11
GPIO
PD4
M12
GPIO
PD8
M13
GPIO
PB8
N1
GPIO
PC5
N2
GPIO
PA9
N3
GPIO
PA11
N4
GPIO
PA12
N5
GPIO (5V)
PB11
N6
GPIO
BODEN
N7
Brown-Out Detector Enable. This pin
may be left disconnected or tied to
AVDD.
PB13
N8
GPIO
PB14
N9
GPIO
AVDD
N10
Analog power supply.
PD5
N11
GPIO
PD6
N12
GPIO
PD7
N13
GPIO
Note:
1. GPIO with 5V tolerance are indicated by (5V).
2. The pins PD13, PD14, and PD15 will not be 5V tolerant on all future devices. In order to preserve upgrade options with full hardware compatibility, do not use these pins with 5V domains.
silabs.com | Building a more connected world.
Rev. 1.0 | 119
EFM32GG12 Family Data Sheet
Pin Definitions
5.2 EFM32GG12B5xx in BGA120 Device Pinout
Figure 5.2. EFM32GG12B5xx in BGA120 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 5.20 GPIO Functionality Table or 5.21 Alternate Functionality Overview.
Table 5.2. EFM32GG12B5xx in BGA120 Device Pinout
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PE15
A1
GPIO
PE14
A2
GPIO
PE12
A3
GPIO
PE9
A4
GPIO
PD11
A5
GPIO
PD9
A6
GPIO
PF7
A7
GPIO
PF5
A8
GPIO
PF14
A9
GPIO (5V)
PF12
A10
GPIO (5V)
VREGI
A11
Input to 5 V regulator.
VREGO
A12
Decoupling for 5 V regulator and regulator output. Power for USB PHY in
USB-enabled OPNs
silabs.com | Building a more connected world.
Rev. 1.0 | 120
EFM32GG12 Family Data Sheet
Pin Definitions
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PF11
A13
GPIO (5V)
PA15
B1
GPIO
PE13
B2
GPIO
PE11
B3
GPIO
PE8
B4
GPIO
PD12
B5
GPIO
PD10
B6
GPIO
PF8
B7
GPIO
PF6
B8
GPIO
PF13
B9
GPIO (5V)
PF4
B10
GPIO
PF3
B11
GPIO
NC
B12
No Connect.
PF10
B13
GPIO (5V)
PA1
C1
GPIO
PA0
C2
GPIO
PE10
C3
GPIO
PD13
C4
GPIO (5V)
VSS
C5
C8
H3
J3
K11
L5
L8
Ground
IOVDD1
C6
Digital IO power supply 1.
Digital IO power supply 0.
PF9
C7
GPIO
IOVDD0
C9
G3
J11
K3
L4
L9
PF2
C10
GPIO
PF1
C11
GPIO (5V)
PC14
C12
GPIO (5V)
PC15
C13
GPIO (5V)
PA3
D1
GPIO
PA2
D2
GPIO
PB15
D3
GPIO (5V)
PF0
D11
GPIO (5V)
PC12
D12
GPIO (5V)
PC13
D13
GPIO (5V)
PA6
E1
GPIO
PA5
E2
GPIO
PA4
E3
GPIO
PC9
E11
GPIO (5V)
PC10
E12
GPIO (5V)
PC11
E13
GPIO (5V)
PB0
F1
GPIO
PB1
F2
GPIO
PB2
F3
GPIO
PE6
F11
GPIO
PE7
F12
GPIO
PC8
F13
GPIO (5V)
PB3
G1
GPIO
PB4
G2
GPIO
PE3
G11
GPIO
PE4
G12
GPIO
PE5
G13
GPIO
PB5
H1
GPIO
PB6
H2
GPIO
DVDD
H11
Digital power supply.
DECOUPLE
H13
Decouple output for on-chip voltage
regulator. An external decoupling capacitor is required at this pin. This pin
should not be used to power any external circuits.
PD15
J2
PE2
H12
PD14
J1
GPIO
GPIO (5V)
silabs.com | Building a more connected world.
GPIO (5V)
Rev. 1.0 | 121
EFM32GG12 Family Data Sheet
Pin Definitions
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PE1
J12
GPIO (5V)
VREGVDD
J13
Voltage regulator VDD input
PC0
K1
GPIO (5V)
PC1
K2
GPIO (5V)
PE0
K12
GPIO (5V)
VREGSW
K13
DCDC regulator switching node
PC2
L1
GPIO (5V)
PC3
L2
GPIO (5V)
PA7
L3
GPIO
PB9
L6
GPIO (5V)
PB10
L7
GPIO (5V)
PD1
L10
GPIO
PC6
L11
GPIO
PC7
L12
GPIO
VREGVSS
L13
Voltage regulator VSS
PB7
M1
GPIO
PC4
M2
GPIO
PA8
M3
GPIO
PA10
M4
GPIO
PA13
M5
GPIO (5V)
PA14
M6
GPIO
RESETn
M7
Reset input, active low. This pin is internally pulled up to AVDD. To apply an
external reset source to this pin, it is required to only drive this pin low during
reset, and let the internal pull-up ensure
that reset is released.
PB12
M8
GPIO
PD0
M9
GPIO (5V)
PD2
M10
GPIO (5V)
PD3
M11
GPIO
PD4
M12
GPIO
PD8
M13
GPIO
PB8
N1
GPIO
PC5
N2
GPIO
PA9
N3
GPIO
PA11
N4
GPIO
PA12
N5
GPIO (5V)
PB11
N6
GPIO
BODEN
N7
Brown-Out Detector Enable. This pin
may be left disconnected or tied to
AVDD.
PB13
N8
GPIO
PB14
N9
GPIO
AVDD
N10
Analog power supply.
PD5
N11
GPIO
PD6
N12
GPIO
PD7
N13
GPIO
Note:
1. GPIO with 5V tolerance are indicated by (5V).
2. The pins PD13, PD14, and PD15 will not be 5V tolerant on all future devices. In order to preserve upgrade options with full hardware compatibility, do not use these pins with 5V domains.
silabs.com | Building a more connected world.
Rev. 1.0 | 122
EFM32GG12 Family Data Sheet
Pin Definitions
5.3 EFM32GG12B4xx in BGA120 Device Pinout
Figure 5.3. EFM32GG12B4xx in BGA120 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 5.20 GPIO Functionality Table or 5.21 Alternate Functionality Overview.
Table 5.3. EFM32GG12B4xx in BGA120 Device Pinout
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PE15
A1
GPIO
PE14
A2
GPIO
PE12
A3
GPIO
PE9
A4
GPIO
PD11
A5
GPIO
PD9
A6
GPIO
PF7
A7
GPIO
PF5
A8
GPIO
PF4
A9
GPIO
PF2
A10
GPIO
VREGI
A11
Input to 5 V regulator.
VREGO
A12
Decoupling for 5 V regulator and regulator output. Power for USB PHY in
USB-enabled OPNs
silabs.com | Building a more connected world.
Rev. 1.0 | 123
EFM32GG12 Family Data Sheet
Pin Definitions
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PF11
A13
GPIO (5V)
PA15
B1
GPIO
PE13
B2
GPIO
PE11
B3
GPIO
PE8
B4
GPIO
PD12
B5
GPIO
PD10
B6
GPIO
PF8
B7
GPIO
PF6
B8
GPIO
PF3
B9
GPIO
PF1
B10
GPIO (5V)
PF12
B11
GPIO (5V)
VBUS
B12
USB VBUS signal and auxiliary input to
5 V regulator.
PF10
B13
GPIO (5V)
PA1
C1
GPIO
PA0
C2
GPIO
PE10
C3
GPIO
PD13
C4
GPIO (5V)
VSS
C5
C8
H3
J3
K11
K12
L5
L6
M8
M11
N8
IOVDD1
C6
Digital IO power supply 1.
IOVDD0
C9
G3
J11
K3
L4
L7
Digital IO power supply 0.
Ground
PF9
C7
GPIO
PF0
C10
GPIO (5V)
PE4
C11
GPIO
PC14
C12
GPIO (5V)
PC15
C13
GPIO (5V)
PA3
D1
GPIO
PA2
D2
GPIO
PB15
D3
GPIO (5V)
PE5
D11
GPIO
PC12
D12
GPIO (5V)
PC13
D13
GPIO (5V)
PA6
E1
GPIO
PA5
E2
GPIO
PA4
E3
GPIO
PE6
E11
GPIO
PC10
E12
GPIO (5V)
PC11
E13
GPIO (5V)
PB0
F1
GPIO
PB1
F2
GPIO
PB2
F3
GPIO
PE7
F11
GPIO
PC8
F12
GPIO (5V)
PC9
F13
GPIO (5V)
PB3
G1
GPIO
PB4
G2
GPIO
PE0
G11
GPIO (5V)
PE1
G12
GPIO (5V)
PE3
G13
GPIO
PB5
H1
GPIO
PB6
H2
GPIO
DVDD
H11
Digital power supply.
PE2
H12
GPIO
PC7
H13
GPIO
PD14
J1
GPIO (5V)
PD15
J2
silabs.com | Building a more connected world.
GPIO (5V)
Rev. 1.0 | 124
EFM32GG12 Family Data Sheet
Pin Definitions
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
DECOUPLE
J13
Decouple output for on-chip voltage
regulator. An external decoupling capacitor is required at this pin. This pin
should not be used to power any external circuits.
GPIO (5V)
PC1
K2
GPIO (5V)
GPIO
PC2
L1
GPIO (5V)
L2
GPIO (5V)
PA7
L3
GPIO
PB9
L8
GPIO (5V)
PB10
L9
GPIO (5V)
PD0
L10
GPIO (5V)
PD1
L11
GPIO
PD4
L12
GPIO
PD7
L13
GPIO
PB7
M1
GPIO
PC4
M2
GPIO
PA8
M3
GPIO
PA10
M4
GPIO
PA13
M5
GPIO (5V)
PA14
M6
GPIO
RESETn
M7
Reset input, active low. This pin is internally pulled up to AVDD. To apply an
external reset source to this pin, it is required to only drive this pin low during
reset, and let the internal pull-up ensure
that reset is released.
AVDD
M9
M10
N11
Analog power supply.
PD3
M12
GPIO
PD6
M13
GPIO
PB8
N1
GPIO
PC5
N2
GPIO
PA9
N3
GPIO
PA11
N4
GPIO
PA12
N5
GPIO (5V)
PB11
N6
GPIO
PB12
N7
GPIO
PB13
N9
GPIO
PB14
N10
GPIO
PD2
N12
GPIO (5V)
PD5
N13
GPIO
PC6
J12
GPIO
PC0
K1
PD8
K13
PC3
Note:
1. GPIO with 5V tolerance are indicated by (5V).
2. The pins PD13, PD14, and PD15 will not be 5V tolerant on all future devices. In order to preserve upgrade options with full hardware compatibility, do not use these pins with 5V domains.
silabs.com | Building a more connected world.
Rev. 1.0 | 125
EFM32GG12 Family Data Sheet
Pin Definitions
5.4 EFM32GG12B8xx in BGA112 Device Pinout
Figure 5.4. EFM32GG12B8xx in BGA112 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 5.20 GPIO Functionality Table or 5.21 Alternate Functionality Overview.
Table 5.4. EFM32GG12B8xx in BGA112 Device Pinout
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PE15
A1
GPIO
PE14
A2
GPIO
PE12
A3
GPIO
PE9
A4
GPIO
PD10
A5
GPIO
PD9
A6
GPIO
PF7
A7
GPIO
PF6
A8
GPIO
VREGI
A9
Input to 5 V regulator.
VREGO
A10
Decoupling for 5 V regulator and regulator output. Power for USB PHY in
USB-enabled OPNs
PF11
A11
GPIO (5V)
PA15
B1
GPIO
silabs.com | Building a more connected world.
Rev. 1.0 | 126
EFM32GG12 Family Data Sheet
Pin Definitions
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PE13
B2
GPIO
PE11
B3
GPIO
PE8
B4
GPIO
PD12
B5
GPIO
PD11
B6
GPIO
PF9
B7
GPIO
PF8
B8
GPIO
PC12
B9
GPIO (5V)
VBUS
B10
USB VBUS signal and auxiliary input to
5 V regulator.
PF10
B11
GPIO (5V)
PA1
C1
GPIO
PA0
C2
GPIO
PE10
C3
GPIO
PF5
C4
GPIO
PF4
C5
GPIO
PF2
C6
GPIO
VSS
C7
D4
G3
G9
H6
H9
K4
Ground
PF12
C8
GPIO (5V)
PE4
C9
GPIO
PC10
C10
GPIO (5V)
PC11
C11
GPIO (5V)
PA3
D1
GPIO
PA2
D2
GPIO
PB15
D3
GPIO (5V)
IOVDD1
D5
Digital IO power supply 1.
PF3
D6
GPIO
IOVDD0
D7
G4
G8
H7
L4
Digital IO power supply 0.
PF1
D8
GPIO (5V)
PE5
D9
GPIO
PC8
D10
GPIO (5V)
PC9
D11
GPIO (5V)
PA6
E1
GPIO
PA5
E2
GPIO
PA4
E3
GPIO
PB0
E4
GPIO
PF0
E8
GPIO (5V)
PE6
E9
GPIO
PE3
E10
GPIO
PE2
E11
GPIO
PB1
F1
GPIO
PB2
F2
GPIO
PB3
F3
GPIO
PB4
F4
GPIO
DVDD
F8
Digital power supply.
PE7
F9
GPIO
PE1
F10
GPIO (5V)
DECOUPLE
F11
Decouple output for on-chip voltage
regulator. An external decoupling capacitor is required at this pin. This pin
should not be used to power any external circuits.
PB5
G1
GPIO
PB6
G2
GPIO
PE0
G10
GPIO (5V)
VREGVDD
G11
Voltage regulator VDD input
PC0
H1
GPIO (5V)
PC2
H2
GPIO (5V)
PD14
H3
GPIO (5V)
PA7
H4
GPIO
PA8
H5
GPIO
silabs.com | Building a more connected world.
Rev. 1.0 | 127
EFM32GG12 Family Data Sheet
Pin Definitions
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PD2
H8
GPIO (5V)
PC6
H10
GPIO
VREGSW
H11
DCDC regulator switching node
PC1
J1
GPIO (5V)
PC3
J2
GPIO (5V)
PD15
J3
GPIO (5V)
PA12
J4
GPIO (5V)
PA9
J5
GPIO
PA10
J6
GPIO
PB9
J7
GPIO (5V)
PD0
J8
GPIO (5V)
PD5
J9
GPIO
PC7
J10
GPIO
VREGVSS
J11
Voltage regulator VSS
PB7
K1
GPIO
PC4
K2
GPIO
PA13
K3
GPIO (5V)
PA11
K5
GPIO
RESETn
K6
Reset input, active low. This pin is internally pulled up to AVDD. To apply an
external reset source to this pin, it is required to only drive this pin low during
reset, and let the internal pull-up ensure
that reset is released.
PB10
K7
GPIO (5V)
PD1
K8
GPIO
PD3
K9
GPIO
PD6
K10
GPIO
PD8
K11
GPIO
PB8
L1
GPIO
PC5
L2
GPIO
PA14
L3
GPIO
PB11
L5
GPIO
PB12
L6
GPIO
PB13
L7
GPIO
PB14
L8
GPIO
PD4
L9
GPIO
AVDD
L10
Analog power supply.
PD7
L11
GPIO
Note:
1. GPIO with 5V tolerance are indicated by (5V).
2. The pins PD14, and PD15 will not be 5V tolerant on all future devices. In order to preserve upgrade options with full hardware
compatibility, do not use these pins with 5V domains.
silabs.com | Building a more connected world.
Rev. 1.0 | 128
EFM32GG12 Family Data Sheet
Pin Definitions
5.5 EFM32GG12B5xx in BGA112 Device Pinout
Figure 5.5. EFM32GG12B5xx in BGA112 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 5.20 GPIO Functionality Table or 5.21 Alternate Functionality Overview.
Table 5.5. EFM32GG12B5xx in BGA112 Device Pinout
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PE15
A1
GPIO
PE14
A2
GPIO
PE12
A3
GPIO
PE9
A4
GPIO
PD10
A5
GPIO
PD9
A6
GPIO
PF7
A7
GPIO
PF6
A8
GPIO
PF10
A9
GPIO (5V)
PC14
A10
GPIO (5V)
PC15
A11
GPIO (5V)
PA15
B1
GPIO
PE13
B2
GPIO
PE11
B3
GPIO
silabs.com | Building a more connected world.
Rev. 1.0 | 129
EFM32GG12 Family Data Sheet
Pin Definitions
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PE8
B4
GPIO
PD12
B5
GPIO
PD11
B6
GPIO
PF9
B7
GPIO
PF8
B8
GPIO
PF11
B9
GPIO (5V)
PC12
B10
GPIO (5V)
PC13
B11
GPIO (5V)
PA1
C1
GPIO
PA0
C2
GPIO
PE10
C3
GPIO
PD13
C4
GPIO (5V)
PF5
C5
GPIO
PF4
C6
GPIO
VSS
C7
D4
G3
G9
H6
H9
K4
Ground
PF2
C8
GPIO
PE4
C9
GPIO
PC10
C10
GPIO (5V)
PC11
C11
GPIO (5V)
PA3
D1
GPIO
PA2
D2
GPIO
PB15
D3
GPIO (5V)
IOVDD1
D5
Digital IO power supply 1.
PF3
D6
GPIO
IOVDD0
D7
G4
G8
H7
L4
Digital IO power supply 0.
PF1
D8
GPIO (5V)
PE5
D9
GPIO
PC8
D10
GPIO (5V)
PC9
D11
GPIO (5V)
PA6
E1
GPIO
PA5
E2
GPIO
PA4
E3
GPIO
PB0
E4
GPIO
PF0
E8
GPIO (5V)
PE6
E9
GPIO
PE3
E10
GPIO
PE2
E11
GPIO
PB1
F1
GPIO
PB2
F2
GPIO
PB3
F3
GPIO
PB4
F4
GPIO
DVDD
F8
Digital power supply.
PE7
F9
GPIO
PE1
F10
GPIO (5V)
DECOUPLE
F11
Decouple output for on-chip voltage
regulator. An external decoupling capacitor is required at this pin. This pin
should not be used to power any external circuits.
PB5
G1
GPIO
PB6
G2
GPIO
PE0
G10
GPIO (5V)
VREGVDD
G11
Voltage regulator VDD input
PC0
H1
GPIO (5V)
PC2
H2
GPIO (5V)
PD14
H3
GPIO (5V)
PA7
H4
GPIO
PA8
H5
GPIO
PD2
H8
GPIO (5V)
PC7
H10
GPIO
VREGSW
H11
DCDC regulator switching node
PC1
J1
silabs.com | Building a more connected world.
GPIO (5V)
Rev. 1.0 | 130
EFM32GG12 Family Data Sheet
Pin Definitions
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PC3
J2
GPIO (5V)
PD15
J3
GPIO (5V)
PA12
J4
GPIO (5V)
PA9
J5
GPIO
PA10
J6
GPIO
PB9
J7
GPIO (5V)
PD0
J8
GPIO (5V)
PD5
J9
GPIO
PC6
J10
GPIO
VREGVSS
J11
Voltage regulator VSS
PB7
K1
GPIO
PC4
K2
GPIO
PA13
K3
GPIO (5V)
PA11
K5
GPIO
RESETn
K6
Reset input, active low. This pin is internally pulled up to AVDD. To apply an
external reset source to this pin, it is required to only drive this pin low during
reset, and let the internal pull-up ensure
that reset is released.
PB10
K7
GPIO (5V)
PD1
K8
GPIO
PD3
K9
GPIO
PD6
K10
GPIO
PD8
K11
GPIO
PB8
L1
GPIO
PC5
L2
GPIO
PA14
L3
GPIO
PB11
L5
GPIO
PB12
L6
GPIO
PB13
L7
GPIO
PB14
L8
GPIO
PD4
L9
GPIO
AVDD
L10
Analog power supply.
PD7
L11
GPIO
Note:
1. GPIO with 5V tolerance are indicated by (5V).
2. The pins PD13, PD14, and PD15 will not be 5V tolerant on all future devices. In order to preserve upgrade options with full hardware compatibility, do not use these pins with 5V domains.
silabs.com | Building a more connected world.
Rev. 1.0 | 131
EFM32GG12 Family Data Sheet
Pin Definitions
5.6 EFM32GG12B4xx in BGA112 Device Pinout
Figure 5.6. EFM32GG12B4xx in BGA112 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 5.20 GPIO Functionality Table or 5.21 Alternate Functionality Overview.
Table 5.6. EFM32GG12B4xx in BGA112 Device Pinout
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PE15
A1
GPIO
PE14
A2
GPIO
PE12
A3
GPIO
PE9
A4
GPIO
PD10
A5
GPIO
PF7
A6
GPIO
PF5
A7
GPIO
PF12
A8
GPIO (5V)
PE4
A9
GPIO
PF10
A10
GPIO (5V)
PF11
A11
GPIO (5V)
PA15
B1
GPIO
PE13
B2
GPIO
PE11
B3
GPIO
silabs.com | Building a more connected world.
Rev. 1.0 | 132
EFM32GG12 Family Data Sheet
Pin Definitions
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PE8
B4
GPIO
PD11
B5
GPIO
PF8
B6
GPIO
PF6
B7
GPIO
VBUS
B8
USB VBUS signal and auxiliary input to
5 V regulator.
PE5
B9
GPIO
VREGI
B10
Input to 5 V regulator.
VREGO
B11
Decoupling for 5 V regulator and regulator output. Power for USB PHY in
USB-enabled OPNs
PA1
C1
GPIO
PA0
C2
GPIO
PE10
C3
GPIO
PD13
C4
GPIO (5V)
PD12
C5
GPIO
PF9
C6
GPIO
VSS
C7
D4
F9
G3
G9
H6
K4
K7
K10
L7
Ground
PF2
C8
GPIO
PE6
C9
GPIO
PC10
C10
GPIO (5V)
PC11
C11
GPIO (5V)
PA3
D1
GPIO
PA2
D2
GPIO
PB15
D3
GPIO (5V)
IOVDD1
D5
Digital IO power supply 1.
PD9
D6
GPIO
IOVDD0
D7
G4
G8
H7
L4
Digital IO power supply 0.
PF1
D8
GPIO (5V)
PE7
D9
GPIO
PC8
D10
GPIO (5V)
PC9
D11
GPIO (5V)
PA6
E1
GPIO
PA5
E2
GPIO
PA4
E3
GPIO
PB0
E4
GPIO
PF0
E8
GPIO (5V)
PE0
E9
GPIO (5V)
PE1
E10
GPIO (5V)
PE3
E11
GPIO
PB1
F1
GPIO
PB2
F2
GPIO
PB3
F3
GPIO
PB4
F4
GPIO
DVDD
F8
Digital power supply.
PE2
F10
GPIO
DECOUPLE
F11
Decouple output for on-chip voltage
regulator. An external decoupling capacitor is required at this pin. This pin
should not be used to power any external circuits.
PB5
G1
GPIO
PB6
G2
GPIO
PC6
G10
GPIO
PC7
G11
GPIO
PC0
H1
GPIO (5V)
PC2
H2
silabs.com | Building a more connected world.
GPIO (5V)
Rev. 1.0 | 133
EFM32GG12 Family Data Sheet
Pin Definitions
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PD14
H3
GPIO (5V)
PA7
H4
GPIO
PA8
H5
GPIO
PD8
H8
GPIO
PD5
H9
GPIO
PD6
H10
GPIO
PD7
H11
GPIO
PC1
J1
GPIO (5V)
PC3
J2
GPIO (5V)
PD15
J3
GPIO (5V)
PA12
J4
GPIO (5V)
PA9
J5
GPIO
PA10
J6
GPIO
PB9
J7
GPIO (5V)
PB10
J8
GPIO (5V)
PD2
J9
GPIO (5V)
PD3
J10
GPIO
PD4
J11
GPIO
PB7
K1
GPIO
PC4
K2
GPIO
PA13
K3
GPIO (5V)
PA11
K5
GPIO
RESETn
K6
Reset input, active low. This pin is internally pulled up to AVDD. To apply an
external reset source to this pin, it is required to only drive this pin low during
reset, and let the internal pull-up ensure
that reset is released.
AVDD
K8
K9
L10
Analog power supply.
PD1
K11
GPIO
PB8
L1
GPIO
PC5
L2
GPIO
PA14
L3
GPIO
PB11
L5
GPIO
PB12
L6
GPIO
PB13
L8
GPIO
PB14
L9
GPIO
PD0
L11
GPIO (5V)
Note:
1. GPIO with 5V tolerance are indicated by (5V).
2. The pins PD13, PD14, and PD15 will not be 5V tolerant on all future devices. In order to preserve upgrade options with full hardware compatibility, do not use these pins with 5V domains.
silabs.com | Building a more connected world.
Rev. 1.0 | 134
EFM32GG12 Family Data Sheet
Pin Definitions
5.7 EFM32GG12B3xx in BGA112 Device Pinout
Figure 5.7. EFM32GG12B3xx in BGA112 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 5.20 GPIO Functionality Table or 5.21 Alternate Functionality Overview.
Table 5.7. EFM32GG12B3xx in BGA112 Device Pinout
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PE15
A1
GPIO
PE14
A2
GPIO
PE12
A3
GPIO
PE9
A4
GPIO
PD10
A5
GPIO
PF7
A6
GPIO
PF5
A7
GPIO
PF4
A8
GPIO
PE4
A9
GPIO
PC14
A10
GPIO (5V)
PC15
A11
GPIO (5V)
PA15
B1
GPIO
PE13
B2
GPIO
PE11
B3
GPIO
silabs.com | Building a more connected world.
Rev. 1.0 | 135
EFM32GG12 Family Data Sheet
Pin Definitions
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PE8
B4
GPIO
PD11
B5
GPIO
PF8
B6
GPIO
PF6
B7
GPIO
PF3
B8
GPIO
PE5
B9
GPIO
PC12
B10
GPIO (5V)
PC13
B11
GPIO (5V)
PA1
C1
GPIO
PA0
C2
GPIO
PE10
C3
GPIO
PD13
C4
GPIO (5V)
PD12
C5
GPIO
PF9
C6
GPIO
VSS
C7
D4
F9
G3
G9
H6
K4
K7
K10
L7
Ground
PF2
C8
GPIO
PE6
C9
GPIO
PC10
C10
GPIO (5V)
PC11
C11
GPIO (5V)
PA3
D1
GPIO
PA2
D2
GPIO
PB15
D3
GPIO (5V)
IOVDD1
D5
Digital IO power supply 1.
PD9
D6
GPIO
IOVDD0
D7
G4
G8
H7
L4
Digital IO power supply 0.
PF1
D8
GPIO (5V)
PE7
D9
GPIO
PC8
D10
GPIO (5V)
PC9
D11
GPIO (5V)
PA6
E1
GPIO
PA5
E2
GPIO
PA4
E3
GPIO
PB0
E4
GPIO
PF0
E8
GPIO (5V)
PE0
E9
GPIO (5V)
PE1
E10
GPIO (5V)
PE3
E11
GPIO
PB1
F1
GPIO
PB2
F2
GPIO
PB3
F3
GPIO
PB4
F4
GPIO
DVDD
F8
Digital power supply.
PE2
F10
GPIO
DECOUPLE
F11
Decouple output for on-chip voltage
regulator. An external decoupling capacitor is required at this pin. This pin
should not be used to power any external circuits.
PB5
G1
GPIO
PB6
G2
GPIO
PC6
G10
GPIO
PC7
G11
GPIO
PC0
H1
GPIO (5V)
PC2
H2
GPIO (5V)
PD14
H3
GPIO (5V)
PA7
H4
GPIO
PA8
H5
GPIO
PD8
H8
GPIO
silabs.com | Building a more connected world.
Rev. 1.0 | 136
EFM32GG12 Family Data Sheet
Pin Definitions
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PD5
H9
GPIO
PD6
H10
GPIO
PD7
H11
GPIO
PC1
J1
GPIO (5V)
PC3
J2
GPIO (5V)
PD15
J3
GPIO (5V)
PA12
J4
GPIO (5V)
PA9
J5
GPIO
PA10
J6
GPIO
PB9
J7
GPIO (5V)
PB10
J8
GPIO (5V)
PD2
J9
GPIO (5V)
PD3
J10
GPIO
PD4
J11
GPIO
PB7
K1
GPIO
PC4
K2
GPIO
PA13
K3
GPIO (5V)
PA11
K5
GPIO
RESETn
K6
Reset input, active low. This pin is internally pulled up to AVDD. To apply an
external reset source to this pin, it is required to only drive this pin low during
reset, and let the internal pull-up ensure
that reset is released.
AVDD
K8
K9
L10
Analog power supply.
PD1
K11
GPIO
PB8
L1
GPIO
PC5
L2
GPIO
PA14
L3
GPIO
PB11
L5
GPIO
PB12
L6
GPIO
PB13
L8
GPIO
PB14
L9
GPIO
PD0
L11
GPIO (5V)
Note:
1. GPIO with 5V tolerance are indicated by (5V).
2. The pins PD13, PD14, and PD15 will not be 5V tolerant on all future devices. In order to preserve upgrade options with full hardware compatibility, do not use these pins with 5V domains.
silabs.com | Building a more connected world.
Rev. 1.0 | 137
EFM32GG12 Family Data Sheet
Pin Definitions
5.8 EFM32GG12B8xx in QFP100 Device Pinout
Figure 5.8. EFM32GG12B8xx in QFP100 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 5.20 GPIO Functionality Table or 5.21 Alternate Functionality Overview.
Table 5.8. EFM32GG12B8xx in QFP100 Device Pinout
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PA0
1
GPIO
PA1
2
GPIO
PA2
3
GPIO
PA3
4
GPIO
PA4
5
GPIO
PA5
6
GPIO
Digital IO power supply 0.
GPIO
PA6
7
GPIO
IOVDD0
8
17
31
44
82
PB0
9
GPIO
PB1
10
silabs.com | Building a more connected world.
Rev. 1.0 | 138
EFM32GG12 Family Data Sheet
Pin Definitions
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PB2
11
GPIO
PB3
12
GPIO
PB4
13
GPIO
PB5
14
GPIO
Ground
PB6
15
GPIO
VSS
16
32
59
83
PC0
18
GPIO (5V)
PC1
19
GPIO (5V)
PC2
20
GPIO (5V)
PC3
21
GPIO (5V)
PC4
22
GPIO
PC5
23
GPIO
PB7
24
GPIO
PB8
25
GPIO
PA7
26
GPIO
PA8
27
GPIO
PA9
28
GPIO
PA10
29
GPIO
PA11
30
GPIO
PA12
33
GPIO (5V)
PA13
34
GPIO (5V)
PA14
35
GPIO
RESETn
36
Reset input, active low. This pin is internally pulled up to AVDD. To apply an
external reset source to this pin, it is required to only drive this pin low during
reset, and let the internal pull-up ensure
that reset is released.
PB9
37
GPIO (5V)
PB10
38
GPIO (5V)
PB11
39
GPIO
PB12
40
GPIO
AVDD
41
Analog power supply.
PB13
42
GPIO
PB14
43
GPIO
PD0
45
GPIO (5V)
PD1
46
GPIO
PD2
47
GPIO (5V)
PD3
48
GPIO
PD4
49
GPIO
PD5
50
GPIO
PD6
51
GPIO
PD7
52
GPIO
PD8
53
GPIO
PC7
54
GPIO
VREGVSS
55
Voltage regulator VSS
VREGSW
56
DCDC regulator switching node
VREGVDD
57
Voltage regulator VDD input
DVDD
58
Digital power supply.
DECOUPLE
60
Decouple output for on-chip voltage
regulator. An external decoupling capacitor is required at this pin. This pin
should not be used to power any external circuits.
PE1
61
GPIO (5V)
PE2
62
GPIO
PE3
63
GPIO
PE4
64
GPIO
PE5
65
GPIO
PE6
66
GPIO
PE7
67
GPIO
PC8
68
GPIO (5V)
PC9
69
GPIO (5V)
PC10
70
GPIO (5V)
PC11
71
GPIO (5V)
VREGI
72
Input to 5 V regulator.
VREGO
73
Decoupling for 5 V regulator and regulator output. Power for USB PHY in
USB-enabled OPNs
silabs.com | Building a more connected world.
Rev. 1.0 | 139
EFM32GG12 Family Data Sheet
Pin Definitions
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PF10
74
GPIO (5V)
PF11
75
GPIO (5V)
PF0
76
GPIO (5V)
PF1
77
GPIO (5V)
PF2
78
GPIO
VBUS
79
USB VBUS signal and auxiliary input to
5 V regulator.
PF12
80
GPIO (5V)
PF5
81
GPIO
PF6
84
GPIO
PF7
85
GPIO
PF8
86
GPIO
PF9
87
GPIO
PD9
88
GPIO
PD10
89
GPIO
PD11
90
GPIO
PD12
91
GPIO
PE8
92
GPIO
PE9
93
GPIO
PE10
94
GPIO
PE11
95
GPIO
PE12
96
GPIO
PE13
97
GPIO
PE14
98
GPIO
PE15
99
GPIO
PA15
100
GPIO
Note:
1. GPIO with 5V tolerance are indicated by (5V).
silabs.com | Building a more connected world.
Rev. 1.0 | 140
EFM32GG12 Family Data Sheet
Pin Definitions
5.9 EFM32GG12B5xx in QFP100 Device Pinout
Figure 5.9. EFM32GG12B5xx in QFP100 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 5.20 GPIO Functionality Table or 5.21 Alternate Functionality Overview.
Table 5.9. EFM32GG12B5xx in QFP100 Device Pinout
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PA0
1
GPIO
PA1
2
GPIO
PA2
3
GPIO
PA3
4
GPIO
PA4
5
GPIO
PA5
6
GPIO
Digital IO power supply 0.
GPIO
PA6
7
GPIO
IOVDD0
8
17
31
44
82
PB0
9
GPIO
PB1
10
silabs.com | Building a more connected world.
Rev. 1.0 | 141
EFM32GG12 Family Data Sheet
Pin Definitions
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PB2
11
GPIO
PB3
12
GPIO
PB4
13
GPIO
PB5
14
GPIO
Ground
PB6
15
GPIO
VSS
16
32
59
83
PC0
18
GPIO (5V)
PC1
19
GPIO (5V)
PC2
20
GPIO (5V)
PC3
21
GPIO (5V)
PC4
22
GPIO
PC5
23
GPIO
PB7
24
GPIO
PB8
25
GPIO
PA7
26
GPIO
PA8
27
GPIO
PA9
28
GPIO
PA10
29
GPIO
PA11
30
GPIO
PA12
33
GPIO (5V)
PA13
34
GPIO (5V)
PA14
35
GPIO
RESETn
36
Reset input, active low. This pin is internally pulled up to AVDD. To apply an
external reset source to this pin, it is required to only drive this pin low during
reset, and let the internal pull-up ensure
that reset is released.
PB9
37
GPIO (5V)
PB10
38
GPIO (5V)
PB11
39
GPIO
PB12
40
GPIO
AVDD
41
Analog power supply.
PB13
42
GPIO
PB14
43
GPIO
PD0
45
GPIO (5V)
PD1
46
GPIO
PD2
47
GPIO (5V)
PD3
48
GPIO
PD4
49
GPIO
PD5
50
GPIO
PD6
51
GPIO
PD7
52
GPIO
PD8
53
GPIO
PC7
54
GPIO
VREGVSS
55
Voltage regulator VSS
VREGSW
56
DCDC regulator switching node
VREGVDD
57
Voltage regulator VDD input
DVDD
58
Digital power supply.
DECOUPLE
60
Decouple output for on-chip voltage
regulator. An external decoupling capacitor is required at this pin. This pin
should not be used to power any external circuits.
PE1
61
GPIO (5V)
PE2
62
GPIO
PE3
63
GPIO
PE4
64
GPIO
PE5
65
GPIO
PE6
66
GPIO
PE7
67
GPIO
PC8
68
GPIO (5V)
PC9
69
GPIO (5V)
PC10
70
GPIO (5V)
PC11
71
GPIO (5V)
VREGI
72
Input to 5 V regulator.
VREGO
73
Decoupling for 5 V regulator and regulator output. Power for USB PHY in
USB-enabled OPNs
silabs.com | Building a more connected world.
Rev. 1.0 | 142
EFM32GG12 Family Data Sheet
Pin Definitions
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PF10
74
GPIO (5V)
PF11
75
GPIO (5V)
PF0
76
GPIO (5V)
PF1
77
GPIO (5V)
PF2
78
GPIO
NC
79
No Connect.
PF12
80
GPIO (5V)
PF5
81
GPIO
PF6
84
GPIO
PF7
85
GPIO
PF8
86
GPIO
PF9
87
GPIO
PD9
88
GPIO
PD10
89
GPIO
PD11
90
GPIO
PD12
91
GPIO
PE8
92
GPIO
PE9
93
GPIO
PE10
94
GPIO
PE11
95
GPIO
PE12
96
GPIO
PE13
97
GPIO
PE14
98
GPIO
PE15
99
GPIO
PA15
100
GPIO
Note:
1. GPIO with 5V tolerance are indicated by (5V).
silabs.com | Building a more connected world.
Rev. 1.0 | 143
EFM32GG12 Family Data Sheet
Pin Definitions
5.10 EFM32GG12B4xx in QFP100 Device Pinout
Figure 5.10. EFM32GG12B4xx in QFP100 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 5.20 GPIO Functionality Table or 5.21 Alternate Functionality Overview.
Table 5.10. EFM32GG12B4xx in QFP100 Device Pinout
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PA0
1
GPIO
PA1
2
GPIO
PA2
3
GPIO
PA3
4
GPIO
PA4
5
GPIO
PA5
6
GPIO
Digital IO power supply 0.
GPIO
PA6
7
GPIO
IOVDD0
8
17
31
44
82
PB0
9
GPIO
PB1
10
silabs.com | Building a more connected world.
Rev. 1.0 | 144
EFM32GG12 Family Data Sheet
Pin Definitions
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PB2
11
GPIO
PB3
12
GPIO
PB4
13
GPIO
PB5
14
GPIO
Ground
PB6
15
GPIO
VSS
16
32
58
83
PC0
18
GPIO (5V)
PC1
19
GPIO (5V)
PC2
20
GPIO (5V)
PC3
21
GPIO (5V)
PC4
22
GPIO
PC5
23
GPIO
PB7
24
GPIO
PB8
25
GPIO
PA7
26
GPIO
PA8
27
GPIO
PA9
28
GPIO
PA10
29
GPIO
PA11
30
GPIO
PA12
33
GPIO (5V)
PA13
34
GPIO (5V)
PA14
35
GPIO
RESETn
36
Reset input, active low. This pin is internally pulled up to AVDD. To apply an
external reset source to this pin, it is required to only drive this pin low during
reset, and let the internal pull-up ensure
that reset is released.
PB9
37
GPIO (5V)
PB10
38
GPIO (5V)
PB11
39
GPIO
PB12
40
GPIO
AVDD
41
45
Analog power supply.
PB13
42
GPIO
PB14
43
GPIO
PD0
46
GPIO (5V)
PD1
47
GPIO
PD2
48
GPIO (5V)
PD3
49
GPIO
PD4
50
GPIO
PD5
51
GPIO
PD6
52
GPIO
PD7
53
GPIO
PD8
54
GPIO
PC6
55
GPIO
PC7
56
GPIO
DVDD
57
Digital power supply.
DECOUPLE
59
Decouple output for on-chip voltage
regulator. An external decoupling capacitor is required at this pin. This pin
should not be used to power any external circuits.
PE0
60
GPIO (5V)
PE1
61
GPIO (5V)
PE2
62
GPIO
PE3
63
GPIO
PE4
64
GPIO
PE5
65
GPIO
PE6
66
GPIO
PE7
67
GPIO
PC8
68
GPIO (5V)
PC9
69
GPIO (5V)
PC10
70
GPIO (5V)
PC11
71
GPIO (5V)
VREGI
72
Input to 5 V regulator.
silabs.com | Building a more connected world.
Rev. 1.0 | 145
EFM32GG12 Family Data Sheet
Pin Definitions
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
VREGO
73
Decoupling for 5 V regulator and regulator output. Power for USB PHY in
USB-enabled OPNs
PF10
74
GPIO (5V)
PF11
75
GPIO (5V)
PF0
76
GPIO (5V)
PF1
77
GPIO (5V)
PF2
78
GPIO
VBUS
79
USB VBUS signal and auxiliary input to
5 V regulator.
PF12
80
GPIO (5V)
PF5
81
GPIO
PF6
84
GPIO
PF7
85
GPIO
PF8
86
GPIO
PF9
87
GPIO
PD9
88
GPIO
PD10
89
GPIO
PD11
90
GPIO
PD12
91
GPIO
PE8
92
GPIO
PE9
93
GPIO
PE10
94
GPIO
PE11
95
GPIO
PE12
96
GPIO
PE13
97
GPIO
PE14
98
GPIO
PE15
99
GPIO
PA15
100
GPIO
Note:
1. GPIO with 5V tolerance are indicated by (5V).
silabs.com | Building a more connected world.
Rev. 1.0 | 146
EFM32GG12 Family Data Sheet
Pin Definitions
5.11 EFM32GG12B3xx in QFP100 Device Pinout
Figure 5.11. EFM32GG12B3xx in QFP100 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 5.20 GPIO Functionality Table or 5.21 Alternate Functionality Overview.
Table 5.11. EFM32GG12B3xx in QFP100 Device Pinout
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PA0
1
GPIO
PA1
2
GPIO
PA2
3
GPIO
PA3
4
GPIO
PA4
5
GPIO
PA5
6
GPIO
Digital IO power supply 0.
GPIO
PA6
7
GPIO
IOVDD0
8
17
31
44
82
PB0
9
GPIO
PB1
10
silabs.com | Building a more connected world.
Rev. 1.0 | 147
EFM32GG12 Family Data Sheet
Pin Definitions
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PB2
11
GPIO
PB3
12
GPIO
PB4
13
GPIO
PB5
14
GPIO
Ground
PB6
15
GPIO
VSS
16
32
58
83
PC0
18
GPIO (5V)
PC1
19
GPIO (5V)
PC2
20
GPIO (5V)
PC3
21
GPIO (5V)
PC4
22
GPIO
PC5
23
GPIO
PB7
24
GPIO
PB8
25
GPIO
PA7
26
GPIO
PA8
27
GPIO
PA9
28
GPIO
PA10
29
GPIO
PA11
30
GPIO
PA12
33
GPIO (5V)
PA13
34
GPIO (5V)
PA14
35
GPIO
RESETn
36
Reset input, active low. This pin is internally pulled up to AVDD. To apply an
external reset source to this pin, it is required to only drive this pin low during
reset, and let the internal pull-up ensure
that reset is released.
PB9
37
GPIO (5V)
PB10
38
GPIO (5V)
PB11
39
GPIO
PB12
40
GPIO
AVDD
41
45
Analog power supply.
PB13
42
GPIO
PB14
43
GPIO
PD0
46
GPIO (5V)
PD1
47
GPIO
PD2
48
GPIO (5V)
PD3
49
GPIO
PD4
50
GPIO
PD5
51
GPIO
PD6
52
GPIO
PD7
53
GPIO
PD8
54
GPIO
PC6
55
GPIO
PC7
56
GPIO
DVDD
57
Digital power supply.
DECOUPLE
59
Decouple output for on-chip voltage
regulator. An external decoupling capacitor is required at this pin. This pin
should not be used to power any external circuits.
PE0
60
GPIO (5V)
PE1
61
GPIO (5V)
PE2
62
GPIO
PE3
63
GPIO
PE4
64
GPIO
PE5
65
GPIO
PE6
66
GPIO
PE7
67
GPIO
PC8
68
GPIO (5V)
PC9
69
GPIO (5V)
PC10
70
GPIO (5V)
PC11
71
GPIO (5V)
PC12
72
GPIO (5V)
PC13
73
GPIO (5V)
PC14
74
GPIO (5V)
silabs.com | Building a more connected world.
Rev. 1.0 | 148
EFM32GG12 Family Data Sheet
Pin Definitions
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PC15
75
GPIO (5V)
PF0
76
GPIO (5V)
PF1
77
GPIO (5V)
PF2
78
GPIO
PF3
79
GPIO
PF4
80
GPIO
PF5
81
GPIO
PF6
84
GPIO
PF7
85
GPIO
PF8
86
GPIO
PF9
87
GPIO
PD9
88
GPIO
PD10
89
GPIO
PD11
90
GPIO
PD12
91
GPIO
PE8
92
GPIO
PE9
93
GPIO
PE10
94
GPIO
PE11
95
GPIO
PE12
96
GPIO
PE13
97
GPIO
PE14
98
GPIO
PE15
99
GPIO
PA15
100
GPIO
Note:
1. GPIO with 5V tolerance are indicated by (5V).
silabs.com | Building a more connected world.
Rev. 1.0 | 149
EFM32GG12 Family Data Sheet
Pin Definitions
5.12 EFM32GG12B8xx in QFP64 Device Pinout
Figure 5.12. EFM32GG12B8xx in QFP64 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 5.20 GPIO Functionality Table or 5.21 Alternate Functionality Overview.
Table 5.12. EFM32GG12B8xx in QFP64 Device Pinout
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PA0
1
GPIO
PA1
2
GPIO
PA2
3
GPIO
PA3
4
GPIO
PA4
5
GPIO
PA5
6
GPIO
IOVDD0
7
27
55
Digital IO power supply 0.
VSS
8
23
56
Ground
PB3
9
GPIO
PB4
10
GPIO
PB5
11
GPIO
PB6
12
GPIO
silabs.com | Building a more connected world.
Rev. 1.0 | 150
EFM32GG12 Family Data Sheet
Pin Definitions
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PC4
13
GPIO
PC5
14
GPIO
PB7
15
GPIO
PB8
16
GPIO
PA8
17
GPIO
PA12
18
GPIO (5V)
PA14
19
GPIO
RESETn
20
Reset input, active low. This pin is internally pulled up to AVDD. To apply an
external reset source to this pin, it is required to only drive this pin low during
reset, and let the internal pull-up ensure
that reset is released.
PB11
21
GPIO
PB12
22
GPIO
AVDD
24
Analog power supply.
PB13
25
GPIO
PB14
26
GPIO
PD0
28
GPIO (5V)
PD1
29
GPIO
PD2
30
GPIO (5V)
PD3
31
GPIO
PD4
32
GPIO
PD5
33
GPIO
PD6
34
GPIO
PD8
35
GPIO
VREGVSS
36
Voltage regulator VSS
VREGSW
37
DCDC regulator switching node
VREGVDD
38
Voltage regulator VDD input
DECOUPLE
40
Decouple output for on-chip voltage
regulator. An external decoupling capacitor is required at this pin. This pin
should not be used to power any external circuits.
DVDD
39
Digital power supply.
PE4
41
GPIO
PE5
42
GPIO
PE6
43
GPIO
PE7
44
GPIO
VREGI
45
Input to 5 V regulator.
VREGO
46
Decoupling for 5 V regulator and regulator output. Power for USB PHY in
USB-enabled OPNs
PF10
47
GPIO (5V)
PF11
48
GPIO (5V)
PF0
49
GPIO (5V)
PF1
50
GPIO (5V)
PF2
51
GPIO
VBUS
52
USB VBUS signal and auxiliary input to
5 V regulator.
PF12
53
GPIO (5V)
PF5
54
GPIO
PE8
57
GPIO
PE9
58
GPIO
PE10
59
GPIO
PE11
60
GPIO
PE12
61
GPIO
PE13
62
GPIO
PE14
63
GPIO
PE15
64
GPIO
Note:
1. GPIO with 5V tolerance are indicated by (5V).
silabs.com | Building a more connected world.
Rev. 1.0 | 151
EFM32GG12 Family Data Sheet
Pin Definitions
5.13 EFM32GG12B5xx in QFP64 Device Pinout
Figure 5.13. EFM32GG12B5xx in QFP64 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 5.20 GPIO Functionality Table or 5.21 Alternate Functionality Overview.
Table 5.13. EFM32GG12B5xx in QFP64 Device Pinout
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PA0
1
GPIO
PA1
2
GPIO
PA2
3
GPIO
PA3
4
GPIO
PA4
5
GPIO
PA5
6
GPIO
IOVDD0
7
27
55
Digital IO power supply 0.
VSS
8
23
56
Ground
PB3
9
GPIO
PB4
10
GPIO
PB5
11
GPIO
PB6
12
GPIO
silabs.com | Building a more connected world.
Rev. 1.0 | 152
EFM32GG12 Family Data Sheet
Pin Definitions
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PC4
13
GPIO
PC5
14
GPIO
PB7
15
GPIO
PB8
16
GPIO
PA8
17
GPIO
PA12
18
GPIO (5V)
PA14
19
GPIO
RESETn
20
Reset input, active low. This pin is internally pulled up to AVDD. To apply an
external reset source to this pin, it is required to only drive this pin low during
reset, and let the internal pull-up ensure
that reset is released.
PB11
21
GPIO
PB12
22
GPIO
AVDD
24
Analog power supply.
PB13
25
GPIO
PB14
26
GPIO
PD0
28
GPIO (5V)
PD1
29
GPIO
PD2
30
GPIO (5V)
PD3
31
GPIO
PD4
32
GPIO
PD5
33
GPIO
PD6
34
GPIO
PD7
35
GPIO
PD8
36
GPIO
PC7
37
GPIO
VREGVSS
38
Voltage regulator VSS
VREGSW
39
DCDC regulator switching node
VREGVDD
40
Voltage regulator VDD input
DECOUPLE
42
Decouple output for on-chip voltage
regulator. An external decoupling capacitor is required at this pin. This pin
should not be used to power any external circuits.
DVDD
41
Digital power supply.
PE4
43
GPIO
PE5
44
GPIO
PE6
45
GPIO
PE7
46
GPIO
PC12
47
GPIO (5V)
PC13
48
GPIO (5V)
PF0
49
GPIO (5V)
PF1
50
GPIO (5V)
PF2
51
GPIO
PF3
52
GPIO
PF4
53
GPIO
PF5
54
GPIO
PE8
57
GPIO
PE9
58
GPIO
PE10
59
GPIO
PE11
60
GPIO
PE12
61
GPIO
PE13
62
GPIO
PE14
63
GPIO
PE15
64
GPIO
Note:
1. GPIO with 5V tolerance are indicated by (5V).
silabs.com | Building a more connected world.
Rev. 1.0 | 153
EFM32GG12 Family Data Sheet
Pin Definitions
5.14 EFM32GG12B4xx in QFP64 Device Pinout
Figure 5.14. EFM32GG12B4xx in QFP64 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 5.20 GPIO Functionality Table or 5.21 Alternate Functionality Overview.
Table 5.14. EFM32GG12B4xx in QFP64 Device Pinout
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PA0
1
GPIO
PA1
2
GPIO
PA2
3
GPIO
PA3
4
GPIO
PA4
5
GPIO
PA5
6
GPIO
IOVDD0
7
26
55
Digital IO power supply 0.
VSS
8
22
56
Ground
PB3
9
GPIO
PB4
10
GPIO
PB5
11
GPIO
PB6
12
GPIO
silabs.com | Building a more connected world.
Rev. 1.0 | 154
EFM32GG12 Family Data Sheet
Pin Definitions
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PC4
13
GPIO
PC5
14
GPIO
PB7
15
GPIO
PB8
16
GPIO
PA12
17
GPIO (5V)
PA13
18
GPIO (5V)
PA14
19
GPIO
RESETn
20
Reset input, active low. This pin is internally pulled up to AVDD. To apply an
external reset source to this pin, it is required to only drive this pin low during
reset, and let the internal pull-up ensure
that reset is released.
PB11
21
GPIO
AVDD
23
27
Analog power supply.
PB13
24
GPIO
PB14
25
GPIO
PD0
28
GPIO (5V)
PD1
29
GPIO
PD2
30
GPIO (5V)
PD3
31
GPIO
PD4
32
GPIO
PD5
33
GPIO
PD6
34
GPIO
PD7
35
GPIO
PD8
36
GPIO
PC6
37
GPIO
PC7
38
GPIO
DVDD
39
Digital power supply.
DECOUPLE
40
Decouple output for on-chip voltage
regulator. An external decoupling capacitor is required at this pin. This pin
should not be used to power any external circuits.
PE4
41
GPIO
PE5
42
GPIO
PE6
43
GPIO
PE7
44
GPIO
VREGI
45
Input to 5 V regulator.
VREGO
46
Decoupling for 5 V regulator and regulator output. Power for USB PHY in
USB-enabled OPNs
PF10
47
GPIO (5V)
PF11
48
GPIO (5V)
PF0
49
GPIO (5V)
PF1
50
GPIO (5V)
PF2
51
GPIO
VBUS
52
USB VBUS signal and auxiliary input to
5 V regulator.
PF12
53
GPIO (5V)
PF5
54
GPIO
PE8
57
GPIO
PE9
58
GPIO
PE10
59
GPIO
PE11
60
GPIO
PE12
61
GPIO
PE13
62
GPIO
PE14
63
GPIO
PE15
64
GPIO
Note:
1. GPIO with 5V tolerance are indicated by (5V).
silabs.com | Building a more connected world.
Rev. 1.0 | 155
EFM32GG12 Family Data Sheet
Pin Definitions
5.15 EFM32GG12B1xx in QFP64 Device Pinout
Figure 5.15. EFM32GG12B1xx in QFP64 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 5.20 GPIO Functionality Table or 5.21 Alternate Functionality Overview.
Table 5.15. EFM32GG12B1xx in QFP64 Device Pinout
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PA0
1
GPIO
PA1
2
GPIO
PA2
3
GPIO
PA3
4
GPIO
PA4
5
GPIO
PA5
6
GPIO
IOVDD0
7
26
55
Digital IO power supply 0.
VSS
8
22
56
Ground
PC0
9
GPIO (5V)
PC1
10
GPIO (5V)
PC2
11
GPIO (5V)
PC3
12
GPIO (5V)
silabs.com | Building a more connected world.
Rev. 1.0 | 156
EFM32GG12 Family Data Sheet
Pin Definitions
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PC4
13
GPIO
PC5
14
GPIO
PB7
15
GPIO
PB8
16
GPIO
PA8
17
GPIO
PA9
18
GPIO
PA10
19
GPIO
RESETn
20
Reset input, active low. This pin is internally pulled up to AVDD. To apply an
external reset source to this pin, it is required to only drive this pin low during
reset, and let the internal pull-up ensure
that reset is released.
PB11
21
GPIO
AVDD
23
27
Analog power supply.
PB13
24
GPIO
PB14
25
GPIO
PD0
28
GPIO (5V)
PD1
29
GPIO
PD2
30
GPIO (5V)
PD3
31
GPIO
PD4
32
GPIO
PD5
33
GPIO
PD6
34
GPIO
PD7
35
GPIO
PD8
36
GPIO
PC6
37
GPIO
PC7
38
GPIO
DVDD
39
Digital power supply.
DECOUPLE
40
Decouple output for on-chip voltage
regulator. An external decoupling capacitor is required at this pin. This pin
should not be used to power any external circuits.
PC8
41
GPIO (5V)
PC9
42
GPIO (5V)
PC10
43
GPIO (5V)
PC11
44
GPIO (5V)
PC12
45
GPIO (5V)
PC13
46
GPIO (5V)
PC14
47
GPIO (5V)
PC15
48
GPIO (5V)
PF0
49
GPIO (5V)
PF1
50
GPIO (5V)
PF2
51
GPIO
PF3
52
GPIO
PF4
53
GPIO
PF5
54
GPIO
PE8
57
GPIO
PE9
58
GPIO
PE10
59
GPIO
PE11
60
GPIO
PE12
61
GPIO
PE13
62
GPIO
PE14
63
GPIO
PE15
64
GPIO
Note:
1. GPIO with 5V tolerance are indicated by (5V).
silabs.com | Building a more connected world.
Rev. 1.0 | 157
EFM32GG12 Family Data Sheet
Pin Definitions
5.16 EFM32GG12B8xx in QFN64 Device Pinout
Figure 5.16. EFM32GG12B8xx in QFN64 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 5.20 GPIO Functionality Table or 5.21 Alternate Functionality Overview.
Table 5.16. EFM32GG12B8xx in QFN64 Device Pinout
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
VSS
0
Ground
PA0
1
GPIO
PA1
2
GPIO
PA2
3
GPIO
PA3
4
GPIO
PA4
5
GPIO
PA5
6
GPIO
PA6
7
GPIO
IOVDD0
8
27
55
Digital IO power supply 0.
PB3
9
GPIO
PB4
10
GPIO
PB5
11
GPIO
silabs.com | Building a more connected world.
Rev. 1.0 | 158
EFM32GG12 Family Data Sheet
Pin Definitions
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PB6
12
GPIO
PC4
13
GPIO
PC5
14
GPIO
PB7
15
GPIO
PB8
16
GPIO
PA8
17
GPIO
PA12
18
GPIO (5V)
PA13
19
GPIO (5V)
PA14
20
GPIO
RESETn
21
Reset input, active low. This pin is internally pulled up to AVDD. To apply an
external reset source to this pin, it is required to only drive this pin low during
reset, and let the internal pull-up ensure
that reset is released.
PB11
22
GPIO
PB12
23
GPIO
AVDD
24
Analog power supply.
PB13
25
GPIO
PB14
26
GPIO
PD0
28
GPIO (5V)
PD1
29
GPIO
PD2
30
GPIO (5V)
PD3
31
GPIO
PD4
32
GPIO
PD5
33
GPIO
PD6
34
GPIO
PD8
35
GPIO
VREGVSS
36
Voltage regulator VSS
VREGSW
37
DCDC regulator switching node
VREGVDD
38
Voltage regulator VDD input
DECOUPLE
40
Decouple output for on-chip voltage
regulator. An external decoupling capacitor is required at this pin. This pin
should not be used to power any external circuits.
DVDD
39
Digital power supply.
PE4
41
GPIO
PE5
42
GPIO
PE6
43
GPIO
PE7
44
GPIO
VREGI
45
Input to 5 V regulator.
VREGO
46
Decoupling for 5 V regulator and regulator output. Power for USB PHY in
USB-enabled OPNs
PF10
47
GPIO (5V)
PF11
48
GPIO (5V)
PF0
49
GPIO (5V)
PF1
50
GPIO (5V)
PF2
51
GPIO
VBUS
52
USB VBUS signal and auxiliary input to
5 V regulator.
PF12
53
GPIO (5V)
PF5
54
GPIO
PE8
56
GPIO
PE9
57
GPIO
PE10
58
GPIO
PE11
59
GPIO
PE12
60
GPIO
PE13
61
GPIO
PE14
62
GPIO
PE15
63
GPIO
PA15
64
GPIO
Note:
1. GPIO with 5V tolerance are indicated by (5V).
silabs.com | Building a more connected world.
Rev. 1.0 | 159
EFM32GG12 Family Data Sheet
Pin Definitions
5.17 EFM32GG12B5xx in QFN64 Device Pinout
Figure 5.17. EFM32GG12B5xx in QFN64 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 5.20 GPIO Functionality Table or 5.21 Alternate Functionality Overview.
Table 5.17. EFM32GG12B5xx in QFN64 Device Pinout
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
VSS
0
Ground
PA0
1
GPIO
PA1
2
GPIO
PA2
3
GPIO
PA3
4
GPIO
PA4
5
GPIO
PA5
6
GPIO
PA6
7
GPIO
IOVDD0
8
27
55
Digital IO power supply 0.
PB3
9
GPIO
PB4
10
GPIO
PB5
11
GPIO
silabs.com | Building a more connected world.
Rev. 1.0 | 160
EFM32GG12 Family Data Sheet
Pin Definitions
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PB6
12
GPIO
PC4
13
GPIO
PC5
14
GPIO
PB7
15
GPIO
PB8
16
GPIO
PA8
17
GPIO
PA12
18
GPIO (5V)
PA13
19
GPIO (5V)
PA14
20
GPIO
RESETn
21
Reset input, active low. This pin is internally pulled up to AVDD. To apply an
external reset source to this pin, it is required to only drive this pin low during
reset, and let the internal pull-up ensure
that reset is released.
PB11
22
GPIO
PB12
23
GPIO
AVDD
24
Analog power supply.
PB13
25
GPIO
PB14
26
GPIO
PD0
28
GPIO (5V)
PD1
29
GPIO
PD2
30
GPIO (5V)
PD3
31
GPIO
PD4
32
GPIO
PD5
33
GPIO
PD6
34
GPIO
PD7
35
GPIO
PD8
36
GPIO
PC7
37
GPIO
VREGVSS
38
Voltage regulator VSS
VREGSW
39
DCDC regulator switching node
VREGVDD
40
Voltage regulator VDD input
DECOUPLE
42
Decouple output for on-chip voltage
regulator. An external decoupling capacitor is required at this pin. This pin
should not be used to power any external circuits.
DVDD
41
Digital power supply.
PE4
43
GPIO
PE5
44
GPIO
PE6
45
GPIO
PE7
46
GPIO
PC12
47
GPIO (5V)
PC13
48
GPIO (5V)
PF0
49
GPIO (5V)
PF1
50
GPIO (5V)
PF2
51
GPIO
PF3
52
GPIO
PF4
53
GPIO
PF5
54
GPIO
PE8
56
GPIO
PE9
57
GPIO
PE10
58
GPIO
PE11
59
GPIO
PE12
60
GPIO
PE13
61
GPIO
PE14
62
GPIO
PE15
63
GPIO
PA15
64
GPIO
Note:
1. GPIO with 5V tolerance are indicated by (5V).
silabs.com | Building a more connected world.
Rev. 1.0 | 161
EFM32GG12 Family Data Sheet
Pin Definitions
5.18 EFM32GG12B4xx in QFN64 Device Pinout
Figure 5.18. EFM32GG12B4xx in QFN64 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 5.20 GPIO Functionality Table or 5.21 Alternate Functionality Overview.
Table 5.18. EFM32GG12B4xx in QFN64 Device Pinout
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
VSS
0
Ground
PA0
1
GPIO
PA1
2
GPIO
PA2
3
GPIO
PA3
4
GPIO
PA4
5
GPIO
PA5
6
GPIO
PA6
7
GPIO
IOVDD0
8
26
55
Digital IO power supply 0.
PB3
9
GPIO
PB4
10
GPIO
PB5
11
GPIO
silabs.com | Building a more connected world.
Rev. 1.0 | 162
EFM32GG12 Family Data Sheet
Pin Definitions
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PB6
12
GPIO
PC4
13
GPIO
PC5
14
GPIO
PB7
15
GPIO
PB8
16
GPIO
PA12
17
GPIO (5V)
PA13
18
GPIO (5V)
PA14
19
GPIO
RESETn
20
Reset input, active low. This pin is internally pulled up to AVDD. To apply an
external reset source to this pin, it is required to only drive this pin low during
reset, and let the internal pull-up ensure
that reset is released.
PB11
21
GPIO
PB12
22
GPIO
AVDD
23
27
Analog power supply.
PB13
24
GPIO
PB14
25
GPIO
PD0
28
GPIO (5V)
PD1
29
GPIO
PD2
30
GPIO (5V)
PD3
31
GPIO
PD4
32
GPIO
PD5
33
GPIO
PD6
34
GPIO
PD7
35
GPIO
PD8
36
GPIO
PC6
37
GPIO
PC7
38
GPIO
DVDD
39
Digital power supply.
DECOUPLE
40
Decouple output for on-chip voltage
regulator. An external decoupling capacitor is required at this pin. This pin
should not be used to power any external circuits.
PE4
41
GPIO
PE5
42
GPIO
PE6
43
GPIO
PE7
44
GPIO
VREGI
45
Input to 5 V regulator.
VREGO
46
Decoupling for 5 V regulator and regulator output. Power for USB PHY in
USB-enabled OPNs
PF10
47
GPIO (5V)
PF11
48
GPIO (5V)
PF0
49
GPIO (5V)
PF1
50
GPIO (5V)
PF2
51
GPIO
VBUS
52
USB VBUS signal and auxiliary input to
5 V regulator.
PF12
53
GPIO (5V)
PF5
54
GPIO
PE8
56
GPIO
PE9
57
GPIO
PE10
58
GPIO
PE11
59
GPIO
PE12
60
GPIO
PE13
61
GPIO
PE14
62
GPIO
PE15
63
GPIO
PA15
64
GPIO
Note:
1. GPIO with 5V tolerance are indicated by (5V).
silabs.com | Building a more connected world.
Rev. 1.0 | 163
EFM32GG12 Family Data Sheet
Pin Definitions
5.19 EFM32GG12B1xx in QFN64 Device Pinout
Figure 5.19. EFM32GG12B1xx in QFN64 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 5.20 GPIO Functionality Table or 5.21 Alternate Functionality Overview.
Table 5.19. EFM32GG12B1xx in QFN64 Device Pinout
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
VSS
0
Ground
PA0
1
GPIO
PA1
2
GPIO
PA2
3
GPIO
PA3
4
GPIO
PA4
5
GPIO
PA5
6
GPIO
PA6
7
GPIO
IOVDD0
8
26
55
Digital IO power supply 0.
PC0
9
GPIO (5V)
PC1
10
GPIO (5V)
PC2
11
GPIO (5V)
silabs.com | Building a more connected world.
Rev. 1.0 | 164
EFM32GG12 Family Data Sheet
Pin Definitions
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PC3
12
GPIO (5V)
PC4
13
GPIO
PC5
14
GPIO
PB7
15
GPIO
PB8
16
GPIO
PA8
17
GPIO
PA9
18
GPIO
PA10
19
GPIO
RESETn
20
Reset input, active low. This pin is internally pulled up to AVDD. To apply an
external reset source to this pin, it is required to only drive this pin low during
reset, and let the internal pull-up ensure
that reset is released.
PB11
21
GPIO
PB12
22
GPIO
AVDD
23
27
Analog power supply.
PB13
24
GPIO
PB14
25
GPIO
PD0
28
GPIO (5V)
PD1
29
GPIO
PD2
30
GPIO (5V)
PD3
31
GPIO
PD4
32
GPIO
PD5
33
GPIO
PD6
34
GPIO
PD7
35
GPIO
PD8
36
GPIO
PC6
37
GPIO
PC7
38
GPIO
DVDD
39
Digital power supply.
DECOUPLE
40
Decouple output for on-chip voltage
regulator. An external decoupling capacitor is required at this pin. This pin
should not be used to power any external circuits.
PC8
41
GPIO (5V)
PC9
42
GPIO (5V)
PC10
43
GPIO (5V)
PC11
44
GPIO (5V)
PC12
45
GPIO (5V)
PC13
46
GPIO (5V)
PC14
47
GPIO (5V)
PC15
48
GPIO (5V)
PF0
49
GPIO (5V)
PF1
50
GPIO (5V)
PF2
51
GPIO
PF3
52
GPIO
PF4
53
GPIO
PF5
54
GPIO
PE8
56
GPIO
PE9
57
GPIO
PE10
58
GPIO
PE11
59
GPIO
PE12
60
GPIO
PE13
61
GPIO
PE14
62
GPIO
PE15
63
GPIO
PA15
64
GPIO
Note:
1. GPIO with 5V tolerance are indicated by (5V).
silabs.com | Building a more connected world.
Rev. 1.0 | 165
EFM32GG12 Family Data Sheet
Pin Definitions
5.20 GPIO Functionality Table
A wide selection of alternate functionality is available for multiplexing to various pins. The following table shows the name of each GPIO
pin, followed by the functionality available on that pin. Refer to 5.21 Alternate Functionality Overview for a list of GPIO locations available for each function.
Table 5.20. GPIO Functionality Table
GPIO Name
Pin Alternate Functionality / Description
Analog
EBI
Timers
Communication
SDIO_DAT0 #1
BUSBY
PA0
BUSAX
LCD_SEG13
TIM0_CC0 #0
US1_RX #5
EBI_AD09 #0
TIM0_CC1 #7
US3_TX #0
EBI_CSTFT #3
TIM3_CC0 #4
QSPI0_CS0 #1
PCNT0_S0IN #4
LEU0_RX #4
I2C0_SDA #0
BUSAY
PA1
BUSBX
LCD_SEG14
BUSBY
PA2
BUSAX
LCD_SEG15
TIM0_CC0 #7
SDIO_DAT1 #1
EBI_AD10 #0
TIM0_CC1 #0
US3_RX #0
EBI_DCLK #3
TIM3_CC1 #4
QSPI0_CS1 #1
PCNT0_S1IN #4
I2C0_SCL #0
Other
PDM_CLK #0
CMU_CLK2 #0
PRS_CH0 #0
PRS_CH3 #3
GPIO_EM4WU0
PDM_DAT0 #0
CMU_CLK1 #0
PRS_CH1 #0
SDIO_DAT2 #1
PDM_DAT1 #0
EBI_AD11 #0
TIM0_CC2 #0
US1_RX #6
CMU_CLK0 #0
EBI_DTEN #3
TIM3_CC2 #4
US3_CLK #0
PRS_CH8 #1
QSPI0_DQ0 #1
ETM_TD0 #3
CMU_CLK2 #1
BUSAY
PA3
BUSBX
LCD_SEG16
SDIO_DAT3 #1
EBI_AD12 #0
TIM0_CDTI0 #0
US3_CS #0
EBI_VSNC #3
TIM3_CC0 #5
U0_TX #2
QSPI0_DQ1 #1
CMU_CLKI0 #1
PDM_DAT2 #0
CMU_CLK2 #4
LES_ALTEX2
PRS_CH9 #1
ETM_TD1 #3
BUSBY
PA4
BUSAX
LCD_SEG17
SDIO_DAT4 #1
EBI_AD13 #0
TIM0_CDTI1 #0
US3_CTS #0
EBI_HSNC #3
TIM3_CC1 #5
U0_RX #2
QSPI0_DQ2 #1
PDM_DAT3 #0
LES_ALTEX3
ETM_TD2 #3
SDIO_DAT5 #1
BUSAY
PA5
BUSBX
LCD_SEG18
EBI_AD14 #0
TIM0_CDTI2 #0
US3_RTS #0
LES_ALTEX4
TIM3_CC2 #5
U0_CTS #2
ACMP1_O #7
PCNT1_S0IN #0
QSPI0_DQ3 #1
ETM_TD3 #3
LEU1_TX #1
silabs.com | Building a more connected world.
Rev. 1.0 | 166
EFM32GG12 Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
EBI
TIM3_CC0 #6
BUSBY
PA6
BUSAX
EBI_AD15 #0
LCD_SEG19
PA7
PA8
PA9
PA10
PA11
PA12
LETIM1_OUT1 #0
BUSAY
EBI_AD13 #1
TIM0_CC2 #5
BUSBX
EBI_A01 #3
LETIM1_OUT0 #0
LCD_SEG35
EBI_CSTFT #0
PCNT1_S0IN #4
BUSBY
EBI_AD14 #1
BUSAX
EBI_A02 #3
LCD_SEG36
EBI_DCLK #0
BUSAY
EBI_AD15 #1
TIM2_CC1 #0
BUSBX
EBI_A03 #3
TIM0_CC1 #6
LCD_SEG37
EBI_DTEN #0
LETIM0_OUT1 #6
BUSBY
EBI_CS0 #1
BUSAX
EBI_A04 #3
LCD_SEG38
EBI_VSNC #0
BUSAY
EBI_CS1 #1
BUSBX
EBI_A05 #3
LCD_SEG39
EBI_HSNC #0
US2_TX #2
US4_CTS #0
US4_RTS #0
Other
PRS_CH6 #0
ACMP0_O #4
ETM_TCLK #3
GPIO_EM4WU1
PRS_CH7 #1
PRS_CH8 #0
PCNT1_S1IN #4
TIM2_CC2 #0
TIM0_CC2 #6
LETIM1_OUT0 #1
WTIM0_CDTI0 #2
BUSAX
EBI_A00 #0
LETIM1_OUT0 #2
EBI_A06 #3
PCNT1_S0IN #5
EBI_A01 #0
LEU1_RX #1
LETIM0_OUT0 #6
EBI_REn #2
BUSBX
U0_RTS #2
US2_RX #2
BUSBY
EBI_NANDWEn #2
SDIO_CD #2
TIM0_CC0 #6
TIM2_CC0 #1
BUSAY
Communication
TIM2_CC0 #0
EBI_CS2 #1
EBI_A07 #3
PA14
WTIM0_CC0 #1
PCNT1_S1IN #0
EBI_WEn #1
PA13
Timers
US2_CLK #2
PRS_CH9 #0
US2_CS #2
PRS_CH10 #0
US2_CTS #2
PRS_CH11 #0
CAN1_RX #5
CMU_CLK0 #5
US0_CLK #5
PRS_CH12 #0
US2_RTS #2
ACMP1_O #3
TIM0_CC2 #7
TIM2_CC1 #1
CAN1_TX #5
WTIM0_CDTI1 #2
US0_CS #5
LETIM1_OUT1 #1
US2_TX #3
PDM_DAT3 #3
PRS_CH13 #0
PCNT1_S1IN #5
BUSBY
EBI_REn #1
TIM2_CC2 #1
US1_TX #6
BUSAX
EBI_A02 #0
WTIM0_CDTI2 #2
US2_RX #3
LCD_BEXT
EBI_A08 #3
LETIM1_OUT1 #2
US3_RTS #2
EBI_AD08 #0
TIM3_CC2 #0
US2_CLK #3
PRS_CH14 #0
ACMP1_O #4
BUSAY
PA15
BUSBX
PRS_CH15 #0
LCD_SEG12
silabs.com | Building a more connected world.
Rev. 1.0 | 167
EFM32GG12 Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
EBI
Timers
Communication
Other
TIM2_CDTI0 #0
PB0
BUSBY
EBI_AD00 #1
BUSAX
EBI_CS0 #3
LCD_SEG32
EBI_A16 #0
TIM1_CC0 #2
TIM3_CC2 #7
WTIM0_CC0 #5
LEU1_TX #3
PRS_CH4 #1
ACMP0_O #5
PCNT0_S0IN #5
PCNT1_S1IN #2
TIM2_CDTI1 #0
PB1
BUSAY
EBI_AD01 #1
TIM1_CC1 #2
BUSBX
EBI_CS1 #3
WTIM0_CC1 #5
LCD_SEG33
EBI_A17 #0
LETIM1_OUT1 #5
LEU1_RX #3
PRS_CH5 #1
US1_CS #6
ACMP0_O #6
PCNT0_S1IN #5
PB2
BUSBY
EBI_AD02 #1
BUSAX
EBI_CS2 #3
LCD_SEG34
EBI_A18 #0
BUSAY
PB3
BUSBX
LCD_SEG20 /
LCD_COM4
BUSBY
PB4
BUSAX
LCD_SEG21 /
LCD_COM5
BUSAY
PB5
BUSBX
LCD_SEG22 /
LCD_COM6
BUSBY
PB6
BUSAX
LCD_SEG23 /
LCD_COM7
TIM2_CDTI2 #0
TIM1_CC2 #2
WTIM0_CC2 #5
LETIM1_OUT0 #5
EBI_AD03 #1
TIM1_CC3 #2
EBI_CS3 #3
WTIM0_CC0 #6
EBI_A19 #0
PCNT1_S0IN #1
EBI_AD04 #1
EBI_ARDY #3
EBI_A20 #0
ACMP0_O #7
QSPI0_DQ4 #1
US2_RX #1
PCNT1_S1IN #1
QSPI0_DQ5 #1
LEU1_TX #4
EBI_ALE #3
LETIM1_OUT0 #4
EBI_A21 #0
PCNT0_S0IN #6
EBI_A22 #0
US3_TX #2
WTIM0_CC1 #6
WTIM0_CC2 #6
EBI_WEn #3
US2_TX #1
SDIO_DAT7 #1
EBI_AD05 #1
EBI_AD06 #1
SDIO_DAT6 #1
TIM0_CC0 #3
TIM2_CC0 #4
LETIM1_OUT1 #4
PCNT0_S1IN #6
US0_RTS #4
US2_CLK #1
QSPI0_DQ6 #1
LEU1_RX #4
US0_CTS #4
US2_CS #1
PRS_CH12 #1
QSPI0_DQ7 #1
US0_TX #4
PB7
LFXTAL_P
TIM0_CDTI0 #4
TIM1_CC0 #3
US1_CLK #0
US3_RX #2
US4_TX #0
U0_CTS #4
silabs.com | Building a more connected world.
Rev. 1.0 | 168
EFM32GG12 Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
EBI
Timers
Communication
Other
US0_RX #4
PB8
LFXTAL_N
TIM0_CDTI1 #4
US1_CS #0
TIM1_CC1 #3
US4_RX #0
CMU_CLKI0 #2
U0_RTS #4
EBI_ALE #1
PB9
BUSAY
BUSBX
SDIO_WP #3
EBI_NANDREn #2
EBI_A00 #1
LETIM0_OUT0 #7
EBI_A03 #0
PB10
BUSAX
EBI_A04 #0
LETIM0_OUT1 #7
EBI_A10 #3
BUSAY
PB11
PB12
CAN0_TX #3
PDM_DAT1 #3
US1_RTS #0
PRS_CH9 #2
US2_CTS #3
ACMP1_O #6
U1_RX #2
TIM0_CDTI2 #4
US0_CTS #5
CMU_CLK1 #5
TIM1_CC2 #3
US1_CLK #5
CMU_CLKI0 #7
VDAC0_OUT0 /
OPA0_OUT
EBI_A02 #1
LETIM0_OUT0 #1
US2_CS #3
PDM_DAT0 #3
EBI_A11 #3
PCNT0_S1IN #7
U1_CTS #2
ACMP0_O #3
IDAC0_OUT
PCNT1_S0IN #6
I2C1_SDA #1
GPIO_EM4WU7
BUSBY
TIM1_CC3 #3
BUSAX
EBI_A03 #1
LETIM0_OUT1 #1
VDAC0_OUT1 /
OPA1_OUT
EBI_A12 #3
PCNT0_S0IN #7
PCNT1_S1IN #6
WTIM1_CC0 #0
BUSBX
PCNT2_S0IN #2
BUSBY
WTIM1_CC1 #0
BUSAX
PCNT2_S1IN #2
HFXTAL_N
PB15
ACMP1_O #5
EBI_BL1 #2
HFXTAL_P
PB14
PRS_CH13 #1
BUSBX
BUSAY
PB13
PDM_DAT2 #3
SDIO_CD #3
EBI_BL0 #2
EBI_A01 #1
US1_CTS #0
U1_TX #2
EBI_A09 #3
BUSBY
CAN0_RX #3
BUSAY
EBI_CS3 #1
BUSBX
EBI_ARDY #2
silabs.com | Building a more connected world.
TIM3_CC1 #7
US2_CTS #1
U1_RTS #2
PDM_CLK #3
I2C1_SCL #1
US0_CLK #4
US1_CTS #5
LEU0_TX #1
CMU_CLKI0 #3
PRS_CH7 #0
US0_CS #4
US1_RTS #5
PRS_CH6 #1
LEU0_RX #1
SDIO_WP #2
US2_RTS #1
ETM_TD2 #1
Rev. 1.0 | 169
EFM32GG12 Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
EBI
Timers
Communication
Other
CAN0_RX #0
VDAC0_OUT0ALT /
OPA0_OUTALT #0
PC0
BUSACMP0Y
BUSACMP0X
EBI_AD07 #1
EBI_CS0 #2
EBI_REn #3
EBI_A23 #0
US0_TX #5
TIM0_CC1 #3
US1_TX #0
TIM2_CC1 #4
US1_CS #4
PCNT0_S0IN #2
US2_RTS #0
LES_CH0
PRS_CH2 #0
US3_CS #3
I2C0_SDA #4
CAN0_TX #0
VDAC0_OUT0ALT /
OPA0_OUTALT #1
PC1
BUSACMP0Y
BUSACMP0X
EBI_AD08 #1
TIM0_CC2 #3
EBI_CS1 #2
TIM2_CC2 #4
EBI_BL0 #3
WTIM0_CC0 #7
EBI_A24 #0
PCNT0_S1IN #2
US0_RX #5
US1_TX #4
US1_RX #0
US2_CTS #0
LES_CH1
PRS_CH3 #0
US3_RTS #1
I2C0_SCL #4
PC2
PC3
VDAC0_OUT0ALT /
OPA0_OUTALT #2
EBI_AD09 #1
TIM0_CDTI0 #3
CAN1_RX #0
EBI_CS2 #2
TIM2_CC0 #5
US1_RX #4
LES_CH2
BUSACMP0Y
EBI_NANDWEn #3
WTIM0_CC1 #7
US2_TX #0
PRS_CH10 #1
BUSACMP0X
EBI_A25 #0
LETIM1_OUT0 #3
QSPI0_RST0 #1
VDAC0_OUT0ALT /
OPA0_OUTALT #3
EBI_AD10 #1
TIM0_CDTI1 #3
CAN1_TX #0
EBI_CS3 #2
TIM2_CC1 #5
US1_CLK #4
LES_CH3
BUSACMP0Y
EBI_BL1 #3
WTIM0_CC2 #7
US2_RX #0
PRS_CH11 #1
BUSACMP0X
EBI_NANDREn #0
LETIM1_OUT1 #3
QSPI0_RST1 #1
BUSACMP0Y
PC4
BUSACMP0X
OPA0_P
EBI_AD11 #1
EBI_ALE #2
EBI_NANDREn #3
EBI_A26 #0
TIM0_CC0 #5
TIM0_CDTI2 #3
TIM2_CC2 #5
LETIM0_OUT0 #3
PCNT1_S0IN #3
SDIO_CD #1
US2_CLK #0
US4_CLK #0
LES_CH4
U0_TX #4
GPIO_EM4WU6
U1_CTS #4
I2C1_SDA #0
SDIO_WP #1
BUSACMP0Y
PC5
BUSACMP0X
OPA0_N
EBI_AD12 #1
EBI_WEn #2
EBI_NANDWEn #0
EBI_A00 #3
TIM0_CC1 #5
LETIM0_OUT1 #3
PCNT1_S1IN #3
US2_CS #0
US4_CS #0
U0_RX #4
LES_CH5
U1_RTS #4
I2C1_SCL #0
silabs.com | Building a more connected world.
Rev. 1.0 | 170
EFM32GG12 Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
EBI
Timers
US0_RTS #2
BUSACMP0Y
PC6
BUSACMP0X
EBI_A05 #0
WTIM1_CC3 #2
OPA3_P
PC7
PC8
PC9
PC10
PC11
EBI_A06 #0
BUSACMP0X
EBI_A13 #1
OPA3_N
EBI_A21 #3
BUSACMP1X
EBI_A20 #1
BUSACMP1X
EBI_A27 #3
BUSACMP1Y
BUSACMP1X
US0_CTS #2
WTIM1_CC0 #3
US1_RTS #3
LEU1_RX #0
I2C0_SCL #2
TIM2_CC0 #2
US0_CS #2
EBI_A26 #3
EBI_A21 #1
BUSACMP1X
LEU1_TX #0
EBI_A15 #0
BUSACMP1Y
BUSACMP1Y
US1_CTS #3
I2C0_SDA #2
BUSACMP0Y
BUSACMP1Y
Communication
EBI_A22 #1
TIM2_CC1 #2
TIM2_CC2 #2
CAN1_RX #3
US0_CLK #2
CAN1_TX #3
US0_RX #2
EBI_ALE #4
CAN1_TX #4
EBI_ALE #5
US0_TX #2
EBI_A23 #1
I2C1_SDA #4
Other
LES_CH6
PRS_CH14 #1
ETM_TCLK #2
LES_CH7
PRS_CH15 #1
ETM_TD0 #2
LES_CH8
PRS_CH4 #0
LES_CH9
PRS_CH5 #0
GPIO_EM4WU2
LES_CH10
LES_CH11
CAN1_RX #4
PC12
US0_RTS #3
VDAC0_OUT1ALT /
OPA1_OUTALT #0
TIM1_CC3 #0
US1_CTS #4
CMU_CLK0 #1
BUSACMP1Y
PCNT2_S0IN #4
US2_CTS #4
LES_CH12
BUSACMP1X
U0_RTS #3
U1_TX #0
VDAC0_OUT1ALT /
OPA1_OUTALT #1
PC13
BUSACMP1Y
BUSACMP1X
silabs.com | Building a more connected world.
EBI_ARDY #4
TIM0_CDTI0 #1
US0_CTS #3
TIM1_CC0 #0
US1_RTS #4
TIM1_CC2 #4
US2_RTS #4
PCNT0_S0IN #0
U0_CTS #3
PCNT2_S1IN #4
U1_RX #0
LES_CH13
Rev. 1.0 | 171
EFM32GG12 Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
EBI
Timers
Communication
Other
US0_CS #3
VDAC0_OUT1ALT /
OPA1_OUTALT #2
PC14
BUSACMP1Y
EBI_NANDWEn #4
BUSACMP1X
TIM0_CDTI1 #1
US1_CS #3
TIM1_CC1 #0
US2_RTS #3
TIM1_CC3 #4
US3_CS #2
LETIM0_OUT0 #5
U0_TX #3
PCNT0_S1IN #0
U1_CTS #0
LES_CH14
PRS_CH0 #2
LEU0_TX #5
US0_CLK #3
VDAC0_OUT1ALT /
OPA1_OUTALT #3
PC15
BUSACMP1Y
EBI_NANDREn #4
BUSACMP1X
TIM0_CDTI2 #1
US1_CLK #3
TIM1_CC2 #0
US3_RTS #3
WTIM0_CC0 #4
U0_RX #3
LETIM0_OUT1 #5
U1_RTS #0
LES_CH15
PRS_CH1 #2
DBG_SWO #1
LEU0_RX #5
VDAC0_OUT0ALT /
OPA0_OUTALT #4
PD0
OPA2_OUTALT
BUSADC0Y
EBI_A04 #1
WTIM1_CC2 #0
EBI_A13 #3
PCNT2_S0IN #0
CAN0_RX #2
US1_TX #1
PDM_CLK #4
USB_VBUSEN #2
BUSADC0X
VDAC0_OUT1ALT /
OPA1_OUTALT #4
PD1
BUSADC0Y
BUSADC0X
EBI_A05 #1
EBI_A14 #3
TIM0_CC0 #2
CAN0_TX #2
PDM_DAT0 #4
US1_RX #1
DBG_SWO #2
TIM0_CC1 #2
US1_CLK #1
PDM_DAT1 #4
WTIM1_CC0 #1
LEU1_TX #2
DBG_SWO #3
CAN1_RX #2
PDM_DAT2 #4
US1_CS #1
ETM_TD1 #0
LEU1_RX #2
ETM_TD1 #2
CAN1_TX #2
CMU_CLKI0 #0
US1_CTS #1
PDM_DAT3 #4
US3_CLK #2
PRS_CH10 #2
LEU0_TX #0
ETM_TD2 #0
I2C1_SDA #3
ETM_TD2 #2
WTIM1_CC3 #0
PCNT2_S1IN #0
OPA3_OUT
PD2
BUSADC0Y
BUSADC0X
BUSADC0Y
PD3
BUSADC0X
OPA2_N
BUSADC0Y
PD4
BUSADC0X
OPA2_P
silabs.com | Building a more connected world.
EBI_A06 #1
EBI_A15 #3
EBI_A27 #0
EBI_A07 #1
TIM0_CC2 #2
EBI_A16 #3
WTIM1_CC1 #1
EBI_A08 #1
WTIM0_CDTI0 #4
EBI_A17 #3
WTIM1_CC2 #1
Rev. 1.0 | 172
EFM32GG12 Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
BUSADC0Y
PD5
BUSADC0X
OPA2_OUT
EBI
EBI_A09 #1
WTIM0_CDTI1 #4
U0_CTS #5
EBI_A18 #3
WTIM1_CC3 #1
LEU0_RX #0
I2C1_SCL #3
TIM1_CC0 #4
BUSADC0X
ADC0_EXTP
EBI_A10 #1
VDAC0_EXT
EBI_A19 #3
ADC1_EXTP
BUSADC0Y
PD7
ADC0_EXTN
ADC1_EXTN
WTIM0_CDTI2 #4
WTIM1_CC0 #2
LETIM0_OUT0 #0
PCNT0_S0IN #3
OPA1_P
BUSADC0X
Communication
US1_RTS #1
BUSADC0Y
PD6
Timers
US0_RTS #5
US1_RX #2
US2_CTS #5
US3_CTS #2
U0_RTS #5
I2C0_SDA #1
Other
PRS_CH11 #2
ETM_TD3 #0
ETM_TD3 #2
CMU_CLK2 #2
LES_ALTEX0
PRS_CH5 #2
ACMP0_O #2
ETM_TD0 #0
TIM1_CC1 #4
US1_TX #2
CMU_CLK0 #2
EBI_A11 #1
WTIM1_CC1 #2
US3_CLK #1
LES_ALTEX1
EBI_A20 #3
LETIM0_OUT1 #0
U0_TX #6
ACMP1_O #2
PCNT0_S1IN #3
I2C0_SCL #1
ETM_TCLK #0
OPA1_N
CMU_CLK1 #1
PD8
BU_VIN
EBI_A12 #1
WTIM1_CC2 #2
US2_RTS #5
PRS_CH12 #2
ACMP2_O #0
PD9
PD10
PD11
LCD_SEG28
LCD_SEG29
LCD_SEG30
SDIO_DAT7 #0
EBI_CS0 #0
QSPI0_DQ0 #0
EBI_DTEN #1
PDM_DAT3 #2
US4_TX #1
SDIO_DAT6 #0
EBI_CS1 #0
QSPI0_DQ1 #0
EBI_VSNC #1
US4_RX #1
CMU_CLK2 #5
CMU_CLKI0 #5
SDIO_DAT5 #0
EBI_CS2 #0
QSPI0_DQ2 #0
EBI_HSNC #1
US4_CLK #1
SDIO_DAT4 #0
PD12
LCD_SEG31
EBI_CS3 #0
QSPI0_DQ3 #0
US4_CS #1
TIM2_CDTI0 #1
PD13
EBI_ARDY #1
TIM3_CC1 #6
US4_CTS #1
ETM_TD1 #1
WTIM0_CC1 #1
PD14
silabs.com | Building a more connected world.
EBI_NANDWEn #1
TIM2_CDTI1 #1
CAN0_RX #5
TIM3_CC2 #6
US4_RTS #1
WTIM0_CC2 #1
I2C0_SDA #3
Rev. 1.0 | 173
EFM32GG12 Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
EBI
Timers
Communication
Other
TIM2_CDTI2 #1
PD15
EBI_NANDREn #1
TIM3_CC0 #7
CAN0_TX #5
WTIM0_CDTI0 #1
I2C0_SCL #3
PCNT1_S0IN #2
PE0
PE1
PE2
PE3
BUSDY
BUSCX
BUSCY
BUSDX
BU_VOUT
BU_STAT
EBI_A07 #0
EBI_A08 #0
TIM3_CC0 #1
CAN0_RX #6
WTIM1_CC1 #3
U0_TX #1
PCNT0_S0IN #1
I2C1_SDA #2
TIM3_CC1 #1
CAN0_TX #6
WTIM1_CC2 #3
U0_RX #1
PCNT0_S1IN #1
I2C1_SCL #2
EBI_A09 #0
TIM3_CC2 #1
EBI_A14 #1
WTIM1_CC3 #3
EBI_A10 #0
TIM3_CC0 #2
EBI_A15 #1
WTIM1_CC0 #4
ACMP2_O #1
CMU_CLKI0 #4
ACMP2_O #2
US0_RTS #1
U0_CTS #1
ACMP0_O #1
U1_TX #3
US0_CTS #1
U0_RTS #1
ACMP1_O #1
U1_RX #3
US0_CS #1
US1_CS #5
PE4
BUSDY
EBI_A11 #0
TIM3_CC1 #2
US3_CS #1
BUSCX
EBI_A16 #1
WTIM0_CC0 #0
U0_RX #6
LCD_COM0
EBI_A22 #3
WTIM1_CC1 #4
U1_CTS #3
I2C0_SDA #7
USB_VBUSEN #1
PE5
PE6
PE7
BUSCY
EBI_A12 #0
BUSDX
EBI_A17 #1
LCD_COM1
EBI_A23 #3
TIM3_CC0 #3
TIM3_CC2 #2
WTIM0_CC1 #0
WTIM1_CC2 #4
BUSDY
EBI_A13 #0
TIM3_CC1 #3
BUSCX
EBI_A18 #1
WTIM0_CC2 #0
LCD_COM2
EBI_A24 #3
WTIM1_CC3 #4
BUSCY
EBI_A14 #0
BUSDX
EBI_A19 #1
LCD_COM3
EBI_A25 #3
silabs.com | Building a more connected world.
US0_CLK #1
US1_CLK #6
US3_CTS #1
U1_RTS #3
I2C0_SCL #7
US0_RX #1
US3_TX #1
TIM3_CC2 #3
US0_TX #1
WTIM1_CC0 #5
US3_RX #1
PRS_CH6 #2
PRS_CH7 #2
Rev. 1.0 | 174
EFM32GG12 Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
BUSDY
PE8
BUSCX
LCD_SEG4
BUSCY
PE9
BUSDX
LCD_SEG5
BUSDY
PE10
BUSCX
LCD_SEG6
BUSCY
PE11
BUSDX
LCD_SEG7
EBI
Timers
Communication
Other
EBI_AD00 #0
TIM2_CDTI0 #2
SDIO_DAT3 #0
PDM_CLK #1
EBI_CS0 #4
PCNT2_S0IN #1
QSPI0_DQ4 #0
PRS_CH3 #1
SDIO_DAT2 #0
PDM_DAT0 #1
QSPI0_DQ5 #0
PRS_CH8 #2
SDIO_DAT1 #0
PDM_DAT1 #1
QSPI0_DQ6 #0
PRS_CH2 #2
US0_TX #0
GPIO_EM4WU9
EBI_AD01 #0
EBI_CS1 #4
EBI_AD02 #0
TIM1_CC0 #1
EBI_CS2 #4
WTIM0_CDTI0 #0
EBI_AD03 #0
TIM1_CC1 #1
EBI_CS3 #4
WTIM0_CDTI1 #0
TIM1_CC2 #1
BUSDY
PE12
BUSCX
EBI_AD04 #0
LCD_SEG8
BUSDX
TIM2_CC1 #3
WTIM0_CDTI2 #0
LETIM0_OUT0 #4
BUSCY
PE13
PCNT2_S1IN #1
EBI_AD05 #0
LCD_SEG9
SDIO_DAT0 #0
QSPI0_DQ7 #0
US0_RX #0
SDIO_CMD #0
US0_RX #3
US0_CLK #0
U1_TX #4
I2C0_SDA #6
LES_ALTEX5
PDM_DAT2 #1
PRS_CH3 #2
ETM_TCLK #4
CMU_CLK1 #2
CMU_CLKI0 #6
LES_ALTEX6
PDM_DAT3 #1
PRS_CH1 #3
ETM_TD0 #4
SDIO_CLK #0
LES_ALTEX7
TIM1_CC3 #1
US0_TX #3
PRS_CH2 #3
TIM2_CC2 #3
US0_CS #0
ACMP0_O #0
LETIM0_OUT1 #4
U1_RX #4
ETM_TD1 #4
I2C0_SCL #6
GPIO_EM4WU5
QSPI0_RST0 #0
BUSDY
PE14
BUSCX
EBI_AD06 #0
LCD_SEG10
TIM2_CDTI1 #2
TIM3_CC0 #0
SDIO_CLK #1
US0_CTS #0
QSPI0_SCLK #1
PRS_CH13 #2
ETM_TD2 #4
LEU0_TX #2
QSPI0_RST1 #0
BUSCY
PE15
BUSDX
LCD_SEG11
EBI_AD07 #0
TIM2_CDTI2 #2
TIM3_CC1 #0
SDIO_CMD #1
US0_RTS #0
QSPI0_DQS #1
PRS_CH14 #2
ETM_TD3 #4
LEU0_RX #2
silabs.com | Building a more connected world.
Rev. 1.0 | 175
EFM32GG12 Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
EBI
Timers
Communication
Other
US2_TX #5
PF0
BUSDY
BUSCX
EBI_A24 #1
TIM0_CC0 #4
CAN0_RX #1
PRS_CH15 #2
WTIM0_CC1 #4
US1_CLK #2
DBG_SWCLKTCK
LETIM0_OUT0 #2
LEU0_TX #3
BOOT_TX
I2C0_SDA #5
US2_RX #5
PF1
BUSCY
BUSDX
TIM0_CC1 #4
EBI_A25 #1
WTIM0_CC2 #4
LETIM0_OUT1 #2
CAN1_RX #1
PRS_CH4 #2
US1_CS #2
DBG_SWDIOTMS
U0_TX #5
GPIO_EM4WU3
LEU0_RX #3
BOOT_RX
I2C0_SCL #5
BUSDY
PF2
BUSCX
LCD_SEG0
EBI_ARDY #0
EBI_A26 #1
BUSCY
PF3
BUSDX
EBI_ALE #0
LCD_SEG1
BUSDY
PF4
BUSCX
LCD_SEG2
PF5
PF6
LCD_SEG3
EBI_A27 #1
BUSCY
PF7
BUSDX
LCD_SEG25
silabs.com | Building a more connected world.
EBI_BL0 #5
PRS_CH0 #3
US1_TX #5
ACMP1_O #0
U0_RX #5
DBG_TDO
LEU0_TX #4
DBG_SWO #0
I2C1_SCL #4
GPIO_EM4WU4
TIM1_CC1 #5
US1_CTS #2
US2_CS #5
PRS_CH2 #1
TIM1_CC3 #6
USB_VBUSEN #0
DBG_TDI
US2_TX #4
TIM0_CC0 #1
QSPI0_SCLK #0
US1_TX #3
EBI_BL1 #0
US2_RX #4
EBI_DCLK #1
ETM_TD3 #1
TIM0_CDTI2 #2
U0_TX #0
EBI_BL1 #5
PRS_CH0 #1
PRS_CH1 #1
EBI_CSTFT #1
EBI_BL1 #4
CMU_CLK1 #4
US1_RTS #2
EBI_BL0 #0
EBI_BL0 #4
CAN0_TX #1
CAN1_TX #1
TIM1_CC2 #5
EBI_REn #5
CMU_CLK0 #4
TIM0_CDTI0 #2
EBI_WEn #5
BUSDX
LCD_SEG24
TIM2_CC0 #3
TIM0_CDTI1 #2
EBI_REn #0
BUSCX
TIM1_CC0 #5
EBI_WEn #0
BUSCY
BUSDY
TIM0_CC2 #4
US2_CLK #5
TIM0_CC1 #1
QSPI0_CS0 #0
US1_RX #3
PDM_CLK #2
PDM_DAT0 #2
U0_RX #0
Rev. 1.0 | 176
EFM32GG12 Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
EBI
Timers
Communication
Other
US2_CLK #4
BUSDY
PF8
BUSCX
LCD_SEG26
EBI_WEn #4
EBI_BL0 #1
TIM0_CC2 #1
QSPI0_CS1 #0
PDM_DAT1 #2
SDIO_CD #0
ETM_TCLK #1
U0_CTS #0
GPIO_EM4WU8
U1_RTS #1
US2_CS #4
BUSCY
PF9
BUSDX
LCD_SEG27
QSPI0_DQS #0
EBI_REn #4
SDIO_WP #0
EBI_BL1 #1
U0_RTS #0
PDM_DAT2 #2
ETM_TD0 #1
U1_CTS #1
PF10
PF11
PF12
PF13
PF14
BUSDY
BUSCX
BUSCY
BUSDX
BUSDY
BUSCX
BUSCY
BUSDX
BUSDY
BUSCX
silabs.com | Building a more connected world.
EBI_ARDY #5
PCNT2_S0IN #3
EBI_NANDWEn #5
PCNT2_S1IN #3
EBI_NANDREn #5
TIM1_CC3 #5
U1_TX #1
USB_DM
U1_RX #1
USB_DP
USB_ID
TIM1_CC0 #6
TIM1_CC1 #6
Rev. 1.0 | 177
EFM32GG12 Family Data Sheet
Pin Definitions
5.21 Alternate Functionality Overview
A wide selection of alternate functionality is available for multiplexing to various pins. The following table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings and the associated GPIO
pin. Refer to 5.20 GPIO Functionality Table for a list of functions available on each GPIO pin.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.
Table 5.21. Alternate Functionality Overview
Alternate
Functionality
ACMP0_O
ACMP1_O
LOCATION
0-3
4-7
0: PE13
4: PA6
1: PE2
5: PB0
2: PD6
6: PB2
3: PB11
7: PB3
0: PF2
4: PA14
1: PE3
5: PB9
2: PD7
6: PB10
3: PA12
7: PA5
Description
Analog comparator ACMP0, digital output.
Analog comparator ACMP1, digital output.
0: PD8
ACMP2_O
1: PE0
Analog comparator ACMP2, digital output.
2: PE1
ADC0_EXTN
0: PD7
Analog to digital converter ADC0 external reference input negative pin.
ADC0_EXTP
0: PD6
Analog to digital converter ADC0 external reference input positive pin.
ADC1_EXTN
0: PD7
Analog to digital converter ADC1 external reference input negative pin.
ADC1_EXTP
0: PD6
Analog to digital converter ADC1 external reference input positive pin.
BOOT_RX
0: PF1
Bootloader RX.
BOOT_TX
0: PF0
Bootloader TX.
BU_STAT
0: PE3
Backup Power Domain status, whether or not the system is in backup mode.
BU_VIN
0: PD8
Battery input for Backup Power Domain.
BU_VOUT
0: PE2
Power output for Backup Power Domain.
CAN0_RX
0: PC0
5: PD14
1: PF0
6: PE0
2: PD0
CAN0 RX.
3: PB9
CAN0_TX
0: PC1
5: PD15
1: PF2
6: PE1
2: PD1
CAN0 TX.
3: PB10
silabs.com | Building a more connected world.
Rev. 1.0 | 178
EFM32GG12 Family Data Sheet
Pin Definitions
Alternate
Functionality
CAN1_RX
LOCATION
0-3
4-7
0: PC2
4: PC12
1: PF1
5: PA12
2: PD3
Description
CAN1 RX.
3: PC9
CAN1_TX
0: PC3
4: PC11
1: PF3
5: PA13
2: PD4
CAN1 TX.
3: PC10
CMU_CLK0
0: PA2
4: PF2
1: PC12
5: PA12
Clock Management Unit, clock output number 0.
2: PD7
CMU_CLK1
0: PA1
4: PF3
1: PD8
5: PB11
Clock Management Unit, clock output number 1.
2: PE12
CMU_CLK2
0: PA0
4: PA3
1: PA3
5: PD10
Clock Management Unit, clock output number 2.
2: PD6
CMU_CLKI0
DBG_SWCLKTCK
DBG_SWDIOTMS
0: PD4
4: PE1
1: PA3
5: PD10
2: PB8
6: PE12
3: PB13
7: PB11
0: PF0
Clock Management Unit, clock input number 0.
Debug-interface Serial Wire clock input and JTAG Test Clock.
Note that this function is enabled to the pin out of reset, and has a built-in pull down.
0: PF1
Debug-interface Serial Wire data input / output and JTAG Test Mode Select.
Note that this function is enabled to the pin out of reset, and has a built-in pull up.
0: PF2
DBG_SWO
1: PC15
2: PD1
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must be enabled by software to be
used.
3: PD2
0: PF5
DBG_TDI
Debug-interface JTAG Test Data In.
Note that this function becomes available after the first valid JTAG command is received, and has a built-in pull up when JTAG is active.
0: PF2
DBG_TDO
silabs.com | Building a more connected world.
Debug-interface JTAG Test Data Out.
Note that this function becomes available after the first valid JTAG command is received.
Rev. 1.0 | 179
EFM32GG12 Family Data Sheet
Pin Definitions
Alternate
Functionality
LOCATION
0-3
4-7
Description
0: PA12
EBI_A00
1: PB9
External Bus Interface (EBI) address output pin 00.
3: PC5
0: PA13
EBI_A01
1: PB10
External Bus Interface (EBI) address output pin 01.
3: PA7
0: PA14
EBI_A02
1: PB11
External Bus Interface (EBI) address output pin 02.
3: PA8
0: PB9
EBI_A03
1: PB12
External Bus Interface (EBI) address output pin 03.
3: PA9
0: PB10
EBI_A04
1: PD0
External Bus Interface (EBI) address output pin 04.
3: PA10
0: PC6
EBI_A05
1: PD1
External Bus Interface (EBI) address output pin 05.
3: PA11
0: PC7
EBI_A06
1: PD2
External Bus Interface (EBI) address output pin 06.
3: PA12
0: PE0
EBI_A07
1: PD3
External Bus Interface (EBI) address output pin 07.
3: PA13
0: PE1
EBI_A08
1: PD4
External Bus Interface (EBI) address output pin 08.
3: PA14
0: PE2
EBI_A09
1: PD5
External Bus Interface (EBI) address output pin 09.
3: PB9
0: PE3
EBI_A10
1: PD6
External Bus Interface (EBI) address output pin 10.
3: PB10
0: PE4
EBI_A11
1: PD7
External Bus Interface (EBI) address output pin 11.
3: PB11
silabs.com | Building a more connected world.
Rev. 1.0 | 180
EFM32GG12 Family Data Sheet
Pin Definitions
Alternate
Functionality
LOCATION
0-3
4-7
Description
0: PE5
EBI_A12
1: PD8
External Bus Interface (EBI) address output pin 12.
3: PB12
0: PE6
EBI_A13
1: PC7
External Bus Interface (EBI) address output pin 13.
3: PD0
0: PE7
EBI_A14
1: PE2
External Bus Interface (EBI) address output pin 14.
3: PD1
0: PC8
EBI_A15
1: PE3
External Bus Interface (EBI) address output pin 15.
3: PD2
0: PB0
EBI_A16
1: PE4
External Bus Interface (EBI) address output pin 16.
3: PD3
0: PB1
EBI_A17
1: PE5
External Bus Interface (EBI) address output pin 17.
3: PD4
0: PB2
EBI_A18
1: PE6
External Bus Interface (EBI) address output pin 18.
3: PD5
0: PB3
EBI_A19
1: PE7
External Bus Interface (EBI) address output pin 19.
3: PD6
0: PB4
EBI_A20
1: PC8
External Bus Interface (EBI) address output pin 20.
3: PD7
0: PB5
EBI_A21
1: PC9
External Bus Interface (EBI) address output pin 21.
3: PC7
0: PB6
EBI_A22
1: PC10
External Bus Interface (EBI) address output pin 22.
3: PE4
0: PC0
EBI_A23
1: PC11
External Bus Interface (EBI) address output pin 23.
3: PE5
silabs.com | Building a more connected world.
Rev. 1.0 | 181
EFM32GG12 Family Data Sheet
Pin Definitions
Alternate
Functionality
LOCATION
0-3
4-7
Description
0: PC1
EBI_A24
1: PF0
External Bus Interface (EBI) address output pin 24.
3: PE6
0: PC2
EBI_A25
1: PF1
External Bus Interface (EBI) address output pin 25.
3: PE7
0: PC4
EBI_A26
1: PF2
External Bus Interface (EBI) address output pin 26.
3: PC8
0: PD2
EBI_A27
1: PF5
External Bus Interface (EBI) address output pin 27.
3: PC9
EBI_AD00
EBI_AD01
EBI_AD02
EBI_AD03
EBI_AD04
EBI_AD05
EBI_AD06
EBI_AD07
EBI_AD08
EBI_AD09
EBI_AD10
EBI_AD11
0: PE8
1: PB0
0: PE9
1: PB1
0: PE10
1: PB2
0: PE11
1: PB3
0: PE12
1: PB4
0: PE13
1: PB5
0: PE14
1: PB6
0: PE15
1: PC0
0: PA15
1: PC1
0: PA0
1: PC2
0: PA1
1: PC3
0: PA2
1: PC4
silabs.com | Building a more connected world.
External Bus Interface (EBI) address and data input / output pin 00.
External Bus Interface (EBI) address and data input / output pin 01.
External Bus Interface (EBI) address and data input / output pin 02.
External Bus Interface (EBI) address and data input / output pin 03.
External Bus Interface (EBI) address and data input / output pin 04.
External Bus Interface (EBI) address and data input / output pin 05.
External Bus Interface (EBI) address and data input / output pin 06.
External Bus Interface (EBI) address and data input / output pin 07.
External Bus Interface (EBI) address and data input / output pin 08.
External Bus Interface (EBI) address and data input / output pin 09.
External Bus Interface (EBI) address and data input / output pin 10.
External Bus Interface (EBI) address and data input / output pin 11.
Rev. 1.0 | 182
EFM32GG12 Family Data Sheet
Pin Definitions
Alternate
Functionality
EBI_AD12
EBI_AD13
EBI_AD14
EBI_AD15
EBI_ALE
LOCATION
0-3
4-7
0: PA3
Description
External Bus Interface (EBI) address and data input / output pin 12.
1: PC5
0: PA4
External Bus Interface (EBI) address and data input / output pin 13.
1: PA7
0: PA5
External Bus Interface (EBI) address and data input / output pin 14.
1: PA8
0: PA6
External Bus Interface (EBI) address and data input / output pin 15.
1: PA9
0: PF3
4: PC11
1: PB9
5: PC11
2: PC4
External Bus Interface (EBI) Address Latch Enable output.
3: PB5
EBI_ARDY
0: PF2
4: PC13
1: PD13
5: PF10
2: PB15
External Bus Interface (EBI) Hardware Ready Control input.
3: PB4
EBI_BL0
0: PF6
4: PF6
1: PF8
5: PF6
2: PB10
External Bus Interface (EBI) Byte Lane/Enable pin 0.
3: PC1
EBI_BL1
0: PF7
4: PF7
1: PF9
5: PF7
2: PB11
External Bus Interface (EBI) Byte Lane/Enable pin 1.
3: PC3
0: PD9
EBI_CS0
4: PE8
1: PA10
External Bus Interface (EBI) Chip Select output 0.
2: PC0
3: PB0
0: PD10
EBI_CS1
4: PE9
1: PA11
External Bus Interface (EBI) Chip Select output 1.
2: PC1
3: PB1
0: PD11
EBI_CS2
4: PE10
1: PA12
2: PC2
External Bus Interface (EBI) Chip Select output 2.
3: PB2
silabs.com | Building a more connected world.
Rev. 1.0 | 183
EFM32GG12 Family Data Sheet
Pin Definitions
Alternate
Functionality
EBI_CS3
LOCATION
0-3
4-7
0: PD12
4: PE11
1: PB15
Description
External Bus Interface (EBI) Chip Select output 3.
2: PC3
3: PB3
0: PA7
EBI_CSTFT
1: PF6
External Bus Interface (EBI) Chip Select output TFT.
3: PA0
0: PA8
EBI_DCLK
1: PF7
External Bus Interface (EBI) TFT Dot Clock pin.
3: PA1
0: PA9
EBI_DTEN
1: PD9
External Bus Interface (EBI) TFT Data Enable pin.
3: PA2
0: PA11
EBI_HSNC
1: PD11
External Bus Interface (EBI) TFT Horizontal Synchronization pin.
3: PA4
EBI_NANDREn
0: PC3
4: PC15
1: PD15
5: PF12
2: PB9
External Bus Interface (EBI) NAND Read Enable output.
3: PC4
EBI_NANDWEn
0: PC5
4: PC14
1: PD14
5: PF11
2: PA13
External Bus Interface (EBI) NAND Write Enable output.
3: PC2
EBI_REn
0: PF5
4: PF9
1: PA14
5: PF5
2: PA12
External Bus Interface (EBI) Read Enable output.
3: PC0
0: PA10
EBI_VSNC
1: PD10
External Bus Interface (EBI) TFT Vertical Synchronization pin.
3: PA3
EBI_WEn
0: PF4
4: PF8
1: PA13
5: PF4
2: PC5
External Bus Interface (EBI) Write Enable output.
3: PB6
silabs.com | Building a more connected world.
Rev. 1.0 | 184
EFM32GG12 Family Data Sheet
Pin Definitions
Alternate
Functionality
LOCATION
0-3
0: PD7
ETM_TCLK
4-7
Description
4: PE11
1: PF8
Embedded Trace Module ETM clock .
2: PC6
3: PA6
0: PD6
ETM_TD0
4: PE12
1: PF9
Embedded Trace Module ETM data 0.
2: PC7
3: PA2
0: PD3
ETM_TD1
4: PE13
1: PD13
Embedded Trace Module ETM data 1.
2: PD3
3: PA3
0: PD4
ETM_TD2
4: PE14
1: PB15
Embedded Trace Module ETM data 2.
2: PD4
3: PA4
0: PD5
ETM_TD3
4: PE15
1: PF3
Embedded Trace Module ETM data 3.
2: PD5
3: PA5
GPIO_EM4WU0
0: PA0
Pin can be used to wake the system up from EM4
GPIO_EM4WU1
0: PA6
Pin can be used to wake the system up from EM4
GPIO_EM4WU2
0: PC9
Pin can be used to wake the system up from EM4
GPIO_EM4WU3
0: PF1
Pin can be used to wake the system up from EM4
GPIO_EM4WU4
0: PF2
Pin can be used to wake the system up from EM4
GPIO_EM4WU5
0: PE13
Pin can be used to wake the system up from EM4
GPIO_EM4WU6
0: PC4
Pin can be used to wake the system up from EM4
GPIO_EM4WU7
0: PB11
Pin can be used to wake the system up from EM4
GPIO_EM4WU8
0: PF8
Pin can be used to wake the system up from EM4
GPIO_EM4WU9
0: PE10
Pin can be used to wake the system up from EM4
HFXTAL_N
0: PB14
High Frequency Crystal negative pin. Also used as external optional clock input pin.
HFXTAL_P
0: PB13
High Frequency Crystal positive pin.
I2C0_SCL
0: PA1
4: PC1
1: PD7
5: PF1
2: PC7
6: PE13
3: PD15
7: PE5
silabs.com | Building a more connected world.
I2C0 Serial Clock Line input / output.
Rev. 1.0 | 185
EFM32GG12 Family Data Sheet
Pin Definitions
Alternate
Functionality
I2C0_SDA
I2C1_SCL
LOCATION
0-3
4-7
0: PA0
4: PC0
1: PD6
5: PF0
2: PC6
6: PE12
3: PD14
7: PE4
0: PC5
4: PF2
1: PB12
Description
I2C0 Serial Data input / output.
I2C1 Serial Clock Line input / output.
2: PE1
3: PD5
0: PC4
I2C1_SDA
4: PC11
1: PB11
2: PE0
I2C1 Serial Data input / output.
3: PD4
IDAC0_OUT
0: PB11
IDAC0 output.
0: PA14
LCD external supply bypass in step down or charge pump mode. If using the LCD in
step-down or charge pump mode, a 1 uF (minimum) capacitor between this pin and
VSS is required.
To reduce supply ripple, a larger capcitor of approximately 1000 times the total LCD
segment capacitance may be used.
LCD_BEXT
If using the LCD with the internal supply source, this pin may be left unconnected or
used as a GPIO.
LCD_COM0
0: PE4
LCD driver common line number 0.
LCD_COM1
0: PE5
LCD driver common line number 1.
LCD_COM2
0: PE6
LCD driver common line number 2.
LCD_COM3
0: PE7
LCD driver common line number 3.
LCD_SEG0
0: PF2
LCD segment line 0.
LCD_SEG1
0: PF3
LCD segment line 1.
LCD_SEG2
0: PF4
LCD segment line 2.
LCD_SEG3
0: PF5
LCD segment line 3.
LCD_SEG4
0: PE8
LCD segment line 4.
LCD_SEG5
0: PE9
LCD segment line 5.
LCD_SEG6
0: PE10
LCD segment line 6.
LCD_SEG7
0: PE11
LCD segment line 7.
LCD_SEG8
0: PE12
LCD segment line 8.
LCD_SEG9
0: PE13
LCD segment line 9.
LCD_SEG10
0: PE14
LCD segment line 10.
LCD_SEG11
0: PE15
LCD segment line 11.
LCD_SEG12
0: PA15
LCD segment line 12.
silabs.com | Building a more connected world.
Rev. 1.0 | 186
EFM32GG12 Family Data Sheet
Pin Definitions
Alternate
Functionality
LOCATION
0-3
4-7
Description
LCD_SEG13
0: PA0
LCD segment line 13.
LCD_SEG14
0: PA1
LCD segment line 14.
LCD_SEG15
0: PA2
LCD segment line 15.
LCD_SEG16
0: PA3
LCD segment line 16.
LCD_SEG17
0: PA4
LCD segment line 17.
LCD_SEG18
0: PA5
LCD segment line 18.
LCD_SEG19
0: PA6
LCD segment line 19.
LCD_SEG20 /
LCD_COM4
0: PB3
LCD_SEG21 /
LCD_COM5
0: PB4
LCD_SEG22 /
LCD_COM6
0: PB5
LCD_SEG23 /
LCD_COM7
0: PB6
LCD_SEG24
0: PF6
LCD segment line 24.
LCD_SEG25
0: PF7
LCD segment line 25.
LCD_SEG26
0: PF8
LCD segment line 26.
LCD_SEG27
0: PF9
LCD segment line 27.
LCD_SEG28
0: PD9
LCD segment line 28.
LCD_SEG29
0: PD10
LCD segment line 29.
LCD_SEG30
0: PD11
LCD segment line 30.
LCD_SEG31
0: PD12
LCD segment line 31.
LCD_SEG32
0: PB0
LCD segment line 32.
LCD_SEG33
0: PB1
LCD segment line 33.
LCD_SEG34
0: PB2
LCD segment line 34.
LCD_SEG35
0: PA7
LCD segment line 35.
LCD_SEG36
0: PA8
LCD segment line 36.
LCD_SEG37
0: PA9
LCD segment line 37.
LCD_SEG38
0: PA10
LCD segment line 38.
LCD_SEG39
0: PA11
LCD segment line 39.
LES_ALTEX0
0: PD6
LESENSE alternate excite output 0.
LES_ALTEX1
0: PD7
LESENSE alternate excite output 1.
LES_ALTEX2
0: PA3
LESENSE alternate excite output 2.
LES_ALTEX3
0: PA4
LESENSE alternate excite output 3.
LES_ALTEX4
0: PA5
LESENSE alternate excite output 4.
LES_ALTEX5
0: PE11
LESENSE alternate excite output 5.
LES_ALTEX6
0: PE12
LESENSE alternate excite output 6.
silabs.com | Building a more connected world.
LCD segment line 20. This pin may also be used as LCD COM line 4
LCD segment line 21. This pin may also be used as LCD COM line 5
LCD segment line 22. This pin may also be used as LCD COM line 6
LCD segment line 23. This pin may also be used as LCD COM line 7
Rev. 1.0 | 187
EFM32GG12 Family Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0-3
LES_ALTEX7
0: PE13
LESENSE alternate excite output 7.
LES_CH0
0: PC0
LESENSE channel 0.
LES_CH1
0: PC1
LESENSE channel 1.
LES_CH2
0: PC2
LESENSE channel 2.
LES_CH3
0: PC3
LESENSE channel 3.
LES_CH4
0: PC4
LESENSE channel 4.
LES_CH5
0: PC5
LESENSE channel 5.
LES_CH6
0: PC6
LESENSE channel 6.
LES_CH7
0: PC7
LESENSE channel 7.
LES_CH8
0: PC8
LESENSE channel 8.
LES_CH9
0: PC9
LESENSE channel 9.
LES_CH10
0: PC10
LESENSE channel 10.
LES_CH11
0: PC11
LESENSE channel 11.
LES_CH12
0: PC12
LESENSE channel 12.
LES_CH13
0: PC13
LESENSE channel 13.
LES_CH14
0: PC14
LESENSE channel 14.
LES_CH15
0: PC15
LESENSE channel 15.
LETIM0_OUT0
LETIM0_OUT1
LETIM1_OUT0
4-7
0: PD6
4: PE12
1: PB11
5: PC14
2: PF0
6: PA8
3: PC4
7: PB9
0: PD7
4: PE13
1: PB12
5: PC15
2: PF1
6: PA9
3: PC5
7: PB10
0: PA7
4: PB5
1: PA11
5: PB2
2: PA12
Description
Low Energy Timer LETIM0, output channel 0.
Low Energy Timer LETIM0, output channel 1.
Low Energy Timer LETIM1, output channel 0.
3: PC2
LETIM1_OUT1
0: PA6
4: PB6
1: PA13
5: PB1
2: PA14
Low Energy Timer LETIM1, output channel 1.
3: PC3
silabs.com | Building a more connected world.
Rev. 1.0 | 188
EFM32GG12 Family Data Sheet
Pin Definitions
Alternate
Functionality
LEU0_RX
LOCATION
0-3
4-7
0: PD5
4: PA0
1: PB14
5: PC15
2: PE15
Description
LEUART0 Receive input.
3: PF1
LEU0_TX
0: PD4
4: PF2
1: PB13
5: PC14
2: PE14
LEUART0 Transmit output. Also used as receive input in half duplex communication.
3: PF0
0: PC7
LEU1_RX
4: PB5
1: PA6
LEUART1 Receive input.
2: PD3
3: PB1
0: PC6
LEU1_TX
4: PB4
1: PA5
LEUART1 Transmit output. Also used as receive input in half duplex communication.
2: PD2
3: PB0
0: PB8
Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin.
LFXTAL_P
0: PB7
Low Frequency Crystal (typically 32.768 kHz) positive pin.
OPA0_N
0: PC5
Operational Amplifier 0 external negative input.
OPA0_P
0: PC4
Operational Amplifier 0 external positive input.
OPA1_N
0: PD7
Operational Amplifier 1 external negative input.
OPA1_P
0: PD6
Operational Amplifier 1 external positive input.
OPA2_N
0: PD3
Operational Amplifier 2 external negative input.
OPA2_OUT
0: PD5
Operational Amplifier 2 output.
OPA2_OUTALT
0: PD0
Operational Amplifier 2 alternative output.
OPA2_P
0: PD4
Operational Amplifier 2 external positive input.
OPA3_N
0: PC7
Operational Amplifier 3 external negative input.
OPA3_OUT
0: PD1
Operational Amplifier 3 output.
OPA3_P
0: PC6
Operational Amplifier 3 external positive input.
LFXTAL_N
PCNT0_S0IN
0: PC13
4: PA0
1: PE0
5: PB0
2: PC0
6: PB5
3: PD6
7: PB12
silabs.com | Building a more connected world.
Pulse Counter PCNT0 input number 0.
Rev. 1.0 | 189
EFM32GG12 Family Data Sheet
Pin Definitions
Alternate
Functionality
PCNT0_S1IN
PCNT1_S0IN
LOCATION
0-3
4-7
0: PC14
4: PA1
1: PE1
5: PB1
2: PC1
6: PB6
3: PD7
7: PB11
0: PA5
4: PA7
1: PB3
5: PA12
2: PD15
6: PB11
Description
Pulse Counter PCNT0 input number 1.
Pulse Counter PCNT1 input number 0.
3: PC4
PCNT1_S1IN
0: PA6
4: PA8
1: PB4
5: PA13
2: PB0
6: PB12
Pulse Counter PCNT1 input number 1.
3: PC5
0: PD0
PCNT2_S0IN
4: PC12
1: PE8
Pulse Counter PCNT2 input number 0.
2: PB13
3: PF10
0: PD1
PCNT2_S1IN
4: PC13
1: PE9
Pulse Counter PCNT2 input number 1.
2: PB14
3: PF11
0: PA0
PDM_CLK
4: PD0
1: PE8
PDM Clock Output.
2: PF6
3: PB12
0: PA1
PDM_DAT0
4: PD1
1: PE9
PDM Data 0.
2: PF7
3: PB11
0: PA2
PDM_DAT1
4: PD2
1: PE10
PDM Data 1.
2: PF8
3: PB10
0: PA3
PDM_DAT2
4: PD3
1: PE11
2: PF9
PDM Data 2.
3: PB9
silabs.com | Building a more connected world.
Rev. 1.0 | 190
EFM32GG12 Family Data Sheet
Pin Definitions
Alternate
Functionality
LOCATION
0-3
0: PA4
PDM_DAT3
4-7
Description
4: PD4
1: PE12
2: PD9
PDM Data 3.
3: PA13
0: PA0
PRS_CH0
1: PF3
2: PC14
Peripheral Reflex System PRS, channel 0.
3: PF2
0: PA1
PRS_CH1
1: PF4
2: PC15
Peripheral Reflex System PRS, channel 1.
3: PE12
0: PC0
PRS_CH2
1: PF5
2: PE10
Peripheral Reflex System PRS, channel 2.
3: PE13
0: PC1
PRS_CH3
1: PE8
2: PE11
Peripheral Reflex System PRS, channel 3.
3: PA0
0: PC8
PRS_CH4
1: PB0
Peripheral Reflex System PRS, channel 4.
2: PF1
0: PC9
PRS_CH5
1: PB1
Peripheral Reflex System PRS, channel 5.
2: PD6
0: PA6
PRS_CH6
1: PB14
Peripheral Reflex System PRS, channel 6.
2: PE6
0: PB13
PRS_CH7
1: PA7
Peripheral Reflex System PRS, channel 7.
2: PE7
0: PA8
PRS_CH8
1: PA2
Peripheral Reflex System PRS, channel 8.
2: PE9
silabs.com | Building a more connected world.
Rev. 1.0 | 191
EFM32GG12 Family Data Sheet
Pin Definitions
Alternate
Functionality
LOCATION
0-3
4-7
Description
0: PA9
PRS_CH9
1: PA3
Peripheral Reflex System PRS, channel 9.
2: PB10
0: PA10
PRS_CH10
1: PC2
Peripheral Reflex System PRS, channel 10.
2: PD4
0: PA11
PRS_CH11
1: PC3
Peripheral Reflex System PRS, channel 11.
2: PD5
0: PA12
PRS_CH12
1: PB6
Peripheral Reflex System PRS, channel 12.
2: PD8
0: PA13
PRS_CH13
1: PB9
Peripheral Reflex System PRS, channel 13.
2: PE14
0: PA14
PRS_CH14
1: PC6
Peripheral Reflex System PRS, channel 14.
2: PE15
0: PA15
PRS_CH15
1: PC7
Peripheral Reflex System PRS, channel 15.
2: PF0
QSPI0_CS0
QSPI0_CS1
QSPI0_DQ0
QSPI0_DQ1
QSPI0_DQ2
QSPI0_DQ3
QSPI0_DQ4
0: PF7
1: PA0
0: PF8
1: PA1
0: PD9
1: PA2
0: PD10
1: PA3
0: PD11
1: PA4
0: PD12
1: PA5
0: PE8
1: PB3
silabs.com | Building a more connected world.
Quad SPI 0 Chip Select 0.
Quad SPI 0 Chip Select 1.
Quad SPI 0 Data 0.
Quad SPI 0 Data 1.
Quad SPI 0 Data 2.
Quad SPI 0 Data 3.
Quad SPI 0 Data 4.
Rev. 1.0 | 192
EFM32GG12 Family Data Sheet
Pin Definitions
Alternate
Functionality
QSPI0_DQ5
QSPI0_DQ6
QSPI0_DQ7
QSPI0_DQS
QSPI0_RST0
QSPI0_RST1
QSPI0_SCLK
LOCATION
0-3
4-7
0: PE9
1: PB4
0: PE10
1: PB5
0: PE11
1: PB6
0: PF9
1: PE15
0: PE14
1: PC2
0: PE15
1: PC3
0: PF6
1: PE14
Description
Quad SPI 0 Data 5.
Quad SPI 0 Data 6.
Quad SPI 0 Data 7.
Quad SPI 0 Data S.
Quad SPI 0 Reset 0.
Quad SPI 0 Reset 1.
Quad SPI 0 Serial Clock.
0: PF8
SDIO_CD
1: PC4
2: PA6
SDIO Card Detect.
3: PB10
SDIO_CLK
SDIO_CMD
SDIO_DAT0
SDIO_DAT1
SDIO_DAT2
SDIO_DAT3
SDIO_DAT4
SDIO_DAT5
SDIO_DAT6
0: PE13
1: PE14
0: PE12
1: PE15
0: PE11
1: PA0
0: PE10
1: PA1
0: PE9
1: PA2
0: PE8
1: PA3
0: PD12
1: PA4
0: PD11
1: PA5
0: PD10
1: PB3
silabs.com | Building a more connected world.
SDIO Serial Clock.
SDIO Command.
SDIO Data 0.
SDIO Data 1.
SDIO Data 2.
SDIO Data 3.
SDIO Data 4.
SDIO Data 5.
SDIO Data 6.
Rev. 1.0 | 193
EFM32GG12 Family Data Sheet
Pin Definitions
Alternate
Functionality
SDIO_DAT7
LOCATION
0-3
4-7
0: PD9
Description
SDIO Data 7.
1: PB4
0: PF9
SDIO_WP
1: PC5
SDIO Write Protect.
2: PB15
3: PB9
TIM0_CC0
TIM0_CC1
TIM0_CC2
TIM0_CDTI0
0: PA0
4: PF0
1: PF6
5: PC4
2: PD1
6: PA8
3: PB6
7: PA1
0: PA1
4: PF1
1: PF7
5: PC5
2: PD2
6: PA9
3: PC0
7: PA0
0: PA2
4: PF2
1: PF8
5: PA7
2: PD3
6: PA10
3: PC1
7: PA13
0: PA3
4: PB7
1: PC13
Timer 0 Capture Compare input / output channel 0.
Timer 0 Capture Compare input / output channel 1.
Timer 0 Capture Compare input / output channel 2.
Timer 0 Complimentary Dead Time Insertion channel 0.
2: PF3
3: PC2
0: PA4
TIM0_CDTI1
4: PB8
1: PC14
Timer 0 Complimentary Dead Time Insertion channel 1.
2: PF4
3: PC3
0: PA5
TIM0_CDTI2
4: PB11
1: PC15
Timer 0 Complimentary Dead Time Insertion channel 2.
2: PF5
3: PC4
TIM1_CC0
0: PC13
4: PD6
1: PE10
5: PF2
2: PB0
6: PF13
Timer 1 Capture Compare input / output channel 0.
3: PB7
silabs.com | Building a more connected world.
Rev. 1.0 | 194
EFM32GG12 Family Data Sheet
Pin Definitions
Alternate
Functionality
TIM1_CC1
LOCATION
0-3
4-7
0: PC14
4: PD7
1: PE11
5: PF3
2: PB1
6: PF14
Description
Timer 1 Capture Compare input / output channel 1.
3: PB8
TIM1_CC2
0: PC15
4: PC13
1: PE12
5: PF4
2: PB2
Timer 1 Capture Compare input / output channel 2.
3: PB11
TIM1_CC3
0: PC12
4: PC14
1: PE13
5: PF12
2: PB3
6: PF5
Timer 1 Capture Compare input / output channel 3.
3: PB12
TIM2_CC0
0: PA8
4: PB6
1: PA12
5: PC2
2: PC8
Timer 2 Capture Compare input / output channel 0.
3: PF2
TIM2_CC1
0: PA9
4: PC0
1: PA13
5: PC3
2: PC9
Timer 2 Capture Compare input / output channel 1.
3: PE12
TIM2_CC2
0: PA10
4: PC1
1: PA14
5: PC4
2: PC10
Timer 2 Capture Compare input / output channel 2.
3: PE13
0: PB0
TIM2_CDTI0
1: PD13
Timer 2 Complimentary Dead Time Insertion channel 0.
2: PE8
0: PB1
TIM2_CDTI1
1: PD14
Timer 2 Complimentary Dead Time Insertion channel 1.
2: PE14
0: PB2
TIM2_CDTI2
1: PD15
Timer 2 Complimentary Dead Time Insertion channel 2.
2: PE15
silabs.com | Building a more connected world.
Rev. 1.0 | 195
EFM32GG12 Family Data Sheet
Pin Definitions
Alternate
Functionality
TIM3_CC0
TIM3_CC1
TIM3_CC2
U0_CTS
LOCATION
0-3
4-7
0: PE14
4: PA0
1: PE0
5: PA3
2: PE3
6: PA6
3: PE5
7: PD15
0: PE15
4: PA1
1: PE1
5: PA4
2: PE4
6: PD13
3: PE6
7: PB15
0: PA15
4: PA2
1: PE2
5: PA5
2: PE5
6: PD14
3: PE7
7: PB0
0: PF8
4: PB7
1: PE2
5: PD5
2: PA5
Description
Timer 3 Capture Compare input / output channel 0.
Timer 3 Capture Compare input / output channel 1.
Timer 3 Capture Compare input / output channel 2.
UART0 Clear To Send hardware flow control input.
3: PC13
U0_RTS
0: PF9
4: PB8
1: PE3
5: PD6
2: PA6
UART0 Request To Send hardware flow control output.
3: PC12
U0_RX
0: PF7
4: PC5
1: PE1
5: PF2
2: PA4
6: PE4
UART0 Receive input.
3: PC15
U0_TX
0: PF6
4: PC4
1: PE0
5: PF1
2: PA3
6: PD7
UART0 Transmit output. Also used as receive input in half duplex communication.
3: PC14
0: PC14
U1_CTS
4: PC4
1: PF9
UART1 Clear To Send hardware flow control input.
2: PB11
3: PE4
0: PC15
U1_RTS
4: PC5
1: PF8
2: PB12
UART1 Request To Send hardware flow control output.
3: PE5
silabs.com | Building a more connected world.
Rev. 1.0 | 196
EFM32GG12 Family Data Sheet
Pin Definitions
Alternate
Functionality
U1_RX
LOCATION
0-3
4-7
0: PC13
4: PE13
1: PF11
Description
UART1 Receive input.
2: PB10
3: PE3
0: PC12
U1_TX
4: PE12
1: PF10
UART1 Transmit output. Also used as receive input in half duplex communication.
2: PB9
3: PE2
US0_CLK
0: PE12
4: PB13
1: PE5
5: PA12
2: PC9
USART0 clock input / output.
3: PC15
US0_CS
0: PE13
4: PB14
1: PE4
5: PA13
2: PC8
USART0 chip select input / output.
3: PC14
US0_CTS
0: PE14
4: PB6
1: PE3
5: PB11
2: PC7
USART0 Clear To Send hardware flow control input.
3: PC13
US0_RTS
0: PE15
4: PB5
1: PE2
5: PD6
2: PC6
USART0 Request To Send hardware flow control output.
3: PC12
US0_RX
0: PE11
4: PB8
1: PE6
5: PC1
2: PC10
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output (MISO).
3: PE12
US0_TX
0: PE10
4: PB7
1: PE7
5: PC0
2: PC11
USART0 Asynchronous Transmit. Also used as receive input in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input (MOSI).
3: PE13
US1_CLK
0: PB7
4: PC3
1: PD2
5: PB11
2: PF0
6: PE5
USART1 clock input / output.
3: PC15
silabs.com | Building a more connected world.
Rev. 1.0 | 197
EFM32GG12 Family Data Sheet
Pin Definitions
Alternate
Functionality
US1_CS
LOCATION
0-3
4-7
0: PB8
4: PC0
1: PD3
5: PE4
2: PF1
6: PB2
Description
USART1 chip select input / output.
3: PC14
US1_CTS
0: PB9
4: PC12
1: PD4
5: PB13
2: PF3
USART1 Clear To Send hardware flow control input.
3: PC6
US1_RTS
0: PB10
4: PC13
1: PD5
5: PB14
2: PF4
USART1 Request To Send hardware flow control output.
3: PC7
US1_RX
0: PC1
4: PC2
1: PD1
5: PA0
USART1 Asynchronous Receive.
2: PD6
6: PA2
USART1 Synchronous mode Master Input / Slave Output (MISO).
3: PF7
US1_TX
0: PC0
4: PC1
1: PD0
5: PF2
2: PD7
6: PA14
USART1 Asynchronous Transmit. Also used as receive input in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input (MOSI).
3: PF6
US2_CLK
0: PC4
4: PF8
1: PB5
5: PF2
2: PA9
USART2 clock input / output.
3: PA15
US2_CS
0: PC5
4: PF9
1: PB6
5: PF5
2: PA10
USART2 chip select input / output.
3: PB11
US2_CTS
0: PC1
4: PC12
1: PB12
5: PD6
2: PA11
USART2 Clear To Send hardware flow control input.
3: PB10
US2_RTS
0: PC0
4: PC13
1: PB15
5: PD8
2: PA12
USART2 Request To Send hardware flow control output.
3: PC14
silabs.com | Building a more connected world.
Rev. 1.0 | 198
EFM32GG12 Family Data Sheet
Pin Definitions
Alternate
Functionality
US2_RX
LOCATION
0-3
4-7
0: PC3
4: PF7
1: PB4
5: PF1
2: PA8
Description
USART2 Asynchronous Receive.
USART2 Synchronous mode Master Input / Slave Output (MISO).
3: PA14
US2_TX
0: PC2
4: PF6
1: PB3
5: PF0
2: PA7
USART2 Asynchronous Transmit. Also used as receive input in half duplex communication.
USART2 Synchronous mode Master Output / Slave Input (MOSI).
3: PA13
0: PA2
US3_CLK
1: PD7
USART3 clock input / output.
2: PD4
0: PA3
US3_CS
1: PE4
2: PC14
USART3 chip select input / output.
3: PC0
0: PA4
US3_CTS
1: PE5
USART3 Clear To Send hardware flow control input.
2: PD6
0: PA5
US3_RTS
1: PC1
2: PA14
USART3 Request To Send hardware flow control output.
3: PC15
0: PA1
US3_RX
1: PE7
2: PB7
0: PA0
US3_TX
US4_CLK
US4_CS
US4_CTS
US4_RTS
USART3 Asynchronous Receive.
USART3 Synchronous mode Master Input / Slave Output (MISO).
1: PE6
USART3 Asynchronous Transmit. Also used as receive input in half duplex communication.
2: PB3
USART3 Synchronous mode Master Output / Slave Input (MOSI).
0: PC4
1: PD11
0: PC5
1: PD12
0: PA7
1: PD13
0: PA8
1: PD14
silabs.com | Building a more connected world.
USART4 clock input / output.
USART4 chip select input / output.
USART4 Clear To Send hardware flow control input.
USART4 Request To Send hardware flow control output.
Rev. 1.0 | 199
EFM32GG12 Family Data Sheet
Pin Definitions
Alternate
Functionality
US4_RX
US4_TX
LOCATION
0-3
4-7
Description
0: PB8
USART4 Asynchronous Receive.
1: PD10
USART4 Synchronous mode Master Input / Slave Output (MISO).
0: PB7
USART4 Asynchronous Transmit. Also used as receive input in half duplex communication.
1: PD9
USART4 Synchronous mode Master Output / Slave Input (MOSI).
USB_DM
0: PF10
USB D- pin.
USB_DP
0: PF11
USB D+ pin.
USB_ID
0: PF12
USB ID pin.
0: PF5
USB_VBUSEN
1: PE4
USB 5 V VBUS enable.
2: PD0
VDAC0_EXT
0: PD6
VDAC0_OUT0 /
OPA0_OUT
0: PB11
0: PC0
VDAC0_OUT0ALT
/ OPA0_OUTALT
Digital to analog converter VDAC0 external reference input pin.
Digital to Analog Converter DAC0 output channel number 0.
4: PD0
1: PC1
Digital to Analog Converter DAC0 alternative output for channel 0.
2: PC2
3: PC3
VDAC0_OUT1 /
OPA1_OUT
0: PB12
0: PC12
VDAC0_OUT1ALT
/ OPA1_OUTALT
Digital to Analog Converter DAC0 output channel number 1.
4: PD1
1: PC13
Digital to Analog Converter DAC0 alternative output for channel 1.
2: PC14
3: PC15
WTIM0_CC0
0: PE4
4: PC15
1: PA6
5: PB0
6: PB3
Wide timer 0 Capture Compare input / output channel 0.
7: PC1
WTIM0_CC1
0: PE5
4: PF0
1: PD13
5: PB1
6: PB4
Wide timer 0 Capture Compare input / output channel 1.
7: PC2
WTIM0_CC2
0: PE6
4: PF1
1: PD14
5: PB2
6: PB5
Wide timer 0 Capture Compare input / output channel 2.
7: PC3
silabs.com | Building a more connected world.
Rev. 1.0 | 200
EFM32GG12 Family Data Sheet
Pin Definitions
Alternate
Functionality
LOCATION
0-3
0: PE10
WTIM0_CDTI0
4-7
Description
4: PD4
1: PD15
Wide timer 0 Complimentary Dead Time Insertion channel 0.
2: PA12
WTIM0_CDTI1
WTIM0_CDTI2
WTIM1_CC0
0: PE11
4: PD5
2: PA13
0: PE12
4: PD6
2: PA14
0: PB13
4: PE3
1: PD2
5: PE7
2: PD6
Wide timer 0 Complimentary Dead Time Insertion channel 1.
Wide timer 0 Complimentary Dead Time Insertion channel 2.
Wide timer 1 Capture Compare input / output channel 0.
3: PC7
0: PB14
WTIM1_CC1
4: PE4
1: PD3
Wide timer 1 Capture Compare input / output channel 1.
2: PD7
3: PE0
0: PD0
WTIM1_CC2
4: PE5
1: PD4
Wide timer 1 Capture Compare input / output channel 2.
2: PD8
3: PE1
0: PD1
WTIM1_CC3
4: PE6
1: PD5
Wide timer 1 Capture Compare input / output channel 3.
2: PC6
3: PE2
Certain alternate function locations may have non-interference priority. These locations will take precedence over any other functions
selected on that pin (i.e. another alternate function enabled to the same pin inadvertently).
Some alternate functions may also have high speed priority on certain locations. These locations ensure the fastest possible paths to
the pins for timing-critical signals.
The following table lists the alternate functions and locations with special priority.
Table 5.22. Alternate Functionality Priority
Alternate Functionality
Location
Priority
CMU_CLK2
1: PA3
5: PD10
High Speed
High Speed
CMU_CLKI0
1: PA3
5: PD10
High Speed
High Speed
PDM_CLK
0: PA0
High Speed
PDM_DAT0
0: PA1
High Speed
silabs.com | Building a more connected world.
Rev. 1.0 | 201
EFM32GG12 Family Data Sheet
Pin Definitions
Alternate Functionality
Location
Priority
PDM_DAT1
0: PA2
High Speed
PDM_DAT2
0: PA3
High Speed
PDM_DAT3
0: PA4
High Speed
QSPI0_CS0
0: PF7
High Speed
QSPI0_CS1
0: PF8
High Speed
QSPI0_DQ0
0: PD9
High Speed
QSPI0_DQ1
0: PD10
High Speed
QSPI0_DQ2
0: PD11
High Speed
QSPI0_DQ3
0: PD12
High Speed
QSPI0_DQ4
0: PE8
High Speed
QSPI0_DQ5
0: PE9
High Speed
QSPI0_DQ6
0: PE10
High Speed
QSPI0_DQ7
0: PE11
High Speed
QSPI0_DQS
0: PF9
High Speed
QSPI0_RST0
0: PE14
High Speed
QSPI0_RST1
0: PE15
High Speed
QSPI0_SCLK
0: PF6
High Speed
SDIO_CLK
0: PE13
High Speed
SDIO_CMD
0: PE12
High Speed
SDIO_DAT0
0: PE11
High Speed
SDIO_DAT1
0: PE10
High Speed
SDIO_DAT2
0: PE9
High Speed
SDIO_DAT3
0: PE8
High Speed
SDIO_DAT4
0: PD12
High Speed
SDIO_DAT5
0: PD11
High Speed
SDIO_DAT6
0: PD10
High Speed
SDIO_DAT7
0: PD9
High Speed
TIM0_CC0
3: PB6
Non-interference
TIM0_CC1
3: PC0
Non-interference
TIM0_CC2
3: PC1
Non-interference
TIM0_CDTI0
1: PC13
Non-interference
TIM0_CDTI1
1: PC14
Non-interference
TIM0_CDTI2
1: PC15
Non-interference
TIM2_CC0
0: PA8
Non-interference
TIM2_CC1
0: PA9
Non-interference
TIM2_CC2
0: PA10
Non-interference
TIM2_CDTI0
0: PB0
Non-interference
silabs.com | Building a more connected world.
Rev. 1.0 | 202
EFM32GG12 Family Data Sheet
Pin Definitions
Alternate Functionality
Location
Priority
TIM2_CDTI1
0: PB1
Non-interference
TIM2_CDTI2
0: PB2
Non-interference
US2_CLK
4: PF8
5: PF2
High Speed
High Speed
US2_CS
4: PF9
5: PF5
High Speed
High Speed
US2_RX
4: PF7
5: PF1
High Speed
High Speed
US2_TX
4: PF6
5: PF0
High Speed
High Speed
silabs.com | Building a more connected world.
Rev. 1.0 | 203
EFM32GG12 Family Data Sheet
Pin Definitions
5.22 Analog Port (APORT) Client Maps
The Analog Port (APORT) is an infrastructure used to connect chip pins with on-chip analog clients such as analog comparators, ADCs,
DACs, etc. The APORT consists of a set of shared buses, switches, and control logic needed to configurably implement the signal routing. Figure 5.20 APORT Connection Diagram on page 204 shows the APORT routing for this device family (note that available features
may vary by part number). A complete description of APORT functionality can be found in the Reference Manual.
IOVDD_1
IOVDD_0
PF0
PF1
PF2
PF3
PF4
PF12
PF13
PF14
PF5
PF7
PF6
PF8
PF9
PE9
PE8
PE11
PE10
PE12
PE13
PE14
PE15
IOVDD_0
CX
CY
AX
AY
BX
BY
CX
CY
DX
DY
PA15
ACMP0X
ACMP0Y
PA1
PA2
PA3
POS
IDAC0_OUTPAD
1X
1Y
IDAC0
ACMP2
NEG
PA4
PA5
PA6
1X
1Y
3X
3Y
2X
2Y
CSEN
ACMP0
CEXT_SENSE
NEG
ADC0X
ADC0Y
AX
AY
BX
BY
CX
CY
DX
DY
4X
4Y
POS
CEXT
POS
PB1
PB2
PB3
ADC0
NEG
OPA0_N
1Y
2Y
3Y
4Y
OUT
ADC1
POS
NEG
OUT0
IDAC0_OUTPAD
OUT0ALT
OUT0ALT
PC1
VDAC0_OUT0ALT
OUT0ALT
VDAC0_OU0ALTT
OPA1
OUT1
VDAC0_OUT0ALT
VDAC0_OUT0ALT
PC2
NEG
OPA0
OUT0ALT
PC3
OUT
0X
1X
2X
3X
4X
NEXT1
NEXT0
0Y
1Y
2Y
3Y
4Y
NEXT1
NEXT0
OUT1ALT
POS
OUT0
OUT0ALT
OUT1
OUT2
OUT3
OUT4
NEXT0
OPA1_P
1X
2X
3X
4X
OPA1_N
1Y
2Y
3Y
4Y
OUT1
OUT1ALT
OUT1
OUT2
OUT3
OUT4
NEXT1
VDAC0_OUT1ALT
PC15
PF11
ACMP1
PF10
NEG
OUT1ALT
VDAC0_OUT1ALT
PC14
0X
1X
2X
3X
4X
NEXT1
NEXT0
0Y
1Y
2Y
3Y
4Y
NEXT1
NEXT0
POS
POS
NEG
1Y
2Y
3Y
4Y
NEXT1
NEXT0
OPA0_P
1X
2X
3X
4X
EXTP
EXTN
EXTP
EXTN
PB6
PC0
0Y
1Y
2Y
3Y
4Y
NEXT3
NEXT1
0Y
1Y
2Y
3Y
4Y
NEXT3
NEXT1
PB4
PB5
0X
1X
2X
3X
4X
NEXT2
NEXT0
0X
1X
2X
3X
4X
NEXT2
NEXT0
PB0
1X
2X
3X
4X
NEXT1
NEXT0
OUT1ALT
VDAC0_OUT1ALT
OUT1ALT
VDAC0_OUT1ALT
PC12
PC11
PC10
PC9
OPA2_P
1X
2X
3X
4X
POS
OPA2_N
1Y
2Y
3Y
4Y
NEG
OUT2
OUT2ALT
OUT1
OUT2
OUT3
OUT4
NEXT2
PC8
OPA2
PE7
PE6
PE5
PE4
OUT
PE1
PE0
OPA3_P
1X
2X
3X
4X
POS
OPA3_N
1Y
2Y
3Y
4Y
NEG
OUT3
OUT3ALT
OUT1
OUT2
OUT3
OUT4
NEXT3
OPA3
OPA3_P
OPA3_N
OUT
ADC_EXTN
OPA1_N
ADC_EXTP
OPA1_P
OPA0_P
PC4
PC13
ADC0X
ADC0Y
PA0
ACMP1Y
ACMP1X
BX
BY
AX
AY
DX
DY
PC7
PC6
PD7
PD6
OPA0_N
PC5
PD5
OPA2_P
OPA2_N
OUT3
OUT1ALT
PD4
PD3
PD2
VDAC0_OUT1ALT
PD1
OUT0ALT
VDAC0_OUT0ALT
PD0
PB12
PB11
PB9
PB10
PA14
PA13
PA11
PA12
BUSACMP0X,
BUSACMP1Y
PA10
BUSADC0X
ACMP0X,
ACMP1Y
PA8
BUSAX, BUSBY, ...
ADC0X
PA9
APORTnX, APORTnY
PA7
nX, nY
AX, BY, …
VDAC0_OUT2ALT
OUT2ALT
OUT2
Figure 5.20. APORT Connection Diagram
Client maps for each analog circuit using the APORT are shown in the following tables. The maps are organized by bus, and show the
peripheral's port connection, the shared bus, and the connection from specific bus channel numbers to GPIO pins.
In general, enumerations for the pin selection field in an analog peripheral's register can be determined by finding the desired pin connection in the table and then combining the value in the Port column (APORT__), and the channel identifier (CH__). For example, if pin
silabs.com | Building a more connected world.
Rev. 1.0 | 204
silabs.com | Building a more connected world.
PE0
PE4
PE6
PE8
PE10
PE12
PE14
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSDY
PE1
PE5
PE7
PE9
PE11
PE13
PE15
PF1
PF3
PF5
PF7
PF9
PF11
PF13
BUSDX
PE1
PE5
PE7
PE9
PE11
PE13
PE15
PF1
PF3
PF5
PF7
PF9
PF11
PF13
BUSCY
PE0
PE4
PE6
PE8
PE10
PE12
PE14
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSCX
PA0
PA2
PA4
PA6
PA8
PA10
PA12
PA14
PB0
PB2
PB4
PB6
PB10
PB12
PB14
BUSBY
PA1
PA3
PA5
PA7
PA9
PA11
PA13
PA15
PB1
PB3
PB5
PB9
PB11
PA1
PA3
PA5
PA7
PA9
PA11
PA13
PA15
PB1
PB3
PB5
PB9
PB11
PB13
PB15
PB15
PB13
BUSAY
BUSBX
PA0
PA2
PA4
PA6
PA8
PA10
PA12
PA14
PB0
PB2
PB4
PB6
PB10
PB12
PB14
BUSAX
APORT4Y APORT4X APORT3Y APORT3X APORT2Y APORT2X APORT1Y APORT1X
APORT0X
Port
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
CH16
CH17
CH18
CH19
CH20
CH21
CH22
CH23
CH24
CH25
CH26
CH27
CH28
CH29
CH30
CH31
BUSACMP0Y BUSACMP0X Bus
APORT0Y
EFM32GG12 Family Data Sheet
Pin Definitions
PF7 is available on port APORT2X as CH23, the register field enumeration to connect to PF7 would be APORT2XCH23. The shared
bus used by this connection is indicated in the Bus column.
Table 5.23. ACMP0 Bus and Pin Mapping
Rev. 1.0 | 205
silabs.com | Building a more connected world.
PE0
PE4
PE6
PE8
PE10
PE12
PE14
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSDY
PE1
PE5
PE7
PE9
PE11
PE13
PE15
PF1
PF3
PF5
PF7
PF9
PF11
PF13
BUSDX
PE1
PE5
PE7
PE9
PE11
PE13
PE15
PF1
PF3
PF5
PF7
PF9
PF11
PF13
BUSCY
PE0
PE4
PE6
PE8
PE10
PE12
PE14
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSCX
PA0
PA2
PA4
PA6
PA8
PA10
PA12
PA14
PB0
PB2
PB4
PB6
PB10
PB12
PB14
BUSBY
PA1
PA3
PA5
PA7
PA9
PA11
PA13
PA15
PB1
PB3
PB5
PB9
PB11
PA1
PA3
PA5
PA7
PA9
PA11
PA13
PA15
PB1
PB3
PB5
PB9
PB11
PB13
PB15
PB15
PB13
BUSAY
BUSBX
PA0
PA2
PA4
PA6
PA8
PA10
PA12
PA14
PB0
PB2
PB4
PB6
PB10
PB12
PB14
BUSAX
APORT4Y APORT4X APORT3Y APORT3X APORT2Y APORT2X APORT1Y APORT1X
APORT0X
Port
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
CH16
CH17
CH18
CH19
CH20
CH21
CH22
CH23
CH24
CH25
CH26
CH27
CH28
CH29
CH30
CH31
BUSACMP1Y BUSACMP1X Bus
APORT0Y
EFM32GG12 Family Data Sheet
Pin Definitions
Table 5.24. ACMP1 Bus and Pin Mapping
Rev. 1.0 | 206
silabs.com | Building a more connected world.
PE0
PE4
PE6
PE8
PE10
PE12
PE14
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSDY
PE1
PE5
PE7
PE9
PE11
PE13
PE15
PF1
PF3
PF5
PF7
PF9
PF11
PF13
BUSDX
PE1
PE5
PE7
PE9
PE11
PE13
PE15
PF1
PF3
PF5
PF7
PF9
PF11
PF13
BUSCY
PE0
PE4
PE6
PE8
PE10
PE12
PE14
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSCX
PA0
PA2
PA4
PA6
PA8
PA10
PA12
PA14
PB0
PB2
PB4
PB6
PB10
PB12
PB14
BUSBY
PA1
PA3
PA5
PA7
PA9
PA11
PA13
PA15
PB1
PB3
PB5
PB9
PB11
PA1
PA3
PA5
PA7
PA9
PA11
PA13
PA15
PB1
PB3
PB5
PB9
PB11
PB13
PB15
PB15
PB13
BUSAY
BUSBX
PA0
PA2
PA4
PA6
PA8
PA10
PA12
PA14
PB0
PB2
PB4
PB6
PB10
PB12
PB14
BUSAX
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
CH16
CH17
CH18
CH19
CH20
CH21
CH22
CH23
CH24
CH25
CH26
CH27
CH28
CH29
CH30
CH31
Bus
APORT4Y APORT4X APORT3Y APORT3X APORT2Y APORT2X APORT1Y APORT1X Port
EFM32GG12 Family Data Sheet
Pin Definitions
Table 5.25. ACMP2 Bus and Pin Mapping
Rev. 1.0 | 207
silabs.com | Building a more connected world.
PE0
PE4
PE6
PE8
PE10
PE12
PE14
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSDY
PE1
PE5
PE7
PE9
PE11
PE13
PE15
PF1
PF3
PF5
PF7
PF9
PF11
PF13
BUSDX
PE1
PE5
PE7
PE9
PE11
PE13
PE15
PF1
PF3
PF5
PF7
PF9
PF11
PF13
BUSCY
PE0
PE4
PE6
PE8
PE10
PE12
PE14
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSCX
PA0
PA2
PA4
PA6
PA8
PA10
PA12
PA14
PB0
PB2
PB4
PB6
PB10
PB12
PB14
BUSBY
PA1
PA3
PA5
PA7
PA9
PA11
PA13
PA15
PB1
PB3
PB5
PB9
PB11
PA1
PA3
PA5
PA7
PA9
PA11
PA13
PA15
PB1
PB3
PB5
PB9
PB11
PB13
PB15
PB15
PB13
BUSAY
BUSBX
PA0
PA2
PA4
PA6
PA8
PA10
PA12
PA14
PB0
PB2
PB4
PB6
PB10
PB12
PB14
BUSAX
APORT4Y APORT4X APORT3Y APORT3X APORT2Y APORT2X APORT1Y APORT1X
APORT0X
Port
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
CH16
CH17
CH18
CH19
CH20
CH21
CH22
CH23
CH24
CH25
CH26
CH27
CH28
CH29
CH30
CH31
BUSADC0Y BUSADC0X Bus
APORT0Y
EFM32GG12 Family Data Sheet
Pin Definitions
Table 5.26. ADC0 Bus and Pin Mapping
Rev. 1.0 | 208
silabs.com | Building a more connected world.
PE0
PE4
PE6
PE8
PE10
PE12
PE14
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSDY
PE1
PE5
PE7
PE9
PE11
PE13
PE15
PF1
PF3
PF5
PF7
PF9
PF11
PF13
BUSDX
PE1
PE5
PE7
PE9
PE11
PE13
PE15
PF1
PF3
PF5
PF7
PF9
PF11
PF13
BUSCY
PE0
PE4
PE6
PE8
PE10
PE12
PE14
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSCX
PA0
PA2
PA4
PA6
PA8
PA10
PA12
PA14
PB0
PB2
PB4
PB6
PB10
PB12
PB14
BUSBY
PA1
PA3
PA5
PA7
PA9
PA11
PA13
PA15
PB1
PB3
PB5
PB9
PB11
PA1
PA3
PA5
PA7
PA9
PA11
PA13
PA15
PB1
PB3
PB5
PB9
PB11
PB13
PB15
PB15
PB13
BUSAY
BUSBX
PA0
PA2
PA4
PA6
PA8
PA10
PA12
PA14
PB0
PB2
PB4
PB6
PB10
PB12
PB14
BUSAX
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
CH16
CH17
CH18
CH19
CH20
CH21
CH22
CH23
CH24
CH25
CH26
CH27
CH28
CH29
CH30
CH31
Bus
APORT4Y APORT4X APORT3Y APORT3X APORT2Y APORT2X APORT1Y APORT1X Port
EFM32GG12 Family Data Sheet
Pin Definitions
Table 5.27. ADC1 Bus and Pin Mapping
Rev. 1.0 | 209
silabs.com | Building a more connected world.
PE1
PE5
PE7
PE9
PE11
PE13
PE15
PF1
PF3
PF5
PF7
PF9
PF11
PF13
BUSCY
PE0
PE4
PE6
PE8
PE10
PE12
PE14
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSCX
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
CH16
CH17
CH18
CH19
CH20
CH21
CH22
CH23
CH24
CH25
CH26
CH27
CH28
CH29
CH30
CH31
Bus
APORT1Y APORT1X Port
PE0
PE4
PE6
PE8
PE10
PE12
PE14
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSDY
PE1
PE5
PE7
PE9
PE11
PE13
PE15
PF1
PF3
PF5
PF7
PF9
PF11
PF13
BUSDX
PA0
PA2
PA4
PA6
PA8
PA10
PA12
PA14
PB0
PB2
PB4
PB6
PB10
PB12
PB14
BUSBY
PA1
PA3
PA5
PA7
PA9
PA11
PA13
PA15
PB1
PB3
PB5
PB9
PB11
PB13
PB15
BUSBX
APORT4Y APORT4X APORT2Y APORT2X
PE1
PE5
PE7
PE9
PE11
PE13
PE15
PF1
PF3
PF5
PF7
PF9
PF11
PF13
BUSCY
PE0
PE4
PE6
PE8
PE10
PE12
PE14
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSCX
PA1
PA3
PA5
PA7
PA9
PA11
PA13
PA15
PB1
PB3
PB5
PB9
PB11
PB13
PB15
BUSAY
PA0
PA2
PA4
PA6
PA8
PA10
PA12
PA14
PB0
PB2
PB4
PB6
PB10
PB12
PB14
BUSAX
APORT3Y APORT3X APORT1Y APORT1X
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
CH16
CH17
CH18
CH19
CH20
CH21
CH22
CH23
CH24
CH25
CH26
CH27
CH28
CH29
CH30
CH31
Bus
Port
EFM32GG12 Family Data Sheet
Pin Definitions
Table 5.28. CSEN Bus and Pin Mapping
CEXT
CEXT_SENSE
Table 5.29. IDAC0 Bus and Pin Mapping
Rev. 1.0 | 210
silabs.com | Building a more connected world.
PE1
PE5
PE7
PE9
PE11
PE13
PE15
PF1
PF3
PF5
PF7
PF9
PF11
PF13
BUSDX
PE0
PE4
PE6
PE8
PE10
PE12
PE14
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSCX
PA1
PA3
PA5
PA7
PA9
PA11
PA13
PA15
PB1
PB3
PB5
PB9
PB11
PB13
PB15
BUSBX
PA0
PA2
PA4
PA6
PA8
PA10
PA12
PA14
PB0
PB2
PB4
PB6
PB10
PB12
PB14
BUSAX
APORT4X APORT3X APORT2X APORT1X
PE0
PE4
PE6
PE8
PE10
PE12
PE14
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSDY
PE1
PE5
PE7
PE9
PE11
PE13
PE15
PF1
PF3
PF5
PF7
PF9
PF11
PF13
BUSCY
PA0
PA2
PA4
PA6
PA8
PA10
PA12
PA14
PB0
PB2
PB4
PB6
PB10
PB12
PB14
BUSBY
PA1
PA3
PA5
PA7
PA9
PA11
PA13
PA15
PB1
PB3
PB5
PB9
PB11
PB13
PB15
BUSAY
APORT4Y APORT3Y APORT2Y APORT1Y
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
CH16
CH17
CH18
CH19
CH20
CH21
CH22
CH23
CH24
CH25
CH26
CH27
CH28
CH29
CH30
CH31
Bus
Port
EFM32GG12 Family Data Sheet
Pin Definitions
Table 5.30. VDAC0 / OPA Bus and Pin Mapping
OPA0_N
OPA0_P
Rev. 1.0 | 211
silabs.com | Building a more connected world.
PE0
PE4
PE6
PE8
PE10
PE12
PE14
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSDY
PE1
PE5
PE7
PE9
PE11
PE13
PE15
PF1
PF3
PF5
PF7
PF9
PF11
PF13
BUSCY
PA0
PA2
PA4
PA6
PA8
PA10
PA12
PA14
PB0
PB2
PB4
PB6
PB10
PB12
PB14
BUSBY
PA1
PA3
PA5
PA7
PA9
PA11
PA13
PA15
PB1
PB3
PB5
PB9
PB11
PB13
PB15
BUSAY
APORT4Y APORT3Y APORT2Y APORT1Y
PE1
PE5
PE7
PE9
PE11
PE13
PE15
PF1
PF3
PF5
PF7
PF9
PF11
PF13
BUSDX
PE0
PE4
PE6
PE8
PE10
PE12
PE14
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSCX
PA1
PA3
PA5
PA7
PA9
PA11
PA13
PA15
PB1
PB3
PB5
PB9
PB11
PB13
PB15
BUSBX
PA0
PA2
PA4
PA6
PA8
PA10
PA12
PA14
PB0
PB2
PB4
PB6
PB10
PB12
PB14
BUSAX
APORT4X APORT3X APORT2X APORT1X
PE0
PE4
PE6
PE8
PE10
PE12
PE14
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSDY
PE1
PE5
PE7
PE9
PE11
PE13
PE15
PF1
PF3
PF5
PF7
PF9
PF11
PF13
BUSCY
PA0
PA2
PA4
PA6
PA8
PA10
PA12
PA14
PB0
PB2
PB4
PB6
PB10
PB12
PB14
BUSBY
PA1
PA3
PA5
PA7
PA9
PA11
PA13
PA15
PB1
PB3
PB5
PB9
PB11
PB13
PB15
BUSAY
APORT4Y APORT3Y APORT2Y APORT1Y
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
CH16
CH17
CH18
CH19
CH20
CH21
CH22
CH23
CH24
CH25
CH26
CH27
CH28
CH29
CH30
CH31
Bus
Port
EFM32GG12 Family Data Sheet
Pin Definitions
OPA1_N
OPA1_P
OPA2_N
Rev. 1.0 | 212
silabs.com | Building a more connected world.
PE0
PE4
PE6
PE8
PE10
PE12
PE14
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSDY
PE1
PE5
PE7
PE9
PE11
PE13
PE15
PF1
PF3
PF5
PF7
PF9
PF11
PF13
BUSCY
PA0
PA2
PA4
PA6
PA8
PA10
PA12
PA14
PB0
PB2
PB4
PB6
PB10
PB12
PB14
BUSBY
PA1
PA3
PA5
PA7
PA9
PA11
PA13
PA15
PB1
PB3
PB5
PB9
PB11
PB13
PB15
BUSAY
APORT4Y APORT3Y APORT2Y APORT1Y
PE1
PE5
PE7
PE9
PE11
PE13
PE15
PF1
PF3
PF5
PF7
PF9
PF11
PF13
BUSDX
PE0
PE4
PE6
PE8
PE10
PE12
PE14
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSCX
PA1
PA3
PA5
PA7
PA9
PA11
PA13
PA15
PB1
PB3
PB5
PB9
PB11
PB13
PB15
BUSBX
PA0
PA2
PA4
PA6
PA8
PA10
PA12
PA14
PB0
PB2
PB4
PB6
PB10
PB12
PB14
BUSAX
APORT4X APORT3X APORT2X APORT1X
PE0
PE4
PE6
PE8
PE10
PE12
PE14
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSDY
PE1
PE5
PE7
PE9
PE11
PE13
PE15
PF1
PF3
PF5
PF7
PF9
PF11
PF13
BUSCY
PA0
PA2
PA4
PA6
PA8
PA10
PA12
PA14
PB0
PB2
PB4
PB6
PB10
PB12
PB14
BUSBY
PA1
PA3
PA5
PA7
PA9
PA11
PA13
PA15
PB1
PB3
PB5
PB9
PB11
PB13
PB15
BUSAY
APORT4Y APORT3Y APORT2Y APORT1Y
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
CH16
CH17
CH18
CH19
CH20
CH21
CH22
CH23
CH24
CH25
CH26
CH27
CH28
CH29
CH30
CH31
Bus
Port
EFM32GG12 Family Data Sheet
Pin Definitions
OPA2_OUT
OPA2_P
OPA3_N
Rev. 1.0 | 213
silabs.com | Building a more connected world.
PE0
PE4
PE6
PE8
PE10
PE12
PE14
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSDY
PE1
PE5
PE7
PE9
PE11
PE13
PE15
PF1
PF3
PF5
PF7
PF9
PF11
PF13
BUSCY
PA0
PA2
PA4
PA6
PA8
PA10
PA12
PA14
PB0
PB2
PB4
PB6
PB10
PB12
PB14
BUSBY
PA1
PA3
PA5
PA7
PA9
PA11
PA13
PA15
PB1
PB3
PB5
PB9
PB11
PB13
PB15
BUSAY
APORT4Y APORT3Y APORT2Y APORT1Y
PE1
PE5
PE7
PE9
PE11
PE13
PE15
PF1
PF3
PF5
PF7
PF9
PF11
PF13
BUSDX
PE0
PE4
PE6
PE8
PE10
PE12
PE14
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSCX
PA1
PA3
PA5
PA7
PA9
PA11
PA13
PA15
PB1
PB3
PB5
PB9
PB11
PB13
PB15
BUSBX
PA0
PA2
PA4
PA6
PA8
PA10
PA12
PA14
PB0
PB2
PB4
PB6
PB10
PB12
PB14
BUSAX
APORT4X APORT3X APORT2X APORT1X
PE0
PE4
PE6
PE8
PE10
PE12
PE14
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSDY
PE1
PE5
PE7
PE9
PE11
PE13
PE15
PF1
PF3
PF5
PF7
PF9
PF11
PF13
BUSCY
PA0
PA2
PA4
PA6
PA8
PA10
PA12
PA14
PB0
PB2
PB4
PB6
PB10
PB12
PB14
BUSBY
PA1
PA3
PA5
PA7
PA9
PA11
PA13
PA15
PB1
PB3
PB5
PB9
PB11
PB13
PB15
BUSAY
APORT4Y APORT3Y APORT2Y APORT1Y
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
CH16
CH17
CH18
CH19
CH20
CH21
CH22
CH23
CH24
CH25
CH26
CH27
CH28
CH29
CH30
CH31
Bus
Port
EFM32GG12 Family Data Sheet
Pin Definitions
OPA3_OUT
OPA3_P
VDAC0_OUT0 / OPA0_OUT
Rev. 1.0 | 214
silabs.com | Building a more connected world.
PE0
PE4
PE6
PE8
PE10
PE12
PE14
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSDY
PE1
PE5
PE7
PE9
PE11
PE13
PE15
PF1
PF3
PF5
PF7
PF9
PF11
PF13
BUSCY
PA0
PA2
PA4
PA6
PA8
PA10
PA12
PA14
PB0
PB2
PB4
PB6
PB10
PB12
PB14
BUSBY
PA1
PA3
PA5
PA7
PA9
PA11
PA13
PA15
PB1
PB3
PB5
PB9
PB11
PB13
PB15
BUSAY
APORT4Y APORT3Y APORT2Y APORT1Y
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
CH16
CH17
CH18
CH19
CH20
CH21
CH22
CH23
CH24
CH25
CH26
CH27
CH28
CH29
CH30
CH31
Bus
Port
EFM32GG12 Family Data Sheet
Pin Definitions
VDAC0_OUT1 / OPA1_OUT
Rev. 1.0 | 215
EFM32GG12 Family Data Sheet
BGA120 Package Specifications
6. BGA120 Package Specifications
6.1 BGA120 Package Dimensions
Figure 6.1. BGA120 Package Drawing
silabs.com | Building a more connected world.
Rev. 1.0 | 216
EFM32GG12 Family Data Sheet
BGA120 Package Specifications
Table 6.1. BGA120 Package Dimensions
Dimension
Min
Typ
Max
A
0.78
0.84
0.90
A1
0.13
0.18
0.23
A3
0.17
0.21
0.25
A2
0.45 REF
D
7.00 BSC
e
0.50 BSC
E
7.00 BSC
D1
6.00 BSC
E1
6.00 BSC
b
0.20
0.25
aaa
0.10
bbb
0.10
ddd
0.08
eee
0.15
fff
0.05
0.30
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
silabs.com | Building a more connected world.
Rev. 1.0 | 217
EFM32GG12 Family Data Sheet
BGA120 Package Specifications
6.2 BGA120 PCB Land Pattern
Figure 6.2. BGA120 PCB Land Pattern Drawing
silabs.com | Building a more connected world.
Rev. 1.0 | 218
EFM32GG12 Family Data Sheet
BGA120 Package Specifications
Table 6.2. BGA120 PCB Land Pattern Dimensions
Dimension
Min
Nom
X
0.20
C1
6.00
C2
6.00
E1
0.5
E2
0.5
Max
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
6. The stencil thickness should be 0.125 mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1.
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
silabs.com | Building a more connected world.
Rev. 1.0 | 219
EFM32GG12 Family Data Sheet
BGA120 Package Specifications
6.3 BGA120 Package Marking
EFM32
PPPPPPPPPP
TTTTTT
YYWW
Figure 6.3. BGA120 Package Marking
The package marking consists of:
• PPPPPPPPPP – The part number designation.
• TTTTTT – A trace or manufacturing code. The first letter is the device revision.
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
silabs.com | Building a more connected world.
Rev. 1.0 | 220
EFM32GG12 Family Data Sheet
BGA112 Package Specifications
7. BGA112 Package Specifications
7.1 BGA112 Package Dimensions
Figure 7.1. BGA112 Package Drawing
silabs.com | Building a more connected world.
Rev. 1.0 | 221
EFM32GG12 Family Data Sheet
BGA112 Package Specifications
Table 7.1. BGA112 Package Dimensions
Dimension
Min
Typ
Max
A
-
-
1.30
A1
0.55
0.60
0.65
A2
0.21 BSC
A3
0.30
0.35
0.40
d
0.43
0.48
0.53
D
10.00 BSC
D1
8.00 BSC
E
10.00 BSC
E1
8.00 BSC
e1
0.80 BSC
e2
0.80 BSC
L1
1.00 REF
L2
1.00 REF
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
silabs.com | Building a more connected world.
Rev. 1.0 | 222
EFM32GG12 Family Data Sheet
BGA112 Package Specifications
7.2 BGA112 PCB Land Pattern
Figure 7.2. BGA112 PCB Land Pattern Drawing
silabs.com | Building a more connected world.
Rev. 1.0 | 223
EFM32GG12 Family Data Sheet
BGA112 Package Specifications
Table 7.2. BGA112 PCB Land Pattern Dimensions
Dimension
Min
Nom
X
0.45
C1
8.00
C2
8.00
E1
0.8
E2
0.8
Max
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
6. The stencil thickness should be 0.125 mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1.
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
silabs.com | Building a more connected world.
Rev. 1.0 | 224
EFM32GG12 Family Data Sheet
BGA112 Package Specifications
7.3 BGA112 Package Marking
EFM32
PPPPPPPPPP
TTTTTT
YYWW
Figure 7.3. BGA112 Package Marking
The package marking consists of:
• PPPPPPPPPP – The part number designation.
• TTTTTT – A trace or manufacturing code. The first letter is the device revision.
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
silabs.com | Building a more connected world.
Rev. 1.0 | 225
EFM32GG12 Family Data Sheet
TQFP100 Package Specifications
8. TQFP100 Package Specifications
8.1 TQFP100 Package Dimensions
Figure 8.1. TQFP100 Package Drawing
silabs.com | Building a more connected world.
Rev. 1.0 | 226
EFM32GG12 Family Data Sheet
TQFP100 Package Specifications
Table 8.1. TQFP100 Package Dimensions
Dimension
Min
Typ
Max
A
-
-
1.20
A1
0.05
-
0.15
A2
0.95
1.00
1.05
b
0.17
0.22
0.27
b1
0.17
0.20
0.23
c
0.09
-
0.20
c1
0.09
-
0.16
D
16.0 BSC
E
16.0 BSC
D1
14.0 BSC
E1
14.0 BSC
e
0.50 BSC
L1
1 REF
L
0.45
0.60
0.75
ϴ
0
3.5
7
ϴ1
0
-
-
ϴ2
11
12
13
ϴ3
11
12
13
R1
0.08
-
-
R2
0.08
-
0.2
S
0.2
-
-
aaa
0.2
bbb
0.2
ccc
0.08
ddd
0.08
eee
0.05
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
silabs.com | Building a more connected world.
Rev. 1.0 | 227
EFM32GG12 Family Data Sheet
TQFP100 Package Specifications
8.2 TQFP100 PCB Land Pattern
Figure 8.2. TQFP100 PCB Land Pattern Drawing
silabs.com | Building a more connected world.
Rev. 1.0 | 228
EFM32GG12 Family Data Sheet
TQFP100 Package Specifications
Table 8.2. TQFP100 PCB Land Pattern Dimensions
Dimension
Min
Nom
C1
15.4
C2
15.4
E
0.50 BSC
X
0.30
Y
1.50
Max
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A No-Clean, Type-3 solder paste is recommended.
8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
8.3 TQFP100 Package Marking
EFM32
PPPPPPPPPP
TTTTTT
YYWW
Figure 8.3. TQFP100 Package Marking
The package marking consists of:
• PPPPPPPPPP – The part number designation.
• TTTTTT – A trace or manufacturing code. The first letter is the device revision.
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
silabs.com | Building a more connected world.
Rev. 1.0 | 229
EFM32GG12 Family Data Sheet
TQFP64 Package Specifications
9. TQFP64 Package Specifications
9.1 TQFP64 Package Dimensions
Figure 9.1. TQFP64 Package Drawing
silabs.com | Building a more connected world.
Rev. 1.0 | 230
EFM32GG12 Family Data Sheet
TQFP64 Package Specifications
Table 9.1. TQFP64 Package Dimensions
Dimension
Min
Typ
Max
A
—
1.15
1.20
A1
0.05
—
0.15
A2
0.95
1.00
1.05
b
0.17
0.22
0.27
b1
0.17
0.20
0.23
c
0.09
—
0.20
c1
0.09
—
0.16
D
12.00 BSC
D1
10.00 BSC
e
0.50 BSC
E
12.00 BSC
E1
10.00 BSC
L
0.45
L1
0.60
0.75
1.00 REF
R1
0.08
—
—
R2
0.08
—
0.20
S
0.20
—
—
θ
0
3.5
7
ϴ1
0
—
0.10
ϴ2
11
12
13
ϴ3
11
12
13
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
silabs.com | Building a more connected world.
Rev. 1.0 | 231
EFM32GG12 Family Data Sheet
TQFP64 Package Specifications
9.2 TQFP64 PCB Land Pattern
Figure 9.2. TQFP64 PCB Land Pattern Drawing
silabs.com | Building a more connected world.
Rev. 1.0 | 232
EFM32GG12 Family Data Sheet
TQFP64 Package Specifications
Table 9.2. TQFP64 PCB Land Pattern Dimensions
Dimension
Min
Max
C1
11.30
11.40
C2
11.30
11.40
E
0.50 BSC
X
0.20
0.30
Y
1.40
1.50
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size can be 1:1 for all pads.
7. A No-Clean, Type-3 solder paste is recommended.
8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
9.3 TQFP64 Package Marking
EFM32
PPPPPPPPPP
TTTTTT
YYWW
Figure 9.3. TQFP64 Package Marking
The package marking consists of:
• PPPPPPPPPP – The part number designation.
• TTTTTT – A trace or manufacturing code. The first letter is the device revision.
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
silabs.com | Building a more connected world.
Rev. 1.0 | 233
EFM32GG12 Family Data Sheet
QFN64 Package Specifications
10. QFN64 Package Specifications
10.1 QFN64 Package Dimensions
Figure 10.1. QFN64 Package Drawing
silabs.com | Building a more connected world.
Rev. 1.0 | 234
EFM32GG12 Family Data Sheet
QFN64 Package Specifications
Table 10.1. QFN64 Package Dimensions
Dimension
Min
Typ
Max
A
0.70
0.75
0.80
A1
0.00
—
0.05
b
0.20
0.25
0.30
A3
0.203 REF
D
9.00 BSC
e
0.50 BSC
E
9.00 BSC
D2
7.10
7.20
7.30
E2
7.10
7.20
7.30
L
0.40
0.45
0.50
L1
0.00
—
0.10
aaa
0.10
bbb
0.10
ccc
0.10
ddd
0.05
eee
0.08
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
silabs.com | Building a more connected world.
Rev. 1.0 | 235
EFM32GG12 Family Data Sheet
QFN64 Package Specifications
10.2 QFN64 PCB Land Pattern
Figure 10.2. QFN64 PCB Land Pattern Drawing
silabs.com | Building a more connected world.
Rev. 1.0 | 236
EFM32GG12 Family Data Sheet
QFN64 Package Specifications
Table 10.2. QFN64 PCB Land Pattern Dimensions
Dimension
Typ
C1
8.90
C2
8.90
E
0.50
X1
0.30
Y1
0.85
X2
7.30
Y2
7.30
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05mm.
4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
6. The stencil thickness should be 0.125 mm (5 mils).
7. The ratio of stencil aperture to land pad size can be 1:1 for all pads.
8. A 3x3 array of 1.45 mm square openings on a 2.00 mm pitch can be used for the center ground pad.
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
silabs.com | Building a more connected world.
Rev. 1.0 | 237
EFM32GG12 Family Data Sheet
QFN64 Package Specifications
10.3 QFN64 Package Marking
EFM32
PPPPPPPPPP
TTTTTT
YYWW
Figure 10.3. QFN64 Package Marking
The package marking consists of:
• PPPPPPPPPP – The part number designation.
• TTTTTT – A trace or manufacturing code. The first letter is the device revision.
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
silabs.com | Building a more connected world.
Rev. 1.0 | 238
EFM32GG12 Family Data Sheet
Revision History
11. Revision History
Revision 1.0
July, 2019
• 4.1 Electrical Characteristics updated with final production test limits.
• RESETn pin pullup connection to AVDD clarified in pinout tables.
• Table 5.20 GPIO Functionality Table on page 166 formatting updated for translation.
Revision 0.6
February, 2019
•
•
•
•
Updated 2. Ordering Information with new high temperature range BGA part numbers.
4.1 Electrical Characteristics updated with notes distinguishing RESETn reference (AVDD) from all other GPIO reference (IOVDD).
Added to pin description of DECOUPLE - decouple output for on-chip voltage should not be used to power external circuits.
5.20 GPIO Functionality Table: re-ordered to show pins in alphabetical order by GPIO name.
Revision 0.5
December, 2018
•
•
•
•
4.1 Electrical Characteristics updated with latest characterization data and production test limits.
4.1 Electrical Characteristics added SDIO location 1 and SDIO SPI mode timing details.
4.1 Electrical Characteristics sorted all table footnotes in order of appearance.
Table 5.21 Alternate Functionality Overview on page 178 changed vertical white space.
Revision 0.1
May, 2018
Initial release.
silabs.com | Building a more connected world.
Rev. 1.0 | 239
Simplicity Studio
One-click access to MCU and
wireless tools, documentation,
software, source code libraries &
more. Available for Windows,
Mac and Linux!
IoT Portfolio
www.silabs.com/IoT
SW/HW
Quality
Support and Community
www.silabs.com/simplicity
www.silabs.com/quality
community.silabs.com
Disclaimer
Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or
intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"
parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes
without further notice to the product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information.
Without prior notification, Silicon Labs may update product firmware during the manufacturing process for security or reliability reasons. Such changes will not alter the specifications or the
performance of the product. Silicon Labs shall have no liability for the consequences of use of the information supplied in this document. This document does not imply or expressly grant
any license to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any FDA Class III devices, applications for which FDA premarket
approval is required or Life Support Systems without the specific written consent of Silicon Labs. A "Life Support System" is any product or system intended to support or sustain life and/or
health, which, if it fails, can be reasonably expected to result in significant personal injury or death. Silicon Labs products are not designed or authorized for military applications. Silicon
Labs products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering
such weapons. Silicon Labs disclaims all express and implied warranties and shall not be responsible or liable for any injuries or damages related to use of a Silicon Labs product in such
unauthorized applications.
Trademark Information
Silicon Laboratories Inc.® , Silicon Laboratories®, Silicon Labs®, SiLabs® and the Silicon Labs logo®, Bluegiga®, Bluegiga Logo®, ClockBuilder®, CMEMS®, DSPLL®, EFM®,
EFM32®, EFR, Ember®, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZRadio®, EZRadioPRO®,
Gecko®, Gecko OS, Gecko OS Studio, ISOmodem®, Precision32®, ProSLIC®, Simplicity Studio®, SiPHY®, Telegesis, the Telegesis Logo®, USBXpress® , Zentri, the Zentri logo and Zentri
DMS, Z-Wave®, and others are trademarks or registered trademarks of Silicon Labs. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings.
Keil is a registered trademark of ARM Limited. Wi-Fi is a registered trademark of the Wi-Fi Alliance. All other products or brand names mentioned herein are trademarks of their respective
holders.
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
USA
http://www.silabs.com
工商网监
湘ICP备2023018690号
