EFM32 Giant Gecko Family
EFM32GG Data Sheet
The EFM32 Giant Gecko MCUs are the world’s most energyfriendly microcontrollers.
KEY FEATURES
The EFM32GG offers unmatched performance and ultra low power consumption in both
active and sleep modes. EFM32GG devices consume as little as 0.6 μA in Stop mode
and 180 μA/MHz in Run mode. It also features autonomous peripherals, high overall chip
and analog integration, and the performance of the industry standard 32-bit ARM CortexM3 processor, making it perfect for battery-powered systems and systems with high-performance, low-energy requirements.
• Industrial and home automation
• Alarm and security systems
• Health and fitness applications
Core / Memory
ARM CortexTM
M3 processor
Clock Management
Memory
Protection Unit
Flash Program
Memory
Debug w/ ETM
RAM Memory
DMA Controller
• Ultra low power operation
• 0.6 μA current in Stop (EM3), with
brown-out detection and RAM retention
• 45 μA/MHz in EM1
• 180 μA/MHz in Run mode (EM0)
• Fast wake-up time of 2 µs
EFM32GG applications include the following:
• Smart metering
• Water metering
• Gas metering
• ARM Cortex-M3 at 48 MHz
• Hardware cryptography (AES)
• Up to 1024 kB of Flash and 128 kB of
RAM
Energy Management
High Frequency
Crystal Oscillator
High Frequency
RC Oscillator
Voltage
Regulator
Voltage
Comparator
Auxiliary High
Freq. RC Osc.
Low Freq.
RC Oscillator
Brown-out
Detector
Power-on
Reset
Low Frequency
Crystal Oscillator
Ultra Low Freq.
RC Oscillator
Back-up Power
Domain
Security
Hardware AES
32-bit bus
Peripheral Reflex System
Serial Interfaces
I/O Ports
Timers and Triggers
USART
UART
External Bus
Interface
TFT Driver
Low Energy
UARTTM
I2C
External
Interrupts
General
Purpose I/O
Pin Reset
Pin Wakeup
USB
Timer/Counter
LESENSE
Low Energy Timer
Real Time Counter
Pulse Counter
Analog Interfaces
ADC
LCD Controller
DAC
Operational
Amplifier
Watchdog Timer
Analog
Comparator
Back-up RTC
Lowest power mode with peripheral operational:
EM0 - Active
EM1 - Sleep
silabs.com | Building a more connected world.
EM2 – Deep Sleep
EM3 - Stop
EM4 - Shutoff
Rev. 2.0
EFM32GG Data Sheet
Feature List
1. Feature List
• ARM Cortex-M3 CPU platform
• High Performance 32-bit processor @ up to 48 MHz
• DSP instruction support and floating-point unit
• Memory Protection Unit
• Flexible Energy Management System
• 20 nA @ 3 V Shutoff Mode
• 0.4 µA @ 3 V Shutoff Mode with RTC
• 0.8 µA @ 3 V Stop Mode, including Power-on Reset, Brown-out Detector, RAM and CPU retention
• 1.1 µA @ 3 V Deep Sleep Mode, including RTC with 32.768 kHz oscillator, Power-on Reset, Brown-out Detector, RAM and CPU
retention
• 80 µA/MHz @ 3 V Sleep Mode
• 219 µA/MHz @ 3 V Run Mode, with code executed from flash
• 1024/512 KB Flash
• Read-while-write support
• 128 KB RAM
• Up to 93 General Purpose I/O pins
• Configurable push-pull, open-drain, pull-up/down, input filter, drive strength
• Configurable peripheral I/O locations
• 16 asynchronous external interrupts
• Output state retention and wake-up from Shutoff Mode
• 12 Channel DMA Controller
• 12 Channel Peripheral Reflex System (PRS) for autonomous inter- peripheral signaling
• Hardware AES with 128/256-bit keys in 54/75 cycles
• Timers/Counters
• 4× 16-bit Timer/Counter
• 4×3 Compare/Capture/PWM channels
• Dead-Time Insertion on TIMER0
• 16-bit Low Energy Timer
• 1× 24-bit Real-Time Counter and 1× 32-bit Real-Time Counter
• 3× 16/8-bit Pulse Counter with asynchronous operation
• Watchdog Timer with dedicated RC oscillator @ 50 nA
• Integrated LCD Controller for up to 8×36 segments
• Voltage boost, adjustable contrast and autonomous animation
• Backup Power Domain
• RTC and retention registers in a separate power domain, available in all energy modes
• Operation from backup battery when main power drains out
• External Bus Interface for up to 4x256 MB of external memory mapped space
• TFT Controller with Direct Drive
• Communication interfaces
• Up to 3× Universal Synchronous/Asynchronous Receiver/ Transmitter
• UART/SPI/SmartCard (ISO 7816)/IrDA/I2S
• 2× Universal Asynchronous Receiver/Transmitter
• 2× Low Energy UART
• Autonomous operation with DMA in Deep Sleep Mode
• 2× I2C Interface with SMBus support
• Address recognition in Stop Mode
• Universal Serial Bus (USB) with Host & OTG support
• Fully USB 2.0 compliant
• On-chip PHY and embedded 5V to 3.3V regulator
silabs.com | Building a more connected world.
Rev. 2.0 | 2
EFM32GG Data Sheet
Feature List
• Ultra low power precision analog peripherals
• 12-bit 1 Msamples/s Analog to Digital Converter
• 8 single ended channels/4 differential channels
• On-chip temperature sensor
• 12-bit 500 ksamples/s Digital to Analog Converter
• 2 single ended channels/1 differential channel
• Up to 2× Analog Comparator
• Capacitive sensing with up to 16 inputs
• 3× Operational Amplifier
• 6.1 MHz GBW, Rail-to-rail, Programmable Gain
• Supply Voltage Comparator
• Low Energy Sensor Interface (LESENSE)
• Autonomous sensor monitoring in Deep Sleep Mode
• Wide range of sensors supported, including LC sensors and capacitive buttons
• Ultra efficient Power-on Reset and Brown-Out Detector
• Debug Interface
• 2-pin Serial Wire Debug interface
• 1-pin Serial Wire Viewer
• Embedded Trace Module v3.5 (ETM)
• Pre-Programmed USB/UART Bootloader
• Temperature range -40 to 85 ºC
• Single power supply 1.98 to 3.8 V
• Packages:
• BGA112
• BGA120
• LQFP100
• TQFP64
• QFN64
• Full wafer
silabs.com | Building a more connected world.
Rev. 2.0 | 3
EFM32GG Data Sheet
Ordering Information
2. Ordering Information
The following table shows the available EFM32GG devices.
Table 2.1. Ordering Information
Flash (kB)
RAM (kB)
Max Speed
(MHz)
Supply
Voltage (V)
Temperature
(ºC)
Package
EFM32GG230F512G-E-QFN64
512
128
48
1.98 - 3.8
-40 - 85
QFN64
EFM32GG230F1024G-E-QFN64
1024
128
48
1.98 - 3.8
-40 - 85
QFN64
EFM32GG232F512G-E-QFP64
512
128
48
1.98 - 3.8
-40 - 85
TQFP64
EFM32GG232F1024G-E-QFP64
1024
128
48
1.98 - 3.8
-40 - 85
TQFP64
EFM32GG280F512G-E-QFP100
512
128
48
1.98 - 3.8
-40 - 85
LQFP100
EFM32GG280F1024G-E-QFP100
1024
128
48
1.98 - 3.8
-40 - 85
LQFP100
EFM32GG290F512G-E-BGA112
512
128
48
1.98 - 3.8
-40 - 85
BGA112
EFM32GG290F1024G-E-BGA112
1024
128
48
1.98 - 3.8
-40 - 85
BGA112
EFM32GG295F512G-E-BGA120
512
128
48
1.98 - 3.8
-40 - 85
BGA120
EFM32GG295F1024G-E-BGA120
1024
128
48
1.98 - 3.8
-40 - 85
BGA120
EFM32GG330F512G-E-QFN64
512
128
48
1.98 - 3.8
-40 - 85
QFN64
EFM32GG330F1024G-E-QFN64
1024
128
48
1.98 - 3.8
-40 - 85
QFN64
EFM32GG332F512G-E-QFP64
512
128
48
1.98 - 3.8
-40 - 85
TQFP64
EFM32GG332F1024G-E-QFP64
1024
128
48
1.98 - 3.8
-40 - 85
TQFP64
EFM32GG380F512G-E-QFP100
512
128
48
1.98 - 3.8
-40 - 85
LQFP100
EFM32GG380F1024G-E-QFP100
1024
128
48
1.98 - 3.8
-40 - 85
LQFP100
EFM32GG390F512G-E-BGA112
512
128
48
1.98 - 3.8
-40 - 85
BGA112
EFM32GG390F1024G-E-BGA112
1024
128
48
1.98 - 3.8
-40 - 85
BGA112
EFM32GG395F512G-E-BGA120
512
128
48
1.98 - 3.8
-40 - 85
BGA120
EFM32GG395F1024G-E-BGA120
1024
128
48
1.98 - 3.8
-40 - 85
BGA120
EFM32GG840F512G-E-QFN64
512
128
48
1.98 - 3.8
-40 - 85
QFN64
EFM32GG840F1024G-E-QFN64
1024
128
48
1.98 - 3.8
-40 - 85
QFN64
EFM32GG842F512G-E-QFP64
512
128
48
1.98 - 3.8
-40 - 85
TQFP64
EFM32GG842F1024G-E-QFP64
1024
128
48
1.98 - 3.8
-40 - 85
TQFP64
EFM32GG880F512G-E-QFP100
512
128
48
1.98 - 3.8
-40 - 85
LQFP100
EFM32GG880F1024G-E-QFP100
1024
128
48
1.98 - 3.8
-40 - 85
LQFP100
EFM32GG890F512G-E-BGA112
512
128
48
1.98 - 3.8
-40 - 85
BGA112
EFM32GG890F1024G-E-BGA112
1024
128
48
1.98 - 3.8
-40 - 85
BGA112
EFM32GG895F512G-E-BGA120
512
128
48
1.98 - 3.8
-40 - 85
BGA120
EFM32GG895F1024G-E-BGA120
1024
128
48
1.98 - 3.8
-40 - 85
BGA120
EFM32GG900F512G-E-D1I
512
128
48
1.9 -3.8
-40 - 85
Wafer
EFM32GG900F1024G-E-D1I
1024
128
48
1.98 - 3.8
-40 - 85
Wafer
Ordering Code
silabs.com | Building a more connected world.
Rev. 2.0 | 4
EFM32GG Data Sheet
Ordering Information
Flash (kB)
RAM (kB)
Max Speed
(MHz)
Supply
Voltage (V)
Temperature
(ºC)
Package
EFM32GG940F512G-E-QFN64
512
128
48
1.98 - 3.8
-40 - 85
QFN64
EFM32GG940F1024G-E-QFN64
1024
128
48
1.98 - 3.8
-40 - 85
QFN64
EFM32GG942F512G-E-QFP64
512
128
48
1.98 - 3.8
-40 - 85
TQFP64
EFM32GG942F1024G-E-QFP64
1024
128
48
1.98 - 3.8
-40 - 85
TQFP64
EFM32GG980F512G-E-QFP100
512
128
48
1.98 - 3.8
-40 - 85
LQFP100
EFM32GG980F1024G-E-QFP100
1024
128
48
1.98 - 3.8
-40 - 85
LQFP100
EFM32GG990F512G-E-BGA112
512
128
48
1.98 - 3.8
-40 - 85
BGA112
EFM32GG990F1024G-E-BGA112
1024
128
48
1.98 - 3.8
-40 - 85
BGA112
EFM32GG995F512G-E-BGA120
512
128
48
1.98 - 3.8
-40 - 85
BGA120
EFM32GG995F1024G-E-BGA120
1024
128
48
1.98 - 3.8
-40 - 85
BGA120
Ordering Code
EFM32 GG 995 F 256 G – E – BGA 120 R
Tape and Reel (Optional)
Pin Count
Package
Revision
Temperature Grade – G (-40 to +85 °C)
Memory Size in kB
Memory Type (Flash)
Feature Set Code
Giant Gecko
Energy Friendly Microcontroller 32-bit
Figure 2.1. Ordering Code Decoder
Adding the suffix 'R' to the part number (e.g. EFM32GGF256G-E-BGA120R) denotes tape and reel.
Visit http://www.silabs.com for information on global distributors and representatives.
silabs.com | Building a more connected world.
Rev. 2.0 | 5
Table of Contents
1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3. System Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
3.1 System Introduction . . . . . . . . . . . . . . . . . . .
3.1.1 ARM Cortex-M3 Core . . . . . . . . . . . . . . . . .
3.1.2 Debug Interface (DBG) . . . . . . . . . . . . . . . . .
3.1.3 Memory System Controller (MSC) . . . . . . . . . . . . .
3.1.4 Direct Memory Access Controller (DMA) . . . . . . . . . . .
3.1.5 Reset Management Unit (RMU) . . . . . . . . . . . . . .
3.1.6 Energy Management Unit (EMU) . . . . . . . . . . . . .
3.1.7 Clock Management Unit (CMU) . . . . . . . . . . . . . .
3.1.8 Watchdog (WDOG) . . . . . . . . . . . . . . . . . .
3.1.9 Peripheral Reflex System (PRS) . . . . . . . . . . . . .
3.1.10 External Bus Interface (EBI) . . . . . . . . . . . . . .
3.1.11 TFT Direct Drive . . . . . . . . . . . . . . . . . .
3.1.12 Universal Serial Bus Controller (USB) . . . . . . . . . . .
3.1.13 Inter-Integrated Circuit Interface (I2C) . . . . . . . . . . .
3.1.14 Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
3.1.15 Pre-Programmed USB/UART Bootloader . . . . . . . . . .
3.1.16 Universal Asynchronous Receiver/Transmitter (UART) . . . . .
3.1.17 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART)
3.1.18 Timer/Counter (TIMER) . . . . . . . . . . . . . . . .
3.1.19 Real Time Counter (RTC) . . . . . . . . . . . . . . .
3.1.20 Backup Real Time Counter (BURTC) . . . . . . . . . . .
3.1.21 Low Energy Timer (LETIMER) . . . . . . . . . . . . . .
3.1.22 Pulse Counter (PCNT) . . . . . . . . . . . . . . . .
3.1.23 Analog Comparator (ACMP) . . . . . . . . . . . . . .
3.1.24 Voltage Comparator (VCMP) . . . . . . . . . . . . . .
3.1.25 Analog to Digital Converter (ADC) . . . . . . . . . . . .
3.1.26 Digital to Analog Converter (DAC) . . . . . . . . . . . .
3.1.27 Operational Amplifier (OPAMP) . . . . . . . . . . . . .
3.1.28 Low Energy Sensor Interface (LESENSE) . . . . . . . . . .
3.1.29 Backup Power Domain . . . . . . . . . . . . . . . .
3.1.30 Advanced Encryption Standard Accelerator (AES) . . . . . . .
3.1.31 General Purpose Input/Output (GPIO) . . . . . . . . . . .
3.1.32 Liquid Crystal Display Driver (LCD) . . . . . . . . . . . .
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.12
.12
.12
.12
.13
.13
.13
.13
.13
.13
.13
.13
.13
.14
.14
.14
.14
.14
.14
.14
.14
.14
.14
.15
.15
.15
.15
.15
.15
.15
.15
.15
.16
3.2 Configuration Summary
3.2.1 EFM32GG230. .
3.2.2 EFM32GG232. .
3.2.3 EFM32GG280. .
3.2.4 EFM32GG290. .
3.2.5 EFM32GG295. .
3.2.6 EFM32GG330. .
3.2.7 EFM32GG332. .
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.16
.17
.19
.21
.23
.25
.27
.29
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silabs.com | Building a more connected world.
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Rev. 2.0 | 6
3.2.8 EFM32GG380.
3.2.9 EFM32GG390.
3.2.10 EFM32GG395
3.2.11 EFM32GG840
3.2.12 EFM32GG842
3.2.13 EFM32GG880
3.2.14 EFM32GG890
3.2.15 EFM32GG895
3.2.16 EFM32GG900
3.2.17 EFM32GG940
3.2.18 EFM32GG942
3.2.19 EFM32GG980
3.2.20 EFM32GG990
3.2.21 EFM32GG995
3.3 Memory Map
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.31
.33
.35
.37
.39
.41
.43
.45
.47
.49
.51
.53
.55
.57
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.59
4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.1 Test Conditions . . . . . . . .
4.1.1 Typical Values . . . . . .
4.1.2 Minimum and Maximum Values .
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.61
.61
.61
4.2 Absolute Maximum Ratings.
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.61
4.3 General Operating Conditions .
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.61
4.4 Current Consumption . . . .
4.4.1 EM1 Current Consumption
4.4.2 EM2 Current Consumption
4.4.3 EM3 Current Consumption
4.4.4 EM4 Current Consumption
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.62
.63
.66
.67
.67
4.5 Transition between Energy Modes .
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.68
4.6 Power Management .
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.68
4.7 Flash .
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.69
4.8 General Purpose Input Output .
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.70
4.9 Oscillators . .
4.9.1 LFXO. . .
4.9.2 HFXO . .
4.9.3 LFRCO . .
4.9.4 HFRCO . .
4.9.5 AUXHFRCO
4.9.6 ULFRCO .
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.77
.78
.78
.79
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.84
.84
4.10 Analog Digital Converter (ADC) .
4.10.1 Typical performance . . .
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.85
.91
4.11 Digital Analog Converter (DAC) .
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.96
4.12 Operational Amplifier (OPAMP) .
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4.13 Analog Comparator (ACMP) .
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. 102
4.14 Voltage Comparator (VCMP) .
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. 104
silabs.com | Building a more connected world.
Rev. 2.0 | 7
4.15 EBI
4.16 LCD
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4.17 I2C
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4.18 USART SPI
4.19 USB
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. 113
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4.20 Digital Peripherals
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. 114
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.115
5. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
5.1 EFM32GG230 (QFN64) . . . . . . . . . . . . . . . . . . . . . . . . . . 116
5.1.1 Pinout
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. 16
5.1.2 Alternate Functionality Pinout
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5.1.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.1.4 Opamp Pinout Overview
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5.2 EFM32GG232 (TQFP64)
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. 25
5.2.1 Pinout
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. 26
5.2.2 Alternate Functionality Pinout
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5.2.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 134
5.2.4 Opamp Pinout Overview
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5.3 EFM32GG280 (LQFP100) . . . . . . . . . . . . . . . . . . . . . . . . . 135
5.3.1 Pinout
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. 36
5.3.2 Alternate Functionality Pinout
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5.3.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 149
5.3.4 Opamp Pinout Overview
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5.4 EFM32GG290 (BGA112)
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. 49
5.4.1 Pinout
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. 50
5.4.2 Alternate Functionality Pinout
. . . . . . . . . . . . . . . . . . . . . 156
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5.4.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 163
5.4.4 Opamp Pinout Overview
. . . . . . . . . . . . . . . . . . . . . . . .163
5.5 EFM32GG295 (BGA120)
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. 63
5.5.1 Pinout
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. 64
5.5.2 Alternate Functionality Pinout
. . . . . . . . . . . . . . . . . . . . . 170
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5.5.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 177
5.5.4 Opamp Pinout Overview
. . . . . . . . . . . . . . . . . . . . . . . .177
5.6 EFM32GG330 (QFN64) . . . . . . . . . . . . . . . . . . . . . . . . . . 177
5.6.1 Pinout
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. 78
5.6.2 Alternate Functionality Pinout
. . . . . . . . . . . . . . . . . . . . . 182
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5.6.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 187
5.6.4 Opamp Pinout Overview
. . . . . . . . . . . . . . . . . . . . . . . .187
5.7 EFM32GG332 (TQFP64)
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. 87
5.7.1 Pinout
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. 88
5.7.2 Alternate Functionality Pinout
. . . . . . . . . . . . . . . . . . . . . 192
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5.7.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 196
5.7.4 Opamp Pinout Overview
. . . . . . . . . . . . . . . . . . . . . . . .197
5.8 EFM32GG380 (LQFP100) . . . . . . . . . . . . . . . . . . . . . . . . . 197
5.8.1 Pinout
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
. 98
silabs.com | Building a more connected world.
Rev. 2.0 | 8
5.8.2 Alternate Functionality Pinout
. . . . . . . . . . . . . . . . . . . . . 203
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5.8.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 210
5.8.4 Opamp Pinout Overview
. . . . . . . . . . . . . . . . . . . . . . . .210
5.9 EFM32GG390 (BGA112)
. . . . . . . . . . . . . . . . . . . . . . . . 2
. 10
5.9.1 Pinout
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. 11
5.9.2 Alternate Functionality Pinout
. . . . . . . . . . . . . . . . . . . . . 217
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5.9.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 224
5.9.4 Opamp Pinout Overview
. . . . . . . . . . . . . . . . . . . . . . . .224
5.10 EFM32GG395 (BGA120) . . . . . . . . . . . . . . . . . . . . . . . . . 224
5.10.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
5.10.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .231
5.10.3 GPIO Pinout Overview
. . . . . . . . . . . . . . . . . . . . . . . 2
. 38
5.10.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 238
5.11 EFM32GG840 (QFN64)
. . . . . . . . . . . . . . . . . . . . . . . . 2
. 38
5.11.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
5.11.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .243
5.11.3 GPIO Pinout Overview
. . . . . . . . . . . . . . . . . . . . . . . 2
. 49
5.11.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 249
5.12 EFM32GG842 (TQFP64) . . . . . . . . . . . . . . . . . . . . . . . . . 249
5.12.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
5.12.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .254
5.12.3 GPIO Pinout Overview
. . . . . . . . . . . . . . . . . . . . . . . 2
. 59
5.12.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 260
5.13 EFM32GG880 (LQFP100)
. . . . . . . . . . . . . . . . . . . . . . . 260
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5.13.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
5.13.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .267
5.13.3 GPIO Pinout Overview
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. 76
5.13.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 277
5.14 EFM32GG890 (BGA112) . . . . . . . . . . . . . . . . . . . . . . . . . 277
5.14.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
5.14.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .284
5.14.3 GPIO Pinout Overview
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. 93
5.14.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 294
5.15 EFM32GG895 (BGA120) . . . . . . . . . . . . . . . . . . . . . . . . . 294
5.15.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
5.15.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .301
5.15.3 GPIO Pinout Overview
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. 10
5.15.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 310
5.16 EFM32GG900 (Wafer) . . . . . . . . . . . . . . . . . . . . . . . . . . 310
5.16.1 Padout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
5.16.2 Alternate Functionality Padout . . . . . . . . . . . . . . . . . . . . . . 317
5.16.3 GPIO Pinout Overview
. . . . . . . . . . . . . . . . . . . . . . . 3
. 26
5.16.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 327
5.17 EFM32GG940 (QFN64)
. . . . . . . . . . . . . . . . . . . . . . . . 3
. 27
5.17.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
5.17.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .332
silabs.com | Building a more connected world.
Rev. 2.0 | 9
5.17.3 GPIO Pinout Overview
. . . . . . . . . . . . . . . . . . . . . . . 3
. 38
5.17.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 338
5.18 EFM32GG942 (TQFP64) . . . . . . . . . . . . . . . . . . . . . . . . . 338
5.18.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
5.18.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .343
5.18.3 GPIO Pinout Overview
. . . . . . . . . . . . . . . . . . . . . . . 3
. 48
5.18.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 349
5.19 EFM32GG980 (LQFP100)
. . . . . . . . . . . . . . . . . . . . . . . 349
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5.19.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
5.19.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .356
5.19.3 GPIO Pinout Overview
. . . . . . . . . . . . . . . . . . . . . . . 3
. 65
5.19.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 365
5.20 EFM32GG990 (BGA112) . . . . . . . . . . . . . . . . . . . . . . . . . 365
5.20.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
5.20.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .372
5.20.3 GPIO Pinout Overview
. . . . . . . . . . . . . . . . . . . . . . . 3
. 81
5.20.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 381
5.21 EFM32GG995 (BGA120) . . . . . . . . . . . . . . . . . . . . . . . . . 381
5.21.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
5.21.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .388
5.21.3 GPIO Pinout Overview
. . . . . . . . . . . . . . . . . . . . . . . 3
. 97
5.21.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 398
6. BGA112 Package Specifications
. . . . . . . . . . . . . . . . . . . . . . .399
6.1 BGA112 Package Dimensions .
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. 399
6.2 BGA112 PCB Layout .
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. 400
6.3 BGA112 Package Marking .
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. 402
7. BGA120 Package Specifications
. . . . . . . . . . . . . . . . . . . . . . .403
7.1 BGA120 Package Dimensions .
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. 403
7.2 BGA120 PCB Layout .
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. 404
7.3 BGA120 Package Marking .
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. 406
8. LQFP100 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . 407
8.1 LQFP100 Package Dimensions
8.2 LQFP100 PCB Layout
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8.3 LQFP100 Package Marking
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. 4
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10. QFN64 Package Specifications
10.1 QFN64 Package Dimensions.
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10.2 QFN64 PCB Layout .
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11.2 Wafer Description
11.2.1 Environmental
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12. Chip Revision, Solder Information, Errata
12.3 Errata
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11.3 Wafer Storage Guidelines .
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Rev. 2.0 | 11
EFM32GG Data Sheet
System Summary
3. System Summary
3.1 System Introduction
The EFM32 MCUs are the world’s most energy friendly microcontrollers. With a unique combination of the powerful 32-bit ARM CortexM3, innovative low energy techniques, short wake-up time from energy saving modes, and a wide selection of peripherals, the
EFM32GG microcontroller is well suited for any battery operated application as well as other systems requiring high performance and
low-energy consumption. This section gives a short introduction to each of the modules in general terms and also shows a summary of
the configuration for the EFM32GG devices. For a complete feature set and in-depth information on the modules, the reader is referred
to the EFM32GG Reference Manual.
A block diagram of the EFM32GG is shown in the following figure.
Core / Memory
ARM CortexTM
M3 processor
Memory
Protection Unit
Flash Program
Memory
Debug w/ ETM
RAM Memory
DMA Controller
Clock Management
Energy Management
High Frequency
Crystal Oscillator
High Frequency
RC Oscillator
Voltage
Regulator
Voltage
Comparator
Auxiliary High
Freq. RC Osc.
Low Freq.
RC Oscillator
Brown-out
Detector
Power-on
Reset
Low Frequency
Crystal Oscillator
Ultra Low Freq.
RC Oscillator
Back-up Power
Domain
Security
Hardware AES
32-bit bus
Peripheral Reflex System
Serial Interfaces
I/O Ports
Timers and Triggers
USART
UART
External Bus
Interface
TFT Driver
Low Energy
UARTTM
I2C
External
Interrupts
General
Purpose I/O
Pin Reset
Pin Wakeup
USB
Timer/Counter
LESENSE
Low Energy Timer
Real Time Counter
Pulse Counter
Watchdog Timer
Analog Interfaces
ADC
LCD Controller
DAC
Operational
Amplifier
Analog
Comparator
Back-up RTC
Lowest power mode with peripheral operational:
EM0 - Active
EM1 - Sleep
EM2 – Deep Sleep
EM3 - Stop
EM4 - Shutoff
Figure 3.1. Block Diagram
3.1.1 ARM Cortex-M3 Core
The ARM Cortex-M3 includes a 32-bit RISC processor which can achieve as much as 1.25 Dhrystone MIPS/MHz. A Memory Protection
Unit with support for up to 8 memory segments is included, as well as a Wake-up Interrupt Controller handling interrupts triggered while
the CPU is asleep. The EFM32 implementation of the Cortex-M3 is described in detail in EFM32GG Reference Manual.
3.1.2 Debug Interface (DBG)
This device includes hardware debug support through a 2-pin serial-wire debug interface and an Embedded Trace Module (ETM) for
data/instruction tracing. In addition there is also a 1-wire Serial Wire Viewer pin which can be used to output profiling information, data
trace and software-generated messages.
3.1.3 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the EFM32GG microcontroller. The flash memory is readable and
writable from both the Cortex-M3 and DMA. The flash memory is divided into two blocks; the main block and the information block.
Program code is normally written to the main block. Additionally, the information block is available for special user data and flash lock
bits. There is also a read-only page in the information block containing system and device calibration data. Read and write operations
are supported in the energy modes EM0 and EM1.
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Rev. 2.0 | 12
EFM32GG Data Sheet
System Summary
3.1.4 Direct Memory Access Controller (DMA)
The Direct Memory Access (DMA) controller performs memory operations independently of the CPU. This has the benefit of reducing
the energy consumption and the workload of the CPU, and enables the system to stay in low energy modes when moving for instance
data from the USART to RAM or from the External Bus Interface to a PWM-generating timer. The DMA controller uses the PL230
µDMA controller licensed from ARM.
3.1.5 Reset Management Unit (RMU)
The RMU is responsible for handling the reset functionality of the EFM32GG.
3.1.6 Energy Management Unit (EMU)
The Energy Management Unit (EMU) manage all the low energy modes (EM) in EFM32GG microcontrollers. Each energy mode manages if the CPU and the various peripherals are available. The EMU can also be used to turn off the power to unused SRAM blocks.
3.1.7 Clock Management Unit (CMU)
The Clock Management Unit (CMU) is responsible for controlling the oscillators and clocks on-board the EFM32GG. The CMU provides
the capability to turn on and off the clock on an individual basis to all peripheral modules in addition to enable/disable and configure the
available oscillators. The high degree of flexibility enables software to minimize energy consumption in any specific application by not
wasting power on peripherals and oscillators that are inactive.
3.1.8 Watchdog (WDOG)
The purpose of the watchdog timer is to generate a reset in case of a system failure, to increase application reliability. The failure may
e.g. be caused by an external event, such as an ESD pulse, or by a software failure.
3.1.9 Peripheral Reflex System (PRS)
The Peripheral Reflex System (PRS) system is a network which lets the different peripheral module communicate directly with each
other without involving the CPU. Peripheral modules which send out Reflex signals are called producers. The PRS routes these reflex
signals to consumer peripherals which apply actions depending on the data received. The format for the Reflex signals is not given, but
edge triggers and other functionality can be applied by the PRS.
3.1.10 External Bus Interface (EBI)
The External Bus Interface provides access to external parallel interface devices such as SRAM, FLASH, ADCs and LCDs. The interface is memory mapped into the address bus of the Cortex-M3. This enables seamless access from software without manually manipulating the IO settings each time a read or write is performed. The data and address lines are multiplexed in order to reduce the number
of pins required to interface the external devices. The timing is adjustable to meet specifications of the external devices. The interface is
limited to asynchronous devices.
3.1.11 TFT Direct Drive
The EBI contains a TFT controller which can drive a TFT via a 565 RGB interface. The TFT controller supports programmable display
and port sizes and offers accurate control of frequency and setup and hold timing. Direct Drive is supported for TFT displays which do
not have their own frame buffer. In that case TFT Direct Drive can transfer data from either on-chip memory or from an external memory device to the TFT at low CPU load. Automatic alpha-blending and masking is also supported for transfers through the EBI interface.
3.1.12 Universal Serial Bus Controller (USB)
The USB is a full-speed USB 2.0 compliant OTG host/device controller. The USB can be used in Device, On-the-go (OTG) Dual Role
Device or Host-only configuration. In OTG mode the USB supports both Host Negotiation Protocol (HNP) and Session Request Protocol (SRP). The device supports both fullspeed (12MBit/s) and low speed (1.5MBit/s) operation. The USB device includes an internal
dedicated Descriptor-Based Scatter/Gather DMA and supports up to 6 OUT endpoints and 6 IN endpoints, in addition to endpoint 0.
The on-chip PHY includes all OTG features, except for the voltage booster for supplying 5V to VBUS when operating as host.
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Rev. 2.0 | 13
EFM32GG Data Sheet
System Summary
3.1.13 Inter-Integrated Circuit Interface (I2C)
The I2C module provides an interface between the MCU and a serial I2C-bus. It is capable of acting as both a master and a slave, and
supports multi-master buses. Both standard-mode, fast-mode and fastmode plus speeds are supported, allowing transmission rates all
the way from 10 kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also provided to allow implementation of an SMBus compliant
system. The interface provided to software by the I2C module, allows both fine-grained control of the transmission process and close to
automatic transfers. Automatic recognition of slave addresses is provided in all energy modes.
3.1.14 Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
The Universal Synchronous Asynchronous serial Receiver and Transmitter (USART) is a very flexible serial I/O module. It supports full
duplex asynchronous UART communication as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with ISO7816 SmartCards, IrDA and I2S devices.
3.1.15 Pre-Programmed USB/UART Bootloader
The bootloader presented in application note AN0042 is pre-programmed in the device at factory. The bootloader enables users to program the EFM32 through a UART or a USB CDC class virtual UART without the need for a debugger. The autobaud feature, interface
and commands are described further in the application note.
3.1.16 Universal Asynchronous Receiver/Transmitter (UART)
The Universal Asynchronous serial Receiver and Transmitter (UART) is a very flexible serial I/O module. It supports full- and half-duplex asynchronous UART communication.
3.1.17 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART)
The unique LEUARTTM, the Low Energy UART, is a UART that allows two-way UART communication on a strict power budget. Only a
32.768 kHz clock is needed to allow UART communication up to 9600 baud/ s. The LEUART includes all necessary hardware support
to make asynchronous serial communication possible with minimum of software intervention and energy consumption.
3.1.18 Timer/Counter (TIMER)
The 16-bit general purpose Timer has 3 compare/capture channels for input capture and compare/Pulse- Width Modulation (PWM) output. TIMER0 also includes a Dead-Time Insertion module suitable for motor control applications.
3.1.19 Real Time Counter (RTC)
The Real Time Counter (RTC) contains a 24-bit counter and is clocked either by a 32.768 kHz crystal oscillator, or a 32.768 kHz RC
oscillator. In addition to energy modes EM0 and EM1, the RTC is also available in EM2. This makes it ideal for keeping track of time
since the RTC is enabled in EM2 where most of the device is powered down.
3.1.20 Backup Real Time Counter (BURTC)
The Backup Real Time Counter (BURTC) contains a 32-bit counter and is clocked either by a 32.768 kHz crystal oscillator, a 32.768
kHz RC oscillator or a 1 kHz ULFRCO. The BURTC is available in all Energy Modes and it can also run in backup mode, making it
operational even if the main power should drain out.
3.1.21 Low Energy Timer (LETIMER)
The unique LETIMERTM, the Low Energy Timer, is a 16-bit timer that is available in energy mode EM2 in addition to EM1 and EM0.
Because of this, it can be used for timing and output generation when most of the device is powered down, allowing simple tasks to be
performed while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of
waveforms with minimal software intervention. It is also connected to the Real Time Counter (RTC), and can be configured to start
counting on compare matches from the RTC.
3.1.22 Pulse Counter (PCNT)
The Pulse Counter (PCNT) can be used for counting pulses on a single input or to decode quadrature encoded inputs. It runs off either
the internal LFACLK or the PCNTn_S0IN pin as external clock source. The module may operate in energy mode EM0 - EM3.
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Rev. 2.0 | 14
EFM32GG Data Sheet
System Summary
3.1.23 Analog Comparator (ACMP)
The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is higher. Inputs can either be one of the selectable internal references or from external pins. Response time and thereby also the current
consumption can be configured by altering the current supply to the comparator.
3.1.24 Voltage Comparator (VCMP)
The Voltage Supply Comparator is used to monitor the supply voltage from software. An interrupt can be generated when the supply
falls below or rises above a programmable threshold. Response time and thereby also the current consumption can be configured by
altering the current supply to the comparator.
3.1.25 Analog to Digital Converter (ADC)
The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to one million samples per
second. The integrated input mux can select inputs from 8 external pins and 6 internal signals.
3.1.26 Digital to Analog Converter (DAC)
The Digital to Analog Converter (DAC) can convert a digital value to an analog output voltage. The DAC is fully differential rail-to-rail,
with 12-bit resolution. It has two single-ended output buffers which can be combined into one differential output. The DAC may be used
for a number of different applications such as sensor interfaces or sound output.
3.1.27 Operational Amplifier (OPAMP)
The EFM32GG features up to 3 Operational Amplifiers. The Operational Amplifier is a versatile general purpose amplifier with rail-to-rail
differential input and rail-to-rail single-ended output. The input can be set to pin, DAC or OPAMP, whereas the output can be pin,
OPAMP or ADC. The current is programmable and the OPAMP has various internal configurations such as unity gain, programmable
gain using internal resistors etc.
3.1.28 Low Energy Sensor Interface (LESENSE)
The Low Energy Sensor Interface (LESENSETM), is a highly configurable sensor interface with support for up to 16 individually configurable sensors. By controlling the analog comparators and DAC, LESENSE is capable of supporting a wide range of sensors and measurement schemes, and can for instance measure LC sensors, resistive sensors and capacitive sensors. LESENSE also includes a programmable FSM which enables simple processing of measurement results without CPU intervention. LESENSE is available in energy
mode EM2, in addition to EM0 and EM1, making it ideal for sensor monitoring in applications with a strict energy budget.
3.1.29 Backup Power Domain
The backup power domain is a separate power domain containing a Backup Real Time Counter, BURTC, and a set of retention registers, available in all energy modes. This power domain can be configured to automatically change power source to a backup battery
when the main power drains out. The backup power domain enables the EFM32GG to keep track of time and retain data, even if the
main power source should drain out.
3.1.30 Advanced Encryption Standard Accelerator (AES)
The AES accelerator performs AES encryption and decryption with 128-bit or 256-bit keys. Encrypting or decrypting one 128-bit data
block takes 52 HFCORECLK cycles with 128-bit keys and 75 HFCORECLK cycles with 256-bit keys. The AES module is an AHB slave
which enables efficient access to the data and key registers. All write accesses to the AES module must be 32-bit operations, i.e. 8- or
16-bit operations are not supported.
3.1.31 General Purpose Input/Output (GPIO)
In the EFM32GG, there are up to 93 General Purpose Input/Output (GPIO) pins, which are divided into ports with up to 16 pins each.
These pins can individually be configured as either an output or input. More advanced configurations like open-drain, filtering and drive
strength can also be configured individually for the pins. The GPIO pins can also be overridden by peripheral pin connections, like Timer PWM outputs or USART communication, which can be routed to several locations on the device. The GPIO supports up to 16 asynchronous external pin interrupts, which enables interrupts from any pin on the device. Also, the input value of a pin can be routed
through the Peripheral Reflex System to other peripherals.
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Rev. 2.0 | 15
EFM32GG Data Sheet
System Summary
3.1.32 Liquid Crystal Display Driver (LCD)
The LCD driver is capable of driving a segmented LCD display with up to 8x36 segments. A voltage boost function enables it to provide
the LCD display with higher voltage than the supply voltage for the device. In addition, an animation feature can run custom animations
on the LCD display without any CPU intervention. The LCD driver can also remain active even in Energy Mode 2 and provides a Frame
Counter interrupt that can wake-up the device on a regular basis for updating data.
3.2 Configuration Summary
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Rev. 2.0 | 16
EFM32GG Data Sheet
System Summary
3.2.1 EFM32GG230
The features of the EFM32GG230 is a subset of the feature set described in the EFM32GG Reference Manual. The following table
describes device specific implementation of the features.
Table 3.1. EFM32GG230 Configuration Summary
Module
Configuration
Pin Connections
Cortex-M3
Full configuration
NA
DBG
Full configuration
DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC
Full configuration
NA
DMA
Full configuration
NA
RMU
Full configuration
NA
EMU
Full configuration
NA
CMU
Full configuration
CMU_OUT0, CMU_OUT1
WDOG
Full configuration
NA
PRS
Full configuration
NA
I2C0
Full configuration
I2C0_SDA, I2C0_SCL
I2C1
Full configuration
I2C1_SDA, I2C1_SCL
USART0
Full configuration with IrDA
US0_TX, US0_RX. US0_CLK, US0_CS
USART1
Full configuration with I2S
US1_TX, US1_RX, US1_CLK, US1_CS
USART2
Full configuration with I2S
US2_TX, US2_RX, US2_CLK, US2_CS
LEUART0
Full configuration
LEU0_TX, LEU0_RX
LEUART1
Full configuration
LEU1_TX, LEU1_RX
TIMER0
Full configuration with DTI
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1
Full configuration
TIM1_CC[2:0]
TIMER2
Full configuration
TIM2_CC[2:0]
TIMER3
Full configuration
TIM3_CC[2:0]
RTC
Full configuration
NA
BURTC
Full configuration
NA
LETIMER0
Full configuration
LET0_O[1:0]
PCNT0
Full configuration, 16-bit count register
PCNT0_S[1:0]
PCNT1
Full configuration, 8-bit count register
PCNT1_S[1:0]
PCNT2
Full configuration, 8-bit count register
PCNT2_S[1:0]
ACMP0
Full configuration
ACMP0_CH[7:0], ACMP0_O
ACMP1
Full configuration
ACMP1_CH[7:0], ACMP1_O
VCMP
Full configuration
NA
ADC0
Full configuration
ADC0_CH[7:0]
DAC0
Full configuration
DAC0_OUT[1:0], DAC0_OUTxALT
OPAMP
Full configuration
Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,
OPAMP_Nx
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Rev. 2.0 | 17
EFM32GG Data Sheet
System Summary
Module
Configuration
Pin Connections
AES
Full configuration
NA
GPIO
56 pins
Available pins are shown in 5.1.3 GPIO Pinout Overview
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Rev. 2.0 | 18
EFM32GG Data Sheet
System Summary
3.2.2 EFM32GG232
The features of the EFM32GG232 is a subset of the feature set described in the EFM32GG Reference Manual. The following table
describes device specific implementation of the features.
Table 3.2. EFM32GG232 Configuration Summary
Module
Configuration
Pin Connections
Cortex-M3
Full configuration
NA
DBG
Full configuration
DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC
Full configuration
NA
DMA
Full configuration
NA
RMU
Full configuration
NA
EMU
Full configuration
NA
CMU
Full configuration
CMU_OUT0, CMU_OUT1
WDOG
Full configuration
NA
PRS
Full configuration
NA
I2C0
Full configuration
I2C0_SDA, I2C0_SCL
I2C1
Full configuration
I2C1_SDA, I2C1_SCL
USART0
Full configuration with IrDA
US0_TX, US0_RX. US0_CLK, US0_CS
USART1
Full configuration with I2S
US1_TX, US1_RX, US1_CLK, US1_CS
USART2
Full configuration with I2S
US2_TX, US2_RX, US2_CLK, US2_CS
LEUART0
Full configuration
LEU0_TX, LEU0_RX
LEUART1
Full configuration
LEU1_TX, LEU1_RX
TIMER0
Full configuration with DTI
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1
Full configuration
TIM1_CC[2:0]
TIMER2
Full configuration
TIM2_CC[2:0]
TIMER3
Full configuration
TIM3_CC[2:0]
RTC
Full configuration
NA
BURTC
Full configuration
NA
LETIMER0
Full configuration
LET0_O[1:0]
PCNT0
Full configuration, 16-bit count register
PCNT0_S[1:0]
PCNT1
Full configuration, 8-bit count register
PCNT1_S[1:0]
PCNT2
Full configuration, 8-bit count register
PCNT2_S[1:0]
ACMP0
Full configuration
ACMP0_CH[7:0], ACMP0_O
ACMP1
Full configuration
ACMP1_CH[7:0], ACMP1_O
VCMP
Full configuration
NA
ADC0
Full configuration
ADC0_CH[7:0]
DAC0
Full configuration
DAC0_OUT[1:0], DAC0_OUTxALT
OPAMP
Full configuration
Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,
OPAMP_Nx
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Rev. 2.0 | 19
EFM32GG Data Sheet
System Summary
Module
Configuration
Pin Connections
AES
Full configuration
NA
GPIO
53 pins
Available pins are shown in 5.2.3 GPIO Pinout Overview
silabs.com | Building a more connected world.
Rev. 2.0 | 20
EFM32GG Data Sheet
System Summary
3.2.3 EFM32GG280
The features of the EFM32GG280 is a subset of the feature set described in the EFM32GG Reference Manual. The following table
describes device specific implementation of the features.
Table 3.3. EFM32GG280 Configuration Summary
Module
Configuration
Pin Connections
Cortex-M3
Full configuration
NA
DBG
Full configuration
DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC
Full configuration
NA
DMA
Full configuration
NA
RMU
Full configuration
NA
EMU
Full configuration
NA
CMU
Full configuration
CMU_OUT0, CMU_OUT1
WDOG
Full configuration
NA
PRS
Full configuration
NA
EBI
Full configuration
EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0],
EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC,
EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn
I2C0
Full configuration
I2C0_SDA, I2C0_SCL
I2C1
Full configuration
I2C1_SDA, I2C1_SCL
USART0
Full configuration with IrDA
US0_TX, US0_RX. US0_CLK, US0_CS
USART1
Full configuration with I2S
US1_TX, US1_RX, US1_CLK, US1_CS
USART2
Full configuration with I2S
US2_TX, US2_RX, US2_CLK, US2_CS
UART0
Full configuration
U0_TX, U0_RX
UART1
Full configuration
U1_TX, U1_RX
LEUART0
Full configuration
LEU0_TX, LEU0_RX
LEUART1
Full configuration
LEU1_TX, LEU1_RX
TIMER0
Full configuration with DTI
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1
Full configuration
TIM1_CC[2:0]
TIMER2
Full configuration
TIM2_CC[2:0]
TIMER3
Full configuration
TIM3_CC[2:0]
RTC
Full configuration
NA
BURTC
Full configuration
NA
LETIMER0
Full configuration
LET0_O[1:0]
PCNT0
Full configuration, 16-bit count register
PCNT0_S[1:0]
PCNT1
Full configuration, 8-bit count register
PCNT1_S[1:0]
PCNT2
Full configuration, 8-bit count register
PCNT2_S[1:0]
ACMP0
Full configuration
ACMP0_CH[7:0], ACMP0_O
ACMP1
Full configuration
ACMP1_CH[7:0], ACMP1_O
silabs.com | Building a more connected world.
Rev. 2.0 | 21
EFM32GG Data Sheet
System Summary
Module
Configuration
Pin Connections
VCMP
Full configuration
NA
ADC0
Full configuration
ADC0_CH[7:0]
DAC0
Full configuration
DAC0_OUT[1:0], DAC0_OUTxALT
OPAMP
Full configuration
Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,
OPAMP_Nx
AES
Full configuration
NA
GPIO
85 pins
Available pins are shown in 5.3.3 GPIO Pinout Overview
silabs.com | Building a more connected world.
Rev. 2.0 | 22
EFM32GG Data Sheet
System Summary
3.2.4 EFM32GG290
The features of the EFM32GG290 is a subset of the feature set described in the EFM32GG Reference Manual. The following table
describes device specific implementation of the features.
Table 3.4. EFM32GG290 Configuration Summary
Module
Configuration
Pin Connections
Cortex-M3
Full configuration
NA
DBG
Full configuration
DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC
Full configuration
NA
DMA
Full configuration
NA
RMU
Full configuration
NA
EMU
Full configuration
NA
CMU
Full configuration
CMU_OUT0, CMU_OUT1
WDOG
Full configuration
NA
PRS
Full configuration
NA
EBI
Full configuration
EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0],
EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC,
EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn
I2C0
Full configuration
I2C0_SDA, I2C0_SCL
I2C1
Full configuration
I2C1_SDA, I2C1_SCL
USART0
Full configuration with IrDA
US0_TX, US0_RX. US0_CLK, US0_CS
USART1
Full configuration with I2S
US1_TX, US1_RX, US1_CLK, US1_CS
USART2
Full configuration with I2S
US2_TX, US2_RX, US2_CLK, US2_CS
UART0
Full configuration
U0_TX, U0_RX
UART1
Full configuration
U1_TX, U1_RX
LEUART0
Full configuration
LEU0_TX, LEU0_RX
LEUART1
Full configuration
LEU1_TX, LEU1_RX
TIMER0
Full configuration with DTI
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1
Full configuration
TIM1_CC[2:0]
TIMER2
Full configuration
TIM2_CC[2:0]
TIMER3
Full configuration
TIM3_CC[2:0]
RTC
Full configuration
NA
BURTC
Full configuration
NA
LETIMER0
Full configuration
LET0_O[1:0]
PCNT0
Full configuration, 16-bit count register
PCNT0_S[1:0]
PCNT1
Full configuration, 8-bit count register
PCNT1_S[1:0]
PCNT2
Full configuration, 8-bit count register
PCNT2_S[1:0]
ACMP0
Full configuration
ACMP0_CH[7:0], ACMP0_O
ACMP1
Full configuration
ACMP1_CH[7:0], ACMP1_O
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Rev. 2.0 | 23
EFM32GG Data Sheet
System Summary
Module
Configuration
Pin Connections
VCMP
Full configuration
NA
ADC0
Full configuration
ADC0_CH[7:0]
DAC0
Full configuration
DAC0_OUT[1:0], DAC0_OUTxALT
OPAMP
Full configuration
Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,
OPAMP_Nx
AES
Full configuration
NA
GPIO
90 pins
Available pins are shown in 5.4.3 GPIO Pinout Overview
silabs.com | Building a more connected world.
Rev. 2.0 | 24
EFM32GG Data Sheet
System Summary
3.2.5 EFM32GG295
The features of the EFM32GG295 is a subset of the feature set described in the EFM32GG Reference Manual. The following table
describes device specific implementation of the features.
Table 3.5. EFM32GG295 Configuration Summary
Module
Configuration
Pin Connections
Cortex-M3
Full configuration
NA
DBG
Full configuration
DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC
Full configuration
NA
DMA
Full configuration
NA
RMU
Full configuration
NA
EMU
Full configuration
NA
CMU
Full configuration
CMU_OUT0, CMU_OUT1
WDOG
Full configuration
NA
PRS
Full configuration
NA
EBI
Full configuration
EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0],
EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC,
EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn
I2C0
Full configuration
I2C0_SDA, I2C0_SCL
I2C1
Full configuration
I2C1_SDA, I2C1_SCL
USART0
Full configuration with IrDA
US0_TX, US0_RX. US0_CLK, US0_CS
USART1
Full configuration with I2S
US1_TX, US1_RX, US1_CLK, US1_CS
USART2
Full configuration with I2S
US2_TX, US2_RX, US2_CLK, US2_CS
UART0
Full configuration
U0_TX, U0_RX
UART1
Full configuration
U1_TX, U1_RX
LEUART0
Full configuration
LEU0_TX, LEU0_RX
LEUART1
Full configuration
LEU1_TX, LEU1_RX
TIMER0
Full configuration with DTI
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1
Full configuration
TIM1_CC[2:0]
TIMER2
Full configuration
TIM2_CC[2:0]
TIMER3
Full configuration
TIM3_CC[2:0]
RTC
Full configuration
NA
BURTC
Full configuration
NA
LETIMER0
Full configuration
LET0_O[1:0]
PCNT0
Full configuration, 16-bit count register
PCNT0_S[1:0]
PCNT1
Full configuration, 8-bit count register
PCNT1_S[1:0]
PCNT2
Full configuration, 8-bit count register
PCNT2_S[1:0]
ACMP0
Full configuration
ACMP0_CH[7:0], ACMP0_O
ACMP1
Full configuration
ACMP1_CH[7:0], ACMP1_O
silabs.com | Building a more connected world.
Rev. 2.0 | 25
EFM32GG Data Sheet
System Summary
Module
Configuration
Pin Connections
VCMP
Full configuration
NA
ADC0
Full configuration
ADC0_CH[7:0]
DAC0
Full configuration
DAC0_OUT[1:0], DAC0_OUTxALT
OPAMP
Full configuration
Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,
OPAMP_Nx
AES
Full configuration
NA
GPIO
93 pins
Available pins are shown in 5.5.3 GPIO Pinout Overview
silabs.com | Building a more connected world.
Rev. 2.0 | 26
EFM32GG Data Sheet
System Summary
3.2.6 EFM32GG330
The features of the EFM32GG330 is a subset of the feature set described in the EFM32GG Reference Manual. The following table
describes device specific implementation of the features.
Table 3.6. EFM32GG330 Configuration Summary
Module
Configuration
Pin Connections
Cortex-M3
Full configuration
NA
DBG
Full configuration
DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC
Full configuration
NA
DMA
Full configuration
NA
RMU
Full configuration
NA
EMU
Full configuration
NA
CMU
Full configuration
CMU_OUT0, CMU_OUT1
WDOG
Full configuration
NA
PRS
Full configuration
NA
USB
Full configuration
USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM,
USB_DMPU, USB_DP, USB_ID
I2C0
Full configuration
I2C0_SDA, I2C0_SCL
I2C1
Full configuration
I2C1_SDA, I2C1_SCL
USART0
Full configuration with IrDA
US0_TX, US0_RX. US0_CLK, US0_CS
USART1
Full configuration with I2S
US1_TX, US1_RX, US1_CLK, US1_CS
USART2
Full configuration with I2S
US2_TX, US2_RX, US2_CLK, US2_CS
LEUART0
Full configuration
LEU0_TX, LEU0_RX
LEUART1
Full configuration
LEU1_TX, LEU1_RX
TIMER0
Full configuration with DTI
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1
Full configuration
TIM1_CC[2:0]
TIMER2
Full configuration
TIM2_CC[2:0]
TIMER3
Full configuration
TIM3_CC[2:0]
RTC
Full configuration
NA
BURTC
Full configuration
NA
LETIMER0
Full configuration
LET0_O[1:0]
PCNT0
Full configuration, 16-bit count register
PCNT0_S[1:0]
PCNT1
Full configuration, 8-bit count register
PCNT1_S[1:0]
PCNT2
Full configuration, 8-bit count register
PCNT2_S[1:0]
ACMP0
Full configuration
ACMP0_CH[7:0], ACMP0_O
ACMP1
Full configuration
ACMP1_CH[7:0], ACMP1_O
VCMP
Full configuration
NA
ADC0
Full configuration
ADC0_CH[7:0]
DAC0
Full configuration
DAC0_OUT[1:0], DAC0_OUTxALT
silabs.com | Building a more connected world.
Rev. 2.0 | 27
EFM32GG Data Sheet
System Summary
Module
Configuration
Pin Connections
OPAMP
Full configuration
Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,
OPAMP_Nx
AES
Full configuration
NA
GPIO
52 pins
Available pins are shown in 5.6.3 GPIO Pinout Overview
silabs.com | Building a more connected world.
Rev. 2.0 | 28
EFM32GG Data Sheet
System Summary
3.2.7 EFM32GG332
The features of the EFM32GG332 is a subset of the feature set described in the EFM32GG Reference Manual. The following table
describes device specific implementation of the features.
Table 3.7. EFM32GG332 Configuration Summary
Module
Configuration
Pin Connections
Cortex-M3
Full configuration
NA
DBG
Full configuration
DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC
Full configuration
NA
DMA
Full configuration
NA
RMU
Full configuration
NA
EMU
Full configuration
NA
CMU
Full configuration
CMU_OUT0, CMU_OUT1
WDOG
Full configuration
NA
PRS
Full configuration
NA
USB
Full configuration
USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM,
USB_DMPU, USB_DP, USB_ID
I2C0
Full configuration
I2C0_SDA, I2C0_SCL
I2C1
Full configuration
I2C1_SDA, I2C1_SCL
USART0
Full configuration with IrDA
US0_TX, US0_RX. US0_CLK, US0_CS
USART1
Full configuration with I2S
US1_TX, US1_RX, US1_CLK, US1_CS
USART2
Full configuration with I2S
US2_TX, US2_RX, US2_CLK, US2_CS
LEUART0
Full configuration
LEU0_TX, LEU0_RX
LEUART1
Full configuration
LEU1_TX, LEU1_RX
TIMER0
Full configuration with DTI
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1
Full configuration
TIM1_CC[2:0]
TIMER2
Full configuration
TIM2_CC[2:0]
TIMER3
Full configuration
TIM3_CC[2:0]
RTC
Full configuration
NA
BURTC
Full configuration
NA
LETIMER0
Full configuration
LET0_O[1:0]
PCNT0
Full configuration, 16-bit count register
PCNT0_S[1:0]
PCNT1
Full configuration, 8-bit count register
PCNT1_S[1:0]
PCNT2
Full configuration, 8-bit count register
PCNT2_S[1:0]
ACMP0
Full configuration
ACMP0_CH[3:0], ACMP0_O
ACMP1
Full configuration
ACMP1_CH[0], ACMP1_O
VCMP
Full configuration
NA
ADC0
Full configuration
ADC0_CH[7:0]
DAC0
Full configuration
DAC0_OUT[1:0], DAC0_OUTxALT
silabs.com | Building a more connected world.
Rev. 2.0 | 29
EFM32GG Data Sheet
System Summary
Module
Configuration
Pin Connections
OPAMP
Full configuration
Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,
OPAMP_Nx
AES
Full configuration
NA
GPIO
50 pins
Available pins are shown in 5.7.3 GPIO Pinout Overview
silabs.com | Building a more connected world.
Rev. 2.0 | 30
EFM32GG Data Sheet
System Summary
3.2.8 EFM32GG380
The features of the EFM32GG380 is a subset of the feature set described in the EFM32GG Reference Manual. The following table
describes device specific implementation of the features.
Table 3.8. EFM32GG380 Configuration Summary
Module
Configuration
Pin Connections
Cortex-M3
Full configuration
NA
DBG
Full configuration
DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC
Full configuration
NA
DMA
Full configuration
NA
RMU
Full configuration
NA
EMU
Full configuration
NA
CMU
Full configuration
CMU_OUT0, CMU_OUT1
WDOG
Full configuration
NA
PRS
Full configuration
NA
USB
Full configuration
USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM,
USB_DMPU, USB_DP, USB_ID
EBI
Full configuration
EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0],
EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC,
EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn
I2C0
Full configuration
I2C0_SDA, I2C0_SCL
I2C1
Full configuration
I2C1_SDA, I2C1_SCL
USART0
Full configuration with IrDA
US0_TX, US0_RX. US0_CLK, US0_CS
USART1
Full configuration with I2S
US1_TX, US1_RX, US1_CLK, US1_CS
USART2
Full configuration with I2S
US2_TX, US2_RX, US2_CLK, US2_CS
UART0
Full configuration
U0_TX, U0_RX
UART1
Full configuration
U1_TX, U1_RX
LEUART0
Full configuration
LEU0_TX, LEU0_RX
LEUART1
Full configuration
LEU1_TX, LEU1_RX
TIMER0
Full configuration with DTI
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1
Full configuration
TIM1_CC[2:0]
TIMER2
Full configuration
TIM2_CC[2:0]
TIMER3
Full configuration
TIM3_CC[2:0]
RTC
Full configuration
NA
BURTC
Full configuration
NA
LETIMER0
Full configuration
LET0_O[1:0]
PCNT0
Full configuration, 16-bit count register
PCNT0_S[1:0]
PCNT1
Full configuration, 8-bit count register
PCNT1_S[1:0]
PCNT2
Full configuration, 8-bit count register
PCNT2_S[1:0]
ACMP0
Full configuration
ACMP0_CH[7:0], ACMP0_O
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Rev. 2.0 | 31
EFM32GG Data Sheet
System Summary
Module
Configuration
Pin Connections
ACMP1
Full configuration
ACMP1_CH[7:0], ACMP1_O
VCMP
Full configuration
NA
ADC0
Full configuration
ADC0_CH[7:0]
DAC0
Full configuration
DAC0_OUT[1:0], DAC0_OUTxALT
OPAMP
Full configuration
Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,
OPAMP_Nx
AES
Full configuration
NA
GPIO
81 pins
Available pins are shown in 5.8.3 GPIO Pinout Overview
silabs.com | Building a more connected world.
Rev. 2.0 | 32
EFM32GG Data Sheet
System Summary
3.2.9 EFM32GG390
The features of the EFM32GG390 is a subset of the feature set described in the EFM32GG Reference Manual. The following table
describes device specific implementation of the features.
Table 3.9. EFM32GG390 Configuration Summary
Module
Configuration
Pin Connections
Cortex-M3
Full configuration
NA
DBG
Full configuration
DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC
Full configuration
NA
DMA
Full configuration
NA
RMU
Full configuration
NA
EMU
Full configuration
NA
CMU
Full configuration
CMU_OUT0, CMU_OUT1
WDOG
Full configuration
NA
PRS
Full configuration
NA
USB
Full configuration
USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM,
USB_DMPU, USB_DP, USB_ID
EBI
Full configuration
EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0],
EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC,
EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn
I2C0
Full configuration
I2C0_SDA, I2C0_SCL
I2C1
Full configuration
I2C1_SDA, I2C1_SCL
USART0
Full configuration with IrDA
US0_TX, US0_RX. US0_CLK, US0_CS
USART1
Full configuration with I2S
US1_TX, US1_RX, US1_CLK, US1_CS
USART2
Full configuration with I2S
US2_TX, US2_RX, US2_CLK, US2_CS
UART0
Full configuration
U0_TX, U0_RX
UART1
Full configuration
U1_TX, U1_RX
LEUART0
Full configuration
LEU0_TX, LEU0_RX
LEUART1
Full configuration
LEU1_TX, LEU1_RX
TIMER0
Full configuration with DTI
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1
Full configuration
TIM1_CC[2:0]
TIMER2
Full configuration
TIM2_CC[2:0]
TIMER3
Full configuration
TIM3_CC[2:0]
RTC
Full configuration
NA
BURTC
Full configuration
NA
LETIMER0
Full configuration
LET0_O[1:0]
PCNT0
Full configuration, 16-bit count register
PCNT0_S[1:0]
PCNT1
Full configuration, 8-bit count register
PCNT1_S[1:0]
PCNT2
Full configuration, 8-bit count register
PCNT2_S[1:0]
ACMP0
Full configuration
ACMP0_CH[7:0], ACMP0_O
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Rev. 2.0 | 33
EFM32GG Data Sheet
System Summary
Module
Configuration
Pin Connections
ACMP1
Full configuration
ACMP1_CH[7:0], ACMP1_O
VCMP
Full configuration
NA
ADC0
Full configuration
ADC0_CH[7:0]
DAC0
Full configuration
DAC0_OUT[1:0], DAC0_OUTxALT
OPAMP
Full configuration
Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,
OPAMP_Nx
AES
Full configuration
NA
GPIO
86 pins
Available pins are shown in 5.9.3 GPIO Pinout Overview
silabs.com | Building a more connected world.
Rev. 2.0 | 34
EFM32GG Data Sheet
System Summary
3.2.10 EFM32GG395
The features of the EFM32GG395 is a subset of the feature set described in the EFM32GG Reference Manual. The following table
describes device specific implementation of the features.
Table 3.10. EFM32GG395 Configuration Summary
Module
Configuration
Pin Connections
Cortex-M3
Full configuration
NA
DBG
Full configuration
DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC
Full configuration
NA
DMA
Full configuration
NA
RMU
Full configuration
NA
EMU
Full configuration
NA
CMU
Full configuration
CMU_OUT0, CMU_OUT1
WDOG
Full configuration
NA
PRS
Full configuration
NA
USB
Full configuration
USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM,
USB_DMPU, USB_DP, USB_ID
EBI
Full configuration
EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0],
EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC,
EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn
I2C0
Full configuration
I2C0_SDA, I2C0_SCL
I2C1
Full configuration
I2C1_SDA, I2C1_SCL
USART0
Full configuration with IrDA
US0_TX, US0_RX. US0_CLK, US0_CS
USART1
Full configuration with I2S
US1_TX, US1_RX, US1_CLK, US1_CS
USART2
Full configuration with I2S
US2_TX, US2_RX, US2_CLK, US2_CS
UART0
Full configuration
U0_TX, U0_RX
UART1
Full configuration
U1_TX, U1_RX
LEUART0
Full configuration
LEU0_TX, LEU0_RX
LEUART1
Full configuration
LEU1_TX, LEU1_RX
TIMER0
Full configuration with DTI
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1
Full configuration
TIM1_CC[2:0]
TIMER2
Full configuration
TIM2_CC[2:0]
TIMER3
Full configuration
TIM3_CC[2:0]
RTC
Full configuration
NA
BURTC
Full configuration
NA
LETIMER0
Full configuration
LET0_O[1:0]
PCNT0
Full configuration, 16-bit count register
PCNT0_S[1:0]
PCNT1
Full configuration, 8-bit count register
PCNT1_S[1:0]
PCNT2
Full configuration, 8-bit count register
PCNT2_S[1:0]
ACMP0
Full configuration
ACMP0_CH[7:0], ACMP0_O
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Rev. 2.0 | 35
EFM32GG Data Sheet
System Summary
Module
Configuration
Pin Connections
ACMP1
Full configuration
ACMP1_CH[7:0], ACMP1_O
VCMP
Full configuration
NA
ADC0
Full configuration
ADC0_CH[7:0]
DAC0
Full configuration
DAC0_OUT[1:0], DAC0_OUTxALT
OPAMP
Full configuration
Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,
OPAMP_Nx
AES
Full configuration
NA
GPIO
93 pins
Available pins are shown in 5.10.3 GPIO Pinout Overview
silabs.com | Building a more connected world.
Rev. 2.0 | 36
EFM32GG Data Sheet
System Summary
3.2.11 EFM32GG840
The features of the EFM32GG840 is a subset of the feature set described in the EFM32GG Reference Manual. The following table
describes device specific implementation of the features.
Table 3.11. EFM32GG840 Configuration Summary
Module
Configuration
Pin Connections
Cortex-M3
Full configuration
NA
DBG
Full configuration
DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC
Full configuration
NA
DMA
Full configuration
NA
RMU
Full configuration
NA
EMU
Full configuration
NA
CMU
Full configuration
CMU_OUT0, CMU_OUT1
WDOG
Full configuration
NA
PRS
Full configuration
NA
I2C0
Full configuration
I2C0_SDA, I2C0_SCL
I2C1
Full configuration
I2C1_SDA, I2C1_SCL
USART0
Full configuration with IrDA
US0_TX, US0_RX. US0_CLK, US0_CS
USART1
Full configuration with I2S
US1_TX, US1_RX, US1_CLK, US1_CS
USART2
Full configuration with I2S
US2_TX, US2_RX, US2_CLK, US2_CS
LEUART0
Full configuration
LEU0_TX, LEU0_RX
LEUART1
Full configuration
LEU1_TX, LEU1_RX
TIMER0
Full configuration with DTI
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1
Full configuration
TIM1_CC[2:0]
TIMER2
Full configuration
TIM2_CC[2:0]
TIMER3
Full configuration
TIM3_CC[2:0]
RTC
Full configuration
NA
BURTC
Full configuration
NA
LETIMER0
Full configuration
LET0_O[1:0]
PCNT0
Full configuration, 16-bit count register
PCNT0_S[1:0]
PCNT1
Full configuration, 8-bit count register
PCNT1_S[1:0]
PCNT2
Full configuration, 8-bit count register
PCNT2_S[1:0]
ACMP0
Full configuration
ACMP0_CH[7:0], ACMP0_O
ACMP1
Full configuration
ACMP1_CH[7:0], ACMP1_O
VCMP
Full configuration
NA
ADC0
Full configuration
ADC0_CH[7:0]
DAC0
Full configuration
DAC0_OUT[1:0], DAC0_OUTxALT
OPAMP
Full configuration
Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,
OPAMP_Nx
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Rev. 2.0 | 37
EFM32GG Data Sheet
System Summary
Module
Configuration
Pin Connections
AES
Full configuration
NA
GPIO
56 pins
Available pins are shown in 5.11.3 GPIO Pinout Overview
LCD
Full configuration
LCD_SEG[19:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N,
LCD_BEXT
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Rev. 2.0 | 38
EFM32GG Data Sheet
System Summary
3.2.12 EFM32GG842
The features of the EFM32GG842 is a subset of the feature set described in the EFM32GG Reference Manual. The following table
describes device specific implementation of the features.
Table 3.12. EFM32GG842 Configuration Summary
Module
Configuration
Pin Connections
Cortex-M3
Full configuration
NA
DBG
Full configuration
DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC
Full configuration
NA
DMA
Full configuration
NA
RMU
Full configuration
NA
EMU
Full configuration
NA
CMU
Full configuration
CMU_OUT0, CMU_OUT1
WDOG
Full configuration
NA
PRS
Full configuration
NA
I2C0
Full configuration
I2C0_SDA, I2C0_SCL
I2C1
Full configuration
I2C1_SDA, I2C1_SCL
USART0
Full configuration with IrDA
US0_TX, US0_RX. US0_CLK, US0_CS
USART1
Full configuration with I2S
US1_TX, US1_RX, US1_CLK, US1_CS
USART2
Full configuration with I2S
US2_TX, US2_RX, US2_CLK, US2_CS
LEUART0
Full configuration
LEU0_TX, LEU0_RX
LEUART1
Full configuration
LEU1_TX, LEU1_RX
TIMER0
Full configuration with DTI
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1
Full configuration
TIM1_CC[2:0]
TIMER2
Full configuration
TIM2_CC[2:0]
TIMER3
Full configuration
TIM3_CC[2:0]
RTC
Full configuration
NA
BURTC
Full configuration
NA
LETIMER0
Full configuration
LET0_O[1:0]
PCNT0
Full configuration, 16-bit count register
PCNT0_S[1:0]
PCNT1
Full configuration, 8-bit count register
PCNT1_S[1:0]
PCNT2
Full configuration, 8-bit count register
PCNT2_S[1:0]
ACMP0
Full configuration
ACMP0_CH[7:0], ACMP0_O
ACMP1
Full configuration
ACMP1_CH[7:0], ACMP1_O
VCMP
Full configuration
NA
ADC0
Full configuration
ADC0_CH[7:0]
DAC0
Full configuration
DAC0_OUT[1:0], DAC0_OUTxALT
OPAMP
Full configuration
Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,
OPAMP_Nx
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Rev. 2.0 | 39
EFM32GG Data Sheet
System Summary
Module
Configuration
Pin Connections
AES
Full configuration
NA
GPIO
53 pins
Available pins are shown in 5.12.3 GPIO Pinout Overview
LCD
Full configuration
LCD_SEG[17:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N,
LCD_BEXT
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Rev. 2.0 | 40
EFM32GG Data Sheet
System Summary
3.2.13 EFM32GG880
The features of the EFM32GG880 is a subset of the feature set described in the EFM32GG Reference Manual. The following table
describes device specific implementation of the features.
Table 3.13. EFM32GG880 Configuration Summary
Module
Configuration
Pin Connections
Cortex-M3
Full configuration
NA
DBG
Full configuration
DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC
Full configuration
NA
DMA
Full configuration
NA
RMU
Full configuration
NA
EMU
Full configuration
NA
CMU
Full configuration
CMU_OUT0, CMU_OUT1
WDOG
Full configuration
NA
PRS
Full configuration
NA
EBI
Full configuration
EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0],
EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC,
EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn
I2C0
Full configuration
I2C0_SDA, I2C0_SCL
I2C1
Full configuration
I2C1_SDA, I2C1_SCL
USART0
Full configuration with IrDA
US0_TX, US0_RX. US0_CLK, US0_CS
USART1
Full configuration with I2S
US1_TX, US1_RX, US1_CLK, US1_CS
USART2
Full configuration with I2S
US2_TX, US2_RX, US2_CLK, US2_CS
UART0
Full configuration
U0_TX, U0_RX
UART1
Full configuration
U1_TX, U1_RX
LEUART0
Full configuration
LEU0_TX, LEU0_RX
LEUART1
Full configuration
LEU1_TX, LEU1_RX
TIMER0
Full configuration with DTI
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1
Full configuration
TIM1_CC[2:0]
TIMER2
Full configuration
TIM2_CC[2:0]
TIMER3
Full configuration
TIM3_CC[2:0]
RTC
Full configuration
NA
BURTC
Full configuration
NA
LETIMER0
Full configuration
LET0_O[1:0]
PCNT0
Full configuration, 16-bit count register
PCNT0_S[1:0]
PCNT1
Full configuration, 8-bit count register
PCNT1_S[1:0]
PCNT2
Full configuration, 8-bit count register
PCNT2_S[1:0]
ACMP0
Full configuration
ACMP0_CH[7:0], ACMP0_O
ACMP1
Full configuration
ACMP1_CH[7:0], ACMP1_O
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Rev. 2.0 | 41
EFM32GG Data Sheet
System Summary
Module
Configuration
Pin Connections
VCMP
Full configuration
NA
ADC0
Full configuration
ADC0_CH[7:0]
DAC0
Full configuration
DAC0_OUT[1:0], DAC0_OUTxALT
OPAMP
Full configuration
Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,
OPAMP_Nx
AES
Full configuration
NA
GPIO
85 pins
Available pins are shown in 5.13.3 GPIO Pinout Overview
LCD
Full configuration
LCD_SEG[35:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N,
LCD_BEXT
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Rev. 2.0 | 42
EFM32GG Data Sheet
System Summary
3.2.14 EFM32GG890
The features of the EFM32GG890 is a subset of the feature set described in the EFM32GG Reference Manual. The following table
describes device specific implementation of the features.
Table 3.14. EFM32GG890 Configuration Summary
Module
Configuration
Pin Connections
Cortex-M3
Full configuration
NA
DBG
Full configuration
DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC
Full configuration
NA
DMA
Full configuration
NA
RMU
Full configuration
NA
EMU
Full configuration
NA
CMU
Full configuration
CMU_OUT0, CMU_OUT1
WDOG
Full configuration
NA
PRS
Full configuration
NA
EBI
Full configuration
EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0],
EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC,
EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn
I2C0
Full configuration
I2C0_SDA, I2C0_SCL
I2C1
Full configuration
I2C1_SDA, I2C1_SCL
USART0
Full configuration with IrDA
US0_TX, US0_RX. US0_CLK, US0_CS
USART1
Full configuration with I2S
US1_TX, US1_RX, US1_CLK, US1_CS
USART2
Full configuration with I2S
US2_TX, US2_RX, US2_CLK, US2_CS
UART0
Full configuration
U0_TX, U0_RX
UART1
Full configuration
U1_TX, U1_RX
LEUART0
Full configuration
LEU0_TX, LEU0_RX
LEUART1
Full configuration
LEU1_TX, LEU1_RX
TIMER0
Full configuration with DTI
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1
Full configuration
TIM1_CC[2:0]
TIMER2
Full configuration
TIM2_CC[2:0]
TIMER3
Full configuration
TIM3_CC[2:0]
RTC
Full configuration
NA
BURTC
Full configuration
NA
LETIMER0
Full configuration
LET0_O[1:0]
PCNT0
Full configuration, 16-bit count register
PCNT0_S[1:0]
PCNT1
Full configuration, 8-bit count register
PCNT1_S[1:0]
PCNT2
Full configuration, 8-bit count register
PCNT2_S[1:0]
ACMP0
Full configuration
ACMP0_CH[7:0], ACMP0_O
ACMP1
Full configuration
ACMP1_CH[7:0], ACMP1_O
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Rev. 2.0 | 43
EFM32GG Data Sheet
System Summary
Module
Configuration
Pin Connections
VCMP
Full configuration
NA
ADC0
Full configuration
ADC0_CH[7:0]
DAC0
Full configuration
DAC0_OUT[1:0], DAC0_OUTxALT
OPAMP
Full configuration
Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,
OPAMP_Nx
AES
Full configuration
NA
GPIO
90 pins
Available pins are shown in 5.14.3 GPIO Pinout Overview
LCD
Full configuration
LCD_SEG[35:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N,
LCD_BEXT
silabs.com | Building a more connected world.
Rev. 2.0 | 44
EFM32GG Data Sheet
System Summary
3.2.15 EFM32GG895
The features of the EFM32GG895 is a subset of the feature set described in the EFM32GG Reference Manual. The following table
describes device specific implementation of the features.
Table 3.15. EFM32GG895 Configuration Summary
Module
Configuration
Pin Connections
Cortex-M3
Full configuration
NA
DBG
Full configuration
DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC
Full configuration
NA
DMA
Full configuration
NA
RMU
Full configuration
NA
EMU
Full configuration
NA
CMU
Full configuration
CMU_OUT0, CMU_OUT1
WDOG
Full configuration
NA
PRS
Full configuration
NA
EBI
Full configuration
EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0],
EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC,
EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn
I2C0
Full configuration
I2C0_SDA, I2C0_SCL
I2C1
Full configuration
I2C1_SDA, I2C1_SCL
USART0
Full configuration with IrDA
US0_TX, US0_RX. US0_CLK, US0_CS
USART1
Full configuration with I2S
US1_TX, US1_RX, US1_CLK, US1_CS
USART2
Full configuration with I2S
US2_TX, US2_RX, US2_CLK, US2_CS
UART0
Full configuration
U0_TX, U0_RX
UART1
Full configuration
U1_TX, U1_RX
LEUART0
Full configuration
LEU0_TX, LEU0_RX
LEUART1
Full configuration
LEU1_TX, LEU1_RX
TIMER0
Full configuration with DTI
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1
Full configuration
TIM1_CC[2:0]
TIMER2
Full configuration
TIM2_CC[2:0]
TIMER3
Full configuration
TIM3_CC[2:0]
RTC
Full configuration
NA
BURTC
Full configuration
NA
LETIMER0
Full configuration
LET0_O[1:0]
PCNT0
Full configuration, 16-bit count register
PCNT0_S[1:0]
PCNT1
Full configuration, 8-bit count register
PCNT1_S[1:0]
PCNT2
Full configuration, 8-bit count register
PCNT2_S[1:0]
ACMP0
Full configuration
ACMP0_CH[7:0], ACMP0_O
ACMP1
Full configuration
ACMP1_CH[7:0], ACMP1_O
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Rev. 2.0 | 45
EFM32GG Data Sheet
System Summary
Module
Configuration
Pin Connections
VCMP
Full configuration
NA
ADC0
Full configuration
ADC0_CH[7:0]
DAC0
Full configuration
DAC0_OUT[1:0], DAC0_OUTxALT
OPAMP
Full configuration
Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,
OPAMP_Nx
AES
Full configuration
NA
GPIO
93 pins
Available pins are shown in 5.15.3 GPIO Pinout Overview
LCD
Full configuration
LCD_SEG[35:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N,
LCD_BEXT
silabs.com | Building a more connected world.
Rev. 2.0 | 46
EFM32GG Data Sheet
System Summary
3.2.16 EFM32GG900
The features of the EFM32GG900 is a subset of the feature set described in the EFM32GG Reference Manual. The following table
describes device specific implementation of the features.
Table 3.16. EFM32GG900 Configuration Summary
Module
Configuration
Pin Connections
Cortex-M3 Full configuration
NA
DBG
Full configuration
DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC
Full configuration
NA
DMA
Full configuration
NA
RMU
Full configuration
NA
EMU
Full configuration
NA
CMU
Full configuration
CMU_OUT0, CMU_OUT1
WDOG
Full configuration
NA
PRS
Full configuration
NA
USB
Full configuration
USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM,
USB_DMPU, USB_DP, USB_ID
EBI
Full configuration
EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0], EBI_CS[3:0],
EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC, EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn
I2C0
Full configuration
I2C0_SDA, I2C0_SCL
I2C1
Full configuration
I2C1_SDA, I2C1_SCL
USART0
Full configuration with IrDA
US0_TX, US0_RX. US0_CLK, US0_CS
USART1
Full configuration with I2S
US1_TX, US1_RX, US1_CLK, US1_CS
USART2
Full configuration with I2S
US2_TX, US2_RX, US2_CLK, US2_CS
UART0
Full configuration
U0_TX, U0_RX
UART1
Full configuration
U1_TX, U1_RX
LEUART0
Full configuration
LEU0_TX, LEU0_RX
LEUART1
Full configuration
LEU1_TX, LEU1_RX
TIMER0
Full configuration with DTI
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1
Full configuration
TIM1_CC[2:0]
TIMER2
Full configuration
TIM2_CC[2:0]
TIMER3
Full configuration
TIM3_CC[2:0]
RTC
Full configuration
NA
BURTC
Full configuration
NA
LETIMER0 Full configuration
LET0_O[1:0]
PCNT0
Full configuration, 16-bit count register PCNT0_S[1:0]
PCNT1
Full configuration, 8-bit count register
PCNT1_S[1:0]
PCNT2
Full configuration, 8-bit count register
PCNT2_S[1:0]
ACMP0
Full configuration
ACMP0_CH[7:0], ACMP0_O
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Rev. 2.0 | 47
EFM32GG Data Sheet
System Summary
Module
Configuration
Pin Connections
ACMP1
Full configuration
ACMP1_CH[7:0], ACMP1_O
VCMP
Full configuration
NA
ADC0
Full configuration
ADC0_CH[7:0]
DAC0
Full configuration
DAC0_OUT[1:0], DAC0_OUTxALT
OPAMP
Full configuration
Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx
AES
Full configuration
NA
GPIO
93 pins
Available pins are shown in 5.16.3 GPIO Pinout Overview
LCD
Full configuration
LCD_SEG[35:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N, LCD_BEXT
silabs.com | Building a more connected world.
Rev. 2.0 | 48
EFM32GG Data Sheet
System Summary
3.2.17 EFM32GG940
The features of the EFM32GG940 is a subset of the feature set described in the EFM32GG Reference Manual. The following table
describes device specific implementation of the features.
Table 3.17. EFM32GG940 Configuration Summary
Module
Configuration
Pin Connections
Cortex-M3
Full configuration
NA
DBG
Full configuration
DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC
Full configuration
NA
DMA
Full configuration
NA
RMU
Full configuration
NA
EMU
Full configuration
NA
CMU
Full configuration
CMU_OUT0, CMU_OUT1
WDOG
Full configuration
NA
PRS
Full configuration
NA
USB
Full configuration
USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM,
USB_DMPU, USB_DP, USB_ID
I2C0
Full configuration
I2C0_SDA, I2C0_SCL
I2C1
Full configuration
I2C1_SDA, I2C1_SCL
USART0
Full configuration with IrDA
US0_TX, US0_RX. US0_CLK, US0_CS
USART1
Full configuration with I2S
US1_TX, US1_RX, US1_CLK, US1_CS
USART2
Full configuration with I2S
US2_TX, US2_RX, US2_CLK, US2_CS
LEUART0
Full configuration
LEU0_TX, LEU0_RX
LEUART1
Full configuration
LEU1_TX, LEU1_RX
TIMER0
Full configuration with DTI
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1
Full configuration
TIM1_CC[2:0]
TIMER2
Full configuration
TIM2_CC[2:0]
TIMER3
Full configuration
TIM3_CC[2:0]
RTC
Full configuration
NA
BURTC
Full configuration
NA
LETIMER0
Full configuration
LET0_O[1:0]
PCNT0
Full configuration, 16-bit count register
PCNT0_S[1:0]
PCNT1
Full configuration, 8-bit count register
PCNT1_S[1:0]
PCNT2
Full configuration, 8-bit count register
PCNT2_S[1:0]
ACMP0
Full configuration
ACMP0_CH[7:0], ACMP0_O
ACMP1
Full configuration
ACMP1_CH[7:0], ACMP1_O
VCMP
Full configuration
NA
ADC0
Full configuration
ADC0_CH[7:0]
DAC0
Full configuration
DAC0_OUT[1:0], DAC0_OUTxALT
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Rev. 2.0 | 49
EFM32GG Data Sheet
System Summary
Module
Configuration
Pin Connections
OPAMP
Full configuration
Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,
OPAMP_Nx
AES
Full configuration
NA
GPIO
52 pins
Available pins are shown in 5.17.3 GPIO Pinout Overview
LCD
Full configuration
LCD_SEG[17:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N,
LCD_BEXT
silabs.com | Building a more connected world.
Rev. 2.0 | 50
EFM32GG Data Sheet
System Summary
3.2.18 EFM32GG942
The features of the EFM32GG942 is a subset of the feature set described in the EFM32GG Reference Manual. The following table
device specific implementation of the features.
Table 3.18. EFM32GG942 Configuration Summary
Module
Configuration
Pin Connections
Cortex-M3
Full configuration
NA
DBG
Full configuration
DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC
Full configuration
NA
DMA
Full configuration
NA
RMU
Full configuration
NA
EMU
Full configuration
NA
CMU
Full configuration
CMU_OUT0, CMU_OUT1
WDOG
Full configuration
NA
PRS
Full configuration
NA
USB
Full configuration
USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM,
USB_DMPU, USB_DP, USB_ID
I2C0
Full configuration
I2C0_SDA, I2C0_SCL
I2C1
Full configuration
I2C1_SDA, I2C1_SCL
USART0
Full configuration with IrDA
US0_TX, US0_RX. US0_CLK, US0_CS
USART1
Full configuration with I2S
US1_TX, US1_RX, US1_CLK, US1_CS
USART2
Full configuration with I2S
US2_TX, US2_RX, US2_CLK, US2_CS
LEUART0
Full configuration
LEU0_TX, LEU0_RX
LEUART1
Full configuration
LEU1_TX, LEU1_RX
TIMER0
Full configuration with DTI
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1
Full configuration
TIM1_CC[2:0]
TIMER2
Full configuration
TIM2_CC[2:0]
TIMER3
Full configuration
TIM3_CC[2:0]
RTC
Full configuration
NA
BURTC
Full configuration
NA
LETIMER0
Full configuration
LET0_O[1:0]
PCNT0
Full configuration, 16-bit count register
PCNT0_S[1:0]
PCNT1
Full configuration, 8-bit count register
PCNT1_S[1:0]
PCNT2
Full configuration, 8-bit count register
PCNT2_S[1:0]
ACMP0
Full configuration
ACMP0_CH[3:0], ACMP0_O
ACMP1
Full configuration
ACMP1_CH[0], ACMP1_O
VCMP
Full configuration
NA
ADC0
Full configuration
ADC0_CH[7:0]
DAC0
Full configuration
DAC0_OUT[1:0], DAC0_OUTxALT
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Rev. 2.0 | 51
EFM32GG Data Sheet
System Summary
Module
Configuration
Pin Connections
OPAMP
Full configuration
Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,
OPAMP_Nx
AES
Full configuration
NA
GPIO
50 pins
Available pins are shown in 5.18.3 GPIO Pinout Overview
LCD
Full configuration
LCD_SEG[15:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N,
LCD_BEXT
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EFM32GG Data Sheet
System Summary
3.2.19 EFM32GG980
The features of the EFM32GG980 is a subset of the feature set described in the EFM32GG Reference Manual. The following table
describes device specific implementation of the features.
Table 3.19. EFM32GG980 Configuration Summary
Module
Configuration
Pin Connections
Cortex-M3
Full configuration
NA
DBG
Full configuration
DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC
Full configuration
NA
DMA
Full configuration
NA
RMU
Full configuration
NA
EMU
Full configuration
NA
CMU
Full configuration
CMU_OUT0, CMU_OUT1
WDOG
Full configuration
NA
PRS
Full configuration
NA
USB
Full configuration
USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM,
USB_DMPU, USB_DP, USB_ID
EBI
Full configuration
EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0],
EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC,
EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn
I2C0
Full configuration
I2C0_SDA, I2C0_SCL
I2C1
Full configuration
I2C1_SDA, I2C1_SCL
USART0
Full configuration with IrDA
US0_TX, US0_RX. US0_CLK, US0_CS
USART1
Full configuration with I2S
US1_TX, US1_RX, US1_CLK, US1_CS
USART2
Full configuration with I2S
US2_TX, US2_RX, US2_CLK, US2_CS
UART0
Full configuration
U0_TX, U0_RX
UART1
Full configuration
U1_TX, U1_RX
LEUART0
Full configuration
LEU0_TX, LEU0_RX
LEUART1
Full configuration
LEU1_TX, LEU1_RX
TIMER0
Full configuration with DTI
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1
Full configuration
TIM1_CC[2:0]
TIMER2
Full configuration
TIM2_CC[2:0]
TIMER3
Full configuration
TIM3_CC[2:0]
RTC
Full configuration
NA
BURTC
Full configuration
NA
LETIMER0
Full configuration
LET0_O[1:0]
PCNT0
Full configuration, 16-bit count register
PCNT0_S[1:0]
PCNT1
Full configuration, 8-bit count register
PCNT1_S[1:0]
PCNT2
Full configuration, 8-bit count register
PCNT2_S[1:0]
ACMP0
Full configuration
ACMP0_CH[7:0], ACMP0_O
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EFM32GG Data Sheet
System Summary
Module
Configuration
Pin Connections
ACMP1
Full configuration
ACMP1_CH[7:0], ACMP1_O
VCMP
Full configuration
NA
ADC0
Full configuration
ADC0_CH[7:0]
DAC0
Full configuration
DAC0_OUT[1:0], DAC0_OUTxALT
OPAMP
Full configuration
Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,
OPAMP_Nx
AES
Full configuration
NA
GPIO
81 pins
Available pins are shown in 5.19.3 GPIO Pinout Overview
LCD
Full configuration
LCD_SEG[33:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N,
LCD_BEXT
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EFM32GG Data Sheet
System Summary
3.2.20 EFM32GG990
The features of the EFM32GG990 is a subset of the feature set described in the EFM32GG Reference Manual. The following table
describes device specific implementation of the features.
Table 3.20. EFM32GG990 Configuration Summary
Module
Configuration
Pin Connections
Cortex-M3
Full configuration
NA
DBG
Full configuration
DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC
Full configuration
NA
DMA
Full configuration
NA
RMU
Full configuration
NA
EMU
Full configuration
NA
CMU
Full configuration
CMU_OUT0, CMU_OUT1
WDOG
Full configuration
NA
PRS
Full configuration
NA
USB
Full configuration
USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM,
USB_DMPU, USB_DP, USB_ID
EBI
Full configuration
EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0],
EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC,
EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn
I2C0
Full configuration
I2C0_SDA, I2C0_SCL
I2C1
Full configuration
I2C1_SDA, I2C1_SCL
USART0
Full configuration with IrDA
US0_TX, US0_RX. US0_CLK, US0_CS
USART1
Full configuration with I2S
US1_TX, US1_RX, US1_CLK, US1_CS
USART2
Full configuration with I2S
US2_TX, US2_RX, US2_CLK, US2_CS
UART0
Full configuration
U0_TX, U0_RX
UART1
Full configuration
U1_TX, U1_RX
LEUART0
Full configuration
LEU0_TX, LEU0_RX
LEUART1
Full configuration
LEU1_TX, LEU1_RX
TIMER0
Full configuration with DTI
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1
Full configuration
TIM1_CC[2:0]
TIMER2
Full configuration
TIM2_CC[2:0]
TIMER3
Full configuration
TIM3_CC[2:0]
RTC
Full configuration
NA
BURTC
Full configuration
NA
LETIMER0
Full configuration
LET0_O[1:0]
PCNT0
Full configuration, 16-bit count register
PCNT0_S[1:0]
PCNT1
Full configuration, 8-bit count register
PCNT1_S[1:0]
PCNT2
Full configuration, 8-bit count register
PCNT2_S[1:0]
ACMP0
Full configuration
ACMP0_CH[7:0], ACMP0_O
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EFM32GG Data Sheet
System Summary
Module
Configuration
Pin Connections
ACMP1
Full configuration
ACMP1_CH[7:0], ACMP1_O
VCMP
Full configuration
NA
ADC0
Full configuration
ADC0_CH[7:0]
DAC0
Full configuration
DAC0_OUT[1:0], DAC0_OUTxALT
OPAMP
Full configuration
Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,
OPAMP_Nx
AES
Full configuration
NA
GPIO
86 pins
Available pins are shown in 5.20.3 GPIO Pinout Overview
LCD
Full configuration
LCD_SEG[33:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N,
LCD_BEXT
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EFM32GG Data Sheet
System Summary
3.2.21 EFM32GG995
The features of the EFM32GG995 is a subset of the feature set described in the EFM32GG Reference Manual. The following table
describes device specific implementation of the features.
Table 3.21. EFM32GG995 Configuration Summary
Module
Configuration
Pin Connections
Cortex-M3
Full configuration
NA
DBG
Full configuration
DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC
Full configuration
NA
DMA
Full configuration
NA
RMU
Full configuration
NA
EMU
Full configuration
NA
CMU
Full configuration
CMU_OUT0, CMU_OUT1
WDOG
Full configuration
NA
PRS
Full configuration
NA
USB
Full configuration
USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM,
USB_DMPU, USB_DP, USB_ID
EBI
Full configuration
EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0],
EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC,
EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn
I2C0
Full configuration
I2C0_SDA, I2C0_SCL
I2C1
Full configuration
I2C1_SDA, I2C1_SCL
USART0
Full configuration with IrDA
US0_TX, US0_RX. US0_CLK, US0_CS
USART1
Full configuration with I2S
US1_TX, US1_RX, US1_CLK, US1_CS
USART2
Full configuration with I2S
US2_TX, US2_RX, US2_CLK, US2_CS
UART0
Full configuration
U0_TX, U0_RX
UART1
Full configuration
U1_TX, U1_RX
LEUART0
Full configuration
LEU0_TX, LEU0_RX
LEUART1
Full configuration
LEU1_TX, LEU1_RX
TIMER0
Full configuration with DTI
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1
Full configuration
TIM1_CC[2:0]
TIMER2
Full configuration
TIM2_CC[2:0]
TIMER3
Full configuration
TIM3_CC[2:0]
RTC
Full configuration
NA
BURTC
Full configuration
NA
LETIMER0
Full configuration
LET0_O[1:0]
PCNT0
Full configuration, 16-bit count register
PCNT0_S[1:0]
PCNT1
Full configuration, 8-bit count register
PCNT1_S[1:0]
PCNT2
Full configuration, 8-bit count register
PCNT2_S[1:0]
ACMP0
Full configuration
ACMP0_CH[7:0], ACMP0_O
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EFM32GG Data Sheet
System Summary
Module
Configuration
Pin Connections
ACMP1
Full configuration
ACMP1_CH[7:0], ACMP1_O
VCMP
Full configuration
NA
ADC0
Full configuration
ADC0_CH[7:0]
DAC0
Full configuration
DAC0_OUT[1:0], DAC0_OUTxALT
OPAMP
Full configuration
Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,
OPAMP_Nx
AES
Full configuration
NA
GPIO
93 pins
Available pins are shown in 5.21.3 GPIO Pinout Overview
LCD
Full configuration
LCD_SEG[35:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N,
LCD_BEXT
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EFM32GG Data Sheet
System Summary
3.3 Memory Map
The EFM32GG memory map is shown in the following figure, with RAM and Flash sizes for the largest memory configuration.
Figure 3.2. System Address Space with Core and Code Space Listing
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EFM32GG Data Sheet
System Summary
Figure 3.3. System Address Space with Peripheral Listing
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EFM32GG Data Sheet
Electrical Characteristics
4. Electrical Characteristics
4.1 Test Conditions
4.1.1 Typical Values
The typical data are based on TAMB=25°C and VDD=3.0 V, as defined in 4.3 General Operating Conditions, unless otherwise specified.
4.1.2 Minimum and Maximum Values
The minimum and maximum values represent the worst conditions of ambient temperature, supply voltage and frequencies, as defined
in 4.3 General Operating Conditions, unless otherwise specified.
4.2 Absolute Maximum Ratings
The absolute maximum ratings are stress ratings, and functional operation under such conditions are not guaranteed. Stress beyond
the limits specified in the following table may affect the device reliability or cause permanent damage to the device. Functional operating conditions are given in 4.3 General Operating Conditions.
Table 4.1. Absolute Maximum Ratings
Parameter
Symbol
Storage temperature range
TSTG
Maximum soldering temperature
TS
External main supply voltage
VDDMAX
Voltage on any I/O pin
VIOPIN
Current per I/O pin (sink)
Current per I/O pin (source)
Test Condition
Min
Typ
Max
Unit
-40
—
150
°C
—
—
260
°C
0
—
3.8
V
-0.3
—
VDD+0.3
V
IIOMAX_SINK
—
—
100
mA
IIOMAX_SOURCE
—
—
-100
mA
Latest IPC/JEDEC JSTD-020 Standard
4.3 General Operating Conditions
Table 4.2. General Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Ambient temperature range
TAMB
-40
—
85
°C
Operating supply voltage
VDDOP
1.98
—
3.8
V
Internal APB clock frequency
fAPB
—
—
48
MHz
Internal AHB clock frequency
fAHB
—
—
48
MHz
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EFM32GG Data Sheet
Electrical Characteristics
4.4 Current Consumption
Table 4.3. Current Consumption
Parameter
Symbol
EM0 current. No prescaling.
IEM0
Running prime num-ber calculation code from flash. (Production test condition = 14MHz)
EM1 current (Production test
condition = 14MHz)
EM2 current
EM3 current
EM4 current
IEM1
IEM2
IEM3
IEM4
Test Condition
Min
Typ
Max
Unit
48 MHz HFXO, all peripheral clocks disabled, VDD= 3.0 V
—
219
240
µA/MHz
28 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V
—
205
225
µA/MHz
21 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V
—
206
229
µA/MHz
14 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V
—
209
232
µA/MHz
11 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V
—
211
234
µA/MHz
6.6 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V
—
215
242
µA/MHz
1.2 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V
—
243
327
µA/MHz
48 MHz HFXO, all peripheral clocks disabled, VDD= 3.0 V
—
80
90
µA/MHz
28 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V
—
80
90
µA/MHz
21 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V
—
81
91
µA/MHz
14 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V
—
83
99
µA/MHz
11 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V
—
85
100
µA/MHz
6.6 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V
—
90
102
µA/MHz
1.2 MHz HFRCO. all peripheral clocks disabled, VDD= 3.0 V
—
122
152
µA/MHz
EM2 current with RTC prescaled to 1 Hz,
32.768 kHz LFRCO, VDD= 3.0 V,
TAMB=25ºC
—
1.11
1.91
µA
EM2 current with RTC prescaled to 1 Hz,
32.768 kHz LFRCO, VDD= 3.0 V,
TAMB=85ºC
—
8.81
21.51
µA
VDD= 3.0 V, TAMB=25ºC
—
0.81
1.51
µA
VDD= 3.0 V, TAMB=85ºC
—
8.21
20.31
µA
VDD= 3.0 V, TAMB=25ºC
—
0.02
0.08
µA
VDD= 3.0 V, TAMB=85ºC
—
0.5
2.5
µA
Note:
1. Only one RAM block enabled. The RAM block size is 32 kB.
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EFM32GG Data Sheet
Electrical Characteristics
4.4.1 EM1 Current Consumption
3.10
3.10
3.05
3.05
Idd [mA]
3.15
Idd [mA]
3.15
3.00
3.00
-40°C
-15°C
5°C
25°C
45°C
65°C
85°C
2.95
2.90
2.0
2.0V
2.2V
2.4V
2.6V
2.8V
3.0V
3.2V
3.4V
3.6V
3.8V
2.2
2.4
2.6
2.8
3.0
Vdd [V]
3.2
3.4
3.6
2.95
2.90
–40
3.8
–15
5
25
Temperature [°C]
45
65
85
Figure 4.1. EM1 Current consumption with all peripheral clocks disabled and HFXO running at 48 MHz
1.80
1.80
1.75
1.75
Idd [mA]
1.85
Idd [mA]
1.85
1.70
1.70
-40°C
-15°C
5°C
25°C
45°C
65°C
85°C
1.65
1.60
2.0
2.0V
2.2V
2.4V
2.6V
2.8V
3.0V
3.2V
3.4V
3.6V
3.8V
2.2
2.4
2.6
2.8
3.0
Vdd [V]
3.2
3.4
3.6
1.65
3.8
1.60
–40
–15
5
25
Temperature [°C]
45
65
85
Figure 4.2. EM1 Current Consumption with all Peripheral Clocks Disabled and HFRCO Running at 28 MHz
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EFM32GG Data Sheet
1.42
1.42
1.40
1.40
1.38
1.38
1.36
1.36
1.34
1.34
Idd [mA]
Idd [mA]
Electrical Characteristics
1.32
-40°C
-15°C
5°C
25°C
45°C
65°C
85°C
1.30
1.28
1.26
1.24
2.0
2.2
2.4
2.6
2.8
3.0
Vdd [V]
3.2
3.4
3.6
2.0V
2.2V
2.4V
2.6V
2.8V
3.0V
3.2V
3.4V
3.6V
3.8V
1.32
1.30
1.28
1.26
1.24
–40
3.8
–15
5
25
Temperature [°C]
45
65
85
0.98
0.98
0.96
0.96
0.94
0.94
Idd [mA]
Idd [mA]
Figure 4.3. EM1 Current Consumption with all Peripheral Clocks Disabled and HFRCO Running at 21 MHz
0.92
-40°C
-15°C
5°C
25°C
45°C
65°C
85°C
0.90
0.88
0.86
2.0
2.2
2.4
2.6
2.8
3.0
Vdd [V]
3.2
3.4
3.6
2.0V
2.2V
2.4V
2.6V
2.8V
3.0V
3.2V
3.4V
3.6V
3.8V
0.92
0.90
0.88
3.8
0.86
–40
–15
5
25
Temperature [°C]
45
65
85
Figure 4.4. EM1 Current Consumption with all Peripheral Clocks Disabled and HFRCO Running at 14 MHz
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EFM32GG Data Sheet
0.78
0.78
0.76
0.76
Idd [mA]
Idd [mA]
Electrical Characteristics
0.74
-40°C
-15°C
5°C
25°C
45°C
65°C
85°C
0.72
0.70
2.0
2.2
2.4
2.6
2.8
3.0
Vdd [V]
3.2
3.4
3.6
2.0V
2.2V
2.4V
2.6V
2.8V
3.0V
3.2V
3.4V
3.6V
3.8V
0.74
0.72
0.70
3.8
–40
–15
5
25
Temperature [°C]
45
65
85
0.52
0.52
0.51
0.51
0.50
0.50
0.49
0.49
Idd [mA]
Idd [mA]
Figure 4.5. EM1 Current Consumption with all Peripheral Clocks Disabled and HFRCO Running at 11 MHz
0.48
-40°C
-15°C
5°C
25°C
45°C
65°C
85°C
0.47
0.46
0.45
2.0
2.2
2.4
2.6
2.8
3.0
Vdd [V]
3.2
3.4
3.6
2.0V
2.2V
2.4V
2.6V
2.8V
3.0V
3.2V
3.4V
3.6V
3.8V
0.48
0.47
0.46
3.8
0.45
–40
–15
5
25
Temperature [°C]
45
65
85
Figure 4.6. EM1 Current Consumption with all Peripheral Clocks Disabled and HFRCO Running at 6.6 MHz
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EFM32GG Data Sheet
Electrical Characteristics
0.160
0.138
-40°C
-15°C
5°C
25°C
45°C
65°C
85°C
0.136
0.134
0.150
0.145
Idd [mA]
Idd [mA]
0.132
0.155
0.130
0.140
2.0V
2.2V
2.4V
2.6V
2.8V
3.0V
3.2V
3.4V
3.6V
3.8V
0.135
0.128
0.130
0.126
0.125
0.124
0.122
2.0
0.120
2.2
2.4
2.6
2.8
3.0
Vdd [V]
3.2
3.4
3.6
3.8
0.115
–40
–15
5
25
Temperature [°C]
45
65
85
4.4.2 EM2 Current Consumption
3.5
3.5
-40.0°C
-15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
3.0
2.5
Idd [uA]
Idd [uA]
2.5
3.0
2.0
2.0
1.5
1.5
1.0
1.0
0.5
2.0
2.2
2.4
2.6
2.8
3.0
Vdd [V]
3.2
3.4
3.6
3.8
0.5
–40
Vdd=2.0V
Vdd=2.2V
Vdd=2.4V
Vdd=2.6V
Vdd=2.8V
Vdd=3.0V
Vdd=3.2V
Vdd=3.4V
Vdd=3.6V
Vdd=3.8V
–20
0
20
40
Temperature [°C]
60
80
Figure 4.7. EM2 Current Consumption, RTC prescaled to 1 kHz, 32.768 kHz LFRCO
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EFM32GG Data Sheet
Electrical Characteristics
4.4.3 EM3 Current Consumption
3.0
3.0
-40.0°C
-15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
2.5
2.0
Idd [uA]
Idd [uA]
2.0
2.5
1.5
1.5
1.0
1.0
0.5
0.5
0.0
2.0
2.2
2.4
2.6
2.8
3.0
Vdd [V]
3.2
3.4
3.6
0.0
–40
3.8
Vdd=2.0V
Vdd=2.2V
Vdd=2.4V
Vdd=2.6V
Vdd=2.8V
Vdd=3.0V
Vdd=3.2V
Vdd=3.4V
Vdd=3.6V
Vdd=3.8V
–20
0
20
40
Temperature [°C]
60
80
0
20
40
Temperature [°C]
60
80
Figure 4.8. EM3 Current Consumption
4.4.4 EM4 Current Consumption
0.7
0.6
0.6
0.5
0.4
Idd [uA]
Idd [uA]
0.5
0.7
-40.0°C
-15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
0.3
0.4
0.3
0.2
0.2
0.1
0.1
0.0
2.0
2.2
2.4
2.6
2.8
3.0
Vdd [V]
3.2
3.4
3.6
3.8
Vdd=2.0V
Vdd=2.2V
Vdd=2.4V
Vdd=2.6V
Vdd=2.8V
Vdd=3.0V
Vdd=3.2V
Vdd=3.4V
Vdd=3.6V
Vdd=3.8V
0.0
–40
–20
Figure 4.9. EM4 Current Consumption
silabs.com | Building a more connected world.
Rev. 2.0 | 67
EFM32GG Data Sheet
Electrical Characteristics
4.5 Transition between Energy Modes
The transition times are measured from the trigger to the first clock edge in the CPU.
Table 4.4. Energy Modes Transitions
Parameter
Symbol
Min
Typ
Max
Unit
Transition time from EM1 to EM0
tEM10
—
0
—
HFCORECLK cycles
Transition time from EM2 to EM0
tEM20
—
2
—
µs
Transition time from EM3 to EM0
tEM30
—
2
—
µs
Transition time from EM4 to EM0
tEM40
—
163
—
µs
4.6 Power Management
The EFM32GG requires the AVDD_x, VDD_DREG and IOVDD_x pins to be connected together (with optional filter) at the PCB level.
For practical schematic recommendations, please see the application note AN0002 EFM32 Hardware Design Considerations.
Table 4.5. Power Management
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
BOD threshold on falling external supply voltage
VBODextthr-
EM0
1.74
—
1.96
V
EM2
1.74
—
1.98
V
BOD threshold on falling internally regulated supply voltage
VBODintthr-
1.57
—
1.70
V
BOD threshold on rising external supply voltage
VBODextthr+
—
1.85
1.98
V
Power-on Reset (POR) threshold on rising external supply
voltage
VPORthr+
—
—
1.98
V
Delay from reset is released un- tRESET
til program execution starts
Applies to Power-on Reset, Brownout Reset and pin reset.
—
163
—
µs
Voltage regulator decoupling
capacitor.
CDECOUPLE
X5R capacitor recommended. Apply
between DECOUPLE pin and
GROUND
—
1
—
µF
USB voltage regulator out decoupling capacitor.
CUSB_VREGO
X5R capacitor recommended. Apply
between USB_VREGO pin and
GROUND
—
1
—
µF
X5R capacitor recommended. Apply
between USB_VREGI pin and
GROUND
—
4.7
—
µF
USB voltage regulator in decou- CUSB_VREGI
pling capacitor.
silabs.com | Building a more connected world.
Rev. 2.0 | 68
EFM32GG Data Sheet
Electrical Characteristics
4.7 Flash
Table 4.6. Flash
Parameter
Symbol
Flash erase cycles before failure
ECFLASH
Flash word write cycles between erase
WWCFLASH
Flash data retention
RETFLASH
Test Condition
Min
Typ
Max
Unit
20000
—
—
cycles
—
—
21
cycles
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