EFM32 Gecko Family
EFM32JG12 Family Data Sheet
The EFM32 Gecko MCUs are the world’s most energy-friendly microcontrollers.
ENERGY FRIENDLY FEATURES
• ARM Cortex-M3 at 40 MHz
EFM32JG12 features a powerful 32-bit ARM® Cortex®-M3 and a wide selection of peripherals, including a unique cryptographic hardware engine and Security Management
Unit, True Random Number Generator, and robust capacitive touch sense unit. These
features, combined with ultra-low current active and sleep modes, make EFM32JG12 microcontrollers well suited for any battery-powered application, as well as other systems
requiring high performance and low energy consumption.
• Ultra low energy operation:
• 0.39 μA EM4H Hibernate current
• 1.5 μA EM2 Deep Sleep current (RTCC
running with state and RAM retention)
• 64 μA/MHz EM0 Active current
• Hardware cryptographic engine (AES,
ECC, and SHA) and TRNG
Example applications:
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• Security Management Unit (SMU)
IoT devices and sensors
Health and fitness
Smart accessories
Home automation and security
Industrial and factory automation
• Autonomous low energy sensor interface
(LESENSE)
• Rich analog features including ADC,
VDAC, OPAMPs, and capacitive sense
• Integrated DC-DC converter
• 5 V tolerant I/O
Core / Memory
ARM CortexTM M3 processor with
Memory Protection Unit
ETM
Debug Interface
Clock Management
Flash Program
Memory
RAM Memory
LDMA
Controller
Energy Management
High Frequency
Crystal
Oscillator
High Frequency
RC Oscillator
with DPLL
Voltage
Regulator
Voltage Monitor
Auxiliary High
Frequency RC
Oscillator
Low Frequency
RC Oscillator
DC-DC
Converter
Power-On Reset
Low Frequency
Crystal
Oscillator
Ultra Low
Frequency RC
Oscillator
Brown-Out
Detector
32-bit bus
Peripheral Reflex System
Serial Interfaces
I/O Ports
USART
External Interrupts
Low Energy Timer
Analog Interfaces
ADC
Other
CRYPTO
Analog Comparator
Pulse Counter
Pin Reset
Watchdog Timer
Real Time Counter
and Calendar
Pin Wakeup
CRYOTIMER
General Purpose I/O
IC
Timer/Counter
Low Energy Sensor
Interface
Low Energy UARTTM
2
Timers and Triggers
IDAC
CRC
Capacitive Sense
True Random
Number Generator
VDAC
Op-Amp
SMU
Lowest power mode with peripheral operational:
EM0 - Active
EM1 - Sleep
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EM2 – Deep Sleep
EM3 - Stop
EM4 - Hibernate
EM4 - Shutoff
Rev. 1.2
EFM32JG12 Family Data Sheet
Feature List
1. Feature List
The EFM32JG12 highlighted features are listed below.
• ARM Cortex-M3 CPU platform
• High performance 32-bit processor @ up to 40 MHz
• Memory Protection Unit
• Wake-up Interrupt Controller
• Flexible Energy Management System
• 64 μA/MHz in Active Mode (EM0)
• 2.1 μA EM2 Deep Sleep current (256 kB RAM retention and
RTCC running from LFXO)
• 1.5 μA EM2 Deep Sleep current (16 kB RAM retention and
RTCC running from LFRCO)
• 1.81 μA EM3 Stop current (State and 256 kB RAM retention, CRYOTIMER running from ULFRCO)
• 0.39 μA EM4H Hibernate Mode (128 byte RAM retention)
• Up to 1024 kB flash program memory
• Dual-bank with read-while-write support
• Up to 256 kB RAM data memory
• Up to 65 General Purpose I/O Pins
• Configurable push-pull, open-drain, pull-up/down, input filter, drive strength
• Configurable peripheral I/O locations
• Asynchronous external interrupts
• Output state retention and wake-up from Shutoff Mode
• Hardware Cryptography
• AES 128/256-bit keys
• ECC B/K163, B/K233, P192, P224, P256
• SHA-1 and SHA-2 (SHA-224 and SHA-256)
• True random number generator (TRNG)
• Security Management Unit (SMU)
• Fine-grained access control for on-chip peripherals
• Timers/Counters
• 2 × 16-bit Timer/Counter
• 3 or 4 Compare/Capture/PWM channels
• 2 × 32-bit Timer/Counter
• 3 or 4 Compare/Capture/PWM channels
• 1 × 32-bit Real Time Counter and Calendar
• 1 × 32-bit Ultra Low Energy CRYOTIMER for periodic wakeup from any Energy Mode
• 16-bit Low Energy Timer for waveform generation
• 3 × 16-bit Pulse Counter with asynchronous operation
• 2 × Watchdog Timer with dedicated RC oscillator
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• 8 Channel DMA Controller
• 12 Channel Peripheral Reflex System (PRS) for autonomous inter-peripheral signaling
• Communication Interfaces
• 4 × Universal Synchronous/Asynchronous Receiver/ Transmitter
• UART/SPI/SmartCard (ISO 7816)/IrDA/I2S/LIN
• Triple buffered full/half-duplex operation with flow control
• Low Energy UART
• Autonomous operation with DMA in Deep Sleep Mode
• 2 × I2C Interface with SMBus support
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• Address recognition in EM3 Stop Mode
Ultra Low-Power Precision Analog Peripherals
• 12-bit 1 Msps SAR Analog to Digital Converter (ADC)
• 2 × Analog Comparator (ACMP)
• 2 × 12-bit 500 ksps Digital to Analog Converter (VDAC)
• 3 × Operational Amplifier (OPAMP)
• Digital to Analog Current Converter (IDAC)
• Multi-channel Capacitive Sense Interface (CSEN)
• Up to 54 pins connected to analog channels (APORT)
shared between analog peripherals
Low-Energy Sensor Interface (LESENSE)
• Autonomous sensor monitoring in deep sleep mode
• Wide range of supported sensors, including LC sensors and
capacitive touch switches
• Up to 16 channels
Ultra efficient Power-on Reset and Brown-Out Detector
Debug Interface
• 2-pin Serial Wire Debug interface
• 1-pin Serial Wire Viewer
• JTAG (programming only)
• Embedded Trace Macrocell (ETM)
Wide Operating Range
• 1.8 V to 3.8 V single power supply
• Integrated DC-DC, down to 1.8 V output with up to 200 mA
load current for system
• Standard (-40 °C to 85 °C TAMB) and Extended (-40 °C to
125 °C TJ) temperature grades available
• Packages
• 7 mm × 7 mm QFN48
• 7 mm × 7 mm BGA125
• Pre-Programmed UART Bootloader
• Full Software Support
• CMSIS register definitions
• Low-power Hardware Abstraction Layer (HAL)
• Portable software components
• Third-party middleware
• Free and available example code
Rev. 1.2 | 2
EFM32JG12 Family Data Sheet
Ordering Information
2. Ordering Information
Table 2.1. Ordering Information
DC-DC
ConRAM (kB) verter
Ordering Code
Flash
(kB)
EFM32JG12B500F1024GL125-C
1024
256
EFM32JG12B500F1024IL125-C
1024
EFM32JG12B500F1024GM48-C
EFM32JG12B500F1024IM48-C
GPIO
Package
Temp Range
Yes
65
BGA125
-40 to +85°C
256
Yes
65
BGA125
-40 to +125°C
1024
256
Yes
33
QFN48
-40 to +85°C
1024
256
Yes
33
QFN48
-40 to +125°C
EFM32 J G 1 2 B 500 F 1024 G M 48 – A R
Tape and Reel (Optional)
Revision
Pin Count
Package – M (QFN)
Temperature Grade – G (-40 to +85 °C), I (-40 to +125 °C)
Flash Memory Size in kB
Memory Type (Flash)
Feature Set Code
Performance Grade – P (Performance), B (Basic), V (Value)
Device Configuration
Series
Gecko
Family – J, P
Energy Friendly Microcontroller 32-bit
Figure 2.1. Ordering Code Key
silabs.com | Building a more connected world.
Rev. 1.2 | 3
Table of Contents
1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Introduction .
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. 7
3.2 Power . . . . . . . . . . .
3.2.1 Energy Management Unit (EMU)
3.2.2 DC-DC Converter . . . . .
3.2.3 Power Domains . . . . . .
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3.3 General Purpose Input/Output (GPIO) .
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. 9
3.4 Clocking . . . . . . . . . .
3.4.1 Clock Management Unit (CMU) .
3.4.2 Internal and External Oscillators.
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. 9
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.10
.10
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.10
3.6 Communications and Other Digital Peripherals . . . . . . . . . .
3.6.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) .
3.6.2 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) .
3.6.3 Inter-Integrated Circuit Interface (I2C) . . . . . . . . . . . .
3.6.4 Peripheral Reflex System (PRS) . . . . . . . . . . . . .
3.6.5 Low Energy Sensor Interface (LESENSE) . . . . . . . . . .
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.10
.10
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.11
3.7 Security Features . . . . . . . . . . . . . .
3.7.1 General Purpose Cyclic Redundancy Check (GPCRC)
3.7.2 Crypto Accelerator (CRYPTO) . . . . . . . .
3.7.3 True Random Number Generator (TRNG) . . . .
3.7.4 Security Management Unit (SMU) . . . . . . .
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.11
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3.8 Analog. . . . . . . . . . . . . .
3.8.1 Analog Port (APORT) . . . . . . .
3.8.2 Analog Comparator (ACMP) . . . . .
3.8.3 Analog to Digital Converter (ADC) . . .
3.8.4 Capacitive Sense (CSEN) . . . . . .
3.8.5 Digital to Analog Current Converter (IDAC)
3.8.6 Digital to Analog Converter (VDAC) . .
3.8.7 Operational Amplifiers . . . . . . .
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.11
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.12
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.12
.12
.12
3.9 Reset Management Unit (RMU) .
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.12
3.10 Core and Memory .
3.10.1 Processor Core .
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.12
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3.5 Counters/Timers and PWM . . . . . . . . .
3.5.1 Timer/Counter (TIMER) . . . . . . . .
3.5.2 Wide Timer/Counter (WTIMER) . . . . . .
3.5.3 Real Time Counter and Calendar (RTCC) . .
3.5.4 Low Energy Timer (LETIMER) . . . . . .
3.5.5 Ultra Low Power Wake-up Timer (CRYOTIMER)
3.5.6 Pulse Counter (PCNT) . . . . . . . . .
3.5.7 Watchdog Timer (WDOG) . . . . . . . .
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silabs.com | Building a more connected world.
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8
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8
Rev. 1.2 | 4
3.10.2 Memory System Controller (MSC) . . . . .
3.10.3 Linked Direct Memory Access Controller (LDMA)
3.10.4 Bootloader . . . . . . . . . . . . .
3.11 Memory Map .
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.14
3.12 Configuration Summary
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.16
4. Electrical Specifications
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4.1 Electrical Characteristics . . . . . . . .
4.1.1 Absolute Maximum Ratings . . . . . .
4.1.2 Operating Conditions . . . . . . . .
4.1.3 Thermal Characteristics . . . . . . .
4.1.4 DC-DC Converter . . . . . . . . .
4.1.5 Current Consumption . . . . . . . .
4.1.6 Wake Up Times . . . . . . . . . .
4.1.7 Brown Out Detector (BOD) . . . . . .
4.1.8 Oscillators . . . . . . . . . . . .
4.1.9 Flash Memory Characteristics . . . . .
4.1.10 General-Purpose I/O (GPIO) . . . . .
4.1.11 Voltage Monitor (VMON) . . . . . . .
4.1.12 Analog to Digital Converter (ADC) . . .
4.1.13 Analog Comparator (ACMP) . . . . .
4.1.14 Digital to Analog Converter (VDAC) . . .
4.1.15 Current Digital to Analog Converter (IDAC)
4.1.16 Capacitive Sense (CSEN) . . . . . .
4.1.17 Operational Amplifier (OPAMP) . . . .
4.1.18 Pulse Counter (PCNT) . . . . . . .
4.1.19 Analog Port (APORT) . . . . . . . .
4.1.20 I2C . . . . . . . . . . . . . .
4.1.21 USART SPI . . . . . . . . . . .
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4.2 Typical Performance Curves .
4.2.1 Supply Current . . . .
4.2.2 DC-DC Converter . . .
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.58
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.64
5. Typical Connection Diagrams
5.1 Power .
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.66
5.2 Other Connections.
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.66
6. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.1 EFM32JG12B5xx in BGA125 Device Pinout .
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.67
6.2 EFM32JG12B5xx in QFN48 Device Pinout
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.71
6.3 GPIO Functionality Table
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6.4 Alternate Functionality Overview .
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7. BGA125 Package Specifications
7.1 BGA125 Package Dimensions .
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Rev. 1.2 | 5
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8. QFN48 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . 118
8.1 QFN48 Package Dimensions
8.2 QFN48 PCB Land Pattern
8.3 QFN48 Package Marking
9. Revision History
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Rev. 1.2 | 6
EFM32JG12 Family Data Sheet
System Overview
3. System Overview
3.1 Introduction
The EFM32JG12 product family is well suited for any battery operated application as well as other systems requiring high performance
and low energy consumption. This section gives a short introduction to the MCU system. The detailed functional description can be
found in the EFM32JG12 Reference Manual.
A block diagram of the EFM32JG12 family is shown in Figure 3.1 Detailed EFM32JG12 Block Diagram on page 7. The diagram
shows a superset of features available on the family, which vary by OPN. For more information about specific device features, consult
Ordering Information.
Port I/O Configuration
IOVDD
Energy Management
AVDD_1
Digital Peripherals
IOVDD
LETIMER
Voltage
Monitor
AVDD_0
DVDD
TIMER
VREGSW
DC-DC
Converter
PCNT
Voltage
Regulator
Port
Mapper
USART
LEUART
ARM Cortex-M3 Core
Up to 1024 KB ISP Flash
Program Memory
Memory Protection Unit
LDMA Controller
Clock Management
ULFRCO
AUXHFRCO
LFXTAL_N
HFXTAL_P
HFXTAL_N
PBn
Port C
Drivers
PCn
Port D
Drivers
PDn
Port F
Drivers
PFn
Port I
Drivers
PIn
Port J
Drivers
PJn
Port K
Drivers
PKn
CRC
LESENSE
Analog Peripherals
IDAC
VDAC
Internal
Reference
12-bit ADC
LFRCO
LFXO
HFRCO + DPLL
HFXO
Op-Amp
VDD
APORT
Serial Wire
and ETM
Debug /
Programming
A A
H P
B B
Mux & FB
Up to 256 KB RAM
CRYPTO
Input Mux
Reset
Management
Unit
Watchdog
Timer
LFXTAL_P
I2C
+
-
Brown Out /
Power-On
Reset
Debug Signals
(shared w/GPIO)
Port B
Drivers
RTC / RTCC
DECOUPLE
RESETn
PAn
CRYOTIMER
bypass
VREGVDD
Port A
Drivers
Temp
Sense
Capacitive
Sense
+
Analog Comparator
Figure 3.1. Detailed EFM32JG12 Block Diagram
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EFM32JG12 Family Data Sheet
System Overview
3.2 Power
The EFM32JG12 has an Energy Management Unit (EMU) and efficient integrated regulators to generate internal supply voltages. Only
a single external supply voltage is required, from which all internal voltages are created. An optional integrated DC-DC buck regulator
can be utilized to further reduce the current consumption. The DC-DC regulator requires one external inductor and one external capacitor.
The EFM32JG12 device family includes support for internal supply voltage scaling, as well as two different power domains groups for
peripherals. These enhancements allow for further supply current reductions and lower overall power consumption.
AVDD and VREGVDD need to be 1.8 V or higher for the MCU to operate across all conditions; however the rest of the system will
operate down to 1.62 V, including the digital supply and I/O. This means that the device is fully compatible with 1.8 V components.
Running from a sufficiently high supply, the device can use the DC-DC to regulate voltage not only for itself, but also for other PCB
components, supplying up to a total of 200 mA.
3.2.1 Energy Management Unit (EMU)
The Energy Management Unit manages transitions of energy modes in the device. Each energy mode defines which peripherals and
features are available and the amount of current the device consumes. The EMU can also be used to turn off the power to unused RAM
blocks, and it contains control registers for the DC-DC regulator and the Voltage Monitor (VMON). The VMON is used to monitor multiple supply voltages. It has multiple channels which can be programmed individually by the user to determine if a sensed supply has
fallen below a chosen threshold.
3.2.2 DC-DC Converter
The DC-DC buck converter covers a wide range of load currents and provides up to 90% efficiency in energy modes EM0, EM1, EM2
and EM3, and can supply up to 200 mA to the device and surrounding PCB components. Protection features include programmable
current limiting, short-circuit protection, and dead-time protection. The DC-DC converter may also enter bypass mode when the input
voltage is too low for efficient operation. In bypass mode, the DC-DC input supply is internally connected directly to its output through a
low resistance switch. Bypass mode also supports in-rush current limiting to prevent input supply voltage droops due to excessive output current transients.
3.2.3 Power Domains
The EFM32JG12 has two peripheral power domains for operation in EM2 and lower. If all of the peripherals in a peripheral power domain are configured as unused, the power domain for that group will be powered off in the low-power mode, reducing the overall current consumption of the device.
Table 3.1. Peripheral Power Subdomains
Peripheral Power Domain 1
Peripheral Power Domain 2
ACMP0
ACMP1
PCNT0
PCNT1
ADC0
PCNT2
LETIMER0
CSEN
LESENSE
DAC0
APORT
LEUART0
-
I2C0
-
I2C1
-
IDAC
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EFM32JG12 Family Data Sheet
System Overview
3.3 General Purpose Input/Output (GPIO)
EFM32JG12 has up to 65 General Purpose Input/Output pins. Each GPIO pin can be individually configured as either an output or input. More advanced configurations including open-drain, open-source, and glitch-filtering can be configured for each individual GPIO
pin. The GPIO pins can be overridden by peripheral connections, like SPI communication. Each peripheral connection can be routed to
several GPIO pins on the device. The input value of a GPIO pin can be routed through the Peripheral Reflex System to other peripherals. The GPIO subsystem supports asynchronous external pin interrupts.
3.4 Clocking
3.4.1 Clock Management Unit (CMU)
The Clock Management Unit controls oscillators and clocks in the EFM32JG12. Individual enabling and disabling of clocks to all peripherals is performed by the CMU. The CMU also controls enabling and configuration of the oscillators. A high degree of flexibility allows
software to optimize energy consumption in any specific application by minimizing power dissipation in unused peripherals and oscillators.
3.4.2 Internal and External Oscillators
The EFM32JG12 supports two crystal oscillators and fully integrates four RC oscillators, listed below.
• A high frequency crystal oscillator (HFXO) with integrated load capacitors, tunable in small steps, provides a precise timing reference for the MCU. Crystal frequencies in the range from 38 to 40 MHz are supported. An external clock source such as a TCXO can
also be applied to the HFXO input for improved accuracy over temperature.
• A 32.768 kHz crystal oscillator (LFXO) provides an accurate timing reference for low energy modes.
• An integrated high frequency RC oscillator (HFRCO) is available for the MCU system. The HFRCO employs fast startup at minimal
energy consumption combined with a wide frequency range. When crystal accuracy is not required, it can be operated in free-running mode at a number of factory-calibrated frequencies. A digital phase-locked loop (DPLL) feature allows the HFRCO to achieve
higher accuracy and stability by referencing other available clock sources such as LFXO and HFXO.
• An integrated auxilliary high frequency RC oscillator (AUXHFRCO) is available for timing the general-purpose ADC and the Serial
Wire Viewer port with a wide frequency range.
• An integrated low frequency 32.768 kHz RC oscillator (LFRCO) can be used as a timing reference in low energy modes, when crystal accuracy is not required.
• An integrated ultra-low frequency 1 kHz RC oscillator (ULFRCO) is available to provide a timing reference at the lowest energy consumption in low energy modes.
3.5 Counters/Timers and PWM
3.5.1 Timer/Counter (TIMER)
TIMER peripherals keep track of timing, count events, generate PWM outputs and trigger timed actions in other peripherals through the
PRS system. The core of each TIMER is a 16-bit counter with up to 4 compare/capture channels. Each channel is configurable in one
of three modes. In capture mode, the counter state is stored in a buffer at a selected input event. In compare mode, the channel output
reflects the comparison of the counter to a programmed threshold value. In PWM mode, the TIMER supports generation of pulse-width
modulation (PWM) outputs of arbitrary waveforms defined by the sequence of values written to the compare registers, with optional
dead-time insertion available in timer unit TIMER_0 only.
3.5.2 Wide Timer/Counter (WTIMER)
WTIMER peripherals function just as TIMER peripherals, but are 32 bits wide. They keep track of timing, count events, generate PWM
outputs and trigger timed actions in other peripherals through the PRS system. The core of each WTIMER is a 32-bit counter with up to
4 compare/capture channels. Each channel is configurable in one of three modes. In capture mode, the counter state is stored in a
buffer at a selected input event. In compare mode, the channel output reflects the comparison of the counter to a programmed threshold value. In PWM mode, the WTIMER supports generation of pulse-width modulation (PWM) outputs of arbitrary waveforms defined by
the sequence of values written to the compare registers, with optional dead-time insertion available in timer unit WTIMER_0 only.
3.5.3 Real Time Counter and Calendar (RTCC)
The Real Time Counter and Calendar (RTCC) is a 32-bit counter providing timekeeping in all energy modes. The RTCC includes a
Binary Coded Decimal (BCD) calendar mode for easy time and date keeping. The RTCC can be clocked by any of the on-board oscillators with the exception of the AUXHFRCO, and it is capable of providing system wake-up at user defined instances. The RTCC includes 128 bytes of general purpose data retention, allowing easy and convenient data storage in all energy modes down to EM4H.
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EFM32JG12 Family Data Sheet
System Overview
3.5.4 Low Energy Timer (LETIMER)
The unique LETIMER is a 16-bit timer that is available in energy mode EM0 Active, EM1 Sleep, EM2 Deep Sleep, and EM3 Stop. This
allows it to be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed
while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of waveforms with minimal software intervention. The LETIMER is connected to the Real Time Counter and Calendar (RTCC), and can be configured to start counting on compare matches from the RTCC.
3.5.5 Ultra Low Power Wake-up Timer (CRYOTIMER)
The CRYOTIMER is a 32-bit counter that is capable of running in all energy modes. It can be clocked by either the 32.768 kHz crystal
oscillator (LFXO), the 32.768 kHz RC oscillator (LFRCO), or the 1 kHz RC oscillator (ULFRCO). It can provide periodic Wakeup events
and PRS signals which can be used to wake up peripherals from any energy mode. The CRYOTIMER provides a wide range of interrupt periods, facilitating flexible ultra-low energy operation.
3.5.6 Pulse Counter (PCNT)
The Pulse Counter (PCNT) peripheral can be used for counting pulses on a single input or to decode quadrature encoded inputs. The
clock for PCNT is selectable from either an external source on pin PCTNn_S0IN or from an internal timing reference, selectable from
among any of the internal oscillators, except the AUXHFRCO. The peripheral may operate in energy mode EM0 Active, EM1 Sleep,
EM2 Deep Sleep, and EM3 Stop.
3.5.7 Watchdog Timer (WDOG)
The watchdog timer can act both as an independent watchdog or as a watchdog synchronous with the CPU clock. It has windowed
monitoring capabilities, and can generate a reset or different interrupts depending on the failure mode of the system. The watchdog can
also monitor autonomous systems driven by PRS.
3.6 Communications and Other Digital Peripherals
3.6.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
The Universal Synchronous/Asynchronous Receiver/Transmitter is a flexible serial I/O interface. It supports full duplex asynchronous
UART communication with hardware flow control as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with devices supporting:
• ISO7816 SmartCards
• IrDA
• I2S
3.6.2 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART)
The unique LEUARTTM provides two-way UART communication on a strict power budget. Only a 32.768 kHz clock is needed to allow
UART communication up to 9600 baud. The LEUART includes all necessary hardware to make asynchronous serial communication
possible with a minimum of software intervention and energy consumption.
3.6.3 Inter-Integrated Circuit Interface (I2C)
The I2C interface enables communication between the MCU and a serial I2C bus. It is capable of acting as both a master and a slave
and supports multi-master buses. Standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates
from 10 kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also available, allowing implementation of an SMBus-compliant system.
The interface provided to software by the I2C peripheral allows precise timing control of the transmission process and highly automated
transfers. Automatic recognition of slave addresses is provided in active and low energy modes.
3.6.4 Peripheral Reflex System (PRS)
The Peripheral Reflex System provides a communication network between different peripherals without software involvement. Peripherals producing Reflex signals are called producers. The PRS routes Reflex signals from producers to consumer peripherals, which in
turn perform actions in response. Edge triggers and other functionality such as simple logic operations (AND, OR, NOT) can be applied
by the PRS to the signals. The PRS allows peripheral to act autonomously without waking the MCU core, saving power.
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EFM32JG12 Family Data Sheet
System Overview
3.6.5 Low Energy Sensor Interface (LESENSE)
The Low Energy Sensor Interface LESENSETM is a highly configurable sensor interface with support for up to 16 individually configurable sensors. By controlling the analog comparators, ADC, and DAC, LESENSE is capable of supporting a wide range of sensors and
measurement schemes, and can for instance measure LC sensors, resistive sensors and capacitive sensors. LESENSE also includes a
programmable finite state machine which enables simple processing of measurement results without CPU intervention. LESENSE is
available in energy mode EM2, in addition to EM0 and EM1, making it ideal for sensor monitoring in applications with a strict energy
budget.
3.7 Security Features
3.7.1 General Purpose Cyclic Redundancy Check (GPCRC)
The GPCRC block implements a Cyclic Redundancy Check (CRC) function. It supports both 32-bit and 16-bit polynomials. The supported 32-bit polynomial is 0x04C11DB7 (IEEE 802.3), while the 16-bit polynomial can be programmed to any value, depending on the
needs of the application.
3.7.2 Crypto Accelerator (CRYPTO)
The Crypto Accelerator is a fast and energy-efficient autonomous hardware encryption and decryption accelerator. EFM32JG12 devices support AES encryption and decryption with 128- or 256-bit keys, ECC over both GF(P) and GF(2m), and SHA-1 and SHA-2
(SHA-224 and SHA-256).
Supported block cipher modes of operation for AES include: ECB, CTR, CBC, PCBC, CFB, OFB, GCM, CBC-MAC, GMAC and CCM.
Supported ECC NIST recommended curves include P-192, P-224, P-256, K-163, K-233, B-163 and B-233.
The CRYPTO peripheral allows fast processing of GCM (AES), ECC and SHA with little CPU intervention. CRYPTO also provides trigger signals for DMA read and write operations.
3.7.3 True Random Number Generator (TRNG)
The TRNG is a non-deterministic random number generator based on a full hardware solution. The TRNG is validated with NIST800-22
and AIS-31 test suites as well as being suitable for FIPS 140-2 certification (for the purposes of cryptographic key generation).
Note: TRNG operation is only supported at VSCALE2. TRNG cannot be used at VSCALE0.
3.7.4 Security Management Unit (SMU)
The Security Management Unit (SMU) allows software to set up fine-grained security for peripheral access, which is not possible in the
Memory Protection Unit (MPU). Peripherals may be secured by hardware on an individual basis, such that only priveleged accesses to
the peripheral's register interface will be allowed. When an access fault occurs, the SMU reports the specific peripheral involved and
can optionally generate an interrupt.
3.8 Analog
3.8.1 Analog Port (APORT)
The Analog Port (APORT) is an analog interconnect matrix allowing access to many analog peripherals on a flexible selection of pins.
Each APORT bus consists of analog switches connected to a common wire. Since many clients can operate differentially, buses are
grouped by X/Y pairs.
3.8.2 Analog Comparator (ACMP)
The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is higher. Inputs are selected from among internal references and external pins. The tradeoff between response time and current consumption
is configurable by software. Two 6-bit reference dividers allow for a wide range of internally-programmable reference sources. The
ACMP can also be used to monitor the supply voltage. An interrupt can be generated when the supply falls below or rises above the
programmable threshold.
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EFM32JG12 Family Data Sheet
System Overview
3.8.3 Analog to Digital Converter (ADC)
The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to 1 Msps. The output
sample resolution is configurable and additional resolution is possible using integrated hardware for averaging over multiple samples.
The ADC includes integrated voltage references and an integrated temperature sensor. Inputs are selectable from a wide range of
sources, including pins configurable as either single-ended or differential.
3.8.4 Capacitive Sense (CSEN)
The CSEN peripheral is a dedicated Capacitive Sensing block for implementing touch-sensitive user interface elements such a
switches and sliders. The CSEN peripheral uses a charge ramping measurement technique, which provides robust sensing even in
adverse conditions including radiated noise and moisture. The peripheral can be configured to take measurements on a single port pin
or scan through multiple pins and store results to memory through DMA. Several channels can also be shorted together to measure the
combined capacitance or implement wake-on-touch from very low energy modes. Hardware includes a digital accumulator and an averaging filter, as well as digital threshold comparators to reduce software overhead.
3.8.5 Digital to Analog Current Converter (IDAC)
The IDAC can source or sink a configurable constant current. This current can be driven on an output pin or routed to the selected ADC
input pin for capacitive sensing. The full-scale current is programmable between 0.05 µA and 64 µA with several ranges consisting of
various step sizes.
3.8.6 Digital to Analog Converter (VDAC)
The Digital to Analog Converter (VDAC) can convert a digital value to an analog output voltage. The VDAC is a fully differential, 500
ksps, 12-bit converter. The opamps are used in conjunction with the VDAC, to provide output buffering. One opamp is used per singleended channel, or two opamps are used to provide differential outputs. The VDAC may be used for a number of different applications
such as sensor interfaces or sound output. The VDAC can generate high-resolution analog signals while the MCU is operating at low
frequencies and with low total power consumption. Using DMA and a timer, the VDAC can be used to generate waveforms without any
CPU intervention. The VDAC is available in all energy modes down to and including EM3.
3.8.7 Operational Amplifiers
The opamps are low power amplifiers with a high degree of flexibility targeting a wide variety of standard opamp application areas, and
are available down to EM3. With flexible built-in programming for gain and interconnection they can be configured to support multiple
common opamp functions. All pins are also available externally for filter configurations. Each opamp has a rail to rail input and a rail to
rail output. They can be used in conjunction with the VDAC peripheral or in stand-alone configurations. The opamps save energy, PCB
space, and cost as compared with standalone opamps because they are integrated on-chip.
3.9 Reset Management Unit (RMU)
The RMU is responsible for handling reset of the EFM32JG12. A wide range of reset sources are available, including several power
supply monitors, pin reset, software controlled reset, core lockup reset, and watchdog reset.
3.10 Core and Memory
3.10.1 Processor Core
The ARM Cortex-M processor includes a 32-bit RISC processor integrating the following features and tasks in the system:
• ARM Cortex-M3 RISC processor achieving 1.25 Dhrystone MIPS/MHz
• Memory Protection Unit (MPU) supporting up to 8 memory segments
• Embedded Trace Macrocell (ETM) for real-time trace and debug
• Up to 1024 kB flash program memory
• Dual-bank memory with read-while-write support
• Up to 256 kB RAM data memory
• Configuration and event handling of all modules
• 2-pin Serial-Wire or 4-pin JTAG debug interface
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Rev. 1.2 | 12
EFM32JG12 Family Data Sheet
System Overview
3.10.2 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the microcontroller. The flash memory is readable and writable
from both the Cortex-M and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code
is normally written to the main block, whereas the information block is available for special user data and flash lock bits. There is also a
read-only page in the information block containing system and device calibration data. Read and write operations are supported in energy modes EM0 Active and EM1 Sleep.
3.10.3 Linked Direct Memory Access Controller (LDMA)
The Linked Direct Memory Access (LDMA) controller allows the system to perform memory operations independently of software. This
reduces both energy consumption and software workload. The LDMA allows operations to be linked together and staged, enabling sophisticated operations to be implemented.
3.10.4 Bootloader
All devices come pre-programmed with a UART bootloader. This bootloader resides in flash and can be erased if it is not needed. More
information about the bootloader protocol and usage can be found in AN0003: UART Bootloader. Application notes can be found on the
Silicon Labs website (www.silabs.com/32bit-appnotes) or within Simplicity Studio in the [Documentation] area.
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Rev. 1.2 | 13
EFM32JG12 Family Data Sheet
System Overview
3.11 Memory Map
The EFM32JG12 memory map is shown in the figures below. RAM and flash sizes are for the largest memory configuration.
Figure 3.2. EFM32JG12 Memory Map — Core Peripherals and Code Space
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Rev. 1.2 | 14
EFM32JG12 Family Data Sheet
System Overview
Figure 3.3. EFM32JG12 Memory Map — Peripherals
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Rev. 1.2 | 15
EFM32JG12 Family Data Sheet
System Overview
3.12 Configuration Summary
The features of the EFM32JG12 are a subset of the feature set described in the device reference manual. The table below describes
device specific implementation of the features. Remaining modules support full configuration.
Table 3.2. Configuration Summary
Module
Configuration
Pin Connections
USART0
IrDA
US0_TX, US0_RX, US0_CLK, US0_CS
SmartCard
USART1
I2S
US1_TX, US1_RX, US1_CLK, US1_CS
SmartCard
USART2
IrDA
US2_TX, US2_RX, US2_CLK, US2_CS
SmartCard
USART3
I2S
US3_TX, US3_RX, US3_CLK, US3_CS
SmartCard
TIMER0
with DTI
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1
-
TIM1_CC[3:0]
WTIMER0
with DTI
WTIM0_CC[2:0], WTIM0_CDTI[2:0]
WTIMER1
-
WTIM1_CC[3:0]
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EFM32JG12 Family Data Sheet
Electrical Specifications
4. Electrical Specifications
4.1 Electrical Characteristics
All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:
• Typical values are based on TAMB=25 °C and VDD= 3.3 V, by production test and/or technology characterization.
• Minimum and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature,
unless stated otherwise.
Refer to 4.1.2.1 General Operating Conditions for more details about operational supply and temperature limits.
4.1.1 Absolute Maximum Ratings
Stresses above those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of
the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and reliability data, see the Quality and Reliability Monitor Report at http://www.silabs.com/support/quality/pages/default.aspx.
Table 4.1. Absolute Maximum Ratings
Parameter
Symbol
Storage temperature range
Min
Typ
Max
Unit
TSTG
-50
—
150
°C
Voltage on any supply pin
VDDMAX
-0.3
—
3.8
V
Voltage ramp rate on any
supply pin
VDDRAMPMAX
—
—
1
V / µs
DC voltage on any GPIO pin
VDIGPIN
5V tolerant GPIO pins1 2 3
-0.3
—
Min of 5.25
and IOVDD
+2
V
Standard GPIO pins
-0.3
—
IOVDD+0.3
V
-0.3
—
1.4
V
Voltage on HFXO pins
Test Condition
VHFXOPIN
Total current into VDD power IVDDMAX
lines
Source
—
—
200
mA
Total current into VSS
ground lines
IVSSMAX
Sink
—
—
200
mA
Current per I/O pin
IIOMAX
Sink
—
—
50
mA
Source
—
—
50
mA
Sink
—
—
200
mA
Source
—
—
200
mA
-G grade devices
-40
—
105
°C
-I grade devices
-40
—
125
°C
Current for all I/O pins
Junction temperature
IIOALLMAX
TJ
Note:
1. When a GPIO pin is routed to the analog module through the APORT, the maximum voltage = IOVDD.
2. Valid for IOVDD in valid operating range or when IOVDD is undriven (high-Z). If IOVDD is connected to a low-impedance source
below the valid operating range (e.g. IOVDD shorted to VSS), the pin voltage maximum is IOVDD + 0.3 V, to avoid exceeding the
maximum IO current specifications.
3. To operate above the IOVDD supply rail, over-voltage tolerance must be enabled according to the GPIO_Px_OVTDIS register.
Pins with over-voltage tolerance disabled have the same limits as Standard GPIO.
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EFM32JG12 Family Data Sheet
Electrical Specifications
4.1.2 Operating Conditions
When assigning supply sources, the following requirements must be observed:
• VREGVDD must be greater than or equal to AVDD, DVDD and all IOVDD supplies.
• VREGVDD = AVDD
• DVDD ≤ AVDD
• IOVDD ≤ AVDD
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Rev. 1.2 | 18
EFM32JG12 Family Data Sheet
Electrical Specifications
4.1.2.1 General Operating Conditions
Table 4.2. General Operating Conditions
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Operating ambient temperature range6
TA
-G temperature grade
-40
25
85
°C
-I temperature grade
-40
25
125
°C
AVDD supply voltage2
VAVDD
1.8
3.3
3.8
V
VREGVDD operating supply
voltage2 1
VVREGVDD
DCDC in regulation
2.4
3.3
3.8
V
DCDC in bypass, 50mA load
1.8
3.3
3.8
V
DCDC not in use. DVDD externally shorted to VREGVDD
1.8
3.3
3.8
V
DCDC in bypass, T ≤ 85 °C
—
—
200
mA
DCDC in bypass, T > 85 °C
—
—
100
mA
1.62
—
VVREGVDD
V
1.62
—
VVREGVDD
V
0.75
1.0
2.75
µF
—
—
0.1
V
VSCALE2, MODE = WS1
—
—
40
MHz
VSCALE0, MODE = WS0
—
—
20
MHz
VSCALE2
—
—
40
MHz
VSCALE0
—
—
20
MHz
VREGVDD current
DVDD operating supply voltage
IVREGVDD
VDVDD
IOVDD operating supply volt- VIOVDD
age
DECOUPLE output capacitor3 4
All IOVDD pins5
CDECOUPLE
Difference between AVDD
dVDD
and VREGVDD, ABS(AVDDVREGVDD)2
HFCORECLK frequency
HFCLK frequency
fCORE
fHFCLK
Note:
1. The minimum voltage required in bypass mode is calculated using RBYP from the DCDC specification table. Requirements for
other loads can be calculated as VDVDD_min+ILOAD * RBYP_max.
2. VREGVDD must be tied to AVDD. Both VREGVDD and AVDD minimum voltages must be satisfied for the part to operate.
3. The system designer should consult the characteristic specs of the capacitor used on DECOUPLE to ensure its capacitance value stays within the specified bounds across temperature and DC bias.
4. VSCALE0 to VSCALE2 voltage change transitions occur at a rate of 10 mV / usec for approximately 20 usec. During this transition, peak currents will be dependent on the value of the DECOUPLE output capacitor, from 35 mA (with a 1 µF capacitor) to 70
mA (with a 2.7 µF capacitor).
5. When the CSEN peripheral is used with chopping enabled (CSEN_CTRL_CHOPEN = ENABLE), IOVDD must be equal to AVDD.
6. The maximum limit on TA may be lower due to device self-heating, which depends on the power dissipation of the specific application. TA (max) = TJ (max) - (THETAJA x PowerDissipation). Refer to the Absolute Maximum Ratings table and the Thermal
Characteristics table for TJ and THETAJA.
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Rev. 1.2 | 19
EFM32JG12 Family Data Sheet
Electrical Specifications
4.1.3 Thermal Characteristics
Table 4.3. Thermal Characteristics
Parameter
Symbol
Test Condition
Thermal Resistance
THETAJA
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Min
Typ
Max
Unit
QFN48 Package, 2-Layer PCB,
Air velocity = 0 m/s
—
75.7
—
°C/W
QFN48 Package, 2-Layer PCB,
Air velocity = 1 m/s
—
61.5
—
°C/W
QFN48 Package, 2-Layer PCB,
Air velocity = 2 m/s
—
55.4
—
°C/W
QFN48 Package, 4-Layer PCB,
Air velocity = 0 m/s
—
30.2
—
°C/W
QFN48 Package, 4-Layer PCB,
Air velocity = 1 m/s
—
26.3
—
°C/W
QFN48 Package, 4-Layer PCB,
Air velocity = 2 m/s
—
24.9
—
°C/W
BGA125 Package, 2-Layer PCB,
Air velocity = 0 m/s
—
90.7
—
°C/W
BGA125 Package, 2-Layer PCB,
Air velocity = 1 m/s
—
73.7
—
°C/W
BGA125 Package, 2-Layer PCB,
Air velocity = 2 m/s
—
66.4
—
°C/W
BGA125 Package, 4-Layer PCB,
Air velocity = 0 m/s
—
45
—
°C/W
BGA125 Package, 4-Layer PCB,
Air velocity = 1 m/s
—
39.6
—
°C/W
BGA125 Package, 4-Layer PCB,
Air velocity = 2 m/s
—
37.6
—
°C/W
Rev. 1.2 | 20
EFM32JG12 Family Data Sheet
Electrical Specifications
4.1.4 DC-DC Converter
Test conditions: L_DCDC=4.7 µH (Murata LQH3NPN4R7MM0L), C_DCDC=4.7 µF (Samsung CL10B475KQ8NQNC), V_DCDC_I=3.3
V, V_DCDC_O=1.8 V, I_DCDC_LOAD=50 mA, Heavy Drive configuration, F_DCDC_LN=7 MHz, unless otherwise indicated.
Table 4.4. DC-DC Converter
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Input voltage range
VDCDC_I
Bypass mode, IDCDC_LOAD = 50
mA
1.8
—
VVREGVDD_
V
Low noise (LN) mode, 1.8 V output, IDCDC_LOAD = 100 mA, or
Low power (LP) mode, 1.8 V output, IDCDC_LOAD = 10 mA
2.4
Low noise (LN) mode, 1.8 V output, IDCDC_LOAD = 200 mA
2.6
Output voltage programmable range1
VDCDC_O
Regulation DC accuracy
ACCDC
Regulation window4
WINREG
Steady-state output ripple
VR
Output voltage under/overshoot
VOV
MAX
—
VVREGVDD_
V
MAX
—
VVREGVDD_
V
MAX
1.8
—
VVREGVDD
V
Low Noise (LN) mode, 1.8 V target output
1.7
—
1.9
V
Low Power (LP) mode,
LPCMPBIASEMxx3 = 0, 1.8 V target output, IDCDC_LOAD ≤ 75 µA
1.63
—
2.2
V
Low Power (LP) mode,
LPCMPBIASEMxx3 = 3, 1.8 V target output, IDCDC_LOAD ≤ 10 mA
1.63
—
2.1
V
—
3
—
mVpp
CCM Mode (LNFORCECCM3 =
1), Load changes between 0 mA
and 100 mA
—
25
60
mV
DCM Mode (LNFORCECCM3 =
0), Load changes between 0 mA
and 10 mA
—
45
90
mV
Overshoot during LP to LN
CCM/DCM mode transitions compared to DC level in LN mode
—
200
—
mV
Undershoot during BYP/LP to LN
CCM (LNFORCECCM3 = 1) mode
transitions compared to DC level
in LN mode
—
40
—
mV
Undershoot during BYP/LP to LN
DCM (LNFORCECCM3 = 0) mode
transitions compared to DC level
in LN mode
—
100
—
mV
DC line regulation
VREG
Input changes between
VVREGVDD_MAX and 2.4 V
—
0.1
—
%
DC load regulation
IREG
Load changes between 0 mA and
100 mA in CCM mode
—
0.1
—
%
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Rev. 1.2 | 21
EFM32JG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Max load current
ILOAD_MAX
Low noise (LN) mode, Heavy
Drive2, T ≤ 85 °C
—
—
200
mA
Low noise (LN) mode, Heavy
Drive2, T > 85 °C
—
—
100
mA
Low noise (LN) mode, Medium
Drive2
—
—
100
mA
Low noise (LN) mode, Light
Drive2
—
—
50
mA
Low power (LP) mode,
LPCMPBIASEMxx3 = 0
—
—
75
µA
Low power (LP) mode,
LPCMPBIASEMxx3 = 3
—
—
10
mA
CDCDC
25% tolerance
1
4.7
4.7
µF
DCDC nominal output induc- LDCDC
tor
20% tolerance
4.7
4.7
4.7
µH
—
1.2
2.5
Ω
DCDC nominal output capacitor5
Resistance in Bypass mode
RBYP
Note:
1. Due to internal dropout, the DC-DC output will never be able to reach its input voltage, VVREGVDD.
2. Drive levels are defined by configuration of the PFETCNT and NFETCNT registers. Light Drive: PFETCNT=NFETCNT=3; Medium Drive: PFETCNT=NFETCNT=7; Heavy Drive: PFETCNT=NFETCNT=15.
3. LPCMPBIASEMxx refers to either LPCMPBIASEM234H in the EMU_DCDCMISCCTRL register or LPCMPBIASEM01 in the
EMU_DCDCLOEM01CFG register, depending on the energy mode.
4. LP mode controller is a hysteretic controller that maintains the output voltage within the specified limits.
5. Output voltage under/over-shoot and regulation are specified with CDCDC 4.7 µF. Different settings for DCDCLNCOMPCTRL
must be used if CDCDC is lower than 4.7 µF. See Application Note AN0948 for details.
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Rev. 1.2 | 22
EFM32JG12 Family Data Sheet
Electrical Specifications
4.1.5 Current Consumption
4.1.5.1 Current Consumption 3.3 V without DC-DC Converter
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = 3.3 V. T = 25 °C. DCDC is off. Minimum and maximum values in this table represent the worst conditions across supply voltage and process variation at T = 25 °C.
Table 4.5. Current Consumption 3.3 V without DC-DC Converter
Parameter
Symbol
Min
Typ
Max
Unit
38.4 MHz crystal, CPU running
while loop from flash1
—
126
—
µA/MHz
38 MHz HFRCO, CPU running
Prime from flash
—
99
—
µA/MHz
38 MHz HFRCO, CPU running
while loop from flash
—
99
105
µA/MHz
38 MHz HFRCO, CPU running
CoreMark from flash
—
124
—
µA/MHz
26 MHz HFRCO, CPU running
while loop from flash
—
102
108
µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
—
280
435
µA/MHz
Current consumption in EM0 IACTIVE_VS
mode with all peripherals disabled and voltage scaling
enabled
19 MHz HFRCO, CPU running
while loop from flash
—
88
—
µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
—
234
—
µA/MHz
Current consumption in EM1 IEM1
mode with all peripherals disabled
38.4 MHz crystal1
—
76
—
µA/MHz
38 MHz HFRCO
—
50
54
µA/MHz
26 MHz HFRCO
—
52
58
µA/MHz
1 MHz HFRCO
—
230
400
µA/MHz
19 MHz HFRCO
—
47
—
µA/MHz
1 MHz HFRCO
—
193
—
µA/MHz
Full 256 kB RAM retention and
RTCC running from LFXO
—
2.9
—
µA
Full 256 kB RAM retention and
RTCC running from LFRCO
—
3.2
—
µA
16 kB (1 bank) RAM retention and
RTCC running from LFRCO2
—
2.1
3.5
µA
Current consumption in EM3 IEM3_VS
mode, with voltage scaling
enabled
Full 256 kB RAM retention and
CRYOTIMER running from ULFRCO
—
2.56
4.8
µA
Current consumption in
EM4H mode, with voltage
scaling enabled
128 byte RAM retention, RTCC
running from LFXO
—
1.0
—
µA
128 byte RAM retention, CRYOTIMER running from ULFRCO
—
0.45
—
µA
128 byte RAM retention, no RTCC
—
0.43
0.9
µA
Current consumption in EM0 IACTIVE
mode with all peripherals disabled
Current consumption in EM1 IEM1_VS
mode with all peripherals disabled and voltage scaling
enabled
Current consumption in EM2 IEM2_VS
mode, with voltage scaling
enabled
IEM4H_VS
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Test Condition
Rev. 1.2 | 23
EFM32JG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Current consumption in
EM4S mode
IEM4S
No RAM retention, no RTCC
Min
Typ
Max
Unit
—
0.04
0.1
µA
Note:
1. CMU_HFXOCTRL_LOWPOWER=1.
2. CMU_LFRCOCTRL_ENVREF = 1, CMU_LFRCOCTRL_VREFUPDATE = 1
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Rev. 1.2 | 24
EFM32JG12 Family Data Sheet
Electrical Specifications
4.1.5.2 Current Consumption 3.3 V using DC-DC Converter
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = 1.8 V DC-DC output. T = 25 °C.
Minimum and maximum values in this table represent the worst conditions across supply voltage and process variation at T = 25 °C.
Table 4.6. Current Consumption 3.3 V using DC-DC Converter
Parameter
Symbol
Current consumption in EM0 IACTIVE_DCM
mode with all peripherals disabled, DCDC in Low Noise
DCM mode2
Current consumption in EM0 IACTIVE_CCM
mode with all peripherals disabled, DCDC in Low Noise
CCM mode1
Current consumption in EM0 IACTIVE_LPM
mode with all peripherals disabled, DCDC in LP mode3
Current consumption in EM0 IACTIVE_CCM_VS
mode with all peripherals disabled and voltage scaling
enabled, DCDC in Low
Noise CCM mode1
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Test Condition
Min
Typ
Max
Unit
38.4 MHz crystal, CPU running
while loop from flash4
—
86
—
µA/MHz
38 MHz HFRCO, CPU running
Prime from flash
—
70
—
µA/MHz
38 MHz HFRCO, CPU running
while loop from flash
—
70
—
µA/MHz
38 MHz HFRCO, CPU running
CoreMark from flash
—
85
—
µA/MHz
26 MHz HFRCO, CPU running
while loop from flash
—
77
—
µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
—
636
—
µA/MHz
38.4 MHz crystal, CPU running
while loop from flash4
—
96
—
µA/MHz
38 MHz HFRCO, CPU running
Prime from flash
—
81
—
µA/MHz
38 MHz HFRCO, CPU running
while loop from flash
—
82
—
µA/MHz
38 MHz HFRCO, CPU running
CoreMark from flash
—
95
—
µA/MHz
26 MHz HFRCO, CPU running
while loop from flash
—
95
—
µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
—
1155
—
µA/MHz
38.4 MHz crystal, CPU running
while loop from flash4
—
80
—
µA/MHz
38 MHz HFRCO, CPU running
Prime from flash
—
64
—
µA/MHz
38 MHz HFRCO, CPU running
while loop from flash
—
64
—
µA/MHz
38 MHz HFRCO, CPU running
CoreMark from flash
—
79
—
µA/MHz
26 MHz HFRCO, CPU running
while loop from flash
—
66
—
µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
—
224
—
µA/MHz
19 MHz HFRCO, CPU running
while loop from flash
—
101
—
µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
—
1128
—
µA/MHz
Rev. 1.2 | 25
EFM32JG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current consumption in EM0 IACTIVE_LPM_VS
mode with all peripherals disabled and voltage scaling
enabled, DCDC in LP mode3
19 MHz HFRCO, CPU running
while loop from flash
—
58
—
µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
—
196
—
µA/MHz
Current consumption in EM1 IEM1_DCM
mode with all peripherals disabled, DCDC in Low Noise
DCM mode2
38.4 MHz crystal4
—
56
—
µA/MHz
38 MHz HFRCO
—
41
—
µA/MHz
26 MHz HFRCO
—
48
—
µA/MHz
1 MHz HFRCO
—
610
—
µA/MHz
38.4 MHz crystal4
—
49
—
µA/MHz
38 MHz HFRCO
—
33
—
µA/MHz
26 MHz HFRCO
—
35
—
µA/MHz
1 MHz HFRCO
—
194
—
µA/MHz
Current consumption in EM1 IEM1_DCM_VS
mode with all peripherals disabled and voltage scaling
enabled, DCDC in Low
Noise DCM mode2
19 MHz HFRCO
—
52
—
µA/MHz
1 MHz HFRCO
—
587
—
µA/MHz
Current consumption in EM1 IEM1_LPM_VS
mode with all peripherals disabled and voltage scaling
enabled. DCDC in LP mode3
19 MHz HFRCO
—
32
—
µA/MHz
1 MHz HFRCO
—
170
—
µA/MHz
Current consumption in EM2 IEM2_VS
mode, with voltage scaling
enabled, DCDC in LP mode3
Full 256 kB RAM retention and
RTCC running from LFXO
—
2.1
—
µA
Full 256 kB RAM retention and
RTCC running from LFRCO
—
2.2
—
µA
16 kB (1 bank) RAM retention and
RTCC running from LFRCO5
—
1.5
—
µA
Current consumption in EM3 IEM3_VS
mode, with voltage scaling
enabled
Full 256 kB RAM retention and
CRYOTIMER running from ULFRCO
—
1.81
—
µA
Current consumption in
EM4H mode, with voltage
scaling enabled
128 byte RAM retention, RTCC
running from LFXO
—
0.69
—
µA
128 byte RAM retention, CRYOTIMER running from ULFRCO
—
0.39
—
µA
128 byte RAM retention, no RTCC
—
0.39
—
µA
No RAM retention, no RTCC
—
0.06
—
µA
Current consumption in EM1 IEM1_LPM
mode with all peripherals disabled, DCDC in Low Power
mode3
Current consumption in
EM4S mode
IEM4H_VS
IEM4S
Note:
1. DCDC Low Noise CCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=6.4 MHz (RCOBAND=4), ANASW=DVDD.
2. DCDC Low Noise DCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=3.0 MHz (RCOBAND=0), ANASW=DVDD.
3. DCDC Low Power Mode = Medium Drive (PFETCNT=NFETCNT=7), LPOSCDIV=1, LPCMPBIASEM234H=0, LPCLIMILIMSEL=1, ANASW=DVDD.
4. CMU_HFXOCTRL_LOWPOWER=1.
5. CMU_LFRCOCTRL_ENVREF = 1, CMU_LFRCOCTRL_VREFUPDATE = 1
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Rev. 1.2 | 26
EFM32JG12 Family Data Sheet
Electrical Specifications
4.1.5.3 Current Consumption 1.8 V without DC-DC Converter
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = 1.8 V. T = 25 °C. DCDC is off. Minimum and maximum values in this table represent the worst conditions across supply voltage and process variation at T = 25 °C.
Table 4.7. Current Consumption 1.8 V without DC-DC Converter
Parameter
Symbol
Min
Typ
Max
Unit
38.4 MHz crystal, CPU running
while loop from flash1
—
126
—
µA/MHz
38 MHz HFRCO, CPU running
Prime from flash
—
99
—
µA/MHz
38 MHz HFRCO, CPU running
while loop from flash
—
99
—
µA/MHz
38 MHz HFRCO, CPU running
CoreMark from flash
—
124
—
µA/MHz
26 MHz HFRCO, CPU running
while loop from flash
—
102
—
µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
—
277
—
µA/MHz
Current consumption in EM0 IACTIVE_VS
mode with all peripherals disabled and voltage scaling
enabled
19 MHz HFRCO, CPU running
while loop from flash
—
87
—
µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
—
231
—
µA/MHz
Current consumption in EM1 IEM1
mode with all peripherals disabled
38.4 MHz crystal1
—
76
—
µA/MHz
38 MHz HFRCO
—
50
—
µA/MHz
26 MHz HFRCO
—
52
—
µA/MHz
1 MHz HFRCO
—
227
—
µA/MHz
19 MHz HFRCO
—
47
—
µA/MHz
1 MHz HFRCO
—
190
—
µA/MHz
Full 256 kB RAM retention and
RTCC running from LFXO
—
2.8
—
µA
Full 256 kB RAM retention and
RTCC running from LFRCO
—
3.0
—
µA
16 kB (1 bank) RAM retention and
RTCC running from LFRCO2
—
1.9
—
µA
Current consumption in EM3 IEM3_VS
mode, with voltage scaling
enabled
Full 256 kB RAM retention and
CRYOTIMER running from ULFRCO
—
2.47
—
µA
Current consumption in
EM4H mode, with voltage
scaling enabled
128 byte RAM retention, RTCC
running from LFXO
—
0.91
—
µA
128 byte RAM retention, CRYOTIMER running from ULFRCO
—
0.35
—
µA
128 byte RAM retention, no RTCC
—
0.35
—
µA
No RAM retention, no RTCC
—
0.04
—
µA
Current consumption in EM0 IACTIVE
mode with all peripherals disabled
Current consumption in EM1 IEM1_VS
mode with all peripherals disabled and voltage scaling
enabled
Current consumption in EM2 IEM2_VS
mode, with voltage scaling
enabled
Current consumption in
EM4S mode
IEM4H_VS
IEM4S
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Test Condition
Rev. 1.2 | 27
EFM32JG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Min
Typ
Max
Unit
—
3
—
AHB
Clocks
Code execution from flash
—
10.1
—
µs
Code execution from RAM
—
3.2
—
µs
Code execution from flash
—
10.1
—
µs
Code execution from RAM
—
3.2
—
µs
Note:
1. CMU_HFXOCTRL_LOWPOWER=1.
2. CMU_LFRCOCTRL_ENVREF = 1, CMU_LFRCOCTRL_VREFUPDATE = 1
4.1.6 Wake Up Times
Table 4.8. Wake Up Times
Parameter
Symbol
Wakeup time from EM1
tEM1_WU
Wake up from EM2
tEM2_WU
Wake up from EM3
tEM3_WU
Test Condition
Wake up from EM4H1
tEM4H_WU
Executing from flash
—
80
—
µs
Wake up from EM4S1
tEM4S_WU
Executing from flash
—
291
—
µs
Time from release of reset
source to first instruction execution
tRESET
Soft Pin Reset released
—
43
—
µs
Any other reset released
—
350
—
µs
Power mode scaling time
tSCALE
VSCALE0 to VSCALE2, HFCLK =
19 MHz4 2
—
31.8
—
µs
VSCALE2 to VSCALE0, HFCLK =
19 MHz3
—
4.3
—
µs
Note:
1. Time from wakeup request until first instruction is executed. Wakeup results in device reset.
2. VSCALE0 to VSCALE2 voltage change transitions occur at a rate of 10 mV/µs for approximately 20 µs. During this transition,
peak currents will be dependent on the value of the DECOUPLE output capacitor, from 35 mA (with a 1 µF capacitor) to 70 mA
(with a 2.7 µF capacitor).
3. Scaling down from VSCALE2 to VSCALE0 requires approximately 2.8 µs + 29 HFCLKs.
4. Scaling up from VSCALE0 to VSCALE2 requires approximately 30.3 µs + 28 HFCLKs.
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Rev. 1.2 | 28
EFM32JG12 Family Data Sheet
Electrical Specifications
4.1.7 Brown Out Detector (BOD)
Table 4.9. Brown Out Detector (BOD)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
DVDD BOD threshold
VDVDDBOD
DVDD rising
—
—
1.62
V
DVDD falling (EM0/EM1)
1.35
—
—
V
DVDD falling (EM2/EM3)
1.3
—
—
V
DVDD BOD hysteresis
VDVDDBOD_HYST
—
18
—
mV
DVDD BOD response time
tDVDDBOD_DELAY Supply drops at 0.1V/µs rate
—
2.4
—
µs
AVDD BOD threshold
VAVDDBOD
—
—
1.8
V
AVDD falling (EM0/EM1)
1.62
—
—
V
AVDD falling (EM2/EM3)
1.53
—
—
V
AVDD rising
AVDD BOD hysteresis
VAVDDBOD_HYST
—
20
—
mV
AVDD BOD response time
tAVDDBOD_DELAY Supply drops at 0.1V/µs rate
—
2.4
—
µs
EM4 BOD threshold
VEM4DBOD
AVDD rising
—
—
1.7
V
AVDD falling
1.45
—
—
V
—
25
—
mV
—
300
—
µs
EM4 BOD hysteresis
VEM4BOD_HYST
EM4 BOD response time
tEM4BOD_DELAY
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Supply drops at 0.1V/µs rate
Rev. 1.2 | 29
EFM32JG12 Family Data Sheet
Electrical Specifications
4.1.8 Oscillators
4.1.8.1 Low-Frequency Crystal Oscillator (LFXO)
Table 4.10. Low-Frequency Crystal Oscillator (LFXO)
Parameter
Symbol
Crystal frequency
Test Condition
Min
Typ
Max
Unit
fLFXO
—
32.768
—
kHz
Supported crystal equivalent
series resistance (ESR)
ESRLFXO
—
—
70
kΩ
Supported range of crystal
load capacitance 1
CLFXO_CL
6
—
18
pF
On-chip tuning cap range 2
CLFXO_T
8
—
40
pF
On-chip tuning cap step size
SSLFXO
—
0.25
—
pF
Current consumption after
startup 3
ILFXO
ESR = 70 kOhm, CL = 7 pF,
GAIN4 = 2, AGC4 = 1
—
273
—
nA
Start- up time
tLFXO
ESR = 70 kOhm, CL = 7 pF,
GAIN4 = 2
—
308
—
ms
On each of LFXTAL_N and
LFXTAL_P pins
Note:
1. Total load capacitance as seen by the crystal.
2. The effective load capacitance seen by the crystal will be CLFXO_T /2. This is because each XTAL pin has a tuning cap and the
two caps will be seen in series by the crystal.
3. Block is supplied by AVDD if ANASW = 0, or DVDD if ANASW=1 in EMU_PWRCTRL register.
4. In CMU_LFXOCTRL register.
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Rev. 1.2 | 30
EFM32JG12 Family Data Sheet
Electrical Specifications
4.1.8.2 High-Frequency Crystal Oscillator (HFXO)
Table 4.11. High-Frequency Crystal Oscillator (HFXO)
Parameter
Symbol
Test Condition
Crystal frequency
fHFXO
Supported crystal equivalent
series resistance (ESR)
ESRHFXO_38M4
Supported range of crystal
load capacitance 1
CHFXO_CL
On-chip tuning cap range 2
CHFXO_T
On-chip tuning capacitance
step
SSHFXO
Startup time
tHFXO
Frequency tolerance for the
crystal
FTHFXO
Min
Typ
Max
Unit
38
38.4
40
MHz
—
—
60
Ω
6
—
12
pF
9
20
25
pF
—
0.04
—
pF
38.4 MHz, ESR = 50 Ohm, CL =
10 pF
—
300
—
µs
38.4 MHz, ESR = 50 Ohm, CL =
10 pF
-40
—
40
ppm
Crystal frequency 38.4 MHz
On each of HFXTAL_N and
HFXTAL_P pins
Note:
1. Total load capacitance as seen by the crystal.
2. The effective load capacitance seen by the crystal will be CHFXO_T /2. This is because each XTAL pin has a tuning cap and the
two caps will be seen in series by the crystal.
4.1.8.3 Low-Frequency RC Oscillator (LFRCO)
Table 4.12. Low-Frequency RC Oscillator (LFRCO)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Oscillation frequency
fLFRCO
ENVREF2 = 1
31.3
32.768
33.6
kHz
ENVREF2 = 1, T > 85 °C
31.6
32.768
36.8
kHz
ENVREF2 = 0
31.3
32.768
33.4
kHz
ENVREF2 = 0, T > 85 °C
30.0
32.768
33.4
kHz
—
500
—
µs
ENVREF = 1 in
CMU_LFRCOCTRL
—
370
—
nA
ENVREF = 0 in
CMU_LFRCOCTRL
—
520
—
nA
Startup time
tLFRCO
Current consumption 1
ILFRCO
Note:
1. Block is supplied by AVDD if ANASW = 0, or DVDD if ANASW=1 in EMU_PWRCTRL register.
2. In CMU_LFRCOCTRL register.
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Rev. 1.2 | 31
EFM32JG12 Family Data Sheet
Electrical Specifications
4.1.8.4 High-Frequency RC Oscillator (HFRCO)
Table 4.13. High-Frequency RC Oscillator (HFRCO)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Frequency accuracy
fHFRCO_ACC
At production calibrated frequencies, across supply voltage and
temperature
-2.5
—
2.5
%
Start-up time
tHFRCO
fHFRCO ≥ 19 MHz
—
300
—
ns
4 < fHFRCO < 19 MHz
—
1
—
µs
fHFRCO ≤ 4 MHz
—
2.5
—
µs
Maximum DPLL lock time1
tDPLL_LOCK
fREF = 32.768 kHz, fHFRCO =
39.98 MHz, N = 1219, M = 0
—
183
—
µs
Current consumption on all
supplies
IHFRCO
fHFRCO = 38 MHz
—
244
265
µA
fHFRCO = 32 MHz
—
204
222
µA
fHFRCO = 26 MHz
—
173
188
µA
fHFRCO = 19 MHz
—
143
156
µA
fHFRCO = 16 MHz
—
123
136
µA
fHFRCO = 13 MHz
—
110
124
µA
fHFRCO = 7 MHz
—
85
94
µA
fHFRCO = 4 MHz
—
32
37
µA
fHFRCO = 2 MHz
—
28
34
µA
fHFRCO = 1 MHz
—
26
31
µA
fHFRCO = 40 MHz, DPLL enabled
—
423
470
µA
fHFRCO = 32 MHz, DPLL enabled
—
338
375
µA
fHFRCO = 16 MHz, DPLL enabled
—
192
220
µA
fHFRCO = 4 MHz, DPLL enabled
—
51
75
µA
fHFRCO = 1 MHz, DPLL enabled
—
36
50
µA
—
0.8
—
%
Coarse trim step size (% of
period)
SSHFRCO_COARS
E
Fine trim step size (% of period)
SSHFRCO_FINE
—
0.1
—
%
Period jitter
PJHFRCO
—
0.2
—
% RMS
Note:
1. Maximum DPLL lock time ~= 6 x (M+1) x tREF, where tREF is the reference clock period.
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EFM32JG12 Family Data Sheet
Electrical Specifications
4.1.8.5 Auxiliary High-Frequency RC Oscillator (AUXHFRCO)
Table 4.14. Auxiliary High-Frequency RC Oscillator (AUXHFRCO)
Parameter
Symbol
Test Condition
Frequency accuracy
fAUXHFRCO_ACC
Start-up time
tAUXHFRCO
Current consumption on all
supplies
IAUXHFRCO
Coarse trim step size (% of
period)
CO_COARSE
Fine trim step size (% of period)
CO_FINE
Period jitter
PJAUXHFRCO
Min
Typ
Max
Unit
At production calibrated frequencies, across supply voltage and
temperature
-3
—
3
%
fAUXHFRCO ≥ 19 MHz
—
400
—
ns
4 < fAUXHFRCO < 19 MHz
—
1.4
—
µs
fAUXHFRCO ≤ 4 MHz
—
2.5
—
µs
fAUXHFRCO = 38 MHz
—
193
213
µA
fAUXHFRCO = 32 MHz
—
157
175
µA
fAUXHFRCO = 26 MHz
—
135
151
µA
fAUXHFRCO = 19 MHz
—
108
122
µA
fAUXHFRCO = 16 MHz
—
100
113
µA
fAUXHFRCO = 13 MHz
—
77
88
µA
fAUXHFRCO = 7 MHz
—
53
63
µA
fAUXHFRCO = 4 MHz
—
29
36
µA
fAUXHFRCO = 2 MHz
—
28
34
µA
fAUXHFRCO = 1 MHz
—
27
31
µA
—
0.8
—
%
—
0.1
—
%
—
0.2
—
% RMS
Min
Typ
Max
Unit
0.95
1
1.07
kHz
SSAUXHFRSSAUXHFR-
4.1.8.6 Ultra-low Frequency RC Oscillator (ULFRCO)
Table 4.15. Ultra-low Frequency RC Oscillator (ULFRCO)
Parameter
Symbol
Oscillation frequency
fULFRCO
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Test Condition
Rev. 1.2 | 33
EFM32JG12 Family Data Sheet
Electrical Specifications
4.1.9 Flash Memory Characteristics5
Table 4.16. Flash Memory Characteristics5
Parameter
Symbol
Flash erase cycles before
failure
ECFLASH
Flash data retention
RETFLASH
Word (32-bit) programming
time
tW_PROG
Test Condition
Min
Typ
Max
Unit
10000
—
—
cycles
T ≤ 85 °C
10
—
—
years
T ≤ 125 °C
10
—
—
years
Burst write, 128 words, average
time per word
20
24.4
30
µs
Single word
60
68.4
80
µs
Page erase time4
tPERASE
20
26.4
35
ms
Mass erase time1
tMERASE
20
26.5
35
ms
Device erase time2 3
tDERASE
T ≤ 85 °C
—
82
100
ms
T ≤ 125 °C
—
82
110
ms
Page Erase
—
—
1.6
mA
Erase current6
IERASE
Write current6
IWRITE
—
—
3.8
mA
Supply voltage during flash
erase and write
VFLASH
1.62
—
3.6
V
Note:
1. Mass erase is issued by the CPU and erases all flash.
2. Device erase is issued over the AAP interface and erases all flash, SRAM, the Lock Bit (LB) page, and the User data page Lock
Word (ULW).
3. From setting the DEVICEERASE bit in AAP_CMD to 1 until the ERASEBUSY bit in AAP_STATUS is cleared to 0. Internal setup
and hold times for flash control signals are included.
4. From setting the ERASEPAGE bit in MSC_WRITECMD to 1 until the BUSY bit in MSC_STATUS is cleared to 0. Internal setup
and hold times for flash control signals are included.
5. Flash data retention information is published in the Quarterly Quality and Reliability Report.
6. Measured at 25 °C.
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Rev. 1.2 | 34
EFM32JG12 Family Data Sheet
Electrical Specifications
4.1.10 General-Purpose I/O (GPIO)
Table 4.17. General-Purpose I/O (GPIO)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Input low voltage
VIL
GPIO pins
—
—
IOVDD*0.3
V
Input high voltage
VIH
GPIO pins
IOVDD*0.7
—
—
V
Output high voltage relative
to IOVDD
VOH
Sourcing 3 mA, IOVDD ≥ 3 V,
IOVDD*0.8
—
—
V
IOVDD*0.6
—
—
V
IOVDD*0.8
—
—
V
IOVDD*0.6
—
—
V
—
—
IOVDD*0.2
V
—
—
IOVDD*0.4
V
—
—
IOVDD*0.2
V
—
—
IOVDD*0.4
V
All GPIO except LFXO pins, GPIO
≤ IOVDD, T ≤ 85 °C
—
0.1
30
nA
LFXO Pins, GPIO ≤ IOVDD, T ≤
85 °C
—
0.1
50
nA
All GPIO except LFXO pins, GPIO
≤ IOVDD, T > 85 °C
—
—
110
nA
LFXO Pins, GPIO ≤ IOVDD, T >
85 °C
—
—
250
nA
IOVDD < GPIO ≤ IOVDD + 2 V
—
3.3
15
µA
30
40
65
kΩ
15
25
45
ns
DRIVESTRENGTH1 = WEAK
Sourcing 1.2 mA, IOVDD ≥ 1.62
V,
DRIVESTRENGTH1 = WEAK
Sourcing 20 mA, IOVDD ≥ 3 V,
DRIVESTRENGTH1 = STRONG
Sourcing 8 mA, IOVDD ≥ 1.62 V,
DRIVESTRENGTH1 = STRONG
Output low voltage relative to VOL
IOVDD
Sinking 3 mA, IOVDD ≥ 3 V,
DRIVESTRENGTH1 = WEAK
Sinking 1.2 mA, IOVDD ≥ 1.62 V,
DRIVESTRENGTH1 = WEAK
Sinking 20 mA, IOVDD ≥ 3 V,
DRIVESTRENGTH1 = STRONG
Sinking 8 mA, IOVDD ≥ 1.62 V,
DRIVESTRENGTH1 = STRONG
Input leakage current
IIOLEAK
Input leakage current on
5VTOL pads above IOVDD
I5VTOLLEAK
I/O pin pull-up/pull-down resistor
RPUD
Pulse width of pulses retIOGLITCH
moved by the glitch suppression filter
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Rev. 1.2 | 35
EFM32JG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Output fall time, From 70%
to 30% of VIO
tIOOF
CL = 50 pF,
Min
Typ
Max
Unit
—
1.8
—
ns
—
4.5
—
ns
—
2.2
—
ns
—
7.4
—
ns
DRIVESTRENGTH1 = STRONG,
SLEWRATE1 = 0x6
CL = 50 pF,
DRIVESTRENGTH1 = WEAK,
SLEWRATE1 = 0x6
Output rise time, From 30%
to 70% of VIO
tIOOR
CL = 50 pF,
DRIVESTRENGTH1 = STRONG,
SLEWRATE = 0x61
CL = 50 pF,
DRIVESTRENGTH1 = WEAK,
SLEWRATE1 = 0x6
Note:
1. In GPIO_Pn_CTRL register.
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Rev. 1.2 | 36
EFM32JG12 Family Data Sheet
Electrical Specifications
4.1.11 Voltage Monitor (VMON)
Table 4.18. Voltage Monitor (VMON)
Parameter
Symbol
Test Condition
Supply current (including
I_SENSE)
IVMON
Loading of monitored supply
ISENSE
Threshold range
VVMON_RANGE
Threshold step size
NVMON_STESP
Response time
tVMON_RES
Hysteresis
VVMON_HYST
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Min
Typ
Max
Unit
In EM0 or EM1, 1 supply monitored, T ≤ 85 °C
—
6.3
10
µA
In EM0 or EM1, 1 supply monitored, T > 85 °C
—
—
14
µA
In EM0 or EM1, 4 supplies monitored, T ≤ 85 °C
—
12.5
17
µA
In EM0 or EM1, 4 supplies monitored, T > 85 °C
—
—
21
µA
In EM2, EM3 or EM4, 1 supply
monitored and above threshold
—
62
—
nA
In EM2, EM3 or EM4, 1 supply
monitored and below threshold
—
62
—
nA
In EM2, EM3 or EM4, 4 supplies
monitored and all above threshold
—
99
—
nA
In EM2, EM3 or EM4, 4 supplies
monitored and all below threshold
—
99
—
nA
In EM0 or EM1
—
2
—
µA
In EM2, EM3 or EM4
—
2
—
nA
1.62
—
3.4
V
Coarse
—
200
—
mV
Fine
—
20
—
mV
Supply drops at 1V/µs rate
—
460
—
ns
—
26
—
mV
Rev. 1.2 | 37
EFM32JG12 Family Data Sheet
Electrical Specifications
4.1.12 Analog to Digital Converter (ADC)
Specified at 1 Msps, ADCCLK = 16 MHz, BIASPROG = 0, GPBIASACC = 0, unless otherwise indicated.
Table 4.19. Analog to Digital Converter (ADC)
Parameter
Symbol
Resolution
VRESOLUTION
Input voltage range5
VADCIN
Test Condition
Single ended
Differential
Input range of external refer- VADCREFIN_P
ence voltage, single ended
and differential
Min
Typ
Max
Unit
6
—
12
Bits
—
—
VFS
V
-VFS/2
—
VFS/2
V
1
—
VAVDD
V
Power supply rejection2
PSRRADC
At DC
—
80
—
dB
Analog input common mode
rejection ratio
CMRRADC
At DC
—
80
—
dB
1 Msps / 16 MHz ADCCLK, BIASPROG = 0, GPBIASACC = 1 3
—
270
315
µA
250 ksps / 4 MHz ADCCLK, BIASPROG = 6, GPBIASACC = 1 3
—
125
—
µA
62.5 ksps / 1 MHz ADCCLK, BIASPROG = 15, GPBIASACC = 1 3
—
80
—
µA
Current from all supplies, us- IADC_NORMAL_LP 35 ksps / 16 MHz ADCCLK, BIAing internal reference buffer.
SPROG = 0, GPBIASACC = 1 3
Duty-cycled operation. WAR5 ksps / 16 MHz ADCCLK BIAMUPMODE4 = NORMAL
SPROG = 0, GPBIASACC = 1 3
—
45
—
µA
—
8
—
µA
Current from all supplies, us- IADC_STANDing internal reference buffer. BY_LP
Duty-cycled operation.
AWARMUPMODE4 = KEEPINSTANDBY or KEEPINSLOWACC
125 ksps / 16 MHz ADCCLK, BIASPROG = 0, GPBIASACC = 1 3
—
105
—
µA
35 ksps / 16 MHz ADCCLK, BIASPROG = 0, GPBIASACC = 1 3
—
70
—
µA
Current from all supplies, us- IADC_CONTIing internal reference buffer. NOUS_HP
Continous operation. WARMUPMODE4 = KEEPADCWARM
1 Msps / 16 MHz ADCCLK, BIASPROG = 0, GPBIASACC = 0 3
—
325
—
µA
250 ksps / 4 MHz ADCCLK, BIASPROG = 6, GPBIASACC = 0 3
—
175
—
µA
62.5 ksps / 1 MHz ADCCLK, BIASPROG = 15, GPBIASACC = 0 3
—
125
—
µA
Current from all supplies, us- IADC_NORMAL_HP 35 ksps / 16 MHz ADCCLK, BIAing internal reference buffer.
SPROG = 0, GPBIASACC = 0 3
Duty-cycled operation. WAR5 ksps / 16 MHz ADCCLK BIAMUPMODE4 = NORMAL
SPROG = 0, GPBIASACC = 0 3
—
85
—
µA
—
16
—
µA
Current from all supplies, us- IADC_STANDing internal reference buffer. BY_HP
Duty-cycled operation.
AWARMUPMODE4 = KEEPINSTANDBY or KEEPINSLOWACC
125 ksps / 16 MHz ADCCLK, BIASPROG = 0, GPBIASACC = 0 3
—
160
—
µA
35 ksps / 16 MHz ADCCLK, BIASPROG = 0, GPBIASACC = 0 3
—
125
—
µA
Current from HFPERCLK
HFPERCLK = 16 MHz
—
160
—
µA
Current from all supplies, us- IADC_CONTIing internal reference buffer. NOUS_LP
Continous operation. WARMUPMODE4 = KEEPADCWARM
IADC_CLK
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EFM32JG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
ADC clock frequency
Min
Typ
Max
Unit
fADCCLK
—
—
16
MHz
Throughput rate
fADCRATE
—
—
1
Msps
Conversion time1
tADCCONV
6 bit
—
7
—
cycles
8 bit
—
9
—
cycles
12 bit
—
13
—
cycles
WARMUPMODE4 = NORMAL
—
—
5
µs
WARMUPMODE4 = KEEPINSTANDBY
—
—
2
µs
WARMUPMODE4 = KEEPINSLOWACC
—
—
1
µs
Internal reference7, differential
measurement
58
67
—
dB
External reference6, differential
measurement
—
68
—
dB
Spurious-free dynamic range SFDRADC
(SFDR)
1 MSamples/s, 10 kHz full-scale
sine wave
—
75
—
dB
Differential non-linearity
(DNL)
DNLADC
12 bit resolution, No missing codes
-1
—
2
LSB
Integral non-linearity (INL),
End point method
INLADC
12 bit resolution
-6
—
6
LSB
Offset error
VADCOFFSETERR
-3
0
3
LSB
Gain error in ADC
VADCGAIN
Using internal reference
—
-0.2
3.5
%
Using external reference
—
-1
—
%
—
-1.84
—
mV/°C
Startup time of reference
generator and ADC core
SNDR at 1Msps and fIN =
10kHz
Temperature sensor slope
tADCSTART
SNDRADC
VTS_SLOPE
Test Condition
Note:
1. Derived from ADCCLK.
2. PSRR is referenced to AVDD when ANASW=0 and to DVDD when ANASW=1 in EMU_PWRCTRL.
3. In ADCn_BIASPROG register.
4. In ADCn_CNTL register.
5. The absolute voltage allowed at any ADC input is dictated by the power rail supplied to on-chip circuitry, and may be lower than
the effective full scale voltage. All ADC inputs are limited to the ADC supply (AVDD or DVDD depending on
EMU_PWRCTRL_ANASW). Any ADC input routed through the APORT will further be limited by the IOVDD supply to the pin.
6. External reference is 1.25 V applied externally to ADCnEXTREFP, with the selection CONF in the SINGLECTRL_REF or
SCANCTRL_REF register field and VREFP in the SINGLECTRLX_VREFSEL or SCANCTRLX_VREFSEL field. The differential
input range with this configuration is ± 1.25 V.
7. Internal reference option used corresponds to selection 2V5 in the SINGLECTRL_REF or SCANCTRL_REF register field. The
differential input range with this configuration is ± 1.25 V. Typical value is characterized using full-scale sine wave input. Minimum
value is production-tested using sine wave input at 1.5 dB lower than full scale.
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Rev. 1.2 | 39
EFM32JG12 Family Data Sheet
Electrical Specifications
4.1.13 Analog Comparator (ACMP)
Table 4.20. Analog Comparator (ACMP)
Parameter
Symbol
Test Condition
Input voltage range
VACMPIN
Supply voltage
VACMPVDD
Active current not including
voltage reference2
IACMP
Current consumption of inter- IACMPREF
nal voltage reference2
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Min
Typ
Max
Unit
ACMPVDD =
ACMPn_CTRL_PWRSEL 1
—
—
VACMPVDD
V
BIASPROG4 ≤ 0x10 or FULLBIAS4 = 0
1.8
—
VVREGVDD_
V
0x10 < BIASPROG4 ≤ 0x20 and
FULLBIAS4 = 1
2.1
BIASPROG4 = 1, FULLBIAS4 = 0
—
50
—
nA
BIASPROG4 = 0x10, FULLBIAS4
=0
—
306
—
nA
BIASPROG4 = 0x02, FULLBIAS4
=1
—
6.5
—
µA
BIASPROG4 = 0x20, FULLBIAS4
=1
—
75
92
µA
VLP selected as input using 2.5 V
Reference / 4 (0.625 V)
—
50
—
nA
VLP selected as input using VDD
—
20
—
nA
VBDIV selected as input using
1.25 V reference / 1
—
4.1
—
µA
VADIV selected as input using
VDD/1
—
2.4
—
µA
MAX
—
VVREGVDD_
V
MAX
Rev. 1.2 | 40
EFM32JG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Hysteresis (VCM = 1.25 V,
BIASPROG4 = 0x10, FULLBIAS4 = 1)
VACMPHYST
Comparator delay3
tACMPDELAY
Min
Typ
Max
Unit
HYSTSEL5 = HYST0
-3
0
3
mV
HYSTSEL5 = HYST1
5
18
27
mV
HYSTSEL5 = HYST2
12
33
50
mV
HYSTSEL5 = HYST3
17
46
65
mV
HYSTSEL5 = HYST4
23
57
82
mV
HYSTSEL5 = HYST5
26
68
98
mV
HYSTSEL5 = HYST6
30
79
130
mV
HYSTSEL5 = HYST7
34
90
150
mV
HYSTSEL5 = HYST8
-3
0
3
mV
HYSTSEL5 = HYST9
-27
-18
-5
mV
HYSTSEL5 = HYST10
-50
-33
-12
mV
HYSTSEL5 = HYST11
-65
-45
-17
mV
HYSTSEL5 = HYST12
-82
-57
-23
mV
HYSTSEL5 = HYST13
-98
-67
-26
mV
HYSTSEL5 = HYST14
-130
-78
-30
mV
HYSTSEL5 = HYST15
-150
-88
-34
mV
BIASPROG4 = 1, FULLBIAS4 = 0
—
30
—
µs
BIASPROG4 = 0x10, FULLBIAS4
=0
—
3.7
—
µs
BIASPROG4 = 0x02, FULLBIAS4
=1
—
360
—
ns
BIASPROG4 = 0x20, FULLBIAS4
=1
—
35
—
ns
-35
—
35
mV
Offset voltage
VACMPOFFSET
BIASPROG4 =0x10, FULLBIAS4
=1
Reference voltage
VACMPREF
Internal 1.25 V reference
1
1.25
1.47
V
Internal 2.5 V reference
2
2.5
2.8
V
CSRESSEL6 = 0
—
infinite
—
kΩ
CSRESSEL6 = 1
—
15
—
kΩ
CSRESSEL6 = 2
—
27
—
kΩ
CSRESSEL6 = 3
—
39
—
kΩ
CSRESSEL6 = 4
—
51
—
kΩ
CSRESSEL6 = 5
—
100
—
kΩ
CSRESSEL6 = 6
—
162
—
kΩ
CSRESSEL6 = 7
—
235
—
kΩ
Capacitive sense internal re- RCSRES
sistance
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Rev. 1.2 | 41
EFM32JG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Note:
1. ACMPVDD is a supply chosen by the setting in ACMPn_CTRL_PWRSEL and may be IOVDD, AVDD or DVDD.
2. The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference. IACMPTOTAL = IACMP +
IACMPREF.
3. ± 100 mV differential drive.
4. In ACMPn_CTRL register.
5. In ACMPn_HYSTERESIS registers.
6. In ACMPn_INPUTSEL register.
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Rev. 1.2 | 42
EFM32JG12 Family Data Sheet
Electrical Specifications
4.1.14 Digital to Analog Converter (VDAC)
DRIVESTRENGTH = 2 unless otherwise specified. Primary VDAC output.
Table 4.21. Digital to Analog Converter (VDAC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output voltage
VDACOUT
Single-Ended
0
—
VVREF
V
-VVREF
—
VVREF
V
500 ksps, 12-bit, DRIVESTRENGTH = 2, REFSEL = 4
—
396
—
µA
44.1 ksps, 12-bit, DRIVESTRENGTH = 1, REFSEL = 4
—
72
—
µA
200 Hz refresh rate, 12-bit Sample-Off mode in EM2, DRIVESTRENGTH = 2, BGRREQTIME =
1, EM2REFENTIME = 9, REFSEL
= 4, SETTLETIME = 0x0A, WARMUPTIME = 0x02
—
1.2
—
µA
Differential2
Current consumption including references (2 channels)1
IDAC
Current from HFPERCLK4
IDAC_CLK
—
5.8
—
µA/MHz
Sample rate
SRDAC
—
—
500
ksps
DAC clock frequency
fDAC
—
—
1
MHz
Conversion time
tDACCONV
fDAC = 1MHz
2
—
—
µs
Settling time
tDACSETTLE
50% fs step settling to 5 LSB
—
2.5
—
µs
Startup time
tDACSTARTUP
Enable to 90% fs output, settling
to 10 LSB
—
—
12
µs
Output impedance
ROUT
DRIVESTRENGTH = 2, 0.4 V ≤
VOUT ≤ VOPA - 0.4 V, -8 mA <
IOUT < 8 mA, Full supply range
—
2
—
Ω
DRIVESTRENGTH = 0 or 1, 0.4 V
≤ VOUT ≤ VOPA - 0.4 V, -400 µA <
IOUT < 400 µA, Full supply range
—
2
—
Ω
DRIVESTRENGTH = 2, 0.1 V ≤
VOUT ≤ VOPA - 0.1 V, -2 mA <
IOUT < 2 mA, Full supply range
—
2
—
Ω
DRIVESTRENGTH = 0 or 1, 0.1 V
≤ VOUT ≤ VOPA - 0.1 V, -100 µA <
IOUT < 100 µA, Full supply range
—
2
—
Ω
Vout = 50% fs. DC
—
65.5
—
dB
Power supply rejection ratio6 PSRR
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Rev. 1.2 | 43
EFM32JG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Min
Typ
Max
Unit
500 ksps, single-ended, internal
1.25V reference
—
60.4
—
dB
500 ksps, single-ended, internal
2.5V reference
—
61.6
—
dB
500 ksps, single-ended, 3.3V
VDD reference
—
64.0
—
dB
500 ksps, differential, internal
1.25V reference
—
63.3
—
dB
500 ksps, differential, internal
2.5V reference
—
64.4
—
dB
500 ksps, differential, 3.3V VDD
reference
—
65.8
—
dB
Signal to noise and distortion SNDRDAC_BAND 500 ksps, single-ended, internal
ratio (1 kHz sine wave),
1.25V reference
Noise band limited to 22 kHz
500 ksps, single-ended, internal
2.5V reference
—
65.3
—
dB
—
66.7
—
dB
500 ksps, single-ended, 3.3V
VDD reference
—
70.0
—
dB
500 ksps, differential, internal
1.25V reference
—
67.8
—
dB
500 ksps, differential, internal
2.5V reference
—
69.0
—
dB
500 ksps, differential, 3.3V VDD
reference
—
68.5
—
dB
—
70.2
—
dB
Signal to noise and distortion SNDRDAC
ratio (1 kHz sine wave),
Noise band limited to 250
kHz
Test Condition
Total harmonic distortion
THD
Differential non-linearity3
DNLDAC
-0.99
—
1
LSB
Intergral non-linearity
INLDAC
-4
—
4
LSB
Offset error5
VOFFSET
T = 25 °C
-8
—
8
mV
Across operating temperature
range
-25
—
25
mV
T = 25 °C, Low-noise internal reference (REFSEL = 1V25LN or
2V5LN)
-2.5
—
2.5
%
T = 25 °C, Internal reference (REFSEL = 1V25 or 2V5)
-5
—
5
%
T = 25 °C, External reference
(REFSEL = VDD or EXT)
-1.8
—
1.8
%
Across operating temperature
range, Low-noise internal reference (REFSEL = 1V25LN or
2V5LN)
-3.5
—
3.5
%
Across operating temperature
range, Internal reference (REFSEL = 1V25 or 2V5)
-7.5
—
7.5
%
Across operating temperature
range, External reference (REFSEL = VDD or EXT)
-2.0
—
2.0
%
Gain error5
VGAIN
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Rev. 1.2 | 44
EFM32JG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
External load capactiance,
OUTSCALE=0
CLOAD
Test Condition
Min
Typ
Max
Unit
—
—
75
pF
Note:
1. Supply current specifications are for VDAC circuitry operating with static output only and do not include current required to drive
the load.
2. In differential mode, the output is defined as the difference between two single-ended outputs. Absolute voltage on each output is
limited to the single-ended range.
3. Entire range is monotonic and has no missing codes.
4. Current from HFPERCLK is dependent on HFPERCLK frequency. This current contributes to the total supply current used when
the clock to the DAC module is enabled in the CMU.
5. Gain is calculated by measuring the slope from 10% to 90% of full scale. Offset is calculated by comparing actual VDAC output at
10% of full scale to ideal VDAC output at 10% of full scale with the measured gain.
6. PSRR calculated as 20 * log10(ΔVDD / ΔVOUT), VDAC output at 90% of full scale
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Rev. 1.2 | 45
EFM32JG12 Family Data Sheet
Electrical Specifications
4.1.15 Current Digital to Analog Converter (IDAC)
Table 4.22. Current Digital to Analog Converter (IDAC)
Parameter
Symbol
Number of ranges
NIDAC_RANGES
Output current
IIDAC_OUT
Linear steps within each
range
NIDAC_STEPS
Step size
SSIDAC
Total accuracy, STEPSEL1 = ACCIDAC
0x10
Start up time
tIDAC_SU
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Test Condition
Min
Typ
Max
Unit
—
4
—
ranges
RANGSEL1 = RANGE0
0.05
—
1.6
µA
RANGSEL1 = RANGE1
1.6
—
4.7
µA
RANGSEL1 = RANGE2
0.5
—
16
µA
RANGSEL1 = RANGE3
2
—
64
µA
—
32
—
steps
RANGSEL1 = RANGE0
—
50
—
nA
RANGSEL1 = RANGE1
—
100
—
nA
RANGSEL1 = RANGE2
—
500
—
nA
RANGSEL1 = RANGE3
—
2
—
µA
EM0 or EM1, AVDD=3.3 V, T = 25
°C
-3
—
3
%
EM0 or EM1, Across operating
temperature range
-18
—
22
%
EM2 or EM3, Source mode,
RANGSEL1 = RANGE0,
AVDD=3.3 V, T = 25 °C
—
-2
—
%
EM2 or EM3, Source mode,
RANGSEL1 = RANGE1,
AVDD=3.3 V, T = 25 °C
—
-1.7
—
%
EM2 or EM3, Source mode,
RANGSEL1 = RANGE2,
AVDD=3.3 V, T = 25 °C
—
-0.8
—
%
EM2 or EM3, Source mode,
RANGSEL1 = RANGE3,
AVDD=3.3 V, T = 25 °C
—
-0.5
—
%
EM2 or EM3, Sink mode, RANGSEL1 = RANGE0, AVDD=3.3 V, T
= 25 °C
—
-0.7
—
%
EM2 or EM3, Sink mode, RANGSEL1 = RANGE1, AVDD=3.3 V, T
= 25 °C
—
-0.6
—
%
EM2 or EM3, Sink mode, RANGSEL1 = RANGE2, AVDD=3.3 V, T
= 25 °C
—
-0.5
—
%
EM2 or EM3, Sink mode, RANGSEL1 = RANGE3, AVDD=3.3 V, T
= 25 °C
—
-0.5
—
%
Output within 1% of steady state
value
—
5
—
µs
Rev. 1.2 | 46
EFM32JG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Settling time, (output settled tIDAC_SETTLE
within 1% of steady state value),
Current consumption2
IIDAC
Output voltage compliance in ICOMP_SRC
source mode, source current
change relative to current
sourced at 0 V
Output voltage compliance in ICOMP_SINK
sink mode, sink current
change relative to current
sunk at IOVDD
Test Condition
Min
Typ
Max
Unit
Range setting is changed
—
5
—
µs
Step value is changed
—
1
—
µs
EM0 or EM1 Source mode, excluding output current, Across operating temperature range
—
11
18
µA
EM0 or EM1 Sink mode, excluding output current, Across operating temperature range
—
13
21
µA
EM2 or EM3 Source mode, excluding output current, T = 25 °C
—
0.023
—
µA
EM2 or EM3 Sink mode, excluding output current, T = 25 °C
—
0.041
—
µA
EM2 or EM3 Source mode, excluding output current, T ≥ 85 °C
—
11
—
µA
EM2 or EM3 Sink mode, excluding output current, T ≥ 85 °C
—
13
—
µA
RANGESEL1=0, output voltage =
min(VIOVDD, VAVDD2-100 mv)
—
0.11
—
%
RANGESEL1=1, output voltage =
min(VIOVDD, VAVDD2-100 mV)
—
0.06
—
%
RANGESEL1=2, output voltage =
min(VIOVDD, VAVDD2-150 mV)
—
0.04
—
%
RANGESEL1=3, output voltage =
min(VIOVDD, VAVDD2-250 mV)
—
0.03
—
%
RANGESEL1=0, output voltage =
100 mV
—
0.12
—
%
RANGESEL1=1, output voltage =
100 mV
—
0.05
—
%
RANGESEL1=2, output voltage =
150 mV
—
0.04
—
%
RANGESEL1=3, output voltage =
250 mV
—
0.03
—
%
Note:
1. In IDAC_CURPROG register.
2. The IDAC is supplied by either AVDD, DVDD, or IOVDD based on the setting of ANASW in the EMU_PWRCTRL register and
PWRSEL in the IDAC_CTRL register. Setting PWRSEL to 1 selects IOVDD. With PWRSEL cleared to 0, ANASW selects between AVDD (0) and DVDD (1).
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Rev. 1.2 | 47
EFM32JG12 Family Data Sheet
Electrical Specifications
4.1.16 Capacitive Sense (CSEN)
Table 4.23. Capacitive Sense (CSEN)
Parameter
Symbol
Test Condition
Single conversion time (1x
accumulation)
tCNV
Maximum external capacitive CEXTMAX
load
Min
Typ
Max
Unit
12-bit SAR Conversions
—
20.2
—
µs
16-bit SAR Conversions
—
26.4
—
µs
Delta Modulation Conversion (single comparison)
—
1.55
—
µs
CS0CG=7 (Gain = 1x), including
routing parasitics
—
68
—
pF
CS0CG=0 (Gain = 10x), including
routing parasitics
—
680
—
pF
—
1
—
kΩ
12-bit SAR conversions, 20 ms
conversion rate, CS0CG=7 (Gain
= 1x), 10 channels bonded (total
capacitance of 330 pF)1
—
326
—
nA
Delta Modulation conversions, 20
ms conversion rate, CS0CG=7
(Gain = 1x), 10 channels bonded
(total capacitance of 330 pF)1
—
226
—
nA
12-bit SAR conversions, 200 ms
conversion rate, CS0CG=7 (Gain
= 1x), 10 channels bonded (total
capacitance of 330 pF)1
—
33
—
nA
Delta Modulation conversions,
200 ms conversion rate,
CS0CG=7 (Gain = 1x), 10 channels bonded (total capacitance of
330 pF)1
—
25
—
nA
12-bit SAR conversions, 20 ms
scan rate, CS0CG=0 (Gain =
10x), 8 samples per scan1
—
690
—
nA
Delta Modulation conversions, 20
ms scan rate, 8 comparisons per
sample (DMCR = 1, DMR = 2),
CS0CG=0 (Gain = 10x), 8 samples per scan1
—
515
—
nA
12-bit SAR conversions, 200 ms
scan rate, CS0CG=0 (Gain =
10x), 8 samples per scan1
—
79
—
nA
Delta Modulation conversions,
200 ms scan rate, 8 comparisons
per sample (DMCR = 1, DMR =
2), CS0CG=0 (Gain = 10x), 8
samples per scan1
—
57
—
nA
Maximum external series im- REXTMAX
pedance
Supply current, EM2 bonded ICSEN_BOND
conversions, WARMUPMODE=NORMAL, WARMUPCNT=0
Supply current, EM2 scan
conversions, WARMUPMODE=NORMAL, WARMUPCNT=0
ICSEN_EM2
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Rev. 1.2 | 48
EFM32JG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Supply current, continuous
conversions, WARMUPMODE=KEEPCSENWARM
ICSEN_ACTIVE
SAR or Delta Modulation conversions of 33 pF capacitor,
CS0CG=0 (Gain = 10x), always
on
—
90.5
—
µA
HFPERCLK supply current
ICSEN_HFPERCLK Current contribution from
HFPERCLK when clock to CSEN
block is enabled.
—
2.25
—
µA/MHz
Note:
1. Current is specified with a total external capacitance of 33 pF per channel. Average current is dependent on how long the module
is actively sampling channels within the scan period, and scales with the number of samples acquired. Supply current for a specific application can be estimated by multiplying the current per sample by the total number of samples per period (total_current =
single_sample_current * (number_of_channels * accumulation)).
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Rev. 1.2 | 49
EFM32JG12 Family Data Sheet
Electrical Specifications
4.1.17 Operational Amplifier (OPAMP)
Unless otherwise indicated, specified conditions are: Non-inverting input configuration, VDD = 3.3 V, DRIVESTRENGTH = 2, MAINOUTEN = 1, CLOAD = 75 pF with OUTSCALE = 0, or CLOAD = 37.5 pF with OUTSCALE = 1. Unit gain buffer and 3X-gain connection as
specified in table footnotes8 1.
Table 4.24. Operational Amplifier (OPAMP)
Parameter
Symbol
Test Condition
Supply voltage (from AVDD)
VOPA
HCMDIS = 0, Rail-to-rail input
range
Input voltage
VIN
Min
Typ
Max
Unit
2
—
3.8
V
HCMDIS = 1
1.62
—
3.8
V
HCMDIS = 0, Rail-to-rail input
range
VVSS
—
VOPA
V
HCMDIS = 1
VVSS
—
VOPA-1.2
V
Input impedance
RIN
100
—
—
MΩ
Output voltage
VOUT
VVSS
—
VOPA
V
Load capacitance2
CLOAD
OUTSCALE = 0
—
—
75
pF
OUTSCALE = 1
—
—
37.5
pF
DRIVESTRENGTH = 2 or 3, 0.4 V
≤ VOUT ≤ VOPA - 0.4 V, -8 mA <
IOUT < 8 mA, Buffer connection,
Full supply range
—
0.25
—
Ω
DRIVESTRENGTH = 0 or 1, 0.4 V
≤ VOUT ≤ VOPA - 0.4 V, -400 µA <
IOUT < 400 µA, Buffer connection,
Full supply range
—
0.6
—
Ω
DRIVESTRENGTH = 2 or 3, 0.1 V
≤ VOUT ≤ VOPA - 0.1 V, -2 mA <
IOUT < 2 mA, Buffer connection,
Full supply range
—
0.4
—
Ω
DRIVESTRENGTH = 0 or 1, 0.1 V
≤ VOUT ≤ VOPA - 0.1 V, -100 µA <
IOUT < 100 µA, Buffer connection,
Full supply range
—
1
—
Ω
Buffer connection
0.99
1
1.01
-
3x Gain connection
2.93
2.99
3.05
-
16x Gain connection
15.07
15.7
16.33
-
DRIVESTRENGTH = 3, OUTSCALE = 0
—
580
—
µA
DRIVESTRENGTH = 2, OUTSCALE = 0
—
176
—
µA
DRIVESTRENGTH = 1, OUTSCALE = 0
—
13
—
µA
DRIVESTRENGTH = 0, OUTSCALE = 0
—
4.7
—
µA
Output impedance
Internal closed-loop gain
Active current4
ROUT
GCL
IOPA
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Rev. 1.2 | 50
EFM32JG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Open-loop gain
GOL
Loop unit-gain frequency7
Phase margin
Output voltage noise
UGF
PM
NOUT
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Min
Typ
Max
Unit
DRIVESTRENGTH = 3
—
135
—
dB
DRIVESTRENGTH = 2
—
137
—
dB
DRIVESTRENGTH = 1
—
121
—
dB
DRIVESTRENGTH = 0
—
109
—
dB
DRIVESTRENGTH = 3, Buffer
connection
—
3.38
—
MHz
DRIVESTRENGTH = 2, Buffer
connection
—
0.9
—
MHz
DRIVESTRENGTH = 1, Buffer
connection
—
132
—
kHz
DRIVESTRENGTH = 0, Buffer
connection
—
34
—
kHz
DRIVESTRENGTH = 3, 3x Gain
connection
—
2.57
—
MHz
DRIVESTRENGTH = 2, 3x Gain
connection
—
0.71
—
MHz
DRIVESTRENGTH = 1, 3x Gain
connection
—
113
—
kHz
DRIVESTRENGTH = 0, 3x Gain
connection
—
28
—
kHz
DRIVESTRENGTH = 3, Buffer
connection
—
67
—
°
DRIVESTRENGTH = 2, Buffer
connection
—
69
—
°
DRIVESTRENGTH = 1, Buffer
connection
—
63
—
°
DRIVESTRENGTH = 0, Buffer
connection
—
68
—
°
DRIVESTRENGTH = 3, Buffer
connection, 10 Hz - 10 MHz
—
146
—
µVrms
DRIVESTRENGTH = 2, Buffer
connection, 10 Hz - 10 MHz
—
163
—
µVrms
DRIVESTRENGTH = 1, Buffer
connection, 10 Hz - 1 MHz
—
170
—
µVrms
DRIVESTRENGTH = 0, Buffer
connection, 10 Hz - 1 MHz
—
176
—
µVrms
DRIVESTRENGTH = 3, 3x Gain
connection, 10 Hz - 10 MHz
—
313
—
µVrms
DRIVESTRENGTH = 2, 3x Gain
connection, 10 Hz - 10 MHz
—
271
—
µVrms
DRIVESTRENGTH = 1, 3x Gain
connection, 10 Hz - 1 MHz
—
247
—
µVrms
DRIVESTRENGTH = 0, 3x Gain
connection, 10 Hz - 1 MHz
—
245
—
µVrms
Rev. 1.2 | 51
EFM32JG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Slew rate5
SR
DRIVESTRENGTH = 3,
INCBW=13
—
4.7
—
V/µs
DRIVESTRENGTH = 3,
INCBW=0
—
1.5
—
V/µs
DRIVESTRENGTH = 2,
INCBW=13
—
1.27
—
V/µs
DRIVESTRENGTH = 2,
INCBW=0
—
0.42
—
V/µs
DRIVESTRENGTH = 1,
INCBW=13
—
0.17
—
V/µs
DRIVESTRENGTH = 1,
INCBW=0
—
0.058
—
V/µs
DRIVESTRENGTH = 0,
INCBW=13
—
0.044
—
V/µs
DRIVESTRENGTH = 0,
INCBW=0
—
0.015
—
V/µs
Startup time6
TSTART
DRIVESTRENGTH = 2
—
—
12
µs
Input offset voltage
VOSI
DRIVESTRENGTH = 2 or 3, T =
25 °C
-2
—
2
mV
DRIVESTRENGTH = 1 or 0, T =
25 °C
-2
—
2
mV
DRIVESTRENGTH = 2 or 3,
across operating temperature
range
-12
—
12
mV
DRIVESTRENGTH = 1 or 0,
across operating temperature
range
-30
—
30
mV
DC power supply rejection
ratio9
PSRRDC
Input referred
—
70
—
dB
DC common-mode rejection
ratio9
CMRRDC
Input referred
—
70
—
dB
Total harmonic distortion
THDOPA
DRIVESTRENGTH = 2, 3x Gain
connection, 1 kHz, VOUT = 0.1 V
to VOPA - 0.1 V
—
90
—
dB
DRIVESTRENGTH = 0, 3x Gain
connection, 0.1 kHz, VOUT = 0.1 V
to VOPA - 0.1 V
—
90
—
dB
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Rev. 1.2 | 52
EFM32JG12 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Note:
1. Specified configuration for 3X-Gain configuration is: INCBW = 1, HCMDIS = 1, RESINSEL = VSS, VINPUT = 0.5 V, VOUTPUT = 1.5
V. Nominal voltage gain is 3.
2. If the maximum CLOAD is exceeded, an isolation resistor is required for stability. See AN0038 for more information.
3. When INCBW is set to 1 the OPAMP bandwidth is increased. This is allowed only when the non-inverting close-loop gain is ≥ 3,
or the OPAMP may not be stable.
4. Current into the load resistor is excluded. When the OPAMP is connected with closed-loop gain > 1, there will be extra current to
drive the resistor feedback network. The internal resistor feedback network has total resistance of 143.5 kOhm, which will cause
another ~10 µA current when the OPAMP drives 1.5 V between output and ground.
5. Step between 0.2V and VOPA-0.2V, 10%-90% rising/falling range.
6. From enable to output settled. In sample-and-off mode, RC network after OPAMP will contribute extra delay. Settling error < 1mV.
7. In unit gain connection, UGF is the gain-bandwidth product of the OPAMP. In 3x Gain connection, UGF is the gain-bandwidth
product of the OPAMP and 1/3 attenuation of the feedback network.
8. Specified configuration for Unit gain buffer configuration is: INCBW = 0, HCMDIS = 0, RESINSEL = DISABLE. VINPUT = 0.5 V,
VOUTPUT = 0.5 V.
9. When HCMDIS=1 and input common mode transitions the region from VOPA-1.4V to VOPA-1V, input offset will change. PSRR
and CMRR specifications do not apply to this transition region.
4.1.18 Pulse Counter (PCNT)
Table 4.25. Pulse Counter (PCNT)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Input frequency
FIN
Asynchronous Single and Quadrature Modes
—
—
20
MHz
Sampled Modes with Debounce
filter set to 0.
—
—
8
kHz
Min
Typ
Max
Unit
4.1.19 Analog Port (APORT)
Table 4.26. Analog Port (APORT)
Parameter
Symbol
Test Condition
Supply current2 1
IAPORT
Operation in EM0/EM1
—
7
—
µA
Operation in EM2/EM3
—
67
—
nA
Note:
1. Specified current is for continuous APORT operation. In applications where the APORT is not requested continuously (e.g. periodic ACMP requests from LESENSE in EM2), the average current requirements can be estimated by mutiplying the duty cycle of
the requests by the specified continuous current number.
2. Supply current increase that occurs when an analog peripheral requests access to APORT. This current is not included in reported module currents. Additional peripherals requesting access to APORT do not incur further current.
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EFM32JG12 Family Data Sheet
Electrical Specifications
4.1.20 I2C
4.1.20.1 I2C Standard-mode (Sm)1
Table 4.27. I2C Standard-mode (Sm)1
Parameter
Symbol
SCL clock frequency2
Test Condition
Min
Typ
Max
Unit
fSCL
0
—
100
kHz
SCL clock low time
tLOW
4.7
—
—
µs
SCL clock high time
tHIGH
4
—
—
µs
SDA set-up time
tSU_DAT
250
—
—
ns
SDA hold time3
tHD_DAT
100
—
3450
ns
Repeated START condition
set-up time
tSU_STA
4.7
—
—
µs
(Repeated) START condition tHD_STA
hold time
4
—
—
µs
STOP condition set-up time
tSU_STO
4
—
—
µs
Bus free time between a
STOP and START condition
tBUF
4.7
—
—
µs
Note:
1. For CLHR set to 0 in the I2Cn_CTRL register.
2. For the minimum HFPERCLK frequency required in Standard-mode, refer to the I2C chapter in the reference manual.
3. The maximum SDA hold time (tHD_DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
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EFM32JG12 Family Data Sheet
Electrical Specifications
4.1.20.2 I2C Fast-mode (Fm)1
Table 4.28. I2C Fast-mode (Fm)1
Parameter
Symbol
SCL clock frequency2
Test Condition
Min
Typ
Max
Unit
fSCL
0
—
400
kHz
SCL clock low time
tLOW
1.3
—
—
µs
SCL clock high time
tHIGH
0.6
—
—
µs
SDA set-up time
tSU_DAT
100
—
—
ns
SDA hold time3
tHD_DAT
100
—
900
ns
Repeated START condition
set-up time
tSU_STA
0.6
—
—
µs
(Repeated) START condition tHD_STA
hold time
0.6
—
—
µs
STOP condition set-up time
tSU_STO
0.6
—
—
µs
Bus free time between a
STOP and START condition
tBUF
1.3
—
—
µs
Note:
1. For CLHR set to 1 in the I2Cn_CTRL register.
2. For the minimum HFPERCLK frequency required in Fast-mode, refer to the I2C chapter in the reference manual.
3. The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
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EFM32JG12 Family Data Sheet
Electrical Specifications
4.1.20.3 I2C Fast-mode Plus (Fm+)1
Table 4.29. I2C Fast-mode Plus (Fm+)1
Parameter
Symbol
SCL clock frequency2
Test Condition
Min
Typ
Max
Unit
fSCL
0
—
1000
kHz
SCL clock low time
tLOW
0.5
—
—
µs
SCL clock high time
tHIGH
0.26
—
—
µs
SDA set-up time
tSU_DAT
50
—
—
ns
SDA hold time
tHD_DAT
100
—
—
ns
Repeated START condition
set-up time
tSU_STA
0.26
—
—
µs
(Repeated) START condition tHD_STA
hold time
0.26
—
—
µs
STOP condition set-up time
tSU_STO
0.26
—
—
µs
Bus free time between a
STOP and START condition
tBUF
0.5
—
—
µs
Note:
1. For CLHR set to 0 or 1 in the I2Cn_CTRL register.
2. For the minimum HFPERCLK frequency required in Fast-mode Plus, refer to the I2C chapter in the reference manual.
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EFM32JG12 Family Data Sheet
Electrical Specifications
4.1.21 USART SPI
SPI Master Timing
Table 4.30. SPI Master Timing
Parameter
Symbol
SCLK period 1 3 2
tSCLK
CS to MOSI 1 3
Test Condition
Min
Typ
Max
Unit
2*
tHFPERCLK
—
—
ns
tCS_MO
-14.5
—
13.5
ns
SCLK to MOSI 1 3
tSCLK_MO
-8.5
—
8
ns
MISO setup time 1 3
tSU_MI
IOVDD = 1.62 V
92
—
—
ns
IOVDD = 3.0 V
42
—
—
ns
-10
—
—
ns
tH_MI
MISO hold time 1 3
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0).
2. tHFPERCLK is one period of the selected HFPERCLK.
3. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD).
CS
tCS_MO
tSCKL_MO
SCLK
CLKPOL = 0
tSCLK
SCLK
CLKPOL = 1
MOSI
tSU_MI
tH_MI
MISO
Figure 4.1. SPI Master Timing Diagram
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EFM32JG12 Family Data Sheet
Electrical Specifications
SPI Slave Timing
Table 4.31. SPI Slave Timing
Parameter
Symbol
SCLK period 1 3 2
Test Condition
Min
Typ
Max
Unit
tSCLK
6*
tHFPERCLK
—
—
ns
SCLK high time1 3 2
tSCLK_HI
2.5 *
tHFPERCLK
—
—
ns
SCLK low time1 3 2
tSCLK_LO
2.5 *
tHFPERCLK
—
—
ns
CS active to MISO 1 3
tCS_ACT_MI
4
—
70
ns
CS disable to MISO 1 3
tCS_DIS_MI
4
—
50
ns
MOSI setup time 1 3
tSU_MO
8
—
—
ns
MOSI hold time 1 3 2
tH_MO
7
—
—
ns
SCLK to MISO 1 3 2
tSCLK_MI
10 + 1.5 *
tHFPERCLK
—
65 + 2.5 *
tHFPERCLK
ns
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0).
2. tHFPERCLK is one period of the selected HFPERCLK.
3. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD).
CS
tCS_ACT_MI
tCS_DIS_MI
SCLK
CLKPOL = 0
SCLK
CLKPOL = 1
tSCLK_HI
tSU_MO
tSCLK_LO
tSCLK
tH_MO
MOSI
tSCLK_MI
MISO
Figure 4.2. SPI Slave Timing Diagram
4.2 Typical Performance Curves
Typical performance curves indicate typical characterized performance under the stated conditions.
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EFM32JG12 Family Data Sheet
Electrical Specifications
4.2.1 Supply Current
Figure 4.3. EM0 Active Mode Typical Supply Current vs. Temperature
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EFM32JG12 Family Data Sheet
Electrical Specifications
Figure 4.4. EM1 Sleep Mode Typical Supply Current vs. Temperature
Typical supply current for EM2, EM3 and EM4H using standard software libraries from Silicon Laboratories.
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EFM32JG12 Family Data Sheet
Electrical Specifications
Figure 4.5. EM2, EM3, EM4H and EM4S Typical Supply Current vs. Temperature
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EFM32JG12 Family Data Sheet
Electrical Specifications
Figure 4.6. EM0 and EM1 Mode Typical Supply Current vs. Supply
Typical supply current for EM2, EM3 and EM4H using standard software libraries from Silicon Laboratories.
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EFM32JG12 Family Data Sheet
Electrical Specifications
Figure 4.7. EM2, EM3, EM4H and EM4S Typical Supply Current vs. Supply
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EFM32JG12 Family Data Sheet
Electrical Specifications
4.2.2 DC-DC Converter
Default test conditions: CCM mode, LDCDC = 4.7 μH, CDCDC = 4.7 μF, VDCDC_I = 3.3 V, VDCDC_O = 1.8 V, FDCDC_LN = 7 MHz
Figure 4.8. DC-DC Converter Typical Performance Characteristics
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EFM32JG12 Family Data Sheet
Electrical Specifications
Load Step Response in LN (CCM) mode
(Heavy Drive)
LN (CCM) and LP mode transition (load: 5mA)
DVDD
DVDD
60mV/div
offset:1.8V
20mV/div
offset:1.8V
100mA
VSW
ILOAD
1mA
2V/div
offset:1.8V
100μs/div
10μs/div
Figure 4.9. DC-DC Converter Transition Waveforms
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EFM32JG12 Family Data Sheet
Typical Connection Diagrams
5. Typical Connection Diagrams
5.1 Power
Typical power supply connections for direct supply, without using the internal DC-DC converter, are shown in Figure 5.1 EFM32JG12
Typical Application Circuit, Direct Supply, No DC-DC Converter on page 66.
VDD
Main
Supply
+
–
VREGVDD
AVDD_0
IOVDD
AVDD_1
VREGSW
HFXTAL_N
VREGVSS
HFXTAL_P
DVDD
LFXTAL_N
LFXTAL_P
DECOUPLE
Figure 5.1. EFM32JG12 Typical Application Circuit, Direct Supply, No DC-DC Converter
A typical application circuit using the internal DC-DC converter is shown in Figure 5.2 EFM32JG12 Typical Application Circuit Using the
DC-DC Converter on page 66. The MCU operates from the DC-DC converter supply.
VDD
Main
Supply
+
–
VREGVDD
VDCDC
AVDD_0
IOVDD
AVDD_1
VREGSW
VREGVSS
DVDD
HFXTAL_N
HFXTAL_P
LFXTAL_N
LFXTAL_P
DECOUPLE
Figure 5.2. EFM32JG12 Typical Application Circuit Using the DC-DC Converter
5.2 Other Connections
Other components or connections may be required to meet the system-level requirements. Application Note AN0002: "Hardware Design Considerations" contains detailed information on these connections. Application Notes can be accessed on the Silicon Labs website (www.silabs.com/32bit-appnotes).
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EFM32JG12 Family Data Sheet
Pin Definitions
6. Pin Definitions
6.1 EFM32JG12B5xx in BGA125 Device Pinout
Figure 6.1. EFM32JG12B5xx in BGA125 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 6.3 GPIO Functionality Table or 6.4 Alternate Functionality Overview.
Table 6.1. EFM32JG12B5xx in BGA125 Device Pinout
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
PF3
A1
GPIO (5V)
PF1
A2
GPIO (5V)
PC5
A3
GPIO (5V)
PC3
A4
GPIO (5V)
PC0
A5
GPIO (5V)
PC11
A6
GPIO (5V)
PC9
A7
GPIO (5V)
PC7
A8
GPIO (5V)
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EFM32JG12 Family Data Sheet
Pin Definitions
Pin Name
Pin(s)
Description
DECOUPLE
A9
Decouple output for on-chip voltage
regulator. An external decoupling capacitor is required at this pin.
VREGVDD
A11
Voltage regulator VDD input
VREGVSS
A13
B11
B12
PF2
Pin Name
Pin(s)
Description
DVDD
A10
Digital power supply.
VREGSW
A12
DCDC regulator switching node
Voltage regulator VSS
PF8
B1
GPIO (5V)
B2
GPIO (5V)
PF0
B3
GPIO (5V)
PC4
B4
GPIO (5V)
PC1
B5
GPIO (5V)
PJ14
B6
GPIO (5V)
PC10
B7
GPIO (5V)
PC8
B8
GPIO (5V)
PC6
B9
GPIO (5V)
IOVDD
B10
F2
F11
M12
Digital IO power supply.
AVDD
B13
J1
J2
Analog power supply.
PF11
C1
GPIO (5V)
PF10
C2
GPIO (5V)
PF9
C3
GPIO (5V)
PC2
C5
GPIO (5V)
PJ15
C6
GPIO (5V)
PB15
C10
GPIO
PB14
C11
GPIO
PB13
C12
GPIO
PB12
C13
GPIO
PF14
D1
GPIO (5V)
PF13
D2
GPIO (5V)
PF12
D3
GPIO (5V)
PB11
D11
GPIO
PB10
D12
GPIO (5V)
PB9
D13
GPIO (5V)
PK1
E1
GPIO (5V)
PK0
E2
GPIO
PF15
E3
GPIO (5V)
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EFM32JG12 Family Data Sheet
Pin Definitions
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
VSS
E5
E6
E7
E8
E9
F5
F6
F7
F8
F9
G5
G6
G7
G8
G9
H5
H6
H7
H8
H9
J5
J6
J7
J8
J9
K2
L2
M2
M3
M4
M5
M6
M7
N5
Ground
PB8
E12
GPIO (5V)
PB7
E13
GPIO (5V)
PK2
F1
GPIO (5V)
PB6
F12
GPIO (5V)
PI3
F13
GPIO (5V)
PF5
G1
GPIO (5V)
PF4
G2
GPIO (5V)
PI2
G11
GPIO (5V)
PI1
G12
GPIO (5V)
PI0
G13
GPIO (5V)
PF7
H1
GPIO (5V)
PF6
H2
GPIO (5V)
PA9
H12
GPIO (5V)
PA8
H13
GPIO (5V)
PA7
J11
GPIO (5V)
PA6
J12
GPIO (5V)
PA5
J13
GPIO (5V)
HFXTAL_N
K1
High Frequency Crystal input pin.
PA4
K12
GPIO
PA3
K13
GPIO
HFXTAL_P
L1
High Frequency Crystal output pin.
BODEN
L10
Brown-Out Detector Enable. This pin
may be left disconnected or tied to
AVDD.
PA2
L12
GPIO
M1
Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during
reset, and let the internal pull-up ensure
that reset is released.
PA1
L13
GPIO
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RESETn
Rev. 1.2 | 69
EFM32JG12 Family Data Sheet
Pin Definitions
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
NC
M8
N1
N2
N3
N4
N6
N7
N8
No Connect.
PD9
M9
GPIO (5V)
PD11
M10
GPIO (5V)
PD13
M11
GPIO
PA0
M13
GPIO
PD8
N9
GPIO (5V)
PD10
N10
GPIO (5V)
PD12
N11
GPIO (5V)
PD14
N12
GPIO
PD15
N13
GPIO
Note:
1. GPIO with 5V tolerance are indicated by (5V).
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EFM32JG12 Family Data Sheet
Pin Definitions
6.2 EFM32JG12B5xx in QFN48 Device Pinout
Figure 6.2. EFM32JG12B5xx in QFN48 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 6.3 GPIO Functionality Table or 6.4 Alternate Functionality Overview.
Table 6.2. EFM32JG12B5xx in QFN48 Device Pinout
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
VSS
0
Ground
PF0
1
GPIO (5V)
PF1
2
GPIO (5V)
PF2
3
GPIO (5V)
PF3
4
GPIO (5V)
PF4
5
GPIO (5V)
PF5
6
GPIO (5V)
PF6
7
GPIO (5V)
PF7
8
GPIO (5V)
AVDD
9
34
Analog power supply.
HFXTAL_N
10
High Frequency Crystal input pin.
HFXTAL_P
11
High Frequency Crystal output pin.
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EFM32JG12 Family Data Sheet
Pin Definitions
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
No Connect.
RESETn
12
Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during
reset, and let the internal pull-up ensure
that reset is released.
PD8
17
GPIO (5V)
PD9
18
GPIO (5V)
PD10
19
GPIO (5V)
PD11
20
GPIO (5V)
PD12
21
GPIO (5V)
PD13
22
GPIO
PD14
23
GPIO
PD15
24
GPIO
PA0
25
GPIO
PA1
26
GPIO
PA2
27
GPIO
PA3
28
GPIO
PA4
29
GPIO
PA5
30
GPIO (5V)
PB11
31
GPIO
PB12
32
GPIO
PB13
33
GPIO
PB14
35
GPIO
PB15
36
GPIO
VREGVSS
37
Voltage regulator VSS
VREGSW
38
DCDC regulator switching node
VREGVDD
39
Voltage regulator VDD input
DVDD
40
Digital power supply.
DECOUPLE
41
Decouple output for on-chip voltage
regulator. An external decoupling capacitor is required at this pin.
IOVDD
42
Digital IO power supply.
PC6
43
GPIO (5V)
PC7
44
GPIO (5V)
PC8
45
GPIO (5V)
PC9
46
GPIO (5V)
PC10
47
GPIO (5V)
PC11
48
GPIO (5V)
NC
13
14
15
16
Note:
1. GPIO with 5V tolerance are indicated by (5V).
2. The PD8 GPIO pin is not available (no-connect) on other device families, and should not be used if direct pin compatibility across
multiple families is required.
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EFM32JG12 Family Data Sheet
Pin Definitions
6.3 GPIO Functionality Table
A wide selection of alternate functionality is available for multiplexing to various pins. The following table shows the name of each GPIO
pin, followed by the functionality available on that pin. Refer to 6.4 Alternate Functionality Overview for a list of GPIO locations available
for each function.
Table 6.3. GPIO Functionality Table
GPIO Name
PF3
PF1
Pin Alternate Functionality / Description
Analog
Timers
BUSAY BUSBX
TIM0_CC0 #27
TIM0_CC1 #26
TIM0_CC2 #25
TIM0_CDTI0 #24
TIM0_CDTI1 #23
TIM0_CDTI2 #22
TIM1_CC0 #27
TIM1_CC1 #26
TIM1_CC2 #25
TIM1_CC3 #24
WTIM0_CDTI2 #31
WTIM1_CC0 #27
WTIM1_CC1 #25
WTIM1_CC2 #23
WTIM1_CC3 #21 LETIM0_OUT0 #27 LETIM0_OUT1 #26
PCNT0_S0IN #27
PCNT0_S1IN #26
US0_TX #27 US0_RX #26
US0_CLK #25 US0_CS
#24 US0_CTS #23
US0_RTS #22 US1_TX
#27 US1_RX #26
US1_CLK #25 US1_CS CMU_CLK1 #6 PRS_CH0
#24 US1_CTS #23
#3 PRS_CH1 #2
US1_RTS #22 US2_TX
PRS_CH2 #1 PRS_CH3
#16 US2_RX #15
#0 ACMP0_O #27
US2_CLK #14 US2_CS
ACMP1_O #27 DBG_TDI
#13 US2_CTS #12
US2_RTS #11 LEU0_TX
#27 LEU0_RX #26
I2C0_SDA #27 I2C0_SCL
#26
BUSAY BUSBX
TIM0_CC0 #25
TIM0_CC1 #24
TIM0_CC2 #23
TIM0_CDTI0 #22
TIM0_CDTI1 #21
TIM0_CDTI2 #20
TIM1_CC0 #25
TIM1_CC1 #24
TIM1_CC2 #23
TIM1_CC3 #22
WTIM0_CDTI1 #31
WTIM0_CDTI2 #29
WTIM1_CC0 #25
WTIM1_CC1 #23
WTIM1_CC2 #21
WTIM1_CC3 #19 LETIM0_OUT0 #25 LETIM0_OUT1 #24
PCNT0_S0IN #25
PCNT0_S1IN #24
US0_TX #25 US0_RX #24
US0_CLK #23 US0_CS
#22 US0_CTS #21
US0_RTS #20 US1_TX
#25 US1_RX #24
US1_CLK #23 US1_CS
#22 US1_CTS #21
US1_RTS #20 US2_TX
#15 US2_RX #14
US2_CLK #13 US2_CS
#12 US2_CTS #11
US2_RTS #10 LEU0_TX
#25 LEU0_RX #24
I2C0_SDA #25 I2C0_SCL
#24
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Communication
Other
PRS_CH0 #1 PRS_CH1
#0 PRS_CH2 #7
PRS_CH3 #6 ACMP0_O
#25 ACMP1_O #25
DBG_SWDIOTMS
BOOT_RX
Rev. 1.2 | 73
EFM32JG12 Family Data Sheet
Pin Definitions
GPIO Name
PC5
PC3
PC0
Pin Alternate Functionality / Description
Analog
Timers
Communication
BUSAY BUSBX
WTIM0_CC0 #25
WTIM0_CC1 #23
WTIM0_CC2 #21
WTIM0_CDTI0 #17
WTIM0_CDTI1 #15
WTIM0_CDTI2 #13
WTIM1_CC0 #9
WTIM1_CC1 #7
WTIM1_CC2 #5
WTIM1_CC3 #3
PCNT1_S0IN #18
PCNT1_S1IN #17
PCNT2_S0IN #18
PCNT2_S1IN #17
US3_TX #23 US3_RX #22
US3_CLK #21 US3_CS
#20 US3_CTS #19
US3_RTS #18 I2C1_SDA
#18 I2C1_SCL #17
BUSAY BUSBX
WTIM0_CC0 #23
WTIM0_CC1 #21
WTIM0_CC2 #19
WTIM0_CDTI0 #15
WTIM0_CDTI1 #13
WTIM0_CDTI2 #11
WTIM1_CC0 #7
WTIM1_CC1 #5
WTIM1_CC2 #3
WTIM1_CC3 #1
PCNT1_S0IN #16
PCNT1_S1IN #15
PCNT2_S0IN #16
PCNT2_S1IN #15
US3_TX #21 US3_RX #20
US3_CLK #19 US3_CS
#18 US3_CTS #17
US3_RTS #16 I2C1_SDA
#16 I2C1_SCL #15
BUSBY BUSAX
WTIM0_CC0 #20
WTIM0_CC1 #18
WTIM0_CC2 #16
WTIM0_CDTI0 #12
WTIM0_CDTI1 #10
WTIM0_CDTI2 #8
WTIM1_CC0 #4
WTIM1_CC1 #2
WTIM1_CC2 #0
PCNT1_S0IN #13
PCNT1_S1IN #12
PCNT2_S0IN #13
PCNT2_S1IN #12
US3_TX #18 US3_RX #17
US3_CLK #16 US3_CS
#15 US3_CTS #14
US3_RTS #13 I2C1_SDA
#13 I2C1_SCL #12
silabs.com | Building a more connected world.
Other
Rev. 1.2 | 74
EFM32JG12 Family Data Sheet
Pin Definitions
GPIO Name
PC11
PC9
Pin Alternate Functionality / Description
Analog
Timers
BUSAY BUSBX
TIM0_CC0 #16
TIM0_CC1 #15
TIM0_CC2 #14
TIM0_CDTI0 #13
TIM0_CDTI1 #12
TIM0_CDTI2 #11
TIM1_CC0 #16
TIM1_CC1 #15
TIM1_CC2 #14
TIM1_CC3 #13
WTIM0_CC0 #31
WTIM0_CC1 #29
WTIM0_CC2 #27
WTIM0_CDTI0 #23
WTIM0_CDTI1 #21
WTIM0_CDTI2 #19
WTIM1_CC0 #15
WTIM1_CC1 #13
WTIM1_CC2 #11
WTIM1_CC3 #9 LETIM0_OUT0 #16 LETIM0_OUT1 #15
PCNT0_S0IN #16
PCNT0_S1IN #15
PCNT2_S0IN #20
PCNT2_S1IN #19
US0_TX #16 US0_RX #15
US0_CLK #14 US0_CS
#13 US0_CTS #12
US0_RTS #11 US1_TX CMU_CLK0 #3 PRS_CH0
#16 US1_RX #15
#13 PRS_CH9 #16
US1_CLK #14 US1_CS
PRS_CH10 #5
#13 US1_CTS #12
PRS_CH11 #4 ACMP0_O
US1_RTS #11 LEU0_TX
#16 ACMP1_O #16
#16 LEU0_RX #15
DBG_SWO #3
I2C0_SDA #16 I2C0_SCL
#15 I2C1_SDA #20
I2C1_SCL #19
BUSAY BUSBX
TIM0_CC0 #14
TIM0_CC1 #13
TIM0_CC2 #12
TIM0_CDTI0 #11
TIM0_CDTI1 #10
TIM0_CDTI2 #9
TIM1_CC0 #14
TIM1_CC1 #13
TIM1_CC2 #12
TIM1_CC3 #11
WTIM0_CC0 #29
WTIM0_CC1 #27
WTIM0_CC2 #25
WTIM0_CDTI0 #21
WTIM0_CDTI1 #19
WTIM0_CDTI2 #17
WTIM1_CC0 #13
WTIM1_CC1 #11
WTIM1_CC2 #9
WTIM1_CC3 #7 LETIM0_OUT0 #14 LETIM0_OUT1 #13
PCNT0_S0IN #14
PCNT0_S1IN #13
US0_TX #14 US0_RX #13
US0_CLK #12 US0_CS
#11 US0_CTS #10
US0_RTS #9 US1_TX
PRS_CH0 #11 PRS_CH9
#14 US1_RX #13
#14 PRS_CH10 #3
US1_CLK #12 US1_CS PRS_CH11 #2 ACMP0_O
#11 US1_CTS #10
#14 ACMP1_O #14
US1_RTS #9 LEU0_TX
ETM_TD2 #3
#14 LEU0_RX #13
I2C0_SDA #14 I2C0_SCL
#13
silabs.com | Building a more connected world.
Communication
Other
Rev. 1.2 | 75
EFM32JG12 Family Data Sheet
Pin Definitions
GPIO Name
PC7
PF8
PF2
Pin Alternate Functionality / Description
Analog
Timers
BUSAY BUSBX
TIM0_CC0 #12
TIM0_CC1 #11
TIM0_CC2 #10
TIM0_CDTI0 #9
TIM0_CDTI1 #8
TIM0_CDTI2 #7
TIM1_CC0 #12
TIM1_CC1 #11
TIM1_CC2 #10
TIM1_CC3 #9
WTIM0_CC0 #27
WTIM0_CC1 #25
WTIM0_CC2 #23
WTIM0_CDTI0 #19
WTIM0_CDTI1 #17
WTIM0_CDTI2 #15
WTIM1_CC0 #11
WTIM1_CC1 #9
WTIM1_CC2 #7
WTIM1_CC3 #5 LETIM0_OUT0 #12 LETIM0_OUT1 #11
PCNT0_S0IN #12
PCNT0_S1IN #11
BUSBY BUSAX
WTIM1_CC1 #30
WTIM1_CC2 #28
WTIM1_CC3 #26
PCNT1_S0IN #21
PCNT1_S1IN #20
PCNT2_S0IN #21
PCNT2_S1IN #20
BUSBY BUSAX
TIM0_CC0 #26
TIM0_CC1 #25
TIM0_CC2 #24
TIM0_CDTI0 #23
TIM0_CDTI1 #22
TIM0_CDTI2 #21
TIM1_CC0 #26
TIM1_CC1 #25
TIM1_CC2 #24
TIM1_CC3 #23
WTIM0_CDTI2 #30
WTIM1_CC0 #26
WTIM1_CC1 #24
WTIM1_CC2 #22
WTIM1_CC3 #20 LETIM0_OUT0 #26 LETIM0_OUT1 #25
PCNT0_S0IN #26
PCNT0_S1IN #25
silabs.com | Building a more connected world.
Communication
Other
US0_TX #12 US0_RX #11
US0_CLK #10 US0_CS
#9 US0_CTS #8
CMU_CLK1 #2 PRS_CH0
US0_RTS #7 US1_TX
#9 PRS_CH9 #12
#12 US1_RX #11
PRS_CH10 #1
US1_CLK #10 US1_CS
PRS_CH11 #0 ACMP0_O
#9 US1_CTS #8
#12 ACMP1_O #12
US1_RTS #7 LEU0_TX
ETM_TD0 #3
#12 LEU0_RX #11
I2C0_SDA #12 I2C0_SCL
#11
US2_TX #21 US2_RX #20
US2_CLK #19 US2_CS
#18 US2_CTS #17
US2_RTS #16 I2C1_SDA
#21 I2C1_SCL #20
ETM_TCLK #0
US0_TX #26 US0_RX #25
US0_CLK #24 US0_CS
CMU_CLK0 #6 PRS_CH0
#23 US0_CTS #22
#2 PRS_CH1 #1
US0_RTS #21 US1_TX
PRS_CH2 #0 PRS_CH3
#26 US1_RX #25
#7 ACMP0_O #26
US1_CLK #24 US1_CS
ACMP1_O #26 DBG_TDO
#23 US1_CTS #22
DBG_SWO #0
US1_RTS #21 LEU0_TX
GPIO_EM4WU0
#26 LEU0_RX #25
I2C0_SDA #26 I2C0_SCL
#25
Rev. 1.2 | 76
EFM32JG12 Family Data Sheet
Pin Definitions
GPIO Name
PF0
PC4
PC1
PJ14
Pin Alternate Functionality / Description
Analog
Timers
Communication
Other
BUSBY BUSAX
TIM0_CC0 #24
TIM0_CC1 #23
TIM0_CC2 #22
TIM0_CDTI0 #21
TIM0_CDTI1 #20
TIM0_CDTI2 #19
TIM1_CC0 #24
TIM1_CC1 #23
TIM1_CC2 #22
TIM1_CC3 #21
WTIM0_CDTI1 #30
WTIM0_CDTI2 #28
WTIM1_CC0 #24
WTIM1_CC1 #22
WTIM1_CC2 #20
WTIM1_CC3 #18 LETIM0_OUT0 #24 LETIM0_OUT1 #23
PCNT0_S0IN #24
PCNT0_S1IN #23
US0_TX #24 US0_RX #23
US0_CLK #22 US0_CS
#21 US0_CTS #20
US0_RTS #19 US1_TX
#24 US1_RX #23
US1_CLK #22 US1_CS
#21 US1_CTS #20
US1_RTS #19 US2_TX
#14 US2_RX #13
US2_CLK #12 US2_CS
#11 US2_CTS #10
US2_RTS #9 LEU0_TX
#24 LEU0_RX #23
I2C0_SDA #24 I2C0_SCL
#23
PRS_CH0 #0 PRS_CH1
#7 PRS_CH2 #6
PRS_CH3 #5 ACMP0_O
#24 ACMP1_O #24
DBG_SWCLKTCK
BOOT_TX
BUSBY BUSAX
WTIM0_CC0 #24
WTIM0_CC1 #22
WTIM0_CC2 #20
WTIM0_CDTI0 #16
WTIM0_CDTI1 #14
WTIM0_CDTI2 #12
WTIM1_CC0 #8
WTIM1_CC1 #6
WTIM1_CC2 #4
WTIM1_CC3 #2
PCNT1_S0IN #17
PCNT1_S1IN #16
PCNT2_S0IN #17
PCNT2_S1IN #16
US3_TX #22 US3_RX #21
US3_CLK #20 US3_CS
#19 US3_CTS #18
US3_RTS #17 I2C1_SDA
#17 I2C1_SCL #16
BUSAY BUSBX
WTIM0_CC0 #21
WTIM0_CC1 #19
WTIM0_CC2 #17
WTIM0_CDTI0 #13
WTIM0_CDTI1 #11
WTIM0_CDTI2 #9
WTIM1_CC0 #5
WTIM1_CC1 #3
WTIM1_CC2 #1
PCNT1_S0IN #14
PCNT1_S1IN #13
PCNT2_S0IN #14
PCNT2_S1IN #13
US3_TX #19 US3_RX #18
US3_CLK #17 US3_CS
#16 US3_CTS #15
US3_RTS #14 I2C1_SDA
#14 I2C1_SCL #13
BUSACMP1Y BUSACMP1X
PCNT1_S0IN #11
PCNT1_S1IN #10
PCNT2_S0IN #11
PCNT2_S1IN #10
US3_TX #16 US3_RX #15
US3_CLK #14 US3_CS
#13 US3_CTS #12
US3_RTS #11 I2C1_SDA
#11 I2C1_SCL #10
silabs.com | Building a more connected world.
LES_ALTEX2
Rev. 1.2 | 77
EFM32JG12 Family Data Sheet
Pin Definitions
GPIO Name
PC10
PC8
Pin Alternate Functionality / Description
Analog
Timers
BUSBY BUSAX
TIM0_CC0 #15
TIM0_CC1 #14
TIM0_CC2 #13
TIM0_CDTI0 #12
TIM0_CDTI1 #11
TIM0_CDTI2 #10
TIM1_CC0 #15
TIM1_CC1 #14
TIM1_CC2 #13
TIM1_CC3 #12
WTIM0_CC0 #30
WTIM0_CC1 #28
WTIM0_CC2 #26
WTIM0_CDTI0 #22
WTIM0_CDTI1 #20
WTIM0_CDTI2 #18
WTIM1_CC0 #14
WTIM1_CC1 #12
WTIM1_CC2 #10
WTIM1_CC3 #8 LETIM0_OUT0 #15 LETIM0_OUT1 #14
PCNT0_S0IN #15
PCNT0_S1IN #14
PCNT2_S0IN #19
PCNT2_S1IN #18
US0_TX #15 US0_RX #14
US0_CLK #13 US0_CS
#12 US0_CTS #11
CMU_CLK1 #3 PRS_CH0
US0_RTS #10 US1_TX
#12 PRS_CH9 #15
#15 US1_RX #14
PRS_CH10 #4
US1_CLK #13 US1_CS
PRS_CH11 #3 ACMP0_O
#12 US1_CTS #11
#15 ACMP1_O #15
US1_RTS #10 LEU0_TX
ETM_TD3 #3
#15 LEU0_RX #14
GPIO_EM4WU12
I2C0_SDA #15 I2C0_SCL
#14 I2C1_SDA #19
I2C1_SCL #18
BUSBY BUSAX
TIM0_CC0 #13
TIM0_CC1 #12
TIM0_CC2 #11
TIM0_CDTI0 #10
TIM0_CDTI1 #9
TIM0_CDTI2 #8
TIM1_CC0 #13
TIM1_CC1 #12
TIM1_CC2 #11
TIM1_CC3 #10
WTIM0_CC0 #28
WTIM0_CC1 #26
WTIM0_CC2 #24
WTIM0_CDTI0 #20
WTIM0_CDTI1 #18
WTIM0_CDTI2 #16
WTIM1_CC0 #12
WTIM1_CC1 #10
WTIM1_CC2 #8
WTIM1_CC3 #6 LETIM0_OUT0 #13 LETIM0_OUT1 #12
PCNT0_S0IN #13
PCNT0_S1IN #12
US0_TX #13 US0_RX #12
US0_CLK #11 US0_CS
#10 US0_CTS #9
US0_RTS #8 US1_TX
PRS_CH0 #10 PRS_CH9
#13 US1_RX #12
#13 PRS_CH10 #2
US1_CLK #11 US1_CS PRS_CH11 #1 ACMP0_O
#10 US1_CTS #9
#13 ACMP1_O #13
US1_RTS #8 LEU0_TX
ETM_TD1 #3
#13 LEU0_RX #12
I2C0_SDA #13 I2C0_SCL
#12
silabs.com | Building a more connected world.
Communication
Other
Rev. 1.2 | 78
EFM32JG12 Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
PC6
PF11
PF10
PF9
Timers
Communication
Other
BUSBY BUSAX
TIM0_CC0 #11
TIM0_CC1 #10
TIM0_CC2 #9
TIM0_CDTI0 #8
TIM0_CDTI1 #7
TIM0_CDTI2 #6
TIM1_CC0 #11
US0_TX #11 US0_RX #10
TIM1_CC1 #10
US0_CLK #9 US0_CS #8
TIM1_CC2 #9 TIM1_CC3
CMU_CLK0 #2
US0_CTS #7 US0_RTS
#8 WTIM0_CC0 #26
CMU_CLKI0 #2
#6 US1_TX #11 US1_RX
WTIM0_CC1 #24
PRS_CH0 #8 PRS_CH9
#10 US1_CLK #9
WTIM0_CC2 #22
#11 PRS_CH10 #0
US1_CS #8 US1_CTS #7
WTIM0_CDTI0 #18
PRS_CH11 #5 ACMP0_O
US1_RTS #6 LEU0_TX
WTIM0_CDTI1 #16
#11 ACMP1_O #11
#11 LEU0_RX #10
WTIM0_CDTI2 #14
ETM_TCLK #3
I2C0_SDA #11 I2C0_SCL
WTIM1_CC0 #10
#10
WTIM1_CC1 #8
WTIM1_CC2 #6
WTIM1_CC3 #4 LETIM0_OUT0 #11 LETIM0_OUT1 #10
PCNT0_S0IN #11
PCNT0_S1IN #10
BUSAY BUSBX
WTIM1_CC2 #31
WTIM1_CC3 #29
PCNT1_S0IN #24
PCNT1_S1IN #23
PCNT2_S0IN #24
PCNT2_S1IN #23
US2_TX #24 US2_RX #23
US2_CLK #22 US2_CS
#21 US2_CTS #20
US2_RTS #19 US3_TX
#24 US3_RX #23
US3_CLK #22 US3_CS
#21 US3_CTS #20
US3_RTS #19 I2C1_SDA
#24 I2C1_SCL #23
ETM_TD2 #0
BUSBY BUSAX
WTIM1_CC2 #30
WTIM1_CC3 #28
PCNT1_S0IN #23
PCNT1_S1IN #22
PCNT2_S0IN #23
PCNT2_S1IN #22
US2_TX #23 US2_RX #22
US2_CLK #21 US2_CS
#20 US2_CTS #19
US2_RTS #18 I2C1_SDA
#23 I2C1_SCL #22
ETM_TD1 #0
BUSAY BUSBX
WTIM1_CC1 #31
WTIM1_CC2 #29
WTIM1_CC3 #27
PCNT1_S0IN #22
PCNT1_S1IN #21
PCNT2_S0IN #22
PCNT2_S1IN #21
US2_TX #22 US2_RX #21
US2_CLK #20 US2_CS
#19 US2_CTS #18
US2_RTS #17 I2C1_SDA
#22 I2C1_SCL #21
ETM_TD0 #0
silabs.com | Building a more connected world.
Rev. 1.2 | 79
EFM32JG12 Family Data Sheet
Pin Definitions
GPIO Name
PC2
PJ15
PB15
PB14
Pin Alternate Functionality / Description
Analog
Timers
Communication
BUSBY BUSAX
WTIM0_CC0 #22
WTIM0_CC1 #20
WTIM0_CC2 #18
WTIM0_CDTI0 #14
WTIM0_CDTI1 #12
WTIM0_CDTI2 #10
WTIM1_CC0 #6
WTIM1_CC1 #4
WTIM1_CC2 #2
WTIM1_CC3 #0
PCNT1_S0IN #15
PCNT1_S1IN #14
PCNT2_S0IN #15
PCNT2_S1IN #14
US3_TX #20 US3_RX #19
US3_CLK #18 US3_CS
#17 US3_CTS #16
US3_RTS #15 I2C1_SDA
#15 I2C1_SCL #14
BUSACMP1Y BUSACMP1X
PCNT1_S0IN #12
PCNT1_S1IN #11
PCNT2_S0IN #12
PCNT2_S1IN #11
US3_TX #17 US3_RX #16
US3_CLK #15 US3_CS
#14 US3_CTS #13
US3_RTS #12 I2C1_SDA
#12 I2C1_SCL #11
BUSCY BUSDX
LFXTAL_P
TIM0_CC0 #10
TIM0_CC1 #9 TIM0_CC2
#8 TIM0_CDTI0 #7
TIM0_CDTI1 #6
TIM0_CDTI2 #5
TIM1_CC0 #10
TIM1_CC1 #9 TIM1_CC2
#8 TIM1_CC3 #7
WTIM0_CC0 #19
WTIM0_CC1 #17
WTIM0_CC2 #15
WTIM0_CDTI0 #11
WTIM0_CDTI1 #9
WTIM0_CDTI2 #7
WTIM1_CC0 #3
WTIM1_CC1 #1 LETIM0_OUT0 #10 LETIM0_OUT1 #9
PCNT0_S0IN #10
PCNT0_S1IN #9
US0_TX #10 US0_RX #9
US0_CLK #8 US0_CS #7
US0_CTS #6 US0_RTS
CMU_CLK0 #1 PRS_CH6
#5 US1_TX #10 US1_RX
#10 PRS_CH7 #9
#9 US1_CLK #8 US1_CS
PRS_CH8 #8 PRS_CH9
#7 US1_CTS #6
#7 ACMP0_O #10
US1_RTS #5 LEU0_TX
ACMP1_O #10
#10 LEU0_RX #9
I2C0_SDA #10 I2C0_SCL
#9
BUSDY BUSCX
LFXTAL_N
TIM0_CC0 #9 TIM0_CC1
#8 TIM0_CC2 #7
TIM0_CDTI0 #6
TIM0_CDTI1 #5
TIM0_CDTI2 #4
TIM1_CC0 #9 TIM1_CC1
#8 TIM1_CC2 #7
TIM1_CC3 #6
WTIM0_CC0 #18
WTIM0_CC1 #16
WTIM0_CC2 #14
WTIM0_CDTI0 #10
WTIM0_CDTI1 #8
WTIM0_CDTI2 #6
WTIM1_CC0 #2
WTIM1_CC1 #0 LETIM0_OUT0 #9 LETIM0_OUT1 #8
PCNT0_S0IN #9
PCNT0_S1IN #8
US0_TX #9 US0_RX #8
US0_CLK #7 US0_CS #6
US0_CTS #5 US0_RTS
CMU_CLK1 #1 PRS_CH6
#4 US1_TX #9 US1_RX
#9 PRS_CH7 #8
#8 US1_CLK #7 US1_CS
PRS_CH8 #7 PRS_CH9
#6 US1_CTS #5
#6 ACMP0_O #9
US1_RTS #4 LEU0_TX
ACMP1_O #9
#9 LEU0_RX #8
I2C0_SDA #9 I2C0_SCL
#8
silabs.com | Building a more connected world.
Other
LES_ALTEX3
Rev. 1.2 | 80
EFM32JG12 Family Data Sheet
Pin Definitions
GPIO Name
PB13
PB12
PF14
PF13
Pin Alternate Functionality / Description
Analog
Timers
Communication
Other
BUSCY BUSDX OPA2_N
TIM0_CC0 #8 TIM0_CC1
#7 TIM0_CC2 #6
TIM0_CDTI0 #5
TIM0_CDTI1 #4
TIM0_CDTI2 #3
TIM1_CC0 #8 TIM1_CC1
#7 TIM1_CC2 #6
TIM1_CC3 #5
WTIM0_CC0 #17
WTIM0_CC1 #15
WTIM0_CC2 #13
WTIM0_CDTI0 #9
WTIM0_CDTI1 #7
WTIM0_CDTI2 #5
WTIM1_CC0 #1 LETIM0_OUT0 #8 LETIM0_OUT1 #7
PCNT0_S0IN #8
PCNT0_S1IN #7
US0_TX #8 US0_RX #7
US0_CLK #6 US0_CS #5
US0_CTS #4 US0_RTS
#3 US1_TX #8 US1_RX
#7 US1_CLK #6 US1_CS
#5 US1_CTS #4
US1_RTS #3 LEU0_TX
#8 LEU0_RX #7
I2C0_SDA #8 I2C0_SCL
#7
CMU_CLKI0 #0
PRS_CH6 #8 PRS_CH7
#7 PRS_CH8 #6
PRS_CH9 #5 ACMP0_O
#8 ACMP1_O #8
DBG_SWO #1
GPIO_EM4WU9
BUSDY BUSCX
OPA2_OUT
TIM0_CC0 #7 TIM0_CC1
#6 TIM0_CC2 #5
TIM0_CDTI0 #4
TIM0_CDTI1 #3
TIM0_CDTI2 #2
TIM1_CC0 #7 TIM1_CC1
#6 TIM1_CC2 #5
TIM1_CC3 #4
WTIM0_CC0 #16
WTIM0_CC1 #14
WTIM0_CC2 #12
WTIM0_CDTI0 #8
WTIM0_CDTI1 #6
WTIM0_CDTI2 #4
WTIM1_CC0 #0 LETIM0_OUT0 #7 LETIM0_OUT1 #6
PCNT0_S0IN #7
PCNT0_S1IN #6
US0_TX #7 US0_RX #6
US0_CLK #5 US0_CS #4
US0_CTS #3 US0_RTS
#2 US1_TX #7 US1_RX
#6 US1_CLK #5 US1_CS
#4 US1_CTS #3
US1_RTS #2 LEU0_TX
#7 LEU0_RX #6
I2C0_SDA #7 I2C0_SCL
#6
PRS_CH6 #7 PRS_CH7
#6 PRS_CH8 #5
PRS_CH9 #4 ACMP0_O
#7 ACMP1_O #7
PCNT1_S0IN #27
PCNT1_S1IN #26
PCNT2_S0IN #27
PCNT2_S1IN #26
US2_TX #27 US2_RX #26
US2_CLK #25 US2_CS
#24 US2_CTS #23
US2_RTS #22 US3_TX
#27 US3_RX #26
US3_CLK #25 US3_CS
#24 US3_CTS #23
US3_RTS #22 I2C1_SDA
#27 I2C1_SCL #26
WTIM1_CC3 #31
PCNT1_S0IN #26
PCNT1_S1IN #25
PCNT2_S0IN #26
PCNT2_S1IN #25
US2_TX #26 US2_RX #25
US2_CLK #24 US2_CS
#23 US2_CTS #22
US2_RTS #21 US3_TX
#26 US3_RX #25
US3_CLK #24 US3_CS
#23 US3_CTS #22
US3_RTS #21 I2C1_SDA
#26 I2C1_SCL #25
BUSBY BUSAX
BUSAY BUSBX
silabs.com | Building a more connected world.
Rev. 1.2 | 81
EFM32JG12 Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
PF12
PB11
PB10
PB9
Timers
Communication
Other
BUSBY BUSAX
WTIM1_CC3 #30
PCNT1_S0IN #25
PCNT1_S1IN #24
PCNT2_S0IN #25
PCNT2_S1IN #24
US2_TX #25 US2_RX #24
US2_CLK #23 US2_CS
#22 US2_CTS #21
US2_RTS #20 US3_TX
#25 US3_RX #24
US3_CLK #23 US3_CS
#22 US3_CTS #21
US3_RTS #20 I2C1_SDA
#25 I2C1_SCL #24
ETM_TD3 #0
BUSCY BUSDX OPA2_P
TIM0_CC0 #6 TIM0_CC1
#5 TIM0_CC2 #4
TIM0_CDTI0 #3
TIM0_CDTI1 #2
TIM0_CDTI2 #1
TIM1_CC0 #6 TIM1_CC1
#5 TIM1_CC2 #4
TIM1_CC3 #3
WTIM0_CC0 #15
WTIM0_CC1 #13
WTIM0_CC2 #11
WTIM0_CDTI0 #7
WTIM0_CDTI1 #5
WTIM0_CDTI2 #3 LETIM0_OUT0 #6 LETIM0_OUT1 #5
PCNT0_S0IN #6
PCNT0_S1IN #5
US0_TX #6 US0_RX #5
US0_CLK #4 US0_CS #3
US0_CTS #2 US0_RTS
#1 US1_TX #6 US1_RX
#5 US1_CLK #4 US1_CS
#3 US1_CTS #2
US1_RTS #1 US3_TX
#15 US3_RX #14
US3_CLK #13 US3_CS
#12 US3_CTS #11
US3_RTS #10 LEU0_TX
#6 LEU0_RX #5
I2C0_SDA #6 I2C0_SCL
#5
PRS_CH6 #6 PRS_CH7
#5 PRS_CH8 #4
PRS_CH9 #3 ACMP0_O
#6 ACMP1_O #6
OPA2_OUTALT #1 BUSDY BUSCX
WTIM0_CC0 #14
WTIM0_CC1 #12
WTIM0_CC2 #10
WTIM0_CDTI0 #6
WTIM0_CDTI1 #4
WTIM0_CDTI2 #2
PCNT1_S0IN #10
PCNT1_S1IN #9
PCNT2_S0IN #10
PCNT2_S1IN #9
US2_TX #13 US2_RX #12
US2_CLK #11 US2_CS
#10 US2_CTS #9
US2_RTS #8 US3_TX
#14 US3_RX #13
US3_CLK #12 US3_CS
#11 US3_CTS #10
US3_RTS #9 I2C1_SDA
#10 I2C1_SCL #9
OPA2_OUTALT #0 BUSCY BUSDX
WTIM0_CC0 #13
WTIM0_CC1 #11
WTIM0_CC2 #9
WTIM0_CDTI0 #5
WTIM0_CDTI1 #3
WTIM0_CDTI2 #1
PCNT1_S0IN #9
PCNT1_S1IN #8
PCNT2_S0IN #9
PCNT2_S1IN #8
US2_TX #12 US2_RX #11
US2_CLK #10 US2_CS
#9 US2_CTS #8
US2_RTS #7 US3_TX
#13 US3_RX #12
US3_CLK #11 US3_CS
#10 US3_CTS #9
US3_RTS #8 I2C1_SDA
#9 I2C1_SCL #8
PCNT1_S0IN #30
PCNT1_S1IN #29
PCNT2_S0IN #30
PCNT2_S1IN #29
US2_TX #30 US2_RX #29
US2_CLK #28 US2_CS
#27 US2_CTS #26
US2_RTS #25 US3_TX
#30 US3_RX #29
US3_CLK #28 US3_CS
#27 US3_CTS #26
US3_RTS #25 I2C1_SDA
#30 I2C1_SCL #29
PK1
silabs.com | Building a more connected world.
Rev. 1.2 | 82
EFM32JG12 Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
PCNT1_S0IN #29
PCNT1_S1IN #28
PCNT2_S0IN #29
PCNT2_S1IN #28
US2_TX #29 US2_RX #28
US2_CLK #27 US2_CS
#26 US2_CTS #25
US2_RTS #24 US3_TX
#29 US3_RX #28
US3_CLK #27 US3_CS
#26 US3_CTS #25
US3_RTS #24 I2C1_SDA
#29 I2C1_SCL #28
BUSAY BUSBX
PCNT1_S0IN #28
PCNT1_S1IN #27
PCNT2_S0IN #28
PCNT2_S1IN #27
US2_TX #28 US2_RX #27
US2_CLK #26 US2_CS
#25 US2_CTS #24
US2_RTS #23 US3_TX
#28 US3_RX #27
US3_CLK #26 US3_CS
#25 US3_CTS #24
US3_RTS #23 I2C1_SDA
#28 I2C1_SCL #27
BUSDY BUSCX
WTIM0_CC0 #12
WTIM0_CC1 #10
WTIM0_CC2 #8
WTIM0_CDTI0 #4
WTIM0_CDTI1 #2
WTIM0_CDTI2 #0
PCNT1_S0IN #8
PCNT1_S1IN #7
PCNT2_S0IN #8
PCNT2_S1IN #7
US2_TX #11 US2_RX #10
US2_CLK #9 US2_CS #8
US2_CTS #7 US2_RTS
#6 US3_TX #12 US3_RX
#11 US3_CLK #10
US3_CS #9 US3_CTS #8
US3_RTS #7 I2C1_SDA
#8 I2C1_SCL #7
ETM_TD3 #2
BUSCY BUSDX
WTIM0_CC0 #11
WTIM0_CC1 #9
WTIM0_CC2 #7
WTIM0_CDTI0 #3
WTIM0_CDTI1 #1
PCNT1_S0IN #7
PCNT1_S1IN #6
PCNT2_S0IN #7
PCNT2_S1IN #6
US2_TX #10 US2_RX #9
US2_CLK #8 US2_CS #7
US2_CTS #6 US2_RTS
#5 US3_TX #11 US3_RX
#10 US3_CLK #9
US3_CS #8 US3_CTS #7
US3_RTS #6 I2C1_SDA
#7 I2C1_SCL #6
ETM_TD2 #2
PK2
PCNT1_S0IN #31
PCNT1_S1IN #30
PCNT2_S0IN #31
PCNT2_S1IN #30
US2_TX #31 US2_RX #30
US2_CLK #29 US2_CS
#28 US2_CTS #27
US2_RTS #26 US3_TX
#31 US3_RX #30
US3_CLK #29 US3_CS
#28 US3_CTS #27
US3_RTS #26 I2C1_SDA
#31 I2C1_SCL #30
PB6
WTIM0_CC0 #10
WTIM0_CC1 #8
WTIM0_CC2 #6
WTIM0_CDTI0 #2
WTIM0_CDTI1 #0
PCNT1_S0IN #6
PCNT1_S1IN #5
PCNT2_S0IN #6
PCNT2_S1IN #5
US2_TX #9 US2_RX #8
US2_CLK #7 US2_CS #6
US2_CTS #5 US2_RTS
#4 US3_TX #10 US3_RX CMU_CLKI0 #3 ETM_TD1
#9 US3_CLK #8 US3_CS
#2
#7 US3_CTS #6
US3_RTS #5 I2C1_SDA
#6 I2C1_SCL #5
PK0
PF15
PB8
PB7
IDAC0_OUT
BUSDY BUSCX
silabs.com | Building a more connected world.
Other
Rev. 1.2 | 83
EFM32JG12 Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
PI3
PF5
PF4
PI2
PI1
Timers
Communication
Other
BUSADC0Y BUSADC0X
PCNT1_S0IN #5
PCNT1_S1IN #4
PCNT2_S0IN #5
PCNT2_S1IN #4
US2_TX #8 US2_RX #7
US2_CLK #6 US2_CS #5
US2_CTS #4 US2_RTS
#3 US3_TX #9 US3_RX
#8 US3_CLK #7 US3_CS
#6 US3_CTS #5
US3_RTS #4 I2C1_SDA
#5 I2C1_SCL #4
LES_ALTEX7 ETM_TD0
#2
BUSAY BUSBX
TIM0_CC0 #29
TIM0_CC1 #28
TIM0_CC2 #27
TIM0_CDTI0 #26
TIM0_CDTI1 #25
TIM0_CDTI2 #24
TIM1_CC0 #29
TIM1_CC1 #28
TIM1_CC2 #27
TIM1_CC3 #26
WTIM1_CC0 #29
WTIM1_CC1 #27
WTIM1_CC2 #25
WTIM1_CC3 #23 LETIM0_OUT0 #29 LETIM0_OUT1 #28
PCNT0_S0IN #29
PCNT0_S1IN #28
US0_TX #29 US0_RX #28
US0_CLK #27 US0_CS
#26 US0_CTS #25
US0_RTS #24 US1_TX
#29 US1_RX #28
US1_CLK #27 US1_CS
#26 US1_CTS #25
US1_RTS #24 US2_TX
#18 US2_RX #17
US2_CLK #16 US2_CS
#15 US2_CTS #14
US2_RTS #13 LEU0_TX
#29 LEU0_RX #28
I2C0_SDA #29 I2C0_SCL
#28
PRS_CH0 #5 PRS_CH1
#4 PRS_CH2 #3
PRS_CH3 #2 ACMP0_O
#29 ACMP1_O #29
BUSBY BUSAX
TIM0_CC0 #28
TIM0_CC1 #27
TIM0_CC2 #26
TIM0_CDTI0 #25
TIM0_CDTI1 #24
TIM0_CDTI2 #23
TIM1_CC0 #28
TIM1_CC1 #27
TIM1_CC2 #26
TIM1_CC3 #25
WTIM1_CC0 #28
WTIM1_CC1 #26
WTIM1_CC2 #24
WTIM1_CC3 #22 LETIM0_OUT0 #28 LETIM0_OUT1 #27
PCNT0_S0IN #28
PCNT0_S1IN #27
US0_TX #28 US0_RX #27
US0_CLK #26 US0_CS
#25 US0_CTS #24
US0_RTS #23 US1_TX
#28 US1_RX #27
US1_CLK #26 US1_CS
#25 US1_CTS #24
US1_RTS #23 US2_TX
#17 US2_RX #16
US2_CLK #15 US2_CS
#14 US2_CTS #13
US2_RTS #12 LEU0_TX
#28 LEU0_RX #27
I2C0_SDA #28 I2C0_SCL
#27
PRS_CH0 #4 PRS_CH1
#3 PRS_CH2 #2
PRS_CH3 #1 ACMP0_O
#28 ACMP1_O #28
BUSADC0Y BUSADC0X
BUSADC0Y BUSADC0X
silabs.com | Building a more connected world.
PCNT1_S0IN #4
PCNT1_S1IN #3
PCNT2_S0IN #4
PCNT2_S1IN #3
US2_TX #7 US2_RX #6
US2_CLK #5 US2_CS #4
US2_CTS #3 US2_RTS
#2 US3_TX #8 US3_RX LES_ALTEX6 ETM_TCLK
#7 US3_CLK #6 US3_CS
#2
#5 US3_CTS #4
US3_RTS #3 I2C1_SDA
#4 I2C1_SCL #3
US2_TX #6 US2_RX #5
US2_CLK #4 US2_CS #3
US2_CTS #2 US2_RTS
#1
LES_ALTEX5
Rev. 1.2 | 84
EFM32JG12 Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
PI0
PF7
PF6
PA9
Timers
BUSADC0Y BUSADC0X
Communication
Other
US2_TX #5 US2_RX #4
US2_CLK #3 US2_CS #2
US2_CTS #1 US2_RTS
#0
LES_ALTEX4
BUSAY BUSBX
TIM0_CC0 #31
TIM0_CC1 #30
TIM0_CC2 #29
TIM0_CDTI0 #28
TIM0_CDTI1 #27
TIM0_CDTI2 #26
TIM1_CC0 #31
TIM1_CC1 #30
TIM1_CC2 #29
TIM1_CC3 #28
WTIM1_CC0 #31
WTIM1_CC1 #29
WTIM1_CC2 #27
WTIM1_CC3 #25 LETIM0_OUT0 #31 LETIM0_OUT1 #30
PCNT0_S0IN #31
PCNT0_S1IN #30
PCNT1_S0IN #20
PCNT1_S1IN #19
US0_TX #31 US0_RX #30
US0_CLK #29 US0_CS
#28 US0_CTS #27
US0_RTS #26 US1_TX
#31 US1_RX #30
CMU_CLKI0 #1
US1_CLK #29 US1_CS CMU_CLK0 #7 PRS_CH0
#28 US1_CTS #27
#7 PRS_CH1 #6
US1_RTS #26 US2_TX
PRS_CH2 #5 PRS_CH3
#20 US2_RX #19
#4 ACMP0_O #31
US2_CLK #18 US2_CS
ACMP1_O #31
#17 US2_CTS #16
GPIO_EM4WU1
US2_RTS #15 LEU0_TX
#31 LEU0_RX #30
I2C0_SDA #31 I2C0_SCL
#30
BUSBY BUSAX
TIM0_CC0 #30
TIM0_CC1 #29
TIM0_CC2 #28
TIM0_CDTI0 #27
TIM0_CDTI1 #26
TIM0_CDTI2 #25
TIM1_CC0 #30
TIM1_CC1 #29
TIM1_CC2 #28
TIM1_CC3 #27
WTIM1_CC0 #30
WTIM1_CC1 #28
WTIM1_CC2 #26
WTIM1_CC3 #24 LETIM0_OUT0 #30 LETIM0_OUT1 #29
PCNT0_S0IN #30
PCNT0_S1IN #29
PCNT1_S0IN #19
PCNT1_S1IN #18
US0_TX #30 US0_RX #29
US0_CLK #28 US0_CS
#27 US0_CTS #26
US0_RTS #25 US1_TX
#30 US1_RX #29
US1_CLK #28 US1_CS CMU_CLK1 #7 PRS_CH0
#27 US1_CTS #26
#6 PRS_CH1 #5
US1_RTS #25 US2_TX
PRS_CH2 #4 PRS_CH3
#19 US2_RX #18
#3 ACMP0_O #30
US2_CLK #17 US2_CS
ACMP1_O #30
#16 US2_CTS #15
US2_RTS #14 LEU0_TX
#30 LEU0_RX #29
I2C0_SDA #30 I2C0_SCL
#29
BUSACMP0Y BUSACMP0X
WTIM0_CC0 #9
WTIM0_CC1 #7
WTIM0_CC2 #5
WTIM0_CDTI0 #1
PCNT1_S0IN #3
PCNT1_S1IN #2
PCNT2_S0IN #3
PCNT2_S1IN #2
silabs.com | Building a more connected world.
US2_TX #4 US2_RX #3
US2_CLK #2 US2_CS #1
US2_CTS #0 US2_RTS
#31 I2C1_SDA #3
I2C1_SCL #2
LES_ALTEX1 ETM_TD3
#1
Rev. 1.2 | 85
EFM32JG12 Family Data Sheet
Pin Definitions
GPIO Name
PA8
PA7
PA6
PA5
PA4
Pin Alternate Functionality / Description
Analog
Timers
Communication
Other
BUSACMP0Y BUSACMP0X
WTIM0_CC0 #8
WTIM0_CC1 #6
WTIM0_CC2 #4
WTIM0_CDTI0 #0
PCNT1_S0IN #2
PCNT1_S1IN #1
PCNT2_S0IN #2
PCNT2_S1IN #1
US2_TX #3 US2_RX #2
US2_CLK #1 US2_CS #0
US2_CTS #31 US2_RTS
#30 I2C1_SDA #2
I2C1_SCL #1
LES_ALTEX0 ETM_TD2
#1
BUSCY BUSDX
WTIM0_CC0 #7
WTIM0_CC1 #5
WTIM0_CC2 #3
PCNT1_S0IN #1
PCNT1_S1IN #0
PCNT2_S0IN #1
PCNT2_S1IN #0
US2_TX #2 US2_RX #1
US2_CLK #0 US2_CS
#31 US2_CTS #30
US2_RTS #29 I2C1_SDA
#1 I2C1_SCL #0
LES_CH15 ETM_TD1 #1
BUSDY BUSCX
WTIM0_CC0 #6
WTIM0_CC1 #4
WTIM0_CC2 #2
PCNT1_S0IN #0
PCNT1_S1IN #31
PCNT2_S0IN #0
PCNT2_S1IN #31
US2_TX #1 US2_RX #0
US2_CLK #31 US2_CS
#30 US2_CTS #29
US2_RTS #28 I2C1_SDA
#0 I2C1_SCL #31
LES_CH14 ETM_TD0 #1
VDAC0_OUT0ALT /
OPA0_OUTALT #0 BUSCY BUSDX
TIM0_CC0 #5 TIM0_CC1
#4 TIM0_CC2 #3
TIM0_CDTI0 #2
TIM0_CDTI1 #1
TIM0_CDTI2 #0
TIM1_CC0 #5 TIM1_CC1
#4 TIM1_CC2 #3
TIM1_CC3 #2
WTIM0_CC0 #5
WTIM0_CC1 #3
WTIM0_CC2 #1 LETIM0_OUT0 #5 LETIM0_OUT1 #4
PCNT0_S0IN #5
PCNT0_S1IN #4
US0_TX #5 US0_RX #4
US0_CLK #3 US0_CS #2
US0_CTS #1 US0_RTS
#0 US1_TX #5 US1_RX
#4 US1_CLK #3 US1_CS
#2 US1_CTS #1
US1_RTS #0 US2_TX #0
US2_RX #31 US2_CLK
#30 US2_CS #29
US2_CTS #28 US2_RTS
#27 LEU0_TX #5
LEU0_RX #4 I2C0_SDA
#5 I2C0_SCL #4
CMU_CLKI0 #4
PRS_CH6 #5 PRS_CH7
#4 PRS_CH8 #3
PRS_CH9 #2 ACMP0_O
#5 ACMP1_O #5
LES_CH13 ETM_TCLK
#1
VDAC0_OUT1ALT /
OPA1_OUTALT #2 BUSDY BUSCX OPA0_N
TIM0_CC0 #4 TIM0_CC1
#3 TIM0_CC2 #2
TIM0_CDTI0 #1
TIM0_CDTI1 #0
TIM0_CDTI2 #31
TIM1_CC0 #4 TIM1_CC1
#3 TIM1_CC2 #2
TIM1_CC3 #1
WTIM0_CC0 #4
WTIM0_CC1 #2
WTIM0_CC2 #0 LETIM0_OUT0 #4 LETIM0_OUT1 #3
PCNT0_S0IN #4
PCNT0_S1IN #3
US0_TX #4 US0_RX #3
US0_CLK #2 US0_CS #1
US0_CTS #0 US0_RTS
#31 US1_TX #4 US1_RX
#3 US1_CLK #2 US1_CS
#1 US1_CTS #0
US1_RTS #31 LEU0_TX
#4 LEU0_RX #3
I2C0_SDA #4 I2C0_SCL
#3
PRS_CH6 #4 PRS_CH7
#3 PRS_CH8 #2
PRS_CH9 #1 ACMP0_O
#4 ACMP1_O #4
LES_CH12
silabs.com | Building a more connected world.
Rev. 1.2 | 86
EFM32JG12 Family Data Sheet
Pin Definitions
GPIO Name
PA3
PA2
PA1
Pin Alternate Functionality / Description
Analog
Timers
Communication
Other
BUSCY BUSDX
VDAC0_OUT0 /
OPA0_OUT
TIM0_CC0 #3 TIM0_CC1
#2 TIM0_CC2 #1
TIM0_CDTI0 #0
TIM0_CDTI1 #31
TIM0_CDTI2 #30
TIM1_CC0 #3 TIM1_CC1
#2 TIM1_CC2 #1
TIM1_CC3 #0
WTIM0_CC0 #3
WTIM0_CC1 #1 LETIM0_OUT0 #3 LETIM0_OUT1 #2
PCNT0_S0IN #3
PCNT0_S1IN #2
US0_TX #3 US0_RX #2
US0_CLK #1 US0_CS #0
US0_CTS #31 US0_RTS
#30 US1_TX #3 US1_RX
#2 US1_CLK #1 US1_CS
#0 US1_CTS #31
US1_RTS #30 LEU0_TX
#3 LEU0_RX #2
I2C0_SDA #3 I2C0_SCL
#2
PRS_CH6 #3 PRS_CH7
#2 PRS_CH8 #1
PRS_CH9 #0 ACMP0_O
#3 ACMP1_O #3
LES_CH11
GPIO_EM4WU8
VDAC0_OUT1ALT /
OPA1_OUTALT #1 BUSDY BUSCX OPA0_P
TIM0_CC0 #2 TIM0_CC1
#1 TIM0_CC2 #0
TIM0_CDTI0 #31
TIM0_CDTI1 #30
TIM0_CDTI2 #29
TIM1_CC0 #2 TIM1_CC1
#1 TIM1_CC2 #0
TIM1_CC3 #31
WTIM0_CC0 #2
WTIM0_CC1 #0 LETIM0_OUT0 #2 LETIM0_OUT1 #1
PCNT0_S0IN #2
PCNT0_S1IN #1
US0_TX #2 US0_RX #1
US0_CLK #0 US0_CS
#31 US0_CTS #30
PRS_CH6 #2 PRS_CH7
US0_RTS #29 US1_TX
#1 PRS_CH8 #0
#2 US1_RX #1 US1_CLK
PRS_CH9 #10 ACMP0_O
#0 US1_CS #31
#2 ACMP1_O #2
US1_CTS #30 US1_RTS
LES_CH10
#29 LEU0_TX #2
LEU0_RX #1 I2C0_SDA
#2 I2C0_SCL #1
BUSCY BUSDX
ADC0_EXTP
VDAC0_EXT
TIM0_CC0 #1 TIM0_CC1
#0 TIM0_CC2 #31
TIM0_CDTI0 #30
TIM0_CDTI1 #29
TIM0_CDTI2 #28
TIM1_CC0 #1 TIM1_CC1
#0 TIM1_CC2 #31
TIM1_CC3 #30
WTIM0_CC0 #1 LETIM0_OUT0 #1 LETIM0_OUT1 #0
PCNT0_S0IN #1
PCNT0_S1IN #0
US0_TX #1 US0_RX #0
US0_CLK #31 US0_CS
#30 US0_CTS #29
CMU_CLK0 #0 PRS_CH6
US0_RTS #28 US1_TX
#1 PRS_CH7 #0
#1 US1_RX #0 US1_CLK
PRS_CH8 #10 PRS_CH9
#31 US1_CS #30
#9 ACMP0_O #1
US1_CTS #29 US1_RTS
ACMP1_O #1 LES_CH9
#28 LEU0_TX #1
LEU0_RX #0 I2C0_SDA
#1 I2C0_SCL #0
silabs.com | Building a more connected world.
Rev. 1.2 | 87
EFM32JG12 Family Data Sheet
Pin Definitions
GPIO Name
PD9
PD11
Pin Alternate Functionality / Description
Analog
Timers
BUSCY BUSDX
TIM0_CC0 #17
TIM0_CC1 #16
TIM0_CC2 #15
TIM0_CDTI0 #14
TIM0_CDTI1 #13
TIM0_CDTI2 #12
TIM1_CC0 #17
TIM1_CC1 #16
TIM1_CC2 #15
TIM1_CC3 #14
WTIM0_CC1 #31
WTIM0_CC2 #29
WTIM0_CDTI0 #25
WTIM0_CDTI1 #23
WTIM0_CDTI2 #21
WTIM1_CC0 #17
WTIM1_CC1 #15
WTIM1_CC2 #13
WTIM1_CC3 #11 LETIM0_OUT0 #17 LETIM0_OUT1 #16
PCNT0_S0IN #17
PCNT0_S1IN #16
US0_TX #17 US0_RX #16
US0_CLK #15 US0_CS
#14 US0_CTS #13
US0_RTS #12 US1_TX
#17 US1_RX #16
CMU_CLK0 #4 PRS_CH3
US1_CLK #15 US1_CS
#8 PRS_CH4 #0
#14 US1_CTS #13
PRS_CH5 #6 PRS_CH6
US1_RTS #12 US3_TX
#11 ACMP0_O #17
#1 US3_RX #0 US3_CLK
ACMP1_O #17 LES_CH1
#31 US3_CS #30
US3_CTS #29 US3_RTS
#28 LEU0_TX #17
LEU0_RX #16 I2C0_SDA
#17 I2C0_SCL #16
BUSCY BUSDX
TIM0_CC0 #19
TIM0_CC1 #18
TIM0_CC2 #17
TIM0_CDTI0 #16
TIM0_CDTI1 #15
TIM0_CDTI2 #14
TIM1_CC0 #19
TIM1_CC1 #18
TIM1_CC2 #17
TIM1_CC3 #16
WTIM0_CC2 #31
WTIM0_CDTI0 #27
WTIM0_CDTI1 #25
WTIM0_CDTI2 #23
WTIM1_CC0 #19
WTIM1_CC1 #17
WTIM1_CC2 #15
WTIM1_CC3 #13 LETIM0_OUT0 #19 LETIM0_OUT1 #18
PCNT0_S0IN #19
PCNT0_S1IN #18
US0_TX #19 US0_RX #18
US0_CLK #17 US0_CS
#16 US0_CTS #15
US0_RTS #14 US1_TX
#19 US1_RX #18
PRS_CH3 #10 PRS_CH4
US1_CLK #17 US1_CS
#2 PRS_CH5 #1
#16 US1_CTS #15
PRS_CH6 #13 ACMP0_O
US1_RTS #14 US3_TX
#19 ACMP1_O #19
#3 US3_RX #2 US3_CLK
LES_CH3
#1 US3_CS #0 US3_CTS
#31 US3_RTS #30
LEU0_TX #19 LEU0_RX
#18 I2C0_SDA #19
I2C0_SCL #18
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Rev. 1.2 | 88
EFM32JG12 Family Data Sheet
Pin Definitions
GPIO Name
PD13
PA0
PD8
Pin Alternate Functionality / Description
Analog
Timers
VDAC0_OUT0ALT /
OPA0_OUTALT #1 BUSCY BUSDX OPA1_P
TIM0_CC0 #21
TIM0_CC1 #20
TIM0_CC2 #19
TIM0_CDTI0 #18
TIM0_CDTI1 #17
TIM0_CDTI2 #16
TIM1_CC0 #21
TIM1_CC1 #20
TIM1_CC2 #19
TIM1_CC3 #18
WTIM0_CDTI0 #29
WTIM0_CDTI1 #27
WTIM0_CDTI2 #25
WTIM1_CC0 #21
WTIM1_CC1 #19
WTIM1_CC2 #17
WTIM1_CC3 #15 LETIM0_OUT0 #21 LETIM0_OUT1 #20
PCNT0_S0IN #21
PCNT0_S1IN #20
BUSDY BUSCX
ADC0_EXTN
TIM0_CC0 #0 TIM0_CC1
#31 TIM0_CC2 #30
TIM0_CDTI0 #29
TIM0_CDTI1 #28
TIM0_CDTI2 #27
TIM1_CC0 #0 TIM1_CC1
#31 TIM1_CC2 #30
TIM1_CC3 #29
WTIM0_CC0 #0 LETIM0_OUT0 #0 LETIM0_OUT1 #31
PCNT0_S0IN #0
PCNT0_S1IN #31
US0_TX #0 US0_RX #31
US0_CLK #30 US0_CS
#29 US0_CTS #28
US0_RTS #27 US1_TX
#0 US1_RX #31
US1_CLK #30 US1_CS
#29 US1_CTS #28
US1_RTS #27 LEU0_TX
#0 LEU0_RX #31
I2C0_SDA #0 I2C0_SCL
#31
CMU_CLK1 #0 PRS_CH6
#0 PRS_CH7 #10
PRS_CH8 #9 PRS_CH9
#8 ACMP0_O #0
ACMP1_O #0 LES_CH8
BUSDY BUSCX
WTIM0_CC1 #30
WTIM0_CC2 #28
WTIM0_CDTI0 #24
WTIM0_CDTI1 #22
WTIM0_CDTI2 #20
WTIM1_CC0 #16
WTIM1_CC1 #14
WTIM1_CC2 #12
WTIM1_CC3 #10
US3_TX #0 US3_RX #31
US3_CLK #30 US3_CS
#29 US3_CTS #28
US3_RTS #27
LES_CH0
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US0_TX #21 US0_RX #20
US0_CLK #19 US0_CS
#18 US0_CTS #17
US0_RTS #16 US1_TX
#21 US1_RX #20
PRS_CH3 #12 PRS_CH4
US1_CLK #19 US1_CS
#4 PRS_CH5 #3
#18 US1_CTS #17
PRS_CH6 #15 ACMP0_O
US1_RTS #16 US3_TX
#21 ACMP1_O #21
#5 US3_RX #4 US3_CLK
LES_CH5
#3 US3_CS #2 US3_CTS
#1 US3_RTS #0
LEU0_TX #21 LEU0_RX
#20 I2C0_SDA #21
I2C0_SCL #20
Rev. 1.2 | 89
EFM32JG12 Family Data Sheet
Pin Definitions
GPIO Name
PD10
PD12
Pin Alternate Functionality / Description
Analog
Timers
BUSDY BUSCX
TIM0_CC0 #18
TIM0_CC1 #17
TIM0_CC2 #16
TIM0_CDTI0 #15
TIM0_CDTI1 #14
TIM0_CDTI2 #13
TIM1_CC0 #18
TIM1_CC1 #17
TIM1_CC2 #16
TIM1_CC3 #15
WTIM0_CC2 #30
WTIM0_CDTI0 #26
WTIM0_CDTI1 #24
WTIM0_CDTI2 #22
WTIM1_CC0 #18
WTIM1_CC1 #16
WTIM1_CC2 #14
WTIM1_CC3 #12 LETIM0_OUT0 #18 LETIM0_OUT1 #17
PCNT0_S0IN #18
PCNT0_S1IN #17
US0_TX #18 US0_RX #17
US0_CLK #16 US0_CS
#15 US0_CTS #14
US0_RTS #13 US1_TX
#18 US1_RX #17
CMU_CLK1 #4 PRS_CH3
US1_CLK #16 US1_CS
#9 PRS_CH4 #1
#15 US1_CTS #14
PRS_CH5 #0 PRS_CH6
US1_RTS #13 US3_TX
#12 ACMP0_O #18
#2 US3_RX #1 US3_CLK
ACMP1_O #18 LES_CH2
#0 US3_CS #31
US3_CTS #30 US3_RTS
#29 LEU0_TX #18
LEU0_RX #17 I2C0_SDA
#18 I2C0_SCL #17
VDAC0_OUT1ALT /
OPA1_OUTALT #0 BUSDY BUSCX
TIM0_CC0 #20
TIM0_CC1 #19
TIM0_CC2 #18
TIM0_CDTI0 #17
TIM0_CDTI1 #16
TIM0_CDTI2 #15
TIM1_CC0 #20
TIM1_CC1 #19
TIM1_CC2 #18
TIM1_CC3 #17
WTIM0_CDTI0 #28
WTIM0_CDTI1 #26
WTIM0_CDTI2 #24
WTIM1_CC0 #20
WTIM1_CC1 #18
WTIM1_CC2 #16
WTIM1_CC3 #14 LETIM0_OUT0 #20 LETIM0_OUT1 #19
PCNT0_S0IN #20
PCNT0_S1IN #19
US0_TX #20 US0_RX #19
US0_CLK #18 US0_CS
#17 US0_CTS #16
US0_RTS #15 US1_TX
#20 US1_RX #19
PRS_CH3 #11 PRS_CH4
US1_CLK #18 US1_CS
#3 PRS_CH5 #2
#17 US1_CTS #16
PRS_CH6 #14 ACMP0_O
US1_RTS #15 US3_TX
#20 ACMP1_O #20
#4 US3_RX #3 US3_CLK
LES_CH4
#2 US3_CS #1 US3_CTS
#0 US3_RTS #31
LEU0_TX #20 LEU0_RX
#19 I2C0_SDA #20
I2C0_SCL #19
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Rev. 1.2 | 90
EFM32JG12 Family Data Sheet
Pin Definitions
GPIO Name
PD14
PD15
Pin Alternate Functionality / Description
Analog
Timers
BUSDY BUSCX
VDAC0_OUT1 /
OPA1_OUT
TIM0_CC0 #22
TIM0_CC1 #21
TIM0_CC2 #20
TIM0_CDTI0 #19
TIM0_CDTI1 #18
TIM0_CDTI2 #17
TIM1_CC0 #22
TIM1_CC1 #21
TIM1_CC2 #20
TIM1_CC3 #19
WTIM0_CDTI0 #30
WTIM0_CDTI1 #28
WTIM0_CDTI2 #26
WTIM1_CC0 #22
WTIM1_CC1 #20
WTIM1_CC2 #18
WTIM1_CC3 #16 LETIM0_OUT0 #22 LETIM0_OUT1 #21
PCNT0_S0IN #22
PCNT0_S1IN #21
US0_TX #22 US0_RX #21
US0_CLK #20 US0_CS
#19 US0_CTS #18
US0_RTS #17 US1_TX
#22 US1_RX #21
CMU_CLK0 #5 PRS_CH3
US1_CLK #20 US1_CS
#13 PRS_CH4 #5
#19 US1_CTS #18
PRS_CH5 #4 PRS_CH6
US1_RTS #17 US3_TX
#16 ACMP0_O #22
#6 US3_RX #5 US3_CLK ACMP1_O #22 LES_CH6
#4 US3_CS #3 US3_CTS
GPIO_EM4WU4
#2 US3_RTS #1
LEU0_TX #22 LEU0_RX
#21 I2C0_SDA #22
I2C0_SCL #21
VDAC0_OUT0ALT /
OPA0_OUTALT #2 BUSCY BUSDX OPA1_N
TIM0_CC0 #23
TIM0_CC1 #22
TIM0_CC2 #21
TIM0_CDTI0 #20
TIM0_CDTI1 #19
TIM0_CDTI2 #18
TIM1_CC0 #23
TIM1_CC1 #22
TIM1_CC2 #21
TIM1_CC3 #20
WTIM0_CDTI0 #31
WTIM0_CDTI1 #29
WTIM0_CDTI2 #27
WTIM1_CC0 #23
WTIM1_CC1 #21
WTIM1_CC2 #19
WTIM1_CC3 #17 LETIM0_OUT0 #23 LETIM0_OUT1 #22
PCNT0_S0IN #23
PCNT0_S1IN #22
US0_TX #23 US0_RX #22
US0_CLK #21 US0_CS
#20 US0_CTS #19
US0_RTS #18 US1_TX
#23 US1_RX #22
CMU_CLK1 #5 PRS_CH3
US1_CLK #21 US1_CS
#14 PRS_CH4 #6
#20 US1_CTS #19
PRS_CH5 #5 PRS_CH6
US1_RTS #18 US3_TX
#17 ACMP0_O #23
#7 US3_RX #6 US3_CLK ACMP1_O #23 LES_CH7
#5 US3_CS #4 US3_CTS
DBG_SWO #2
#3 US3_RTS #2
LEU0_TX #23 LEU0_RX
#22 I2C0_SDA #23
I2C0_SCL #22
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Other
Rev. 1.2 | 91
EFM32JG12 Family Data Sheet
Pin Definitions
6.4 Alternate Functionality Overview
A wide selection of alternate functionality is available for multiplexing to various pins. The following table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings and the associated GPIO
pin. Refer to 6.3 GPIO Functionality Table for a list of functions available on each GPIO pin.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.
Table 6.4. Alternate Functionality Overview
Alternate
Functionality
LOCATION
0-3
4-7
8 - 11
12 - 15
16 - 19
20 - 23
ACMP0_O
0: PA0
1: PA1
2: PA2
3: PA3
ACMP1_O
0: PA0
1: PA1
2: PA2
3: PA3
24 - 27
28 - 31
Description
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
11: PC6
12: PC7
13: PC8
14: PC9
15: PC10
16: PC11
17: PD9
18: PD10
19: PD11
20: PD12
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
Analog comparator
ACMP0, digital output.
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
11: PC6
12: PC7
13: PC8
14: PC9
15: PC10
16: PC11
17: PD9
18: PD10
19: PD11
20: PD12
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
Analog comparator
ACMP1, digital output.
0: PA0
Analog to digital
converter ADC0 external reference input negative pin.
0: PA1
Analog to digital
converter ADC0 external reference input positive pin.
ADC0_EXTN
ADC0_EXTP
0: PF1
BOOT_RX
Bootloader RX.
0: PF0
BOOT_TX
Bootloader TX.
CMU_CLK0
0: PA1
1: PB15
2: PC6
3: PC11
4: PD9
5: PD14
6: PF2
7: PF7
Clock Management
Unit, clock output
number 0.
CMU_CLK1
0: PA0
1: PB14
2: PC7
3: PC10
4: PD10
5: PD15
6: PF3
7: PF6
Clock Management
Unit, clock output
number 1.
4: PA5
CMU_CLKI0
0: PB13
1: PF7
2: PC6
3: PB6
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Clock Management
Unit, clock input
number 0.
Rev. 1.2 | 92
EFM32JG12 Family Data Sheet
Pin Definitions
Alternate
Functionality
LOCATION
0-3
4-7
0: PF0
DBG_SWCLKTCK
12 - 15
16 - 19
20 - 23
24 - 27
28 - 31
Description
Debug-interface
Serial Wire clock
input and JTAG
Test Clock.
Note that this function is enabled to
the pin out of reset,
and has a built-in
pull down.
0: PF1
DBG_SWDIOTMS
Debug-interface
Serial Wire data input / output and
JTAG Test Mode
Select.
Note that this function is enabled to
the pin out of reset,
and has a built-in
pull up.
0: PF2
1: PB13
2: PD15
3: PC11
Debug-interface
Serial Wire viewer
Output.
0: PF3
Debug-interface
JTAG Test Data In.
DBG_SWO
Note that this function is not enabled
after reset, and
must be enabled by
software to be
used.
Note that this function becomes available after the first
valid JTAG command is received,
and has a built-in
pull up when JTAG
is active.
DBG_TDI
0: PF2
Debug-interface
JTAG Test Data
Out.
Note that this function becomes available after the first
valid JTAG command is received.
DBG_TDO
ETM_TCLK
8 - 11
0: PF8
1: PA5
2: PI2
3: PC6
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Embedded Trace
Module ETM clock .
Rev. 1.2 | 93
EFM32JG12 Family Data Sheet
Pin Definitions
Alternate
Functionality
LOCATION
0-3
4-7
8 - 11
12 - 15
16 - 19
20 - 23
24 - 27
28 - 31
Description
ETM_TD0
0: PF9
1: PA6
2: PI3
3: PC7
Embedded Trace
Module ETM data
0.
ETM_TD1
0: PF10
1: PA7
2: PB6
3: PC8
Embedded Trace
Module ETM data
1.
ETM_TD2
0: PF11
1: PA8
2: PB7
3: PC9
Embedded Trace
Module ETM data
2.
ETM_TD3
0: PF12
1: PA9
2: PB8
3: PC10
Embedded Trace
Module ETM data
3.
0: PF2
Pin can be used to
wake the system
up from EM4
GPIO_EM4WU0
0: PF7
Pin can be used to
wake the system
up from EM4
GPIO_EM4WU1
0: PD14
Pin can be used to
wake the system
up from EM4
GPIO_EM4WU4
0: PA3
Pin can be used to
wake the system
up from EM4
GPIO_EM4WU8
0: PB13
Pin can be used to
wake the system
up from EM4
GPIO_EM4WU9
0: PC10
Pin can be used to
wake the system
up from EM4
GPIO_EM4WU12
I2C0_SCL
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
5: PB11
6: PB12
7: PB13
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
14: PC10
15: PC11
16: PD9
17: PD10
18: PD11
19: PD12
20: PD13
21: PD14
22: PD15
23: PF0
24: PF1
25: PF2
26: PF3
27: PF4
28: PF5
29: PF6
30: PF7
31: PA0
I2C0 Serial Clock
Line input / output.
I2C0_SDA
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
11: PC6
12: PC7
13: PC8
14: PC9
15: PC10
16: PC11
17: PD9
18: PD10
19: PD11
20: PD12
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
I2C0 Serial Data input / output.
I2C1_SCL
0: PA7
1: PA8
2: PA9
3: PI2
4: PI3
5: PB6
6: PB7
7: PB8
8: PB9
9: PB10
10: PJ14
11: PJ15
12: PC0
13: PC1
14: PC2
15: PC3
16: PC4
17: PC5
18: PC10
19: PC11
20: PF8
21: PF9
22: PF10
23: PF11
24: PF12
25: PF13
26: PF14
27: PF15
28: PK0
29: PK1
30: PK2
31: PA6
I2C1 Serial Clock
Line input / output.
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Rev. 1.2 | 94
EFM32JG12 Family Data Sheet
Pin Definitions
Alternate
Functionality
I2C1_SDA
LOCATION
0-3
4-7
0: PA6
1: PA7
2: PA8
3: PA9
4: PI2
5: PI3
6: PB6
7: PB7
8 - 11
12 - 15
16 - 19
20 - 23
24 - 27
28 - 31
Description
8: PB8
9: PB9
10: PB10
11: PJ14
12: PJ15
13: PC0
14: PC1
15: PC2
16: PC3
17: PC4
18: PC5
19: PC10
20: PC11
21: PF8
22: PF9
23: PF10
24: PF11
25: PF12
26: PF13
27: PF14
28: PF15
29: PK0
30: PK1
31: PK2
I2C1 Serial Data input / output.
0: PK0
IDAC0_OUT
IDAC0 output.
0: PA8
LESENSE alternate
excite output 0.
LES_ALTEX0
0: PA9
LESENSE alternate
excite output 1.
LES_ALTEX1
0: PJ14
LESENSE alternate
excite output 2.
LES_ALTEX2
0: PJ15
LESENSE alternate
excite output 3.
LES_ALTEX3
0: PI0
LESENSE alternate
excite output 4.
LES_ALTEX4
0: PI1
LESENSE alternate
excite output 5.
LES_ALTEX5
0: PI2
LESENSE alternate
excite output 6.
LES_ALTEX6
0: PI3
LESENSE alternate
excite output 7.
LES_ALTEX7
0: PD8
LESENSE channel
0.
LES_CH0
0: PD9
LESENSE channel
1.
LES_CH1
0: PD10
LES_CH2
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LESENSE channel
2.
Rev. 1.2 | 95
EFM32JG12 Family Data Sheet
Pin Definitions
Alternate
Functionality
LOCATION
0-3
4-7
8 - 11
12 - 15
16 - 19
20 - 23
24 - 27
28 - 31
Description
0: PD11
LESENSE channel
3.
LES_CH3
0: PD12
LESENSE channel
4.
LES_CH4
0: PD13
LESENSE channel
5.
LES_CH5
0: PD14
LESENSE channel
6.
LES_CH6
0: PD15
LESENSE channel
7.
LES_CH7
0: PA0
LESENSE channel
8.
LES_CH8
0: PA1
LESENSE channel
9.
LES_CH9
0: PA2
LESENSE channel
10.
LES_CH10
0: PA3
LESENSE channel
11.
LES_CH11
0: PA4
LESENSE channel
12.
LES_CH12
0: PA5
LESENSE channel
13.
LES_CH13
0: PA6
LESENSE channel
14.
LES_CH14
0: PA7
LES_CH15
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LESENSE channel
15.
Rev. 1.2 | 96
EFM32JG12 Family Data Sheet
Pin Definitions
Alternate
Functionality
LOCATION
0-3
4-7
8 - 11
12 - 15
16 - 19
20 - 23
LETIM0_OUT0
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
11: PC6
12: PC7
13: PC8
14: PC9
15: PC10
16: PC11
17: PD9
18: PD10
19: PD11
20: PD12
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
Low Energy Timer
LETIM0, output
channel 0.
LETIM0_OUT1
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
5: PB11
6: PB12
7: PB13
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
14: PC10
15: PC11
16: PD9
17: PD10
18: PD11
19: PD12
20: PD13
21: PD14
22: PD15
23: PF0
24: PF1
25: PF2
26: PF3
27: PF4
28: PF5
29: PF6
30: PF7
31: PA0
Low Energy Timer
LETIM0, output
channel 1.
LEU0_RX
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
5: PB11
6: PB12
7: PB13
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
14: PC10
15: PC11
16: PD9
17: PD10
18: PD11
19: PD12
20: PD13
21: PD14
22: PD15
23: PF0
24: PF1
25: PF2
26: PF3
27: PF4
28: PF5
29: PF6
30: PF7
31: PA0
LEUART0 Receive
input.
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
11: PC6
12: PC7
13: PC8
14: PC9
15: PC10
16: PC11
17: PD9
18: PD10
19: PD11
20: PD12
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
LEU0_TX
24 - 27
28 - 31
Description
LEUART0 Transmit
output. Also used
as receive input in
half duplex communication.
0: PB14
Low Frequency
Crystal (typically
32.768 kHz) negative pin. Also used
as an optional external clock input
pin.
0: PB15
Low Frequency
Crystal (typically
32.768 kHz) positive pin.
LFXTAL_N
LFXTAL_P
0: PA4
OPA0_N
0: PA2
OPA0_P
0: PD15
OPA1_N
0: PD13
OPA1_P
0: PB13
OPA2_N
Operational Amplifier 0 external negative input.
Operational Amplifier 0 external positive input.
Operational Amplifier 1 external negative input.
Operational Amplifier 1 external positive input.
Operational Amplifier 2 external negative input.
0: PB12
OPA2_OUT
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Operational Amplifier 2 output.
Rev. 1.2 | 97
EFM32JG12 Family Data Sheet
Pin Definitions
Alternate
Functionality
OPA2_OUTALT
LOCATION
0-3
4-7
8 - 11
12 - 15
16 - 19
20 - 23
24 - 27
28 - 31
0: PB9
1: PB10
Description
Operational Amplifier 2 alternative output.
0: PB11
Operational Amplifier 2 external positive input.
OPA2_P
PCNT0_S0IN
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
11: PC6
12: PC7
13: PC8
14: PC9
15: PC10
16: PC11
17: PD9
18: PD10
19: PD11
20: PD12
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
Pulse Counter
PCNT0 input number 0.
PCNT0_S1IN
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
5: PB11
6: PB12
7: PB13
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
14: PC10
15: PC11
16: PD9
17: PD10
18: PD11
19: PD12
20: PD13
21: PD14
22: PD15
23: PF0
24: PF1
25: PF2
26: PF3
27: PF4
28: PF5
29: PF6
30: PF7
31: PA0
Pulse Counter
PCNT0 input number 1.
PCNT1_S0IN
0: PA6
1: PA7
2: PA8
3: PA9
4: PI2
5: PI3
6: PB6
7: PB7
8: PB8
9: PB9
10: PB10
11: PJ14
12: PJ15
13: PC0
14: PC1
15: PC2
16: PC3
17: PC4
18: PC5
19: PF6
20: PF7
21: PF8
22: PF9
23: PF10
24: PF11
25: PF12
26: PF13
27: PF14
28: PF15
29: PK0
30: PK1
31: PK2
Pulse Counter
PCNT1 input number 0.
PCNT1_S1IN
0: PA7
1: PA8
2: PA9
3: PI2
4: PI3
5: PB6
6: PB7
7: PB8
8: PB9
9: PB10
10: PJ14
11: PJ15
12: PC0
13: PC1
14: PC2
15: PC3
16: PC4
17: PC5
18: PF6
19: PF7
20: PF8
21: PF9
22: PF10
23: PF11
24: PF12
25: PF13
26: PF14
27: PF15
28: PK0
29: PK1
30: PK2
31: PA6
Pulse Counter
PCNT1 input number 1.
PCNT2_S0IN
0: PA6
1: PA7
2: PA8
3: PA9
4: PI2
5: PI3
6: PB6
7: PB7
8: PB8
9: PB9
10: PB10
11: PJ14
12: PJ15
13: PC0
14: PC1
15: PC2
16: PC3
17: PC4
18: PC5
19: PC10
20: PC11
21: PF8
22: PF9
23: PF10
24: PF11
25: PF12
26: PF13
27: PF14
28: PF15
29: PK0
30: PK1
31: PK2
Pulse Counter
PCNT2 input number 0.
PCNT2_S1IN
0: PA7
1: PA8
2: PA9
3: PI2
4: PI3
5: PB6
6: PB7
7: PB8
8: PB9
9: PB10
10: PJ14
11: PJ15
12: PC0
13: PC1
14: PC2
15: PC3
16: PC4
17: PC5
18: PC10
19: PC11
20: PF8
21: PF9
22: PF10
23: PF11
24: PF12
25: PF13
26: PF14
27: PF15
28: PK0
29: PK1
30: PK2
31: PA6
Pulse Counter
PCNT2 input number 1.
PRS_CH0
0: PF0
1: PF1
2: PF2
3: PF3
4: PF4
5: PF5
6: PF6
7: PF7
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10
13: PC11
PRS_CH1
0: PF1
1: PF2
2: PF3
3: PF4
4: PF5
5: PF6
6: PF7
7: PF0
Peripheral Reflex
System PRS, channel 1.
PRS_CH2
0: PF2
1: PF3
2: PF4
3: PF5
4: PF6
5: PF7
6: PF0
7: PF1
Peripheral Reflex
System PRS, channel 2.
PRS_CH3
0: PF3
1: PF4
2: PF5
3: PF6
4: PF7
5: PF0
6: PF1
7: PF2
PRS_CH4
0: PD9
1: PD10
2: PD11
3: PD12
4: PD13
5: PD14
6: PD15
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8: PD9
9: PD10
10: PD11
11: PD12
12: PD13
13: PD14
14: PD15
Peripheral Reflex
System PRS, channel 0.
Peripheral Reflex
System PRS, channel 3.
Peripheral Reflex
System PRS, channel 4.
Rev. 1.2 | 98
EFM32JG12 Family Data Sheet
Pin Definitions
Alternate
Functionality
LOCATION
0-3
4-7
8 - 11
12 - 15
16 - 19
20 - 23
24 - 27
28 - 31
Description
PRS_CH5
0: PD10
1: PD11
2: PD12
3: PD13
4: PD14
5: PD15
6: PD9
PRS_CH6
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
11: PD9
PRS_CH7
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
5: PB11
6: PB12
7: PB13
8: PB14
9: PB15
10: PA0
PRS_CH8
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PA0
10: PA1
PRS_CH9
0: PA3
1: PA4
2: PA5
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
8: PA0
9: PA1
10: PA2
11: PC6
PRS_CH10
0: PC6
1: PC7
2: PC8
3: PC9
4: PC10
5: PC11
PRS_CH11
0: PC7
1: PC8
2: PC9
3: PC10
4: PC11
5: PC6
TIM0_CC0
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
11: PC6
12: PC7
13: PC8
14: PC9
15: PC10
16: PC11
17: PD9
18: PD10
19: PD11
20: PD12
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
Timer 0 Capture
Compare input /
output channel 0.
TIM0_CC1
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
5: PB11
6: PB12
7: PB13
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
14: PC10
15: PC11
16: PD9
17: PD10
18: PD11
19: PD12
20: PD13
21: PD14
22: PD15
23: PF0
24: PF1
25: PF2
26: PF3
27: PF4
28: PF5
29: PF6
30: PF7
31: PA0
Timer 0 Capture
Compare input /
output channel 1.
TIM0_CC2
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PC6
10: PC7
11: PC8
12: PC9
13: PC10
14: PC11
15: PD9
16: PD10
17: PD11
18: PD12
19: PD13
20: PD14
21: PD15
22: PF0
23: PF1
24: PF2
25: PF3
26: PF4
27: PF5
28: PF6
29: PF7
30: PA0
31: PA1
Timer 0 Capture
Compare input /
output channel 2.
TIM0_CDTI0
0: PA3
1: PA4
2: PA5
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10
13: PC11
14: PD9
15: PD10
16: PD11
17: PD12
18: PD13
19: PD14
20: PD15
21: PF0
22: PF1
23: PF2
24: PF3
25: PF4
26: PF5
27: PF6
28: PF7
29: PA0
30: PA1
31: PA2
Timer 0 Complimentary Dead Time
Insertion channel 0.
TIM0_CDTI1
0: PA4
1: PA5
2: PB11
3: PB12
4: PB13
5: PB14
6: PB15
7: PC6
8: PC7
9: PC8
10: PC9
11: PC10
12: PC11
13: PD9
14: PD10
15: PD11
16: PD12
17: PD13
18: PD14
19: PD15
20: PF0
21: PF1
22: PF2
23: PF3
24: PF4
25: PF5
26: PF6
27: PF7
28: PA0
29: PA1
30: PA2
31: PA3
Timer 0 Complimentary Dead Time
Insertion channel 1.
TIM0_CDTI2
0: PA5
1: PB11
2: PB12
3: PB13
4: PB14
5: PB15
6: PC6
7: PC7
8: PC8
9: PC9
10: PC10
11: PC11
12: PD9
13: PD10
14: PD11
15: PD12
16: PD13
17: PD14
18: PD15
19: PF0
20: PF1
21: PF2
22: PF3
23: PF4
24: PF5
25: PF6
26: PF7
27: PA0
28: PA1
29: PA2
30: PA3
31: PA4
Timer 0 Complimentary Dead Time
Insertion channel 2.
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Peripheral Reflex
System PRS, channel 5.
12: PD10
13: PD11
14: PD12
15: PD13
16: PD14
17: PD15
Peripheral Reflex
System PRS, channel 6.
Peripheral Reflex
System PRS, channel 7.
Peripheral Reflex
System PRS, channel 8.
12: PC7
13: PC8
14: PC9
15: PC10
16: PC11
Peripheral Reflex
System PRS, channel 9.
Peripheral Reflex
System PRS, channel 10.
Peripheral Reflex
System PRS, channel 11.
Rev. 1.2 | 99
EFM32JG12 Family Data Sheet
Pin Definitions
Alternate
Functionality
LOCATION
0-3
4-7
8 - 11
12 - 15
16 - 19
20 - 23
TIM1_CC0
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
11: PC6
12: PC7
13: PC8
14: PC9
15: PC10
16: PC11
17: PD9
18: PD10
19: PD11
20: PD12
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
Timer 1 Capture
Compare input /
output channel 0.
TIM1_CC1
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
5: PB11
6: PB12
7: PB13
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
14: PC10
15: PC11
16: PD9
17: PD10
18: PD11
19: PD12
20: PD13
21: PD14
22: PD15
23: PF0
24: PF1
25: PF2
26: PF3
27: PF4
28: PF5
29: PF6
30: PF7
31: PA0
Timer 1 Capture
Compare input /
output channel 1.
TIM1_CC2
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PC6
10: PC7
11: PC8
12: PC9
13: PC10
14: PC11
15: PD9
16: PD10
17: PD11
18: PD12
19: PD13
20: PD14
21: PD15
22: PF0
23: PF1
24: PF2
25: PF3
26: PF4
27: PF5
28: PF6
29: PF7
30: PA0
31: PA1
Timer 1 Capture
Compare input /
output channel 2.
TIM1_CC3
0: PA3
1: PA4
2: PA5
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10
13: PC11
14: PD9
15: PD10
16: PD11
17: PD12
18: PD13
19: PD14
20: PD15
21: PF0
22: PF1
23: PF2
24: PF3
25: PF4
26: PF5
27: PF6
28: PF7
29: PA0
30: PA1
31: PA2
Timer 1 Capture
Compare input /
output channel 3.
US0_CLK
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PC6
10: PC7
11: PC8
12: PC9
13: PC10
14: PC11
15: PD9
16: PD10
17: PD11
18: PD12
19: PD13
20: PD14
21: PD15
22: PF0
23: PF1
24: PF2
25: PF3
26: PF4
27: PF5
28: PF6
29: PF7
30: PA0
31: PA1
USART0 clock input / output.
US0_CS
0: PA3
1: PA4
2: PA5
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10
13: PC11
14: PD9
15: PD10
16: PD11
17: PD12
18: PD13
19: PD14
20: PD15
21: PF0
22: PF1
23: PF2
24: PF3
25: PF4
26: PF5
27: PF6
28: PF7
29: PA0
30: PA1
31: PA2
USART0 chip select input / output.
US0_CTS
0: PA4
1: PA5
2: PB11
3: PB12
4: PB13
5: PB14
6: PB15
7: PC6
8: PC7
9: PC8
10: PC9
11: PC10
12: PC11
13: PD9
14: PD10
15: PD11
16: PD12
17: PD13
18: PD14
19: PD15
20: PF0
21: PF1
22: PF2
23: PF3
24: PF4
25: PF5
26: PF6
27: PF7
28: PA0
29: PA1
30: PA2
31: PA3
USART0 Clear To
Send hardware
flow control input.
US0_RTS
0: PA5
1: PB11
2: PB12
3: PB13
4: PB14
5: PB15
6: PC6
7: PC7
8: PC8
9: PC9
10: PC10
11: PC11
12: PD9
13: PD10
14: PD11
15: PD12
16: PD13
17: PD14
18: PD15
19: PF0
20: PF1
21: PF2
22: PF3
23: PF4
24: PF5
25: PF6
26: PF7
27: PA0
28: PA1
29: PA2
30: PA3
31: PA4
USART0 Request
To Send hardware
flow control output.
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
5: PB11
6: PB12
7: PB13
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
14: PC10
15: PC11
16: PD9
17: PD10
18: PD11
19: PD12
20: PD13
21: PD14
22: PD15
23: PF0
24: PF1
25: PF2
26: PF3
27: PF4
28: PF5
29: PF6
30: PF7
31: PA0
USART0 Asynchronous Receive.
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
11: PC6
12: PC7
13: PC8
14: PC9
15: PC10
16: PC11
17: PD9
18: PD10
19: PD11
20: PD12
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
USART0 Asynchronous Transmit. Also used as receive
input in half duplex
communication.
US0_RX
24 - 27
28 - 31
US0_TX
Description
USART0 Synchronous mode Master
Input / Slave Output (MISO).
USART0 Synchronous mode Master
Output / Slave Input (MOSI).
US1_CLK
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
5: PB12
6: PB13
7: PB14
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8: PB15
9: PC6
10: PC7
11: PC8
12: PC9
13: PC10
14: PC11
15: PD9
16: PD10
17: PD11
18: PD12
19: PD13
20: PD14
21: PD15
22: PF0
23: PF1
24: PF2
25: PF3
26: PF4
27: PF5
28: PF6
29: PF7
30: PA0
31: PA1
USART1 clock input / output.
Rev. 1.2 | 100
EFM32JG12 Family Data Sheet
Pin Definitions
Alternate
Functionality
LOCATION
0-3
4-7
8 - 11
US1_CS
0: PA3
1: PA4
2: PA5
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
US1_CTS
0: PA4
1: PA5
2: PB11
3: PB12
US1_RTS
US1_RX
12 - 15
16 - 19
20 - 23
24 - 27
28 - 31
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10
13: PC11
14: PD9
15: PD10
16: PD11
17: PD12
18: PD13
19: PD14
20: PD15
21: PF0
22: PF1
23: PF2
24: PF3
25: PF4
26: PF5
27: PF6
28: PF7
29: PA0
30: PA1
31: PA2
USART1 chip select input / output.
4: PB13
5: PB14
6: PB15
7: PC6
8: PC7
9: PC8
10: PC9
11: PC10
12: PC11
13: PD9
14: PD10
15: PD11
16: PD12
17: PD13
18: PD14
19: PD15
20: PF0
21: PF1
22: PF2
23: PF3
24: PF4
25: PF5
26: PF6
27: PF7
28: PA0
29: PA1
30: PA2
31: PA3
USART1 Clear To
Send hardware
flow control input.
0: PA5
1: PB11
2: PB12
3: PB13
4: PB14
5: PB15
6: PC6
7: PC7
8: PC8
9: PC9
10: PC10
11: PC11
12: PD9
13: PD10
14: PD11
15: PD12
16: PD13
17: PD14
18: PD15
19: PF0
20: PF1
21: PF2
22: PF3
23: PF4
24: PF5
25: PF6
26: PF7
27: PA0
28: PA1
29: PA2
30: PA3
31: PA4
USART1 Request
To Send hardware
flow control output.
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
5: PB11
6: PB12
7: PB13
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
14: PC10
15: PC11
16: PD9
17: PD10
18: PD11
19: PD12
20: PD13
21: PD14
22: PD15
23: PF0
24: PF1
25: PF2
26: PF3
27: PF4
28: PF5
29: PF6
30: PF7
31: PA0
USART1 Asynchronous Receive.
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
11: PC6
12: PC7
13: PC8
14: PC9
15: PC10
16: PC11
17: PD9
18: PD10
19: PD11
20: PD12
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
USART1 Asynchronous Transmit. Also used as receive
input in half duplex
communication.
US1_TX
Description
USART1 Synchronous mode Master
Input / Slave Output (MISO).
USART1 Synchronous mode Master
Output / Slave Input (MOSI).
US2_CLK
0: PA7
1: PA8
2: PA9
3: PI0
4: PI1
5: PI2
6: PI3
7: PB6
8: PB7
9: PB8
10: PB9
11: PB10
12: PF0
13: PF1
14: PF3
15: PF4
16: PF5
17: PF6
18: PF7
19: PF8
20: PF9
21: PF10
22: PF11
23: PF12
24: PF13
25: PF14
26: PF15
27: PK0
28: PK1
29: PK2
30: PA5
31: PA6
USART2 clock input / output.
US2_CS
0: PA8
1: PA9
2: PI0
3: PI1
4: PI2
5: PI3
6: PB6
7: PB7
8: PB8
9: PB9
10: PB10
11: PF0
12: PF1
13: PF3
14: PF4
15: PF5
16: PF6
17: PF7
18: PF8
19: PF9
20: PF10
21: PF11
22: PF12
23: PF13
24: PF14
25: PF15
26: PK0
27: PK1
28: PK2
29: PA5
30: PA6
31: PA7
USART2 chip select input / output.
US2_CTS
0: PA9
1: PI0
2: PI1
3: PI2
4: PI3
5: PB6
6: PB7
7: PB8
8: PB9
9: PB10
10: PF0
11: PF1
12: PF3
13: PF4
14: PF5
15: PF6
16: PF7
17: PF8
18: PF9
19: PF10
20: PF11
21: PF12
22: PF13
23: PF14
24: PF15
25: PK0
26: PK1
27: PK2
28: PA5
29: PA6
30: PA7
31: PA8
USART2 Clear To
Send hardware
flow control input.
US2_RTS
0: PI0
1: PI1
2: PI2
3: PI3
4: PB6
5: PB7
6: PB8
7: PB9
8: PB10
9: PF0
10: PF1
11: PF3
12: PF4
13: PF5
14: PF6
15: PF7
16: PF8
17: PF9
18: PF10
19: PF11
20: PF12
21: PF13
22: PF14
23: PF15
24: PK0
25: PK1
26: PK2
27: PA5
28: PA6
29: PA7
30: PA8
31: PA9
USART2 Request
To Send hardware
flow control output.
0: PA6
1: PA7
2: PA8
3: PA9
4: PI0
5: PI1
6: PI2
7: PI3
8: PB6
9: PB7
10: PB8
11: PB9
12: PB10
13: PF0
14: PF1
15: PF3
16: PF4
17: PF5
18: PF6
19: PF7
20: PF8
21: PF9
22: PF10
23: PF11
24: PF12
25: PF13
26: PF14
27: PF15
28: PK0
29: PK1
30: PK2
31: PA5
US2_RX
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USART2 Asynchronous Receive.
USART2 Synchronous mode Master
Input / Slave Output (MISO).
Rev. 1.2 | 101
EFM32JG12 Family Data Sheet
Pin Definitions
Alternate
Functionality
LOCATION
0-3
4-7
8 - 11
12 - 15
0: PA5
1: PA6
2: PA7
3: PA8
4: PA9
5: PI0
6: PI1
7: PI2
8: PI3
9: PB6
10: PB7
11: PB8
12: PB9
13: PB10
14: PF0
15: PF1
16 - 19
16: PF3
17: PF4
18: PF5
19: PF6
20 - 23
24 - 27
28 - 31
Description
20: PF7
21: PF8
22: PF9
23: PF10
24: PF11
25: PF12
26: PF13
27: PF14
28: PF15
29: PK0
30: PK1
31: PK2
USART2 Asynchronous Transmit. Also used as receive
input in half duplex
communication.
US2_TX
USART2 Synchronous mode Master
Output / Slave Input (MOSI).
US3_CLK
0: PD10
1: PD11
2: PD12
3: PD13
4: PD14
5: PD15
6: PI2
7: PI3
8: PB6
9: PB7
10: PB8
11: PB9
12: PB10
13: PB11
14: PJ14
15: PJ15
16: PC0
17: PC1
18: PC2
19: PC3
20: PC4
21: PC5
22: PF11
23: PF12
24: PF13
25: PF14
26: PF15
27: PK0
28: PK1
29: PK2
30: PD8
31: PD9
USART3 clock input / output.
US3_CS
0: PD11
1: PD12
2: PD13
3: PD14
4: PD15
5: PI2
6: PI3
7: PB6
8: PB7
9: PB8
10: PB9
11: PB10
12: PB11
13: PJ14
14: PJ15
15: PC0
16: PC1
17: PC2
18: PC3
19: PC4
20: PC5
21: PF11
22: PF12
23: PF13
24: PF14
25: PF15
26: PK0
27: PK1
28: PK2
29: PD8
30: PD9
31: PD10
USART3 chip select input / output.
US3_CTS
0: PD12
1: PD13
2: PD14
3: PD15
4: PI2
5: PI3
6: PB6
7: PB7
8: PB8
9: PB9
10: PB10
11: PB11
12: PJ14
13: PJ15
14: PC0
15: PC1
16: PC2
17: PC3
18: PC4
19: PC5
20: PF11
21: PF12
22: PF13
23: PF14
24: PF15
25: PK0
26: PK1
27: PK2
28: PD8
29: PD9
30: PD10
31: PD11
USART3 Clear To
Send hardware
flow control input.
US3_RTS
0: PD13
1: PD14
2: PD15
3: PI2
4: PI3
5: PB6
6: PB7
7: PB8
8: PB9
9: PB10
10: PB11
11: PJ14
12: PJ15
13: PC0
14: PC1
15: PC2
16: PC3
17: PC4
18: PC5
19: PF11
20: PF12
21: PF13
22: PF14
23: PF15
24: PK0
25: PK1
26: PK2
27: PD8
28: PD9
29: PD10
30: PD11
31: PD12
USART3 Request
To Send hardware
flow control output.
0: PD9
1: PD10
2: PD11
3: PD12
4: PD13
5: PD14
6: PD15
7: PI2
8: PI3
9: PB6
10: PB7
11: PB8
12: PB9
13: PB10
14: PB11
15: PJ14
16: PJ15
17: PC0
18: PC1
19: PC2
20: PC3
21: PC4
22: PC5
23: PF11
24: PF12
25: PF13
26: PF14
27: PF15
28: PK0
29: PK1
30: PK2
31: PD8
USART3 Asynchronous Receive.
0: PD8
1: PD9
2: PD10
3: PD11
4: PD12
5: PD13
6: PD14
7: PD15
8: PI2
9: PI3
10: PB6
11: PB7
12: PB8
13: PB9
14: PB10
15: PB11
16: PJ14
17: PJ15
18: PC0
19: PC1
20: PC2
21: PC3
22: PC4
23: PC5
24: PF11
25: PF12
26: PF13
27: PF14
28: PF15
29: PK0
30: PK1
31: PK2
USART3 Asynchronous Transmit. Also used as receive
input in half duplex
communication.
US3_RX
US3_TX
USART3 Synchronous mode Master
Input / Slave Output (MISO).
USART3 Synchronous mode Master
Output / Slave Input (MOSI).
0: PA1
Digital to analog
converter VDAC0
external reference
input pin.
0: PA3
Digital to Analog
Converter DAC0
output channel
number 0.
0: PA5
1: PD13
2: PD15
Digital to Analog
Converter DAC0 alternative output for
channel 0.
VDAC0_EXT
VDAC0_OUT0 /
OPA0_OUT
VDAC0_OUT0AL
T / OPA0_OUTALT
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Rev. 1.2 | 102
EFM32JG12 Family Data Sheet
Pin Definitions
Alternate
Functionality
LOCATION
0-3
4-7
8 - 11
12 - 15
16 - 19
20 - 23
24 - 27
28 - 31
0: PD14
Digital to Analog
Converter DAC0
output channel
number 1.
0: PD12
1: PA2
2: PA4
Digital to Analog
Converter DAC0 alternative output for
channel 1.
VDAC0_OUT1 /
OPA1_OUT
VDAC0_OUT1AL
T / OPA1_OUTALT
Description
WTIM0_CC0
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PA6
7: PA7
8: PA8
9: PA9
10: PB6
11: PB7
12: PB8
13: PB9
14: PB10
15: PB11
16: PB12
17: PB13
18: PB14
19: PB15
20: PC0
21: PC1
22: PC2
23: PC3
24: PC4
25: PC5
26: PC6
27: PC7
28: PC8
29: PC9
30: PC10
31: PC11
Wide timer 0 Capture Compare input / output channel
0.
WTIM0_CC1
0: PA2
1: PA3
2: PA4
3: PA5
4: PA6
5: PA7
6: PA8
7: PA9
8: PB6
9: PB7
10: PB8
11: PB9
12: PB10
13: PB11
14: PB12
15: PB13
16: PB14
17: PB15
18: PC0
19: PC1
20: PC2
21: PC3
22: PC4
23: PC5
24: PC6
25: PC7
26: PC8
27: PC9
28: PC10
29: PC11
30: PD8
31: PD9
Wide timer 0 Capture Compare input / output channel
1.
WTIM0_CC2
0: PA4
1: PA5
2: PA6
3: PA7
4: PA8
5: PA9
6: PB6
7: PB7
8: PB8
9: PB9
10: PB10
11: PB11
12: PB12
13: PB13
14: PB14
15: PB15
16: PC0
17: PC1
18: PC2
19: PC3
20: PC4
21: PC5
22: PC6
23: PC7
24: PC8
25: PC9
26: PC10
27: PC11
28: PD8
29: PD9
30: PD10
31: PD11
Wide timer 0 Capture Compare input / output channel
2.
WTIM0_CDTI0
0: PA8
1: PA9
2: PB6
3: PB7
4: PB8
5: PB9
6: PB10
7: PB11
8: PB12
9: PB13
10: PB14
11: PB15
12: PC0
13: PC1
14: PC2
15: PC3
16: PC4
17: PC5
18: PC6
19: PC7
20: PC8
21: PC9
22: PC10
23: PC11
24: PD8
25: PD9
26: PD10
27: PD11
28: PD12
29: PD13
30: PD14
31: PD15
Wide timer 0 Complimentary Dead
Time Insertion
channel 0.
WTIM0_CDTI1
0: PB6
1: PB7
2: PB8
3: PB9
4: PB10
5: PB11
6: PB12
7: PB13
8: PB14
9: PB15
10: PC0
11: PC1
12: PC2
13: PC3
14: PC4
15: PC5
16: PC6
17: PC7
18: PC8
19: PC9
20: PC10
21: PC11
22: PD8
23: PD9
24: PD10
25: PD11
26: PD12
27: PD13
28: PD14
29: PD15
30: PF0
31: PF1
Wide timer 0 Complimentary Dead
Time Insertion
channel 1.
WTIM0_CDTI2
0: PB8
1: PB9
2: PB10
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
8: PC0
9: PC1
10: PC2
11: PC3
12: PC4
13: PC5
14: PC6
15: PC7
16: PC8
17: PC9
18: PC10
19: PC11
20: PD8
21: PD9
22: PD10
23: PD11
24: PD12
25: PD13
26: PD14
27: PD15
28: PF0
29: PF1
30: PF2
31: PF3
Wide timer 0 Complimentary Dead
Time Insertion
channel 2.
WTIM1_CC0
0: PB12
1: PB13
2: PB14
3: PB15
4: PC0
5: PC1
6: PC2
7: PC3
8: PC4
9: PC5
10: PC6
11: PC7
12: PC8
13: PC9
14: PC10
15: PC11
16: PD8
17: PD9
18: PD10
19: PD11
20: PD12
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
Wide timer 1 Capture Compare input / output channel
0.
WTIM1_CC1
0: PB14
1: PB15
2: PC0
3: PC1
4: PC2
5: PC3
6: PC4
7: PC5
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10
13: PC11
14: PD8
15: PD9
16: PD10
17: PD11
18: PD12
19: PD13
20: PD14
21: PD15
22: PF0
23: PF1
24: PF2
25: PF3
26: PF4
27: PF5
28: PF6
29: PF7
30: PF8
31: PF9
Wide timer 1 Capture Compare input / output channel
1.
WTIM1_CC2
0: PC0
1: PC1
2: PC2
3: PC3
4: PC4
5: PC5
6: PC6
7: PC7
8: PC8
9: PC9
10: PC10
11: PC11
12: PD8
13: PD9
14: PD10
15: PD11
16: PD12
17: PD13
18: PD14
19: PD15
20: PF0
21: PF1
22: PF2
23: PF3
24: PF4
25: PF5
26: PF6
27: PF7
28: PF8
29: PF9
30: PF10
31: PF11
Wide timer 1 Capture Compare input / output channel
2.
WTIM1_CC3
0: PC2
1: PC3
2: PC4
3: PC5
4: PC6
5: PC7
6: PC8
7: PC9
8: PC10
9: PC11
10: PD8
11: PD9
12: PD10
13: PD11
14: PD12
15: PD13
16: PD14
17: PD15
18: PF0
19: PF1
20: PF2
21: PF3
22: PF4
23: PF5
24: PF6
25: PF7
26: PF8
27: PF9
28: PF10
29: PF11
30: PF12
31: PF13
Wide timer 1 Capture Compare input / output channel
3.
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Rev. 1.2 | 103
EFM32JG12 Family Data Sheet
Pin Definitions
6.5 Analog Port (APORT) Client Maps
The Analog Port (APORT) is an infrastructure used to connect chip pins with on-chip analog clients such as analog comparators, ADCs,
DACs, etc. The APORT consists of a set of shared buses, switches, and control logic needed to configurably implement the signal
routing. Figure 6.3 APORT Connection Diagram on page 104 shows the APORT routing for this device family (note that available features may vary by part number). A complete description of APORT functionality can be found in the Reference Manual.
ACMP0X
ACMP0Y
ADC1X
ADC1Y
DY
DX
CY
CX
PC6
PC7
PC8
PC9
PC10
PJ14
PC11
PC0
PJ15
PC1
PC2
PC3
PC4
PC5
1X
IDAC0
ACMP1X
ACMP1Y
PF0
POS
PF1
PF2
PF3
ACMP1
PF8
NEG
PF9
PF10
POS
NEG
0Y
1Y
2Y
3Y
4Y
NEXT1
PF13
PF14
ADC0
PF15
PK0
PK1
0Y
1Y
2Y
3Y
4Y
NEXT1
NEXT0
0X
1X
2X
3X
4X
NEXT0
NEXT2
PF11
PF12
0X
1X
2X
3X
4X
NEXT1
NEXT0
0X
1X
2X
3X
4X
NEXT1
NEXT0
0Y
1Y
2Y
3Y
4Y
NEXT1
NEXT0
1Y
PB15
PB14
POS
PB13
OPA2_N
ACMP0
PB12
OUT2
NEG
PB11
OPA2_P
VDAC0_OPA2ALT
VDAC0_OPA2ALT
OUT2ALT
OUT2ALT
PB9
PB8
PB7
PB6
PI3
PI2
EXTP
EXTN
PK2
PF4
PF5
POS
OPA0_P
1X
2X
3X
4X
NEG
OPA0_N
1Y
2Y
3Y
4Y
PF6
PF7
AX
AY
BX
BY
OPA0
OUT
OUT0
OUT0ALT
OUT1
OUT2
OUT3
OUT4
NEXT0
POS
OPA2_P
1X
2X
3X
4X
NEG
OPA2_N
1Y
2Y
3Y
4Y
OPA2
PB10
PI1
OPA1_P
1X
2X
3X
4X
POS
OPA1_N
1Y
2Y
3Y
4Y
NEG
OUT1
OUT1ALT
OUT1
OUT2
OUT3
OUT4
NEXT1
PI0
PA9
PA8
PA7 LESENSE
OPA1
PA6 LESENSE
OUT
OUT0ALT
OUT1ALT
VDAC0_OUT0ALT
VDAC0_OUT1ALT
OPA0_N
OPA0_INN0
PA5 LESENSE
PA4 LESENSE
OUT0
OUT1ALT
OPA0_OUT
VDAC0_OUT1ALT
OPA0_P
OPA0_INP0
PA3 LESENSE
PA2 LESENSE
ADC_EXTP
ADC_EXTN
OUT0ALT
ADC0_EXTP
ADC0_EXTN
PA1 LESENSE
PA0 LESENSE
OPA0ALT
PD15 LESENSE
BUSADC0X,
BUSADC0Y
ACMP0X,
ACMP1Y, …
BUSACMP0X,
BUSACMP1Y, ...
CEXT_SENSE
2X
2Y
4X
4Y
VDAC0_OUT1ALT
OPA1_OUT
ADC0X,
ADC0Y
OPA1_INN0
OUT1
BUSAX, BUSBY, ...
CSEN
VDAC0_OUT0ALT
OPA1_INP0
AX, BY, …
ALT0OUT
OPA1_P
APORTnX, APORTnY
OPA1N
1X
1Y
3X
3Y
CEXT
nX, nY
OUT2
OUT2ALT
OUT1
OUT2
OUT3
OUT4
NEXT2
ALT1OUT
OUT
PD14 LESENSE
PD13 LESENSE
PD11 LESENSE
PD12 LESENSE
PD9 LESENSE
PD10 LESENSE
PD8 LESENSE
Figure 6.3. APORT Connection Diagram
Client maps for each analog circuit using the APORT are shown in the following tables. The maps are organized by bus, and show the
peripheral's port connection, the shared bus, and the connection from specific bus channel numbers to GPIO pins.
In general, enumerations for the pin selection field in an analog peripheral's register can be determined by finding the desired pin connection in the table and then combining the value in the Port column (APORT__), and the channel identifier (CH__). For example, if pin
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Rev. 1.2 | 104
silabs.com | Building a more connected world.
PD8
PD10
PD12
PD14
PA0
PA2
PA4
PA6
PB6
PB8
PB10
PB12
PB14
BUSDY
PD9
PD11
PD13
PD15
PA1
PA3
PA5
PA7
PB7
PB9
PB11
PD9
PD11
PD13
PD15
PA1
PA3
PA5
PA7
PB7
PB9
PB11
PB13
PB15
PB15
PB13
BUSCY
BUSDX
PD8
PD10
PD12
PD14
PA0
PA2
PA4
PA6
PB6
PB8
PB10
PB12
PB14
BUSCX
PC0
PC2
PC4
PC6
PC8
PC10
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSBY
PC1
PC3
PC5
PC7
PC9
PC11
PF1
PF3
PF5
PF7
PF9
PF11
PF13
PF15
BUSBX
PC1
PC3
PC5
PC7
PC9
PC11
PF1
PF3
PF5
PF7
PF9
PF11
PF13
PF15
BUSAY
PC0
PC2
PC4
PC6
PC8
PC10
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSAX
APORT4Y APORT4X APORT3Y APORT3X APORT2Y APORT2X APORT1Y APORT1X
APORT0X
Port
PA8
PA9
PA8
PA9
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
CH16
CH17
CH18
CH19
CH20
CH21
CH22
CH23
CH24
CH25
CH26
CH27
CH28
CH29
CH30
CH31
BUSACMP0Y BUSACMP0X Bus
APORT0Y
EFM32JG12 Family Data Sheet
Pin Definitions
PF7 is available on port APORT2X as CH23, the register field enumeration to connect to PF7 would be APORT2XCH23. The shared
bus used by this connection is indicated in the Bus column.
Table 6.5. ACMP0 Bus and Pin Mapping
Rev. 1.2 | 105
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PD8
PD10
PD12
PD14
PA0
PA2
PA4
PA6
PB6
PB8
PB10
PB12
PB14
BUSDY
PD9
PD11
PD13
PD15
PA1
PA3
PA5
PA7
PB7
PB9
PB11
PD9
PD11
PD13
PD15
PA1
PA3
PA5
PA7
PB7
PB9
PB11
PB13
PB15
PB15
PB13
BUSCY
BUSDX
PD8
PD10
PD12
PD14
PA0
PA2
PA4
PA6
PB6
PB8
PB10
PB12
PB14
BUSCX
PC0
PC2
PC4
PC6
PC8
PC10
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSBY
PC1
PC3
PC5
PC7
PC9
PC11
PF1
PF3
PF5
PF7
PF9
PF11
PF13
PF15
BUSBX
PC1
PC3
PC5
PC7
PC9
PC11
PF1
PF3
PF5
PF7
PF9
PF11
PF13
PF15
BUSAY
PC0
PC2
PC4
PC6
PC8
PC10
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSAX
APORT4Y APORT4X APORT3Y APORT3X APORT2Y APORT2X APORT1Y APORT1X
APORT0X
Port
PJ14
PJ15
PJ14
PJ15
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
CH16
CH17
CH18
CH19
CH20
CH21
CH22
CH23
CH24
CH25
CH26
CH27
CH28
CH29
CH30
CH31
BUSACMP1Y BUSACMP1X Bus
APORT0Y
EFM32JG12 Family Data Sheet
Pin Definitions
Table 6.6. ACMP1 Bus and Pin Mapping
Rev. 1.2 | 106
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PD8
PD10
PD12
PD14
PA0
PA2
PA4
PA6
PB6
PB8
PB10
PB12
PB14
BUSDY
PD9
PD11
PD13
PD15
PA1
PA3
PA5
PA7
PB7
PB9
PB11
PD9
PD11
PD13
PD15
PA1
PA3
PA5
PA7
PB7
PB9
PB11
PB13
PB15
PB15
PB13
BUSCY
BUSDX
PD8
PD10
PD12
PD14
PA0
PA2
PA4
PA6
PB6
PB8
PB10
PB12
PB14
BUSCX
PC0
PC2
PC4
PC6
PC8
PC10
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSBY
PC1
PC3
PC5
PC7
PC9
PC11
PF1
PF3
PF5
PF7
PF9
PF11
PF13
PF15
BUSBX
PC1
PC3
PC5
PC7
PC9
PC11
PF1
PF3
PF5
PF7
PF9
PF11
PF13
PF15
BUSAY
PC0
PC2
PC4
PC6
PC8
PC10
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSAX
APORT4Y APORT4X APORT3Y APORT3X APORT2Y APORT2X APORT1Y APORT1X
APORT0X
Port
PI0
PI1
PI2
PI3
PI0
PI1
PI2
PI3
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
CH16
CH17
CH18
CH19
CH20
CH21
CH22
CH23
CH24
CH25
CH26
CH27
CH28
CH29
CH30
CH31
BUSADC0Y BUSADC0X Bus
APORT0Y
EFM32JG12 Family Data Sheet
Pin Definitions
Table 6.7. ADC0 Bus and Pin Mapping
Rev. 1.2 | 107
silabs.com | Building a more connected world.
PD9
PD11
PD13
PD15
PA1
PA3
PA5
PA7
PB7
PB9
PB11
PB13
PB15
BUSCY
PD8
PD10
PD12
PD14
PA0
PA2
PA4
PA6
PB6
PB8
PB10
PB12
PB14
BUSCX
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
CH16
CH17
CH18
CH19
CH20
CH21
CH22
CH23
CH24
CH25
CH26
CH27
CH28
CH29
CH30
CH31
Bus
APORT1Y APORT1X Port
PD8
PD10
PD12
PD14
PA0
PA2
PA4
PA6
PB6
PB8
PB10
PB12
PB14
BUSDY
PD9
PD11
PD13
PD15
PA1
PA3
PA5
PA7
PB7
PB9
PB11
PB13
PB15
BUSDX
PC0
PC2
PC4
PC6
PC8
PC10
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSBY
PC1
PC3
PC5
PC7
PC9
PC11
PF1
PF3
PF5
PF7
PF9
PF11
PF13
PF15
BUSBX
APORT4Y APORT4X APORT2Y APORT2X
PD9
PD11
PD13
PD15
PA1
PA3
PA5
PA7
PB7
PB9
PB11
PB13
PB15
BUSCY
PD8
PD10
PD12
PD14
PA0
PA2
PA4
PA6
PB6
PB8
PB10
PB12
PB14
BUSCX
PC1
PC3
PC5
PC7
PC9
PC11
PF1
PF3
PF5
PF7
PF9
PF11
PF13
PF15
BUSAY
PC0
PC2
PC4
PC6
PC8
PC10
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSAX
APORT3Y APORT3X APORT1Y APORT1X
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
CH16
CH17
CH18
CH19
CH20
CH21
CH22
CH23
CH24
CH25
CH26
CH27
CH28
CH29
CH30
CH31
Bus
Port
EFM32JG12 Family Data Sheet
Pin Definitions
Table 6.8. CSEN Bus and Pin Mapping
CEXT
CEXT_SENSE
Table 6.9. IDAC0 Bus and Pin Mapping
Rev. 1.2 | 108
silabs.com | Building a more connected world.
PD9
PD11
PD13
PD15
PA1
PA3
PA5
PA7
PB7
PB9
PB11
PB13
PB15
BUSDX
PD8
PD10
PD12
PD14
PA0
PA2
PA4
PA6
PB6
PB8
PB10
PB12
PB14
BUSCX
PC1
PC3
PC5
PC7
PC9
PC11
PF1
PF3
PF5
PF7
PF9
PF11
PF13
PF15
BUSBX
PC0
PC2
PC4
PC6
PC8
PC10
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSAX
APORT4X APORT3X APORT2X APORT1X
PD8
PD10
PD12
PD14
PA0
PA2
PA4
PA6
PB6
PB8
PB10
PB12
PB14
BUSDY
PD9
PD11
PD13
PD15
PA1
PA3
PA5
PA7
PB7
PB9
PB11
PB13
PB15
BUSCY
PC0
PC2
PC4
PC6
PC8
PC10
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSBY
PC1
PC3
PC5
PC7
PC9
PC11
PF1
PF3
PF5
PF7
PF9
PF11
PF13
PF15
BUSAY
APORT4Y APORT3Y APORT2Y APORT1Y
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
CH16
CH17
CH18
CH19
CH20
CH21
CH22
CH23
CH24
CH25
CH26
CH27
CH28
CH29
CH30
CH31
Bus
Port
EFM32JG12 Family Data Sheet
Pin Definitions
Table 6.10. VDAC0 / OPA Bus and Pin Mapping
OPA0_N
OPA0_P
Rev. 1.2 | 109
silabs.com | Building a more connected world.
PD8
PD10
PD12
PD14
PA0
PA2
PA4
PA6
PB6
PB8
PB10
PB12
PB14
BUSDY
PD9
PD11
PD13
PD15
PA1
PA3
PA5
PA7
PB7
PB9
PB11
PB13
PB15
BUSCY
PC0
PC2
PC4
PC6
PC8
PC10
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSBY
PC1
PC3
PC5
PC7
PC9
PC11
PF1
PF3
PF5
PF7
PF9
PF11
PF13
PF15
BUSAY
APORT4Y APORT3Y APORT2Y APORT1Y
PD9
PD11
PD13
PD15
PA1
PA3
PA5
PA7
PB7
PB9
PB11
PB13
PB15
BUSDX
PD8
PD10
PD12
PD14
PA0
PA2
PA4
PA6
PB6
PB8
PB10
PB12
PB14
BUSCX
PC1
PC3
PC5
PC7
PC9
PC11
PF1
PF3
PF5
PF7
PF9
PF11
PF13
PF15
BUSBX
PC0
PC2
PC4
PC6
PC8
PC10
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSAX
APORT4X APORT3X APORT2X APORT1X
PD8
PD10
PD12
PD14
PA0
PA2
PA4
PA6
PB6
PB8
PB10
PB12
PB14
BUSDY
PD9
PD11
PD13
PD15
PA1
PA3
PA5
PA7
PB7
PB9
PB11
PB13
PB15
BUSCY
PC0
PC2
PC4
PC6
PC8
PC10
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSBY
PC1
PC3
PC5
PC7
PC9
PC11
PF1
PF3
PF5
PF7
PF9
PF11
PF13
PF15
BUSAY
APORT4Y APORT3Y APORT2Y APORT1Y
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
CH16
CH17
CH18
CH19
CH20
CH21
CH22
CH23
CH24
CH25
CH26
CH27
CH28
CH29
CH30
CH31
Bus
Port
EFM32JG12 Family Data Sheet
Pin Definitions
OPA1_N
OPA1_P
OPA2_N
Rev. 1.2 | 110
silabs.com | Building a more connected world.
PD8
PD10
PD12
PD14
PA0
PA2
PA4
PA6
PB6
PB8
PB10
PB12
PB14
BUSDY
PD9
PD11
PD13
PD15
PA1
PA3
PA5
PA7
PB7
PB9
PB11
PB13
PB15
BUSCY
PC0
PC2
PC4
PC6
PC8
PC10
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSBY
PC1
PC3
PC5
PC7
PC9
PC11
PF1
PF3
PF5
PF7
PF9
PF11
PF13
PF15
BUSAY
APORT4Y APORT3Y APORT2Y APORT1Y
PD9
PD11
PD13
PD15
PA1
PA3
PA5
PA7
PB7
PB9
PB11
PB13
PB15
BUSDX
PD8
PD10
PD12
PD14
PA0
PA2
PA4
PA6
PB6
PB8
PB10
PB12
PB14
BUSCX
PC1
PC3
PC5
PC7
PC9
PC11
PF1
PF3
PF5
PF7
PF9
PF11
PF13
PF15
BUSBX
PC0
PC2
PC4
PC6
PC8
PC10
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSAX
APORT4X APORT3X APORT2X APORT1X
PD8
PD10
PD12
PD14
PA0
PA2
PA4
PA6
PB6
PB8
PB10
PB12
PB14
BUSDY
PD9
PD11
PD13
PD15
PA1
PA3
PA5
PA7
PB7
PB9
PB11
PB13
PB15
BUSCY
PC0
PC2
PC4
PC6
PC8
PC10
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSBY
PC1
PC3
PC5
PC7
PC9
PC11
PF1
PF3
PF5
PF7
PF9
PF11
PF13
PF15
BUSAY
APORT4Y APORT3Y APORT2Y APORT1Y
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
CH16
CH17
CH18
CH19
CH20
CH21
CH22
CH23
CH24
CH25
CH26
CH27
CH28
CH29
CH30
CH31
Bus
Port
EFM32JG12 Family Data Sheet
Pin Definitions
OPA2_OUT
OPA2_P
VDAC0_OUT0 / OPA0_OUT
Rev. 1.2 | 111
silabs.com | Building a more connected world.
PD8
PD10
PD12
PD14
PA0
PA2
PA4
PA6
PB6
PB8
PB10
PB12
PB14
BUSDY
PD9
PD11
PD13
PD15
PA1
PA3
PA5
PA7
PB7
PB9
PB11
PB13
PB15
BUSCY
PC0
PC2
PC4
PC6
PC8
PC10
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
BUSBY
PC1
PC3
PC5
PC7
PC9
PC11
PF1
PF3
PF5
PF7
PF9
PF11
PF13
PF15
BUSAY
APORT4Y APORT3Y APORT2Y APORT1Y
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
CH16
CH17
CH18
CH19
CH20
CH21
CH22
CH23
CH24
CH25
CH26
CH27
CH28
CH29
CH30
CH31
Bus
Port
EFM32JG12 Family Data Sheet
Pin Definitions
VDAC0_OUT1 / OPA1_OUT
Rev. 1.2 | 112
EFM32JG12 Family Data Sheet
BGA125 Package Specifications
7. BGA125 Package Specifications
7.1 BGA125 Package Dimensions
Figure 7.1. BGA125 Package Drawing
silabs.com | Building a more connected world.
Rev. 1.2 | 113
EFM32JG12 Family Data Sheet
BGA125 Package Specifications
Table 7.1. BGA125 Package Dimensions
Dimension
Min
Typ
Max
A
0.80
0.87
0.94
A1
0.16
0.21
0.26
A2
0.61
0.66
0.71
c
0.17
0.21
0.25
D
6.90
7.00
7.10
E
6.90
7.00
7.10
D1
—
6.00
—
E1
—
6.00
—
e
—
0.50
—
b
0.25
0.30
0.35
aaa
0.10
bbb
0.10
ddd
0.08
eee
0.15
fff
0.05
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
silabs.com | Building a more connected world.
Rev. 1.2 | 114
EFM32JG12 Family Data Sheet
BGA125 Package Specifications
7.2 BGA125 PCB Land Pattern
Figure 7.2. BGA125 PCB Land Pattern Drawing
silabs.com | Building a more connected world.
Rev. 1.2 | 115
EFM32JG12 Family Data Sheet
BGA125 Package Specifications
Table 7.2. BGA125 PCB Land Pattern Dimensions
Dimension
Min
Nom
X
0.25
C1
6.00
C2
6.00
E1
0.5
E2
0.5
Max
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
6. The stencil thickness should be 0.125 mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1.
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
silabs.com | Building a more connected world.
Rev. 1.2 | 116
EFM32JG12 Family Data Sheet
BGA125 Package Specifications
7.3 BGA125 Package Marking
EFM32
PPPPPPPPPP
TTTTTT
YYWW
Figure 7.3. BGA125 Package Marking
The package marking consists of:
• PPPPPPPPPP – The part number designation.
• TTTTTT – A trace or manufacturing code. The first letter is the device revision.
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
silabs.com | Building a more connected world.
Rev. 1.2 | 117
EFM32JG12 Family Data Sheet
QFN48 Package Specifications
8. QFN48 Package Specifications
8.1 QFN48 Package Dimensions
Figure 8.1. QFN48 Package Drawing
silabs.com | Building a more connected world.
Rev. 1.2 | 118
EFM32JG12 Family Data Sheet
QFN48 Package Specifications
Table 8.1. QFN48 Package Dimensions
Dimension
Min
Typ
Max
A
0.80
0.85
0.90
A1
0.00
0.02
0.05
A3
0.20 REF
b
0.18
0.25
0.30
D
6.90
7.00
7.10
E
6.90
7.00
7.10
D2
5.15
5.30
5.45
E2
5.15
5.30
5.45
e
0.50 BSC
L
0.30
0.40
0.50
K
0.20
—
—
R
0.09
—
—
aaa
0.15
bbb
0.10
ccc
0.10
ddd
0.05
eee
0.08
fff
0.10
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VKKD-4.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
silabs.com | Building a more connected world.
Rev. 1.2 | 119
EFM32JG12 Family Data Sheet
QFN48 Package Specifications
8.2 QFN48 PCB Land Pattern
Figure 8.2. QFN48 PCB Land Pattern Drawing
silabs.com | Building a more connected world.
Rev. 1.2 | 120
EFM32JG12 Family Data Sheet
QFN48 Package Specifications
Table 8.2. QFN48 PCB Land Pattern Dimensions
Dimension
Typ
S1
6.01
S
6.01
L1
4.70
W1
4.70
e
0.50
W
0.26
L
0.86
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads.
7. A 4x4 array of 0.75 mm square openings on a 1.00 mm pitch can be used for the center ground pad.
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
silabs.com | Building a more connected world.
Rev. 1.2 | 121
EFM32JG12 Family Data Sheet
QFN48 Package Specifications
8.3 QFN48 Package Marking
EFM32
PPPPPPPPPP
TTTTTT
YYWW
Figure 8.3. QFN48 Package Marking
The package marking consists of:
• PPPPPPPPPP – The part number designation.
• TTTTTT – A trace or manufacturing code. The first letter is the device revision.
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
silabs.com | Building a more connected world.
Rev. 1.2 | 122
EFM32JG12 Family Data Sheet
Revision History
9. Revision History
Revision 1.2
November, 2019
•
•
•
•
In the front page block diagram, updated the lowest energy mode for LETIMER.
Updated 3.5.4 Low Energy Timer (LETIMER) lowest energy mode.
Added a Note about the operating voltage in 3.7.3 True Random Number Generator (TRNG).
Reworded or removed mentions of “modules” in reference to device peripherals in system overview.
Revision 1.1
February, 2018
• Updated 2. Ordering Information to revision-C OPNs.
• System Overview Updates
• Added "4-pin JTAG" to debug interface options in Processor Core section.
• Memory maps updated with LE peripherals and new formatting.
• 4.1.1 Absolute Maximum Ratings: Added footnotes to clarify VDIGPIN specification for 5V tolerant GPIO.
• Table 4.2 General Operating Conditions on page 19:
• Added footnote about IOVDD voltage restriction when CSEN peripheral is used with chopping enabled.
• Added footnote for additional information on peak current during voltage scaling operations.
• 4.1.4 DC-DC Converter: Expanded footnote on control loop settings to include appnote and register field reference.
• Table 4.16 Flash Memory Characteristics5 on page 34: Device Erase Time typical values corrected from 69 to 82 ms.
• Table 4.21 Digital to Analog Converter (VDAC) on page 43: Gain Error min/max specifications relaxed for REFSEL on 1V25LN,
VDD, and EXT settings.
• Table 4.22 Current Digital to Analog Converter (IDAC) on page 46: Total accuracy STEPSEL value setting corrected from 0x80 to
0x10.
• Table 4.26 Analog Port (APORT) on page 53: Operation in EM2/EM3 supply current changed from 915 to 67 nA (silicon fix from rev
B to C).
Revision 1.0
2017-06-30
•
•
•
•
Finalized specification tables. All tables were updated with latest characterization data and production test limits.
Updated typical performance graphs for DC-DC.
Minor typographical, clarity, and consistency improvements.
Condensed pin function tables with new formatting.
Revision 0.5
2017-02-10
• Updated Feature List and Front Page with latest characterization numbers.
• List of OPNs in Ordering Table consolidated.
• Electrical Characteristics Table Changes
• All specification tables updated with latest characterization data and production test limits.
• Split HFRCO/AUXHFRCO table into separate tables for HFRCO and AUXHFRCO.
• OPAMP, CSEN, and VDAC specification line items updated to match test conditions.
• Added tables for Analog Port (APORT) and Pulse Counter (PCNT).
• Added Typical Performance Curves for supply current and DCDC parameters.
• Added APORT Connection Diagram.
silabs.com | Building a more connected world.
Rev. 1.2 | 123
EFM32JG12 Family Data Sheet
Revision History
Revision 0.2
December 9th, 2016
Initial release.
silabs.com | Building a more connected world.
Rev. 1.2 | 124
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Disclaimer
Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or
intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"
parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes
without further notice to the product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information.
Without prior notification, Silicon Labs may update product firmware during the manufacturing process for security or reliability reasons. Such changes will not alter the specifications or the
performance of the product. Silicon Labs shall have no liability for the consequences of use of the information supplied in this document. This document does not imply or expressly grant
any license to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any FDA Class III devices, applications for which FDA premarket
approval is required or Life Support Systems without the specific written consent of Silicon Labs. A "Life Support System" is any product or system intended to support or sustain life and/or
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unauthorized applications.
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