EFM32TG-STK3300

...the world's most energy friendly microcontrollers EFM32TG Reference Manual Tiny Gecko Series • • • • • 32-bit ARM Cortex-M3 processor running at up to 32 MHz Up to 32 kB Flash and 4 kB RAM memory Energy efficient and autonomous peripherals Ultra low power Energy Modes with sub-µA operation Fast wake-up time of only 2 µs The EFM32TG microcontroller series revolutionizes the 8- to 32-bit market with a combination of unmatched performance and ultra low power consumption in both active- and sleep modes. EFM32TG devices consume as little as 150 µA/MHz in run mode, and as little as 1.0 µA with a Real Time Counter running, Brown-out and full RAM and register retention. EFM32TG's low energy consumption outperforms any other available 8-, 16-, and 32-bit solution. The EFM32TG includes autonomous and energy efficient peripherals, high overall chip- and analog integration, and the performance of the industry standard 32-bit ARM Cortex-M3 processor. ...the world's most energy friendly microcontrollers 1 Energy Friendly Microcontrollers 1.1 Typical Applications The EFM32TG Tiny Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications. These devices are developed to minimize the energy consumption by lowering both the power and the active time, over all phases of MCU operation. This unique combination of ultra low energy consumption and the performance of the 32-bit ARM Cortex-M3 processor, help designers get more out of the available energy in a variety of applications. Ultra low energy EFM32TG microcontrollers are perfect for: • • • • • • • Gas metering Energy metering Water metering Smart metering Alarm and security systems Health and fitness applications Industrial and home automation 0 1 2 3 4 1.2 EFM32TG Development Because EFM32TG use the Cortex-M3 CPU, embedded designers benefit from the largest development ecosystem in the industry, the ARM ecosystem. The development suite spans the whole design process and includes powerful debug tools, and some of the world’s top brand compilers. Libraries with documentation and user examples shorten time from idea to market. The range of EFM32TG devices ensure easy migration and feature upgrade possibilities. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 2 www.silabs.com ...the world's most energy friendly microcontrollers 2 About This Document This document contains reference material for the EFM32TG series of microcontrollers. All modules and peripherals in the EFM32TG series devices are described in general terms. Not all modules are present in all devices, and the feature set for each device might vary. Such differences, including pin-out, are covered in the device-specific datasheets. 2.1 Conventions Register Names Register names are given as a module name prefix followed by the short register name: TIMERn_CTRL - Control Register The "n" denotes the numeric instance for modules that might have more than one instance. Some registers are grouped which leads to a group name following the module prefix: GPIO_Px_DOUT - Port Data Out Register, where x denotes the port instance (A,B,...). Bit Fields Registers contain one or more bit fields which can be 1 to 32 bits wide. Multi-bit fields are denoted with (x:y), where x is the start bit and y is the end bit. Address The address for each register can be found by adding the base address of the module (found in the Memory Map), and the offset address for the register (found in module Register Map). Access Type The register access types used in the register descriptions are explained in Table 2.1 (p. 3) . Table 2.1. Register Access Types Access Type Description R Read only. Writes are ignored. RW Readable and writable. RW1 Readable and writable. Only writes to 1 have effect. RW1H Readable, writable and updated by hardware. Only writes to 1 have effect. W1 Read value undefined. Only writes to 1 have effect. W Write only. Read value undefined. RWH Readable, writable and updated by hardware. Number format 0x prefix is used for hexadecimal numbers. 0b prefix is used for binary numbers. Numbers without prefix are in decimal representation. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 3 www.silabs.com ...the world's most energy friendly microcontrollers Reserved Registers and bit fields marked with reserved are reserved for future use. These should be written to 0 unless otherwise stated in the Register Description. Reserved bits might be read as 1 in future devices. Reset Value The reset value denotes the value after reset. Registers denoted with X have an unknown reset value and need to be initialized before use. Note that, before these registers are initialized, read-modify-write operations might result in undefined register values. Pin Connections Pin connections are given as a module prefix followed by a short pin name: USn_TX (USARTn TX pin) The pin locations referenced in this document are given in the device-specific datasheet. 2.2 Related Documentation Further documentation on the EFM32TG family and the ARM Cortex-M3 can be found at the Silicon Laboratories and ARM web pages: www.silabs.com www.arm.com 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 4 www.silabs.com ...the world's most energy friendly microcontrollers 3 System Overview 3.1 Introduction The EFM32 MCUs are the world’s most energy friendly microcontrollers. With a unique combination of the powerful 32-bit ARM Cortex-M3, innovative low energy techniques, short wake-up time from energy saving modes, and a wide selection of peripherals, the EFM32TG microcontroller is well suited for any battery operated application, as well as other systems requiring high performance and low-energy consumption, see Figure 3.1 (p. 7) . 3.2 Features • ARM Cortex-M3 CPU platform • High Performance 32-bit processor @ up to 32 MHz • Wake-up Interrupt Controller • Flexible Energy Management System • 20 nA @ 3 V Shutoff Mode • 0.6 µA @ 3 V Stop Mode, including Power-on Reset, Brown-out Detector, RAM and CPU retention • 1.0 µA @ 3 V Deep Sleep Mode, including RTC with 32.768 kHz oscillator, Power-on Reset, Brown-out Detector, RAM and CPU retention • 51 µA/MHz @ 3 V Sleep Mode • 150 µA/MHz @ 3 V Run Mode, with code executed from flash • 32/16/8/4 KB Flash • 4/2 KB RAM • Up to 56 General Purpose I/O pins • Configurable push-pull, open-drain, pull-up/down, input filter, drive strength • Configurable peripheral I/O locations • 16 asynchronous external interrupts • Output state retention and wake-up from Shutoff Mode • 8 Channel DMA Controller • Alternate/primary descriptors with scatter-gather/ping-pong operation • 8 Channel Peripheral Reflex System • Autonomous inter-peripheral signaling enables smart operation in low energy modes • Integrated LCD Controller for up to 8×20 Segments • Voltage boost, adjustable contrast adjustment and autonomous animation feature • Hardware AES with 128/256-bit Keys in 54/75 cycles • Communication interfaces • 2× Universal Synchronous/Asynchronous Receiver/Transmitter • SPI/SmartCard (ISO 7816)/IrDA (USART0)/I2S (USART1) • Triple buffered full/half-duplex operation • 4-16 data bits • 1× Low Energy UART • Autonomous operation with DMA in Deep Sleep Mode 2 • 1× I C Interface with SMBus support • Address recognition in Stop Mode • Timers/Counters • 2× 16-bit Timer/Counter • 3 Compare/Capture/PWM channels • 16-bit Low Energy Timer • 24-bit Real-Time Counter • 1× 16-bit Pulse Counter 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 5 www.silabs.com ...the world's most energy friendly microcontrollers • • • • • • • • Asynchronous pulse counting/quadrature decoding • Watchdog Timer with dedicated RC oscillator @ 50 nA Ultra low power precision analog peripherals • 12-bit 1 Msamples/s Analog to Digital Converter • 8 input channels and on-chip temperature sensor • Single ended or differential operation • Conversion tailgating for predictable latency • 12-bit 500 ksamples/s Digital to Analog Converter • 2 single ended channels/1 differential channel • Up to 3 Operational Amplifiers • Supports rail-to-rail inputs and outputs • Programmable gain • 2× Analog Comparator • Programmable speed/current • Capacitive sensing with up to 8 inputs • Supply Voltage Comparator Ultra low power sensor interface • Autonomous sensor monitoring in Deep Sleep Mode • Wide range of sensors supported, including LC sensors and capacitive buttons Ultra efficient Power-on Reset and Brown-Out Detector 2-pin Serial Wire Debug interface • 1-pin Serial Wire Viewer Temperature range -40 - 85°C Single power supply 1.98 - 3.8 V Packages • QFN24 • QFN32 • QFN64 • TQFP48 • TQFP64 3.3 Block Diagram Figure 3.1 (p. 7) shows the block diagram of EFM32TG. The color indicates peripheral availability in the different energy modes, described in Section 3.4 (p. 7) . 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 6 www.silabs.com ...the world's most energy friendly microcontrollers Figure 3.1. Block Diagram of EFM32TG Tiny Gecko Core and Memory Clock Managem ent ARM Cortex- M3 processor Flash Memory Debug Interface RAM Memory DMA Controller Energy Managem ent High Frequency Crystal Oscilla tor High Frequency RC Oscilla tor Lo w Frequency Crystal Oscilla tor Lo w Frequency RC Oscilla tor Watchdog Oscillator Voltage Regulator Voltage Comparator Power-on Reset Brown-out Detector 32-bit bus Peripheral Reflex System Serial Interfaces Ex ternal Interrupts USA RT Low Energy UART I/O Ports I2C Tim ers/ Triggers Timer/ Counter General Purpose I/ O LESENSE ADC Low Energy Timer Real Time Counter DAC Pulse Counter Watchdog Timer Analog Comparator Pin Reset Security Analog Interfaces LCD Controller AES Operational Amplifier Figure 3.2. Energy Mode Indicator 0 1 2 3 4 Note In the energy mode indicator, the numbers indicates Energy Mode, i.e EM0-EM4. 3.4 Energy Modes There are five different Energy Modes (EM0-EM4) in the EFM32TG, see Table 3.1 (p. 8) . The EFM32TG is designed to achieve a high degree of autonomous operation in low energy modes. The intelligent combination of peripherals, RAM with data retention, DMA, low-power oscillators, and short wake-up time, makes it attractive to remain in low energy modes for long periods and thus saving energy consumption. Tip Throughout this document, the first figure in every module description contains an Energy Mode Indicator showing which energy mode(s) the module can operate (see Table 3.1 (p. 8) ). 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 7 www.silabs.com ...the world's most energy friendly microcontrollers Table 3.1. Energy Mode Description Energy Mode Name Description EM0 – Energy Mode 0 0 1 2 3 0 1 2 3 0 1 2 3 (Run mode) In EM0, the CPU is running and consuming as little as 150 µA/MHz, when running code from flash. All peripherals can be active. EM1 – Energy Mode 1 (Sleep Mode) In EM1, the CPU is sleeping and the power consumption is only 51 µA/MHz. All peripherals, including DMA, PRS and memory system, are still available. EM2 – Energy Mode 2 (Deep Sleep Mode) In EM2 the high frequency oscillator is turned off, but with the 32.768 kHz oscillator running, selected low energy peripherals (LCD, RTC, LETIMER, 2 PCNT, LEUART, I C, LESENSE, OPAMP, WDOG and ACMP) are still available. This gives a high degree of autonomous operation with a current consumption as low as 1.0 µA with RTC enabled. Power-on Reset, Brown-out Detection and full RAM and CPU retention is also included. EM3 - Energy Mode 3 (Stop Mode) In EM3, the low-frequency oscillator is disabled, but there is still full CPU and RAM retention, as well as Power-on Reset, Pin reset, EM4 wake-up and Brown-out Detection, with a consumption of only 0.6 µA. The low-power 2 ACMP, asynchronous external interrupt, PCNT, and I C can wake-up the device. Even in this mode, the wake-up time is a few microseconds. 4 4 4 0 1 2 3 4 0 1 2 3 4 EM4 – Energy Mode 4 (Shutoff Mode) In EM4, the current is down to 20 nA and all chip functionality is turned off except the pin reset, GPIO pin wake-up, GPIO pin retention and the PowerOn Reset. All pins are put into their reset state. 3.5 Product Overview Table 3.2 (p. 8) shows a device overview of the EFM32TG Microcontroller Series, including peripheral functionality. For more information, the reader is referred to the device specific datasheets. USART LEUART LETIMER RTC PCNT Watchdog ADC(pins) DAC(pins) AES EBI LESENSE Op-Amps 4 1 17 - 1 1 1 2 (6) 1 1 1 1 - - 2 (4) - - Y - QFN24 108F8 8 2 17 - 1 1 1 2 (6) 1 1 1 1 - - 2 (4) - - Y - QFN24 108F16 16 4 17 - 1 1 1 2 (6) 1 1 1 1 - - 2 (4) - - Y - QFN24 108F32 32 4 17 - 1 1 1 2 (6) 1 1 1 1 - - 2 (4) - - Y - QFN24 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 8 2 Package LCD ACMP(pins) GPIO(pins) Timer(PWM) RAM 108F4 I C Flash EFM32TG Part # Table 3.2. EFM32TG Microcontroller Series www.silabs.com LCD USART LEUART LETIMER RTC PCNT Watchdog ADC(pins) DAC(pins) ACMP(pins) AES EBI LESENSE Op-Amps 4 1 17 - 1 1 1 2 (6) 1 1 1 1 1 (2) 2 (1) 2 (4) Y - Y 3 QFN24 110F8 8 2 17 - 1 1 1 2 (6) 1 1 1 1 1 (2) 2 (1) 2 (4) Y - Y 3 QFN24 110F16 16 4 17 - 1 1 1 2 (6) 1 1 1 1 1 (2) 2 (1) 2 (4) Y - Y 3 QFN24 110F32 32 4 17 - 1 1 1 2 (6) 1 1 1 1 1 (2) 2 (1) 2 (4) Y - Y 3 QFN24 210F8 8 2 24 - 2 1 1 2 (6) 1 1 1 1 1 (4) 2 (1) 2 (5) Y - Y 3 QFN32 210F16 16 4 24 - 2 1 1 2 (6) 1 1 1 1 1 (4) 2 (1) 2 (5) Y - Y 3 QFN32 210F32 32 4 24 - 2 1 1 2 (6) 1 1 1 1 1 (4) 2 (1) 2 (5) Y - Y 3 QFN32 222F8 8 2 37 - 2 1 1 2 (6) 1 1 1 1 1 (4) 2 (1) 2 (12) Y - Y 3 QFP48 222F16 16 4 37 - 2 1 1 2 (6) 1 1 1 1 1 (4) 2 (1) 2 (12) Y - Y 3 QFP48 222F32 32 4 37 - 2 1 1 2 (6) 1 1 1 1 1 (4) 2 (1) 2 (12) Y - Y 3 QFP48 225F8 8 2 37 - 2 1 1 2 (6) 1 1 1 1 1 (4) 2 (1) 2 (12) Y - Y 3 BGA48 225F16 16 4 37 - 2 1 1 2 (6) 1 1 1 1 1 (4) 2 (1) 2 (12) Y - Y 3 BGA48 225F32 32 4 37 - 2 1 1 2 (6) 1 1 1 1 1 (4) 2 (1) 2 (12) Y - Y 3 BGA48 230F8 8 2 56 - 2 1 1 2 (6) 1 1 1 1 1 (8) 2 (2) 2 (16) Y - Y 3 QFN64 230F16 16 4 56 - 2 1 1 2 (6) 1 1 1 1 1 (8) 2 (2) 2 (16) Y - Y 3 QFN64 230F32 32 4 56 - 2 1 1 2 (6) 1 1 1 1 1 (8) 2 (2) 2 (16) Y - Y 3 QFN64 232F8 8 2 53 - 2 1 1 2 (6) 1 1 1 1 1 (8) 2 (2) 2 (16) Y - Y 3 QFP64 232F16 16 4 53 - 2 1 1 2 (6) 1 1 1 1 1 (8) 2 (2) 2 (16) Y - Y 3 QFP64 232F32 32 4 53 - 2 1 1 2 (6) 1 1 1 1 1 (8) 2 (2) 2 (16) Y - Y 3 QFP64 822F8 8 2 37 Y 2 1 1 2 (6) 1 1 1 1 1 (5) 2 (1) 2 (4) Y - Y 3 QFP48 822F16 16 4 37 Y 2 1 1 2 (6) 1 1 1 1 1 (5) 2 (1) 2 (4) Y - Y 3 QFP48 822F32 32 4 37 Y 2 1 1 2 (6) 1 1 1 1 1 (5) 2 (1) 2 (4) Y - Y 3 QFP48 825F8 8 2 37 Y 2 1 1 2 (6) 1 1 1 1 1 (5) 2 (1) 2 (4) Y - Y 3 BGA48 825F16 16 4 37 Y 2 1 1 2 (6) 1 1 1 1 1 (5) 2 (1) 2 (4) Y - Y 3 BGA48 825F32 32 4 37 Y 2 1 1 2 (6) 1 1 1 1 1 (5) 2 (1) 2 (4) Y - Y 3 BGA48 840F8 8 2 56 Y 2 1 1 2 (6) 1 1 1 1 1 (8) 2 (2) 2 (8) Y - Y 3 QFN64 840F16 16 4 56 Y 2 1 1 2 (6) 1 1 1 1 1 (8) 2 (2) 2 (8) Y - Y 3 QFN64 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 9 2 Package GPIO(pins) Timer(PWM) RAM 110F4 I C Flash EFM32TG Part # ...the world's most energy friendly microcontrollers www.silabs.com LCD USART LEUART LETIMER RTC PCNT Watchdog ADC(pins) DAC(pins) ACMP(pins) AES EBI LESENSE Op-Amps 32 4 56 Y 2 1 1 2 (6) 1 1 1 1 1 (8) 2 (2) 2 (8) Y - Y 3 QFN64 842F8 8 2 53 Y 2 1 1 2 (6) 1 1 1 1 1 (8) 2 (2) 2 (8) Y - Y 3 QFP64 842F16 16 4 53 Y 2 1 1 2 (6) 1 1 1 1 1 (8) 2 (2) 2 (8) Y - Y 3 QFP64 842F32 32 4 53 Y 2 1 1 2 (6) 1 1 1 1 1 (8) 2 (2) 2 (8) Y - Y 3 QFP64 2 Package GPIO(pins) Timer(PWM) RAM 840F32 I C Flash EFM32TG Part # ...the world's most energy friendly microcontrollers 3.6 Device Revision The device revision number is read from the ROM Table. The major revision number and the chip family number is read from PID0 and PID1 registers. The minor revision number is extracted from the PID2 and PID3 registers, as illustrated in Figure 3.3 (p. 10) . The Fam[5:2] and Fam[1:0] must be combined to complete the chip family number, while the Minor Rev[7:4] and Minor Rev[3:0] must be combined to form the complete revision number. Figure 3.3. Revision Number Extraction 31:8 31:7 PID2 (0 xE0 0 FFFE8 ) 7:4 3:0 Minor Rev[7:4] 31:8 PID3 (0 xE0 0 FFFEC) 7:4 3:0 Minor Rev[3:0] PID0 (0 xE0 0 FFFE0 ) 6:5 5:0 Fam [1:0] Major Rev[5:0] PID1 (0 xE0 0 FFFE4 ) 31:4 3:0 Fam [5:2] For the latest revision of the Tiny Gecko family, the chip family number is 0x01 and the major revision number is 0x01. The minor revision number is to be interpreted according to Table 3.3 (p. 10) . Table 3.3. Minor Revision Number Interpretation Minor Rev[7:0] Revision 0x00 A 0x01 B 0x02 C 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 10 www.silabs.com ...the world's most energy friendly microcontrollers 4 System Processor Quick Facts What? The industry leading Cortex-M3 processor from ARM is the CPU in the EFM32TG microcontrollers. Why? 0 1 2 3 The ARM Cortex-M3 is designed for exceptional short response time, high code density, and high 32-bit throughput while maintaining a strict cost and power consumption budget. 4 How? Combined with the ultra low energy peripherals available, the Cortex-M3 makes the EFM32TG devices perfect for 8- to 32bit applications. The processor is featuring a Harvard architecture, 3 stage pipeline, single cycle instructions, Thumb-2 instruction set support, and fast interrupt handling. 4.1 Introduction The ARM Cortex-M3 32-bit RISC processor provides outstanding computational performance and exceptional system response to interrupts while meeting low cost requirements and low power consumption. The ARM Cortex-M3 implemented is revision r2p1. 4.2 Features • Harvard Architecture • Separate data and program memory buses (No memory bottleneck as for a single-bus system) • 3-stage pipeline • Thumb-2 instruction set • Enhanced levels of performance, energy efficiency, and code density • Single-cycle multiply and efficient divide instructions • 32-bit multiplication in a single cycle • Signed and unsigned divide operations between 2 and 12 cycles • Atomic bit manipulation with bit banding • Direct access to single bits of data • Two 1MB bit banding regions for memory and peripherals mapping to 32MB alias regions • Atomic operation which cannot be interrupted by other bus activities • 1.25 DMIPS/MHz • 24-bit System Tick Timer for Real-Time Operating System (RTOS) • Excellent 32-bit migration choice for 8/16 bit architecture based designs • Simplified stack-based programmer's model is compatible with traditional ARM architecture and retains the programming simplicity of legacy 8- and 16-bit architectures • Unaligned data storage and access 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 11 www.silabs.com ...the world's most energy friendly microcontrollers • Continuous storage of data requiring different byte lengths • Data access in a single core clock cycle • Integrated power modes • Sleep Now mode for immediate transfer to low power state • Sleep on Exit mode for entry into low power state after the servicing of an interrupt • Ability to extend power savings to other system components • Optimized for low latency, nested interrupts 4.3 Functional Description For a full functional description of the ARM Cortex-M3 (r2p1) implementation in the EFM32TG family, the reader is referred to the EFM32 Cortex-M3 Reference Manual. 4.3.1 Interrupt Operation Figure 4.1. Interrupt Operation Module IFS[n] Cortex - M3 NVIC IFC[n] IEN[n] SETENA[n]/ CLRENA[n] Active interrupt Interrupt condition set clear IRQ IF[n] set Interrupt request clear SETPEND[n]/ CLRPEND[n] Software generated interrupt The EFM32TG devices have up to 23 interrupt request lines (IRQ) which are connected to the CortexM3. Each of these lines (shown in Table 4.1 (p. 12) ) are connected to one or more interrupt flags in one or more modules. The interrupt flags are set by hardware on an interrupt condition. It is also possible to set/clear the interrupt flags through the IFS/IFC registers. Each interrupt flag is then qualified with its own interrupt enable bit (IEN register), before being OR'ed with the other interrupt flags to generate the IRQ. A high IRQ line will set the corresponding pending bit (can also be set/cleared with the SETPEND/ CLRPEND bits in ISPR0/ICPR0) in the Cortex-M3 NVIC. The pending bit is then qualified with an enable bit (set/cleared with SETENA/CLRENA bits in ISER0/ICER0) before generating an interrupt request to the core. Figure 4.1 (p. 12) illustrates the interrupt system. For more information on how the interrupts are handled inside the Cortex-M3, the reader is referred to the EFM32 Cortex-M3 Reference Manual. Table 4.1. Interrupt Request Lines (IRQ) IRQ # Source 0 DMA 1 GPIO_EVEN 2 TIMER0 3 USART0_RX 4 USART0_TX 5 ACMP0/ACMP1 6 ADC0 7 DAC0 8 I2C0 9 GPIO_ODD 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 12 www.silabs.com ...the world's most energy friendly microcontrollers IRQ # Source 10 TIMER1 11 USART1_RX 12 USART1_TX 13 LESENSE 14 LEUART0 15 LETIMER0 16 PCNT0 17 RTC 18 CMU 19 VCMP 20 LCD 21 MSC 22 AES 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 13 www.silabs.com ...the world's most energy friendly microcontrollers 5 Memory and Bus System Quick Facts What? 0 1 2 3 A low latency memory system, including low energy flash and RAM with data retention, makes extended use of low-power energymodes possible. 4 Why? RAM retention reduces the need for storing data in flash and enables frequent use of the ultra low energy modes EM2 and EM3 with as little as 0.6 µA current consumption. Flash ARM Cortex- M3 RAM How? Peripherals DMA Controller Low energy and non-volatile flash memory stores program and application data in all energy modes and can easily be reprogrammed in system. Low leakage RAM, with data retention in EM0 to EM3, removes the data restore time penalty, and the DMA ensures fast autonomous transfers with predictable response time. 5.1 Introduction The EFM32TG contains an AMBA AHB Bus system allowing bus masters to access the memory mapped address space. A multilayer AHB bus matrix, using a Round-robin arbitration scheme, connects the master bus interfaces to the AHB slaves (Figure 5.1 (p. 15) ). The bus matrix allows several AHB slaves to be accessed simultaneously. An AMBA APB interface is used for the peripherals, which are accessed through an AHB-to-APB bridge connected to the AHB bus matrix. The AHB bus masters are: • Cortex-M3 ICode: Used for instruction fetches from Code memory (0x00000000 - 0x1FFFFFFF). • Cortex-M3 DCode: Used for debug and data access to Code memory (0x00000000 - 0x1FFFFFFF). • Cortex-M3 System: Used for instruction fetches, data and debug access to system space (0x20000000 - 0xDFFFFFFF). • DMA: Can access SRAM, Flash and peripherals (0x00000000 - 0xDFFFFFFF). 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 14 www.silabs.com ...the world's most energy friendly microcontrollers Figure 5.1. EFM32TG Bus System Cortex Flash AHB Multilayer Bus Matrix ICode RAM AES DCode System AHB/ APB Bridge Peripheral 0 DMA Peripheral n 5.2 Functional Description The memory segments are mapped together with the internal segments of the Cortex-M3 into the system memory map shown by Figure 5.2 (p. 16) 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 15 www.silabs.com ...the world's most energy friendly microcontrollers Figure 5.2. System Address Space The embedded SRAM is located at address 0x20000000 in the memory map of the EFM32TG. When running code located in SRAM starting at this address, the Cortex-M3 uses the System bus to fetch instructions. This results in reduced performance as the Cortex-M3 accesses stack, other data in SRAM and peripherals using the System bus. To be able to run code from SRAM efficiently, the SRAM is also mapped in the code space at address 0x10000000. When running code from this space, the Cortex-M3 fetches instructions through the I/D-Code bus interface, leaving the System bus for data access. The SRAM mapped into the code space can however only be accessed by the CPU, i.e. not the DMA. 5.2.1 Bit-banding The SRAM bit-band alias and peripheral bit-band alias regions are located at 0x22000000 and 0x42000000 respectively. Read and write operations to these regions are converted into masked singlebit reads and atomic single-bit writes to the embedded SRAM and peripherals of the EFM32TG. The standard approach to modify a single register or SRAM bit in the aliased regions, requires software to read the value of the byte, half-word or word containing the bit, modify the bit, and then write the byte, half-word or word back to the register or SRAM address. Using bit-banding, this read-modify-write can be done in a single atomic operation. As read-writeback, bit-masking and bit-shift operations are not necessary in software, code size is reduced and execution speed improved. The bit-band regions allows addressing each individual bit in the SRAM and peripheral areas of the memory map. To set or clear a bit in the embedded SRAM, write a 1 or a 0 to the following address: Memory SRAM Area Set/Clear Bit 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 16 www.silabs.com ...the world's most energy friendly microcontrollers bit_address = 0x22000000 + (address – 0x20000000) × 32 + bit × 4, (5.1) where address is the address of the 32-bit word containing the bit to modify, and bit is the index of the bit in the 32-bit word. To modify a bit in the Peripheral area, use the following address: Memory Peripheral Area Bit Modification bit_address = 0x42000000 + (address – 0x40000000) × 32 + bit × 4, (5.2) where address and bit are defined as above. Note that the AHB-peripheral AES does not support bit-banding. 5.2.2 Peripherals The peripherals are mapped into the peripheral memory segment, each with a fixed size address range according to Table 5.1 (p. 17) , Table 5.2 (p. 18) and Table 5.3 (p. 19) . Table 5.1. Memory System Core Peripherals Core peripherals Address range Peripheral 0x400E0400 – 0x41FFFFFF Reserved 0x400E0000 – 0x400E03FF AES 0x400CC400 – 0x400FFFFF Reserved 0x400CC000 – 0x400CC3FF PRS 0x400CA400 – 0x400CBFFF Reserved 0x400CA000 – 0x400CA3FF RMU 0x400C8400 – 0x400C9FFF Reserved 0x400C8000 – 0x400C83FF CMU 0x400C6400 – 0x400C7FFF Reserved 0x400C6000 – 0x400C63FF EMU 0x400C4000 – 0x400C5FFF Reserved 0x400C2000 – 0x400C3FFF DMA 0x400C0400 – 0x400C1FFF Reserved 0x400C0000 – 0x400C03FF MSC 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 17 www.silabs.com ...the world's most energy friendly microcontrollers Table 5.2. Memory System Low Energy Peripherals Low energy peripherals Address range Peripheral 0x4008A400 – 0x400BFFFF Reserved 0x4008C000 – 0x4008C3FF LESENSE 0x4008A000 – 0x4008A3FF LCD 0x40088400 – 0x40089FFF Reserved 0x40088000 – 0x400883FF WDOG 0x40086C00 – 0x40087FFF Reserved 0x40086000 – 0x400863FF PCNT0 0x40084800 – 0x40085FFF Reserved 0x40084000 – 0x400843FF LEUART0 0x40082400 – 0x40083FFF Reserved 0x40082000 – 0x400823FF LETIMER0 0x40080400 – 0x40081FFF Reserved 0x40080000 – 0x400803FF RTC 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 18 www.silabs.com ...the world's most energy friendly microcontrollers Table 5.3. Memory System Peripherals Peripherals Address range Peripheral 0x40010C00 – 0x4007FFFF Reserved 0x40010400 – 0x400107FF TIMER1 0x40010000 – 0x400103FF TIMER0 0x4000E400 – 0x4000FFFF Reserved 0x4000CC00 – 0x4000DFFF Reserved 0x4000C400 – 0x4000C7FF USART1 0x4000C000 – 0x4000C3FF USART0 0x4000A400 – 0x4000BFFF Reserved 0x4000A000 – 0x4000A3FF I2C0 0x40008400 – 0x40009FFF Reserved 0x40007000 – 0x40007FFF Reserved 0x40006000 – 0x40006FFF GPIO 0x40004400 – 0x40005FFF Reserved 0x40004000 – 0x400043FF DAC0 0x40002400 – 0x40003FFF Reserved 0x40002000 – 0x400023FF ADC0 0x40001800 – 0x40001FFF Reserved 0x40001400 – 0x400017FF ACMP1 0x40001000 – 0x400013FF ACMP0 0x40000400 – 0x40000FFF Reserved 0x40000000 - 0x400003FF VCMP 5.2.3 Bus Matrix The Bus Matrix connects the memory segments to the bus masters: • Code: CPU instruction or data fetches from the code space • System: CPU read and write to the SRAM and peripherals • DMA: Access to SRAM, Flash and peripherals 5.2.3.1 Arbitration The Bus Matrix uses a round-robin arbitration algorithm which enables high throughput and low latency while starvation of simultaneous accesses to the same bus slave are eliminated. Round-robin does not assign a fixed priority to each bus master. The arbiter does not insert any bus wait-states. 5.2.3.2 Access Performance The Bus Matrix is a multi-layer energy optimized AMBA AHB compliant bus with an internal bandwidth equal to 4 times a single AHB-bus. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 19 www.silabs.com ...the world's most energy friendly microcontrollers The Bus Matrix accepts new transfers initiated by each master in every clock cycle without inserting any wait-states. The slaves, however, may insert wait-states depending on their internal throughput and the clock frequency. The Cortex-M3, the DMA Controller, and the peripherals run on clocks that can be prescaled separately. When accessing a peripheral which runs on a frequency equal to or faster than the HFCORECLK, the number of wait cycles per access, in addition to master arbitration, is given by: Memory Wait Cycles with Clock Equal or Faster than HFCORECLK Ncycles = 2 + Nslave cycles, (5.3) where Nslave cycles is the wait cycles introduced by the slave. When accessing a peripheral running on a clock slower than the HFCORECLK, wait-cycles are introduced to allow the transfer to complete on the peripheral clock. The number of wait cycles per access, in addition to master arbitration, is given by: Memory Wait Cycles with Clock Slower than CPU Ncycles = (2 + Nslave cycles) x fHFCORECLK/fHFPERCLK, (5.4) where Nslave cycles is the number of wait cycles introduced by the slave. For general register access, Nslave cycles = 1. More details on clocks and prescaling can be found in Chapter 11 (p. 99) . 5.3 Access to Low Energy Peripherals (Asynchronous Registers) 5.3.1 Introduction The Low Energy Peripherals are capable of running when the high frequency oscillator and core system is powered off, i.e. in energy mode EM2 and in some cases also EM3. This enables the peripherals to perform tasks while the system energy consumption is minimal. The Low Energy Peripherals are: • • • • • • • Liquid Crystal Display driver - LCD Low Energy Timer - LETIMER Low Energy UART - LEUART Pulse Counter - PCNT Real Time Counter - RTC Watchdog - WDOG Low Energy Sensor Interface - LESENSE All Low Energy Peripherals are memory mapped, with automatic data synchronization. Because the Low Energy Peripherals are running on clocks asynchronous to the core clock, there are some constraints on how register accesses can be done, as described in the following sections. 5.3.1.1 Writing Every Low Energy Peripheral has one or more registers with data that needs to be synchronized into the Low Energy clock domain to maintain data consistency and predictable operation. There are two 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 20 www.silabs.com ...the world's most energy friendly microcontrollers different synchronization mechanisms on the Tiny Gecko; immediate synchronization, and delayed synchronization. Immediate synchronization is available for the RTC, LETIMER and LESENSE, and results in an immediate update of the target registers. Delayed synchronization is used for the other Low Energy Peripherals, and for these peripherals, a write operation requires 3 positive edges on the clock of the Low Energy Peripheral being accessed. Registers requiring synchronization are marked "Asynchronous" in their description header. 5.3.1.1.1 Delayed synchronization After writing data to a register which value is to be synchronized into the Low Energy Peripheral using delayed synchronization, a corresponding busy flag in the _SYNCBUSY register (e.g. LEUART_SYNCBUSY) is set. This flag is set as long as synchronization is in progress and is cleared upon completion. Note Subsequent writes to the same register before the corresponding busy flag is cleared is not supported. Write before the busy flag is cleared may result in undefined behavior. In general, the SYNCBUSY register only needs to be observed if there is a risk of multiple write access to a register (which must be prevented). It is not required to wait until the relevant flag in the SYNCBUSY register is cleared after writing a register. E.g EM2 can be entered immediately after writing a register. See Figure 5.3 (p. 21) for a more detailed overview of the write operation. Figure 5.3. Write operation to Low Energy Peripherals Core Clock Dom ain Low Frequency Clock Dom ain Freeze Low Frequency Clock Low Frequency Clock Register 0 Synchronizer 0 Register 0 Sync Register 1 . . . Register n Synchronizer 1 . . . Synchronizer n Register 1 Sync . . . Register n Sync Core Clock Synchronization Done Write[0:n] Set 0 Syncbusy Register 0 Clear 0 Set 1 Syncbusy Register 1 . . . Syncbusy Register n Clear 1 Set n Clear n 5.3.1.1.2 Immediate synchronization Contrary to the peripherals with delayed synchronization, data written to peripherals with immediate synchronization, takes effect in the peripheral immediately. They are updated immediately on the peripheral write access. If a write is set up close to a peripheral clock edge, the write is delayed to after the clock edge. This will introduce wait-states on peripheral access. In the worst case, there can be three wait-state cycles of the HFCORECLK_LE and an additional wait-state equivalent of up to 315 ns. For peripherals with immediate synchronization, the SYNCBUSY registers are still present and serve two purposes: (1) commands written to a peripheral with immediate synchronization are not executed before the first peripheral clock after the write. During this period, the SYNCBUSY flag in the command register 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 21 www.silabs.com ...the world's most energy friendly microcontrollers is set, indicating that the command has not yet been executed; (2) to maintain backwards compatibility with the EFM32G series, SYNCBUSY registers are also present for other registers. These are however, always 0, indicating that register writes are always safe. Note If the application must be compatible with the EFM32G series, all Low Energy Peripherals should be accessed as if they only had delayed synchronization, i.e. using SYNCBUSY. 5.3.1.2 Reading When reading from Low Energy Peripherals, the data is synchronized regardless of the originating clock domain. Registers updated/maintained by the Low Energy Peripheral are read directly from the Low Energy clock domain. Registers residing in the core clock domain, are read from the core clock domain. See Figure 5.4 (p. 22) for a more detailed overview of the read operation. Note Writing a register and then immediately reading back the value of the register may give the impression that the write operation is complete. This is not necessarily the case. Please refer to the SYNCBUSY register for correct status of the write operation to the Low Energy Peripheral. Figure 5.4. Read operation from Low Energy Peripherals Core Clock Dom ain Low Frequency Clock Dom ain Freeze Low Frequency Clock Low Frequency Clock Register 0 Synchronizer 0 Register 0 Sync Register 1 . . . Register n Synchronizer 1 . . . Synchronizer n Register 1 Sync . . . Register n Sync Core Clock HW Status Register 0 Read Synchronizer HW Status Register 1 . . . HW Status Register m Low Energy Peripheral Main Function Read Data 5.3.2 FREEZE register For Low Energy Peripherals with delayed synchronization there is a _FREEZE register (e.g. RTC_FREEZE), containing a bit named REGFREEZE. If precise control of the synchronization process is required, this bit may be utilized. When REGFREEZE is set, the synchronization process is halted, allowing the software to write multiple Low Energy registers before starting the synchronization process, thus providing precise control of the module update process. The synchronization process is started by clearing the REGFREEZE bit. Note The FREEZE register is also present on peripherals with immediate synchronization, but has no effect. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 22 www.silabs.com ...the world's most energy friendly microcontrollers 5.4 Flash The Flash retains data in any state and typically stores the application code, special user data and security information. The Flash memory is typically programmed through the debug interface, but can also be erased and written to from software. • • • • • • Up to 32 kB of memory Page size of 512 bytes (minimum erase unit) Minimum 20 000 erase cycles More than 10 years data retention at 85°C Lock-bits for memory protection Data retention in any state 5.5 SRAM The primary task of the SRAM memory is to store application data. Additionally, it is possible to execute instructions from SRAM, and the DMA may used to transfer data between the SRAM, Flash and peripherals. • • • • Up to 4 kB memory Bit-band access support 4 kB blocks may be individually powered down when not in use Data retention of the entire memory in EM0 to EM3 5.6 Device Information (DI) Page The DI page contains calibration values, a unique identification number and other useful data. See the table below for a complete overview. Table 5.4. Device Information Page Contents DI Address Register Description 0x0FE08020 CMU_LFRCOCTRL Register reset value. 0x0FE08028 CMU_HFRCOCTRL Register reset value. 0x0FE08030 CMU_AUXHFRCOCTRL Register reset value. 0x0FE08040 ADC0_CAL Register reset value. 0x0FE08048 ADC0_BIASPROG Register reset value. 0x0FE08050 DAC0_CAL Register reset value. 0x0FE08058 DAC0_BIASPROG Register reset value. 0x0FE08060 ACMP0_CTRL Register reset value. 0x0FE08068 ACMP1_CTRL Register reset value. 0x0FE08078 CMU_LCDCTRL Register reset value. 0x0FE080A0 DAC0_OPACTRL Register reset value 0x0FE080A8 DAC0_OPAOFFSET Register reset value 0x0FE081B0 DI_CRC [15:0]: DI data CRC-16. 0x0FE081B2 CAL_TEMP_0 [7:0] Calibration temperature (°C). 0x0FE081B4 ADC0_CAL_1V25 [14:8]: Gain for 1V25 reference, [6:0]: Offset for 1V25 reference. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 23 www.silabs.com ...the world's most energy friendly microcontrollers DI Address Register Description 0x0FE081B6 ADC0_CAL_2V5 [14:8]: Gain for 2V5 reference, [6:0]: Offset for 2V5 reference. 0x0FE081B8 ADC0_CAL_VDD [14:8]: Gain for VDD reference, [6:0]: Offset for VDD reference. 0x0FE081BA ADC0_CAL_5VDIFF [14:8]: Gain for 5VDIFF reference, [6:0]: Offset for 5VDIFF reference. 0x0FE081BC ADC0_CAL_2XVDD [14:8]: Reserved (gain for this reference cannot be calibrated), [6:0]: Offset for 2XVDD reference. 0x0FE081BE ADC0_TEMP_0_READ_1V25 [15:4] Temperature reading at 1V25 reference, [3:0] Reserved. 0x0FE081C8 DAC0_CAL_1V25 [22:16]: Gain for 1V25 reference, [13:8]: Channel 1 offset for 1V25 reference, [5:0]: Channel 0 offset for 1V25 reference. 0x0FE081CC DAC0_CAL_2V5 [22:16]: Gain for 2V5 reference, [13:8]: Channel 1 offset for 2V5 reference, [5:0]: Channel 0 offset for 2V5 reference. 0x0FE081D0 DAC0_CAL_VDD [22:16]: Reserved (gain for this reference cannot be calibrated), [13:8]: Channel 1 offset for VDD reference, [5:0]: Channel 0 offset for VDD reference. 0x0FE081D4 AUXHFRCO_CALIB_BAND_1 [7:0]: Tuning for the 1.2 MHZ AUXHFRCO band. 0x0FE081D5 AUXHFRCO_CALIB_BAND_7 [7:0]: Tuning for the 6.6 MHZ AUXHFRCO band. 0x0FE081D6 AUXHFRCO_CALIB_BAND_11 [7:0]: Tuning for the 11 MHZ AUXHFRCO band. 0x0FE081D7 AUXHFRCO_CALIB_BAND_14 [7:0]: Tuning for the 14 MHZ AUXHFRCO band. 0x0FE081D8 AUXHFRCO_CALIB_BAND_21 [7:0]: Tuning for the 21 MHZ AUXHFRCO band. 0x0FE081D9 AUXHFRCO_CALIB_BAND_28 [7:0]: Tuning for the 28 MHZ AUXHFRCO band. 0x0FE081DC HFRCO_CALIB_BAND_1 [7:0]: Tuning for the 1.2 MHZ HFRCO band. 0x0FE081DD HFRCO_CALIB_BAND_7 [7:0]: Tuning for the 6.6 MHZ HFRCO band. 0x0FE081DE HFRCO_CALIB_BAND_11 [7:0]: Tuning for the 11 MHZ HFRCO band. 0x0FE081DF HFRCO_CALIB_BAND_14 [7:0]: Tuning for the 14 MHZ HFRCO band. 0x0FE081E0 HFRCO_CALIB_BAND_21 [7:0]: Tuning for the 21 MHZ HFRCO band. 0x0FE081E1 HFRCO_CALIB_BAND_28 [7:0]: Tuning for the 28 MHZ HFRCO band. 0x0FE081E7 MEM_INFO_PAGE_SIZE [7:0] Flash page size in bytes coded as 2 ^ ((MEM_INFO_PAGE_SIZE + 10) & 0xFF). Ie. the value 0xFF = 512 bytes. 0x0FE081F0 UNIQUE_0 [31:0] Unique number. 0x0FE081F4 UNIQUE_1 [63:32] Unique number. 0x0FE081F8 MEM_INFO_FLASH [15:0]: Flash size, kbyte count as unsigned integer (eg. 128). 0x0FE081FA MEM_INFO_RAM [15:0]: Ram size, kbyte count as unsigned integer (eg. 16). 0x0FE081FC PART_NUMBER [15:0]: EFM32 part number as unsigned integer (eg. 230). 0x0FE081FE PART_FAMILY [7:0]: EFM32 part family number (Gecko = 71, Giant Gecko = 72, Tiny Gecko = 73, Leopard Gecko=74, Wonder Gecko=75). 0x0FE081FF PROD_REV [7:0]: EFM32 Production ID. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 24 www.silabs.com ...the world's most energy friendly microcontrollers 6 DBG - Debug Interface Quick Facts What? 0 1 2 3 4 The DBG (Debug Interface) is used to program and debug EFM32TG devices. Why? The Debug Interface makes it easy to reprogram and update the system in the field, and allows debugging with minimal I/O pin usage. ARM Cortex- M3 How? DBG Debug Data The Cortex-M3 supports advanced debugging features. EFM32TG devices only use two port pins for debugging or programming. The internal and external state of the system can be examined with debug extensions supporting instruction or data access break- and watch points. 6.1 Introduction The EFM32TG devices include hardware debug support through a 2-pin serial-wire debug (SWD) interface. In addition, there is also a Serial Wire Viewer pin which can be used to output profiling information, data trace and software-generated messages. For more technical information about the debug interface the reader is referred to: • ARM Cortex-M3 Technical Reference Manual • ARM CoreSight Components Technical Reference Manual • ARM Debug Interface v5 Architecture Specification 6.2 Features • Flash Patch and Breakpoint (FPB) unit • Implement breakpoints and code patches • Data Watch point and Trace (DWT) unit • Implement watch points, trigger resources and system profiling • Instrumentation Trace Macrocell (ITM) • Application-driven trace source that supports printf style debugging 6.3 Functional Description There are three debug pins and four trace pins available on the device. Operation of these pins are described in the following section. 6.3.1 Debug Pins The following pins are the debug connections for the device: 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 25 www.silabs.com ...the world's most energy friendly microcontrollers • Serial Wire Clock input (SWCLK): This pin is enabled after reset and has a built-in pull down. • Serial Wire Data Input/Output (SWDIO): This pin is enabled after reset and has a built-in pull-up. • Serial Wire Viewer (SWV): This pin is disabled after reset. The debug pins can be enabled and disabled through GPIO_ROUTE, see Section 28.3.4.1 (p. 471) . Please remeberer that upon disabling, debug contact with the device is lost. Also note that, because the debug pins have pull-down and pull-up enabled by default, leaving them enabled might increase the current consumption with up to 200 µA if left connected to supply or ground. 6.3.2 Debug and EM2/EM3 Leaving the debugger connected when issuing a WFI or WFE to enter EM2 or EM3 will make the system enter a special EM2. This mode differs from regular EM2 and EM3 in that the high frequency clocks are still enabled, and certain core functionality is still powered in order to maintain debug-functionality. Because of this, the current consumption in this mode is closer to EM1 and it is therefore important to disconnect the debugger before doing current consumption measurements. 6.4 Debug Lock and Device Erase The debug access to the Cortex-M3 is locked by clearing the Debug Lock Word (DLW) and resetting the device, see Section 7.3.2 (p. 32) . When debug access is locked, the debug interface remains accessible but the connection to the CortexM3 core and the whole bus-system is blocked as shown in Figure 6.2 (p. 27) . This mechanism is controlled by the Authentication Access Port (AAP) as illustrated by Figure 6.1 (p. 26) . The AAP is only accessible from a debugger and not from the core. Figure 6.1. AAP - Authentication Access Port DEVICEERASE ERASEBUSY DLW[3:0] = = 0x F SerialWire debug interface SW- DP Authentication Access Port (AAP) Cortex AHB- AP The debugger can access the AAP-registers, and only these registers just after reset, for the time of the AAP-window outlined in Figure 6.2 (p. 27) . If the device is locked, access to the core and bus-system is blocked even after code execution starts, and the debugger can only access the AAP-registers. If the device is not locked, the AAP is no longer accessible after code execution starts, and the debugger can access the core and bus-system normally. The AAP window can be extended by issuing the bit pattern on SWDIO/SWCLK as shown in Figure 6.3 (p. 27) . This pattern should be applied just before reset is deasserted, and will give the debugger more time to access the AAP. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 26 www.silabs.com ...the world's most energy friendly microcontrollers Figure 6.2. Device Unlock Reset Program ex ecution Locked No access AAP Program ex ecution 150 us Unlocked No access AAP Cortex Program ex ecution 47 us Ex tended unlocked No access Ex tended AAP Cortex 255 x 47 us Figure 6.3. AAP Expansion SWDIO SWCLK AAP ex pand If the device is locked, it can be unlocked by writing a valid key to the AAP_CMDKEY register and then setting the DEVICEERASE bit of the AAP_CMD register via the debug interface. The commands are not executed before AAP_CMDKEY is invalidated, so this register should be cleared to to start the erase operation. This operation erases the main block of flash, all lock bits are reset and debug access through the AHB-AP is enabled. The operation takes 40 ms to complete. Note that the SRAM contents will also be deleted during a device erase, while the UD-page is not erased. Even if the device is not locked, the can device can be erased through the AAP, using the above procedure during the AAP window. This can be useful if the device has been programmed with code that, e.g., disables the debug interface pins on start-up, or does something else that prevents communication with a debugger. If the device is locked, the debugger may read the status from the AAP_STATUS register. When the ERASEBUSY bit is set low after DEVICEERASE of the AAP_CMD register is set, the debugger may set the SYSRESETREQ bit in the AAP_CMD register. After reset, the debugger may resume a normal debug session through the AHB-AP. If the device is not locked, the device erase starts when the AAP window closes, so it is not possible to poll the status. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 27 www.silabs.com ...the world's most energy friendly microcontrollers 6.5 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 AAP_CMD W1 Command Register 0x004 AAP_CMDKEY W1 Command Key Register 0x008 AAP_STATUS R Status Register 0x0FC AAP_IDR R AAP Identification Register 6.6 Register Description 6.6.1 AAP_CMD - Command Register SYSRESETREQ Name Access 0 0 W1 Access DEVICEERASE W1 0 Reset 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x000 Bit Position 31 Offset Bit Name Reset Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 1 SYSRESETREQ 0 W1 System Reset Request A system reset request is generated when set to 1. This register is write enabled from the AAP_CMDKEY register. 0 DEVICEERASE 0 W1 Erase the Flash Main Block, SRAM and Lock Bits When set, all data and program code in the main block is erased, the SRAM is cleared and then the Lock Bit (LB) page is erased. This also includes the Debug Lock Word (DLW), causing debug access to be enabled after the next reset. The information block User Data page (UD) is left unchanged, but the User data page Lock Word (ULW) is erased. This register is write enabled from the AAP_CMDKEY register. 6.6.2 AAP_CMDKEY - Command Key Register 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0x00000000 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x004 Bit Position 31 Offset W1 Reset WRITEKEY Access Name Bit Name Reset Access Description 31:0 WRITEKEY 0x00000000 W1 CMD Key Register 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 28 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description The key value must be written to this register to write enable the AAP_CMD register. After AAP_CMD is written, this register should be cleared to excecute the command. Value Mode Description 0xCFACC118 WRITEEN Enable write to AAP_CMD 6.6.3 AAP_STATUS - Status Register 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x008 Bit Position 31 Offset ERASEBUSY R Access Name Bit Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 0 ERASEBUSY 0 R Device Erase Command Status This bit is set when a device erase is executing. 6.6.4 AAP_IDR - AAP Identification Register 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0x16E60001 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x0FC 17 Bit Position Offset Reset R Access ID Name Bit Name Reset Access Description 31:0 ID 0x16E60001 R AAP Identification Register Access port identification register in compliance with the ARM ADI v5 specification (JEDEC Manufacturer ID) . 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 29 www.silabs.com ...the world's most energy friendly microcontrollers 7 MSC - Memory System Controller Quick Facts What? The user can perform Flash memory read, read configuration and write operations through the Memory System Controller (MSC) . Why? 0 1 2 3 The MSC allows the application code, user data and flash lock bits to be stored in nonvolatile Flash memory. Certain memory system functions, such as program memory wait-states and bus faults are also configured from the MSC peripheral register interface, giving the developer the ability to dynamically customize the memory system performance, security level, energy consumption and error handling capabilities to the requirements at hand. 4 01000101011011100110010101110010 01100111011110010010000001001101 01101001011000110111001001101111 00100000011100100111010101101100 01100101011100110010000001110100 01101000011001010010000001110111 01101111011100100110110001100100 00100000011011110110011000100000 01101100011011110111011100101101 01100101011011100110010101110010 01100111011110010010000001101101 01101001011000110111001001101111 01100011011011110110111001110100 01110010011011110110110001101100 01100101011100100010000001100100 01100101011100110110100101100111 01101110001000010100010101101110 How? The MSC integrates a low-energy Flash IP with a charge pump, enabling minimum energy consumption while eliminating the need for external programming voltage to erase the memory. An easy to use write and erase interface is supported by an internal, fixed-frequency oscillator and autonomous flash timing and control reduces software complexity while not using other timer resources. Application code may dynamically scale between high energy optimization and high code execution performance through advanced read modes. A highly efficient low energy instruction cache reduces the number of flash reads significantly, thus saving energy. Performance is also improved when waitstates are used, since many of the wait-states are eliminated. Built-in performance counters can be used to measure the efficiency of the instruction cache. 7.1 Introduction The Memory System Controller (MSC) is the program memory unit of the EFM32TG microcontroller. The flash memory is readable and writable from both the Cortex-M3 and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code is normally written to the main block. Additionally, the information block is available for special user data and flash lock bits. There is also a read-only page in the information block containing system and device calibration data. Read and write operations are supported in the energy modes EM0 and EM1. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 30 www.silabs.com ...the world's most energy friendly microcontrollers 7.2 Features • AHB read interface • Scalable access performance to optimize the Cortex-M3 code interface • Zero wait-state access up to 16 MHz and one wait-state for 16 MHz and above • Advanced energy optimization functionality • Conditional branch target prefetch suppression • Cortex-M3 disfolding of if-then (IT) blocks • Instruction Cache • DMA read support in EM0 and EM1 • Command and status interface • Flash write and erase • Accessible from Cortex-M3 in EM0 • DMA write support in EM0 and EM1 • Core clock independent Flash timing • Internal oscillator and internal timers for precise and autonomous Flash timing • General purpose timers are not occupied during Flash erase and write operations • Configurable interrupt erase abort • Improved interrupt predictability • Memory and bus fault control • Security features • Lockable debug access • Page lock bits • User data lock bits • End-of-write and end-of-erase interrupts 7.3 Functional Description The size of the main block is device dependent. The largest size available is 32 kB (64 pages). The information block has 512 bytes available for user data. The information block also contains chip configuration data located in a reserved area. The main block is mapped to address 0x00000000 and the information block is mapped to address 0x0FE00000. Table 7.1 (p. 32) outlines how the Flash is mapped in the memory space. All Flash memory is organized into 512 byte pages. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 31 www.silabs.com ...the world's most energy friendly microcontrollers Table 7.1. MSC Flash Memory Mapping Block 1 Main Page Base address Write/Erase by Software readable Purpose/Name Size 0 0x00000000 Software, debug Yes User code and data 8 KB - 32 kB Software, debug Yes . 63 0x00007E00 Software, debug Yes Reserved - 0x00008000 - - Reserved for flash expansion ~24 MB Information 0 0x0FE00000 Software, debug Yes User Data (UD) 512 B - 0x0FE00200 - - Reserved 1 0x0FE04000 Write: Software, debug Yes Lock Bits (LB) 512 B Erase: Debug only Reserved - 0x0FE04200 - - Reserved 2 0x0FE08000 - Yes Device Information (DI) - 0x0FE08200 - - Reserved - 0x0FE10000 - - Reserved for flash expansion 512 B Rest of code space 1 Block/page erased by a device erase 7.3.1 User Data (UD) Page Description This is the user data page in the information block. The page can be erased and written by software. The page is erased by the ERASEPAGE command of the MSC_WRITECMD register. Note that the page is not erased by a device erase operation. The device erase operation is described in Section 6.4 (p. 26) . 7.3.2 Lock Bits (LB) Page Description This page contains the following information: • Debug Lock Word (DLW) • User data page Lock Word (ULW) • Main block Page Lock Words (PLWs) The words in this page are organized as shown in Table 7.2 (p. 32) : Table 7.2. Lock Bits Page Structure 127 DLW 126 ULW … … 0 PLW[0] Word 127 is the debug lock word (DLW). The four LSBs of this word are the debug lock bits. If these bits are 0xF, then debug access is enabled. If the bits are not 0xF, then debug access to the core is locked. See Section 6.4 (p. 26) for details on how to unlock the debug access. Word 126 is the user page lock word (ULW). Bit 0 of this word is the User Data Page lock bit. Bit 1 in this word locks the Lock Bits Page. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 32 www.silabs.com ...the world's most energy friendly microcontrollers There are 32 page lock bits per page lock word (PLW). Bit 0 refers to the first page and bit 31 refers to the last page within a PLW. Thus, PLW[0] contains lock bits for page 0-31 in the main block. A page is locked when the bit is 0. A locked page cannot be erased or written. The lock bits can be reset by a device erase operation initiated from the Authentication Access Port (AAP) registers. The AAP is described in more detail in Section 6.4 (p. 26) . Note that the AAP is only accessible from the debug interface, and cannot be accessed from the Cortex-M3 core. 7.3.3 Device Information (DI) Page This read-only page holds the calibration data for the oscillator and other analog peripherals from the production test as well as a unique device ID. The page is further described in Section 5.6 (p. 23) . 7.3.4 Post-reset Behavior Calibration values are automatically written to registers by the MSC before application code startup. The values are also available to read from the DI page for later reference by software. Other information such as the device ID and production date is also stored in the DI page and is readable from software. 7.3.4.1 One Wait-state Access After reset, the HFCORECLK is normally 14 MHz from the HFRCO and the MODE field of the MSC_READCTRL register is set to WS1 (one wait-state). The reset value must be WS1 as an uncalibrated HFRCO may produce a frequency higher than 16 MHz. Software must not select a zero wait-state mode unless the clock is guaranteed to be 16 MHz or below, otherwise the resulting behavior is undefined. If a HFCORECLK frequency above 16 MHz is to be set by software, the MODE field of the MSC_READCTRL register must be set to WS1 or WS1SCBTP before the core clock is switched to the higher frequency clock source. When changing to a lower frequency, the MODE field of the MSC_READCTRL register can be set to WS0 or WS0SCBTP, but only after the frequency transition is completed. If the HFRCO is used, wait until the oscillator is stable on the new frequency. Otherwise, the behavior is unpredictable. 7.3.4.2 Zero Wait-state Access At 16 MHz and below, read operations from flash may be performed without any wait-states. Zero waitstate access greatly improves code execution performance at frequencies from 16 MHz and below. By default, the Cortex-M3 uses speculative prefetching and If-Then block folding to maximize code execution performance at the cost of additional flash accesses and energy consumption. 7.3.4.3 Suppressed Conditional Branch Target Prefetch (SCBTP) MSC offers a special instruction fetch mode which optimizes energy consumption by cancelling CortexM3 conditional branch target prefetches. Normally, the Cortex-M3 core prefetches both the next sequential instruction and the instruction at the branch target address when a conditional branch instruction reaches the pipeline decode stage. This prefetch scheme improves performance while one extra instruction is fetched from memory at each conditional branch, regardless of whether the branch is taken or not. To optimize for low energy, the MSC can be configured to cancel these speculative branch target prefetches. With this configuration, energy consumption is more optimal, as the branch target instruction fetch is delayed until the branch condition is evaluated. The performance penalty with this mode enabled is source code dependent, but is normally less than 1% for core frequencies from 16 MHz and below. To enable the mode at frequencies from 16 MHz and below write WS0SCBTP to the MODE field of the MSC_READCTRL register. For frequencies above 16 MHz, use the WS1SCBTP mode. An increased performance penalty per clock cycle must be expected compared to WS0SCBTP mode. The performance penalty in WS1SCBTP mode depends greatly on the density and organization of conditional branch instructions in the code. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 33 www.silabs.com ...the world's most energy friendly microcontrollers 7.3.4.4 Cortex-M3 If-Then Block Folding The Cortex-M3 offers a mechanism known as if-then block folding. This is a form of speculative prefetching where small if-then blocks are collapsed in the prefetch buffer if the condition evaluates to false. The instructions in the block then appear to execute in zero cycles. With this scheme, performance is optimized at the cost of higher energy consumption as the processor fetches more instructions from memory than it actually executes. To disable the mode, write a 1 to the DISFOLD bit in the NVIC Auxiliary Control Register; see the Cortex-M3 Technical Reference Manual for details. Normally, it is expected that this feature is most efficient at core frequencies above 16 MHz. Folding is enabled by default. 7.3.4.5 Instruction Cache The MSC includes an instruction cache. The instruction cache for the internal flash memory is enabled by default, but can be disabled by setting IFCDIS in MSC_READCTRL. When enabled, the instruction cache typically reduces the number of flash reads significantly, thus saving energy. In most cases a cache hit-rate of more than 70 % is achievable. When a 32-bit instruction fetch hits in the cache the data is returned to the processor in one clock cycle. Thus, performance is also improved when wait-states are used (i.e. running at frequencies above 16 MHz). The instruction cache is connected directly to the Cortex-M3 and functions as a memory access filter between the processor and the memory system, as illustrated in Figure 7.1 (p. 34) . The cache consists of an access filter, lookup logic, a 128x32 SRAM (512 bytes) and two performance counters. The access filter checks that the address for the access is of an instruction in the code space (instructions in RAM outside the code space are not cached). If the address matches, the cache lookup logic and SRAM is enabled. Otherwise, the cache is bypassed and the access is forwarded to the memory system. The cache is then updated when the memory access completes. The access filter also disables cache updates for interrupt context accesses if caching in interrupt context is disabled. The performance counters, when enabled, keep track of the number of cache hits and misses. The cache consists of 16 8-word cachelines organized as 4 sets with 4 ways. The cachelines are filled up continuously one word at a time as the individual words are requested by the processor. Thus, not all words of a cacheline might be valid at a given time. Figure 7.1. Instruction Cache Instruction Cache ICODE AHB- Lite Bus Cache Look- up Logic Access Filter ICODE AHB- Lite Bus 128x 32 SRAM Cortex IDCODE MUX Perform ance Counters IDCODE AHB- Lite Bus CODE Mem ory Space DCODE AHB- Lite Bus By default, the instruction cache is automatically invalidated when the contents of the flash is changed (i.e. written or erased). In many cases, however, the application only makes changes to data in the flash, not code. In this case, the automatic invalidate feature can be disabled by setting AIDIS in MSC_READCTRL. The cache can (independent of the AIDIS setting) be manually invalidated by writing 1 to INVCACHE in MSC_CMD. In general it is highly recommended to keep the cache enabled all the time. However, for some sections of code with very low cache hit-rate more energy-efficient execution can be achieved by disabling the cache temporarily. To measure the hit-rate of a code-section, the built-in performance counters can be used. Before the section, start the performance counters by writing 1 to STARTPC in MSC_CMD. This starts the performance counters, counting from 0. At the end of the section, stop the performance counters by writing 1 to STOPPC in MSC_CMD. The number of cache hits and cache misses for that section can then be read from MSC_CACHEHITS and MSC_CACHEMISSES respectively. The 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 34 www.silabs.com ...the world's most energy friendly microcontrollers total number of 32-bit instruction fetches will be MSC_CACHEHITS + MSC_CACHEMISSES. Thus, the cache hit-ratio can be calculated as MSC_CACHEHITS / (MSC_CACHEHITS + MSC_CACHEMISSES). When MSC_CACHEHITS overflows the CHOF interrupt flag is set. When MSC_CACHEMISSES overflows the CMOF interrupt flag is set. These flags must be cleared explicitly by software. The range of the performance counters can thus be extended by increasing a counter in the MSC interrupt routine. The performance counters only count when a cache lookup is performed. If the lookup fails, MSC_CACHEMISSES is increased. If the lookup is successful, MSC_CACHEHITS is increased. For example, a cache lookup is not performed if the cache is disabled or the code is executed from RAM outside the code space. When caching of vector fetches and instructions in interrupt routines is disabled (ICCDIS in MSC_READCTRL is set), the performance counters do not count when these types of fetches occur (i.e. while in interrupt context). By default, interrupt vector fetches and instructions in interrupt routines are also cached. Some applications may get better cache utilization by not caching instructions in interrupt context. This is done by setting ICCDIS in MSC_READCTRL. You should only set this bit based on the results from a cache hit ratio measurement. In general, it is recommended to keep the ICCDIS bit cleared. Note that lookups in the cache are still performed, regardless of the ICCDIS setting - but instructions are not cached when cache misses occur inside the interrupt routine. So, for example, if a cached function is called from the interrupt routine, the instructions for that function will be taken from the cache. The cache content is not retained in EM2, EM3 and EM4. The cache is therefore invalidated regardless of the setting of AIDIS in MSC_READCTRL when entering these energy modes. Applications that switch frequently between EM0 and EM2/3 and execute the very same non-looping code almost every time will most likely benefit from putting this code in RAM. The interrupt vectors can also be put in RAM to reduce current consumption even further. 7.3.5 Erase and Write Operations The AUXHFRCO is used for timing during flash write and erase operations. To achieve correct timing, the MSC_TIMEBASE register has to be configured according to the settings in CMU_AUXHFRCOCTRL. BASE in MSC_TIMEBASE defines how many AUXCLK cycles - 1 there is in 1 us or 5 us, depending on the configuration of PERIOD. To ensure that timing of flash write and erase operations is within the specification of the flash, the value written to BASE should give at least a 10% margin with respect to the period, i.e. for the 1 us PERIOD, the number of cycles should at least span 1.1 us, and for the 5 us period they should span at least 5.5 us. For the 1 MHz band, PERIOD in MSC_TIMEBASE should be set to 5US, while it should be set to 1US for all other AUXHFRCO bands. Both page erase and write operations require that the address is written into the MSC_ADDRB register. For erase operations, the address may be any within the page to be erased. Load the address by writing 1 to the LADDRIM bit in the MSC_WRITECMD register. The LADDRIM bit only has to be written once when loading the first address. After each word is written the internal address register ADDR will be incremented automatically by 4. The INVADDR bit of the MSC_STATUS register is set if the loaded address is outside the flash and the LOCKED bit of the MSC_STATUS register is set if the page addressed is locked. Any attempts to command erase of or write to the page are ignored if INVADDR or the LOCKED bits of the MSC_STATUS register are set. To abort an ongoing erase, set the ERASEABORT bit in the MSC_WRITECMD register. When a word is written to the MSC_WDATA register, the WDATAREADY bit of the MSC_STATUS register is cleared. When this status bit is set, software or DMA may write the next word. A single word write is commanded by setting the WRITEONCE bit of the MSC_WRITECMD register. The operation is complete when the BUSY bit of the MSC_STATUS register is cleared and control of the flash is handed back to the AHB interface, allowing application code to resume execution. For a DMA write the software must write the first word to the MSC_WDATA register and then set the WRITETRIG bit of the MSC_WRITECMD register. DMA triggers when the WDATAREADY bit of the MSC_STATUS register is set. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 35 www.silabs.com ...the world's most energy friendly microcontrollers It is possible to write words twice between each erase by keeping at 1 the bits that are not to be changed. Let us take as an example writing two 16 bit values, 0xAAAA and 0x5555. To safely write them in the same flash word this method can be used: • Write 0xFFFFAAAA (word in flash becomes 0xFFFFAAAA) • Write 0x5555FFFF (word in flash becomes 0x5555AAAA) Note During a write or erase, flash read accesses will be stalled, effectively halting code execution from flash. Code execution continues upon write/erase completion. Code residing in RAM may be executed during a write/erase operation. Note The MSC_WDATA and MSC_ADDRB registers are not retained when entering EM2 or lower energy modes. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 36 www.silabs.com ...the world's most energy friendly microcontrollers 7.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 MSC_CTRL RW Memory System Control Register 0x004 MSC_READCTRL RW Read Control Register 0x008 MSC_WRITECTRL RW Write Control Register 0x00C MSC_WRITECMD W1 Write Command Register 0x010 MSC_ADDRB RW Page Erase/Write Address Buffer 0x018 MSC_WDATA RW Write Data Register 0x01C MSC_STATUS R Status Register 0x02C MSC_IF R Interrupt Flag Register 0x030 MSC_IFS W1 Interrupt Flag Set Register 0x034 MSC_IFC W1 Interrupt Flag Clear Register 0x038 MSC_IEN RW Interrupt Enable Register 0x03C MSC_LOCK RW Configuration Lock Register 0x040 MSC_CMD W1 Command Register 0x044 MSC_CACHEHITS R Cache Hits Performance Counter 0x048 MSC_CACHEMISSES R Cache Misses Performance Counter 0x050 MSC_TIMEBASE RW Flash Write and Erase Timebase 7.5 Register Description 7.5.1 MSC_CTRL - Memory System Control Register 0 1 RW 1 Reset 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x000 Bit Position 31 Offset BUSFAULT Access Name Bit Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 0 BUSFAULT 1 RW Bus Fault Response Enable When this bit is set, the memory system generates bus error response. Value Mode Description 0 GENERATE A bus fault is generated on access to unmapped code and system space. 1 IGNORE Accesses to unmapped address space is ignored. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 37 www.silabs.com ...the world's most energy friendly microcontrollers 7.5.2 MSC_READCTRL - Read Control Register Access 0 1 2 RW 0x1 3 0 4 0 RW RW MODE Name IFCDIS ICCDIS Access AIDIS RW 0 Reset 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x004 Bit Position 31 Offset Bit Name Reset Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 5 ICCDIS 0 RW Interrupt Context Cache Disable Set this bit to automatically disable caching of vector fetches and instruction fetches in interrupt context. Cache lookup will still be performed in interrupt context. When set, the performance counters will not count when these types of fetches occur. 4 AIDIS 0 RW Automatic Invalidate Disable When this bit is set the cache is not automatically invalidated when a write or page erase is performed. 3 IFCDIS 0 RW Internal Flash Cache Disable Disable instruction cache for internal flash memory. 2:0 MODE 0x1 RW Read Mode If software wants to set a core clock frequency above 16 MHz, this register must be set to WS1 or WS1SCBTP before the core clock is switched to the higher frequency. When changing to a lower frequency, this register can be set to WS0 or WS0SCBTP after the frequency transition has been completed. After reset, the core clock is 14 MHz from the HFRCO but the MODE field of MSC_READCTRL register is set to WS1. This is because the HFRCO may produce a frequency above 16 MHz before it is calibrated. If the HFRCO is used as clock source, wait until the oscillator is stable on the new frequency to avoid unpredictable behavior. Value Mode Description 0 WS0 Zero wait-states inserted in fetch or read transfers. 1 WS1 One wait-state inserted for each fetch or read transfer. This mode is required for a core frequency above 16 MHz. 2 WS0SCBTP Zero wait-states inserted with the Suppressed Conditional Branch Target Prefetch (SCBTP) function enabled. SCBTP saves energy by delaying the Cortex' conditional branch target prefetches until the conditional branch instruction is in the execute stage. When the instruction reaches this stage, the evaluation of the branch condition is completed and the core does not perform a speculative prefetch of both the branch target address and the next sequential address. With the SCBTP function enabled, one instruction fetch is saved for each branch not taken, with a negligible performance penalty. 3 WS1SCBTP One wait-state access with SCBTP enabled. 7.5.3 MSC_WRITECTRL - Write Control Register Name 0 0 Bit Name Reset 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 1 IRQERASEABORT 0 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 Access RW RW IRQERASEABORT Access WREN 1 2 3 4 5 6 7 0 Reset 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x008 Bit Position 31 Offset Description RW Abort Page Erase on Interrupt 38 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description When this bit is set to 1, any Cortex interrupt aborts any current page erase operation. Executing that interrupt vector from Flash will halt the CPU. 0 WREN 0 RW Enable Write/Erase Controller When this bit is set, the MSC write and erase functionality is enabled. 7.5.4 MSC_WRITECMD - Write Command Register Access 0 0 W1 LADDRIM 1 2 0 0 W1 3 0 W1 4 0 W1 W1 WRITEEND ERASEPAGE Name WRITEONCE ERASEABORT Access WRITETRIG W1 0 Reset 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x00C Bit Position 31 Offset Bit Name Reset Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 5 ERASEABORT 0 W1 Abort erase sequence Writing to this bit will abort an ongoing erase sequence. 4 WRITETRIG 0 W1 Word Write Sequence Trigger Functions like MSC_CMD_WRITEONCE, but will set MSC_STATUS_WORDTIMEOUT if no new data is written to MSC_WDATA within the 30 µs timeout. 3 WRITEONCE 0 W1 Word Write-Once Trigger Start write of the first word written to MSC_WDATA, then add 4 to ADDR and write the next word if available within a 30 µs timeout. When ADDR is incremented past the page boundary, ADDR is set to the base of the page. 2 WRITEEND 0 W1 End Write Mode Write 1 to end write mode when using the WRITETRIG command. 1 ERASEPAGE 0 W1 Erase Page Erase any user defined page selected by the MSC_ADDRB register. The WREN bit in the MSC_WRITECTRL register must be set in order to use this command. 0 LADDRIM 0 W1 Load MSC_ADDRB into ADDR Load the internal write address register ADDR from the MSC_ADDRB register. The internal address register ADDR is incremented automatically by 4 after each word is written. When ADDR is incremented past the page boundary, ADDR is set to the base of the page. 7.5.5 MSC_ADDRB - Page Erase/Write Address Buffer 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RW Reset ADDRB Access Name 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 16 0x00000000 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x010 17 Bit Position Offset 39 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description 31:0 ADDRB 0x00000000 RW Page Erase or Write Address Buffer This register holds the page address for the erase or write operation. This register is loaded into the internal MSC_ADDR register when the LADDRIM field in MSC_WRITECMD is set. The MSC_ADDR register is not readable. This register is not retained when entering EM2 or lower energy modes. 7.5.6 MSC_WDATA - Write Data Register 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0x00000000 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x018 Bit Position 31 Offset RW Reset WDATA Access Name Bit Name Reset Access Description 31:0 WDATA 0x00000000 RW Write Data The data to be written to the address in MSC_ADDR. This register must be written when the WDATAREADY bit of MSC_STATUS is set, otherwise the data is ignored. This register is not retained when entering EM2 or lower energy modes. 7.5.7 MSC_STATUS - Status Register Access 0 R BUSY 0 1 2 R LOCKED 0 R INVADDR 0 3 R WDATAREADY 1 4 R 0 5 0 WORDTIMEOUT Name R PCRUNNING R Access ERASEABORTED 6 0 Reset 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x01C Bit Position 31 Offset Bit Name Reset Description 31:7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 6 PCRUNNING 0 R Performance Counters Running This bit is set while the performance counters are running. When one performance counter reaches the maximum value, this bit is cleared. 5 ERASEABORTED 0 R The Current Flash Erase Operation Aborted When set, the current erase operation was aborted by interrupt. 4 WORDTIMEOUT 0 R Flash Write Word Timeout When this bit is set, MSC_WDATA was not written within the timeout. The flash write operation timed out and access to the flash is returned to the AHB interface. This bit is cleared when the ERASEPAGE, WRITETRIG or WRITEONCE commands in MSC_WRITECMD are triggered. 3 WDATAREADY 1 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 R WDATA Write Ready 40 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description When this bit is set, the content of MSC_WDATA is read by MSC Flash Write Controller and the register may be updated with the next 32-bit word to be written to flash. This bit is cleared when writing to MSC_WDATA. 2 INVADDR 0 R Invalid Write Address or Erase Page Set when software attempts to load an invalid (unmapped) address into ADDR. 1 LOCKED 0 R Access Locked When set, the last erase or write is aborted due to erase/write access constraints. 0 BUSY 0 R Erase/Write Busy When set, an erase or write operation is in progress and new commands are ignored. 7.5.8 MSC_IF - Interrupt Flag Register Access 0 0 1 2 0 0 R R R ERASE Name CHOF CMOF R Access WRITE 0 Reset 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x02C 17 Bit Position Offset Bit Name Reset Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 3 CMOF 0 R Cache Misses Overflow Interrupt Flag R Cache Hits Overflow Interrupt Flag 0 R Write Done Interrupt Read Flag 0 R Erase Done Interrupt Read Flag Set when MSC_CACHEMISSES overflows. 2 CHOF 0 Set when MSC_CACHEHITS overflows. 1 WRITE Set when a write is done. 0 ERASE Set when erase is done. 7.5.9 MSC_IFS - Interrupt Flag Set Register Offset Access 0 W1 W1 ERASE 0 1 2 W1 CHOF WRITE 0 W1 Name CMOF Access 0 3 4 5 0 Reset 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x030 Bit Position Bit Name Reset Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 3 CMOF 0 W1 Cache Misses Overflow Interrupt Set W1 Cache Hits Overflow Interrupt Set Set the CMOF flag and generate interrupt. 2 CHOF 0 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 41 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description W1 Write Done Interrupt Set W1 Erase Done Interrupt Set Set the CHOF flag and generate interrupt. 1 WRITE 0 Set the write done bit and generate interrupt. 0 ERASE 0 Set the erase done bit and generate interrupt. 7.5.10 MSC_IFC - Interrupt Flag Clear Register Access 0 0 1 2 0 0 W1 W1 W1 ERASE Name CHOF CMOF Access WRITE W1 0 Reset 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x034 Bit Position 31 Offset Bit Name Reset Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 3 CMOF 0 W1 Cache Misses Overflow Interrupt Clear W1 Cache Hits Overflow Interrupt Clear 0 W1 Write Done Interrupt Clear 0 W1 Erase Done Interrupt Clear Clear the CMOF interrupt flag. 2 CHOF 0 Clear the CHOF interrupt flag. 1 WRITE Clear the write done bit. 0 ERASE Clear the erase done bit. 7.5.11 MSC_IEN - Interrupt Enable Register Access 0 RW RW ERASE 0 1 2 RW CHOF WRITE 0 RW Name CMOF Access 0 3 4 0 Reset 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x038 Bit Position 31 Offset Bit Name Reset Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 3 CMOF 0 RW Cache Misses Overflow Interrupt Enable Enable the cache misses performance counter overflow interrupt. 2 CHOF 0 RW Cache Hits Overflow Interrupt Enable Enable the cache hits performance counter overflow interrupt. 1 WRITE 0 RW Write Done Interrupt Enable Enable the write done interrupt. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 42 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description 0 ERASE 0 RW Erase Done Interrupt Enable Enable the erase done interrupt. 7.5.12 MSC_LOCK - Configuration Lock Register 0 1 2 3 4 5 6 7 8 0x0000 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x03C Bit Position 31 Offset RW Reset LOCKKEY Access Name Bit Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 LOCKKEY 0x0000 RW Configuration Lock Write any other value than the unlock code to lock access to MSC_CTRL, MSC_READCTRL, MSC_WRITECTRL and MSC_TIMEBASE. Write the unlock code to enable access. When reading the register, bit 0 is set when the lock is enabled. Mode Value Description UNLOCKED 0 MSC registers are unlocked. LOCKED 1 MSC registers are locked. LOCK 0 Lock MSC registers. UNLOCK 0x1B71 Unlock MSC registers. Read Operation Write Operation 7.5.13 MSC_CMD - Command Register Access 0 W1 INVCACHE 0 1 2 W1 0 W1 Name STOPPC Access STARTPC 0 Reset 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x040 Bit Position 31 Offset Bit Name Reset Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 2 STOPPC 0 W1 Stop Performance Counters Use this command bit to stop the performance counters. 1 STARTPC 0 W1 Start Performance Counters Use this command bit to start the performance counters. The performance counters always start counting from 0. 0 INVCACHE 0 W1 Invalidate Instruction Cache Use this register to invalidate the instruction cache. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 43 www.silabs.com ...the world's most energy friendly microcontrollers 7.5.14 MSC_CACHEHITS - Cache Hits Performance Counter 0 1 2 3 4 5 6 7 8 9 10 0x00000 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x044 Bit Position 31 Offset Reset CACHEHITS R Access Name Bit Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 19:0 CACHEHITS 0x00000 R Cache hits since last performance counter start command. Use to measure cache performance for a particular code section. 7.5.15 MSC_CACHEMISSES - Cache Misses Performance Counter 0 1 2 3 4 5 6 7 8 9 10 0x00000 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x048 Bit Position 31 Offset Reset CACHEMISSES R Access Name Bit Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 19:0 CACHEMISSES 0x00000 R Cache misses since last performance counter start command. Use to measure cache performance for a particular code section. 7.5.16 MSC_TIMEBASE - Flash Write and Erase Timebase PERIOD Name 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 44 0 1 2 3 0x10 4 6 7 8 9 10 11 12 13 14 15 5 RW Access BASE RW 0 Reset 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x050 17 Bit Position Offset www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 16 PERIOD 0 RW Sets the timebase period Decides whether TIMEBASE specifies the number of AUX cycles in 1 us or 5 us. 5 us should only be used with 1 MHz AUXHFRCO band. Value Mode Description 0 1US TIMEBASE period is 1 us. 1 5US TIMEBASE period is 5 us. 15:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 5:0 BASE 0x10 RW Timebase used by MSC to time flash writes and erases Should be set to the number of full AUX clock cycles in the period given by MSC_TIMEBASE_PERIOD. I.e. 1.1 us or 5.5. us with PERIOD cleared or set, respectively. The resetvalue of the timebase matches a 14 MHz AUXHFRCO, which is the default frequency of the AUXHFRCO. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 45 www.silabs.com ...the world's most energy friendly microcontrollers 8 DMA - DMA Controller Quick Facts What? 0 1 2 3 The DMA controller can move data without CPU intervention, effectively reducing the energy consumption for a data transfer. 4 Why? The DMA can perform data transfers more energy efficiently than the CPU and allows autonomous operation in low energy modes. The LEUART can for instance provide full UART communication in EM2, consuming only a few µA by using the DMA to move data between the LEUART and RAM. Flash DMA controller RAM How? The DMA controller has multiple highly configurable, prioritized DMA channels. Advanced transfer modes such as ping-pong and scatter-gather make it possible to tailor the controller to the specific needs of an application. Peripherals 8.1 Introduction The Direct Memory Access (DMA) controller performs memory operations independently of the CPU. This has the benefit of reducing the energy consumption and the workload of the CPU, and enables the system to stay in low energy modes for example when moving data from the USART to RAM. The DMA 1 controller uses the PL230 µDMA controller licensed from ARM . Each of the PL230s channels on the EFM32 can be connected to any of the EFM32 peripherals. 8.2 Features • The DMA controller is accessible as a memory mapped peripheral • Possible data transfers include • RAM/Flash to peripheral • RAM to Flash • Peripheral to RAM • RAM/Flash to RAM • The DMA controller has 8 independent channels • Each channel has one (primary) or two (primary and alternate) descriptors • The configuration for each channel includes • Transfer mode • Priority • Word-count • Word-size (8, 16, 32 bit) • The transfer modes include • Basic (using the primary or alternate DMA descriptor) 1 ARM PL230 homepage [http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0417a/index.html] 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 46 www.silabs.com ...the world's most energy friendly microcontrollers • • • • • • • • Ping-pong (switching between the primary or alternate DMA descriptors, for continuous data flow to/from peripherals) • Scatter-gather (using the primary descriptor to configure the alternate descriptor) Each channel has a programmable transfer length Channels 0 and 1 support looped transfers Channel 0 supports 2D copy A DMA channel can be triggered by any of several sources: • Communication modules (USART, LEUART) • Timers (TIMER) • Analog modules (DAC, ACMP, ADC) • Software Programmable mapping between channel number and peripherals - any DMA channel can be triggered by any of the available sources Interrupts upon transfer completion Data transfer to/from LEUART in EM2 is supported by the DMA, providing extremely low energy consumption while performing UART communications 8.3 Block Diagram An overview of the DMA and the modules it interacts with is shown in Figure 8.1 (p. 47) . Figure 8.1. DMA Block Diagram Interrupts Cortex AHB APB block AHB to APB bridge Configuration control AHB block APB m em ory m apped registers AHB- Lite m aster interface DMA data transfer Configuration Error Peripheral Channel select REQ/ ACK DMA Core Channel done Peripheral DMA control block The DMA Controller consists of four main parts: • An APB block allowing software to configure the DMA controller • An AHB block allowing the DMA to read and write the DMA descriptors and the source and destination data for the DMA transfers • A DMA control block controlling the operation of the DMA, including request/acknowledge signals for the connected peripherals 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 47 www.silabs.com ...the world's most energy friendly microcontrollers • A channel select block routing the right peripheral request to each DMA channel 8.4 Functional Description The DMA Controller is highly flexible. It is capable of transferring data between peripherals and memory without involvement from the processor core. This can be used to increase system performance by off-loading the processor from copying large amounts of data or avoiding frequent interrupts to service peripherals needing more data or having available data. It can also be used to reduce the system energy consumption by making the DMA work autonomously with the LEUART for data transfer in EM2 without having to wake up the processor core from sleep. The DMA Controller contains 8 independent channels. Each of these channels can be connected to any of the available peripheral trigger sources by writing to the configuration registers, see Section 8.4.1 (p. 48) . In addition, each channel can be triggered by software (for large memory transfers or for debugging purposes). What the DMA Controller should do (when one of its channels is triggered) is configured through channel descriptors residing in system memory. Before enabling a channel, the software must therefore take care to write this configuration to memory. When a channel is triggered, the DMA Controller will first read the channel descriptor from system memory, and then it will proceed to perform the memory transfers as specified by the descriptor. The descriptor contains the memory address to read from, the memory address to write to, the number of bytes to be transferred, etc. The channel descriptor is described in detail in Section 8.4.3 (p. 58) . In addition to the basic transfer mode, the DMA Controller also supports two advanced transfer modes; ping-pong and scatter-gather. Ping-pong transfers are ideally suited for streaming data for high-speed peripheral communication as the DMA will be ready to retrieve the next incoming data bytes immediately while the processor core is still processing the previous ones (and similarly for outgoing communication). Scatter-gather involves executing a series of tasks from memory and allows sophisticated schemes to be implemented by software. Using different priority levels for the channels and setting the number of bytes after which the DMA Controller re-arbitrates, it is possible to ensure that timing-critical transfers are serviced on time. 8.4.1 Channel Select Configuration The channel select block allows selecting which peripheral's request lines (dma_req, dma_sreq) to connect to each DMA channel. This configuration is done by software through the control registers DMA_CH0_CTRLDMA_CH7_CTRL, with SOURCESEL and SIGSEL components. SOURCESEL selects which peripheral to listen to and SIGSEL picks which output signals to use from the selected peripheral. All peripherals are connected to dma_req. When this signal is triggered, the DMA performs a number R of transfers as specified by the channel descriptor (2 ). The USARTs are additionally connected to the dma_sreq line. When only dma_sreq is asserted but not dma_req, then the DMA will perform exactly one transfer only (given that dma_sreq is enabled by software). 8.4.2 DMA control 8.4.2.1 DMA arbitration rate You can configure when the controller arbitrates during a DMA transfer. This enables you to reduce the latency to service a higher priority channel. The controller provides four bits that configure how many AHB bus transfers occur before it re-arbitrates. These bits are known as the R_power bits because the value you enter, R, is raised to the power of two 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 48 www.silabs.com ...the world's most energy friendly microcontrollers 4 and this determines the arbitration rate. For example, if R = 4 then the arbitration rate is 2 , that is, the controller arbitrates every 16 DMA transfers. Table 8.1 (p. 49) lists the arbitration rates. Table 8.1. AHB bus transfer arbitration interval R_power Arbitrate after x DMA transfers b0000 x=1 b0001 x=2 b0010 x=4 b0011 x=8 b0100 x = 16 b0101 x = 32 b0110 x = 64 b0111 x = 128 b1000 x = 256 b1001 x = 512 b1010 - b1111 x = 1024 Note You must take care not to assign a low-priority channel with a large R_power because this prevents the controller from servicing high-priority requests, until it re-arbitrates. R The number of dma transfers N that need to be done is specified by the user. When N > 2 and is not an R R R integer multiple of 2 then the controller always performs sequences of 2 transfers until N < 2 remain to be transferred. The controller performs the remaining N transfers at the end of the DMA cycle. You store the value of the R_power bits in the channel control data structure. See Section 8.4.3.3 (p. 61) for more information about the location of the R_power bits in the data structure. 8.4.2.2 Priority When the controller arbitrates, it determines the next channel to service by using the following information: • the channel number • the priority level, default or high, that is assigned to the channel. You can configure each channel to use either the default priority level or a high priority level by setting the DMA_CHPRIS register. Channel number zero has the highest priority and as the channel number increases, the priority of a channel decreases. Table 8.2 (p. 49) lists the DMA channel priority levels in descending order of priority. Table 8.2. DMA channel priority Channel Priority level Descending order of number setting channel priority 0 High Highest-priority DMA channel 1 High - 2 High - 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 49 www.silabs.com ...the world's most energy friendly microcontrollers Channel Priority level Descending order of number setting channel priority 3 High - 4 High - 5 High - 6 High - 7 High - 0 Default - 1 Default - 2 Default - 3 Default - 4 Default - 5 Default - 6 Default - 7 Default Lowest-priority DMA channel After a DMA transfer completes, the controller polls all the DMA channels that are available. Figure 8.2 (p. 50) shows the process it uses to determine which DMA transfer to perform next. Figure 8.2. Polling flowchart Start polling Is there a channel request ? No Yes Are any channel requests using a high prioritylevel ? No Yes Select channel that has the lowest channel num ber and is set to high priority- level Select channel that has the lowest channel num ber Start DMA transfer 8.4.2.3 DMA cycle types The cycle_ctrl bits control how the controller performs a DMA cycle. You can set the cycle_ctrl bits as Table 8.3 (p. 51) lists. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 50 www.silabs.com ...the world's most energy friendly microcontrollers Table 8.3. DMA cycle types cycle_ctrl Description b000 Channel control data structure is invalid b001 Basic DMA transfer b010 Auto-request b011 Ping-pong b100 Memory scatter-gather using the primary data structure b101 Memory scatter-gather using the alternate data structure b110 Peripheral scatter-gather using the primary data structure b111 Peripheral scatter-gather using the alternate data structure Note The cycle_ctrl bits are located in the channel_cfg memory location that Section 8.4.3.3 (p. 61) describes. R For all cycle types, the controller arbitrates after 2 DMA transfers. If you set a low-priority channel with R a large 2 value then it prevents all other channels from performing a DMA transfer, until the low-priority DMA transfer completes. Therefore, you must take care when setting the R_power, that you do not significantly increase the latency for high-priority channels. 8.4.2.3.1 Invalid After the controller completes a DMA cycle it sets the cycle type to invalid, to prevent it from repeating the same DMA cycle. 8.4.2.3.2 Basic In this mode, you configure the controller to use either the primary or the alternate data structure. After you enable the channel C and the controller receives a request for this channel, then the flow for this DMA cycle is as follows: R 1. The controller performs 2 transfers. If the number of transfers remaining becomes zero, then the flow continues at step 3 (p. 51) . 2. The controller arbitrates: • if a higher-priority channel is requesting service then the controller services that channel • if the peripheral or software signals a request to the controller then it continues at step 1 (p. 51) . 3. The controller sets dma_done[C] HIGH for one HFCORECLK cycle. This indicates to the host processor that the DMA cycle is complete. 8.4.2.3.3 Auto-request When the controller operates in this mode, it is only necessary for it to receive a single request to enable it to complete the entire DMA cycle. This enables a large data transfer to occur, without significantly increasing the latency for servicing higher priority requests, or requiring multiple requests from the processor or peripheral. You can configure the controller to use either the primary or the alternate data structure. After you enable the channel C and the controller receives a request for this channel, then the flow for this DMA cycle is as follows: R 1. The controller performs 2 transfers for channel C. If the number of transfers remaining is zero the flow continues at step 3 (p. 52) . 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 51 www.silabs.com ...the world's most energy friendly microcontrollers 2. The controller arbitrates. When channel C has the highest priority then the DMA cycle continues at step 1 (p. 51) . 3. The controller sets dma_done[C] HIGH for one HFCORECLK cycle. This indicates to the host processor that the DMA cycle is complete. 8.4.2.3.4 Ping-pong In ping-pong mode, the controller performs a DMA cycle using one of the data structures (primary or alternate) and it then performs a DMA cycle using the other data structure. The controller continues to switch from primary to alternate to primary… until it reads a data structure that is invalid, or until the host processor disables the channel. Figure 8.3 (p. 52) shows an example of a ping-pong DMA transaction. Figure 8.3. Ping-pong example Task A: Prim ary, cycle_ctrl = b011, 2 R = 4, N = 6 Request Task A Request dma_done[C] Task B: Alternate, cycle_ctrl = b011, 2 R = 4, N = 12 Request Task B Request Request dma_done[C] Task C: Prim ary, cycle_ctrl = b011, 2 R = 2, N = 2 Request Task C dma_done[C] Task D: Alternate, cycle_ctrl = b011, 2 R = 4, N = 5 Request Task D Request dma_done[C] Task E: Prim ary, cycle_ctrl = b011, 2 R = 4, N = 7 Request Task E Request dma_done[C] End: Alternate, cycle_ctrl = b000 Invalid In Figure 8.3 (p. 52) : Task A 1. The host processor configures the primary data structure for task A. 2. The host processor configures the alternate data structure for task B. This enables the controller to immediately switch to task B after task A completes, provided that a higher priority channel does not require servicing. 3. The controller receives a request and performs four DMA transfers. 4. The controller arbitrates. After the controller receives a request for this channel, the flow continues if the channel has the highest priority. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 52 www.silabs.com ...the world's most energy friendly microcontrollers 5. The controller performs the remaining two DMA transfers. 6. The controller sets dma_done[C] HIGH for one HFCORECLK cycle and enters the arbitration process. After task A completes, the host processor can configure the primary data structure for task C. This enables the controller to immediately switch to task C after task B completes, provided that a higher priority channel does not require servicing. After the controller receives a new request for the channel and it has the highest priority then task B commences: Task B 7. The controller performs four DMA transfers. 8. The controller arbitrates. After the controller receives a request for this channel, the flow continues if the channel has the highest priority. 9. The controller performs four DMA transfers. 10.The controller arbitrates. After the controller receives a request for this channel, the flow continues if the channel has the highest priority. 11.The controller performs the remaining four DMA transfers. 12.The controller sets dma_done[C] HIGH for one HFCORECLK cycle and enters the arbitration process. After task B completes, the host processor can configure the alternate data structure for task D. After the controller receives a new request for the channel and it has the highest priority then task C commences: Task C 13.The controller performs two DMA transfers. 14.The controller sets dma_done[C] HIGH for one HFCORECLK cycle and enters the arbitration process. After task C completes, the host processor can configure the primary data structure for task E. After the controller receives a new request for the channel and it has the highest priority then task D commences: Task D 15.The controller performs four DMA transfers. 16.The controller arbitrates. After the controller receives a request for this channel, the flow continues if the channel has the highest priority. 17.The controller performs the remaining DMA transfer. 18.The controller sets dma_done[C] HIGH for one HFCORECLK cycle and enters the arbitration process. After the controller receives a new request for the channel and it has the highest priority then task E commences: Task E 19.The controller performs four DMA transfers. 20.The controller arbitrates. After the controller receives a request for this channel, the flow continues if the channel has the highest priority. 21.The controller performs the remaining three DMA transfers. 22.The controller sets dma_done[C] HIGH for one HFCORECLK cycle and enters the arbitration process. If the controller receives a new request for the channel and it has the highest priority then it attempts to start the next task. However, because the host processor has not configured the alternate data structure, 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 53 www.silabs.com ...the world's most energy friendly microcontrollers and on completion of task D the controller set the cycle_ctrl bits to b000, then the ping-pong DMA transaction completes. Note You can also terminate the ping-pong DMA cycle in Figure 8.3 (p. 52) , if you configure task E to be a basic DMA cycle by setting the cycle_ctrl field to 3’b001. 8.4.2.3.5 Memory scatter-gather In memory scatter-gather mode the controller receives an initial request and then performs four DMA transfers using the primary data structure. After this transfer completes, it starts a DMA cycle using the alternate data structure. After this cycle completes, the controller performs another four DMA transfers using the primary data structure. The controller continues to switch from primary to alternate to primary… until either: • the host processor configures the alternate data structure for a basic cycle • it reads an invalid data structure. Note After the controller completes the N primary transfers it invalidates the primary data structure by setting the cycle_ctrl field to b000. The controller only asserts dma_done[C] when the scatter-gather transaction completes using an autorequest cycle. In scatter-gather mode, the controller uses the primary data structure to program the alternate data structure. Table 8.4 (p. 54) lists the fields of the channel_cfg memory location for the primary data structure, that you must program with constant values and those that can be user defined. Table 8.4. channel_cfg for a primary data structure, in memory scatter-gather mode Bit Field Value Description Constant-value fields: [31:30} dst_inc b10 Configures the controller to use word increments for the address [29:28] dst_size b10 Configures the controller to use word transfers [27:26] src_inc b10 Configures the controller to use word increments for the address [25:24] src_size b10 Configures the controller to use word transfers [17:14] R_power b0010 Configures the controller to perform four DMA transfers [3] next_useburst 0 For a memory scatter-gather DMA cycle, this bit must be set to zero [2:0] cycle_ctrl b100 Configures the controller to perform a memory scatter-gather DMA cycle User defined values: [23:21] dst_prot_ctrl - Configures the state of HPROT when the controller writes the destination data [20:18] src_prot_ctrl - Configures the state of HPROT when the controller reads the source data [13:4] n_minus_1 N 1 Configures the controller to perform N DMA transfers, where N is a multiple of four 1 Because the R_power field is set to four, you must set N to be a multiple of four. The value given by N/4 is the number of times that you must configure the alternate data structure. See Section 8.4.3.3 (p. 61) for more information. Figure 8.4 (p. 55) shows a memory scatter-gather example. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 54 www.silabs.com ...the world's most energy friendly microcontrollers Figure 8.4. Memory scatter-gather example Initialization: 1. Configure prim ary to enable the copy A, B, C, and D operations: cycle_ctrl = b100, 2 R = 4, N = 16. 2. Write the prim ary source data to m em ory, using the structure shown in the following table. src_data_end_ptr dst_data_end_ptr channel_cfg Data for Task A 0x 0A000000 0x 0AE00000 cycle_ctrl = b101, 2 R = 4, N = 3 0x XXXXXXXX Data for Task B 0x 0B000000 0x 0BE00000 cycle_ctrl = b101, 2 R = 2, N = 8 0x XXXXXXXX Data for Task C Data for Task D 0x 0C000000 0x 0D000000 0x 0CE00000 0x 0DE00000 Mem ory scatter- gather transaction: Primary Request Unused R 0x XXXXXXXX R 0x XXXXXXXX cycle_ctrl = b101, 2 = 8, N = 5 cycle_ctrl = b010, 2 = 4, N = 4 Alternate Copy from A in m em ory, to Alternate Auto request Copy from B in m em ory, to Alternate Task A N = 3, 2 R = 4 Auto request Auto request Auto request Auto request Auto request Auto request Copy from C in Task B N = 8, 2 R = 2 m em ory, to Alternate Auto request Task C N = 5, 2 R = 8 Copy from D in m em ory, to Alternate Auto request Auto request Task D N = 4, 2 R = 4 dma_done[C] In Figure 8.4 (p. 55) : Initialization 1. The host processor configures the primary data structure to operate in memory scatter-gather mode by setting cycle_ctrl to b100. Because a data structure for a R single channel consists of four words then you must set 2 to 4. In this example, there are four tasks and therefore N is set to 16. 2. The host processor writes the data structure for tasks A, B, C, and D to the memory locations that the primary src_data_end_ptr specifies. 3. The host processor enables the channel. The memory scatter-gather transaction commences when the controller receives a request on dma_req[ ] or a manual request from the host processor. The transaction continues as follows: Primary, copy A Task A Primary, copy B Task B Primary, copy C 1. After receiving a request, the controller performs four DMA transfers. These transfers write the alternate data structure for task A. 2. The controller generates an auto-request for the channel and then arbitrates. 3. The controller performs task A. After it completes the task, it generates an auto-request for the channel and then arbitrates. 4. The controller performs four DMA transfers. These transfers write the alternate data structure for task B. 5. The controller generates an auto-request for the channel and then arbitrates. 6. The controller performs task B. After it completes the task, it generates an auto-request for the channel and then arbitrates. 7. The controller performs four DMA transfers. These transfers write the alternate data structure for task C. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 55 www.silabs.com ...the world's most energy friendly microcontrollers 8. The controller generates an auto-request for the channel and then arbitrates. 9. The controller performs task C. After it completes the task, it generates an auto-request for the channel and then arbitrates. 10.The controller performs four DMA transfers. These transfers write the alternate data structure for task D. 11.The controller sets the cycle_ctrl bits of the primary data structure to b000, to indicate that this data structure is now invalid. 12.The controller generates an auto-request for the channel and then arbitrates. 13.The controller performs task D using an auto-request cycle. 14.The controller sets dma_done[C] HIGH for one HFCORECLK cycle and enters the arbitration process. Task C Primary, copy D Task D 8.4.2.3.6 Peripheral scatter-gather In peripheral scatter-gather mode the controller receives an initial request from a peripheral and then it performs four DMA transfers using the primary data structure. It then immediately starts a DMA cycle using the alternate data structure, without re-arbitrating. Note These are the only circumstances, where the controller does not enter the arbitration process after completing a transfer using the primary data structure. After this cycle completes, the controller re-arbitrates and if the controller receives a request from the peripheral that has the highest priority then it performs another four DMA transfers using the primary data structure. It then immediately starts a DMA cycle using the alternate data structure, without rearbitrating. The controller continues to switch from primary to alternate to primary… until either: • the host processor configures the alternate data structure for a basic cycle • it reads an invalid data structure. Note After the controller completes the N primary transfers it invalidates the primary data structure by setting the cycle_ctrl field to b000. The controller asserts dma_done[C] when the scatter-gather transaction completes using a basic cycle. In scatter-gather mode, the controller uses the primary data structure to program the alternate data structure. Table 8.5 (p. 56) lists the fields of the channel_cfg memory location for the primary data structure, that you must program with constant values and those that can be user defined. Table 8.5. channel_cfg for a primary data structure, in peripheral scatter-gather mode Bit Field Value Description Constant-value fields: [31:30] dst_inc b10 Configures the controller to use word increments for the address [29:28] dst_size b10 Configures the controller to use word transfers [27:26] src_inc b10 Configures the controller to use word increments for the address [25:24] src_size b10 Configures the controller to use word transfers [17:14] R_power b0010 Configures the controller to perform four DMA transfers [2:0] cycle_ctrl b110 Configures the controller to perform a peripheral scatter-gather DMA cycle - Configures the state of HPROT when the controller writes the destination data User defined values: [23:21] dst_prot_ctrl 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 56 www.silabs.com ...the world's most energy friendly microcontrollers Bit Field Value Description [20:18] src_prot_ctrl - Configures the state of HPROT when the controller reads the source data [13:4] n_minus_1 N [3] next_useburst - 1 Configures the controller to perform N DMA transfers, where N is a multiple of four When set to 1, the controller sets the chnl_useburst_set [C] bit to 1 after the alternate transfer completes 1 Because the R_power field is set to four, you must set N to be a multiple of four. The value given by N/4 is the number of times that you must configure the alternate data structure. See Section 8.4.3.3 (p. 61) for more information. Figure 8.5 (p. 57) shows a peripheral scatter-gather example. Figure 8.5. Peripheral scatter-gather example Initialization: 1. Configure prim ary to enable the copy A, B, C, and D operations: cycle_ctrl = b110, 2 R = 4, N = 16. 2. Write the prim ary source data in m em ory, using the structure shown in the following table. src_data_end_ptr dst_data_end_ptr channel_cfg Unused Data for Task A 0x 0A000000 0x 0AE00000 cycle_ctrl = b111, 2 R = 4, N = 3 0x XXXXXXXX Data for Task B 0x 0B000000 0x 0BE00000 cycle_ctrl = b111, 2 R = 2, N = 8 0x XXXXXXXX Data for Task C 0x 0C000000 0x 0CE00000 cycle_ctrl = b111, 2 R = 8, N = 5 0x XXXXXXXX Data for Task D 0x 0D000000 0x 0DE00000 Peripheral scatter- gather transaction: Primary Request R cycle_ctrl = b001, 2 = 4, N = 4 Alternate Copy from A in m em ory, to Alternate 0x XXXXXXXX For all prim ary to alternate transitions, the controller does not enter the arbitration process and im m ediately perform s the DMA transfer that the alternate channel control data structure specifies. Task A N = 3, 2 R = 4 Request Copy from B in m em ory, to Alternate Task B Request Request Request N = 8, 2 R = 2 Request Copy from C in m em ory, to Alternate Task C N = 5, 2 R = 8 Request Copy from D in m em ory, to Alternate Task D N = 4, 2 R = 4 dma_done[C] In Figure 8.5 (p. 57) : Initialization 1. The host processor configures the primary data structure to operate in peripheral scatter-gather mode by setting cycle_ctrl to b110. Because a data structure for a R single channel consists of four words then you must set 2 to 4. In this example, there are four tasks and therefore N is set to 16. 2. The host processor writes the data structure for tasks A, B, C, and D to the memory locations that the primary src_data_end_ptr specifies. 3. The host processor enables the channel. The peripheral scatter-gather transaction commences when the controller receives a request on dma_req[ ]. The transaction continues as follows: 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 57 www.silabs.com ...the world's most energy friendly microcontrollers Primary, copy A Task A 1. After receiving a request, the controller performs four DMA transfers. These transfers write the alternate data structure for task A. 2. The controller performs task A. 3. After the controller completes the task it enters the arbitration process. After the peripheral issues a new request and it has the highest priority then the process continues with: Primary, copy B Task B 4. The controller performs four DMA transfers. These transfers write the alternate data structure for task B. 5. The controller performs task B. To enable the controller to complete the task, the peripheral must issue a further three requests. 6. After the controller completes the task it enters the arbitration process. After the peripheral issues a new request and it has the highest priority then the process continues with: Primary, copy C Task C 7. The controller performs four DMA transfers. These transfers write the alternate data structure for task C. 8. The controller performs task C. 9. After the controller completes the task it enters the arbitration process. After the peripheral issues a new request and it has the highest priority then the process continues with: Primary, copy D Task D 10.The controller performs four DMA transfers. These transfers write the alternate data structure for task D. 11.The controller sets the cycle_ctrl bits of the primary data structure to b000, to indicate that this data structure is now invalid. 12.The controller performs task D using a basic cycle. 13.The controller sets dma_done[C] HIGH for one HFCORECLK cycle and enters the arbitration process. 8.4.2.4 Error signaling If the controller detects an ERROR response on the AHB-Lite master interface, it: • disables the channel that corresponds to the ERROR • sets dma_err HIGH. After the host processor detects that dma_err is HIGH, it must check which channel was active when the ERROR occurred. It can do this by: 1. Reading the DMA_CHENS register to create a list of disabled channels. When a channel asserts dma_done[ ] then the controller disables the channel. The program running on the host processor must always keep a record of which channels have recently asserted their dma_done[ ] outputs. 2. It must compare the disabled channels list from step 1 (p. 58) , with the record of the channels that have recently set their dma_done[ ] outputs. The channel with no record of dma_done[C] being set is the channel that the ERROR occurred on. 8.4.3 Channel control data structure You must provide an area of system memory to contain the channel control data structure. This system memory must: 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 58 www.silabs.com ...the world's most energy friendly microcontrollers • provide a contiguous area of system memory that the controller and host processor can access • have a base address that is an integer multiple of the total size of the channel control data structure. Figure 8.6 (p. 59) shows the memory that the controller requires for the channel control data structure, when all 8 channels and the optional alternate data structure are in use. Figure 8.6. Memory map for 8 channels, including the alternate data structure Alternate data structure Alternate_Ch_7 Alternate_Ch_6 Alternate_Ch_5 Alternate_Ch_4 Alternate_Ch_3 Alternate_Ch_2 Alternate_Ch_1 Alternate_Ch_0 0x 100 0x 0F0 0x 0E0 0x 0D0 0x 0C0 0x 0B0 0x 0A0 0x 090 0x 080 Prim ary data structure 0x 080 0x 070 0x 060 0x 050 0x 040 0x 030 0x 020 0x 010 0x 000 Prim ary_Ch_7 Prim ary_Ch_6 Prim ary_Ch_5 Prim ary_Ch_4 Prim ary_Ch_3 Prim ary_Ch_2 Prim ary_Ch_1 Prim ary_Ch_0 Unused Control Destination End Pointer Source End Pointer 0x 00C 0x 008 0x 004 0x 000 This structure in Figure 8.6 (p. 59) uses 256 bytes of system memory. The controller uses the lower 8 address bits to enable it to access all of the elements in the structure and therefore the base address must be at 0xXXXXXX00. You can configure the base address for the primary data structure by writing the appropriate value in the DMA_CTRLBASE register. You do not need to set aside the full 256 bytes if all dma channels are not used or if all alternate descriptors are not used. If, for example, only 4 channels are used and they only need the primary descriptors, then only 64 bytes need to be set aside. Table 8.6 (p. 59) lists the address bits that the controller uses when it accesses the elements of the channel control data structure. Table 8.6. Address bit settings for the channel control data structure Address bits [7] [6] [5] [4] [3:0] A C[2] C[1] C[0] 0x0, 0x4, or 0x8 Where: A Selects one of the channel control data structures: A=0 Selects the primary data structure. A=1 Selects the alternate data structure. Selects the DMA channel. C[2:0] Address[3:0] Selects one of the control elements: 0x0 Selects the source data end pointer. 0x4 Selects the destination data end pointer. 0x8 Selects the control data configuration. 0xC The controller does not access this address location. If required, you can enable the host processor to use this memory location as system memory. Note It is not necessary for you to calculate the base address of the alternate data structure because the DMA_ALTCTRLBASE register provides this information. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 59 www.silabs.com ...the world's most energy friendly microcontrollers Figure 8.7 (p. 60) shows a detailed memory map of the descriptor structure. Figure 8.7. Detailed memory map for the 8 channels, including the alternate data structure Unused Alternate for channel 7 Control Destination End Pointer Source End Pointer Unused Alternate for channel 1 Control Destination End Pointer Source End Pointer Unused Alternate for channel 0 Control Destination End Pointer Source End Pointer Unused Prim ary for channel 7 Control Destination End Pointer Source End Pointer Unused Prim ary for channel 1 Control Destination End Pointer Source End Pointer Unused Prim ary for channel 0 Control Destination End Pointer Source End Pointer 0x 0FC 0x 0F8 0x 0F4 0x 0F0 0x 09C 0x 098 0x 094 0x 090 0x 08C 0x 088 0x 084 0x 080 0x 07C 0x 078 0x 074 0x 070 0x 01C 0x 018 0x 014 0x 010 0x 00C 0x 008 0x 004 0x 000 Alternate data structure Prim ary data structure The controller uses the system memory to enable it to access two pointers and the control information that it requires for each channel. The following subsections will describe these 32-bit memory locations and how the controller calculates the DMA transfer address. 8.4.3.1 Source data end pointer The src_data_end_ptr memory location contains a pointer to the end address of the source data. Figure 8.7 (p. 60) lists the bit assignments for this memory location. Table 8.7. src_data_end_ptr bit assignments Bit Name Description [31:0] src_data_end_ptr Pointer to the end address of the source data Before the controller can perform a DMA transfer, you must program this memory location with the end R address of the source data. The controller reads this memory location when it starts a 2 DMA transfer. Note The controller does not write to this memory location. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 60 www.silabs.com ...the world's most energy friendly microcontrollers 8.4.3.2 Destination data end pointer The dst_data_end_ptr memory location contains a pointer to the end address of the destination data. Table 8.8 (p. 61) lists the bit assignments for this memory location. Table 8.8. dst_data_end_ptr bit assignments Bit Name Description [31:0] dst_data_end_ptr Pointer to the end address of the destination data Before the controller can perform a DMA transfer, you must program this memory location with the end R address of the destination data. The controller reads this memory location when it starts a 2 DMA transfer. Note The controller does not write to this memory location. 8.4.3.3 Control data configuration For each DMA transfer, the channel_cfg memory location provides the control information for the controller. Figure 8.8 (p. 61) shows the bit assignments for this memory location. Figure 8.8. channel_cfg bit assignments 31 30 29 28 27 26 25 24 23 21 20 18 17 R_power dst_inc src_inc dst_size src_size 4 3 2 14 13 0 n_m inus_1 src_prot_ctrl dst_prot_ctrl cycle_ctrl nex t_useburst Table 8.9 (p. 61) lists the bit assignments for this memory location. Table 8.9. channel_cfg bit assignments Bit Name Description [31:30] dst_inc Destination address increment. The address increment depends on the source data width as follows: Source data width = byte b00 = byte. b01 = halfword. b10 = word. b11 = no increment. Address remains set to the value that the dst_data_end_ptr memory location contains. Source data width = halfword b00 = reserved. b01 = halfword. b10 = word. b11 = no increment. Address remains set to the value that the dst_data_end_ptr memory location contains. Source data width = word b00 = reserved. b01 = reserved. b10 = word. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 61 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Description b11 = no increment. Address remains set to the value that the dst_data_end_ptr memory location contains. [29:28] dst_size Destination data size. Note You must set dst_size to contain the same value that src_size contains. [27:26] src_inc Set the bits to control the source address increment. The address increment depends on the source data width as follows: Source data width = byte b00 = byte. b01 = halfword. b10 = word. Source data width = halfword b11 = no increment. Address remains set to the value that the src_data_end_ptr memory location contains. b00 = reserved. b01 = halfword. b10 = word. Source data width = word b11 = no increment. Address remains set to the value that the src_data_end_ptr memory location contains. b00 = reserved. b01 = reserved. b10 = word. b11 = no increment. Address remains set to the value that the src_data_end_ptr memory location contains. [25:24] src_size Set the bits to match the size of the source data: b00 = byte b01 = halfword b10 = word b11 = reserved. [23:21] dst_prot_ctrl Set the bits to control the state of HPROT when the controller writes the destination data. Bit [23] Bit [22] Bit [21] This bit has no effect on the DMA. This bit has no effect on the DMA. Controls the state of HPROT as follows: 0 = HPROT is LOW and the access is non-privileged. 1 = HPROT is HIGH and the access is privileged. [20:18] src_prot_ctrl Set the bits to control the state of HPROT when the controller reads the source data. Bit [20] Bit [19] Bit [18] This bit has no effect on the DMA. This bit has no effect on the DMA. Controls the state of HPROT as follows: 0 = HPROT is LOW and the access is non-privileged. 1 = HPROT is HIGH and the access is privileged. [17:14] R_power Set these bits to control how many DMA transfers can occur before the controller re-arbitrates. The possible arbitration rate settings are: b0000 b0001 b0010 b0011 b0100 b0101 b0110 b0111 Arbitrates after each DMA transfer. Arbitrates after 2 DMA transfers. Arbitrates after 4 DMA transfers. Arbitrates after 8 DMA transfers. Arbitrates after 16 DMA transfers. Arbitrates after 32 DMA transfers. Arbitrates after 64 DMA transfers. Arbitrates after 128 DMA transfers. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 62 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Description b1000 b1001 b1010 - b1111 [13:4] n_minus_1 Arbitrates after 256 DMA transfers. Arbitrates after 512 DMA transfers. Arbitrates after 1024 DMA transfers. This means that no arbitration occurs during the DMA transfer because the maximum transfer size is 1024. Prior to the DMA cycle commencing, these bits represent the total number of DMA transfers that the DMA cycle contains. You must set these bits according to the size of DMA cycle that you require. The 10-bit value indicates the number of DMA transfers, minus one. The possible values are: b000000000 = 1 DMA transfer b000000001 = 2 DMA transfers b000000010 = 3 DMA transfers b000000011 = 4 DMA transfers b000000100 = 5 DMA transfers . . . b111111111 = 1024 DMA transfers. The controller updates this field immediately prior to it entering the arbitration process. This enables the controller to store the number of outstanding DMA transfers that are necessary to complete the DMA cycle. [3] next_useburst Controls if the chnl_useburst_set [C] bit is set to a 1, when the controller is performing a peripheral scatter-gather and is completing a DMA cycle that uses the alternate data structure. Note Immediately prior to completion of the DMA cycle that the alternate data structure specifies, the controller sets the chnl_useburst_set [C] bit to 0 if the number of R remaining transfers is less than 2 . The setting of the next_useburst bit controls if the controller performs an additional modification of the chnl_useburst_set [C] bit. In peripheral scatter-gather DMA cycle then after the DMA cycle that uses the alternate data structure completes , either: 0 = the controller does not change the value of the chnl_useburst_set [C] bit. If the chnl_useburst_set [C] bit is 0 then for all the remaining DMA cycles in the peripheral scattergather transaction, the controller responds to requests on dma_req[ ] and dma_sreq[ ], when it performs a DMA cycle that uses an alternate data structure. 1 = the controller sets the chnl_useburst_set [C] bit to a 1. Therefore, for the remaining DMA cycles in the peripheral scatter-gather transaction, the controller only responds to requests on dma_req[ ], when it performs a DMA cycle that uses an alternate data structure. [2:0] cycle_ctrl The operating mode of the DMA cycle. The modes are: b000 b001 b100 Stop. Indicates that the data structure is invalid. Basic. The controller must receive a new request, prior to it entering the arbitration process, to enable the DMA cycle to complete. Auto-request. The controller automatically inserts a request for the appropriate channel during the arbitration process. This means that the initial request is sufficient to enable the DMA cycle to complete. Ping-pong. The controller performs a DMA cycle using one of the data structures. After the DMA cycle completes, it performs a DMA cycle using the other data structure. After the DMA cycle completes and provided that the host processor has updated the original data structure, it performs a DMA cycle using the original data structure. The controller continues to perform DMA cycles until it either reads an invalid data structure or the host processor changes the cycle_ctrl bits to b001 or b010. See Section 8.4.2.3.4 (p. 52) . Memory scatter/gather. See Section 8.4.2.3.5 (p. 54) . b101 When the controller operates in memory scatter-gather mode, you must only use this value in the primary data structure. Memory scatter/gather. See Section 8.4.2.3.5 (p. 54) . b110 When the controller operates in memory scatter-gather mode, you must only use this value in the alternate data structure. Peripheral scatter/gather. See Section 8.4.2.3.6 (p. 56) . b010 b011 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 63 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Description b111 When the controller operates in peripheral scatter-gather mode, you must only use this value in the primary data structure. Peripheral scatter/gather. See Section 8.4.2.3.6 (p. 56) . When the controller operates in peripheral scatter-gather mode, you must only use this value in the alternate data structure. R At the start of a DMA cycle, or 2 DMA transfer, the controller fetches the channel_cfg from system R memory. After it performs 2 , or N, transfers it stores the updated channel_cfg in system memory. The controller does not support a dst_size value that is different to the src_size value. If it detects a mismatch in these values, it uses the src_size value for source and destination and when it next updates the n_minus_1 field, it also sets the dst_size field to the same as the src_size field. After the controller completes the N transfers it sets the cycle_ctrl field to b000, to indicate that the channel_cfg data is invalid. This prevents it from repeating the same DMA transfer. 8.4.3.4 Address calculation To calculate the source address of a DMA transfer, the controller performs a left shift operation on the n_minus_1 value by a shift amount that src_inc specifies, and then subtracts the resulting value from the source data end pointer. Similarly, to calculate the destination address of a DMA transfer, it performs a left shift operation on the n_minus_1 value by a shift amount that dst_inc specifies, and then subtracts the resulting value from the destination end pointer. Depending on the value of src_inc and dst_inc, the source address and destination address can be calculated using the equations: src_inc = b00 and dst_inc = b00 • • • • • • • • src_inc = b01 and dst_inc = b01 src_inc = b10 and dst_inc = b10 src_inc = b11 and dst_inc = b11 source address = src_data_end_ptr - n_minus_1 destination address = dst_data_end_ptr - n_minus_1. source address = src_data_end_ptr - (n_minus_1 0) REP0 = REP0 - 1 If (REP1 > 0) REP1 = REP1 - 1 STOP = 1 REP0 = 0 TOP* If (COMP0TOP) TOP* = COMP0 Else TOP* = 0x FFFF 19.3.3.3 Clock Source The LETIMER clock source and its prescaler value are defined in the Clock Management Unit (CMU). The LFACLKLETIMERn has a frequency given by Equation 19.1 (p. 300) . LETIMER Clock Frequency LETIMERn fLFACKL_LETIMERn = 32.768/2 (19.1) where the exponent LETIMERn is a 4 bit value in the CMU_LFAPRESC0 register. To use this module, the LE interface clock must be enabled in CMU_HFCORECLKEN0, in addition to the module clock. 19.3.3.4 RTC Trigger The LETIMER can be configured to start on compare match events from the Real Time Counter (RTC). If RTCC0TEN in LETIMERn_CTRL is set, the LETIMER will start on a compare match on RTC compare channel 0. In the same way, RTCC1TEN in LETIMERn_CTRL enables the LETIMER to start on a compare match with RTC compare channel 1. Note The LETIMER can only use compare match events from the RTC if the LETIMER runs at a higher than or equal frequency than the RTC. Also, if the LETIMER runs at twice the frequency of the RTC, a compare match event in the RTC will trigger the LETIMER twice. Four times the frequency gives four consecutive triggers, etc. The LETIMER will only 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 300 www.silabs.com ...the world's most energy friendly microcontrollers continue running if triggered while it is running, so the multiple-triggering will only have an effect if you try to disable the RTC when it is being triggered. 19.3.3.5 Debug If DEBUGRUN in LETIMERn_CTRL is cleared, the LETIMER automatically stops counting when the CPU is halted during a debug session, and resumes operation when the CPU continues. Because of synchronization, the LETIMER is halted two clock cycles after the CPU is halted, and continues running two clock cycles after the CPU continues. RUNNING in LETIMERn_STATUS is not cleared when the LETIMER stops because of a debug-session. Set DEBUGRUN in LETIMERn_CTRL to allow the LETIMER to continue counting even when the CPU is halted in debug mode. 19.3.4 Underflow Output Action For each of the repeat registers, an underflow output action can be set. The configured output action is performed every time the counter underflows while the respective repeat register is nonzero. In PWM mode, the output is similarly only changed on COMP1 match if the repeat register is nonzero. As an example, the timer will perform 7 output actions if LETIMERn_REP0 is set to 7 when starting the timer in one-shot mode and leaving it untouched for a while. The output actions can be set by configuring UFOA0 and UFOA1 in LETIMERn_CTRL. UFOA0 defines the action on output 0, and is connected to LETIMERn_REP0, while UFOA1 defines the action on output 1 and is connected to LETIMERn_REP1. The possible actions are defined in Table 19.2 (p. 301) . Table 19.2. LETIMER Underflow Output Actions UF0A0/UF0A1 Mode Description 00 Idle The output is held at its idle value 01 Toggle The output is toggled on LETIMERn_CNT underflow if LEIMERn_REPx is nonzero 10 Pulse The output is held active for one clock cycle on LETIMERn_CNT underflow if LETIMERn_REPx is nonzero. It then returns to its idle value 11 PWM The output is set idle on LETIMERn_CNT underflow and active on compare match with LETIMERn_COMP1 if LETIMERn_REPx is nonzero. Note For the Pulse and PWM modes, the outputs will return to their idle states regardless of the state of the corresponding LETIMERn_REPx registers. They will only be set active if the LETIMERn_REPx registers are nonzero however. The polarity of the outputs can be set individually by configuring OPOL0 and OPOL1 in LETIMERn_CTRL. When these are cleared, their respective outputs have a low idle value and a high active value. When they are set, the idle value is high, and the active value is low. When using the toggle action, the outputs can be driven to their idle values by setting their respective CTO0/CTO1 command bits in LETIMERn_CTRL. This can be used to put the output in a well-defined state before beginning to generate toggle output, which may be important in some applications. The command bit can also be used while the timer is running. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 301 www.silabs.com ...the world's most energy friendly microcontrollers Some simple waveforms generated with the different output modes are shown in Figure 19.6 (p. 302) . For the example, REPMODE in LETIMERn_CTRL has been cleared, COMP0TOP also in LETIMERn_CTRL has been set and LETIMERn_COMP0 has been written to 3. As seen in the figure, LETIMERn_COMP0 now decides the length of the signal periods. For the toggle mode, the period of the output signal is 2(LETIMERn_COMP0 + 1), and for the pulse modes, the periods of the output signals are LETIMERn_COMP0+1. Note that the pulse outputs are delayed by one period relative to the toggle output. The pulses come at the end of their periods. Figure 19.6. LETIMER Simple Waveforms Output Initial configuration COMP0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 CNT 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 Int. flags set UFIF UFIF UFIF UFIF UFIF UFIF LFACLKLETIMERn LETn_O0 UFOA0 = 00 LETn_O0 UFOA0 = 01 LETn_O0 UFOA0 = 10 For the example in Figure 19.7 (p. 302) , the One-shot repeat mode has been selected, and LETIMERn_REP0 has been written to 3. The resulting behavior is pretty similar to that shown in Figure 6, but in this case, the timer stops after counting to zero LETIMERn_REP0 times. By using LETIMERn_REP0 the user has full control of the number of pulses/toggles generated on the output. Figure 19.7. LETIMER Repeated Counting Initial configuration Stop COMP0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 CNT 0 3 2 1 0 3 2 1 0 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 3 3 3 3 3 2 2 2 2 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 REP0 Int. flags set UFIF UFIF UFIF REP0IF LFACLKLETIMERn LETn_O0 UFOA0 = 00 LETn_O0 UFOA0 = 01 LETn_O0 UFOA0 = 10 Using the Double repeat mode, output can be generated on both the LETIMER outputs. Figure 19.8 (p. 303) shows an example of this. UFOA0 and UFOA1 in LETIMERn_CTRL are configured for pulse output and the outputs are configured for low idle polarity. As seen in the figure, the number written to the repeat registers determine the number of pulses generated on each of the outputs. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 302 www.silabs.com ...the world's most energy friendly microcontrollers Figure 19.8. LETIMER Dual Output UFOA0 = 10 UFOA1 = 10 REP0 = 2 REP1 = 7 START REP0 = 3 START REP0 = 2 REP1 = 3 START LETn_O0 LETn_O1 19.3.5 PRS Output The LETIMER outputs can be routed out onto the PRS system. LETn_O0 can be routed to PRS channel 0, and LETn_1O can be routed to PRS channel 1. Enabling the RRS connection can be done by setting SOURCESEL to LETIMERx and SIGSEL to LETIMERxCHn in PRS_CHx_CTRL. The PRS register description can be found in Section 13.5 (p. 140) 19.3.6 Examples This section presents a couple of usage examples for the LETIMER. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 303 www.silabs.com ...the world's most energy friendly microcontrollers 19.3.6.1 Triggered Output Generation Example 19.1. LETIMER Triggered Output Generation If both LETIMERn_CNT and LETIMERn_REP0 are 0 in buffered mode, and COMP0TOP and BUFTOP in LETIMERn_CTRL are set, the values of LETIMERn_COMP1 and LETIMERn_REP1 are loaded into LETIMERn_CNT and LETIMERn_REP0 respectively when the timer is started. If no additional writes to LETIMERn_REP1 are done before the timer stops, LETIMERn_REP1 determines the number of pulses/ toggles generated on the output, and LETIMERn_COMP1 determines the period lengths. As the RTC can be used to start the LETIMER, the RTC and LETIMER can thus be combined to generate specific pulse-trains at given intervals. Software can update LETIMERn_COMP1 and LETIMERn_REP1 to change the number of pulses and pulse-period in each train, but if changes are not required, software does not have to update the registers between each pulse train. For the example in Figure 19.9 (p. 304) , the initial values cause the LETIMER to generate two pulses with 3 cycle periods, or a single pulse 3 cycles wide every time the LETIMER is started. After the output has been generated, the LETIMER stops, and is ready to be triggered again. Figure 19.9. LETIMER Triggered Operation Initial configuration, REP1 just written Write START= 1 Stop Stop Write START= 1 TOP1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 TOP0 X 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 CNT 0 2 1 0 2 1 0 0 0 0 0 0 2 1 0 2 1 0 0 0 0 2 1 0 REP0 0 2 2 2 1 1 1 0 0 0 0 0 2 2 2 1 1 1 0 0 0 2 2 2 REP1 2 2u 2u 2u 2u 2u 2u 2u 2u 2u 2u 2u 2u 2u 2u 2u 2u 2u 2u 2u 2u 2u 2u 2u Int. flags set UFIF UFIF REP0IF UFIF UFIF UFIF REP0IF LFACLKLETIMERn LETn_O0 UFOA0 = 01 LETn_O1 UFOA0 = 10 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 304 www.silabs.com ...the world's most energy friendly microcontrollers 19.3.6.2 Continuous Output Generation Example 19.2. LETIMER Continuous Output Generation In some scenarios, it might be desired to make LETIMER generate a continuous waveform. Very simple constant waveforms can be generated without the repeat counter as shown in Figure 19.6 (p. 302) , but to generate changing waveforms, using the repeat counter and buffer registers can prove advantageous. For the example in Figure 19.10 (p. 305) , the goal is to produce a pulse train consisting of 3 sequences with the following properties: • 3 pulses with periods of 3 cycles • 4 pulses with periods of 2 cycles • 2 pulses with periods of 3 cycles Figure 19.10. LETIMER Continuous Operation Write COMP1 = 2 REP1 = 2 Initial configuration, REPB just written Stop, final values COMP1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 COMP0 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 CNT 0 2 1 0 2 1 0 2 1 0 1 0 1 0 1 0 1 0 2 1 0 2 1 0 0 REP0 3 3 3 3 2 2 2 1 1 1 4 4 3 3 2 2 1 1 2 2 2 1 1 1 0 REP1 4 4 4 4 4 4 4 4 4 4 4u 4u 4u 2 2 2 2 2 2u 2u 2u 2u 2u 2u 2u UFIF UFIF Int. flags set UFIF UFIF UFIF UFIF UFIF REP0IF REP0IF UFIF REP0IF LFACLKLETIMERn LETn_O0 UFOA0 = 01 LETn_O1 UFOA0 = 10 Pulse Seq. 1 Pulse Seq. 2 Pulse Seq. 3 The first two sequences are loaded into the LETIMER before the timer is started. LETIMERn_COMP0 is set to 2 (cycles – 1), and LETIMERn_REP0 is set to 3 for the first sequence, and the second sequence is loaded into the buffer registers, i.e. COMP1 is set to 1 and LETIMERn_REP1 is set to 4. The LETIMER is set to trigger an interrupt when LETIMERn_REP0 is done by setting REP0 in LETIMERn_IEN. This interrupt is a good place to update the values of the buffers. Last but not least REPMODE in LETIMERn_CTRL is set to buffered mode, and the timer is started. In the interrupt routine the buffers are updated with the values for the third sequence. If this had not been done, the timer would have stopped after the second sequence. The final result is shown in Figure 19.10 (p. 305) . The pulse output is grouped to show which sequence generated which output. Toggle output is also shown in the figure. Note that the toggle output is not aligned with the pulse outputs. Note 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 305 www.silabs.com ...the world's most energy friendly microcontrollers Multiple LETIMER cycles are required to write a value to the LETIMER registers. The example in Figure 19.10 (p. 305) assumes that writes are done in advance so they arrive in the LETIMER as described in the figure. Figure 19.11 (p. 306) shows an example where the LETIMER is started while LETIMERn_CNT is nonzero. In this case the length of the first repetition is given by the value in LETIMERn_CNT. Figure 19.11. LETIMER LETIMERn_CNT Not Initialized to 0 Initial configuration, REP1 just written Stop, final values TOP1 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TOP0 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 CNT 4 3 2 1 0 2 1 0 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 0 REP0 3 3 3 3 3 2 2 2 1 1 1 3 3 3 3 2 2 2 2 1 1 1 1 0 REP1 3 3 3 3 3 3 3 3 3 3 3 3u 3u 3u 3u 3u 3u 3u 3u 3u 3u 3u 3u 3u Int. flags set UFIF UFIF UFIF REP0IF UFIF UFIF UFIF REP0IF LFACLKLETIMERn LETn_O0 UFOA0 = 01 LETn_O1 UFOA0 = 10 19.3.6.3 PWM Output Example 19.3. LETIMER PWM Output There are several ways of generating PWM output with the LETIMER, but the most straight-forward way is using the PWM output mode. This mode is enabled by setting UFOA0 or OFUA1 in LETIMERn_CTRL to 3. In PWM mode, the output is set idle on timer underflow, and active on LETIMERn_COMP1 match, so if for instance COMP0TOP = 1 and OPOL0 = 0 in LETIMERn_CTRL, LETIMERn_COMP0 determines the PWM period, and LETIMERn_LETIMERn_COMP1 determines the active period. The PWM period in PWM mode is LETIMERn_COMP0 + 1. There is no special handling of the case where LETIMERn_COMP1 > LETIMERn_COMP0, so if LETIMERn_COMP1 > LETIMERn_COMP0, the PWM output is given by the idle output value. This means that for OPOLx = 0 in LETIMERn_CTRL, the PWM output will always be 0 for at least one clock cycle, and for OPOLx = 1 LETIMERn_CTRL, the PWM output will always be 1 for at least one clock cycle. To generate a PWM signal using the full PWM range, invert OPOLx when LETIMERn_COMP1 is set to a value larger than LETIMERn_COMP0. 19.3.6.4 Interrupts Example 19.4. LETIMER PWM Output The interrupts generated by the LETIMER are combined into one interrupt vector. If the interrupt for the LETIMER is enabled, an interrupt will be made if one or more of the interrupt flags in LETIMERn_IF and their corresponding bits in LETIMER_IEN are set. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 306 www.silabs.com ...the world's most energy friendly microcontrollers 19.3.7 Using the LETIMER in EM3 The LETIMER can be enabled all the way down to EM3 by using the ULFRCO as clock source. This is done by clearing CMU_LFCLKSEL_LFA and setting CMU_LFCLKSEL_LFAE to 1. This will make the RTC use the internal 1 kHz ultra low frequency RC oscillator (ULFRCO), consuming very little energy. Please note that the ULFRCO is not accurate over temperature and voltage, and it should be verified that the ULFRCO fulfills the timekeeping needs of the application before using this in the design. 19.3.8 Register access This module is a Low Energy Peripheral, and supports immediate synchronization. For description regarding immediate synchronization, the reader is referred to Section 5.3.1.1 (p. 20) . 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 307 www.silabs.com ...the world's most energy friendly microcontrollers 19.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 LETIMERn_CTRL RW Control Register 0x004 LETIMERn_CMD W1 Command Register 0x008 LETIMERn_STATUS R Status Register 0x00C LETIMERn_CNT RWH Counter Value Register 0x010 LETIMERn_COMP0 RW Compare Value Register 0 0x014 LETIMERn_COMP1 RW Compare Value Register 1 0x018 LETIMERn_REP0 RW Repeat Counter Register 0 0x01C LETIMERn_REP1 RW Repeat Counter Register 1 0x020 LETIMERn_IF R Interrupt Flag Register 0x024 LETIMERn_IFS W1 Interrupt Flag Set Register 0x028 LETIMERn_IFC W1 Interrupt Flag Clear Register 0x02C LETIMERn_IEN RW Interrupt Enable Register 0x030 LETIMERn_FREEZE RW Freeze Register 0x034 LETIMERn_SYNCBUSY R Synchronization Busy Register 0x040 LETIMERn_ROUTE RW I/O Routing Register 19.5 Register Description 19.5.1 LETIMERn_CTRL - Control Register (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p. 20) . Access 0 1 RW 0x0 REPMODE 2 3 RW 0x0 UFOA0 4 5 RW 0x0 UFOA1 6 7 RW OPOL0 0 RW OPOL1 0 8 RW BUFTOP 0 9 RW COMP0TOP 0 10 RW RTCC0TEN 0 11 12 RW RTCC1TEN Name RW Access DEBUGRUN 0 Reset 0 13 14 15 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x000 16 Bit Position Offset Bit Name Reset Description 31:13 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 12 DEBUGRUN 0 RW Debug Mode Run Enable Set to keep the LETIMER running in debug mode. 11 Value Description 0 LETIMER is frozen in debug mode 1 LETIMER is running in debug mode RTCC1TEN 0 RW RTC Compare 1 Trigger Enable Allows the LETIMER to be started on a compare match on RTC compare channel 1. Value Description 0 LETIMER is not affected by RTC compare channel 1 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 308 www.silabs.com ...the world's most energy friendly microcontrollers Bit 10 Name Reset Access Description Value Description 1 A compare match on RTC compare channel 1 starts the LETIMER if the LETIMER is not already started RTCC0TEN 0 RW RTC Compare 0 Trigger Enable Allows the LETIMER to be started on a compare match on RTC compare channel 0. 9 Value Description 0 LETIMER is not affected by RTC compare channel 0 1 A compare match on RTC compare channel 0 starts the LETIMER if the LETIMER is not already started COMP0TOP 0 RW Compare Value 0 Is Top Value When set, the counter is cleared in the clock cycle after a compare match with compare channel 0. 8 Value Description 0 The top value of the LETIMER is 65535 (0xFFFF) 1 The top value of the LETIMER is given by COMP0 BUFTOP 0 RW Buffered Top Set to load COMP1 into COMP0 when REP0 reaches 0, allowing a buffered top value 7 Value Description 0 COMP0 is only written by software 1 COMP0 is set to COMP1 when REP0 reaches 0 OPOL1 0 RW Output 1 Polarity RW Output 0 Polarity RW Underflow Output Action 1 Defines the idle value of output 1. 6 OPOL0 0 Defines the idle value of output 0. 5:4 UFOA1 0x0 Defines the action on LETn_O1 on a LETIMER underflow. 3:2 Value Mode Description 0 NONE LETn_O1 is held at its idle value as defined by OPOL1. 1 TOGGLE LETn_O1 is toggled on CNT underflow. 2 PULSE LETn_O1 is held active for one LFACLKLETIMER0 clock cycle on CNT underflow. The output then returns to its idle value as defined by OPOL1. 3 PWM LETn_O1 is set idle on CNT underflow, and active on compare match with COMP1 UFOA0 0x0 RW Underflow Output Action 0 Defines the action on LETn_O0 on a LETIMER underflow. 1:0 Value Mode Description 0 NONE LETn_O0 is held at its idle value as defined by OPOL0. 1 TOGGLE LETn_O0 is toggled on CNT underflow. 2 PULSE LETn_O0 is held active for one LFACLKLETIMER0 clock cycle on CNT underflow. The output then returns to its idle value as defined by OPOL0. 3 PWM LETn_O0 is set idle on CNT underflow, and active on compare match with COMP1 REPMODE 0x0 RW Repeat Mode Allows the repeat counter to be enabled and disabled. Value Mode Description 0 FREE When started, the LETIMER counts down until it is stopped by software. 1 ONESHOT The counter counts REP0 times. When REP0 reaches zero, the counter stops. 2 BUFFERED The counter counts REP0 times. If REP1 has been written, it is loaded into REP0 when REP0 reaches zero. Else the counter stops 3 DOUBLE Both REP0 and REP1 are decremented when the LETIMER wraps around. The LETIMER counts until both REP0 and REP1 are zero 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 309 www.silabs.com ...the world's most energy friendly microcontrollers 19.5.2 LETIMERn_CMD - Command Register Offset Access 0 0 W1 START 2 1 0 0 W1 3 0 W1 W1 STOP Name CLEAR CTO1 Access CTO0 W1 0 Reset 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x004 Bit Position Bit Name Reset Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 4 CTO1 0 W1 Clear Toggle Output 1 W1 Clear Toggle Output 0 0 W1 Clear LETIMER 0 W1 Stop LETIMER 0 W1 Start LETIMER Set to drive toggle output 1 to its idle value 3 CTO0 0 Set to drive toggle output 0 to its idle value 2 CLEAR Set to clear LETIMER 1 STOP Set to stop LETIMER 0 START Set to start LETIMER 19.5.3 LETIMERn_STATUS - Status Register 0 1 2 3 4 5 6 7 8 9 10 0 Reset 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x008 Bit Position 31 Offset RUNNING R Access Name Bit Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 0 RUNNING 0 R LETIMER Running Set when LETIMER is running. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 310 www.silabs.com ...the world's most energy friendly microcontrollers 19.5.4 LETIMERn_CNT - Counter Value Register Offset 0 1 2 3 4 5 6 7 8 0x0000 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x00C Bit Position RWH Reset CNT Access Name Bit Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 CNT 0x0000 RWH Counter Value Use to read the current value of the LETIMER. 19.5.5 LETIMERn_COMP0 - Compare Value Register 0 (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p. 20) . Offset 0 1 2 3 4 5 6 7 8 0x0000 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x010 Bit Position RW Reset COMP0 Access Name Bit Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 COMP0 0x0000 RW Compare Value 0 Compare and optionally top value for LETIMER 19.5.6 LETIMERn_COMP1 - Compare Value Register 1 (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p. 20) . 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 311 www.silabs.com ...the world's most energy friendly microcontrollers 0 1 2 3 4 5 6 7 8 0x0000 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x014 Bit Position 31 Offset RW Reset COMP1 Access Name Bit Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 COMP1 0x0000 RW Compare Value 1 Compare and optionally buffered top value for LETIMER 19.5.7 LETIMERn_REP0 - Repeat Counter Register 0 (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p. 20) . 0 1 2 3 4 0x00 5 6 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x018 17 Bit Position Offset RW Reset REP0 Access Name Bit Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 7:0 REP0 0x00 RW Repeat Counter 0 Optional repeat counter. 19.5.8 LETIMERn_REP1 - Repeat Counter Register 1 (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p. 20) . 0 1 2 3 4 0x00 5 6 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x01C 17 Bit Position Offset RW Reset REP1 Access Name Bit Name Reset 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 Access Description 312 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description 7:0 REP1 0x00 RW Repeat Counter 1 Optional repeat counter or buffer for REP0 19.5.9 LETIMERn_IF - Interrupt Flag Register Access 0 0 R COMP0 1 2 0 0 R 3 0 R R UF Name COMP1 REP1 R Access REP0 0 Reset 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x020 Bit Position 31 Offset Bit Name Reset Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 4 REP1 0 R Repeat Counter 1 Interrupt Flag R Repeat Counter 0 Interrupt Flag Set when repeat counter 1 reaches zero. 3 REP0 0 Set when repeat counter 0 reaches zero or when the REP1 interrupt flag is loaded into the REP0 interrupt flag. 2 UF 0 R Underflow Interrupt Flag 0 R Compare Match 1 Interrupt Flag Set on LETIMER underflow. 1 COMP1 Set when LETIMER reaches the value of COMP1 0 COMP0 0 R Compare Match 0 Interrupt Flag Set when LETIMER reaches the value of COMP0 19.5.10 LETIMERn_IFS - Interrupt Flag Set Register Access 0 0 W1 COMP0 1 2 W1 0 0 W1 UF COMP1 3 0 W1 REP0 4 5 0 Name W1 Access REP1 Reset 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x024 Bit Position 31 Offset Bit Name Reset Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 4 REP1 0 W1 Set Repeat Counter 1 Interrupt Flag W1 Set Repeat Counter 0 Interrupt Flag W1 Set Underflow Interrupt Flag Write to 1 to set the REP1 interrupt flag. 3 REP0 0 Write to 1 to set the REP0 interrupt flag. 2 UF 0 Write to 1 to set the UF interrupt flag. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 313 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description 1 COMP1 0 W1 Set Compare Match 1 Interrupt Flag W1 Set Compare Match 0 Interrupt Flag Write to 1 to set the COMP1 interrupt flag. 0 COMP0 0 Write to 1 to set the COMP0 interrupt flag. 19.5.11 LETIMERn_IFC - Interrupt Flag Clear Register Access 0 0 W1 COMP0 1 2 0 0 W1 3 0 W1 W1 UF Name COMP1 REP1 Access REP0 W1 0 Reset 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x028 Bit Position 31 Offset Bit Name Reset Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 4 REP1 0 W1 Clear Repeat Counter 1 Interrupt Flag W1 Clear Repeat Counter 0 Interrupt Flag W1 Clear Underflow Interrupt Flag W1 Clear Compare Match 1 Interrupt Flag W1 Clear Compare Match 0 Interrupt Flag Write to 1 to clear the REP1 interrupt flag. 3 REP0 0 Write to 1 to clear the REP0 interrupt flag. 2 UF 0 Write to 1 to clear the UF interrupt flag. 1 COMP1 0 Write to 1 to clear the COMP1 interrupt flag. 0 COMP0 0 Write to 1 to clear the COMP0 interrupt flag. 19.5.12 LETIMERn_IEN - Interrupt Enable Register Access 0 0 RW COMP0 1 2 RW 0 0 RW UF COMP1 3 0 RW REP0 4 5 6 0 Name RW Access REP1 Reset 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x02C Bit Position 31 Offset Bit Name Reset Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 4 REP1 0 RW Repeat Counter 1 Interrupt Enable Set to enable interrupt on the REP1 interrupt flag. 3 REP0 0 RW Repeat Counter 0 Interrupt Enable Set to enable interrupt on the REP0 interrupt flag. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 314 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description 2 UF 0 RW Underflow Interrupt Enable RW Compare Match 1 Interrupt Enable Set to enable interrupt on the UF interrupt flag. 1 COMP1 0 Set to enable interrupt on the COMP1 interrupt flag. 0 COMP0 0 RW Compare Match 0 Interrupt Enable Set to enable interrupt on the COMP0 interrupt flag. 19.5.13 LETIMERn_FREEZE - Freeze Register RW 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x030 Bit Position 31 Offset REGFREEZE Access Name Bit Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 0 REGFREEZE 0 RW Register Update Freeze When set, the update of the LETIMER is postponed until this bit is cleared. Use this bit to update several registers simultaneously. Value Mode Description 0 UPDATE Each write access to a LETIMER register is updated into the Low Frequency domain as soon as possible. 1 FREEZE The LETIMER is not updated with the new written value. 19.5.14 LETIMERn_SYNCBUSY - Synchronization Busy Register Access 0 R R CMD CTRL 0 1 2 R COMP0 0 R COMP1 0 3 R REP0 0 4 R Name REP1 Access 0 5 6 7 8 9 0 Reset 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x034 Bit Position 31 Offset Bit Name Reset Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 5 REP1 0 R REP1 Register Busy Set when the value written to REP1 is being synchronized. 4 REP0 0 R REP0 Register Busy Set when the value written to REP0 is being synchronized. 3 COMP1 0 R COMP1 Register Busy Set when the value written to COMP1 is being synchronized. 2 COMP0 0 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 R COMP0 Register Busy 315 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description Set when the value written to COMP0 is being synchronized. 1 CMD 0 R CMD Register Busy Set when the value written to CMD is being synchronized. 0 CTRL 0 R CTRL Register Busy Set when the value written to CTRL is being synchronized. 19.5.15 LETIMERn_ROUTE - I/O Routing Register Access 0 RW 0 1 2 3 4 6 7 5 0 OUT0PEN Name RW LOCATION Access OUT1PEN Reset 8 9 RW 0x0 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x040 Bit Position 31 Offset Bit Name Reset Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 10:8 LOCATION 0x0 RW I/O Location Decides the location of the LETIMER I/O pins Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 7:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 1 OUT1PEN 0 RW Output 1 Pin Enable When set, output 1 of the LETIMER is enabled 0 Value Description 0 The LETn_O1 pin is disabled 1 The LETn_O1 pin is enabled OUT0PEN 0 RW Output 0 Pin Enable When set, output 0 of the LETIMER is enabled Value Description 0 The LETn_O0 pin is disabled 1 The LETn_O0 pin is enabled 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 316 www.silabs.com ...the world's most energy friendly microcontrollers 20 PCNT - Pulse Counter Quick Facts What? 0 1 2 3 4 The Pulse Counter (PCNT) decodes incoming pulses. The module has a quadrature mode which may be used to decode the speed and direction of a mechanical shaft. PCNT can operate in EM0EM3. Reload value Why? 0 The PCNT generates an interrupt after a specific number of pulses (or rotations), eliminating the need for timing- or I/O interrupts and CPU processing to measure pulse widths, etc. Interrupt Quadrature code How? PCNT uses the LFACLK or may be externally clocked from a pin. The module incorporates a 16-bit up/down-counter to keep track of incoming pulses or rotations. 20.1 Introduction The Pulse Counter (PCNT) can be used for counting incoming pulses on a single input or to decode quadrature encoded inputs. It can run from the internal LFACLK (EM0-EM2) while counting pulses on the PCNTn_S0IN pin or using this pin as an external clock source (EM0-EM3) that runs both the PCNT counter and register access. 20.2 Features • • • • • • • • • • 16-bit counter with reload register Auxiliary counter for counting a single direction Single input oversampling up/down counter mode (EM0-EM2) Externally clocked single input pulse up/down counter mode (EM0-EM3) Externally clocked quadrature decoder mode (EM0-EM3) Interrupt on counter underflow and overflow Interrupt when a direction change is detected (quadrature decoder mode only) Optional pulse width filter Optional input inversion/edge detect select PRS S0IN and S1IN input 20.3 Functional Description An overview of the PCNT module is shown in Figure 20.1 (p. 318) . 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 317 www.silabs.com ...the world's most energy friendly microcontrollers Figure 20.1. PCNT Overview CMU (conseptual) LFACLK Clock switch CLKPCNT S0PRS Input N PC Peripheral bus Tn N Pulse Width Filter Edge detector OVR_SINGLE EXTCLK_SINGLE 1 Tn 1I _S N Inverter Quadrature decoder Count Enable N PC Analog de- glitch filter 0I _S Inverter TOP TOPB CNT EXTCLK_QUAD S1PRS Input 20.3.1 Pulse Counter Modes The pulse counter can operate in single input oversampling mode (OVSSINGLE), externally clocked single input counter mode (EXTCLKSINGLE) and externally clocked quadrature decoder mode (EXTCLKQUAD). The following sections describe operation of each of the three modes and how they are enabled. Input timing constraints are described in Section 20.3.5 (p. 321) and Section 20.3.6 (p. 321) . 20.3.1.1 Single Input Oversampling Mode This mode is enabled by writing OVSSINGLE to the MODE field in the PCNTn_CTRL register and disabled by writing DISABLE to the same field. LFACLK is configured from the registers in the Clock Management Unit (CMU), Chapter 11 (p. 99) . The optional pulse width filter is enabled by setting the FILT bit in the PCNTn_CTRL register. Additionally, the PCNTn_S0IN input may be inverted, so that falling edges are counted, by setting the EDGE bit in the PCNTn_CTRL register. If S1CDIR is cleared, PCNTn_S0IN is the only observed input in this mode. The PCNTn_S0IN input is sampled by the LFACLK and the number of detected positive or negative edges on PCNTn_S0IN appears in PCNTn_CNT. The counter may be configured to count down by setting the CNTDIR bit in PCNTn_CTRL. Default is to count up. The counting direction can also be controlled externally in this mode by setting S1CDIR in PCNTn_CTRL. This will make the input value on PCNTn_S1IN decide the direction counted on a PCNTn_S0IN edge. If PCNTn_S1IN is high, the count is done according to CNTDIR in PCNTn_CTRL. If low, the count direction is opposite. 20.3.1.2 Externally Clocked Single Input Counter Mode This mode is enabled by writing EXTCLKSINGLE to the MODE field in the PCNTn_CTRL register and disabled by writing DISABLE to the same field. The external pin clock source must be configured from the registers in the CMU (Chapter 11 (p. 99) ). Positive edges on PCNTn_S0IN are used to clock the counter. Similar to the oversampled mode, PCNTn_S1IN is used to determine the count direction if S1CDIR in PCNTn_CTRL is set. If not, CNTDIR in PCNTn_CTRL solely defines count direction. As the LFACLK is not used in this mode, the PCNT module can operate in EM3. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 318 www.silabs.com ...the world's most energy friendly microcontrollers The digital pulse width filter is not available in this mode. The analog de-glitch filter in the GPIO pads is capable of removing some unwanted noise. However, this mode may be susceptible to spikes and unintended pulses from devices such as mechanical switches, and is therefore most suited to take input from electronic sensors etc. that generate single wire pulses. 20.3.1.3 Externally Clocked Quadrature Decoder Mode This mode is enabled by writing EXTCLKQUAD to the MODE field in PCNTn_CTRL and disabled by writing DISABLE to the same field. The external pin clock source must be configured from the registers in the CMU, (Chapter 11 (p. 99) ). Both edges on PCNTn_S0IN pin are used to sample PCNTn_S1IN pin to decode the quadrature code. Consequently, this mode does not depend on the internal LFACLK and may be operated in EM3. A quadrature coded signal contains information about the relative speed and direction of a rotating shaft as illustrated by Figure 20.2 (p. 319) , hence the direction of the counter register PCNTn_CNT is controlled automatically. Figure 20.2. PCNT Quadrature Coding Clockwise direction Reset 1 cycle/ sector, 4 states 00 10 11 01 X X PCNTn_S0IN PCNTn_S1IN PCNTn_CNT 0 Counter clockwise direction 0 1 2 PCNTn_TOP PCNTn_TOP- 1 1 cycle/ sector, 4 states 00 01 11 10 X X PCNTn_S0IN PCNTn_S1IN PCNTn_CNT 0 0 X = sensor position If PCNTn_S0IN leads PCNTn_S1IN in phase, the direction is clockwise, and if it lags in phase the direction is counter-clockwise. Although the direction is automatically detected, the detected direction may be inverted by writing 1 to the EDGE bit in the PCNTn_CTRL register. Default behavior is illustrated by Figure 20.2 (p. 319) . The counter direction may be read from the DIR bit in the PCNTn_STATUS register. Additionally, the DIRCNG interrupt in the PCNTn_IF register is generated when a direction change is detected. When a change is detected, the DIR bit in the PCNTn_STATUS register must be read to determine the current new direction. Note The sector disc illustrated in the figure may be finer grained in some systems. Typically, they may generate 2-4 PCNTn_S0IN wave periods per 360° rotation. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 319 www.silabs.com ...the world's most energy friendly microcontrollers The direction of the quadrature code and control of the counter is generated by the simple binary function outlined by Table 20.1 (p. 320) . Note that this function also filters some invalid inputs that may occur when the shaft changes direction or temporarily toggles direction. Table 20.1. PCNT QUAD Mode Counter Control Function Inputs Control/Status S1IN posedge S1IN negedge Count Enable CNTDIR status bit 0 0 0 0 0 1 1 0 1 0 1 1 1 1 0 0 Note PCNTn_S1IN is sampled on both edges of PCNTn_S0IN. 20.3.2 Hysteresis By default the pulse counter wraps to 0 when passing the configured top value, and wraps to the top value when counting down from 0. On these events, a system will likely want to wake up to store and track the overflow count. This is fine if the pulse counter is tracking a monotonic value or a value that does not change directions frequently. If you have the latter however, and the counter changes directions around the overflow/underflow point, the system will have to wake up a lot to keep track of the rotations, causing high current consumptions To solve this, the pulse counter has a way of introducing hysteresis to the counter. When HYST in PCNTn_CTRL is set, the pulse counter will always wrap to TOP/2 on underflows and overflows. This takes the counter away from the area where it might overflow or underflow, removing the problem. Given a starting value of 0 for the counter, the absolute count value when hysteresis is enabled can be calculated with the equations Equation 20.1 (p. 320) or Equation 20.2 (p. 320) , depending on whether the TOP value is even or odd. Absolute position with hysteresis and even TOP value CNTabs = CNT - UFCNT x (TOP/2+1) + OFCNT x (TOP/2+1) (20.1) Absolute position with hysteresis and odd TOP value CNTabs = CNT - UFCNT x (TOP/2+1) + OFCNT x (TOP/2+2) (20.2) 20.3.3 Auxiliary counter To be able to keep explicit track of counting in one direction in addition to the regular counter which counts both up and down, the auxiliary counter can be used. The pulse counter can for instance be configured to keep track of the absolute rotation of the wheel, and at the same time the auxiliary counter can keep track of how much the wheel has reversed. The auxiliary counter is enabled by configuring AUXCNTEV in PCNTn_CTRL. It will always count up, but it can be configured whether it should count up on up-events, down-events or both, keeping track of rotation either way or general movement. The value of the auxiliary counter can be read from the PCNTn_AUXCNT register. Overflows on the auxiliary counter happen when the auxiliary counter passes the top value of the pulse counter, configured in PCNTn_TOP. In that event, the AUXOF interrupt flag is set, and the auxiliary counter wraps to 0. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 320 www.silabs.com ...the world's most energy friendly microcontrollers As the auxiliary counter, the main counter can be configured to count only on certain events. This is done through CNTEV in PCNTn_CTRL, and it is possible like for the auxiliary counter, to make the main counter count on only up and down events. The difference between the counters is that where the auxiliary counter will only count up, the main counter will count up or down depending on the direction of the count event. 20.3.4 Register Access The counter-clock domain may be clocked externally. To update the counter-clock domain registers from software in this mode, 2-3 clock pulses on the external clock are needed to synchronize accesses to the externally clocked domain. Clock source switching is controlled from the registers in the CMU (Chapter 11 (p. 99) ). When the RSTEN bit in the PCNTn_CTRL register is set to 1, the PCNT clock domain is asynchronously held in reset. The reset is synchronously released two PCNT clock edges after the RSTEN bit in the PCNTn_CTRL register is cleared by software. This asynchronous reset restores the reset values in PCNTn_TOP, PCNTn_CNT and other control registers in the PCNT clock domain. Since this module is a Low Energy Peripheral, and runs off a clock which is asynchronous to the HFCORECLK, special considerations must be taken when accessing registers. Please refer to Section 5.3 (p. 20) for a description on how to perform register accesses to Low Energy Peripherals. Note PCNTn_TOP and PCNTn_CNT are read-only registers. When writing to PCNTn_TOPB, make sure that the counter value, PCNTn_CNT, can not exceed the value written to PCNTn_TOPB within two clock cycles. 20.3.5 Clock Sources The 32 kHz LFACLK is one of two possible clock sources. The clock select register is described in Chapter 11 (p. 99) . The default clock source is the LFACLK. This PCNT module may also use PCNTn_S0IN as an external clock to clock the counter (EXTCLKSINGLE mode) and to sample PCNTn_S1IN (EXTCLKQUAD mode). Setup, hold and max frequency constraints for PCNTn_S0IN and PCNTn_S1IN for these modes are specified in the device datasheet. To use this module, the LE interface clock must be enabled in CMU_HFCORECLKEN0, in addition to the module clock. Note PCNT Clock Domain Reset, RSTEN, should be set when changing clock source for PCNT. If changing to an external clock source, the clock pin has to be enabled as input prior to deasserting RSTEN. Changing clock source without asserting RSTEN results in undefined behaviour. 20.3.6 Input Filter An optional pulse width filter is available in OVSSINGLE mode. The filter is enabled by writing 1 to the FILT bit in the PCNTn_CTRL register. When enabled, the high and low periods of PCNTn_S0IN must be stable for 5 consecutive clock cycles before the edge is passed to the edge detector. In EXTCLKSINGLE and EXTCLKQUAD mode, there is no digital pulse width filter available. 20.3.7 Edge Polarity The edge polarity can be set by configuring the EDGE bit in the PCNTn_CTRL register. When this bit is cleared, the pulse counter counts positive edges in OVSSINGLE mode and negative edges if the bit is set. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 321 www.silabs.com ...the world's most energy friendly microcontrollers In EXTCLKQUAD mode, the EDGE bit in PCNTn_CTRL inverts the direction of the counter (which is automatically detected). Note The EDGE bit in PCNTn_CTRL has no effect in EXTCLKSINGLE mode. 20.3.8 PRS S0IN and S1IN Input It is possible to receive input from PRS on both SOIN and S1IN by setting S0PRSEN or S1PRSEN in PCNTn_INPUT. The PRS channel used can be selected using S0PRSSEL in PCNTn_INPUT. 20.3.9 Interrupts The interrupt generated by PCNT uses the PCNTn_INT interrupt vector. Software must read the PCNTn_IF register to determine which module interrupt that generated the vector invocation. 20.3.9.1 Underflow and Overflow Interrupts The underflow interrupt flag (UF) is set when the counter counts down from 0. I.e. when the value of the counter is 0 and a new pulse is received. The PCNTn_CNT register is loaded with the PCNTn_TOP value after this event. The overflow interrupt flag (OF) is set when the counter counts up from the PCNTn_TOP (reload) value. I.e. if PCNTn_CNT = PCNTn_TOP and a new pulse is received. The PCNTn_CNT register is loaded with the value 0 after this event. 20.3.9.2 Direction Change Interrupt The PCNTn_PCNT module sets the DIRCNG interrupt flag (PCNTn_IF register) when the direction of the quadrature code changes. The behavior of this interrupt is illustrated by Figure 20.3 (p. 322) . Figure 20.3. PCNT Direction Change Interrupt (DIRCNG) Generation X X Standard async handshake interface Invalid pulse generated when the shaft changes direction PCNTn_S0IN PCNTn_S1IN Interrupt PCNTn_CNT n n+ 1 n+ 2 n+ 3 n+ 2 Delay from the shaft physically changed direction until the counter direction is changed and the interrupt is generated 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 322 www.silabs.com ...the world's most energy friendly microcontrollers 20.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 PCNTn_CTRL RW Control Register 0x004 PCNTn_CMD W1 Command Register 0x008 PCNTn_STATUS R Status Register 0x00C PCNTn_CNT R Counter Value Register 0x010 PCNTn_TOP R Top Value Register 0x014 PCNTn_TOPB RW Top Value Buffer Register 0x018 PCNTn_IF R Interrupt Flag Register 0x01C PCNTn_IFS W1 Interrupt Flag Set Register 0x020 PCNTn_IFC W1 Interrupt Flag Clear Register 0x024 PCNTn_IEN RW Interrupt Enable Register 0x028 PCNTn_ROUTE RW I/O Routing Register 0x02C PCNTn_FREEZE RW Freeze Register 0x030 PCNTn_SYNCBUSY R Synchronization Busy Register 0x038 PCNTn_AUXCNT RWH Auxiliary Counter Value Register 0x03C PCNTn_INPUT RW PCNT Input Register 20.5 Register Description 20.5.1 PCNTn_CTRL - Control Register (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p. 20) . Access 0 1 RW 0x0 MODE 2 RW CNTDIR 0 3 RW EDGE 0 4 0 RW FILT 6 5 0 RW RSTEN 7 8 0 RW HYST 9 0 RW S1CDIR 10 11 RW 0x0 12 13 CNTEV Name 14 15 Access RW 0x0 Reset AUXCNTEV 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x000 Bit Position 31 Offset Bit Name Reset Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:14 AUXCNTEV 0x0 RW Controls when the auxiliary counter counts Selects whether the auxiliary counter responds to up-count events, down-count events or both Value Mode Description 0 NONE Never counts. 1 UP Counts up on up-count events. 2 DOWN Counts up on down-count events. 3 BOTH Counts up on both up-count and down-count events. 13:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 11:10 CNTEV 0x0 RW Controls when the counter counts Selects whether the regular counter responds to up-count events, down-count events or both 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 323 www.silabs.com ...the world's most energy friendly microcontrollers Bit 9 Name Reset Access Description Value Mode Description 0 BOTH Counts up on up-count and down on down-count events. 1 UP Only counts up on up-count events. 2 DOWN Only counts down on down-count events. 3 NONE Never counts. S1CDIR 0 RW Count direction determined by S1 S1 gives the direction of counting when in the OVSSINGLE or EXTCLKSINGLE modes. When S1 is high, the count direction is given by CNTDIR, and when S1 is low, the count direction is the opposite 8 HYST 0 RW Enable Hysteresis When hysteresis is enabled, the PCNT will always overflow and underflow to TOP/2. 7:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 5 RSTEN 0 RW Enable PCNT Clock Domain Reset The PCNT clock domain is asynchronously held in reset when this bit is set. The reset is synchronously released two PCNT clock edges after this bit is cleared. If external clock used the reset should be performed by setting and clearing the bit without pending for SYNCBUSY bit. 4 FILT 0 RW Enable Digital Pulse Width Filter The filter passes all high and low periods that are at least 5 clock cycles long. This filter is only available in OVSSINGLE mode. 3 EDGE 0 RW Edge Select Determines the polarity of the incoming edges. This bit should be written when PCNT is in DISABLE mode, otherwise the behavior is unpredictable. This bit is ignored in EXTCLKSINGLE mode. 2 Value Mode Description 0 POS Positive edges on the PCNTn_S0IN inputs are counted in OVSSINGLE mode. 1 NEG Negative edges on the PCNTn_S0IN inputs are counted in OVSSINGLE mode, and the counter direction is inverted in EXTCLKQUAD mode. CNTDIR 0 RW Non-Quadrature Mode Counter Direction Control The direction of the counter must be set in the OVSSINGLE and EXTCLKSINGLE modes. This bit is ignored in EXTCLKQUAD mode as the direction is automatically detected. 1:0 Value Mode Description 0 UP Up counter mode. 1 DOWN Down counter mode. MODE 0x0 RW Mode Select Selects the mode of operation. The corresponding clock source must be selected from the CMU. Value Mode Description 0 DISABLE The module is disabled. 1 OVSSINGLE Single input LFACLK oversampling mode (available in EM0-EM2). 2 EXTCLKSINGLE Externally clocked single input counter mode (available in EM0-EM3). 3 EXTCLKQUAD Externally clocked quadrature decoder mode (available in EM0-EM3). 20.5.2 PCNTn_CMD - Command Register (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p. 20) . 324 0 W1 LCNTIM 0 2 3 4 5 6 7 8 9 10 11 12 13 14 1 W1 Name LTOPBIM Access 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 15 0 Reset 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x004 Bit Position 31 Offset www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 1 LTOPBIM 0 W1 Load TOPB Immediately This bit has no effect since TOPB is not buffered and it is loaded directly into TOP. 0 LCNTIM 0 W1 Load CNT Immediately Load PCNTn_TOP into PCNTn_CNT on the next counter clock cycle. 20.5.3 PCNTn_STATUS - Status Register Offset 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x008 Bit Position R Access DIR Name Bit Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 0 DIR 0 R Current Counter Direction Current direction status of the counter. This bit is valid in EXTCLKQUAD mode only. Value Mode Description 0 UP Up counter mode (clockwise in EXTCLKQUAD mode with the NEDGE bit in PCNTn_CTRL set to 0). 1 DOWN Down counter mode. 20.5.4 PCNTn_CNT - Counter Value Register 0 1 2 3 4 5 6 7 8 0x0000 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x00C Bit Position 31 Offset Reset CNT R Access Name Bit Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 CNT 0x0000 R Counter Value Gives read access to the counter. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 325 www.silabs.com ...the world's most energy friendly microcontrollers 20.5.5 PCNTn_TOP - Top Value Register 0 1 2 3 4 5 6 7 8 0x00FF 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x010 Bit Position 31 Offset Reset TOP R Access Name Bit Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 TOP 0x00FF R Counter Top Value When counting down, this value is reloaded into PCNTn_CNT when counting past 0. When counting up, 0 is written to the PCNTn_CNT register when counting past this value. 20.5.6 PCNTn_TOPB - Top Value Buffer Register (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p. 20) . 0 1 2 3 4 5 6 7 8 0x00FF 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x014 Bit Position 31 Offset RW Reset TOPB Access Name Bit Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 TOPB 0x00FF RW Counter Top Buffer Loaded automatically to TOP when written. 20.5.7 PCNTn_IF - Interrupt Flag Register 326 0 R UF 0 1 2 R OF 0 R DIRCNG 0 4 5 6 7 8 9 10 11 12 13 14 3 R Name AUXOF Access 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 15 0 Reset 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x018 Bit Position 31 Offset www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 3 AUXOF 0 R Overflow Interrupt Read Flag R Direction Change Detect Interrupt Flag Set when an Auxiliary CNT overflow occurs 2 DIRCNG 0 Set when the count direction changes. Set in EXTCLKQUAD mode only. 1 OF 0 R Overflow Interrupt Read Flag R Underflow Interrupt Read Flag Set when a CNT overflow occurs 0 UF 0 Set when a CNT underflow occurs 20.5.8 PCNTn_IFS - Interrupt Flag Set Register Offset Access 0 0 1 2 0 0 W1 W1 W1 UF Name OF AUXOF Access DIRCNG W1 0 Reset 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x01C Bit Position Bit Name Reset Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 3 AUXOF 0 W1 Auxiliary Overflow Interrupt Set Write to 1 to set the auxiliary overflow interrupt flag 2 DIRCNG 0 W1 Direction Change Detect Interrupt Set Write to 1 to set the direction change interrupt flag 1 OF 0 W1 Overflow Interrupt Set W1 Underflow interrupt set Write to 1 to set the overflow interrupt flag 0 UF 0 Write to 1 to set the underflow interrupt flag 20.5.9 PCNTn_IFC - Interrupt Flag Clear Register Offset 0 W1 UF 0 1 2 W1 OF 0 W1 DIRCNG Bit Name Reset 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 3 AUXOF 0 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 Access W1 Name AUXOF Access 0 3 4 5 6 0 Reset 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x020 Bit Position Description W1 Auxiliary Overflow Interrupt Clear 327 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description Write to 1 to clear the auxiliary overflow interrupt flag 2 DIRCNG 0 W1 Direction Change Detect Interrupt Clear Write to 1 to clear the direction change detect interrupt flag 1 OF 0 W1 Overflow Interrupt Clear W1 Underflow Interrupt Clear Write to 1 to clear the overflow interrupt flag 0 UF 0 Write to 1 to clear the underflow interrupt flag 20.5.10 PCNTn_IEN - Interrupt Enable Register Access 0 0 1 2 0 0 RW RW RW UF Name OF AUXOF Access DIRCNG RW 0 Reset 3 4 5 6 7 8 9 10 11 12 13 14 15 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x024 16 Bit Position Offset Bit Name Reset Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 3 AUXOF 0 RW Auxiliary Overflow Interrupt Enable RW Direction Change Detect Interrupt Enable 0 RW Overflow Interrupt Enable 0 RW Underflow Interrupt Enable Enable the auxiliary overflow interrupt 2 DIRCNG 0 Enable the direction change detect interrupt. 1 OF Enable the overflow interrupt 0 UF Enable the underflow interrupt 20.5.11 PCNTn_ROUTE - I/O Routing Register Offset 0 1 2 3 4 5 6 7 8 9 RW 0x0 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x028 Bit Position Reset LOCATION Access Name Bit Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 10:8 LOCATION 0x0 RW I/O Location Defines the location of the PCNT input pins. E.g. PCNTn_S0#0, #1 or #2. Value Mode Description 0 LOC0 Location 0 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 328 www.silabs.com ...the world's most energy friendly microcontrollers Bit 7:0 Name Reset Access Description Value Mode Description 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 20.5.12 PCNTn_FREEZE - Freeze Register RW 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x02C 16 Bit Position Offset REGFREEZE Access Name Bit Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 0 REGFREEZE 0 RW Register Update Freeze When set, the update of the PCNT clock domain is postponed until this bit is cleared. Use this bit to update several registers simultaneously. Value Mode Description 0 UPDATE Each write access to a PCNT register is updated into the Low Frequency domain as soon as possible. 1 FREEZE The PCNT clock domain is not updated with the new written value. 20.5.13 PCNTn_SYNCBUSY - Synchronization Busy Register Access 0 R R CTRL 0 1 2 R CMD Name TOPB Access 0 3 4 5 6 7 8 9 0 Reset 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x030 Bit Position 31 Offset Bit Name Reset Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 2 TOPB 0 R TOPB Register Busy Set when the value written to TOPB is being synchronized. 1 CMD 0 R CMD Register Busy Set when the value written to CMD is being synchronized. 0 CTRL 0 R CTRL Register Busy Set when the value written to CTRL is being synchronized. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 329 www.silabs.com ...the world's most energy friendly microcontrollers 20.5.14 PCNTn_AUXCNT - Auxiliary Counter Value Register 0 1 2 3 4 5 6 7 8 0x0000 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x038 Bit Position 31 Offset RWH Reset AUXCNT Access Name Bit Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 AUXCNT 0x0000 RWH Auxiliary Counter Value Gives read access to the auxiliary counter. 20.5.15 PCNTn_INPUT - PCNT Input Register Access 0 1 2 RW 0x0 S0PRSSEL 3 4 6 7 5 0 RW S0PRSEN Name 8 RW 0x0 S1PRSSEL Access 9 10 0 RW S1PRSEN Reset 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x03C Bit Position 31 Offset Bit Name Reset Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 10 S1PRSEN 0 RW S1IN PRS Enable When set, the PRS channel is selected as input to S1IN. 9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 8:6 S1PRSSEL 0x0 RW S1IN PRS Channel Select Select PRS channel as input to S1IN. Value Mode Description 0 PRSCH0 PRS Channel 0 selected. 1 PRSCH1 PRS Channel 1 selected. 2 PRSCH2 PRS Channel 2 selected. 3 PRSCH3 PRS Channel 3 selected. 4 PRSCH4 PRS Channel 4 selected. 5 PRSCH5 PRS Channel 5 selected. 6 PRSCH6 PRS Channel 6 selected. 7 PRSCH7 PRS Channel 7 selected. 5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 4 S0PRSEN 0 RW S0IN PRS Enable When set, the PRS channel is selected as input to S0IN. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 330 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description 3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 2:0 S0PRSSEL 0x0 RW S0IN PRS Channel Select Select PRS channel as input to S0IN. Value Mode Description 0 PRSCH0 PRS Channel 0 selected. 1 PRSCH1 PRS Channel 1 selected. 2 PRSCH2 PRS Channel 2 selected. 3 PRSCH3 PRS Channel 3 selected. 4 PRSCH4 PRS Channel 4 selected. 5 PRSCH5 PRS Channel 5 selected. 6 PRSCH6 PRS Channel 6 selected. 7 PRSCH7 PRS Channel 7 selected. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 331 www.silabs.com ...the world's most energy friendly microcontrollers 21 LESENSE - Low Energy Sensor Interface Quick Facts What? 0 1 2 3 LESENSE is a low energy sensor interface capable of autonomously collecting and processing data from multiple sensors even when in EM2. Flexible configuration makes LESENSE a versatile sensor interface compatible with a wide range of sensors and measurement schemes. 4 Why? Z Z Z Z Capability to autonomously monitor sensors allows the EFM32TG to reside in a low energy mode for long periods of time while keeping track of sensor status and sensor events. Z EFM32 How? LESENSE is highly configurable and is capable of collecting data from a wide range of sensor types. Once the data is collected, the programmable state machine, LESENSE decoder, is capable of processing sensor data without CPU intervention. A large result buffer allows the chip to remain in EM2 for long periods of time while autonomously collecting data. 21.1 Introduction LESENSE is a low energy sensor interface which utilizes on-chip peripherals to perform measurement of a configurable set of sensors. The results from sensor measurements can be processed by the LESENSE decoder, which is a configurable state machine with up to 16 states. The results can also be stored in a result buffer to be collected by CPU or DMA for further processing. LESENSE operates in EM2, in addition to EM1 and EM0, and can wake up the CPU on configurable events. 21.2 Features • • • • • • • Up to 16 sensors Autonomous sensor monitoring in EM0, EM1, and EM2 Highly configurable decoding of sensor results Interrupt on sensor events Configurable enable signals to external sensors Circular buffer for storage of up to 16 sensor results. Support for multiple sensor types • LC sensors • Capacitive sensing • General analog sensors 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 332 www.silabs.com ...the world's most energy friendly microcontrollers 21.3 Functional description LESENSE is a module capable of controlling on-chip peripherals in order to perform monitoring of different sensors with little or no CPU intervention. LESENSE uses the analog comparators, ACMP, for measurement of sensor signals. LESENSE can also control the DAC to generate accurate reference voltages. Figure 21.1 (p. 333) shows an overview of the LESENSE module. LESENSE consists of a sequencer, count and compare block, a decoder, and a RAM block used for configuration and result storage. The sequencer handles interaction with other peripherals as well as timing of sensor measurements. The count and compare block is used to count pulses from ACMP outputs before comparing with a configurable threshold. To autonomously analyze sensor results, the LESENSE decoder provides possibility to define a finite state machine with up to 16 states, and programmable actions upon state transitions. This allows the decoder to implement a wide range of decoding schemes, for instance quadrature decoding. A RAM block is used for storage of configuration and measurement results. This allows LESENSE to have a relatively large result buffer enabling the chip to remain in a low energy mode for long periods of time while collecting sensor data. Figure 21.1. LESENSE block diagram ACMP1 ACMP1_CHn * LESENSE controls CONVMODE and OUTMODE individually for the DAC channels POSSEL Register bitfields overridden by LESENSE LESENSE ACMP sam ple reg VSS DAC0_CH0 DAC0_CH1 PRS input Counter 1.25 V ACMP1INV 2.5 V DAC0_CH1 VDD Scaler ACMP0 ACMP0_CHn VDDLEVEL Decoder PRS Com pare POSSEL ACMP0INV DAC interface VSS DAC0_CH0 DAC0_CH1 DAC0 RAM CONVMODE* 1.25 V OUTMODE* 2.5 V VDD Sequencer CHx DATA Scaler VDDLEVEL CHx CTRL_EN CH0 DAC0_CH0 AUXHFRCO CH1 DAC0_CH0 DAC0_CH1 LES_ALTEXn 21.3.1 Channel configuration LESENSE has 16 individually configurable channels, the first eight are mapped to the channels of ACMP0, while the last eight are mapped to the channels of ACMP1. Each LESENSE channel has its own set of configuration registers. Channel configuration is split into three registers; CHx_TIMING, CHx_INTERACT, and CHx_EVAL. Individual timing for each sensor is configured in CHx_TIMING, sensor interaction is configured in CHx_INTERACT, and configurations regarding evaluation of the measurements are done in CHx_EVAL. For improved readability, CHx_CONF will be used to address 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 333 www.silabs.com ...the world's most energy friendly microcontrollers the channel configuration registers, CHx_TIMING, CHx_INTERACT, and CHx_EVAL, throughout this chapter. By default, the channel configuration registers are directly mapped to the channel number. Configuring SCANCONF in CTRL makes it possible to alter this mapping. Configuring SCANCONF to INVMAP will make channels 0-7 use the channel configuration registers for channels 8-15, and vice versa. This feature allows an application to quickly and easily switch configuration set for the channels. Setting SCANCONF to TOGGLE will make channel x alternate between using CHX_CONF and CHX +8_CONF. The configuration used is decided by the state of the corresponding bit in SCANRES. For instance, if channel 3 is performing a scan and bit 3 in SCANRES is set, CH11_CONF will be used. Channels 8 through 15 will toggle between CHX_CONF and CHX-8_CONF. This mode provides an easy way for implementation of hysteresis on channel events as threshold values can be changed depending on sensor status. Setting SCANCONF to DECDEF will make the state of the decoder define which scan configuration to be used. If the decoder state is at index 8 or higher, channel x will use CHX+8_CONF, otherwise it will use CHX configuration. Similarly, channels 8 through 15 will use CHX configuration when decoder state index is less than 8 and CHX-8_CONF when decoder state index is higher than 7. Allowing the decoder state to define which configuration to use, enables easy implementation of for instance hysteresis, as different threshold values can be used for the same channel, depending on the state of the application. Table 21.1 (p. 334) summarizes how channel configuration is selected for different setting of SCANCONF. Table 21.1. LESENSE scan configuration selection SCANCONF LESENSE channel x DIRMAP INVMAP TOGGLE DECDEF SCANRES[n] = 0 SCANRES[n] = 1 DECSTATE < 8 DECSTATE >= 8 0 X ? VDD < X ? How? Interrupts The scaled power supply is compared to a programmable reference voltage, and an interrupt can be generated when the supply is higher or lower than the reference. The VCMP can also be duty-cycled by software to further reduce the energy consumption. GND 23.1 Introduction The Voltage Supply Comparator is used to monitor the supply voltage from software. An interrupt can be generated when the supply falls below or rises above a programmable threshold. Note Note that VCMP comes in addition to the Power-on Reset and Brown-out Detector peripherals, that both generate reset signals when the voltage supply is insufficient for reliable operation. VCMP does not generate reset, only interrupt. Also note that the ADC is capable of sampling the input voltage supply. 23.2 Features • • • • • • • • • • Voltage supply monitoring Scalable VDD in 64 steps selectable as positive comparator input Internal 1.25 V bandgap reference Low power mode for internal VDD and bandgap references Selectable hysteresis • 0 or ±20 mV Selectable response time Asynchronous interrupt generation on selectable edges • Rising edge • Falling edge • Rising and Falling edges Operational in EM0-EM3 Comparator output direct on PRS Configurable output when inactive to avoid unwanted interrupts 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 389 www.silabs.com ...the world's most energy friendly microcontrollers 23.3 Functional Description An overview of the VCMP is shown in Figure 23.1 (p. 390) . Figure 23.1. VCMP Overview Warm up interrupt TRIGLEVEL VDD EN Warm - up counter VCMPACT Edge interrupt Scaler 1 0 VCMPOUT INACTVAL BIASPROG HALFBIAS HYSTEN PRS LPREF Read/ Write registers 1.25V Read only register The comparator has two analog inputs, one positive and one negative. When the comparator is active, the output indicates which of the two input voltages is higher. When the voltage on the positive input is higher than the negative input voltage, the digital output is high and vice versa. The output of the comparator can be read in the VCMPOUT bit in VCMP_STATUS. Configuration registers should only be changed while the comparator is disabled. 23.3.1 Warm-up Time VCMP is enabled by setting the EN bit in VCMP_CTRL. When this bit is set, the comparator must stabilize before becoming active and the outputs can be used. This time period is called the warm-up time. The warm-up time is a configurable number of HFPERCLK cycles, set in WARMTIME, which should be set to at least 10 µs. When the comparator is enabled and warmed up, the VCMPACT bit in VCMP_STATUS will be set to indicate that the comparator is active. As long as the comparator is not enabled or not warmed up, VCMPACT will be cleared and the comparator output value is set to the value in INACTVAL in VCMP_CTRL. One should wait until the warm-up period is over before entering EM2 or EM3, otherwise no comparator interrupts will be detected. EM1 can still be entered during warm-up. After the warm-up period is completed, interrupts will be detected in EM2 and EM3. 23.3.2 Response Time There is a delay from when the actual input voltage changes polarity, to when the output toggles. This period is called the response time and can be altered by increasing or decreasing the bias current to the comparator through the BIAS and HALFBIAS fields in VCMP_CTRL as shown in Table 23.1 (p. 390) . Setting a lower bias current will result in lower power consumption, but a longer response time. Table 23.1. Bias Configuration BIAS Bias Current (µA) HALFBIAS=0 HALFBIAS=1 0b0000 0.1 0.05 0b0001 0.2 0.1 0b0010 0.4 0.2 0b0011 0.6 0.3 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 390 www.silabs.com ...the world's most energy friendly microcontrollers BIAS Bias Current (µA) HALFBIAS=0 HALFBIAS=1 0b0100 0.8 0.4 0b0101 1.0 0.5 0b0110 1.2 0.6 0b0111 1.4 0.7 0b1000 2.0 1.0 0b1001 2.2 1.1 0b1010 2.4 1.2 0b1011 2.6 1.3 0b1100 2.8 1.4 0b1101 3.0 1.5 0b1110 3.2 1.6 0b1111 3.4 1.7 23.3.3 Hysteresis In the voltage supply comparator, hysteresis can be enabled by setting HYSTEN in VCMP_CTRL. When HYSTEN is set, the digital output will not toggle until the positive input voltage is at least 20mV above or below the negative input voltage. This feature can be used to filter out uninteresting input fluctuations around zero and only show changes that are big enough to breach the hysteresis threshold. Figure 23.2. VCMP 20 mV Hysteresis Enabled In POS In NEG + 20m V In NEG In NEG - 20m V Tim e VCMPOUT without hysteresis VCMPOUT with hysteresis 23.3.4 Input Selection The positive comparator input is always connected to the scaled power supply input. The negative comparator input is connected to the internal 1.25 V bandgap reference. The VDD trigger level can be configured by setting the TRIGLEVEL field in VCMP_CTRL according to the following formula: VCMP VDD Trigger Level VDD Trigger Level= 1.667V + 0.034V × TRIGLEVEL (23.1) A low power reference mode can be enabled by setting the LPREF bit in VCMP_INPUTSEL. In this mode, the power consumption in the reference buffer (VDD and bandgap) is lowered at the cost of accuracy. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 391 www.silabs.com ...the world's most energy friendly microcontrollers 23.3.5 Interrupts and PRS Output The VCMP includes an edge triggered interrupt flag (EDGE in VCMP_IF). If either IRISE and/or IFALL in VCMPn_CTRL is set, the EDGE interrupt flag will be set on rising and/or falling edge of the comparator output respectively. An interrupt request will be sent if the EDGE interrupt flag in VCMP_IF is set and enabled through the EDGE bit in VCMPn_IEN. The edge interrupt can also be used to wake up the device from EM3-EM1. VCMP also includes an interrupt flag, WARMUP in VCMP_IF, which is set when a warm-up sequence has finished. An interrupt request will be sent if the WARMUP interrupt flag in VCMP_IF is set and enabled through the WARMUP bit in VCMPn_IEN. The synchronized comparator output is also available as a PRS output signal. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 392 www.silabs.com ...the world's most energy friendly microcontrollers 23.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 VCMP_CTRL RW Control Register 0x004 VCMP_INPUTSEL RW Input Selection Register 0x008 VCMP_STATUS R Status Register 0x00C VCMP_IEN RW Interrupt Enable Register 0x010 VCMP_IF R Interrupt Flag Register 0x014 VCMP_IFS W1 Interrupt Flag Set Register 0x018 VCMP_IFC W1 Interrupt Flag Clear Register 23.5 Register Description 23.5.1 VCMP_CTRL - Control Register Offset 0 0 RW EN 1 2 0 RW INACTVAL 3 4 RW HYSTEN 0 5 6 7 8 9 RW 0x0 WARMTIME 10 11 12 13 14 15 16 0 RW 17 RW 0 18 19 21 22 23 24 25 20 Access IRISE Name IFALL Access 26 RW 0x7 BIASPROG 27 28 29 30 1 RW Reset HALFBIAS 31 0x000 Bit Position Bit Name Reset Description 31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 30 HALFBIAS 1 RW Half Bias Current Set this bit to 1 to halve the bias current. Table 23.1 (p. 390) . 29:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 27:24 BIASPROG 0x7 RW VCMP Bias Programming Value These bits control the bias current level. Table 23.1 (p. 390) . 23:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 17 IFALL 0 RW Falling Edge Interrupt Sense Set this bit to 1 to set the EDGE interrupt flag on falling edges of comparator output. 16 IRISE 0 RW Rising Edge Interrupt Sense Set this bit to 1 to set the EDGE interrupt flag on rising edges of comparator output. 15:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 10:8 WARMTIME 0x0 RW Warm-Up Time Set warm-up time Value Mode Description 0 4CYCLES 4 HFPERCLK cycles 1 8CYCLES 8 HFPERCLK cycles 2 16CYCLES 16 HFPERCLK cycles 3 32CYCLES 32 HFPERCLK cycles 4 64CYCLES 64 HFPERCLK cycles 5 128CYCLES 128 HFPERCLK cycles 6 256CYCLES 256 HFPERCLK cycles 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 393 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description Value Mode Description 7 512CYCLES 512 HFPERCLK cycles 7:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 4 HYSTEN 0 RW Hysteresis Enable Enable hysteresis. Value Description 0 No hysteresis 1 +-20 mV hysteresis 3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 2 INACTVAL 0 RW Inactive Value Configure the output value when the comparator is inactive. 1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 0 EN 0 RW Voltage Supply Comparator Enable Enable/disable voltage supply comparator. 23.5.2 VCMP_INPUTSEL - Input Selection Register Name Access 0 1 RW TRIGLEVEL LPREF Access 2 3 0x00 4 5 6 7 RW 0 Reset 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x004 Bit Position 31 Offset Bit Name Reset Description 31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 8 LPREF 0 RW Low Power Reference Enable/disable low power mode for VDD and bandgap reference. When using this bit, always leave it as 0 during warm-up and then set it to 1 if desired when the warm-up is done. 7:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 5:0 TRIGLEVEL 0x00 RW Trigger Level Select VDD trigger level. Vtrig = 1.667V+0.034V×TRIGLEVEL. 23.5.3 VCMP_STATUS - Status Register 394 0 R VCMPACT 0 2 3 4 5 6 7 8 9 10 11 12 13 14 1 R Name VCMPOUT Access 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 15 0 Reset 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x008 Bit Position 31 Offset www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 1 VCMPOUT 0 R Voltage Supply Comparator Output R Voltage Supply Comparator Active Voltage supply comparator output value 0 VCMPACT 0 Voltage supply comparator active status. 23.5.4 VCMP_IEN - Interrupt Enable Register Offset WARMUP Name Access 0 0 RW Access EDGE RW 0 Reset 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x00C Bit Position Bit Name Reset Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 1 WARMUP 0 RW Warm-up Interrupt Enable RW Edge Trigger Interrupt Enable Enable/disable interrupt on finished warm-up. 0 EDGE 0 Enable/disable edge triggered interrupt. 23.5.5 VCMP_IF - Interrupt Flag Register Access 0 R R EDGE Name WARMUP Access 0 1 2 3 4 5 6 7 0 Reset 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x010 17 Bit Position Offset Bit Name Reset Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 1 WARMUP 0 R Warm-up Interrupt Flag R Edge Triggered Interrupt Flag Indicates that warm-up has finished. 0 EDGE 0 Indicates that there has been a rising and/or falling edge on the VCMP output. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 395 www.silabs.com ...the world's most energy friendly microcontrollers 23.5.6 VCMP_IFS - Interrupt Flag Set Register Offset WARMUP Name Access 0 0 W1 Access EDGE W1 0 Reset 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x014 Bit Position Bit Name Reset Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 1 WARMUP 0 W1 Warm-up Interrupt Flag Set W1 Edge Triggered Interrupt Flag Set Write to 1 to set warm-up finished interrupt flag 0 EDGE 0 Write to 1 to set edge triggered interrupt flag 23.5.7 VCMP_IFC - Interrupt Flag Clear Register Access 0 W1 W1 EDGE Name WARMUP Access 0 1 2 3 4 5 0 Reset 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x018 Bit Position 31 Offset Bit Name Reset Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 1 WARMUP 0 W1 Warm-up Interrupt Flag Clear Write to 1 to clear warm-up finished interrupt flag 0 EDGE 0 W1 Edge Triggered Interrupt Flag Clear Write to 1 to clear edge triggered interrupt flag 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 396 www.silabs.com ...the world's most energy friendly microcontrollers 24 ADC - Analog to Digital Converter Quick Facts What? The ADC is used to convert analog signals into a digital representation and features 8 external input channels 0 1 2 3 4 Why? In many applications there is a need to measure analog signals and record them in a digital representation, without exhausting your energy source. + ADC - ...0101110... How? A low power Successive Approximation Register ADC samples up to 8 input channels in a programmable sequence. With the help of PRS and DMA, the ADC can operate without CPU intervention, minimizing the number of powered up resources. The ADC can further be duty-cycled to reduce the energy consumption. 24.1 Introduction The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to one million samples per second. The integrated input mux can select inputs from 8 external pins and 6 internal signals. 24.2 Features • Programmable resolution (6/8/12-bit) • 13 prescaled clock (ADC_CLK) cycles per conversion • Maximum 1 MSPS @ 12-bit • Maximum 1.86 MSPS @ 6-bit • Configurable acquisition time • Integrated prescaler • Selectable clock division factor from 1 to 128 • 13 MHz to 32 kHz allowed for ADC_CLK • 18 input channels • 8 external single ended channels • 6 internal single ended channels • Including temperature sensor • 4 external differential channels • Integrated input filter • Low pass RC filter • Decoupling capacitor • Left or right adjusted results • Results in 2’s complement representation • Differential results sign extended to 32-bit results 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 397 www.silabs.com ...the world's most energy friendly microcontrollers • Programmable scan sequence • Up to 8 configurable samples in scan sequence • Mask to select which pins are included in the sequence • Triggered by software or PRS input • One shot or repetitive mode • Oversampling available • Overflow interrupt flag set when overwriting unread results • Conversion tailgating support for predictable periodic scans • Programmable single conversion • Triggered by software or PRS input • Can be interleaved between two scan sequences • One shot or repetitive mode • Oversampling available • Overflow interrupt flag set when overwriting unread results • Hardware oversampling support • 1st order accumulate and dump filter • From 2 to 4096 oversampling ratio (OSR) • Results in 16-bit representation • Enabled individually for scan sequence and single sample mode • Common OSR select • Individually selectable voltage reference for scan and single mode • Internal 1.25V reference • Internal 2.5V reference • VDD • Internal 5 V differential reference • Single ended external reference • Differential external reference • Unbuffered 2xVDD • Support for offset and gain calibration • Interrupt generation and/or DMA request • Finished single conversion • Finished scan conversion • Single conversion results overflow • Scan sequence results overflow • Loopback configuration with DAC output measurement 24.3 Functional Description An overview of the ADC is shown in Figure 24.1 (p. 399) . 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 398 www.silabs.com ...the world's most energy friendly microcontrollers Figure 24.1. ADC Overview ADCn_CTRL ADCn_SINGLEDATA ADCn_CMD ADCn_SCANDATA ADCn_SINGLECTRL ADCn_STATUS HFPERCLKADCn Prescaler ADCn_SCANCTRL Oversam pling filter Sequencer ADC_CLK ADCn_CH0 ADCn_CH1 ADCn_CH2 ADCn_CH3 ADCn_CH4 ADCn_CH5 ADCn_CH6 ADCn_CH7 Result buffer Control + SAR - Tem p VDD/ 3 VDD VSS Vref / 2 DAC0/ OPA0 DAC1/ OPA1 VDD 1.25 V 2.5 V 5 V differential 2x (VDD- VSS) 24.3.1 Clock Selection The ADC has an internal prescaler (PRESC bits in ADCn_CTRL) which can divide the peripheral clock (HFPERCLK) by any factor between 1 and 128. Note that the resulting ADC_CLK should not be set to a higher frequency than 13 MHz and not lower than 32 kHz. 24.3.2 Conversions A conversion consists of two phases. The input is sampled in the acquisition phase before it is converted to digital representation during the approximation phase. The acquisition time can be configured independently for scan and single conversions (see Section 24.3.7 (p. 403) ) by setting AT in ADCn_SINGLECTRL/ADCn_SCANCTRL. The acquisition times can be set to any integer power of 2 from 1 to 256 ADC_CLK cycles. Note For high impedance sources the acquisition time should be adjusted to allow enough time for the internal sample capacitor to fully charge. The minimum acquisition time for the internal temperature sensor and Vdd/3 is given in the electrical characteristics for the device. The analog to digital converter core uses one clock cycle per output bit in the approximation phase. ADC Total Conversion Time (in ADC_CLK cycles) Per Output Tconv= (TA+N) x OSR (24.1) TA equals the number of acquisition cycles and N is the resolution. OSR is the oversampling ratio (see Section 24.3.7.7 (p. 405) ). The minimum conversion time is 7 ADC_CYCLES with 6 bit resolution and 13 ADC_CYCLES with 12 bit resolution. The maximum conversion time is 1097728 ADC_CYCLES with the longest acquisition time, 12 bit resolution and highest oversampling rate. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 399 www.silabs.com ...the world's most energy friendly microcontrollers Figure 24.2. ADC Conversion Timing HFPERCLKADCn Prescaled clock (4x ) ADC action SINGLEAT/ SCANAT Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 6- bit value ready Bit 4 Bit 3 8- bit value ready Bit 2 Bit 1 Bit 0 12- bit value ready 24.3.3 Warm-up Time The ADC needs to be warmed up some time before a conversion can take place. This time period is called the warm-up time. When enabling the ADC or changing references between samples, the ADC is automatically warmed up for 1µs and an additional 5 µs if the bandgap is selected as reference. Normally, the ADC will be warmed up only when samples are requested and is shut off when there are no more samples waiting. However, if lower latency is needed, configuring the WARMUPMODE field in ADCn_CTRL allows the ADC and/or reference to stay warm between samples, eliminating the need for warm-up. Figure 24.3 (p. 401) shows the analog power consumption in scenarios using the different WARMUPMODE settings. Only the bandgap reference selected for scan mode can be kept warm. If a different bandgap reference is selected for single mode, the warm-up time still applies. • NORMAL: ADC and references are shut off when there are no samples waiting. a) in Figure 24.3 (p. 401) shows this mode used with an internal bandgap reference. Figure d) shows this mode when using VDD or an external reference. • FASTBG: Bandgap warm-up is eliminated, but with reduced reference accuracy. d) in Figure 24.3 (p. 401) shows this mode used with an internal bandgap reference. • KEEPSCANREFWARM: The reference selected for scan mode is kept warm. The ADC will still need to be warmed up before conversion. b) in Figure 24.3 (p. 401) shows this mode used with an internal bandgap reference. • KEEPADCWARM: The ADC and the reference selected for scan mode is kept warm. c) in Figure 24.3 (p. 401) shows this mode used with an internal bandgap reference. The minimum warm-up times are given in µs. The timing is done automatically by the ADC, given that a proper time base is given in the TIMEBASE bits in ADCn_CTRL. The TIMEBASE must be set to the number of HFPERCLK which corresponds to at least 1 µs. The TIMEBASE only affects the timing of the warm-up sequence and not the ADC_CLK. When entering Energy Modes 2 or 3, the ADC must be stopped and WARMUPMODE in ADCn_CTRL written to 0. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 400 www.silabs.com ...the world's most energy friendly microcontrollers Figure 24.3. ADC Analog Power Consumption With Different WARMUPMODE Settings Bandgap reference warm - up ADC warm - up ADC conversion ADC enabled Conversion trigger Conversion trigger Power a) NORMAL 5 µs Tim e 1 µs Power 1 µs KEEPSCANREFWARM b) 5 µs (w SCANREF = internal bandgap) Tim e Power KEEPADCWARM c) 5 µs (w SCANREF = internal bandgap) FASTBG (w SCANREF = any) or Power NORMAL d) (w SCANREF = external or VDD) Tim e 24.3.4 Input Selection The ADC is connected to 8 external input pins, which can be selected as 8 different single ended inputs or 4 differential inputs. In addition, 6 single ended internal inputs can be selected. The available selections are given in the register description for ADCn_SINGLECTRL and ADCn_SCANCTRL. For offset calibration purposes it is possible to internally short the differential ADC inputs and thereby measure a 0 V differential. Differential 0 V is selected by writing the DIFF bit to 1 and INPUTSEL to 4 in ADCn_SINGLECTRL. Calibration is described in detail in Section 24.3.10 (p. 406) . Note When VDD/3 is sampled, the acquisition time should be above a lower limit. The reader is referred to the datasheet for minimum VDD/3 acquisition time. 24.3.4.1 Input Filtering The selected input signal can be filtered, either through an internal low pass RC filter or an internal decoupling capacitor. The different filter configurations can be enabled through the LPFMODE bits in ADCn_CTRL. For maximum SNR, LPFMODE is recommended set to DECAP, with a cutoff frequency of 31.5 MHz. The RC input filter configuration is given in Figure 24.4 (p. 402) . The resistance and capacitance values are given in the electrical characteristics for the device, named RADCFILT and CADCFILT respectively. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 401 www.silabs.com ...the world's most energy friendly microcontrollers Figure 24.4. ADC RC Input Filter Configuration Input ADC R C 24.3.4.2 Temperature Measurement The ADC includes an internal temperature sensor. This sensor is characterized during production and the temperature readout from the ADC at production temperature, ADC0_TEMP_0_READ_1V25, is given in the Device Information (DI) page. The production temperature, CAL_TEMP_0, is also given in this page. The temperature gradient, TGRAD_ADCTH (mV/degree Celsius), for the sensor is found in the datasheet for the devices. By selecting 1.25 V internal reference and measuring the internal temperature sensor with 12 bit resolution, the temperature can be calculated according to the following formula: ADC Temperature Measurement TCELSIUS=CAL_TEMP_0-(ADC0_TEMP_0_READ_1V25ADC_result)×Vref/(4096×TGRAD_ADCTH) (24.2) Note The minimum acquisition time for the temperature reference is found in the electrical characteristics for the device. 24.3.5 Reference Selection The reference voltage can be selected from these sources: • • • • • • • • • 1.25 V internal bandgap. 2.5 V internal bandgap. VDD. 5 V internal differential bandgap. External single ended input from Ch. 6. Differential input, 2x(Ch. 6 - Ch. 7). Unbuffered 2xVDD. The 2.5 V reference needs a supply voltage higher than 2.5 V. The differential 5 V reference needs a supply voltage higher than 2.75 V. Since the 2xVDD differential reference is unbuffered, it is directly connected to the ADC supply voltage and more susceptible to supply noise. The VDD reference is buffered both in single ended and differential mode. If a differential reference with a larger range than the supply voltage is combined with single ended measurements, for instance the 5 V internal reference, the full ADC range will not be available because the maximum input voltage is limited by the maximum electrical ratings. Note Single ended measurements with the external differential reference are not supported. 24.3.6 Programming of Bias Current The bias current of the bandgap reference and the ADC comparator can be scaled by the BIASPROG, HALFBIAS and COMPBIAS bit fields of the ADCn_BIASPROG register. The BIASPROG and HALFBIAS 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 402 www.silabs.com ...the world's most energy friendly microcontrollers bitfields scale the current of ADC bandgap reference, and the COMPBIAS bits provide an additional bias programming for the ADC comparator as illustrated in Figure 24.5 (p. 403) . The electrical characteristics given in the datasheet require the bias configuration to be set to the default values, where no other bias values are given. Figure 24.5. ADC Bias Programming Reference Current BIASPROG HALFBIAS COMPBIAS Internal bandgap reference ADC Com parator The minimum value of the BIASPROG and COMPBIAS bitfields of the ADCn_BIASPROG register (i.e. BIASPROG=0b0000, COMPBIAS=0b0000) represent the minimum bias currents. Similarly BIASPROG=0b1111 and COMPBIAS=0b1111 represent the maximum bias currents. Additionally, the bias current defined by the BIASPROG setting can be halved by setting the HALFBIAS bit of the ADCn_BIASPROG register. The bias current settings should only be changed while the ADC is disabled. 24.3.7 ADC Modes The ADC contains two separate programmable modes, one single sample mode and one scan mode. Both modes have separate configuration and result registers and can be set up to run only once per trigger or repetitively. The scan mode has priority over the single sample mode. However, if scan sequence is running, a triggered single sample will be interleaved between two scan samples. 24.3.7.1 Single Sample Mode The single sample mode can be used to convert a single sample either once per trigger or repetitively. The configuration of the single sample mode is done in the ADCn_SINGLECTRL register and the results are found in the ADCn_SINGLEDATA register. The SINGLEDV bit in ADCn_STATUS is set high when there is valid data in the result register and is cleared when the data is read. The single mode results can also be read through ADCn_SINGLEDATAP without SINGLEDV being cleared. DIFF in ADCn_SINGLECTRL selects whether differential or single ended inputs are used and INPUTSEL selects input pin(s). 24.3.7.2 Scan mode The scan mode is used to perform sweeps of the inputs. The configuration of the scan sequence is done in the ADCn_SCANCTRL register and the results are found in the ADCn_SCANDATA register. The SCANDV bit in ADCn_STATUS is set high when there is valid data in the result register and is cleared when the data is read. The scan mode results can also be read through ADCn_SCANDATAP without SCANDV being cleared. The inputs included in the sequence are defined by a the mask in INPUTMASK in ADCn_SCANCTRL. When the scan sequence is triggered, the sequence samples all inputs that are included in the mask, starting at the lowest pin number. DIFF in ADCn_SCANCTRL selects whether single ended or differential inputs are used. 24.3.7.3 Conversion Tailgating The scan sequence has priority over the single sample mode. However, a scan trigger will not interrupt in the middle of a single conversion. If a scan sequence is triggered by a timer on a periodic basis, 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 403 www.silabs.com ...the world's most energy friendly microcontrollers single sample just before a scan trigger can delay the start of the scan sequence, thus causing jitter in sample rate. To solve this, conversion tailgating can be chosen by setting TAILGATE in ADCn_CTRL. When this bit is set, any triggered single samples will wait for the next scan sequence to finish before activating (see Figure 24.6 (p. 404) ). The single sample will then follow immediately after the scan sequence. In this way, the scan sequence will always start immediately when triggered, if the period between the scan triggers is big enough to allow any single samples that might be triggered to finish in between the scan sequences. Figure 24.6. ADC Conversion Tailgating ADC action Scan Single Scan Single Scan SCANSTART SINGLESTART SCANACT SINGLEACT 24.3.7.4 Conversion Trigger The conversion modes can be activated by writing a 1 to the SINGLESTART or SCANSTART bit in the ADCn_CMD register. The conversions can be stopped by writing a 1 to the SINGLESTOP or SCANSTOP bit in the ADCn_CMD register. A START command will have priority over a stop command. When the ADC is stopped in the middle of a conversion, the result buffer is cleared. The SINGLEACT and SCANACT bits in ADCn_STATUS are set high when the modes are actively converting or have pending conversions. It is also possible to trigger conversions from PRS signals. The system requires one HFPERCLK cycle pulses to trigger conversions. Setting PRSEN in ADCn_SINGLECTRL/ADCn_SCANCTRL enables triggering from PRS input. Which PRS channel to listen to is defined by PRSSEL in ADCn_SINGLECTRL/ADCn_SCANCTRL. When PRS trigger is selected, it is still possible to trigger the conversion from software. The reader is referred to the PRS datasheet for more information on how to set up the PRS channels. Note The conversion settings should not be changed while the ADC is running as this can lead to unpredictable behavior. The prescaled clock phase is always reset by a triggered conversion as long as a conversion is not ongoing. This gives predictable latency from the time of the trigger to the time the conversion starts, regardless of when in the prescaled clock cycle the trigger occur. 24.3.7.5 Results The results are presented in 2’s complement form and the format for differential and single ended mode is given in Table 24.1 (p. 404) and Table 24.2 (p. 405) . If differential mode is selected, the results are sign extended up to 32-bit (shown in Table 24.4 (p. 406) ). Table 24.1. ADC Single Ended Conversion Results Input/Reference Binary Hex value 1 111111111111 FFF 0.5 011111111111 7FF 1/4096 000000000001 001 0 000000000000 000 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 404 www.silabs.com ...the world's most energy friendly microcontrollers Table 24.2. ADC Differential Conversion Results Input/Reference Binary Hex value 0.5 011111111111 7FF 0.25 001111111111 3FF 1/2048 000000000001 001 0 000000000000 000 -1/2048 111111111111 FFF -0.25 101111111111 BFF -0.5 100000000000 800 24.3.7.6 Resolution The ADC gives out 12-bit results, by default. However, if full 12-bit resolution is not needed, it is possible to speed up the conversion by selecting a lower resolution (N = 6 or 8 bits). For more information on the accuracy of the ADC, the reader is referred to the electrical characteristics section for the device. 24.3.7.7 Oversampling To achieve higher accuracy, hardware oversampling can be enabled individually for each mode (Set RES in ADCn_SINGLECTRL/ADCn_SCANCTRL to 0x3). The oversampling rate (OVSRSEL in ADCn_CTRL) can be set to any integer power of 2 from 2 to 4096 and the configuration is shared between the scan and single sample mode (OVSRSEL field in ADCn_CTRL). With oversampling, each selected input is sampled a number (given by the OVSR) of times, and the results are filtered by a first order accumulate and dump filter to form the end result. The data presented in the ADCn_SINGLEDATA and ADCn_SCANDATA registers are the direct contents of the accumulation register (sum of samples). However, if the oversampling ratio is set higher than 16x, the accumulated results are shifted to fit the MSB in bit 15 as shown in Table 24.3 (p. 405) . Table 24.3. Oversampling Result Shifting and Resolution Oversampling setting # right shifts Result Resolution # bits 2x 0 13 4x 0 14 8x 0 15 16x 0 16 32x 1 16 64x 2 16 128x 3 16 256x 4 16 512x 5 16 1024x 6 16 2048x 7 16 4096x 8 16 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 405 www.silabs.com ...the world's most energy friendly microcontrollers 24.3.7.8 Adjustment By default, all results are right adjusted, with the LSB of the result in bit position 0 (zero). In differential mode the signed bit is extended up to bit 31, but in single ended mode the bits above the result are read as 0. By setting ADJ in ADCn_SINGLECTRL/ADCn_SCANCTRL, the results are left adjusted as shown in Table 24.4 (p. 406) . When left adjusted, the MSB is always placed on bit 15 and sign extended to bit 31. All bits below the conversion result are read as 0 (zero). Left Right Resolution Adjustment Table 24.4. ADC Results Representation Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 12 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 10 9 8 7 6 5 4 3 2 1 0 8 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 5 4 3 2 1 0 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 3 2 1 0 OVS 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 12 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 10 9 8 7 6 5 4 3 2 1 0 - - - - 8 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 5 4 3 2 1 0 - - - - - - - - 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 3 2 1 0 - - - - - - - - - - OVS 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 24.3.8 Interrupts, PRS Output The single and scan modes have separate interrupt flags indicating finished conversions. Setting one of these flags will result in an ADC interrupt if the corresponding interrupt enable bit is set in ADCn_IEN. In addition to the finished conversion flags, there is a scan and single sample result overflow flag which signalizes that a result from a scan sequence or single sample has been overwritten before being read. A finished conversion will result in a one HFPERCLK cycle pulse which is output to the Peripheral Reflex System (PRS). 24.3.9 DMA Request The ADC has two DMA request lines, SINGLE and SCAN, which are set when a single or scan conversion has completed. The request are cleared when the corresponding single or scan result register is read. 24.3.10 Calibration The ADC supports offset and gain calibration to correct errors due to process and temperature variations. This must be done individually for each reference used. The ADC calibration (ADCn_CAL) register contains four register fields for calibrating offset and gain for both single and scan mode. The gain and offset calibration are done in single mode, but the resulting calibration values can be used for both single and scan mode. Gain and offset for the 1V25, 2V5 and VDD references are calibrated during production and the calibration values for these can be found in the Device Information page. During reset, the gain and offset calibration registers are loaded with the production calibration values for the 1V25 reference. The SCANGAIN and SINGLEGAIN calibration fields are not used when the unbuffered differential 2xVDD reference is selected. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 406 www.silabs.com ...the world's most energy friendly microcontrollers The effects of changing the calibration register values are given in Table 24.5 (p. 407) . Step by step calibration procedures for offset and gain are given in Section 24.3.10.1 (p. 407) and Section 24.3.10.2 (p. 407) . Table 24.5. Calibration Register Effect Calibration Register ADC Result Calibration Binary Value Calibration Hex Value Lowest Output 0111111 3F Highest Output 1000000 40 Lowest Output 0000000 00 Highest Output 1111111 7F Offset Gain The offset calibration register expects a signed 2’s complement value with negative effect. A high value gives a low ADC reading. The gain calibration register expects an unsigned value with positive effect. A high value gives a high ADC reading. 24.3.10.1 Offset Calibration Offset calibration must be performed prior to gain calibration. Follow these steps for the offset calibration in single mode: 1. Select wanted reference by setting the REF bitfield of the ADCn_SINGLECTRL register. 2. Set the AT bitfield of the ADCn_SINGLECTRL register to 16CYCLES. 3. Set the INPUTSEL bitfield of the ADCn_SINGLECTRL register to DIFF0, and set the DIFF bitfield to 1 for enabling differential input. Since the input voltage is 0, the expected ADC output is the half of the ADC code range as it is in differential mode. 4. A binary search is used to find the offset calibration value. Set the SINGLESTART bit in the ADCn_CMD register and read the ADCn_SINGLEDATA register. The result of the binary search is written to the SINGLEOFFSET field of the ADCn_CAL register. 24.3.10.2 Gain Calibration Offset calibration must be performed prior to gain calibration. The Gain Calibration is done in the following manner: 1. Select an external ADC channel (a differential channel can also be used). 2. Apply an external voltage on the selected ADC input channel. This voltage should correspond to the top of the ADC range. 3. A binary search is used to find the gain calibration value. Set the SINGLESTART bit in the ADCn_CTRL register and read the ADCn_SINGLEDATA register. The target value is ideally the top of the ADC range, but it is recommended to use a value a couple of LSBs below in order to avoid overshooting. The result of the binary search is written to the SINGLEGAIN field of the ADCn_CAL register. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 407 www.silabs.com ...the world's most energy friendly microcontrollers 24.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 ADCn_CTRL RW Control Register 0x004 ADCn_CMD W1 Command Register 0x008 ADCn_STATUS R Status Register 0x00C ADCn_SINGLECTRL RW Single Sample Control Register 0x010 ADCn_SCANCTRL RW Scan Control Register 0x014 ADCn_IEN RW Interrupt Enable Register 0x018 ADCn_IF R Interrupt Flag Register 0x01C ADCn_IFS W1 Interrupt Flag Set Register 0x020 ADCn_IFC W1 Interrupt Flag Clear Register 0x024 ADCn_SINGLEDATA R Single Conversion Result Data 0x028 ADCn_SCANDATA R Scan Conversion Result Data 0x02C ADCn_SINGLEDATAP R Single Conversion Result Data Peek Register 0x030 ADCn_SCANDATAP R Scan Sequence Result Data Peek Register 0x034 ADCn_CAL RW Calibration Register 0x03C ADCn_BIASPROG RW Bias Programming Register 24.5 Register Description 24.5.1 ADCn_CTRL - Control Register Access 0 1 0x0 RW WARMUPMODE 2 3 RW TAILGATE 0 4 5 0x0 RW LPFMODE 6 7 8 9 10 11 RW 0x00 12 13 14 15 16 17 PRESC Name TIMEBASE OVSRSEL Access RW RW Reset 18 0x1F 19 20 21 22 23 24 25 26 0x0 27 28 29 30 0x000 Bit Position 31 Offset Bit Name Reset Description 31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 27:24 OVSRSEL 0x0 RW Oversample Rate Select Select oversampling rate. Oversampling must be enabled for each mode for this setting to take effect. Value Mode Description 0 X2 2 samples for each conversion result 1 X4 4 samples for each conversion result 2 X8 8 samples for each conversion result 3 X16 16 samples for each conversion result 4 X32 32 samples for each conversion result 5 X64 64 samples for each conversion result 6 X128 128 samples for each conversion result 7 X256 256 samples for each conversion result 8 X512 512 samples for each conversion result 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 408 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description Value Mode Description 9 X1024 1024 samples for each conversion result 10 X2048 2048 samples for each conversion result 11 X4096 4096 samples for each conversion result 23:21 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 20:16 TIMEBASE 0x1F RW Time Base Set time base used for ADC warm up sequence according to the HFPERCLK frequency. The time base is defined as a number of HFPERCLK cycles which should be set equal to or higher than 1us. Value Description TIMEBASE ADC warm-up is set to TIMEBASE+1 HFPERCLK clock cycles and bandgap warm-up is set to 5x(TIMEBASE+1) HFPERCLK cycles. 15 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 14:8 PRESC 0x00 RW Prescaler Setting Select clock division factor. Value Description PRESC Clock division factor of PRESC+1. 7:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 5:4 LPFMODE 0x0 RW Low Pass Filter Mode These bits control the filtering of the ADC input. Details on the filter characteristics can be found in the device datasheets. 3 Value Mode Description 0 BYPASS No filter or decoupling capacitor 1 DECAP On chip decoupling capacitor selected 2 RCFILT On chip RC filter selected TAILGATE 0 RW Conversion Tailgating Enable/disable conversion tailgating. Value Description 0 Scan sequence has priority, but can be delayed by ongoing single samples. 1 Scan sequence has priority and single samples will only start immediately after scan sequence. 2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 1:0 WARMUPMODE 0x0 RW Warm-up Mode Select Warm-up Mode for ADC Value Mode Description 0 NORMAL ADC is shut down after each conversion 1 FASTBG Bandgap references do not need warm up, but have reduced accuracy. 2 KEEPSCANREFWARM Reference selected for scan mode is kept warm. 3 KEEPADCWARM ADC is kept warmed up and scan reference is kept warm 24.5.2 ADCn_CMD - Command Register Offset 409 0 W1 SINGLESTART 0 1 2 W1 0 W1 SCANSTART SINGLESTOP 0 4 5 6 7 8 9 10 11 12 13 14 3 W1 Name SCANSTOP Access 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 15 0 Reset 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x004 Bit Position www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 3 SCANSTOP 0 W1 Scan Sequence Stop W1 Scan Sequence Start W1 Single Conversion Stop W1 Single Conversion Start Write a 1 to stop scan sequence. 2 SCANSTART 0 Write a 1 to start scan sequence. 1 SINGLESTOP 0 Write a 1 to stop single conversion. 0 SINGLESTART 0 Write to 1 to start single conversion. 24.5.3 ADCn_STATUS - Status Register 0 R SINGLEACT 0 2 1 R SCANACT 0 3 4 5 6 7 8 R SINGLEREFWARM 0 9 R SCANREFWARM 0 10 11 12 13 R WARM 0 14 15 16 0 0 Access R Name SCANDV SCANDATASRC R Access R Reset SINGLEDV 17 18 19 20 21 22 23 24 25 26 0x0 27 28 29 30 0x008 Bit Position 31 Offset Bit Name Reset Description 31:27 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 26:24 SCANDATASRC 0x0 R Scan Data Source This value indicates from which input channel the results in the ADCn_SCANDATA register originates. Value Mode Description 0 CH0 Single ended mode: SCANDATA result originates from ADCn_CH0. Differential mode: SCANDATA result originates from ADCn_CH0-ADCn_CH1 1 CH1 Single ended mode: SCANDATA result originates from ADCn_CH1. Differential mode: SCANDATA result originates from ADCn_CH2_ADCn_CH3 2 CH2 Single ended mode: SCANDATA result originates from ADCn_CH2. Differential mode: SCANDATA result originates from ADCn_CH4-ADCn_CH5 3 CH3 Single ended mode: SCANDATA result originates from ADCn_CH3. Differential mode: SCANDATA result originates from ADCn_CH6-ADCn_CH7 4 CH4 SCANDATA result originates from ADCn_CH4 5 CH5 SCANDATA result originates from ADCn_CH5 6 CH6 SCANDATA result originates from ADCn_CH6 7 CH7 SCANDATA result originates from ADCn_CH7 23:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 17 SCANDV 0 R Scan Data Valid R Single Sample Data Valid Scan conversion data is valid. 16 SINGLEDV 0 Single conversion data is valid. 15:13 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 12 WARM 0 R ADC Warmed Up ADC is warmed up. 11:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 9 SCANREFWARM 0 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 R Scan Reference Warmed Up 410 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description Reference selected for scan mode is warmed up. 8 SINGLEREFWARM 0 R Single Reference Warmed Up Reference selected for single mode is warmed up. 7:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 1 SCANACT 0 R Scan Conversion Active Scan sequence is active or has pending conversions. 0 SINGLEACT 0 R Single Conversion Active Single conversion is active or has pending conversions. 24.5.4 ADCn_SINGLECTRL - Single Sample Control Register Access 0 0 RW REP 2 1 0 RW 0 RW ADJ DIFF 3 4 5 RW 0x0 RES 6 7 8 9 10 INPUTSEL RW 0x0 11 12 13 14 15 17 RW 0x0 18 19 21 22 20 REF 0 RW 0x0 AT Name PRSEN PRSSEL Access RW Reset 23 24 25 26 27 28 29 30 RW 0x0 31 0x00C 16 Bit Position Offset Bit Name Reset Description 31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 30:28 PRSSEL 0x0 RW Single Sample PRS Trigger Select Select PRS trigger for single sample. Value Mode Description 0 PRSCH0 PRS ch 0 triggers single sample 1 PRSCH1 PRS ch 1 triggers single sample 2 PRSCH2 PRS ch 2 triggers single sample 3 PRSCH3 PRS ch 3 triggers single sample 4 PRSCH4 PRS ch 4 triggers single sample 5 PRSCH5 PRS ch 5 triggers single sample 6 PRSCH6 PRS ch 6 triggers single sample 7 PRSCH7 PRS ch 7 triggers single sample 27:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 24 PRSEN 0 RW Single Sample PRS Trigger Enable Enabled/disable PRS trigger of single sample. 23:20 Value Description 0 Single sample is not triggered by PRS input 1 Single sample is triggered by PRS input selected by PRSSEL AT 0x0 RW Single Sample Acquisition Time Select the acquisition time for single sample. Value Mode Description 0 1CYCLE 1 ADC_CLK cycle acquisition time for single sample 1 2CYCLES 2 ADC_CLK cycles acquisition time for single sample 2 4CYCLES 4 ADC_CLK cycles acquisition time for single sample 3 8CYCLES 8 ADC_CLK cycles acquisition time for single sample 4 16CYCLES 16 ADC_CLK cycles acquisition time for single sample 5 32CYCLES 32 ADC_CLK cycles acquisition time for single sample 6 64CYCLES 64 ADC_CLK cycles acquisition time for single sample 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 411 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description Value Mode Description 7 128CYCLES 128 ADC_CLK cycles acquisition time for single sample 8 256CYCLES 256 ADC_CLK cycles acquisition time for single sample 19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 18:16 REF 0x0 RW Single Sample Reference Selection Select reference to ADC single sample mode. Value Mode Description 0 1V25 Internal 1.25 V reference 1 2V5 Internal 2.5 V reference 2 VDD Buffered VDD 3 5VDIFF Internal differential 5 V reference 4 EXTSINGLE Single ended external reference from pin 6 5 2XEXTDIFF Differential external reference, 2x(pin 6 - pin 7) 6 2XVDD Unbuffered 2xVDD 15:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 11:8 INPUTSEL 0x0 RW Single Sample Input Selection Select input to ADC single sample mode in either single ended mode or differential mode. DIFF = 0 Mode Value Description CH0 0 ADCn_CH0 CH1 1 ADCn_CH1 CH2 2 ADCn_CH2 CH3 3 ADCn_CH3 CH4 4 ADCn_CH4 CH5 5 ADCn_CH5 CH6 6 ADCn_CH6 CH7 7 ADCn_CH7 TEMP 8 Temperature reference VDDDIV3 9 VDD/3 VDD 10 VDD VSS 11 VSS VREFDIV2 12 VREF/2 DAC0OUT0 13 DAC0 output 0 DAC0OUT1 14 DAC0 output 1 Mode Value Description CH0CH1 0 Positive input: ADCn_CH0 Negative input: ADCn_CH1 CH2CH3 1 Positive input: ADCn_CH2 Negative input: ADCn_CH3 CH4CH5 2 Positive input: ADCn_CH4 Negative input: ADCn_CH5 CH6CH7 3 Positive input: ADCn_CH6 Negative input: ADCn_CH7 DIFF0 4 Differential 0 (Short between positive and negative inputs) DIFF = 1 7:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 5:4 RES 0x0 RW Single Sample Resolution Select Select single sample conversion resolution. 3 Value Mode Description 0 12BIT 12-bit resolution 1 8BIT 8-bit resolution 2 6BIT 6-bit resolution 3 OVS Oversampling enabled. Oversampling rate is set in OVSRSEL Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 412 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description 2 ADJ 0 RW Single Sample Result Adjustment Select single sample result adjustment. 1 Value Mode Description 0 RIGHT Results are right adjusted 1 LEFT Results are left adjusted DIFF 0 RW Single Sample Differential Mode RW Single Sample Repetitive Mode Select single ended or differential input. 0 Value Description 0 Single ended input 1 Differential input REP 0 Enable/disable repetitive single samples. Value Description 0 Single conversion mode is deactivated after one conversion 1 Single conversion mode is converting continuously until SINGLESTOP is written 24.5.5 ADCn_SCANCTRL - Scan Control Register 0 RW REP 0 2 1 0 RW 0 RW ADJ DIFF 3 4 5 0x0 RW RES 6 7 8 9 10 11 RW INPUTMASK REF Access 12 0x00 13 14 15 17 RW 0x0 18 19 20 21 22 0x0 RW 0 AT Name RW PRSSEL Access PRSEN RW Reset 23 24 25 26 27 28 29 30 0x0 31 0x010 16 Bit Position Offset Bit Name Reset Description 31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 30:28 PRSSEL 0x0 RW Scan Sequence PRS Trigger Select Select PRS trigger for scan sequence. Value Mode Description 0 PRSCH0 PRS ch 0 triggers scan sequence 1 PRSCH1 PRS ch 1 triggers scan sequence 2 PRSCH2 PRS ch 2 triggers scan sequence 3 PRSCH3 PRS ch 3 triggers scan sequence 4 PRSCH4 PRS ch 4 triggers scan sequence 5 PRSCH5 PRS ch 5 triggers scan sequence 6 PRSCH6 PRS ch 6 triggers scan sequence 7 PRSCH7 PRS ch 7 triggers scan sequence 27:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 24 PRSEN 0 RW Scan Sequence PRS Trigger Enable Enabled/disable PRS trigger of scan sequence. 23:20 Value Description 0 Scan sequence is not triggered by PRS input 1 Scan sequence is triggered by PRS input selected by PRSSEL AT 0x0 RW Scan Sample Acquisition Time Select the acquisition time for scan samples. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 413 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description Value Mode Description 0 1CYCLE 1 ADC_CLK cycle acquisition time for scan samples 1 2CYCLES 2 ADC_CLK cycles acquisition time for scan samples 2 4CYCLES 4 ADC_CLK cycles acquisition time for scan samples 3 8CYCLES 8 ADC_CLK cycles acquisition time for scan samples 4 16CYCLES 16 ADC_CLK cycles acquisition time for scan samples 5 32CYCLES 32 ADC_CLK cycles acquisition time for scan samples 6 64CYCLES 64 ADC_CLK cycles acquisition time for scan samples 7 128CYCLES 128 ADC_CLK cycles acquisition time for scan samples 8 256CYCLES 256 ADC_CLK cycles acquisition time for scan samples 19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 18:16 REF 0x0 RW Scan Sequence Reference Selection Select reference to ADC scan sequence. 15:8 Value Mode Description 0 1V25 Internal 1.25 V reference 1 2V5 Internal 2.5 V reference 2 VDD VDD 3 5VDIFF Internal differential 5 V reference 4 EXTSINGLE Single ended external reference from pin 6 5 2XEXTDIFF Differential external reference, 2x(pin 6 - pin 7) 6 2XVDD Unbuffered 2xVDD INPUTMASK 0x00 RW Scan Sequence Input Mask Set one or more bits in this mask to select which inputs are included the scan sequence in either single ended or differential mode. DIFF = 0 Mode Value Description CH0 00000001 ADCn_CH0 included in mask CH1 00000010 ADCn_CH1 included in mask CH2 00000100 ADCn_CH2 included in mask CH3 00001000 ADCn_CH3 included in mask CH4 00010000 ADCn_CH4 included in mask CH5 00100000 ADCn_CH5 included in mask CH6 01000000 ADCn_CH6 included in mask CH7 10000000 ADCn_CH7 included in mask Mode Value Description CH0CH1 00000001 (Positive input: ADCn_CH0 Negative input: ADCn_CH1) included in mask CH2CH3 00000010 (Positive input: ADCn_CH2 Negative input: ADCn_CH3) included in mask CH4CH5 00000100 (Positive input: ADCn_CH4 Negative input: ADCn_CH5) included in mask CH6CH7 00001000 (Positive input: ADCn_CH6 Negative input: ADCn_CH7) included in mask 0001xxxx-1111xxxx Reserved DIFF = 1 7:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 5:4 RES 0x0 RW Scan Sequence Resolution Select Select scan sequence conversion resolution. 3 Value Mode Description 0 12BIT 12-bit resolution 1 8BIT 8-bit resolution 2 6BIT 6-bit resolution 3 OVS Oversampling enabled. Oversampling rate is set in OVSRSEL Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 414 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description 2 ADJ 0 RW Scan Sequence Result Adjustment Select scan sequence result adjustment. 1 Value Mode Description 0 RIGHT Results are right adjusted 1 LEFT Results are left adjusted DIFF 0 RW Scan Sequence Differential Mode RW Scan Sequence Repetitive Mode Select single ended or differential input. 0 Value Description 0 Single ended input 1 Differential input REP 0 Enable/disable repetitive scan sequence. Value Description 0 Scan conversion mode is deactivated after one sequence 1 Scan conversion mode is converting continuously until SCANSTOP is written 24.5.6 ADCn_IEN - Interrupt Enable Register Access 0 RW SINGLE 0 1 2 3 0 RW SCAN RW SINGLEOF 4 5 6 7 8 RW Name SCANOF Access 0 9 10 11 0 Reset 12 13 14 15 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x014 17 Bit Position Offset Bit Name Reset Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 9 SCANOF 0 RW Scan Result Overflow Interrupt Enable RW Single Result Overflow Interrupt Enable Enable/disable scan result overflow interrupt. 8 SINGLEOF 0 Enable/disable single result overflow interrupt. 7:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 1 SCAN 0 RW Scan Conversion Complete Interrupt Enable Enable/disable scan conversion complete interrupt. 0 SINGLE 0 RW Single Conversion Complete Interrupt Enable Enable/disable single conversion complete interrupt. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 415 www.silabs.com ...the world's most energy friendly microcontrollers 24.5.7 ADCn_IF - Interrupt Flag Register Access 0 0 1 2 R 0 3 4 5 6 7 8 0 R R SINGLE Name SCAN SCANOF R Access SINGLEOF 0 Reset 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x018 Bit Position 31 Offset Bit Name Reset Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 9 SCANOF 0 R Scan Result Overflow Interrupt Flag Indicates scan result overflow when this bit is set. 8 SINGLEOF 0 R Single Result Overflow Interrupt Flag Indicates single result overflow when this bit is set. 7:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 1 SCAN 0 R Scan Conversion Complete Interrupt Flag Indicates scan conversion complete when this bit is set. 0 SINGLE 0 R Single Conversion Complete Interrupt Flag Indicates single conversion complete when this bit is set. 24.5.8 ADCn_IFS - Interrupt Flag Set Register Offset Access 0 W1 SINGLE 0 1 2 0 W1 SCAN W1 SINGLEOF 3 4 5 6 7 8 W1 Name SCANOF Access 0 9 10 11 0 Reset 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x01C Bit Position Bit Name Reset Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 9 SCANOF 0 W1 Scan Result Overflow Interrupt Flag Set Write to 1 to set scan result overflow interrupt flag 8 SINGLEOF 0 W1 Single Result Overflow Interrupt Flag Set Write to 1 to set single result overflow interrupt flag. 7:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 1 SCAN 0 W1 Scan Conversion Complete Interrupt Flag Set Write to 1 to set scan conversion complete interrupt flag. 0 SINGLE 0 W1 Single Conversion Complete Interrupt Flag Set Write to 1 to set single conversion complete interrupt flag. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 416 www.silabs.com ...the world's most energy friendly microcontrollers 24.5.9 ADCn_IFC - Interrupt Flag Clear Register Offset Access 0 0 1 2 W1 0 3 4 5 6 7 8 0 W1 W1 SINGLE Name SCAN SCANOF Access SINGLEOF W1 0 Reset 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x020 Bit Position Bit Name Reset Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 9 SCANOF 0 W1 Scan Result Overflow Interrupt Flag Clear Write to 1 to clear scan result overflow interrupt flag. 8 SINGLEOF 0 W1 Single Result Overflow Interrupt Flag Clear Write to 1 to clear single result overflow interrupt flag. 7:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 1 SCAN 0 W1 Scan Conversion Complete Interrupt Flag Clear Write to 1 to clear scan conversion complete interrupt flag. 0 SINGLE 0 W1 Single Conversion Complete Interrupt Flag Clear Write to 1 to clear single conversion complete interrupt flag. 24.5.10 ADCn_SINGLEDATA - Single Conversion Result Data 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0x00000000 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x024 Bit Position 31 Offset Reset DATA R Access Name Bit Name Reset Access Description 31:0 DATA 0x00000000 R Single Conversion Result Data The register holds the results from the last single conversion. Reading this field clears the SINGLEDV bit in the ADCn_STATUS register. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 417 www.silabs.com ...the world's most energy friendly microcontrollers 24.5.11 ADCn_SCANDATA - Scan Conversion Result Data Offset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0x00000000 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x028 Bit Position Reset DATA R Access Name Bit Name Reset Access Description 31:0 DATA 0x00000000 R Scan Conversion Result Data The register holds the results from the last scan conversion. Reading this field clears the SCANDV bit in the ADCn_STATUS register. 24.5.12 ADCn_SINGLEDATAP - Single Conversion Result Data Peek Register 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0x00000000 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x02C 17 Bit Position Offset Reset DATAP R Access Name Bit Name Reset Access Description 31:0 DATAP 0x00000000 R Single Conversion Result Data Peek The register holds the results from the last single conversion. Reading this field will not clear SINGLEDV in ADCn_STATUS or SINGLE DMA request. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 418 www.silabs.com ...the world's most energy friendly microcontrollers 24.5.13 ADCn_SCANDATAP - Scan Sequence Result Data Peek Register 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0x00000000 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x030 Bit Position 31 Offset Reset DATAP R Access Name Bit Name Reset Access Description 31:0 DATAP 0x00000000 R Scan Conversion Result Data Peek The register holds the results from the last scan conversion. Reading this field will not clear SCANDV in ADCn_STATUS or single DMA request. 24.5.14 ADCn_CAL - Calibration Register 0 1 2 3 RW 0x00 4 5 SINGLEOFFSET RW Access 6 7 8 9 10 0x3F 11 12 13 14 15 18 19 16 SINGLEGAIN Name 20 0x00 RW SCANGAIN Access SCANOFFSET RW Reset 21 22 23 24 25 26 27 28 0x3F 29 30 31 0x034 17 Bit Position Offset Bit Name Reset Description 31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 30:24 SCANGAIN 0x3F RW Scan Mode Gain Calibration Value This register contains the gain calibration value used with scan conversions. This field is set to the production gain calibration value for the 1V25 internal reference during reset, hence the reset value might differ from device to device. The field is unsigned. Higher values lead to higher ADC results. 23 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 22:16 SCANOFFSET 0x00 RW Scan Mode Offset Calibration Value This register contains the offset calibration value used with scan conversions. This field is set to the production offset calibration value for the 1V25 internal reference during reset, hence the reset value might differ from device to device. The field is encoded as a signed 2's complement number. Higher values lead to lower ADC results. 15 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 14:8 SINGLEGAIN 0x3F RW Single Mode Gain Calibration Value This register contains the gain calibration value used with single conversions. This field is set to the production gain calibration value for the 1V25 internal reference during reset, hence the reset value might differ from device to device. The field is unsigned. Higher values lead to higher ADC results. 7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 6:0 SINGLEOFFSET 0x00 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 RW Single Mode Offset Calibration Value 419 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description This register contains the offset calibration value used with single conversions. This field is set to the production offset calibration value for the 1V25 internal reference during reset, hence the reset value might differ from device to device. The field is encoded as a signed 2's complement number. Higher values lead to lower ADC results. 24.5.15 ADCn_BIASPROG - Bias Programming Register Access 0 1 2 BIASPROG RW 0x7 3 4 5 7 6 1 RW 8 HALFBIAS Name 9 10 Access RW 0x7 Reset COMPBIAS 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x03C Bit Position 31 Offset Bit Name Reset Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 11:8 COMPBIAS 0x7 RW Comparator Bias Value These bits are used to adjust the bias current to the ADC Comparator. 7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 6 HALFBIAS 1 RW Half Bias Current Set this bit to halve the bias current. 5:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 3:0 BIASPROG 0x7 RW Bias Programming Value These bits are used to adjust the bias current. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 420 www.silabs.com ...the world's most energy friendly microcontrollers 25 DAC - Digital to Analog Converter Quick Facts What? 0 1 2 3 The DAC is designed for low energy consumption, but can also provide very good performance. It can convert digital values to analog signals at up to 500 kilo samples/ second and with 12-bit accuracy. 4 Why? The DAC is able to generate accurate analog signals using only a limited amount of energy. ...0101110... DAC How? ...0100010... The DAC can generate high-resolution analog signals while the MCU is operating at low frequencies and with low total power consumption. Using DMA and a timer, the DAC can be used to generate waveforms without any CPU intervention. 25.1 Introduction The Digital to Analog Converter (DAC) can convert a digital value to an analog output voltage. The DAC is fully differential rail-to-rail, with 12-bit resolution. It has two single ended output buffers which can be combined into one differential output. The DAC may be used for a number of different applications such as sensor interfaces or sound output. 25.2 Features • 500 ksamples/s operation • Two single ended output channels • Can be combined into one differential output • Integrated prescaler with division factor selectable between 1-128 • Selectable voltage reference • Internal 2.5V • Internal 1.25V • VDD • Conversion triggers • Data write • PRS input • Automatic refresh timer • Selection from 16-64 prescaled HFPERCLK cycles • Individual refresh enable for each channel • Interrupt generation on finished conversion • Separate interrupt flag for each channel • PRS output pulse on finished conversion • Separate line for each channel • DMA request on finished conversion • Separate request for each channel • Support for offset and gain calibration 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 421 www.silabs.com ...the world's most energy friendly microcontrollers • Output to ADC • Sine generation mode • Optional high strength line driver 25.3 Functional Description An overview of the DAC module is shown in Figure 25.1 (p. 422) . Figure 25.1. DAC Overview CH0DATA Ch 0 DACn_OUT0 CH1DATA Ch 1 DACn_OUT1 1.25 V 2.5 V VDD ADC and ACMP REFSEL 25.3.1 Conversions The DAC consists of two channels (Channel 0 and 1) with separate 12-bit data registers (DACn_CH0DATA and DACn_CH1DATA). These can be used to produce two independent single ended outputs or the channel 0 register can be used to drive both outputs in differential mode. The DAC supports three conversion modes, continuous, sample/hold, sample/off. 25.3.1.1 Continuous Mode In continuous mode the DAC channels will drive their outputs continuously with the data in the DACn_CHxDATA registers. This mode will maintain the output voltage and refresh is therefore not needed. 25.3.1.2 Sample/Hold Mode In sample/hold mode, the DAC core converts data on a triggered conversion and then holds the output in a sample/hold element. When not converting, the DAC core is turned off between samples, which reduces the power consumption. Because of output voltage drift the sample/hold element will only hold the output for a certain period without a refresh conversion. The reader is referred to the electrical characteristics for the details on the voltage drift. The sampling period in this mode is set to the length of one prescaled clock cycle. 25.3.1.3 Sample/Off Mode In sample/off mode the DAC and the sample/hold element is turned completely off between samples, tri-stating the DAC output. This requires the DAC output voltage to be held externally. The references are also turned off between samples, which means that a new warm-up period is needed before each conversion. The sampling period in this mode is set to the length of one prescaled clock cycle. 25.3.1.4 Conversion Start The DAC channel must be enabled before it can be used. When the channel is enabled, a conversion can be started by writing to the DACn_CHxDATA register. These data registers are also mapped into 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 422 www.silabs.com ...the world's most energy friendly microcontrollers a combined data register, DACn_COMBDATA, where the data values for both channels can be written simultaneously. Writing to this register will start all enabled channels. If the PRSEN bit in DACn_CHxCTRL is set, a DAC conversion on channel x will not be started by data write, but when a positive one HFPERCLK cycle pulse is received on the PRS input selected by PRSSEL in DACn_CHxCTRL. The CH0DV and CH1DV bits in DACn_STATUS indicate that the corresponding channel contains data that has not yet been converted. When entering Energy Mode 4, both DAC channels must be stopped. 25.3.1.5 Clock Prescaling The DAC has an internal clock prescaler, which can divide the HFPERCLK by any factor between 1 and 128, by setting the PRESC bits in DACnCTRL. The resulting DAC_CLK is used by the converter core and the frequency is given by Equation 25.1 (p. 423) : DAC Clock Prescaling fDAC_CLK = fHFPERCLK / 2 ^ PRESC (25.1) where fHFPERCLK is the HFPERCLK frequency. One conversion takes 2 DAC_CLK cycles and the DAC_CLK should not be set higher than 1 MHz. Normally the PRESCALER runs continuously when either of the channels are enabled. When running with a prescaler setting higher than 0, there will be an unpredictable delay from the time the conversion was triggered to the time the actual conversion takes place. This is because the conversions is controlled by the prescaled clock and the conversion can arrive at any time during a prescaled clock (DAC_CLK) period. However, if the CH0PRESCRST bit in DACn_CTRL is set, the prescaler will be reset every time a conversion is triggered on channel 0. This leads to a predictable latency between channel 0 trigger and conversion. 25.3.2 Reference Selection Three internal voltage references are available and are selected by setting the REFSEL bits in DACn_CTRL: • Internal 2.5V • Internal 1.25V • VDD The reference selection can only be changed while both channels are disabled. The references for the DAC need to be enabled for some time before they can be used. This is called the warm-up period, and starts when one of the channels is enabled. For a bandgap reference, this period is 5 DAC_CLK cycles while the VDD reference needs 1 DAC_CLK cycle. The DAC will time this period automatically(given that the prescaler is set correctly) and delay any conversion triggers received during the warm-up until the references have stabilized. 25.3.3 Programming of Bias Current The bias current of the bandgap reference and the DAC output buffer can be scaled by the BIASPROG and HALFBIAS bit fields of the DACn_BIASPROG register as illustrated in Figure 25.2 (p. 424) . 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 423 www.silabs.com ...the world's most energy friendly microcontrollers Figure 25.2. DAC Bias Programming Reference Current BIASPROG HALFBIAS Internal bandgap reference DAC output buffer The minimum value of the BIASPROG bit-field of the DACn_BIASPROG register (i.e. BIASPROG=0b0000) represents the minimum bias current. Similarly BIASPROG=0b1111 represents the maximum bias current. The bias current defined by the BIASPROG setting can be halved by setting the HALFBIAS bit of the DACn_BIASPROG register. The bias current settings should only be changed while both DAC channels are disabled. The electrical characteristics given in the datasheet require the bias configuration to be set to the default values, where no other bias values are given. 25.3.4 Mode The two DAC channels can act as two separate single ended channels or be combined into one differential channel. This is selected through the DIFF bit in DACn_CTRL. 25.3.4.1 Single Ended Output When operating in single ended mode, the channel 0 output is on DACn_OUT0 and the channel 1 output is on DACn_OUT1. The output voltage can be calculated using Equation 25.2 (p. 424) DAC Single Ended Output Voltage VOUT = VDACn_OUTx - VSS= Vref x CHxDATA/4095 (25.2) where CHxDATA is a 12-bit unsigned integer. 25.3.4.2 Differential Output When operating in differential mode, both DAC outputs are used as output for the bipolar voltage. The differential conversion uses DACn_CH0DATA as source. The positive output is on DACn_OUT1 and the negative output is on DACn_OUT0. Since the output can be negative, it is expected that the data is written in 2’s complement form with the MSB of the 12-bit value being the signed bit. The output voltage can be calculated using Equation 25.3 (p. 424) : DAC Differential Output Voltage VOUT = VDACn_OUT1 - VDACn_OUT0= Vref x CH0DATA/2047 (25.3) where CH0DATA is a 12-bit signed integer. The common mode voltage is VDD/2. 25.3.5 Sine Generation Mode The DAC contains an automatic sine-generation mode, which is enabled by setting the SINEMODE bit in DACn_CTRL. In this mode, the DAC data is overridden with a conversion data taken from a sine lookup 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 424 www.silabs.com ...the world's most energy friendly microcontrollers table. The sine signal is controlled by the PRS line selected by CH0PRSSEL in DACn_CH0CTRL. When the PRS line is low, a voltage of Vref/2 will be produced. When the line is high, a sine wave will be produced. Each period, starting at 0 degrees, is made up of 16 samples and the frequency is given by Equation 25.4 (p. 425) : DAC Sine Generation fsine = fHFPERCLK / 32 x (PRESC + 1) (25.4) The SINE wave will be output on channel 0. If DIFF is set in DACn_CTRL, the sine wave will be output on both channels (if enabled), but inverted (see Figure 25.1 (p. 422) ). Note that when OUTENPRS in DACn_CTRL is set, the sine output will be reset to 0 degrees when the PRS line selected by CH1PRSSEL is low. Figure 25.3. DAC Sine Mode CH0 PRS CH1 PRS Vref DACn_OUT1 Vref/ 2 Hi- Z 0 Vref DACn_OUT0 Hi- Z Vref/ 2 0 25.3.6 Interrupts and PRS Output Both DAC channels have separate interrupt flags (in DACn_IF) indicating that a conversion has finished on the channel and that new data can be written to the data registers. Setting one of these flags will result in a DAC interrupt if the corresponding interrupt enable bit is set in DACn_IEN. All generated interrupts from the DAC will activate the same interrupt vector when enabled. The DAC has two PRS outputs which will carry a one cycle (HFPERCLK) high pulse when the corresponding channel has finished a conversion. 25.3.7 DMA Request The DAC sends out a DMA request when a conversion on a channel is complete. This request is cleared when the corresponding channel’s data register is written. 25.3.8 Analog Output Each DAC channel has its own output pin (DACn_OUT0 and DACn_OUT1) in addition to an internal loopback to the ADC and ACMP. These outputs can be enabled and disabled individually in the EN field in DACn_CHxCTRL registers in combination with OUTPUTSEL in DACn_CTRL. The DAC outputs can also be directed to the ADC and ACMP, which is also configurable in the OUTPUTSEL field in DACn_CTRL. The DAC outputs are tri-stated when the channels are not enabled. By setting the OUTENPRS bit in DACn_CTRL, the outputs are also tri-stated when the PRS line selected by CH1PRSSEL in DACn_CH1CTRL is low. When the PRS signal is high, the outputs are enabled as normal. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 425 www.silabs.com ...the world's most energy friendly microcontrollers The DAC channels can also drive an alternative output network, which is described in the Opamp chapter in Section 26.3.1.2 (p. 444) . To enable this network, OUTMODE must be configured to ADC in DACn_CTRL. The actual output network can be configred by configuring DACn_OPAxMUX registers. 25.3.9 Calibration The DAC contains a calibration register, DACn_CAL, where calibration values for both offset and gain correction can be written. Offset calibration is done separately for each channel through the CHxOFFSET bit-fields. Gain is calibrated in one common register field, GAIN. The gain calibration is linked to the reference and when the reference is changed, the gain must be re-calibrated. Gain and offset for the 1V25, 2V5 and VDD references are calibrated during production and the calibration values for these can be found in the Device Information page. During reset, the gain and offset calibration registers are loaded with the production calibration values for the 1V25 reference. 25.3.10 Opamps The DAC includes a set of three highly configurable opamps that can be accessed in the DAC module. Two of the opamps are located in the DAC, while the third opamp is a standalone opamp. For detailed description see the OPAMP chapter. The register description can be found Section 25.5 (p. 427) 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 426 www.silabs.com ...the world's most energy friendly microcontrollers 25.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 DACn_CTRL RW Control Register 0x004 DACn_STATUS R Status Register 0x008 DACn_CH0CTRL RW Channel 0 Control Register 0x00C DACn_CH1CTRL RW Channel 1 Control Register 0x010 DACn_IEN RW Interrupt Enable Register 0x014 DACn_IF R Interrupt Flag Register 0x018 DACn_IFS W1 Interrupt Flag Set Register 0x01C DACn_IFC W1 Interrupt Flag Clear Register 0x020 DACn_CH0DATA RW Channel 0 Data Register 0x024 DACn_CH1DATA RW Channel 1 Data Register 0x028 DACn_COMBDATA W Combined Data Register 0x02C DACn_CAL RW Calibration Register 0x030 DACn_BIASPROG RW Bias Programming Register 0x054 DACn_OPACTRL RW Operational Amplifier Control Register 0x058 DACn_OPAOFFSET RW Operational Amplifier Offset Register 0x05C DACn_OPA0MUX RW Operational Amplifier Mux Configuration Register 0x060 DACn_OPA1MUX RW Operational Amplifier Mux Configuration Register 0x064 DACn_OPA2MUX RW Operational Amplifier Mux Configuration Register 25.5 Register Description 25.5.1 DACn_CTRL - Control Register 0 0 RW DIFF 2 1 0 RW SINEMODE 3 RW 0x0 CONVMODE 4 5 RW 0x1 OUTMODE 7 6 0 RW 0 RW OUTENPRS 8 9 RW 0x0 10 11 12 13 14 15 16 17 Access CH0PRESCRST Name PRESC REFRSEL Access REFSEL Reset RW 0x0 18 19 20 21 RW 0x0 22 23 24 25 26 27 28 29 30 0x000 Bit Position 31 Offset Bit Name Reset Description 31:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 21:20 REFRSEL 0x0 RW Refresh Interval Select Select refresh counter timeout value. A channel x will be refreshed with the interval set in this register if the REFREN bit in DACn_CHxCTRL is set. Value Mode Description 0 8CYCLES All channels with enabled refresh are refreshed every 8 prescaled cycles 1 16CYCLES All channels with enabled refresh are refreshed every 16 prescaled cycles 2 32CYCLES All channels with enabled refresh are refreshed every 32 prescaled cycles 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 427 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description Value Mode Description 3 64CYCLES All channels with enabled refresh are refreshed every 64 prescaled cycles 19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 18:16 PRESC 0x0 RW Prescaler Setting Select clock division factor. Value Description PRESC Clock division factor of 2^PRESC. 15:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 9:8 REFSEL 0x0 RW Reference Selection Select reference. 7 Value Mode Description 0 1V25 Internal 1.25 V bandgap reference 1 2V5 Internal 2.5 V bandgap reference 2 VDD VDD reference CH0PRESCRST 0 RW Channel 0 Start Reset Prescaler Select if prescaler is reset on channel 0 start. 6 Value Description 0 Prescaler not reset on channel 0 start 1 Prescaler reset on channel 0 start OUTENPRS 0 RW PRS Controlled Output Enable Enable PRS Control of DAC output enable. 5:4 Value Description 0 DAC output enable always on 1 DAC output enable controlled by PRS signal selected for CH1. OUTMODE 0x1 RW Output Mode Select output mode. 3:2 Value Mode Description 0 DISABLE DAC output to pin and ADC disabled 1 PIN DAC output to pin enabled. DAC output to ADC and ACMP disabled 2 ADC DAC output to pin disabled. DAC output to ADC and ACMP enabled 3 PINADC DAC output to pin, ADC, and ACMP enabled CONVMODE 0x0 RW Conversion Mode Configure conversion mode. 1 Value Mode Description 0 CONTINUOUS DAC is set in continuous mode 1 SAMPLEHOLD DAC is set in sample/hold mode 2 SAMPLEOFF DAC is set in sample/shut off mode SINEMODE 0 RW Sine Mode Enable/disable sine mode. 0 Value Description 0 Sine mode disabled. Sine reset to 0 degrees 1 Sine mode enabled DIFF 0 RW Differential Mode Select single ended or differential mode. Value Description 0 Single ended output 1 Differential output 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 428 www.silabs.com ...the world's most energy friendly microcontrollers 25.5.2 DACn_STATUS - Status Register CH1DV Name Access 0 0 R R Access CH0DV 0 Reset 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x004 Bit Position 31 Offset Bit Name Reset Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 1 CH1DV 0 R Channel 1 Data Valid This bit is set high when CH1DATA is written and is set low when CH1DATA is used in conversion. 0 CH0DV 0 R Channel 0 Data Valid This bit is set high when CH0DATA is written and is set low when CH0DATA is used in conversion. 25.5.3 DACn_CH0CTRL - Channel 0 Control Register Access 0 RW EN 0 2 3 4 1 0 0 RW Name RW PRSSEL Access PRSEN Reset REFREN RW 0x0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x008 Bit Position 31 Offset Bit Name Reset Description 31:7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 6:4 PRSSEL 0x0 RW Channel 0 PRS Trigger Select Select Channel 0 PRS input channel. Value Mode Description 0 PRSCH0 PRS ch 0 triggers channel 0 conversion. 1 PRSCH1 PRS ch 1 triggers channel 0 conversion. 2 PRSCH2 PRS ch 2 triggers channel 0 conversion. 3 PRSCH3 PRS ch 3 triggers channel 0 conversion. 4 PRSCH4 PRS ch 4 triggers channel 0 conversion. 5 PRSCH5 PRS ch 5 triggers channel 0 conversion. 6 PRSCH6 PRS ch 6 triggers channel 0 conversion. 7 PRSCH7 PRS ch 7 triggers channel 0 conversion. 3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 2 PRSEN 0 RW Channel 0 PRS Trigger Enable Select Channel 0 conversion trigger. Value Description 0 Channel 0 is triggered by CH0DATA or COMBDATA write 1 Channel 0 is triggered by PRS input 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 429 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description 1 REFREN 0 RW Channel 0 Automatic Refresh Enable Set to enable automatic refresh of channel 0. Refresh period is set by REFRSEL in DACn_CTRL. 0 Value Description 0 Channel 0 is not refreshed automatically 1 Channel 0 is refreshed automatically EN 0 RW Channel 0 Enable Enable/disable channel 0. 25.5.4 DACn_CH1CTRL - Channel 1 Control Register Access 0 RW EN 0 2 3 1 0 RW 0 RW Name PRSEN PRSSEL Access REFREN Reset 4 5 RW 0x0 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x00C Bit Position 31 Offset Bit Name Reset Description 31:7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 6:4 PRSSEL 0x0 RW Channel 1 PRS Trigger Select Select Channel 1 PRS input channel. Value Mode Description 0 PRSCH0 PRS ch 0 triggers channel 1 conversion. 1 PRSCH1 PRS ch 1 triggers channel 1 conversion. 2 PRSCH2 PRS ch 2 triggers channel 1 conversion. 3 PRSCH3 PRS ch 3 triggers channel 1 conversion. 4 PRSCH4 PRS ch 4 triggers channel 1 conversion. 5 PRSCH5 PRS ch 5 triggers channel 1 conversion. 6 PRSCH6 PRS ch 6 triggers channel 1 conversion. 7 PRSCH7 PRS ch 7 triggers channel 1 conversion. 3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 2 PRSEN 0 RW Channel 1 PRS Trigger Enable Select Channel 1 conversion trigger. 1 Value Description 0 Channel 1 is triggered by CH1DATA or COMBDATA write 1 Channel 1 is triggered by PRS input REFREN 0 RW Channel 1 Automatic Refresh Enable Set to enable automatic refresh of channel 1. Refresh period is set by REFRSEL in DACn_CTRL. 0 Value Description 0 Channel 1 is not refreshed automatically 1 Channel 1 is refreshed automatically EN 0 RW Channel 1 Enable Enable/disable channel 1. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 430 www.silabs.com ...the world's most energy friendly microcontrollers 25.5.5 DACn_IEN - Interrupt Enable Register Access 0 0 1 2 RW 0 3 4 0 RW RW CH0 Name CH1 CH1UF Access CH0UF RW 0 Reset 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x010 Bit Position 31 Offset Bit Name Reset Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 5 CH1UF 0 RW Channel 1 Conversion Data Underflow Interrupt Enable Enable/disable channel 1 data underflow interrupt. 4 CH0UF 0 RW Channel 0 Conversion Data Underflow Interrupt Enable Enable/disable channel 0 data underflow interrupt. 3:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 1 CH1 0 RW Channel 1 Conversion Complete Interrupt Enable Enable/disable channel 1 conversion complete interrupt. 0 CH0 0 RW Channel 0 Conversion Complete Interrupt Enable Enable/disable channel 0 conversion complete interrupt. 25.5.6 DACn_IF - Interrupt Flag Register Offset Access 0 0 R CH0 2 1 0 R CH1 3 4 0 R CH0UF Name R Access CH1UF 0 Reset 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x014 Bit Position Bit Name Reset Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 5 CH1UF 0 R Channel 1 Data Underflow Interrupt Flag R Channel 0 Data Underflow Interrupt Flag Indicates channel 1 data underflow. 4 CH0UF 0 Indicates channel 0 data underflow. 3:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 1 CH1 0 R Channel 1 Conversion Complete Interrupt Flag Indicates channel 1 conversion complete and that new data can be written to the data register. 0 CH0 0 R Channel 0 Conversion Complete Interrupt Flag Indicates channel 0 conversion complete and that new data can be written to the data register. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 431 www.silabs.com ...the world's most energy friendly microcontrollers 25.5.7 DACn_IFS - Interrupt Flag Set Register Access 0 0 1 2 W1 0 3 4 0 W1 W1 CH0 Name CH1 CH1UF Access CH0UF W1 0 Reset 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x018 Bit Position 31 Offset Bit Name Reset Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 5 CH1UF 0 W1 Channel 1 Data Underflow Interrupt Flag Set Write to 1 to set channel 1 Data Underflow interrupt flag. 4 CH0UF 0 W1 Channel 0 Data Underflow Interrupt Flag Set Write to 1 to set channel 0 Data Underflow interrupt flag. 3:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 1 CH1 0 W1 Channel 1 Conversion Complete Interrupt Flag Set Write to 1 to set channel 1 conversion complete interrupt flag. 0 CH0 0 W1 Channel 0 Conversion Complete Interrupt Flag Set Write to 1 to set channel 0 conversion complete interrupt flag. 25.5.8 DACn_IFC - Interrupt Flag Clear Register Access 0 W1 CH0 0 1 W1 CH1 2 W1 CH0UF 0 3 4 W1 Name CH1UF Access 0 5 6 7 8 9 10 11 0 Reset 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x01C Bit Position 31 Offset Bit Name Reset Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 5 CH1UF 0 W1 Channel 1 Data Underflow Interrupt Flag Clear Write to 1 to clear channel 1 data underflow interrupt flag. 4 CH0UF 0 W1 Channel 0 Data Underflow Interrupt Flag Clear Write to 1 to clear channel 0 data underflow interrupt flag. 3:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 1 CH1 0 W1 Channel 1 Conversion Complete Interrupt Flag Clear Write to 1 to clear channel 1 conversion complete interrupt flag. 0 CH0 0 W1 Channel 0 Conversion Complete Interrupt Flag Clear Write to 1 to clear channel 0 conversion complete interrupt flag. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 432 www.silabs.com ...the world's most energy friendly microcontrollers 25.5.9 DACn_CH0DATA - Channel 0 Data Register 0 1 2 3 4 5 6 0x000 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x020 Bit Position 31 Offset RW Reset DATA Access Name Bit Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 11:0 DATA 0x000 RW Channel 0 Data This register contains the value which will be converted by channel 0. 25.5.10 DACn_CH1DATA - Channel 1 Data Register 0 1 2 3 4 5 0x000 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x024 Bit Position 31 Offset RW Reset DATA Access Name Bit Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 11:0 DATA 0x000 RW Channel 1 Data This register contains the value which will be converted by channel 1. 25.5.11 DACn_COMBDATA - Combined Data Register Name 0 1 2 3 4 5 0x000 6 7 8 9 10 11 CH0DATA CH1DATA W Access W Reset 12 13 14 15 16 18 19 20 21 22 0x000 23 24 25 26 27 28 29 30 31 0x028 17 Bit Position Offset Bit Name Reset 31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 Access Description 433 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description 27:16 CH1DATA 0x000 W Channel 1 Data Data written to this register will be written to DATA in DACn_CH1DATA. 15:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 11:0 CH0DATA 0x000 W Channel 0 Data Data written to this register will be written to DATA in DACn_CH0DATA. 25.5.12 DACn_CAL - Calibration Register Access 0 1 2 3 RW 0x00 4 5 6 7 8 9 CH0OFFSET Name 10 11 RW GAIN Access CH1OFFSET RW Reset 0x00 12 13 14 15 16 18 19 20 0x40 21 22 23 24 25 26 27 28 29 30 31 0x02C 17 Bit Position Offset Bit Name Reset Description 31:23 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 22:16 GAIN 0x40 RW Gain Calibration Value This register contains the gain calibration value. This field is set to the production gain calibration value for the 1V25 internal reference during reset, hence the reset value might differ from device to device. The field is unsigned. Higher values lead to lower DAC results. 15:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 13:8 CH1OFFSET 0x00 RW Channel 1 Offset Calibration Value This register contains the offset calibration value used with channel 1 conversions. This field is set to the production channel 1 offset calibration value for the 1V25 internal reference during reset, hence the reset value might differ from device to device. The field is sign-magnitude encoded. Higher values lead to lower DAC results. 7:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 5:0 CH0OFFSET 0x00 RW Channel 0 Offset Calibration Value This register contains the offset calibration value used with channel 0 conversions. This field is set to the production channel 0 offset calibration value for the 1V25 internal reference during reset, hence the reset value might differ from device to device. The field is sign-magnitude encoded. Higher values lead to lower DAC results. 25.5.13 DACn_BIASPROG - Bias Programming Register 0 1 2 BIASPROG RW 0x7 3 4 5 7 6 1 RW 8 9 Bit Name Reset 31:15 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 14 OPA2HALFBIAS 1 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 Access HALFBIAS Name 10 RW 0x7 OPA2BIASPROG Access 11 12 13 14 15 1 RW OPA2HALFBIAS Reset 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x030 17 Bit Position Offset Description RW Half Bias Current 434 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description Set this bit to halve the bias current. 13:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 11:8 OPA2BIASPROG 0x7 RW Bias Programming Value for OPA2 These bits control the bias current level. 7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 6 HALFBIAS 1 RW Half Bias Current Set this bit to halve the bias current. 5:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 3:0 BIASPROG 0x7 RW Bias Programming Value These bits control the bias current level. 25.5.14 DACn_OPACTRL - Operational Amplifier Control Register Access 0 RW OPA0EN 0 1 2 RW OPA1EN 0 RW OPA2EN 0 3 4 5 7 6 0 RW OPA0HCMDIS 0 RW OPA1HCMDIS 8 0 RW OPA2HCMDIS 9 10 11 12 13 RW 0x0 OPA0LPFDIS 14 15 RW 0x0 OPA1LPFDIS 16 OPA2LPFDIS RW OPA0SHORT 17 RW 0x0 18 19 20 21 22 RW OPA1SHORT 0 23 RW Name OPA2SHORT Access 0 24 25 26 0 Reset 27 28 29 30 0x054 Bit Position 31 Offset Bit Name Reset Description 31:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 24 OPA2SHORT 0 RW Short the non-inverting and inverting input. Set to short the non-inverting and inverting input. 23 OPA1SHORT 0 RW Short the non-inverting and inverting input. Set to short the non-inverting and inverting input. 22 OPA0SHORT 0 RW Short the non-inverting and inverting input. Set to short the non-inverting and inverting input. 21:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 17:16 OPA2LPFDIS 0x0 RW Disables Low Pass Filter. Disables the low pass filter between pad and the positive and negative input mux. 15:14 LPF DISABLE VALUE Description PLPFDIS x1 Disables the low pass filter between positive pad and positive input. NLPFDIS 1x Disables the low pass filter between negative pad and negative input. OPA1LPFDIS 0x0 RW Disables Low Pass Filter. Disables the low pass filter between pad and the positive and negative input mux. 13:12 LPF DISABLE VALUE Description PLPFDIS x1 Disables the low pass filter between positive pad and positive input. NLPFDIS 1x Disables the low pass filter between negative pad and negative input. OPA0LPFDIS 0x0 RW Disables Low Pass Filter. Disables the low pass filter between pad and the positive and negative input mux. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 435 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description LPF DISABLE VALUE Description PLPFDIS x1 Disables the low pass filter between positive pad and positive input. NLPFDIS 1x Disables the low pass filter between negative pad and negative input. 11:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 8 OPA2HCMDIS 0 RW High Common Mode Disable. Set to disable high common mode. Disables rail-to-rail on input, while output still remains rail-to-rail. The input voltage to the opamp while HCM is disabled is restricted between VSS and VDD-1.2V. 7 OPA1HCMDIS 0 RW High Common Mode Disable. Set to disable high common mode. Disables rail-to-rail on input, while output still remains rail-to-rail. The input voltage to the opamp while HCM is disabled is restricted between VSS and VDD-1.2V. 6 OPA0HCMDIS 0 RW High Common Mode Disable. Set to disable high common mode. Disables rail-to-rail on input, while output still remains rail-to-rail. The input voltage to the opamp while HCM is disabled is restricted between VSS and VDD-1.2V. 5:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 2 OPA2EN 0 RW OPA2 Enable RW OPA1 Enable Set to enable OPA2, clear to disable. 1 OPA1EN 0 Set to enable OPA1, clear to disable. CH1EN in DAC_CH1CTRL must also be set. 0 OPA0EN 0 RW OPA0 Enable Set to enable OPA0, clear to disable. CH0EN in DAC_CH0CTRL must also be set. 25.5.15 DACn_OPAOFFSET - Operational Amplifier Offset Register 0 1 2 3 0x20 4 5 6 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x058 17 Bit Position Offset RW Reset OPA2OFFSET Access Name Bit Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 5:0 OPA2OFFSET 0x20 RW OPA2 Offset Configuration Value This register contains the offset calibration value for OPA2. This field is set to the production OPA2 offset calibration value, hence the reset value might differ from device to device. The field is sign-magnitude encoded. Higher values lead to lower OPA results. The resolution of the LSB is 1.6mV/LSB 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 436 www.silabs.com ...the world's most energy friendly microcontrollers 25.5.16 DACn_OPA0MUX - Operational Amplifier Mux Configuration Register 0 2 1 0x0 RW POSSEL 3 4 5 RW NEGSEL RW RESINMUX 0x0 6 7 8 9 0x0 10 11 13 14 12 0 RW 0 RW PPEN OUTPEN NPEN RW RW OUTMODE Access 15 16 0x00 17 18 19 20 21 22 23 0x1 24 25 26 RW 0 27 NEXTOUT Name 28 29 30 0x0 Access RW Reset RESSEL 0x05C Bit Position 31 Offset Bit Name Reset Description 31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 30:28 RESSEL 0x0 RW OPA0 Resistor Ladder Select Configures the resistor ladder tap for OPA0. Value Mode Resistor Value Inverting Mode Gain (-R2/R1) Non-inverting Mode Gain (1+(R2/ R1) 0 RES0 R2 = 1/3 x R1 -1/3 1 1/3 1 RES1 R2 = R1 -1 2 2 RES2 R2 = 1 2/3 x R1 -1 2/3 2 2/3 3 RES3 R2 = 2 x R1 -2 1/5 3 1/5 4 RES4 R2 = 3 x R1 -3 4 5 RES5 R2 = 4 1/3 x R1 -4 1/3 5 1/3 6 RES6 R2 = 7 x R1 -7 8 7 RES7 R2 = 15 x R1 -15 16 27 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 26 NEXTOUT 0 RW OPA0 Next Enable Makes output of OPA0 available to OPA1. 25:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 23:22 OUTMODE 0x1 RW Output Select Select output channel. Value Mode Description 0 DISABLE OPA0 output is disabled 1 MAIN Main OPA0 output to pin enabled 2 ALT OPA0 alternative output enabled. 3 ALL Main OPA0 output drives both main and alternative outputs. 21:19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 18:14 OUTPEN 0x00 RW OPA0 Output Enable Value Set to enable output, clear to disable output 13 OUT ENABLE VALUE Description OUT0 xxxx1 Alternate Output 0 OUT1 xxx1x Alternate Output 1 OUT2 xx1xx Alternate Output 2 OUT3 x1xxx Alternate Output 3 OUT4 1xxxx Alternate Output 4 NPEN 0 RW OPA0 Negative Pad Input Enable RW OPA0 Positive Pad Input Enable Connects pad to the negative input mux 12 PPEN 0 Connects pad to the positive input mux 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 437 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description 11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 10:8 RESINMUX 0x0 RW OPA0 Resistor Ladder Input Mux These bits selects the source for the input mux to the resistor ladder Value Mode Description 0 DISABLE Set for Unity Gain 1 OPA0INP Set for OPA0 input 2 NEGPAD NEG pad connected 3 POSPAD POS pad connected 4 VSS VSS connected 7:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 5:4 NEGSEL 0x0 RW OPA0 inverting Input Mux These bits selects the source for the inverting input on OPA0 Value Mode Description 0 DISABLE Input disabled 1 UG Unity Gain feedback path 2 OPATAP OPA0 Resistor ladder as input 3 NEGPAD Input from NEG PAD 3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 2:0 POSSEL 0x0 RW OPA0 non-inverting Input Mux These bits selects the source for the non-inverting input on OPA0 Value Mode Description 0 DISABLE Input disabled 1 DAC DAC as input 2 POSPAD POS PAD as input 3 OPA0INP OPA0 as input 4 OPATAP OPA0 Resistor ladder as input 25.5.17 DACn_OPA1MUX - Operational Amplifier Mux Configuration Register 0 2 1 0x0 RW POSSEL 3 4 5 RW NEGSEL 0x0 6 7 8 9 0x0 RW RESINMUX 10 11 13 14 12 0 RW 0 RW PPEN OUTPEN NPEN RW RW OUTMODE Access 15 16 0x00 17 18 19 20 21 22 23 0x0 24 25 26 RW 0 27 NEXTOUT Name 28 29 30 0x0 Access RW Reset RESSEL 0x060 Bit Position 31 Offset Bit Name Reset Description 31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 30:28 RESSEL 0x0 RW OPA1 Resistor Ladder Select Configures the resistor ladder tap for OPA1. Value Mode Resistor Value Inverting Mode Gain (-R2/R1) Non-inverting Mode Gain (1+(R2/ R1) 0 RES0 R2 = 1/3 x R1 -1/3 1 1/3 1 RES1 R2 = R1 -1 2 2 RES2 R2 = 1 2/3 x R1 -1 2/3 2 2/3 3 RES3 R2 = 2 x R1 -2 1/5 3 1/5 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 438 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description Value Mode Resistor Value Inverting Mode Gain (-R2/R1) Non-inverting Mode Gain (1+(R2/ R1) 4 RES4 R2 = 3 x R1 -3 4 5 RES5 R2 = 4 1/3 x R1 -4 1/3 5 1/3 6 RES6 R2 = 7 x R1 -7 8 7 RES7 R2 = 15 x R1 -15 16 27 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 26 NEXTOUT 0 RW OPA1 Next Enable Makes output of OPA1 available to OPA2. 25:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 23:22 OUTMODE 0x0 RW Output Select Select output channel. Value Mode Description 0 DISABLE OPA0 output is disabled 1 MAIN Main OPA1 output to pin enabled 2 ALT OPA1 alternative output enabled. 3 ALL Main OPA1 output drives both main and alternative outputs. 21:19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 18:14 OUTPEN 0x00 RW OPA1 Output Enable Value Set to enable output, clear to disable output 13 OUT ENABLE VALUE Description OUT0 xxxx1 Alternate Output 0 OUT1 xxx1x Alternate Output 1 OUT2 xx1xx Alternate Output 2 OUT3 x1xxx Alternate Output 3 OUT4 1xxxx Alternate Output 4 NPEN 0 RW OPA1 Negative Pad Input Enable RW OPA1 Positive Pad Input Enable Connects pad to the negative input mux 12 PPEN 0 Connects pad to the positive input mux 11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 10:8 RESINMUX 0x0 RW OPA1 Resistor Ladder Input Mux These bits selects the source for the input mux to the resistor ladder Value Mode Description 0 DISABLE Set for Unity Gain 1 OPA0INP Set for OPA0 input 2 NEGPAD NEG PAD connected 3 POSPAD POS PAD connected 4 VSS VSS connected 7:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 5:4 NEGSEL 0x0 RW OPA1 inverting Input Mux These bits selects the source for the inverting input on OPA1 3 Value Mode Description 0 DISABLE Input disabled 1 UG Unity Gain feedback path 2 OPATAP OPA1 Resistor ladder as input 3 NEGPAD Input from NEG PAD Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 439 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description 2:0 POSSEL 0x0 RW OPA1 non-inverting Input Mux These bits selects the source for the non-inverting input on OPA1 Value Mode Description 0 DISABLE Input disabled 1 DAC DAC as input 2 POSPAD POS PAD as input 3 OPA0INP OPA0 as input 4 OPATAP OPA 1 Resistor ladder as input 25.5.18 DACn_OPA2MUX - Operational Amplifier Mux Configuration Register Offset 0 1 2 RW 0x0 POSSEL 3 4 5 RW 0x0 NEGSEL 6 7 8 9 RW 0x0 RESINMUX 10 11 13 12 0 RW 0 RW PPEN OUTPEN Access NPEN 14 15 RW 0x0 16 17 18 19 20 21 22 OUTMODE RW 0 23 24 25 26 0 RW 27 28 NEXTOUT Name 29 30 Access RW 0x0 Reset RESSEL 31 0x064 Bit Position Bit Name Reset Description 31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 30:28 RESSEL 0x0 RW OPA2 Resistor Ladder Select Configures the resistor ladder tap for OPA2. Value Mode Resistor Value Inverting Mode Gain (-R2/R1) Non-inverting Mode Gain (1+(R2/ R1) 0 RES0 R2 = 1/3 x R1 -1/3 1 1/3 1 RES1 R2 = R1 -1 2 2 RES2 R2 = 1 2/3 x R1 -1 2/3 2 2/3 3 RES3 R2 = 2 x R1 -2 1/5 3 1/5 4 RES4 R2 = 3 x R1 -3 4 5 RES5 R2 = 4 1/3 x R1 -4 1/3 5 1/3 6 RES6 R2 = 7 x R1 -7 8 7 RES7 R2 = 15 x R1 -15 16 27 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 26 NEXTOUT 0 RW OPA2 Next Enable OPA2 does not have an next output. 25:23 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 22 OUTMODE 0 RW Output Select Enables OPA2 main output. 21:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:14 OUTPEN 0x0 RW OPA2 Output Location Select location for main output 13 Value Mode Description 1 OUT0 Main Output 0 2 OUT1 Main Output 1 NPEN 0 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 RW OPA2 Negative Pad Input Enable 440 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description RW OPA2 Positive Pad Input Enable Connects pad to the negative input mux 12 PPEN 0 Connects pad to the positive input mux 11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 10:8 RESINMUX 0x0 RW OPA2 Resistor Ladder Input Mux These bits selects the source for the input mux to the resistor ladder Value Mode Description 0 DISABLE Set for Unity Gain 1 OPA1INP Set for OPA1 input 2 NEGPAD NEG PAD connected 3 POSPAD POS PAD connected 4 VSS VSS connected 7:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 5:4 NEGSEL 0x0 RW OPA2 inverting Input Mux These bits selects the source for the inverting input on OPA2 Value Mode Description 0 DISABLE Input disabled 1 UG Unity Gain feedback path 2 OPATAP OPA2 Resistor ladder as input 3 NEGPAD Input from NEG PAD 3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 2:0 POSSEL 0x0 RW OPA2 non-inverting Input Mux These bits selects the source for the non-inverting input on OPA2 Value Mode Description 0 DISABLE Input disabled 2 POSPAD POS PAD as input 3 OPA1INP OPA1 as input 4 OPATAP OPA0 Resistor ladder as input 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 441 www.silabs.com ...the world's most energy friendly microcontrollers 26 OPAMP - Operational Amplifier Quick Facts What? The opamps are low power amplifiers with a high degree of flexibility targeting a wide variety of standard opamp application areas. With flexible gain and interconnection builtin programming they can be configured to support multiple common opamp functions, with all pins available externally for filter configurations. Each opamp has a rail to rail input and a rail to rail output. 0 1 2 3 4 Why? VIN The opamps are included to save energy on a pcb compared to standalone opamps, but also reduce system cost by replacing external opamps. + - VOUT How? Two of the opamps are made available as part of the DAC, while the third opamp is standalone. An ADC unity gain buffer mode configuration makes it possible to isolate kickback noise, in addition to popular differential to single ended and differential to differential driver modes. The opamps can also be configured as a one, two- or three-step cascaded PGA, and for all of the built-in modes no external components are necessary. 26.1 Introduction The opamps are highly configurable general purpose opamps, suitable for simple filters and buffer applications. The three opamps can be configured to support various operational amplifier functions through a network of muxes, with possibilities of selecting ranges of on-chip non-inverting and inverting gain configurations, and selecting between outputs to various destinations. The opamps can also be configured with external feedback in addition to supporting cascade connections between two or three opamps. The opamps are rail-to-rail in and out. A user selectable mode has been added to optimize linearity, in which case the input voltage to the opamp is restricted between VSS and VDD-1.2V. 26.2 Features • 3 individually configurable opamps • Opamps support rail-to-rail inputs and outputs • Supports the following functions • General Opamp Mode • Voltage Follower Unity Gain • Inverting Input PGA • Non-inverting PGA • Cascaded Inverting PGA 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 442 www.silabs.com ...the world's most energy friendly microcontrollers • Cascaded Non-inverting PGA • Two Opamp Differential Amplifier • Three Opamp Differential Amplifier • Dual Buffer ADC Driver • Programmable gain 26.3 Functional Description The three opamps can be configured to perform various opamp functions through a network of muxes. An overview of the opamps are shown in Figure 26.1 (p. 443) . Two of the three opamps are part of the DAC, while the third opamp is standalone. The output of OPA0 can be routed to ADC CH0, OPA1 and various pin outputs. The output of OPA1 can be routed to ADC CH1, OPA2, and various pin outputs. The output of OPA2 can be routed to ADC CH0, CH5, and various pin output destinations. All three opamps can also take input from pins. Since OPA0 and OPA1 are part of the DAC, special considerations needs to be taken when both the DAC Ch0/Ch1 and OPA0/OPA1 are being used. For detailed explanation the reader is referred to Section 26.3.3 (p. 452) . Figure 26.1. OPAMP System Overview POS2 OPA0 Alternative outputs DAC NEG2 POS0 ADC CH0 input m ux ADC CH5 input m ux OPA0 OPA0 Main output OPA2 Main outputs OPA0NEXT NEG0 ADC CH0 input m ux OPA2 OPA1 Alternative outputs POS1 ADC CH1 input m ux OPA1 OPA1 Main output OPA1NEXT NEG1 A more detailed view of the three opamps, including the mux network is shown in Figure 26.2 (p. 444) . There is a set of input muxes for each opamp, making it possible to select various input sources. The POSSEL mux connected to the positive input makes it possible to select pin, another opamp output, or tap from the resistor network. Similarly, the NEGSEL mux on the negative input makes it possible to select pin or a feedback path as its source. The feedback path can be a unity gain configuration, or selected from the resistor network for programmable gain. The output of the opamp have different sets of outputs, a main output, an alternative output network and a next output. These outputs make it possible to route the output to pin, another opamp input, ADC, or into the feedback path. For details regarding configuring the outputs, the reader is referred to Section 26.3.1.2 (p. 444) . In addition, there is also a mux to configure the resistor ladder to be connected to vss, pin, or another opamp output. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 443 www.silabs.com ...the world's most energy friendly microcontrollers Figure 26.2. OPAMP Overview POS0 POSSEL[2:0] PPEN POSPAD + NEXTOUT0 OPA0TAP OPA0 Main output Alternative output network NEXTOUT0 NEG0 NPEN NEGPAD NEGSEL[1:0] Unity gain OPA0TAP R1 POS2 POSSEL[2:0] PPEN POSPAD R2 + NEXTOUT1 OPA0TAP NEXTOUT0 OPA2 Main output VSS NEG2 RESINMUX[3:0] POS1 PPEN NEGPAD NEGSEL[1:0] POSPAD Unity gain OPA2TAP + NEXTOUT0 OPA1TAP OPA1 Main output Alternative output network NEXTOUT1 NEG1 NPEN POSSEL[2:0] NPEN R1 R2 NEXTOUT1 NEGPAD VSS NEGSEL[1:0] RESINMUX[3:0] Unity gain OPA1TAP R1 R2 NEXTOUT0 VSS RESINMUX[3:0] 26.3.1 Opamp Configuration Since two of the three opamps (OPA0, OPA1) are part of the DAC, the opamp configuration registers are located in the DAC. The mux registers for OPA0/OPA1 together with OPA2 registers are separate registers, also located under the DAC module. OPA0 and OPA1 can be enabled by setting OPAxEN in DACn_OPACTRL and CHxEN in CHxCTRL. OPA2 can be enabled by only setting OPA2EN in DACn_OPACTRL. 26.3.1.1 Input Configuration The inputs to the opamps are controlled through a set of input muxes. The mux connected to the positive input is configured by the POSSEL bit-field in the DACn_OPAxMUX register. Similarly, the mux connected to the negative input is configured by setting the NEGSEL bit-field in DACn_OPAxMUX. To connect the pins to the input muxes, the pin switches must also be enabled. Setting the PPEN bitfield enables to POSPADx, while setting the NPEN bit-field enables the NEGPADx, both located in DACn_OPAxMUX. The input into the resistor ladder can be configured by setting the RESINMUX bitfield in DACn_OPAxMUX. 26.3.1.2 Output Configuration The opamp have two outputs, one main output and one alternative output with lower drive strength. These two outputs can be used to drive the different outputs as shown in Figure 26.3 (p. 445) . The main opamp output can be used to drive the main output by setting OUTMODE to MAIN in DACn_OPAxMUX. The alternative opamp output can drive the alternative output network by setting OUTMODE to ALT in DACn_OPAxMUX. In addition, it is also possible to use the main opamp output to drive both the main output and the alternative output network by setting OUTMODE to ALL in DACn_OPAxMUX. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 444 www.silabs.com ...the world's most energy friendly microcontrollers Figure 26.3. Opamp Output Stage Overview OPA0 Main output OPA0 output OPA1 Main output + OPA0 OPA2 Main outputs + OPA0 Alternative output network ADC CH5 input m ux OUT0 OUT1 OPA1 Alternative output network ADC CH0 input m ux OUT0 OUT1 OUT1 OUT2 OUT2 OUT3 OUT3 NEXTOUT MAIN OPA2 - OUT0 OUT4 OPA2 output MAIN/ ALL OPA1 - ALT/ ALL - OPA1 output MAIN/ ALL ALT/ ALL + OUT4 ADC CH0 input m ux NEXTOUT ADC CH1 input m ux The alternative output network consists of connections to pins, ADC, and a connection to the next opamp (OPA0 to OPA1, and OPA1 to OPA2). The connections to pins can be individually enabled by configuring OUTPEN in DACn_OPAxMUX register. To enable cascaded opamp configurations, each opamp has a NEXTOUT connection. This output makes it possible to connect OPA0 to OPA1, and OPA1 to OPA2. This output connection is enabled by setting NEXTOUT in DACn_OPAxMUX. The opamps can also be routed to the ADC. OPA0 can be connected to ADC CH0, OPA1 to ADC CH1 and OPA2 can be connected to both ADC CH1 and CH5. The ADC connections are created by routing the OPA output by setting corresponding bits in OUTPEN in DACn_OPAxMUX. For OPA0 alternative output 4 is connected to ADC input mux CH0 when enabled. OPA1's alternative output 4 is connected to ADC input mux CH1 when enabled. For OPA2, the two main outputs can be connected to ADC input mux CH0 and ADC input mux CH5 respectively when enabled. See Section 24.3.4 (p. 401) , in the ADC chapter for information on how to configure the ADC input mux. 26.3.1.3 Gain Programming The feedback path of each mux includes a resistor ladder, which can be used to select a set of gain values. The gain can be selected by the RESSEL bit-field located in DACn_OPAxMUX register. The gain values are taken from tappings of the resistor ladder based on ratio of R2/R1. It is also possible to bypass the resistor ladder in Unity Gain (UG) mode. 26.3.1.4 Offset Calibration The offset calibration registers are located in different registers for the opamps. OPA0 and OPA1's offset can be set through the CH0OFFSET and CH1OFFSET bit-fields respectively in DACn_CAL. The offset for OPA2 can be set through OPA2OFFSET in DACn_OPAOFFSET. 26.3.1.5 Shorting Non-inverting and Inverting Input Functionality for offset calibration of the opamps has been added, this functionality is enabled by setting the OPAxSHORT bit-field in DACn_OPAxCTRL. Setting this bit-field enables a switch that shorts between the inverting and non-inverting input of the OPA, effectively driving the offset voltage of the opamp to the output. Using the ADC to measure this offset, the calibration register can be adjusted to minimize the output offset. 26.3.1.6 Low Pass Filter The low pass filter is located between the pad and the positive input. The low-pass filter is designed to couple the input signal to local VSS for high frequencies and has a 3 dB frequency of approximately 130 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 445 www.silabs.com ...the world's most energy friendly microcontrollers MHz when driven from a 50 ohm source. The filter adds a parasitic capacitance of approximately 1.2 pF towards local VSS when enabled. The filter is enabled out of reset and can be disabled by setting OPAxLPFDIS in DACn_OPAxCTRL. 26.3.1.7 Disabling of rail-to-rail Operation Each opamp can have the input rail-to-rail stage disabled by setting the OPAxHCMDIS bit-field in DACn_OPACTRL. Disabling the rail-to-rail input stage improves linearity of the opamp, thus improving the Total Harmonic Distortion, THD, at the cost of reduced input signal swing. 26.3.2 Opamp Modes The opamp can be configured to perform different Operational Amplifier functions by configuring the internal signal routing between the opamps. The modes available are described in the following sections. 26.3.2.1 General Opamp Mode In this mode the resistor ladder is isolated from the feedback path and input signal routing is defined by OPAxPOSSEL and OPAxNEGSEL in DACn_OPAxMUX. The output signal routing is defined by OUTPEN in DACn_OPAxMUX Table 26.1. General Opamp Mode Configuration OPA bit-fields OPA Configuration OPAx POSSEL POSPADx OPAx NEGSEL OPATAP, UG, NEGPADx OPAx RESINMUX NEXTOUT, POSPADx, NEGPADx VSS 26.3.2.2 Voltage Follower Unity Gain In this mode the unity gain feedback path is selected for the negative input by setting the OPAxNEGSEL bit-field to UG in the DACn_OPAxMUX register as shown in Figure 26.4 (p. 446) . The positive input is selected by the OPAxPOSSEL bit-field, and the output is configured by the OUTPEN bit-field, both in the DACn_OPAxMUX register. Figure 26.4. Voltage Follower Unity Gain Overview VIN + - VOUT Table 26.2. Voltage Follower Unity Gain Configuration OPA bit-fields OPA Configuration OPAx POSSEL OPATAP, NEXTOUT, POSPADx OPAx NEGSEL UG OPAx RESINMUX DISABLE 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 446 www.silabs.com ...the world's most energy friendly microcontrollers 26.3.2.3 Inverting input PGA Figure 26.5 (p. 447) shows the inverting input PGA configuration. In this mode the negative input is connected to the resistor ladder by setting the OPAxNEGSEL bit-field to OPATAP in the DACn_OPAxMUX register. This setting provides a programmable gain on the negative input, which can be set by choosing the wanted gain value in the RESSEL bit-field in DACn_OPAxMUX. Signal ground for the positive input can be generated off-chip through the pad by setting OPAxPOSSEL bitfield to PAD in DACn_OPAxMUX. In addition the output is configured by the OUTPEN bit-field, located in DACn_OPAxMUX. Figure 26.5. Inverting input PGA Overview POS + VOUT - VOUT= - (VIN- POS) R2/ R1 + POS VIN R1 R2 Table 26.3. Inverting input PGA Configuration OPA bit-fields OPA Configuration OPAx POSSEL POSPADx OPAx NEGSEL OPATAP OPAx RESINMUX NEXTOUT, NEGPADx, POSPADx 26.3.2.4 Non-inverting PGA Figure 26.6 (p. 447) shows the non-inverting input configuration. In this mode the negative input is connected to the resistor ladder by setting the OPAxNEGSEL bit-field to OPATAP in DACn_OPAxMUX. This setting provides a programmable gain on the negative input, which can be set by choosing the wanted gain value in the RESSEL bit-field in DACn_OPAxMUX. In addition the OPAxRESINMUX bit-field must be set to VSS or NEGPAD in DACn_OPAxMUX. The positive input is selected by the OPAxPOSSEL bit-field, and the output is configured by the OUTPEN bit-field, both located in DACn_OPAxMUX. Figure 26.6. Non-inverting PGA Overview VIN + VOUT - VOUT= VIN(1+ R2/ R1) R1 R2 Table 26.4. Non-inverting PGA Configuration OPA bit-fields OPA Configuration OPAx POSSEL NEXTOUT, POSPADx OPAx NEGSEL OPATAP OPAx RESINMUX VSS, NEGPAD 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 447 www.silabs.com ...the world's most energy friendly microcontrollers 26.3.2.5 Cascaded Inverting PGA This mode enables the opamp signals to be internally configured to cascade two or three opamps in inverting mode as shown in Figure 26.7 (p. 448) . In both cases the positive input will be configured to signal ground by setting OPAxPOSSEL bit-field to PAD in DACn_OPAx_MUX. When cascaded, the negative input is connected to the resistor ladder by setting the OPAxNEGSEL bit-field to OPATAP in DACn_OPAxMUX. The input to the resistor ladder can be configured in the OPAxRESINMUX bit-field in DAC_nOPAxMUX. The output from OPA0 can be connected to OPA1 to create the second stage by setting the NEXTOUT bit-field in DACn_OPAxMUX. To complete the stage, OPA1RESINMUX field must be set to OPA0INP. Similarly, the last stage can be created by setting the NEXTOUT bit-field in DACn_OPA1MUX and OPA2RESINMUX bit-field to OPA1INP in DACn_OPA2MUX. Figure 26.7. Cascaded Inverting PGA Overview POS2 + VOUT3= - (VOUT2- POS3) x R2/ R1 + POS3 POS1 + R1 - R2 VOUT2= - (VOUT1- POS1) x R2/ R1 + POS1 POS0 + R1 - R2 VOUT1= - (VIN- POS0) x R2/ R1 + POS0 VIN R1 R2 Table 26.5. Cascaded Inverting PGA Configuration OPA OPA bit-fields OPA Configuration OPA0 POSSEL POSPAD0 OPA0 NEGSEL OPA0TAP OPA0 RESINMUX NEGPAD0 OPA0 NEXTOUT 1 OPA1 POSSEL POSPAD1 OPA1 NEGSEL OPATAP OPA1 RESINMUX OPA0INP OPA1 NEXTOUT 1 OPA2 POSSEL POSPAD2 OPA2 NEGSEL OPATAP OPA2 RESINMUX OPA1INP 26.3.2.6 Cascaded Non-inverting PGA This mode enables the opamp signals to be internally configured to cascade two or three opamps in noninverting mode as shown in Figure 26.8 (p. 449) . In both cases the negative input for all opamps will be connected to the resistor ladder by setting the OPAxNEGSEL bit-field to OPATAP. In addition the resistor ladder input must be set to VSS or NEGPADx in the OPAxRESINMUX in DACn_OPAxMUX. When cascaded, the positive input on OPA0 is configured by the OPA0POSSEL bit-field. The output from OPA0 can be connected to OPA1 to create the second stage by setting NEXTOUT in DACn_OPA0MUX. To complete the stage, the OPA1POSSEL bit-field must be set to OPA0INP in DACn_OPA1MUX. Similarly, 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 448 www.silabs.com ...the world's most energy friendly microcontrollers the last stage can be created by setting NEXTOUT in DACn_OPA1MUX and OPA2POSSEL bit-field to OPA1INP in DACn_OPA2MUX. Figure 26.8. Cascaded Non-inverting PGA Overview VIN + VOUT1= VIN(1+ R2/ R1) + VOUT2= VIN(1+ R2/ R1) - + VOUT3= VIN(1+ R2/ R1) - R1 R2 R1 R2 R1 R2 Table 26.6. Cascaded Non-inverting PGA Configuration OPA OPA bit-fields OPA Configuration OPA0 POSSEL POSPAD0 OPA0 NEGSEL OPATAP OPA0 RESINMUX VSS, NEGPAD0 OPA0 NEXTOUT 1 OPA1 POSSEL OPA0INP OPA1 NEGSEL OPATAP OPA1 RESINMUX VSS, NEGPAD1 OPA1 NEXTOUT 1 OPA2 POSSEL OPA1INP OPA2 NEGSEL OPATAP OPA2 RESINMUX VSS, NEGPAD2 26.3.2.7 Two Opamp Differential Amplifier This mode enables OPA0 and OPA1 or OPA1 and OPA2 to be internally configured to form a two opamp differential amplifier as shown in Figure 26.9 (p. 450) . When using OPA0 and OPA1, the positive input of OPA0 can be connected to any input by configuring the OPA0POSSEL bit-field in DACn_OPA0MUX. The OPA0 feedback path must be configured to unity gain by setting the OPA0NEGSEL bit-field to UG in DACn_OPA0MUX. In addition, the OPA0RESINMUX bit-field must be set to DISABLED. The OPA0OUT must be connected to OPA1 by setting NEXTOUT in DACn_OPA0MUX, and OPA1RESINMUX to OPA0INP. The positive input on OPA1 can be set by configuring OPA1POSSEL. The OPA1 output can be configured by configuring the OUTPEN and OUTMODE bit-field. When using OPA1 and OPA2, the positive input of OPA1 can be connected to any input by configuring the OPA1POSSEL bit-field in DACn_OPA1MUX. The OPA1 feedback path must be configured to unity gain by setting the OPA1NEGSEL bit-field to UG in DACn_OPA1MUX. In addition, the OPA1RESINMUX bit-field must be set to DISABLED. The OPA1OUT must be connected to OPA2 by setting NEXTOUT in DACn_OPA1MUX, and OPA2RESINMUX to OPA1INP. The positive input on OPA2 can be set by configuring OPA2POSSEL. The OPA2 output can be configured by configuring the OUTPEN and OUTMODE bit-field. Note When making a differential connection with the ADC, only OPA1 and OPA2 can be used 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 449 www.silabs.com ...the world's most energy friendly microcontrollers Figure 26.9. Two Op-amp Differential Amplifier Overview V2 V1 + OPA1 + OPA0 - VDIFF= (V2- V1)R2/ R1 R1 R2 V2 V1 + OPA2 + OPA1 - VDIFF= (V2- V1)R2/ R1 R1 R2 Table 26.7. OPA0/OPA1 Differential Amplifier Configuration OPA OPA bit-fields OPA Configuration OPA0 POSSEL POSPAD1 OPA0 NEGSEL UG OPA0 RESINMUX DISABLE OPA0 NEXTOUT 1 OPA1 POSSEL POSPAD1 OPA1 NEGSEL OPATAP OPA1 RESINMUX OPA1INP Table 26.8. OPA1/OPA2 Differential Amplifier Configuration OPA OPA bit-fields OPA Configuration OPA1 POSSEL POSPAD1 OPA1 NEGSEL UG OPA1 RESINMUX DISABLE OPA1 NEXTOUT 1 OPA2 POSSEL POSPAD1 OPA2 NEGSEL OPATAP OPA2 RESINMUX OPA1INP 26.3.2.8 Three Opamp Differential Amplifier This mode enables the three opamps to be internally configured to form a three opamp differential amplifier as shown in Figure 26.10 (p. 451) . Both OPA0 and OPA1 can be configured in the same unity gain mode. For both OPA0/OPA1 the positive input can be connected to any input by configuring the OPA0POSSEL/OPA1POSSEL bit-field. The OPA0/OPA1 feedback path must be configured to unity gain by setting the OPA0NEGSEL/OPA1NEGSEL bit-field to UG. In addition the OPA0RESINMUX/ OPA1RESINMUX bit-fields must be set to DISABLED. The OPA1 output must be connected to 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 450 www.silabs.com ...the world's most energy friendly microcontrollers OPA2 by setting the NEXTOUT bit-field in DACn_OPA1MUX and OPA2RESINMUX to OPA1INP in DACn_OPA2MUX. In addition the OPA2POSSEL must be set to 0PATAP. The OPA2 output can be configured by configuring the OUTPEN and OUTMODE bit-field. Figure 26.10. Three Op-amp Differential Amplifier Overview V2 + OPA0 - R1 R2 + OPA2 - V1 + OPA1 - VOUT VOUT= (V2- V1)R2/ R1 R1 R2 The gain values for the Three Opamp Differential Amplifier is determined by the combination of the gain settings of OPA0 and OPA2. The 3 different gain values available, 1/3, 1 and 3, can be programmed as shown in the table below. Table 26.9. Three Opamp Differential Amplifier Gain Programming Gain OPA0 RESSEL OPA2 RESSEL 1/3 4 0 1 1 1 3 0 4 Table 26.10. Three Opamp Differential Amplifier Configuration OPA OPA bit-fields OPA Configuration OPA0 POSSEL POSPAD OPA0 NEGSEL UG OPA0 RESINMUX DISABLE OPA1 POSSEL POSPAD OPA1 NEGSEL UG OPA1 RESINMUX DISABLE OPA1 NEXTOUT 1 OPA2 POSSEL OPATAP OPA2 NEGSEL OPATAP OPA2 RESINMUX OPA1INP 26.3.2.9 Dual Buffer ADC Driver It is possible to use OPA0 and OPA1 to form a Dual Buffer ADC driver as shown in Figure 26.11 (p. 452) . Both opamps used can be configured in the same way. The positive input is configured by setting the 0PAxPOSSEL to PAD and the negative input can be connected to the resistor ladder by 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 451 www.silabs.com ...the world's most energy friendly microcontrollers setting OPATAP in DACn_OPAxMUX. The output from the opamps can be configured to connect to the ADC by setting OUTMODE to ALT or ALL in DACn_OPAxMUX. Figure 26.11. Dual Buffer ADC Driver Overview VIP VIN + - R1 R2 + - VOUTP= VIP(1+ R2/ R1) or VOUTP = VIP (Unity Gain) R1 VOUTN= VIN(1+ R2/ R1) or VOUTN = VIN (Unity Gain) R2 Table 26.11. Dual Buffer ADC Driver Configuration OPA OPA bit-fields OPA Configuration OPA0 POSSEL POSPAD0 OPA0 NEGSEL OPATAP OPA0 RESINMUX VSS OPA1 POSSEL POSPAD1 OPA1 NEGSEL OPATAP OPA1 RESINMUX VSS 26.3.3 Opamp DAC Combination Since two of the opamps are part of the DAC it is not possible to use both DAC channels and all three opamps at the same time. If both DAC channels are used, only OPA2 is available out of the 3 opamps. However, it is possible to use one of the DAC channels in combination with OPA0/OPA1. OPA1 is available when DAC channel 0 is in use and OPA0 is available when DAC channel 1 is used. When using the opamp DAC combination, the DAC CONVMODE can only be configured to either CONTINUOUS or SAMPLEHOLD mode. The CONVMODE bitfield can be configured in DACn_CTRL register. In the opamp/DAC combination, the DAC channel enabled is configured through the DAC registers while the opamp is controlled through the opamp registers. 26.4 Register Description The register description of the opamp can be found in Section 25.4 (p. 427) in the DAC chapter. 26.5 Register Map The register map of the opamp can be found in Section 25.4 (p. 427) in the DAC chapter. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 452 www.silabs.com ...the world's most energy friendly microcontrollers 27 AES - Advanced Encryption Standard Accelerator Quick Facts What? 0 1 2 3 A fast and energy efficient hardware accelerator for AES-128 and AES-256 encryption and decryption. 4 Why? How are you? AES Efficient encryption/decryption with little or no CPU intervention helps to meet the speed and energy demands of the application. &G#%5 How? I am fine AES High AES throughput allows the EFM32TG to spend more time in lower energy modes. In addition, specialized data access functions allow autonomous DMA/AES operation in both EM0 and EM1. !T4/ #2 27.1 Introduction The Advanced Encryption Standard (FIPS-197) is a symmetric block cipher operating on 128-bit blocks of data and 128-, 192- or 256-bit keys. The AES accelerator performs AES encryption and decryption with 128-bit or 256-bit keys. Encrypting or decrypting one 128-bit data block takes 54 HFCORECLK cycles with 128-bit keys and 75 HFCORECLK cycles with 256-bit keys. The AES module is an AHB slave which enables efficient access to the data and key registers. All write accesses to the AES module must be 32-bit operations, i.e. 8- or 16-bit operations are not supported. 27.2 Features • AES hardware encryption/decryption • 128-bit key (54 HFCORECLK cycles) • 256-bit key (75 HFCORECLK cycles) • Efficient CPU/DMA support • Interrupt on finished encryption/decryption • DMA request on finished encryption/decryption • Key buffer in AES128 mode • Optional XOR on Data write • Configurable byte ordering 27.3 Functional Description Some data and a key must be loaded into the KEY and DATA registers before an encryption or decryption can take place. The input data before encryption is called the PlainText and output from the encryption is called CipherText. For encryption, the key is called PlainKey. After one encryption, the resulting key in the KEY registers is the CipherKey. This key must be loaded into the KEY registers before every decryption. After one decryption, the resulting key will be the PlainKey. The resulting PlainKey/CipherKey is only dependent on the value in the KEY registers before encryption/decryption. The resulting keys and data are shown in Figure 27.1 (p. 454) . 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 453 www.silabs.com ...the world's most energy friendly microcontrollers Figure 27.1. AES Key and Data Definitions Encryption PlainTex t Decryption PlainKey Decryption CipherTex t Encryption CipherKey 27.3.1 Encryption/Decryption The AES module can be set to encrypt or decrypt by clearing/setting the DECRYPT bit in AES_CTRL. The AES256 bit in AES_CTRL configures the size of the key used for encryption/decryption. The AES_CTRL register should not be altered while AES is running, as this may lead to unpredictable behaviour. An AES encryption/decryption can be started in the following ways: • Writing a 1 to the START bit in AES_CMD • Writing 4 times 32 bits to AES_DATA when the DATASTART control bit is set • Writing 4 times 32 bits to AES_XORDATA when the XORSTART control bit is set An AES encryption/decryption can be stopped by writing a 1 to the STOP bit in AES_CMD. The RUNNING bit in AES_STATUS indicates that an AES encryption/decryption is ongoing. 27.3.2 Data and Key Access The AES module contains a 128-bit DATA (State) register and two 128-bit KEY registers defined as DATA3-DATA0, KEY3-KEY0 (KEYL) and KEY7-KEY4 (KEYH). In AES128 mode, the 128-bit key is read from KEYL, while both KEYH and KEYL are used in AES256 mode. The AES module has configurable byte ordering which is configured in BYTEORDER in AES_CTRL. Figure 27.2 (p. 454) illustrates how data written to the AES registers is mapped to the key and state defined in the Advanced Encryption Standard (FIPS-197). The figure presents the key byte order for 256-bit keys. In 128-bit mode with BYTEORDER cleared, a16 represents the first byte of the 128-bit key. When BYTEORDER is set, a0 represents the first byte in the key. AES encryption/decryption takes two extra cycles when BYTEORDER is set. BYTEORDER has to be set prior to loading the data and key registers. Figure 27.2. AES Data and Key Orientation as Defined in the Advanced Encryption Standard BYTEORDER = 0 a17 a21 a25 a29 a14 a18 a22 a26 a30 [7:0] S3,0 S3,1 S3,2 S3,3 a3 a7 a11 a15 a19 a23 a27 a31 a16 a20 a24 a28 [15:8] S1,0 S1,1 S1,2 S1,3 a1 a5 a9 a13 a17 a21 a25 a29 [23:16] S2,0 S2,1 S2,2 S2,3 a2 a6 a10 a14 a18 a22 a26 a30 [31:24] S3,0 S3,1 S3,2 S3,3 a3 a7 a11 a15 a19 a23 a27 a31 KEY7 a13 a10 a12 KEY6 a9 a6 a8 KEY5 a2 a4 KEY4 a1 S2,3 a0 KEY3 S1,3 S2,2 S0,3 KEY2 S1,2 S2,1 S0,2 KEY1 S1,1 S2,0 S0,1 KEY0 S1,0 [15:8] S0,0 DATA3 a5 KEY0 [23:16] [7:0] DATA2 a28 KEY1 a4 KEYH DATA1 a24 KEY2 a0 KEYL DATA0 a20 KEY3 S0,3 Byte order in word a16 KEY4 S0,2 DATA0 a12 KEY5 S0,1 DATA1 a8 KEY6 S0,0 DATA KEYL KEY7 [31:24] DATA2 KEYH DATA3 Byte order in word DATA BYTEORDER = 1 The registers DATA3-DATA0, are not memory mapped directly, but can be written/read by accessing AES_DATA or AES_XORDATA. The same applies for the key registers, KEY3-KEY0 which are 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 454 www.silabs.com ...the world's most energy friendly microcontrollers accessed through AES_KEYLn (n=A, B, C or D), while KEY7-KEY4 are accessed through KEYHn (n=A, B, C or D). Writing DATA3-DATA0 is then done through 4 consecutive writes to AES_DATA (or AES_XORDATA), starting with the word which is to be written to DATA0. For each write, the words will be word wise barrel shifted towards the least significant word. Accessing the KEY registers are done in the same fashion through KEYLn and KEYHn. See Figure 27.3 (p. 455) . Note that KEYHA, KEYHB, KEYHC and KEYHD are really the same register, just mapped to four different addresses. You can then choose freely which of these addresses you want to use to update the KEY7-KEY4 registers. The same principle applies to the KEYLn registers. Mapping the same registers to multiple addresses like this, allows the DMA controller to write a full 256-bit key in one sweep, when incrementing the address between each word write. Figure 27.3. AES Data and Key Register Operation Shift on write and read Write data AES_DATA/ AES_XORDATA DATA3 Write data AES_KEYLn KEY3 Write data AES_KEYHn KEY7 DATA2 DATA1 DATA0 Read data KEY0 Read data KEY4 Read data Shift on write and read KEY2 KEY1 Shift on write and read KEY6 KEY5 27.3.2.1 Key Buffer When encrypting multiple blocks of data in a row, the PlainKey must be written to the key register between each encryption, since the contents of the key registers will be turned into the CipherKey during the encryption. The opposite applies when decrypting, where you have to re-supply the CipherKey between each block. However, in AES128 mode, KEY4-KEY7 can be used as a buffer register, to hold an extra copy of the KEY3-KEY0 registers. When KEYBUFEN is set in AES_CTRL, the contents of KEY7-KEY4 are copied to KEY3-KEY0, when an encryption/decryption is started. This eliminates the need for re-loading the KEY for every encrypted/decrypted block when running in AES128 mode. 27.3.2.2 Data Write XOR The AES module contains an array of XOR gates connected to the DATA registers, which can be used during a data write to XOR the existing contents of the registers with the new data written. To use the XOR function, the data must be written to AES_XORDATA location. Reading data from AES_XORDATA is equivalent to reading data from AES_DATA. 27.3.2.3 Start on Data Write The AES module can be configured to start an encryption/decryption when the new data has been written to AES_DATA and/or AES_XORDATA. A 2-bit counter is incremented each time the AES_DATA or AES_XORDATA registers are written. This counter indicates which data word is written. If DATASTART/ XORSTART in AES_CTRL is set, an encryption will start each time the counter overflows (DATA3 is written). Writing to the AES_CTRL register will reset the counter to 0. 27.3.3 Interrupt Request The DONE interrupt flag is set when an encryption/ decryption has finished. 27.3.4 DMA Request The AES module has 4 DMA requests which are all set on a finished encryption/decryption and cleared on the following conditions: 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 455 www.silabs.com ...the world's most energy friendly microcontrollers • • • • DATAWR: Cleared on a AES_DATA write or AES_CTRL write XORDATAWR: Cleared on a AES_XORDATA write or AES_CTRL write DATARD: Cleared on a AES_DATA read or AES_CTRL write KEYWR: Cleared on a AES_KEYHn write or AES_CTRL write 27.3.5 Block Chaining Example Example 27.1 (p. 456) below illustrates how the AES module could be configured to perform Cipher Block Chaining with 128-bit keys. Example 27.1. AES Cipher Block Chaining 1. 2. 3. 4. Configure module to encryption, key buffer enabled and XORSTART in AES_CTRL. Write 128-bit initialization vector to AES_DATA, starting with least significant word. Write PlainKey to AES_KEYHn, starting with least significant word. Write PlainText to AES_XORDATA, starting with least significant word. Encryption will be started when the DATA3 is written. KEYH (PlainKey) will be copied to KEYL before encryption starts. 5. When encryption finished, read CipherText from AES_DATA, starting with least significant word. 6. Loop to step 4, if new PlainText is available. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 456 www.silabs.com ...the world's most energy friendly microcontrollers 27.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 AES_CTRL RW Control Register 0x004 AES_CMD W1 Command Register 0x008 AES_STATUS R Status Register 0x00C AES_IEN RW Interrupt Enable Register 0x010 AES_IF R Interrupt Flag Register 0x014 AES_IFS W1 Interrupt Flag Set Register 0x018 AES_IFC W1 Interrupt Flag Clear Register 0x01C AES_DATA RW DATA Register 0x020 AES_XORDATA RW XORDATA Register 0x030 AES_KEYLA RW KEY Low Register 0x034 AES_KEYLB RW KEY Low Register 0x038 AES_KEYLC RW KEY Low Register 0x03C AES_KEYLD RW KEY Low Register 0x040 AES_KEYHA RW KEY High Register 0x044 AES_KEYHB RW KEY High Register 0x048 AES_KEYHC RW KEY High Register 0x04C AES_KEYHD RW KEY High Register 27.5 Register Description 27.5.1 AES_CTRL - Control Register Access 0 RW DECRYPT 0 2 1 0 RW AES256 0 RW KEYBUFEN 3 4 0 RW 6 5 0 DATASTART Name RW RW BYTEORDER Access XORSTART 7 8 0 Reset 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x000 Bit Position 31 Offset Bit Name Reset Description 31:7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 6 BYTEORDER 0 RW Configure byte order in data and key registers When set, the byte orders in the data and key registers are swapped before and after encryption/decryption. 5 XORSTART 0 RW AES_XORDATA Write Start Set this bit to start encryption/decryption when DATA3 is written through AES_XORDATA. 4 DATASTART 0 RW AES_DATA Write Start Set this bit to start encryption/decryption when DATA3 is written through AES_DATA. 3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 2 KEYBUFEN 0 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 RW Key Buffer Enable 457 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description RW AES-256 Mode RW Decryption/Encryption Mode Enable/disable key buffer in AES-128 mode. 1 AES256 0 Select AES-128 or AES-256 mode. 0 Value Description 0 AES-128 mode 1 AES-256 mode DECRYPT 0 Select encryption or decryption. Value Description 0 AES Encryption 1 AES Decryption 27.5.2 AES_CMD - Command Register Offset STOP Name Access 0 0 W1 Access START W1 0 Reset 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x004 Bit Position Bit Name Reset Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 1 STOP 0 W1 Encryption/Decryption Stop W1 Encryption/Decryption Start Set to stop encryption/decryption. 0 START 0 Set to start encryption/decryption. 27.5.3 AES_STATUS - Status Register 0 1 2 3 4 5 6 7 8 9 10 11 0 Reset 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x008 Bit Position 31 Offset RUNNING R Access Name Bit Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 0 RUNNING 0 R AES Running This bit indicates that the AES module is running an encryption/decryption. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 458 www.silabs.com ...the world's most energy friendly microcontrollers 27.5.4 AES_IEN - Interrupt Enable Register RW 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x00C Bit Position 31 Offset DONE Access Name Bit Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 0 DONE 0 RW Encryption/Decryption Done Interrupt Enable Enable/disable interrupt on encryption/decryption done. 27.5.5 AES_IF - Interrupt Flag Register 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x010 Bit Position 31 Offset DONE R Access Name Bit Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 0 DONE 0 R Encryption/Decryption Done Interrupt Flag Set when an encryption/decryption has finished. 27.5.6 AES_IFS - Interrupt Flag Set Register Offset 0 1 2 W1 0 Reset 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x014 Bit Position DONE Access Name Bit Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 0 DONE 0 W1 Encryption/Decryption Done Interrupt Flag Set Write to 1 to set encryption/decryption done interrupt flag 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 459 www.silabs.com ...the world's most energy friendly microcontrollers 27.5.7 AES_IFC - Interrupt Flag Clear Register W1 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x018 Bit Position 31 Offset DONE Access Name Bit Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 0 DONE 0 W1 Encryption/Decryption Done Interrupt Flag Clear Write to 1 to clear encryption/decryption done interrupt flag 27.5.8 AES_DATA - DATA Register 2 1 0 2 1 0 6 6 3 7 7 3 8 8 4 9 9 4 10 10 5 11 11 5 12 13 12 14 15 16 0x00000000 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x01C 17 Bit Position Offset RW Reset DATA Access Name Bit Name Reset Access Description 31:0 DATA 0x00000000 RW Data Access Access data through this register. 27.5.9 AES_XORDATA - XORDATA Register 13 14 15 RW Reset XORDATA Access Name 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 16 0x00000000 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x020 Bit Position 31 Offset 460 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description 31:0 XORDATA 0x00000000 RW XOR Data Access Access data with XOR function through this register. 27.5.10 AES_KEYLA - KEY Low Register 3 2 1 0 2 1 0 6 6 3 7 7 4 8 8 4 9 9 5 10 10 5 11 12 11 13 14 15 16 0x00000000 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x030 Bit Position 31 Offset RW Reset KEYLA Access Name Bit Name Reset Access Description 31:0 KEYLA 0x00000000 RW Key Low Access A Access the low key words through this register. 27.5.11 AES_KEYLB - KEY Low Register Offset 12 13 14 15 16 0x00000000 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x034 Bit Position RW Reset KEYLB Access Name Bit Name Reset Access Description 31:0 KEYLB 0x00000000 RW Key Low Access B Access the low key words through this register. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 461 www.silabs.com ...the world's most energy friendly microcontrollers 27.5.12 AES_KEYLC - KEY Low Register 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0x00000000 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x038 Bit Position 31 Offset RW Reset KEYLC Access Name Bit Name Reset Access Description 31:0 KEYLC 0x00000000 RW Key Low Access C Access the low key words through this register. 27.5.13 AES_KEYLD - KEY Low Register 3 2 1 0 2 1 0 6 6 3 7 7 4 8 8 4 9 9 5 10 10 5 11 11 12 13 14 15 16 0x00000000 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x03C Bit Position 31 Offset RW Reset KEYLD Access Name Bit Name Reset Access Description 31:0 KEYLD 0x00000000 RW Key Low Access D Access the low key words through this register. 27.5.14 AES_KEYHA - KEY High Register 12 13 14 15 RW Reset KEYHA Access Name 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 16 0x00000000 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x040 17 Bit Position Offset 462 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description 31:0 KEYHA 0x00000000 RW Key High Access A Access the high key words through this register. 27.5.15 AES_KEYHB - KEY High Register 3 2 1 0 3 2 1 0 6 6 4 7 7 4 8 8 5 9 9 5 10 10 11 12 13 14 15 16 0x00000000 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x044 Bit Position 31 Offset RW Reset KEYHB Access Name Bit Name Reset Access Description 31:0 KEYHB 0x00000000 RW Key High Access B Access the high key words through this register. 27.5.16 AES_KEYHC - KEY High Register Offset 11 12 13 14 15 16 0x00000000 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x048 Bit Position RW Reset KEYHC Access Name Bit Name Reset Access Description 31:0 KEYHC 0x00000000 RW Key High Access C Access the high key words through this register. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 463 www.silabs.com ...the world's most energy friendly microcontrollers 27.5.17 AES_KEYHD - KEY High Register Offset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0x00000000 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x04C Bit Position RW Reset KEYHD Access Name Bit Name Reset Access Description 31:0 KEYHD 0x00000000 RW Key High Access D Access the high key words through this register. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 464 www.silabs.com ...the world's most energy friendly microcontrollers 28 GPIO - General Purpose Input/Output Quick Facts What? 0 1 2 3 The GPIO (General Purpose Input/Output) is used for pin configuration and direct pin manipulation and sensing as well as routing for peripheral pin connections. 4 Why? Easy to use and highly configurable input/ output pins are important to fit many communication protocols as well as minimizing software control overhead. Flexible routing of peripheral functions helps to ease PCB layout. EFM32 MCU GPIO How? Peripherals Each pin on the device can be individually configured as either an input or an output with several different drive modes. Also, individual bit manipulation registers minimizes control overhead. Peripheral connections to pins can be routed to several different locations, thus solving congestion issues that may arise with multiple functions on the same pin. Fully asynchronous interrupts can also be generated from any pin. ARM Cortex - M3 28.1 Introduction In the EFM32TG devices the General Purpose Input/Output (GPIO) pins are organized into ports with up to 16 pins each. These pins can individually be configured as either an output or input. More advanced configurations like open-drain, filtering and drive strength can also be configured individually for the pins. The GPIO pins can also be overridden by peripheral pin connections, like Timer PWM outputs or USART communication, which can be routed to several locations on the device. The GPIO supports up to 16 asynchronous external pin interrupts, which enables interrupts from any pin on the device. Also, the input value of a pin can be routed through the Peripheral Reflex System to other peripherals. 28.2 Features • Individual configuration for each pin • Tristate (reset state) • Push-pull • Open-drain • Pull-up resistor • Pull-down resistor • Four drive strength modes • HIGH • STANDARD • LOW • LOWEST 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 465 www.silabs.com ...the world's most energy friendly microcontrollers • EM4 IO pin retention. This includes • Output enable • Output value • Pull enable • Pull direction • EM4 wake-up on selected GPIO pins • Glitch suppression input filter. • Analog connection to e.g. ADC or LCD. • Alternate functions (e.g. peripheral outputs and inputs) • Routed to several locations on the device • Pin connections can be enabled individually • Output data can be overridden by peripheral • Output enable can be overridden by peripheral • Toggle, set and clear registers for output data • Dedicated data input register (read-only) • Interrupts • 2 interrupt lines from up to 16 pending sources • All GPIO pins are selectable • Separate enable, status, set and clear registers • Asynchronous sensing • Rising, falling or both edges • Wake up from EM0-EM3 • Peripheral Reflex System producer • All GPIO pins are selectable • Configuration lock functionality to avoid accidental changes 28.3 Functional Description An overview of the GPIO module is shown in Figure 28.1 (p. 467) .The GPIO pins are grouped into 16pin ports. Each individual GPIO pin is called Pxn where x indicates the port (A, B, C ...) and n indicates the pin number (0,1,....,15). Fewer than 16 bits may be available on some ports, depending on the total number of I/O pins on the package. After a reset both input and output is disabled for all pins on the device, except for debug pins. To use a pin, the port GPIO_Px_MODEL/GPIO_Px_MODEH registers must be configured for the pin to make it an input or output. These registers can also do more advanced configuration, which is covered in Section 28.3.1 (p. 467) . When the port is either configured as an input or an output, the Data In Register (GPIO_Px_DIN) can be used to read the level of each pin in the port (bit n in the register is connected to pin n on the port). When configured as an output, the value of the Data Out Register (GPIO_Px_DOUT) will be driven to the pin. The DOUT value can be changed in 4 different ways • • • • Writing to the GPIO_Px_DOUT register. Writing a 1 to a bit in the GPIO_Px_DOUTSET register sets the corresponding DOUT bit Writing a 1 to a bit in the GPIO_Px_DOUTCLR register clears the corresponding DOUT bit Writing a 1 to a bit in the GPIO_Px_DOUTTGL register toggles the corresponding DOUT bit Reading the GPIO_Px_DOUT register will return its contents. Reading the GPIO_Px_DOUTSET, GPIO_Px_CLR or GPIO_Px_TGL will return 0. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 466 www.silabs.com ...the world's most energy friendly microcontrollers Figure 28.1. Pin Configuration Alternate function override Alternate function output enable Alternate function data out Port Control Output enable Output enable 1 VDD Data out Output value DOUT ESD protection Pull- up enable Pull- down enable MODEn[3:0] Input enable ESD diode Filter enable DIN VSS Glitch suppression filter Alternate function input Interrupt input PRS Analog connection Note There is no ESD diode to Vdd because if using LCD voltage boost the pin voltage will be higher than Vdd. Nevertheless there is an ESD protection block against over voltage. 28.3.1 Pin Configuration In addition to setting the pins as either outputs or inputs, the GPIO_Px_MODEL and GPIO_Px_MODEH registers can be used for more advanced configurations. GPIO_Px_MODEL contains 8 bit fields named MODEn (n=0,1,..7) which control pins 0-7, while GPIO_Px_MODEH contains 8 bit fields named MODEn (n=8,9,..15) which control pins 8-15. In some modes GPIO_Px_DOUT is also used for extra configurations like pull-up/down and glitch suppression filter enable. Table 28.1 (p. 467) shows the available configurations. Table 28.1. Pin Configuration MODEn Input Output DOUT 0b0000 Disabled Disabled 0 Pulldown Enabled On 0 0 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 Description Input disabled with pull-up Input enabled 1 0b0010 Alt. Input strength Filter Input disabled 1 0b0001 Pullup On On Input enabled with filter Input enabled with pull-down 467 www.silabs.com ...the world's most energy friendly microcontrollers MODEn Input Output DOUT Pulldown 1 0b0011 0 Push-pull x 0b0110 Open x Source (Wired-OR) x 0b1000 Description Input enabled with pull-up On On On Input enabled with pull-down and filter On Input enabled with pull-up and filter x 0b0101 0b0111 Alt. Input strength Filter On 1 0b0100 Pullup Push-pull On Push-pull with alt. drive strength Open-source On Open-source with pull-down 0b1001 Open Drain x (Wiredx AND) Open-drain 0b1010 x On 0b1011 x On 0b1100 x On 0b1101 x On 0b1110 x On On 0b1111 x On On On Open-drain with filter Open-drain with pull-up On Open-drain with pull-up and filter Open-drain with alt. drive strength On Open-drain with alt. drive strength and filter Open-drain with alt. drive strength and pull-up On Open-drain with alt. drive strength, pull-up and filter MODEn determines which mode the pin is in at a given time. Setting MODEn to 0b0000 disables the pin, reducing power consumption to a minimum. When the output driver is disabled, the pin can be used as a connection for an analog module (e.g. ADC, LCD...). Input is enabled by setting MODEn to any value other than 0b0000. The pull-up, pull-down and filter function can optionally be applied to the input, see Figure 28.2 (p. 468) . The internal pull-up resistance, RPU, and pull-down resistance, RPD, are defined in the device datasheet. When the filter is enabled it suppresses glitches with pulse widths as defined by the parameter tIOGLITCH in the device datasheet. Figure 28.2. Tristated Output with Optional Pull-up or Pull-down VDD Filter enable Optional pull- up Input enable DIN Glitch suppression filter Optional pull- down Analog connection VSS When MODEn=0b0100 or MODEn=0b0101, the pin operates in push-pull mode. In this mode, the pin is driven either high or low, dependent on the value of GPIO_Px_DOUT. The push-pull configuration is shown in Figure 28.3 (p. 469) . 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 468 www.silabs.com ...the world's most energy friendly microcontrollers Figure 28.3. Push-Pull Configuration Output Enable DOUT Input Enable DIN When MODEn is 0110 or 0111, the pin operates in open-source mode, the latter with a pull-down resistor. When driving a high value in open-source mode, the pull-down is disconnected to save power. For the remaining MODEn values, i.e. MODEn >= 1000, the pin operates in open-drain mode as shown in Figure 28.4 (p. 469) . In open-drain mode, the pin can have an input filter, a pull-up, different driver strengths or any combination of these. When driving a low value in open-drain mode, the pull-up is disconnected to save power. Figure 28.4. Open-drain VDD Filter enable DIN Optional pull- up Glitch suppression filter DOUT VSS When MODEn=0b0101 or 0b11xx, the output driver uses the drive strength specified in DRIVEMODE in GPIO_Px_CTRL. In all other output modes, the drive strength is set to STANDARD. 28.3.1.1 Configuration Lock GPIO_Px_MODEL, GPIO_Px_MODEH, GPIO_Px_CTRL, GPIO_Px_PINLOCKN, GPIO_EXTIPSELL, GPIO_EXTIPSELH, GPIO_INSENSE and GPIO_ROUTE can be locked by writing any other value than 0xA534 to GPIO_LOCK. Writing the value 0xA534 to the GPIOx_LOCK register unlocks the configuration registers. In addition to configuration lock, GPIO_Px_MODEL, GPIO_Px_MODEH, GPIO_Px_DOUT, GPIO_Px_DOUTSET, GPIO_Px_DOUTCLR, and GPIO_Px_DOUTTGL can be locked individually for each pin by clearing the corresponding bit in GPIO_Px_PINLOCKN. Bits in the GPIO_Px_PINLOCKN register can only be cleared, they are set high again after reset. 28.3.2 EM4 Wake-up It is possible to wake-up from EM4 through reset triggered from any of up to 6 selectable GPIO pins. For the wake-up logic to work correctly, EM4 retention needs to be enabled before entering EM4, as described in Section 28.3.3 (p. 470) The wake-up request can be triggered through the pins by enabling the corresponding bit in the GPIO_EM4WUEN register. When EM4 wake-up is enabled for the 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 469 www.silabs.com ...the world's most energy friendly microcontrollers pin, the input filter is enabled during EM4. This is done to avoid false wake-up caused by glitches. In addition, the polarity of the EM4 wake-up request can be selected using the GPIO_EM4WUPOL register. Figure 28.5. EM4 Wake-up Logic GPIO_EM4WUCAUSE GPIO_CMD GPIO_EM4WUEN GPIO_EM4WUPOL Wake- up Logic Wake- up request The pins used for EM4 wake-up must be configured as inputs using the GPIO_Px_MODEL/ GPIO_Px_MODEH register. Before going down to EM4, it is important to clear the wake-up logic by setting the EM4WUCLR bitfield in the GPIO_CMD register, which clears the complete wake-up logic, including the GPIO_EM4WUCAUSE register. When the chip comes out of reset, it is possible to determine what caused the reset by reading the RMU_RSTCAUSE register. If an EM4 wake-up reset occurred, the EM4RST (indicating the chip was in EM4) and the EM4WU (indicating the EM4 wake-up reset) bits should be set. It is possible to determine which pin caused the reset by reading the GPIO_EM4WUCAUSE register. The mapping between pins and the bits in the GPIO_EM4WUEN, GPIO_EM4WUPOL, and GPIO_EM4WUCAUSE registers are described in Table 28.2 (p. 470) Table 28.2. EM4 WU Register bits to pin mapping Wake-up Registers Bits Pin bit 0 A0 bit 1 A6 bit 2 C9 bit 3 F1 bit 4 F2 bit 5 E13 28.3.3 EM4 Retention It is possible to enable retention of output enable, output value, pull enable and pull direction when in EM4. EM4 retention also makes it possible to wake up from EM4 on pin reset as described in Section 28.3.2 (p. 469) EM4 retention can be enabled by setting the EM4RET field in GPIO_CTRL register before going down in EM4. 28.3.4 Alternate Functions Alternate functions are connections to pins from Timers, USARTs etc. These modules contain route registers, where the pin connections are enabled. In addition, these registers contain a location bit field, which configures which pins the outputs of that module will be connected to if they are enabled. If an alternate signal output is enabled for a pin and output is enabled for the pin, the alternate 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 470 www.silabs.com ...the world's most energy friendly microcontrollers function’s output data and output enable signals override the data output and output enable signals from the GPIO. However, the pin configuration stays as set in GPIO_Px_MODEL, GPIO_Px_MODEH and GPIO_Px_DOUT registers. I.e. the pin configuration must be set to output enable in GPIO for a peripheral to be able to use the pin as an output. It is possible, but not recommended to select two or more peripherals as output on the same pin. These signals will then be OR'ed together. However, TIMER CCx outputs, which are routed as alternate functions, have priority, and will never be OR'ed with other alternate functions. The reader is referred to the pin map section of the device datasheet for more information on the possible locations of each alternate function and any priority settings. 28.3.4.1 Serial Wire Debug Port Connection The SW Debug Port is routed as an alternate function and the SWDIO and SWCLK pin connections are enabled by default with internal pull-up and pull-down resistors, respectively. It is possible to disable these pin connections (and disable the pull resistors) by setting the SWDIOPEN and SWCLKPEN bits in GPIO_ROUTE to 0. WARNING: When the debug pins are disabled, the device can no longer be accessed by a debugger. A reset will set the debug pins back to their default state as enabled. If you do disable the debug pins, make sure you have at least a 3 second timeout at the start of your program code before you disable the debug pins. This way the debugger will have time to halt the device after a reset before the pins are disabled. The Serial Wire Viewer Output pin (SWO) can be enabled by setting the SWOPEN bit in GPIO_ROUTE. This bit can also be routed to alternate locations by configuring the LOCATION bitfield in GPIO_ROUTE. 28.3.4.2 Analog Connections When using the GPIO pin for analog functionality, it is recommended to disable the digital output and set the MODEn in GPIO_Px_MODEL/GPIO_Px_MODEH equal to 0b0000 to disable the input sense and pull resistors. 28.3.5 Interrupt Generation The GPIO can generate an interrupt from the input of any GPIO pin on a device. The interrupts have asynchronous sense capability, enabling wake-up from energy modes as low as EM3, see Figure 28.6 (p. 471) . Figure 28.6. Pin n Interrupt Generation EXTIPSELn[2:0] EXTIRISE[n] PAn PBn PCn PDn PEn PFn IFS[n] IFC[n] IEN[n] wakeup set Synch clear IRQ_GPIO_EVEN/ IRQ_GPIO_ODD IF[n] Odd/ even inputs EXTIFALL[n] PRS All pins with the same pin number (n) are grouped together to trigger one interrupt flag (EXT[n] in GPIO_IF). The EXTIPSELn[2:0] bits in GPIO_EXTIPSELL or GPIO_EXTIPSELH select which port will trigger the interrupt flag. The GPIO_EXTIRISE[n] and GPIO_EXTIFALL[n] registers enables sensing of rising and falling edges. By setting the EXT[n] bit in GPIO_IEN, a high interrupt flag n, will trigger one of two interrupt lines. The even interrupt line is triggered by any enabled even numbered interrupt flag, 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 471 www.silabs.com ...the world's most energy friendly microcontrollers while the odd is triggered by odd flags. The interrupt flags can be set and cleared by software by writing the GPIO_IFS and GPIO_IFC registers, see Example 28.1 (p. 472) . Since the external interrupts are asynchronous, they are sensitive to noise. To increase noise tolerance, the MODEL and MODEH fields in the GPIO_Px_MODEL and GPIO_Px_MODEH registers, respectively, should be set to include filtering for pins that have external interrupts enabled. Example 28.1. GPIO Interrupt Example Setting EXTIPSEL3 in GPIO_EXTIPSELL to 2 (Port C) and setting the GPIO_EXTIRISE[3] bit, the interrupt flag EXT[3] in GPIO_IF will be triggered by a rising edge on pin 3 on PORT C. If EXT[3] in GPIO_IEN is set as well, a interrupt request will be sent on IRQ_GPIO_ODD. 28.3.6 Output to PRS All pins with the same pin number (n) are grouped together to form one PRS producer output, giving a total of 16 outputs to the PRS. The port on which the output n should be taken is selected by the EXTIPSELn[3:0] bits in the GPIO_EXTIPSELL or the GPIO_EXTIPSELH registers. 28.3.7 Synchronization To avoid metastability in synchronous logic connected to the pins, all inputs are synchronized with double flip-flops. The flip-flops for the input data run on the HFCORECLK. Consequently, when a pin changes state, the change will have propagated to GPIO_Px_DIN after 2 positive HFCORECLK edges, or maximum 2 HFCORECLK cycles. Synchronization (also running on the HFCORECLK) is also added for interrupt input. The input to the PRS generation is also synchronized, but these flip-flops run on the HFPERCLK. To save power when the external interrupts or PRS generation is not used, the synchronization flip-flops for these can be turned off by clearing the INTSENSE or PRSSENSE, respectively, in GPIO_INSENSE register. Note To use the GPIO, the GPIO clock must first be enabled in CMU_HFPERCLKEN0. Setting this bit enables the HFCORECLK and the HFPERCLK for the GPIO. HFCORECLK is used for updating registers, while HFPERCLK is only used to synchronize PRS and interrupts. The PRS and interrupt synchronization can also be disabled through GPIO_INSENSE, if these are not used. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 472 www.silabs.com ...the world's most energy friendly microcontrollers 28.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 GPIO_PA_CTRL RW Port Control Register 0x004 GPIO_PA_MODEL RW Port Pin Mode Low Register 0x008 GPIO_PA_MODEH RW Port Pin Mode High Register 0x00C GPIO_PA_DOUT RW Port Data Out Register 0x010 GPIO_PA_DOUTSET W1 Port Data Out Set Register 0x014 GPIO_PA_DOUTCLR W1 Port Data Out Clear Register 0x018 GPIO_PA_DOUTTGL W1 Port Data Out Toggle Register 0x01C GPIO_PA_DIN R Port Data In Register 0x020 GPIO_PA_PINLOCKN RW Port Unlocked Pins Register 0x024 GPIO_PB_CTRL RW Port Control Register 0x028 GPIO_PB_MODEL RW Port Pin Mode Low Register 0x02C GPIO_PB_MODEH RW Port Pin Mode High Register 0x030 GPIO_PB_DOUT RW Port Data Out Register 0x034 GPIO_PB_DOUTSET W1 Port Data Out Set Register 0x038 GPIO_PB_DOUTCLR W1 Port Data Out Clear Register 0x03C GPIO_PB_DOUTTGL W1 Port Data Out Toggle Register 0x040 GPIO_PB_DIN R Port Data In Register 0x044 GPIO_PB_PINLOCKN RW Port Unlocked Pins Register 0x048 GPIO_PC_CTRL RW Port Control Register 0x04C GPIO_PC_MODEL RW Port Pin Mode Low Register 0x050 GPIO_PC_MODEH RW Port Pin Mode High Register 0x054 GPIO_PC_DOUT RW Port Data Out Register 0x058 GPIO_PC_DOUTSET W1 Port Data Out Set Register 0x05C GPIO_PC_DOUTCLR W1 Port Data Out Clear Register 0x060 GPIO_PC_DOUTTGL W1 Port Data Out Toggle Register 0x064 GPIO_PC_DIN R Port Data In Register 0x068 GPIO_PC_PINLOCKN RW Port Unlocked Pins Register 0x06C GPIO_PD_CTRL RW Port Control Register 0x070 GPIO_PD_MODEL RW Port Pin Mode Low Register 0x074 GPIO_PD_MODEH RW Port Pin Mode High Register 0x078 GPIO_PD_DOUT RW Port Data Out Register 0x07C GPIO_PD_DOUTSET W1 Port Data Out Set Register 0x080 GPIO_PD_DOUTCLR W1 Port Data Out Clear Register 0x084 GPIO_PD_DOUTTGL W1 Port Data Out Toggle Register 0x088 GPIO_PD_DIN R Port Data In Register 0x08C GPIO_PD_PINLOCKN RW Port Unlocked Pins Register 0x090 GPIO_PE_CTRL RW Port Control Register 0x094 GPIO_PE_MODEL RW Port Pin Mode Low Register 0x098 GPIO_PE_MODEH RW Port Pin Mode High Register 0x09C GPIO_PE_DOUT RW Port Data Out Register 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 473 www.silabs.com ...the world's most energy friendly microcontrollers Offset Name Type Description 0x0A0 GPIO_PE_DOUTSET W1 Port Data Out Set Register 0x0A4 GPIO_PE_DOUTCLR W1 Port Data Out Clear Register 0x0A8 GPIO_PE_DOUTTGL W1 Port Data Out Toggle Register 0x0AC GPIO_PE_DIN R Port Data In Register 0x0B0 GPIO_PE_PINLOCKN RW Port Unlocked Pins Register 0x0B4 GPIO_PF_CTRL RW Port Control Register 0x0B8 GPIO_PF_MODEL RW Port Pin Mode Low Register 0x0BC GPIO_PF_MODEH RW Port Pin Mode High Register 0x0C0 GPIO_PF_DOUT RW Port Data Out Register 0x0C4 GPIO_PF_DOUTSET W1 Port Data Out Set Register 0x0C8 GPIO_PF_DOUTCLR W1 Port Data Out Clear Register 0x0CC GPIO_PF_DOUTTGL W1 Port Data Out Toggle Register 0x0D0 GPIO_PF_DIN R Port Data In Register 0x0D4 GPIO_PF_PINLOCKN RW Port Unlocked Pins Register 0x100 GPIO_EXTIPSELL RW External Interrupt Port Select Low Register 0x104 GPIO_EXTIPSELH RW External Interrupt Port Select High Register 0x108 GPIO_EXTIRISE RW External Interrupt Rising Edge Trigger Register 0x10C GPIO_EXTIFALL RW External Interrupt Falling Edge Trigger Register 0x110 GPIO_IEN RW Interrupt Enable Register 0x114 GPIO_IF R Interrupt Flag Register 0x118 GPIO_IFS W1 Interrupt Flag Set Register 0x11C GPIO_IFC W1 Interrupt Flag Clear Register 0x120 GPIO_ROUTE RW I/O Routing Register 0x124 GPIO_INSENSE RW Input Sense Register 0x128 GPIO_LOCK RW Configuration Lock Register 0x12C GPIO_CTRL RW GPIO Control Register 0x130 GPIO_CMD W1 GPIO Command Register 0x134 GPIO_EM4WUEN RW EM4 Wake-up Enable Register 0x138 GPIO_EM4WUPOL RW EM4 Wake-up Polarity Register 0x13C GPIO_EM4WUCAUSE R EM4 Wake-up Cause Register 28.5 Register Description 28.5.1 GPIO_Px_CTRL - Port Control Register Offset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RW 0x0 Reset DRIVEMODE Access Name 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x000 Bit Position 474 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 1:0 DRIVEMODE 0x0 RW Drive Mode Select Select drive mode for all pins on port configured with alternate drive strength. Value Mode Description 0 STANDARD 6 mA drive current 1 LOWEST 0.1 mA drive current 2 HIGH 20 mA drive current 3 LOW 1 mA drive current 28.5.2 GPIO_Px_MODEL - Port Pin Mode Low Register Bit Name Reset Access Description 31:28 MODE7 0x0 RW Pin 7 Mode 0 1 2 RW 0x0 MODE0 3 4 5 6 RW 0x0 MODE1 7 8 9 10 RW 0x0 MODE2 11 12 13 14 RW 0x0 MODE3 15 16 17 18 MODE4 RW 0x0 19 20 21 22 MODE5 RW 0x0 23 24 25 26 RW 0x0 27 28 MODE6 Name 29 30 Access RW 0x0 Reset MODE7 0x004 Bit Position 31 Offset Configure mode for pin 7. Enumeration is equal to MODE0. 27:24 MODE6 0x0 RW Pin 6 Mode Configure mode for pin 6. Enumeration is equal to MODE0. 23:20 MODE5 0x0 RW Pin 5 Mode Configure mode for pin 5. Enumeration is equal to MODE0. 19:16 MODE4 0x0 RW Pin 4 Mode Configure mode for pin 4. Enumeration is equal to MODE0. 15:12 MODE3 0x0 RW Pin 3 Mode Configure mode for pin 3. Enumeration is equal to MODE0. 11:8 MODE2 0x0 RW Pin 2 Mode Configure mode for pin 2. Enumeration is equal to MODE0. 7:4 MODE1 0x0 RW Pin 1 Mode Configure mode for pin 1. Enumeration is equal to MODE0. 3:0 MODE0 0x0 RW Pin 0 Mode Configure mode for pin 0. Value Mode Description 0 DISABLED Input disabled. Pullup if DOUT is set. 1 INPUT Input enabled. Filter if DOUT is set 2 INPUTPULL Input enabled. DOUT determines pull direction 3 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction 4 PUSHPULL Push-pull output 5 PUSHPULLDRIVE Push-pull output with drive-strength set by DRIVEMODE 6 WIREDOR Wired-or output 7 WIREDORPULLDOWN Wired-or output with pull-down 8 WIREDAND Open-drain output 9 WIREDANDFILTER Open-drain output with filter 10 WIREDANDPULLUP Open-drain output with pullup 11 WIREDANDPULLUPFILTER Open-drain output with filter and pullup 12 WIREDANDDRIVE Open-drain output with drive-strength set by DRIVEMODE 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 475 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description Value Mode Description 13 WIREDANDDRIVEFILTER Open-drain output with filter and drive-strength set by DRIVEMODE 14 WIREDANDDRIVEPULLUP Open-drain output with pullup and drive-strength set by DRIVEMODE 15 WIREDANDDRIVEPULLUPFILTER Open-drain output with filter, pullup and drive-strength set by DRIVEMODE 28.5.3 GPIO_Px_MODEH - Port Pin Mode High Register Bit Name Reset Access Description 31:28 MODE15 0x0 RW Pin 15 Mode 0 1 2 RW 0x0 MODE8 3 4 5 6 RW 0x0 MODE9 7 8 9 10 RW 0x0 MODE10 11 12 13 14 RW 0x0 MODE11 15 16 17 18 MODE12 RW 0x0 19 20 21 22 MODE13 RW 0x0 23 24 25 26 RW 0x0 27 28 MODE14 Name 29 30 Access RW 0x0 Reset MODE15 0x008 Bit Position 31 Offset Configure mode for pin 15. Enumeration is equal to MODE8. 27:24 MODE14 0x0 RW Pin 14 Mode Configure mode for pin 14. Enumeration is equal to MODE8. 23:20 MODE13 0x0 RW Pin 13 Mode Configure mode for pin 13. Enumeration is equal to MODE8. 19:16 MODE12 0x0 RW Pin 12 Mode Configure mode for pin 12. Enumeration is equal to MODE8. 15:12 MODE11 0x0 RW Pin 11 Mode Configure mode for pin 11. Enumeration is equal to MODE8. 11:8 MODE10 0x0 RW Pin 10 Mode Configure mode for pin 10. Enumeration is equal to MODE8. 7:4 MODE9 0x0 RW Pin 9 Mode Configure mode for pin 9. Enumeration is equal to MODE8. 3:0 MODE8 0x0 RW Pin 8 Mode Configure mode for pin 8. Value Mode Description 0 DISABLED Input disabled. Pullup if DOUT is set. 1 INPUT Input enabled. Filter if DOUT is set 2 INPUTPULL Input enabled. DOUT determines pull direction 3 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction 4 PUSHPULL Push-pull output 5 PUSHPULLDRIVE Push-pull output with drive-strength set by DRIVEMODE 6 WIREDOR Wired-or output 7 WIREDORPULLDOWN Wired-or output with pull-down 8 WIREDAND Open-drain output 9 WIREDANDFILTER Open-drain output with filter 10 WIREDANDPULLUP Open-drain output with pullup 11 WIREDANDPULLUPFILTER Open-drain output with filter and pullup 12 WIREDANDDRIVE Open-drain output with drive-strength set by DRIVEMODE 13 WIREDANDDRIVEFILTER Open-drain output with filter and drive-strength set by DRIVEMODE 14 WIREDANDDRIVEPULLUP Open-drain output with pullup and drive-strength set by DRIVEMODE 15 WIREDANDDRIVEPULLUPFILTER Open-drain output with filter, pullup and drive-strength set by DRIVEMODE 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 476 www.silabs.com ...the world's most energy friendly microcontrollers 28.5.4 GPIO_Px_DOUT - Port Data Out Register 0 1 2 3 4 5 6 7 8 0x0000 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x00C Bit Position 31 Offset RW Reset DOUT Access Name Bit Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 DOUT 0x0000 RW Data Out Data output on port. 28.5.5 GPIO_Px_DOUTSET - Port Data Out Set Register 0 1 2 3 4 5 6 7 8 0x0000 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x010 Bit Position 31 Offset W1 Reset DOUTSET Access Name Bit Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 DOUTSET 0x0000 W1 Data Out Set Write bits to 1 to set corresponding bits in GPIO_Px_DOUT. Bits written to 0 will have no effect. 28.5.6 GPIO_Px_DOUTCLR - Port Data Out Clear Register 0 1 2 3 4 5 6 7 8 0x0000 9 10 11 12 13 14 15 W1 Reset DOUTCLR Access Name 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x014 Bit Position 31 Offset 477 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 DOUTCLR 0x0000 W1 Data Out Clear Write bits to 1 to clear corresponding bits in GPIO_Px_DOUT. Bits written to 0 will have no effect. 28.5.7 GPIO_Px_DOUTTGL - Port Data Out Toggle Register 0 1 2 3 4 5 6 7 8 0x0000 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x018 Bit Position 31 Offset W1 Reset DOUTTGL Access Name Bit Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 DOUTTGL 0x0000 W1 Data Out Toggle Write bits to 1 to toggle corresponding bits in GPIO_Px_DOUT. Bits written to 0 will have no effect. 28.5.8 GPIO_Px_DIN - Port Data In Register 0 1 2 3 4 5 6 7 8 0x0000 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x01C Bit Position 31 Offset Reset R Access DIN Name Bit Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 DIN 0x0000 R Data In Port data input. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 478 www.silabs.com ...the world's most energy friendly microcontrollers 28.5.9 GPIO_Px_PINLOCKN - Port Unlocked Pins Register 0 1 2 3 4 5 6 7 8 0xFFFF 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x020 Bit Position 31 Offset RW Reset PINLOCKN Access Name Bit Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 PINLOCKN 0xFFFF RW Unlocked Pins Shows unlocked pins in the port. To lock pin n, clear bit n. The pin is then locked until reset. 28.5.10 GPIO_EXTIPSELL - External Interrupt Port Select Low Register Access 0 1 2 RW 0x0 EXTIPSEL0 3 4 RW 0x0 EXTIPSEL1 5 6 7 8 9 RW 0x0 EXTIPSEL2 10 11 12 14 13 RW 0x0 EXTIPSEL3 15 17 EXTIPSEL4 RW 0x0 18 19 20 21 EXTIPSEL5 RW 0x0 22 23 24 25 26 RW 0x0 27 28 EXTIPSEL6 Name 29 30 Access RW 0x0 Reset EXTIPSEL7 31 0x100 16 Bit Position Offset Bit Name Reset Description 31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 30:28 EXTIPSEL7 0x0 RW External Interrupt 7 Port Select Select input port for external interrupt 7. Value Mode Description 0 PORTA Port A pin 7 selected for external interrupt 7 1 PORTB Port B pin 7 selected for external interrupt 7 2 PORTC Port C pin 7 selected for external interrupt 7 3 PORTD Port D pin 7 selected for external interrupt 7 4 PORTE Port E pin 7 selected for external interrupt 7 5 PORTF Port F pin 7 selected for external interrupt 7 27 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 26:24 EXTIPSEL6 0x0 RW External Interrupt 6 Port Select Select input port for external interrupt 6. Value Mode Description 0 PORTA Port A pin 6 selected for external interrupt 6 1 PORTB Port B pin 6 selected for external interrupt 6 2 PORTC Port C pin 6 selected for external interrupt 6 3 PORTD Port D pin 6 selected for external interrupt 6 4 PORTE Port E pin 6 selected for external interrupt 6 5 PORTF Port F pin 6 selected for external interrupt 6 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 479 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description 23 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 22:20 EXTIPSEL5 0x0 RW External Interrupt 5 Port Select Select input port for external interrupt 5. Value Mode Description 0 PORTA Port A pin 5 selected for external interrupt 5 1 PORTB Port B pin 5 selected for external interrupt 5 2 PORTC Port C pin 5 selected for external interrupt 5 3 PORTD Port D pin 5 selected for external interrupt 5 4 PORTE Port E pin 5 selected for external interrupt 5 5 PORTF Port F pin 5 selected for external interrupt 5 19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 18:16 EXTIPSEL4 0x0 RW External Interrupt 4 Port Select Select input port for external interrupt 4. Value Mode Description 0 PORTA Port A pin 4 selected for external interrupt 4 1 PORTB Port B pin 4 selected for external interrupt 4 2 PORTC Port C pin 4 selected for external interrupt 4 3 PORTD Port D pin 4 selected for external interrupt 4 4 PORTE Port E pin 4 selected for external interrupt 4 5 PORTF Port F pin 4 selected for external interrupt 4 15 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 14:12 EXTIPSEL3 0x0 RW External Interrupt 3 Port Select Select input port for external interrupt 3. Value Mode Description 0 PORTA Port A pin 3 selected for external interrupt 3 1 PORTB Port B pin 3 selected for external interrupt 3 2 PORTC Port C pin 3 selected for external interrupt 3 3 PORTD Port D pin 3 selected for external interrupt 3 4 PORTE Port E pin 3 selected for external interrupt 3 5 PORTF Port F pin 3 selected for external interrupt 3 11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 10:8 EXTIPSEL2 0x0 RW External Interrupt 2 Port Select Select input port for external interrupt 2. Value Mode Description 0 PORTA Port A pin 2 selected for external interrupt 2 1 PORTB Port B pin 2 selected for external interrupt 2 2 PORTC Port C pin 2 selected for external interrupt 2 3 PORTD Port D pin 2 selected for external interrupt 2 4 PORTE Port E pin 2 selected for external interrupt 2 5 PORTF Port F pin 2 selected for external interrupt 2 7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 6:4 EXTIPSEL1 0x0 RW External Interrupt 1 Port Select Select input port for external interrupt 1. Value Mode Description 0 PORTA Port A pin 1 selected for external interrupt 1 1 PORTB Port B pin 1 selected for external interrupt 1 2 PORTC Port C pin 1 selected for external interrupt 1 3 PORTD Port D pin 1 selected for external interrupt 1 4 PORTE Port E pin 1 selected for external interrupt 1 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 480 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description Value Mode Description 5 PORTF Port F pin 1 selected for external interrupt 1 3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 2:0 EXTIPSEL0 0x0 RW External Interrupt 0 Port Select Select input port for external interrupt 0. Value Mode Description 0 PORTA Port A pin 0 selected for external interrupt 0 1 PORTB Port B pin 0 selected for external interrupt 0 2 PORTC Port C pin 0 selected for external interrupt 0 3 PORTD Port D pin 0 selected for external interrupt 0 4 PORTE Port E pin 0 selected for external interrupt 0 5 PORTF Port F pin 0 selected for external interrupt 0 28.5.11 GPIO_EXTIPSELH - External Interrupt Port Select High Register Access 0 1 2 RW 0x0 EXTIPSEL8 3 4 5 RW 0x0 EXTIPSEL9 6 7 8 9 RW 0x0 EXTIPSEL10 10 11 12 14 13 RW 0x0 EXTIPSEL11 15 17 EXTIPSEL12 RW 0x0 18 19 20 21 EXTIPSEL13 RW 0x0 22 23 24 25 26 RW 0x0 27 28 EXTIPSEL14 Name 29 30 Access RW 0x0 Reset EXTIPSEL15 31 0x104 16 Bit Position Offset Bit Name Reset Description 31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 30:28 EXTIPSEL15 0x0 RW External Interrupt 15 Port Select Select input port for external interrupt 15. Value Mode Description 0 PORTA Port A pin 15 selected for external interrupt 15 1 PORTB Port B pin 15 selected for external interrupt 15 2 PORTC Port C pin 15 selected for external interrupt 15 3 PORTD Port D pin 15 selected for external interrupt 15 4 PORTE Port E pin 15 selected for external interrupt 15 5 PORTF Port F pin 15 selected for external interrupt 15 27 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 26:24 EXTIPSEL14 0x0 RW External Interrupt 14 Port Select Select input port for external interrupt 14. Value Mode Description 0 PORTA Port A pin 14 selected for external interrupt 14 1 PORTB Port B pin 14 selected for external interrupt 14 2 PORTC Port C pin 14 selected for external interrupt 14 3 PORTD Port D pin 14 selected for external interrupt 14 4 PORTE Port E pin 14 selected for external interrupt 14 5 PORTF Port F pin 14 selected for external interrupt 14 23 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 22:20 EXTIPSEL13 0x0 RW External Interrupt 13 Port Select Select input port for external interrupt 13. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 481 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description Value Mode Description 0 PORTA Port A pin 13 selected for external interrupt 13 1 PORTB Port B pin 13 selected for external interrupt 13 2 PORTC Port C pin 13 selected for external interrupt 13 3 PORTD Port D pin 13 selected for external interrupt 13 4 PORTE Port E pin 13 selected for external interrupt 13 5 PORTF Port F pin 13 selected for external interrupt 13 19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 18:16 EXTIPSEL12 0x0 RW External Interrupt 12 Port Select Select input port for external interrupt 12. Value Mode Description 0 PORTA Port A pin 12 selected for external interrupt 12 1 PORTB Port B pin 12 selected for external interrupt 12 2 PORTC Port C pin 12 selected for external interrupt 12 3 PORTD Port D pin 12 selected for external interrupt 12 4 PORTE Port E pin 12 selected for external interrupt 12 5 PORTF Port F pin 12 selected for external interrupt 12 15 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 14:12 EXTIPSEL11 0x0 RW External Interrupt 11 Port Select Select input port for external interrupt 11. Value Mode Description 0 PORTA Port A pin 11 selected for external interrupt 11 1 PORTB Port B pin 11 selected for external interrupt 11 2 PORTC Port C pin 11 selected for external interrupt 11 3 PORTD Port D pin 11 selected for external interrupt 11 4 PORTE Port E pin 11 selected for external interrupt 11 5 PORTF Port F pin 11 selected for external interrupt 11 11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 10:8 EXTIPSEL10 0x0 RW External Interrupt 10 Port Select Select input port for external interrupt 10. Value Mode Description 0 PORTA Port A pin 10 selected for external interrupt 10 1 PORTB Port B pin 10 selected for external interrupt 10 2 PORTC Port C pin 10 selected for external interrupt 10 3 PORTD Port D pin 10 selected for external interrupt 10 4 PORTE Port E pin 10 selected for external interrupt 10 5 PORTF Port F pin 10 selected for external interrupt 10 7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 6:4 EXTIPSEL9 0x0 RW External Interrupt 9 Port Select Select input port for external interrupt 9. Value Mode Description 0 PORTA Port A pin 9 selected for external interrupt 9 1 PORTB Port B pin 9 selected for external interrupt 9 2 PORTC Port C pin 9 selected for external interrupt 9 3 PORTD Port D pin 9 selected for external interrupt 9 4 PORTE Port E pin 9 selected for external interrupt 9 5 PORTF Port F pin 9 selected for external interrupt 9 3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 2:0 EXTIPSEL8 0x0 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 RW External Interrupt 8 Port Select 482 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description Select input port for external interrupt 8. Value Mode Description 0 PORTA Port A pin 8 selected for external interrupt 8 1 PORTB Port B pin 8 selected for external interrupt 8 2 PORTC Port C pin 8 selected for external interrupt 8 3 PORTD Port D pin 8 selected for external interrupt 8 4 PORTE Port E pin 8 selected for external interrupt 8 5 PORTF Port F pin 8 selected for external interrupt 8 28.5.12 GPIO_EXTIRISE - External Interrupt Rising Edge Trigger Register 0 1 2 3 4 5 6 7 8 0x0000 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x108 Bit Position 31 Offset RW Reset EXTIRISE Access Name Bit Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 EXTIRISE 0x0000 RW External Interrupt n Rising Edge Trigger Enable Set bit n to enable triggering of external interrupt n on rising edge. Value Description EXTIRISE[n] = 0 Rising edge trigger disabled EXTIRISE[n] = 1 Rising edge trigger enabled 28.5.13 GPIO_EXTIFALL - External Interrupt Falling Edge Trigger Register Offset 0 1 2 3 4 5 6 7 8 0x0000 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x10C Bit Position RW Reset EXTIFALL Access Name Bit Name Reset 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 EXTIFALL 0x0000 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 Access Description RW External Interrupt n Falling Edge Trigger Enable 483 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description Set bit n to enable triggering of external interrupt n on falling edge. Value Description EXTIFALL[n] = 0 Falling edge trigger disabled EXTIFALL[n] = 1 Falling edge trigger enabled 28.5.14 GPIO_IEN - Interrupt Enable Register 0 1 2 3 4 5 6 7 8 0x0000 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x110 17 Bit Position Offset RW Reset EXT Access Name Bit Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 EXT 0x0000 RW External Interrupt n Enable Set bit n to enable external interrupt from pin n. Value Description EXT[n] = 0 Pin n external interrupt disabled EXT[n] = 1 Pin n external interrupt enabled 28.5.15 GPIO_IF - Interrupt Flag Register 0 1 2 3 4 5 6 7 8 0x0000 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x114 Bit Position 31 Offset Reset EXT R Access Name Bit Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 EXT 0x0000 R External Interrupt Flag n Pin n external interrupt flag. Value Description EXT[n] = 0 Pin n external interrupt flag cleared 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 484 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description Value Description EXT[n] = 1 Pin n external interrupt flag set 28.5.16 GPIO_IFS - Interrupt Flag Set Register Offset 0 1 2 3 4 5 6 7 8 0x0000 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x118 Bit Position W1 Reset EXT Access Name Bit Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 EXT 0x0000 W1 External Interrupt Flag n Set Write bit n to 1 to set interrupt flag n. Value Description EXT[n] = 0 Pin n external interrupt flag unchanged EXT[n] = 1 Pin n external interrupt flag set 28.5.17 GPIO_IFC - Interrupt Flag Clear Register 0 1 2 3 4 5 6 7 8 0x0000 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x11C Bit Position 31 Offset W1 Reset EXT Access Name Bit Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 EXT 0x0000 W1 External Interrupt Flag Clear Write bit n to 1 to clear external interrupt flag n. Value Description EXT[n] = 0 Pin n external interrupt flag unchanged EXT[n] = 1 Pin n external interrupt flag cleared 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 485 www.silabs.com ...the world's most energy friendly microcontrollers 28.5.18 GPIO_ROUTE - I/O Routing Register Access 0 1 1 2 0 1 RW RW SWCLKPEN Name SWOPEN SWLOCATION Access RW Reset SWDIOPEN 3 4 5 6 7 8 9 RW 0x0 10 11 12 13 14 15 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x120 16 Bit Position Offset Bit Name Reset Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 9:8 SWLOCATION 0x0 RW I/O Location Decides the location of the SW pins. Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 7:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 2 SWOPEN 0 RW Serial Wire Viewer Output Pin Enable Enable Serial Wire Viewer Output connection to pin. 1 SWDIOPEN 1 RW Serial Wire Data Pin Enable Enable Serial Wire Data connection to pin. WARNING: When this pin is disabled, the device can no longer be accessed by a debugger. A reset will set the pin back to a default state as enabled. If you disable this pin, make sure you have at least a 3 second timeout at the start of you program code before you disable the pin. This way, the debugger will have time to halt the device after a reset before the pin is disabled. 0 SWCLKPEN 1 RW Serial Wire Clock Pin Enable Enable Serial Wire Clock connection to pin. WARNING: When this pin is disabled, the device can no longer be accessed by a debugger. A reset will set the pin back to a default state as enabled. If you disable this pin, make sure you have at least a 3 second timeout at the start of you program code before you disable the pin. This way, the debugger will have time to halt the device after a reset before the pin is disabled. 28.5.19 GPIO_INSENSE - Input Sense Register Access 0 RW RW INT Name PRS Access 1 1 2 3 4 5 6 7 8 9 1 Reset 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x124 Bit Position 31 Offset Bit Name Reset Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 1 PRS 1 RW PRS Sense Enable RW Interrupt Sense Enable Set this bit to enable input sensing for PRS. 0 INT 1 Set this bit to enable input sensing for interrupts. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 486 www.silabs.com ...the world's most energy friendly microcontrollers 28.5.20 GPIO_LOCK - Configuration Lock Register Offset 0 1 2 3 4 5 6 7 8 0x0000 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x128 Bit Position RW Reset LOCKKEY Access Name Bit Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 LOCKKEY 0x0000 RW Configuration Lock Key Write any other value than the unlock code to lock MODEL, MODEH, CTRL, PINLOCKN, EPISELL, EIPSELH, INSENSE and SWDPROUTE from editing. Write the unlock code to unlock. When reading the register, bit 0 is set when the lock is enabled. Mode Value Description UNLOCKED 0 GPIO registers are unlocked LOCKED 1 GPIO registers are locked LOCK 0 Lock GPIO registers UNLOCK 0xA534 Unlock GPIO registers Read Operation Write Operation 28.5.21 GPIO_CTRL - GPIO Control Register 0 1 2 3 4 5 6 7 8 9 RW 0 Reset 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x12C Bit Position 31 Offset EM4RET Access Name Bit Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 0 EM4RET 0 RW Enable EM4 retention Set to enable EM4 retention of output enable, output value and pull enable. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 487 www.silabs.com ...the world's most energy friendly microcontrollers 28.5.22 GPIO_CMD - GPIO Command Register W1 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x130 Bit Position 31 Offset EM4WUCLR Access Name Bit Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 0 EM4WUCLR 0 W1 EM4 Wake-up clear Write 1 to clear all wake-up requests. 28.5.23 GPIO_EM4WUEN - EM4 Wake-up Enable Register 0 1 2 3 0x00 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x134 Bit Position 31 Offset RW Reset EM4WUEN Access Name Bit Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 5:0 EM4WUEN 0x00 RW EM4 Wake-up enable Write 1 to enable wake-up request, write 0 to disable wake-up request. Value Mode Description 0x01 A0 Enable em4 wakeup on pin A0 0x02 A6 Enable em4 wakeup on pin A6 0x04 C9 Enable em4 wakeup on pin C9 0x08 F1 Enable em4 wakeup on pin F1 0x10 F2 Enable em4 wakeup on pin F2 0x20 E13 Enable em4 wakeup on pin E13 28.5.24 GPIO_EM4WUPOL - EM4 Wake-up Polarity Register 0 1 2 3 0x00 4 5 6 7 8 9 10 11 12 13 14 15 RW Reset EM4WUPOL Access Name 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x138 17 Bit Position Offset 488 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 5:0 EM4WUPOL 0x00 RW EM4 Wake-up Polarity Write bit n to 1 for high wake-up request. Write bit n to 0 for low wake-up request Value Mode Description 0x01 A0 Determines polarity on pin A0 0x02 A6 Determines polarity on pin A6 0x04 C9 Determines polarity on pin C9 0x08 F1 Determines polarity on pin F1 0x10 F2 Determines polarity on pin F2 0x20 E13 Determines polarity on pin E13 28.5.25 GPIO_EM4WUCAUSE - EM4 Wake-up Cause Register 0 1 2 3 0x00 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x13C Bit Position 31 Offset Reset EM4WUCAUSE R Access Name Bit Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 5:0 EM4WUCAUSE 0x00 R EM4 wake-up cause Bit n indicates which pin the wake-up request occurred. Value Mode Description 0x01 A0 This bit indicates an em4 wake-up request occurred on pin A0 0x02 A6 This bit indicates an em4 wake-up request occurred on pin A6 0x04 C9 This bit indicates an em4 wake-up request occurred on pin C9 0x08 F1 This bit indicates an em4 wake-up request occurred on pin F1 0x10 F2 This bit indicates an em4 wake-up request occurred on pin F2 0x20 E13 This bit indicates an em4 wake-up request occurred on pin E13 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 489 www.silabs.com ...the world's most energy friendly microcontrollers 29 LCD - Liquid Crystal Display Driver Quick Facts What? The LCD driver can drive up to 8x20 segmented LCD directly. The LCD driver consumes less than 900 nA in EM2. The animation feature makes it possible to have active animations without CPU intervention. 0 1 2 3 4 Why? Segmented LCD displays are common way to display information. The extreme low-power LCD driver enables a lot of applications to utilize an LCD display even in energy critical systems. LCD Driver How? EFM32 The low frequency clock signal, low-power waveform, animation and blink capabilities enable the LCD driver to run autonomously in EM2 for long periods. Adding the flexible frame rate setting, contrast control, and different multiplexing modes make the EFM32TG the optimal choice for batterydriven systems with LCD panels. 29.1 Introduction The LCD driver is capable of driving a segmented LCD display combination of: 1x24, 2x24, 3x24, 4x24, 6x22 or 8x20 segments. A voltage boost function enables it to provide the LCD display with higher voltage than the supply voltage for the device. In addition, an animation feature can run custom animations on the LCD display without any CPU intervention. The LCD driver can also remain active even in Energy Mode 2 and provides a Frame Counter interrupt that can wake-up the device on a regular basis for updating data. 29.2 Features • Up to 8x20 segments. • Configurable multiplexing (1, 2, 3, 4, 6, 8) • LCD supports the following COM/SEG combinations • 1x24, 2x24, 3x24, 4x24, 6x22, 8x20 • Configurable bias/voltage levels settings • Configurable clock source prescaler • Configurable Frame rate • Segment lines can be enabled or disabled individually • Blink capabilities • Integrated animation functionality • Voltage boost capabilities • Possible to run on external power • Programmable contrast • Frame Counter 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 490 www.silabs.com ...the world's most energy friendly microcontrollers • LCD frame interrupt • Direct segment control 29.3 Functional Description An overview of the LCD module is shown in Figure 29.1 (p. 491) . In its simplest form, an LCD driver would apply a voltage above a certain threshold voltage in order to darken a segment and a voltage below threshold to make a segment clear. However, the LCD display segment will degrade if the applied voltage has a DC-component. To avoid this, the applied waveforms are arranged such that the differential voltage seen by each segment has an average value of zero, and such that the RMS voltage (or differential sum of the two waveforms for fast response LCDs) is below the segment threshold voltage if the segment shall be transparent, and above the segment threshold voltage when the segment shall be dark. The waveforms are multiplexed between eight (1-8) different common lines and segment lines to support up to 160 different LCD segments. The common lines and segment lines can be enabled or disabled individually to prevent the LCD driver from occupying more I/O resources than required. Figure 29.1. LCD Block Diagram VBOOST VEXT VINT LCD_BEXT VLCDSEL LCD_BCAP_P LCD_BCAP_N Data bus LCD control and status LCD segm ent data register LCD anim ation registers Contrast and bias setting Mux and fram erate setting LCD voltage generator Display data Special effects LFACLKLCD VLC4 VLC3 VLC2 VLC1 VLC0 VLC4 VLC3 VLC2 VLC1 VLC0 LCD sequence generator Disable SEG out 20x SEG 4x SEG/ COM LCD_SEGx 4x Disable COM out LCD_COMx For simplicity, only one segment pin and one common terminal is shown in the figure. 29.3.1 LCD Driver Enable Setting the EN bit in LCD_CTRL enables the LCD driver. The MUX bit-field in LCD_DISPCTRL determines which COM lines are driven by the LCD driver. By default, LCD_COM0 is driven whenever the LCD driver is enabled. The LCD_SEGEN register determines which segment lines are enabled. Segment lines can be enabled in groups of 4 and disabled in groups of 4 or individually disabled. To enable output on segment lines 0-7 for instance, the two lowest segment groups, set the two lowest bits in LCD_SEGEN. Each LCD segment pin can also be individually disabled by setting the pin to any other state than DISABLED in the GPIO pin configuration. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 491 www.silabs.com ...the world's most energy friendly microcontrollers Each LCD segment pin can also be individually disabled by setting the pin to any other state than DISABLED in the GPIO pin configuration. 29.3.2 Multiplexing, Bias, and Wave Settings The LCD driver supports different multiplexing and bias settings, and these can be set individually in the MUX and BIAS bits in LCD_DISPCTRL respectively, see Table 29.1 (p. 492) and Table 29.2 (p. 492) . Note If the MUX and BIAS settings in LCD_DISPCTRL are changed while the LCD driver is enabled, the output waveform is unpredictable and may lead to a DC-component for one LCD frame. The MUX setting determines the number of LCD COM lines that are enabled. When using octaplex or sextaplex multiplexing, the additional COM lines used (COM4-COM7) are actually located on the SEG (SEG20-SEG23) lines. When static multiplexing is selected, LCD output is enabled on LCD_COM0, when duplex multiplexing is used, LCD_COM0-LCD_COM1 are used, when triplex multiplexing is selected, LCD_COM0-LCD_COM2 are used, when quadruplex multiplexing is selected, LCD_COM0LCD_COM3 are used, when sextaplex multiplexing is selected, LCD_COM0-LCD_COM3 together with SEG20-SEG21 as LCD_COM4-LCD_COM5 are used, making 22 segments available, located in SEG0SEG19, and SEG22-SEG23. Finally when octaplex multiplexing is selected, LCD_COM0-LCD_COM3 together with SEG20-SEG23 as LCD_COM4-LCD_COM7 are used, making the 36 segments available, located in SEG0-SEG19, and SEG24-SEG39. See Section 29.3.3 (p. 493) for waveforms for the different bias and multiplexing settings. The waveforms generated by the LCD controller can be generated in two different versions, regular and low-power. The low power mode waveforms have a lower switching frequency than the regular waveforms, and thus consume less power. The WAVE bit in LCD_DISPCTRL decides which waveforms to generate. An example of a low-power waveform is shown in Figure 29.2 (p. 493) , and an example of a regular waveform is shown in Figure 29.3 (p. 493) . Table 29.1. LCD Mux Settings MUXE MUX Mode Multiplexing 0 00 Static Static (segments can be multiplexed with LCD_COM[0]) 0 01 Duplex Duplex (segments can be multiplexed with LCD_COM[1:0]) 0 10 Triplex Triplex (segments can be multiplexed with LCD_COM[2:0]) 0 11 Quadruplex Quadruplex (segments can be multiplexed with LCD_COM[3:0]) 1 01 Sextaplex Sextaplex (segments can be multiplexed with LCD_COM[3:0] and SEG[21:20]) 1 11 Octaplex Octaplex (segments can be multiplexed with LCD_COM[3:0]) and SEG[23:20] Table 29.2. LCD BIAS Settings BIAS Mode Bias setting 00 Static Static (2 levels) 01 Half Bias 1/2 Bias (3 levels) 10 Third Bias 1/3 Bias (4 levels) 11 Fourth Bias 1/4 Bias (5 levels) 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 492 www.silabs.com ...the world's most energy friendly microcontrollers Table 29.3. LCD Wave Settings WAVE Mode Wave mode 0 LowPower Low power optimized waveform output 1 Normal Regular waveform output Figure 29.2. LCD Low-power Waveform for LCD_COM0 in Quadruples Multiplex Mode, 1/3 Bias VLC0 (VLCD) VLC1 (2/ 3VLCD) VLC2 (1/ 3VLCD) VLC3 (VSS) Fram e Start Fram e End Figure 29.3. LCD Normal Waveform for LCD_COM0 in Quadruples Multiplex Mode, 1/3 Bias VLC0 (VLCD) VLC1 (2/ 3VLCD) VLC2 (1/ 3VLCD) VLC3 (VSS) Fram e Start Fram e End 29.3.3 Waveform Examples The numbers on the illustration's y-axes in the following sections only indicate different voltage levels. All examples are shown with low-power waveforms. 29.3.3.1 Waveforms with Static Bias and Multiplexing • With static bias and multiplexing, each segment line can be connected to LCD_COM0. When the segment line has the same waveform as LCD_COM0, the LCD panel pixel is turned off, while when the segment line has the opposite waveform, the LCD panel pixel is turned on. • DC voltage = 0 (over one frame) • VRMS (on) = VLCD_OUT • VRMS (off) = 0 (VSS) Figure 29.4. LCD Static Bias and Multiplexing - LCD_COM0 VLC0 (VLCD) VLC3 (VSS) Fram e Start Fram e End 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 493 www.silabs.com ...the world's most energy friendly microcontrollers 29.3.3.2 Waveforms with 1/2 Bias and Duplex Multiplexing In this mode, each frame is divided into 4 periods. LCD_COM[1:0] lines can be multiplexed with all segment lines. Figures show 1/2 bias and duplex multiplexing (waveforms show two frames) Figure 29.5. LCD 1/2 Bias and Duplex Multiplexing - LCD_COM0 VLC0 (VLCD) VLC1 (1/ 2VLCD) VLC3 (VSS) Fram e Start Fram e End Figure 29.6. LCD 1/2 Bias and Duplex Multiplexing - LCD_COM1 VLC0 (VLCD) VLC1 (1/ 2VLCD) VLC3 (VSS) Fram e Start Fram e End 1/2 bias and duplex multiplexing - LCD_SEG0 The LCD_SEG0 waveform on the left is just an example to illustrate how different segment waveforms can be multiplexed with the LCD_COM lines in order to turn on and off LCD pixels. As illustrated in the figures below, this waveform will turn ON pixels connected to LCD_COM0, while pixels connected to LCD_COM1 will be turned OFF. Figure 29.7. LCD 1/2 Bias and Duplex Multiplexing - LCD_SEG0 VLC0 (VLCD) VLC1 (1/ 2VLCD) VLC3 (VSS) Fram e Start Fram e End Figure 29.8. LCD 1/2 Bias and Duplex Multiplexing - LCD_SEG0 Connection seg0 com 0 com 1 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 494 www.silabs.com ...the world's most energy friendly microcontrollers 1/2 bias and duplex multiplexing - LCD_SEG0-LCD_COM0 • DC voltage = 0 (over one frame) • VRMS = 0.79 × VLCD_OUT • The LCD display pixel that is connected to LCD_SEG0 and LCD_COM0 will be ON with this waveform. Figure 29.9. LCD 1/2 Bias and Duplex Multiplexing - LCD_SEG0-LCD_COM0 VLC0 (VLCD) VLC1 (1/ 2VLCD) VLC3 (VSS) - VLC1 (1/ 2VLCD) - VLC0 (VLCD) Fram e Start Fram e End 1/2 bias and duplex multiplexing - LCD_SEG0-LCD_COM1 • DC voltage = 0 (over one frame) • VRMS = 0.35 × VLCD_OUT • The LCD display pixel that is connected to LCD_SEG0 and LCD_COM0 will be OFF with this waveform Figure 29.10. LCD 1/2 Bias and Duplex Multiplexing - LCD_SEG0-LCD_COM1 VLC0 (VLCD) VLC1 (1/ 2VLCD) VLC3 (VSS) - VLC1 (1/ 2VLCD) - VLC0 (VLCD) Fram e Start Fram e End 29.3.3.3 Waveforms with 1/3 Bias and Duplex Multiplexing In this mode, each frame is divided into 4 periods. LCD_COM[1:0] lines can be multiplexed with all segment lines. Figures show 1/3 bias and duplex multiplexing (waveforms show two frames). Figure 29.11. LCD 1/3 Bias and Duplex Multiplexing - LCD_COM0 VLC0 (VLCD) VLC1 (2/ 3VLCD) VLC2 (1/ 3VLCD) VLC3 (VSS) Fram e Start 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 Fram e End 495 www.silabs.com ...the world's most energy friendly microcontrollers Figure 29.12. LCD 1/3 Bias and Duplex Multiplexing - LCD_COM1 VLC0 (VLCD) VLC1 (2/ 3VLCD) VLC2 (1/ 3VLCD) VLC3 (VSS) Fram e Start Fram e End 1/3 bias and duplex multiplexing - LCD_SEG0 The LCD_SEG0 waveform on the left is just an example to illustrate how different segment waveforms can be multiplexed with the COM lines in order to turn on and off LCD pixels. As illustrated in the figures below, this waveform will turn ON pixels connected to LCD_COM0, while pixels connected to LCD_COM1 will be turned OFF. Figure 29.13. LCD 1/3 Bias and Duplex Multiplexing - LCD_SEG0 VLC0 (VLCD) VLC1 (2/ 3VLCD) VLC2 (1/ 3VLCD) VLC3 (VSS) Fram e Start Fram e End Figure 29.14. LCD 1/3 Bias and Duplex Multiplexing - LCD_SEG0 Connection seg0 com 0 com 1 1/3 bias and duplex multiplexing - LCD_SEG0-LCD_COM0 • DC voltage = 0 (over one frame) • VRMS = 0.75 × VLCD_OUT • The LCD display pixel that is connected to LCD_SEG0 and LCD_COM0 will be ON with this waveform 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 496 www.silabs.com ...the world's most energy friendly microcontrollers Figure 29.15. LCD 1/3 Bias and Duplex Multiplexing - LCD_SEG0-LCD_COM0 VLC0 (VLCD) VLC1 (2/ 3VLCD) VLC2 (1/ 3VLCD) VLC3 (VSS) - VLC2 (1/ 3VLCD) - VLC1 (2/ 3VLCD) - VLC0 (VLCD) Fram e Start Fram e End 1/3 bias and duplex multiplexing - LCD_SEG0-LCD_COM0 • DC voltage = 0 (over one frame) • VRMS = 0.33 × VLCD_OUT • The LCD display pixel that is connected to LCD_SEG0 and LCD_COM1 will be OFF with this waveform Figure 29.16. LCD 1/3 Bias and Duplex Multiplexing - LCD_SEG0-LCD_COM1 VLC0 (VLCD) VLC1 (2/ 3VLCD) VLC2 (1/ 3VLCD) VLC3 (VSS) - VLC2 (1/ 3VLCD) - VLC1 (2/ 3VLCD) - VLC0 (VLCD) Fram e Start Fram e End 29.3.3.4 Waveforms with 1/2 Bias and Triplex Multiplexing In this mode, each frame is divided into 6 periods. LCD_COM[2:0] lines can be multiplexed with all segment lines. Figures show 1/2 bias and triplex multiplexing (waveforms show two frames). Figure 29.17. LCD 1/2 Bias and Triplex Multiplexing - LCD_COM0 VLC0 (VLCD) VLC1 (1/ 2VLCD) VLC3 (VSS) Fram e Start Fram e End Figure 29.18. LCD 1/2 Bias and Triplex Multiplexing - LCD_COM1 VLC0 (VLCD) VLC1 (1/ 2VLCD) VLC3 (VSS) Fram e Start 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 Fram e End 497 www.silabs.com ...the world's most energy friendly microcontrollers Figure 29.19. LCD 1/2 Bias and Triplex Multiplexing - LCD_COM2 VLC0 (VLCD) VLC1 (1/ 2VLCD) VLC3 (VSS) Fram e Start Fram e End 1/2 bias and triplex multiplexing - LCD_SEG0 The LCD_SEG0 waveform on the left is just an example to illustrate how different segment waveforms can be multiplexed with the COM lines in order to turn on and off LCD pixels. As illustrated in the figures below, this waveform will turn ON pixels connected to LCD_COM1, while pixels connected to LCD_COM0 and LCD_COM2 will be turned OFF. Figure 29.20. LCD 1/2 Bias and Triplex Multiplexing - LCD_SEG0 VLC0 (VLCD) VLC1 (1/ 2VLCD) VLC3 (VSS) Fram e Start Fram e End Figure 29.21. LCD 1/2 Bias and Triplex Multiplexing - LCD_SEG0 Connection seg0 com 0 com 1 com 2 1/2 bias and triplex multiplexing - LCD_SEG0-LCD_COM0 • DC voltage = 0 (over one frame) • VRMS = 0.4 × VLCD_OUT • The LCD display pixel that is connected to LCD_SEG0 and LCD_COM0 will be OFF with this waveform Figure 29.22. LCD 1/2 Bias and Triplex Multiplexing - LCD_SEG0-LCD_COM0 VLC0 (VLCD) VLC1 (1/ 2VLCD) VLC3 (VSS) - VLC1 (1/ 2VLCD) - VLC0 (VLCD) Fram e Start 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 Fram e End 498 www.silabs.com ...the world's most energy friendly microcontrollers 1/2 bias and triplex multiplexing - LCD_SEG0-LCD_COM1 • DC voltage = 0 (over one frame) • VRMS = 0.7 VLCD_OUT • The LCD display pixel that is connected to LCD_SEG0 and LCD_COM1 will be ON with this waveform Figure 29.23. LCD 1/2 Bias and Triplex Multiplexing - LCD_SEG0-LCD_COM1 VLC0 (VLCD) VLC1 (1/ 2VLCD) VLC3 (VSS) - VLC1 (1/ 2VLCD) - VLC0 (VLCD) Fram e Start Fram e End 1/2 bias and triplex multiplexing - LCD_SEG0-LCD_COM2 • DC voltage = 0 (over one frame) • VRMS = 0.4 × VLCD_OUT • The LCD display pixel that is connected to LCD_SEG0 and LCD_COM2 will be OFF with this waveform Figure 29.24. LCD 1/2 Bias and Triplex Multiplexing - LCD_SEG0-LCD_COM2 VLC0 (VLCD) VLC1 (1/ 2VLCD) VLC3 (VSS) - VLC1 (1/ 2VLCD) - VLC0 (VLCD) Fram e Start Fram e End 29.3.3.5 Waveforms with 1/3 Bias and Triplex Multiplexing In this mode, each frame is divided into 6 periods. LCD_COM[2:0] lines can be multiplexed with all segment lines. Figures show 1/3 bias and triplex multiplexing (waveforms show two frames). Figure 29.25. LCD 1/3 Bias and Triplex Multiplexing - LCD_COM0 VLC0 (VLCD) VLC1 (2/ 3VLCD) VLC2 (1/ 3VLCD) VLC3 (VSS) Fram e Start 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 Fram e End 499 www.silabs.com ...the world's most energy friendly microcontrollers Figure 29.26. LCD 1/3 Bias and Triplex Multiplexing - LCD_COM1 VLC0 (VLCD) VLC1 (2/ 3VLCD) VLC2 (1/ 3VLCD) VLC3 (VSS) Fram e Start Fram e End Figure 29.27. LCD 1/3 Bias and Triplex Multiplexing - LCD_COM2 VLC0 (VLCD) VLC1 (2/ 3VLCD) VLC2 (1/ 3VLCD) VLC3 (VSS) Fram e Start Fram e End 1/3 bias and triplex multiplexing - LCD_SEG0 The LCD_SEG0 waveform illustrates how different segment waveforms can be multiplexed with the COM lines in order to turn on and off LCD pixels. As illustrated in the figures below, this waveform will turn ON pixels connected to LCD_COM1, while pixels connected to LCD_COM0 and LCD_COM2 will be turned OFF. Figure 29.28. LCD 1/3 Bias and Triplex Multiplexing - LCD_SEG0 VLC0 (VLCD) VLC1 (2/ 3VLCD) VLC2 (1/ 3VLCD) VLC3 (VSS) Fram e Start Fram e End Figure 29.29. LCD 1/3 Bias and Triplex Multiplexing - LCD_SEG0 Connection seg0 com 0 com 1 com 2 1/3 bias and triplex multiplexing - LCD_SEG0-LCD_COM0 • DC voltage = 0 (over one frame) • VRMS = 0.33 VLCD_OUT • The LCD display pixel that is connected to LCD_SEG0 and LCD_COM0 will be OFF with this waveform 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 500 www.silabs.com ...the world's most energy friendly microcontrollers Figure 29.30. LCD 1/3 Bias and Triplex Multiplexing - LCD_SEG0-LCD_COM0 VLC0 (VLCD) VLC1 (2/ 3VLCD) VLC2 (1/ 3VLCD) VLC3 (VSS) - VLC2 (1/ 3VLCD) - VLC1 (2/ 3VLCD) - VLC0 (VLCD) Fram e Start Fram e End 1/3 bias and triplex multiplexing - LCD_SEG0-LCD_COM1 • DC voltage = 0 (over one frame) • VRMS = 0.64 × VLCD_OUT • The LCD display pixel that is connected to LCD_SEG0 and LCD_COM1 will be ON with this waveform Figure 29.31. LCD 1/3 Bias and Triplex Multiplexing - LCD_SEG0-LCD_COM1 VLC0 (VLCD) VLC1 (2/ 3VLCD) VLC2 (1/ 3VLCD) VLC3 (VSS) - VLC2 (1/ 3VLCD) - VLC1 (2/ 3VLCD) - VLC0 (VLCD) Fram e Start Fram e End 1/3 bias and triplex multiplexing - LCD_SEG0-LCD_COM2 • DC voltage = 0 (over one frame) • VRMS = 0.33 × VLCD_OUT • The LCD display pixel that is connected to LCD_SEG0 and LCD_COM2 will be OFF with this waveform Figure 29.32. LCD 1/3 Bias and Triplex Multiplexing - LCD_SEG0-LCD_COM2 VLC0 (VLCD) VLC1 (2/ 3VLCD) VLC2 (1/ 3VLCD) VLC3 (VSS) - VLC2 (1/ 3VLCD) - VLC1 (2/ 3VLCD) - VLC0 (VLCD) Fram e Start Fram e End 29.3.3.6 Waveforms with 1/3 Bias and Quadruplex Multiplexing In this mode, each frame is divided into 8 periods. All COM lines can be multiplexed with all segment lines. Figures show 1/3 bias and quadruplex multiplexing (waveforms show two frames). 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 501 www.silabs.com ...the world's most energy friendly microcontrollers Figure 29.33. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_COM0 VLC0 (VLCD) VLC1 (2/ 3VLCD) VLC2 (1/ 3VLCD) VLC3 (VSS) Fram e Start Fram e End Figure 29.34. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_COM1 VLC0 (VLCD) VLC1 (2/ 3VLCD) VLC2 (1/ 3VLCD) VLC3 (VSS) Fram e Start Fram e End Figure 29.35. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_COM2 VLC0 (VLCD) VLC1 (2/ 3VLCD) VLC2 (1/ 3VLCD) VLC3 (VSS) Fram e Start Fram e End Figure 29.36. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_COM3 VLC0 (VLCD) VLC1 (2/ 3VLCD) VLC2 (1/ 3VLCD) VLC3 (VSS) Fram e Start Fram e End 1/3 bias and quadruplex multiplexing - LCD_SEG0 The LCD_SEG0 waveform on the left is just an example to illustrate how different segment waveforms can be multiplexed with the COM lines in order to turn on and off LCD pixels. As illustrated in the figures below, this wave form will turn ON pixels connected to LCD_COM0 and LCD_COM2, while pixels connected to LCD_COM1 and LCD_COM3 will be turned OFF. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 502 www.silabs.com ...the world's most energy friendly microcontrollers Figure 29.37. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_SEG0 VLC0 (VLCD) VLC1 (2/ 3VLCD) VLC2 (1/ 3VLCD) VLC3 (VSS) Fram e Start Fram e End Figure 29.38. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_SEG0 Connection seg0 com 0 com 1 com 2 com 3 1/3 bias and quadruplex multiplexing - LCD_SEG0-LCD_COM0 • DC voltage = 0 (over one frame) • VRMS = 0.58 × VLCD_OUT • The LCD display pixel that is connected to LCD_SEG0 and LCD_COM0 will be ON with this waveform Figure 29.39. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_SEG0-LCD_COM0 VLC0 (VLCD) VLC1 (2/ 3VLCD) VLC2 (1/ 3VLCD) VLC3 (VSS) - VLC2 (1/ 3VLCD) - VLC1 (2/ 3VLCD) - VLC0 (VLCD) Fram e Start Fram e End 1/3 bias and quadruplex multiplexing - LCD_SEG0-LCD_COM1 • DC voltage = 0 (over one frame) • VRMS = 0.33 × VLCD_OUT • The LCD display pixel that is connected to LCD_SEG0 and LCD_COM1 will be OFF with this waveform 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 503 www.silabs.com ...the world's most energy friendly microcontrollers Figure 29.40. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_SEG0-LCD_COM1 VLC0 (VLCD) VLC1 (2/ 3VLCD) VLC2 (1/ 3VLCD) VLC3 (VSS) - VLC2 (1/ 3VLCD) - VLC1 (2/ 3VLCD) - VLC0 (VLCD) Fram e Start Fram e End 1/3 bias and quadruplex multiplexing - LCD_SEG0-LCD_COM2 • DC voltage = 0 (over one frame) • VRMS = 0.58 × VLCD_OUT • The LCD display pixel that is connected to LCD_SEG0 and LCD_COM2 will be ON with this waveform Figure 29.41. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_SEG0-LCD_COM2 VLC0 (VLCD) VLC1 (2/ 3VLCD) VLC2 (1/ 3VLCD) VLC3 (VSS) - VLC2 (1/ 3VLCD) - VLC1 (2/ 3VLCD) - VLC0 (VLCD) Fram e Start Fram e End 1/3 bias and quadruplex multiplexing - LCD_SEG0-LCD_COM2 • DC voltage = 0 (over one frame) • VRMS = 0.33 × VLCD_OUT • The LCD display pixel that is connected to LCD_SEG0 and LCD_COM3 will be OFF with this waveform Figure 29.42. LCD 1/3 Bias and Quadruplex Multiplexing- LCD_SEG0-LCD_COM3 VLC0 (VLCD) VLC1 (2/ 3VLCD) VLC2 (1/ 3VLCD) VLC3 (VSS) - VLC2 (1/ 3VLCD) - VLC1 (2/ 3VLCD) - VLC0 (VLCD) Fram e Start Fram e End 29.3.4 LCD Contrast Different LCD panels have different characteristics and also temperature may affect the characteristics of the LCD panels. To compensate for such variations, the LCD driver has a programmable contrast that 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 504 www.silabs.com ...the world's most energy friendly microcontrollers adjusts the VLCD_OUT. The contrast is set by CONLEV in LCD_DISPCTRL, and can be adjusted relative to either VDD (VLCD) or Ground using CONCONF in LCD_DISPCTRL. See Table 29.4 (p. 505) and Table 29.5 (p. 505) , Table 29.5 (p. 505) and Table 29.6 (p. 506) . Table 29.4. LCD Contrast BIAS CONLEV Equation Range 00 00000-11111 VLCD_OUT = VLCD x (0.61 x (1 + CONLEV/(2 - 1))) 5 CONLEV = 0 => VLCD_OUT = 0.61VLCD CONLEV = 31 => VLCD_OUT = VLCD 01 00000-11111 5 VLCD_OUT = VLCD x (0.53 x (1 + CONLEV/(2 - 1))) CONLEV = 0 => VLCD_OUT = 0.53VLCD CONLEV = 31 => VLCD_OUT = VLCD 10 00000-11111 5 VLCD_OUT = VLCD x (0.61 x (1 + CONLEV/(2 - 1))) CONLEV = 0 => VLCD_OUT = 0.61VLCD CONLEV = 31 => VLCD_OUT = VLCD 11 00000-11111 5 VLCD_OUT = VLCD x (0.61 x (1 + CONLEV/(2 - 1))) CONLEV = 0 => VLCD_OUT = 0.61VLCD CONLEV = 31 => VLCD_OUT = VLCD Note Reset value is maximum contrast Table 29.5. LCD Contrast Function CONCONF Function 0 Contrast is adjusted relative to VDD (VLCD) 1 Contrast is adjusted relative to Ground 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 505 www.silabs.com ...the world's most energy friendly microcontrollers Table 29.6. LCD Principle of Contrast Adjustment for Different Bias Settings. Contrast adjustment relative to VDD (VLCD) (CONCONF = 0) Contrast adjustment relative to GND (CONCONF = 1) No contrast adjustment (CONLEV = 11111) 1/4 bias VLCD VLCD VLCD VLC0 Rx VLC0 VLC0 R0 R0 VLC1 R0 VLC1 R1 VLC1 R1 VLC2 VLCD_OUT R1 VLC2 VLCD_OUT VLC2 VLCD_OUT R2 R2 VLC3 VLC3 R2 VLC3 R3 VLC4 Rx R3 R3 VLC4 VLC4 1/3 bias VLCD VLCD VLCD VLC0 Rx VLC0 VLC0 R0 R0 VLC1 R0 R1 VLC1 VLCD_OUT R1 VLC1 VLCD_OUT VLCD_OUT VLC2 VLC2 R2 VLC2 R1 R2 VLC3 R2 VLC3 Rx VLC3 1/2 bias VLCD VLCD VLCD VLC0 VLC0 Rx R0 R0 VLC0 VLC1 V LCD_OUT VLC1 VLCD_OUT R0 VLC1 VLCD_OUT R1 R1 VLC3 VLC3 R1 Rx VLC3 Static VLCD Rx R0 VLC0 VLC0 VLCD_OUT VLC3 VLCD_OUT R0 VLCD VLCD VLC0 VLCD_OUT VLC3 Rx VLC3 R0 = R1 = R2 = R3 in the figure, while Rx is adjusted by changing the CONLEV bits. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 506 www.silabs.com ...the world's most energy friendly microcontrollers 29.3.5 VLCD Selection By default, the LCD driver runs on main external power (VLCD = VDD), see Table 29.7 (p. 507) . An internal boost circuit can be enabled by setting VBOOSTEN in CMU_LCDCTRL and selecting the boosted voltage by setting VLCDSEL in LCD_DISPCTRL. This will boosts VLCD to VBOOST. VBOOST can be selected in the range of 3.0 V – 3.6 V by configuring VBLEV in LCD_DISPCTRL. Note that the boost circuit is not designed to operate with the selected boost voltage, VBOOST, smaller than VDD. The boost circuit can boost the VLCD up to 3.6 V when VDD is as low as 2.0 V. When using the voltage booster, the LCD_BEXT pin must be connected through a 1 µF capacitor to VSS, and the LCD_BCAP_P and LCD_BCAP_N pins must be connected to each other through a 22 nF capacitor. It is also possible to connect a dedicated power supply to the LCD module. The LCD external power supply must be connected to the LCD_BEXT pin and VLCDSEL in LCD_DISPCTRL must be set. In this mode, the voltage booster should be disabled. Table 29.7. LCD VLCD VLCDSEL Mode VLCD 0 VDD VDD (same as main external power) 1 VBOOST Voltage booster/External VDD 29.3.6 VBOOST Control The boost voltage is configurable. By programming the VBLEV bits in LCD_DISPCTRL, the boost voltage level can be adjusted between 3.0V and 3.6V. The boost circuit will use an update frequency given by the VBFDIV bits in CMU_LCDCTRL, see Table 29.8 (p. 507) ). It is possible to adjust the frequency to optimize performance for all kinds of LCD panels (large capacitors may require less frequent updates, while small capacitors may require more frequent updates). A lower update frequency would in general lead to smaller current consumption. Table 29.8. LCD VBOOST Frequency VBFDIV VBOOST Update Frequency 000 LFACLK 001 LFACLK/2 010 LFACLK/4 011 LFACLK/8 100 LFACLK/16 101 LFACLK/32 110 LFACLK/64 111 LFACLK/128 29.3.7 Frame rate It is important to choose the correct frame rate for the LCD display. Normally, the frame rate should be between 30 and 100 Hz. A frame rate below 30 Hz may lead to flickering, while a frame rate above 100 Hz may lead to ghostering and unnecessarily high power consumption. 29.3.7.1 Clock Selection and Prescaler The LFACLK is prescaled to LFACLKLCDprein the CMU. The available prescaler settings are: 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 507 www.silabs.com ...the world's most energy friendly microcontrollers • • • • LFCLK16: LFACLKLCDpre = LFACLK/16 LFCLK32: LFACLKLCDpre = LFACLK/32 LFCLK64: LFACLKLCDpre = LFACLK/64 LFCLK128: LFACLKLCDpre = LFACLK/128 In addition to selecting the correct prescaling, the clock source can be selected in the CMU. To use this module, the LE interface clock must be enabled in CMU_HFCORECLKEN0, in addition to the module clock. 29.3.7.2 Frame rate Division Register The frame rate is set in the CMU by programming the frame rate division bits FDIV in CMU_LCDCTRL. This setting should not be changed while the LCD driver is running. The equation for calculating the resulting frame rate is given from Equation 29.1 (p. 508) LCD Frame rate Calculation LFACLKLCD = LFACLKLCDpre/(1 + FDIV) (29.1) Table 29.9. LCD Frame rate Conversion Table Resulting Frame rate, CLKFRAME(Hz) MUX Mode Frame- rate formula LFACLKLCDpre = 2 kHz LFACLKLCDpre = 1 kHz LFACLKLCDpre = 0.5 kHz LFACLKLCDpre = 0.25 kHz Min Max Min Max Min Max Min Max Static LFACLKLCD/2 128 1024 64 512 32 256 16 128 Duplex LFACLKLCD/4 64 512 32 256 16 128 8 64 Triplex LFACLKLCD/6 43 341 21 171 11 85 5 43 Quadruplex LFACLKLCD/8 32 256 16 128 8 64 4 32 Sextaplex LFACLKLCD/12 21.33 170.67 10.67 85.33 5.33 42.67 2.67 21.33 Octaplex LFACLKLCD/16 16 128 8 64 4 32 2 16 Table settings: Min: FDIV = 7, Max: FDIV = 0 29.3.8 Data Update The LCD Driver logic that controls the output waveforms is clocked on LFACLKLCDpre. The LCD data and Control Registers are clocked on the HFCORECLK. To avoid metastability and unpredictable behavior, the data in the Segment Data (SEGDn) registers must be synchronized to the LCD driver logic. Also, it is important that data is updated at the beginning of an LCD frame since the segment waveform depends on the segment data and a change in the middle of a frame may lead to a DC-component in that frame. The LCD driver has dedicated functionality to synchronize data transfer to the LCD frames. The synchronization logic is applied to all data that need to be updated at the beginning of the LCD frames: • • • • LCD_SEGDn LCD_AREGA LCD_AREGB LCD_BACTRL The different methods to update data are controlled by the UDCTRL bits in LCD_CTRL. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 508 www.silabs.com ...the world's most energy friendly microcontrollers Table 29.10. LCD Update Data Control (UDCTRL) Bits UDCTRL Mode Description 00 REGULAR The data transfer is controlled by SW and data synchronization is initiated by writing data to the buffers. Data is transferred as soon as possible, possibly creating a frame with a DC component on the LCD. 01 FCEVENT The data transfer is done at the next event triggered by the Frame Counter (FC). See Section 29.3.10 (p. 509) for details on how to configure the Frame Counter. Optionally, the Frame Counter can also generate an interrupt at every event. 10 FRAMESTART The data transfer is done at frame-start. 29.3.9 Direct Segment Control (DSC) It is possible to gain direct control over the bias levels for each SEG/COM line by setting DSC in LCD_CTRL, overwriting the BIAS settings in LCD_DISPCTRL. The SEG lines bias levels can be set in SEGD0-SEGD3, while the COM line bias levels can be set in SEGD4. To represent the different bias levels, 2-bits per SEG lines are needed. For example, SEG0's bias levels can be set using SEGD0[1:0], and SEG1 can be controlled through SEGD0[3:2] etc. Bias level encoding is shown in Table 29.11 (p. 509) . Table 29.11. DSC BIAS Encoding SEGD Mode Bias setting 00 Static Static (2 levels) 01 Half Bias 1/2 Bias (3 levels) 10 Third Bias 1/3 Bias (4 levels) 11 Fourth Bias 1/4 Bias (5 levels) 29.3.10 Frame Counter (FC) The Frame Counter is synchronized to the LCD frame start and will generate an event after a programmable number of frames. An FC event can trigger: • • • • LCD ready interrupt Blink (controlling the blink frequency) Next state in the Animation State Machine Data update if UDCTRL = 01 The Frame Counter is a down counter. It is enabled by writing FCEN in LCD_BACTRL. Optionally, the Frame Counter can be prescaled so that the Frame Counter is decremented at: • • • • Every frame Every second frame Every fourth frame Every eight frame This is controlled by the FCPRESC in LCD_BACTRL, see Table 29.12 (p. 510) 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 509 www.silabs.com ...the world's most energy friendly microcontrollers Table 29.12. FCPRESC FCPRESC Mode Description 00 Div1 CLKFRAME/1 01 Div2 CLKFRAME/2 10 Div4 CLKFRAME/4 11 Div8 CLKFRAME/8 General equation FCPRESC CLKFC = CLKFRAME/2 The top value for the Frame Counter is set by FCTOP in LCD_BACTRL. Every time the frame counter reaches zero, it is reloaded with the top value, and at the same time an event, which can cause an interrupt, data update, blink, or an animation state transition is triggered. LCD Event Frequency Equation CLKEVENT = CLKFC/(1 + FCTOP[5:0]) Hz (29.2) The above equation shows how to set-up the LCD event frequency. In this example, the frame rate is 64Hz, and the LCD event frequency should be set-up to 2 seconds. Example 29.1. LCD Event Frequency Example • Write FCPRESC to 3 => CLKFC = 8Hz (0.125 seconds) • Write FCTOP to 15 => CLKEVENT = 0.5Hz (2 seconds) If higher resolution is required, configure a lower prescaler value and increase the FCPRESC in LCD_BACTRL accordingly (e.g. FCPRESC = 2, FCTOP = 31). Figure 29.43. LCD Clock System in LCD Driver CMU FDIV[2:0] div16 LFXO LFACLK LFRCO div32 LFACLKLCDpre Counter div64 LFACLKLCD div128 LCD in CMU_LFAPRESC0 div2 div4 div6 div8 div2 CLKFC div4 div12 div16 FCTOP[5:0] div1 static duplex triplex quadruplex sex taplex octaplex div8 MUX in LCD_DISPCTRL LCD Fram e Counter CLKEVENT FCPRESC in LCD_BACTRL CLKFRAME 29.3.11 LCD Interrupt The LCD interrupt can be used to synchronize data update. The FC interrupt flag is set at every LCD Frame Counter Event, which must be set-up separately. The interrupt is enabled by setting FC bit in LCD_IEN. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 510 www.silabs.com ...the world's most energy friendly microcontrollers 29.3.12 Blink, Blank, and Animation Features 29.3.12.1 Blink The LCD driver can be configured to blink, alternating all enabled segments between on and off. The blink frequency is given by the CLKEVENT frequency, see Section 29.3.10 (p. 509) . See Section 29.3.8 (p. 508) for details regarding synchronization of the blink feature. The FC must be on for blink to work. 29.3.12.2 Blank Setting BLANK in LCD_BACTRL will output the “OFF” waveform on all enabled segments, effectively blanking the entire display. Writing the BLANK bit to zero disables the blanking and segment data will be output as normal. See Section 29.3.8 (p. 508) for details regarding synchronization of blank. 29.3.12.3 Animation State Machine The Animation State Machine makes it possible to enable different animations without updating the data registers, allowing specialized patterns running on the LCD panel while the microcontroller remains in Low Energy Mode and thus saving power consumption. The animation feature is available on segment 0 to 7 multiplexed with LCD_COM0. The animation is implemented as two programmable 8 bits registers that are shifted left or right every other Animation state for a total of 16 states. The shift operations applied to the shift registers are controlled by AREGASC and AREGBSC in LCD_BACTRL as shown in the table below. Note also that the FC must be on for animation to work, as it is the FC event that drives the animation state machine. Table 29.13. LCD Animation Shift Register AREGnSC, n = A or B Mode Description 00 NOSHIFT No Shift operation 01 SHIFTLEFT Animation register is shifted left (LCD_AREGA is shifted every odd state, LCD_AREGB is shifted every even state) 10 SHIFTRIGHT Animation register is shifted right (LCD_AREGA is shifted every odd state, LCD_AREGB is shifted every even state) 11 Reserved Reserved The two registers are either OR’ed or AND’ed to achieve the displayed animation pattern. This is controlled by ALOGSEL in LCD_BACTRL as shown in Table 29.14 (p. 511) . In addition, the regular segment data SEGD0[7:0] is OR’ed with the animation pattern to generate the resulting output. Table 29.14. LCD Animation Pattern ALOGSEL Mode Description 0 AND LCD_AREGA and LCD_AREGB are AND’ed together 1 OR LCD_AREGA and LCD_AREGB are OR’ed together Each state is displayed one CLKEVENT period, see Section 29.3.10 (p. 509) . By reading ASTATE in LCD_STATUS, software can identify which state that is currently active in the state sequence. Note that the shifting operation is performed on internal registers that are not accessible in SW (when reading LCD_AREGA and LCD_AREGB, the data that was original written will also be read back). The SW must utilize the knowledge about the current state (ASTATE) to calculate what is currently output. ASTATE is cleared when LCD_AREGA or LCD_AREGB are updated with new values. See Table 29.15 (p. 512) for an example. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 511 www.silabs.com ...the world's most energy friendly microcontrollers Table 29.15. LCD Animation Example ASTATE LCD_AREGA LCD_AREGB Resulting Data 0 11000000 11000000 11000000 1 01100000 11000000 11100000 2 01100000 01100000 01100000 3 00110000 01100000 01110000 4 00110000 00110000 00110000 5 00011000 00110000 00111000 6 00011000 00011000 00011000 7 00001100 00011000 00011100 8 00001100 00001100 00001100 9 00000110 00001100 00001110 10 00000110 00000110 00000110 11 00000011 00000110 00000111 12 00000011 00000011 00000011 13 10000001 00000011 10000011 14 10000001 10000001 10000001 15 11000000 10000001 11000001 In the table, AREGASC = 10, AREGBSC = 10, ALOGSEL = 1 and the resulting data is to be displayed on segment lines 7-0 multiplexed with LCD_COM0. Figure 29.44. LCD Block Diagram of the Animation Circuit SEGD0[7:0] AREGASC = 1 = > shift left AREGASC = 2 = > shift right Odd anim ation states AREGA Data Out[7:0] CLKEVENT AREGB AREGBSC = 1 = > shift left AREGBSC = 2 = > shift right Even anim ation states 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 ALOGSEL 512 www.silabs.com ...the world's most energy friendly microcontrollers Example 29.2. LCD Animation Enable Example • Write data into the animation registers LCD_AREGA, LCD_AREGB • Enable the correct shift direction (if any) • Decide which logical function to perform on the registers • ALOGSEL = 0: Data_out = LCD_AREGA & LCD_AREGB • ALOGSEL = 1:Data_out = LCD_AREGA | LCD_AREGB • Configure the right animation period (CLKEVENT) • Enable the animation pattern and frame counter (AEN = 1, FCEN = 1) For updating data in the LCD while it is running an animation, and the new animation data depends on the pattern visible on the LCD, see the following example. Example 29.3. LCD Animation Dependence Example • Enable the LCD interrupt (the interrupt will be triggered simultaneously as the Animation State machine changes state) • In the interrupt handler, read back the current state (ASTATE) • Knowing the current state of the Animation State Machine makes it possible to calculate what data that is currently output • Modify data as required (Data will be updated at the next Frame Counter Event). It is important that new data is written before the next Frame Counter Event. 29.3.13 LCD in Low Energy Modes As long as the LFACLK is running (EM0-EM2), the LCD controller continues to output LCD waveforms according to the data that is currently synchronized to the LCD Driver logic. In addition, the following features are still active if enabled: • Animation State Machine • Blink • LCD Event Interrupt 29.3.14 Register access Since this module is a Low Energy Peripheral, and runs off a clock which is asynchronous to the HFCORECLK, special considerations must be taken when accessing registers. Please refer to Section 5.3 (p. 20) for a description on how to perform register accesses to Low Energy Peripherals. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 513 www.silabs.com ...the world's most energy friendly microcontrollers 29.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 LCD_CTRL RW Control Register 0x004 LCD_DISPCTRL RW Display Control Register 0x008 LCD_SEGEN RW Segment Enable Register 0x00C LCD_BACTRL RW Blink and Animation Control Register 0x010 LCD_STATUS R Status Register 0x014 LCD_AREGA RW Animation Register A 0x018 LCD_AREGB RW Animation Register B 0x01C LCD_IF R Interrupt Flag Register 0x020 LCD_IFS W1 Interrupt Flag Set Register 0x024 LCD_IFC W1 Interrupt Flag Clear Register 0x028 LCD_IEN RW Interrupt Enable Register 0x040 LCD_SEGD0L RW Segment Data Low Register 0 0x044 LCD_SEGD1L RW Segment Data Low Register 1 0x048 LCD_SEGD2L RW Segment Data Low Register 2 0x04C LCD_SEGD3L RW Segment Data Low Register 3 0x060 LCD_FREEZE RW Freeze Register 0x064 LCD_SYNCBUSY R Synchronization Busy Register 0x0CC LCD_SEGD4L RW Segment Data Low Register 4 0x0D0 LCD_SEGD5L RW Segment Data Low Register 5 0x0D4 LCD_SEGD6L RW Segment Data Low Register 6 0x0D8 LCD_SEGD7L RW Segment Data Low Register 7 29.5 Register Description 29.5.1 LCD_CTRL - Control Register (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p. 20) . 0 0 RW 1 2 3 4 5 6 7 RW 0x0 Access EN Name 8 UDCTRL DSC Access 9 10 11 12 13 14 15 16 18 19 20 21 22 RW 0 Reset 23 24 25 26 27 28 29 30 31 0x000 17 Bit Position Offset Bit Name Reset Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 23 DSC 0 RW Direct Segment Control This bit enables direct control over bias levels for each SEG/COM line. Value Description 0 DSC disable 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 514 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Value Description 1 DSC enable Access Description 22:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 2:1 UDCTRL 0x0 RW Update Data Control These bits control how data from the SEGDn registers are transferred to the LCD driver. 0 Value Mode Description 0 REGULAR The data transfer is controlled by SW. Transfer is performed as soon as possible 1 FCEVENT The data transfer is done at the next event triggered by the Frame Counter 2 FRAMESTART The data transfer is done continuously at every LCD frame start EN 0 RW LCD Enable When this bit is set, the LCD driver is enabled and the driver will start outputting waveforms on the com/segment lines. 29.5.2 LCD_DISPCTRL - Display Control Register 0 1 RW MUX 0x0 2 3 RW BIAS 0x0 RW WAVE 0 4 5 6 7 8 9 10 RW CONLEV 0x1F 11 12 13 14 15 16 RW 0 RW CONCONF 0 17 18 RW Access VLCDSEL Name VBLEV MUXE Access 19 20 0x3 21 RW 0 Reset 22 23 24 25 26 27 28 29 30 0x004 Bit Position 31 Offset Bit Name Reset Description 31:23 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 22 MUXE 0 RW Extended Mux Configuration This bit redefines the meaning of the MUX field. Value Mode Description 0 MUX Multiplex mode determined by MUX field. 1 MUXE Mux extended mode. Extends the meaning of the MUX field. 21 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 20:18 VBLEV 0x3 RW Voltage Boost Level These bits control Voltage Boost level. Please refer to datasheet for further details of the boost levels. Value Mode Description 0 LEVEL0 Minimum boost level 1 LEVEL1 2 LEVEL2 3 LEVEL3 4 LEVEL4 5 LEVEL5 6 LEVEL6 7 LEVEL7 Maximum boost level 17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 16 VLCDSEL 0 RW VLCD Selection This bit controls which Voltage source that is connected to VLCD. Value Mode Description 0 VDD VDD 1 VEXTBOOST Voltage Booster/External VDD 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 515 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description 15 CONCONF 0 RW Contrast Configuration This bit selects whether the contrast adjustment is done relative to VLCD or Ground. Value Mode Description 0 VLCD Contrast is adjusted relative to VLCD 1 GND Contrast is adjusted relative to Ground 14:13 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 12:8 CONLEV 0x1F RW Contrast Level These bits control the contrast setting according to this formula: VLCD_OUT = VLCD × 0.5(1+CONLEV/31). Value Mode Description 0 MIN Minimum contrast 31 MAX Maximum contrast 7:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 4 WAVE 0 RW Waveform Selection This bit configures the output waveform. 3:2 Value Mode Description 0 LOWPOWER Low power waveform 1 NORMAL Normal waveform BIAS 0x0 RW Bias Configuration These bits set the bias mode for the LCD Driver. 1:0 Value Mode Description 0 STATIC Static 1 ONEHALF 1/2 Bias 2 ONETHIRD 1/3 Bias 3 ONEFOURTH 1/4 Bias MUX 0x0 RW Mux Configuration These bits set the multiplexing mode for the LCD Driver. The field is dependent on the value of MUXE field MUX MUXE Mode Description 0 0 STATIC Static. Uses com line LCD_COM0. 1 0 DUPLEX Duplex. Uses com lines LCD_COM0LCD_COM1. 2 0 TRIPLEX Triplex. Uses com lines LCD_COM0LCD_COM2. 3 0 QUADRUPLEX Quadruplex. Uses com lines LCD_COM0LCD_COM3. 1 1 SEXTAPLEX Sextaplex. Uses com lines LCD_COM0LCD_COM5. 3 1 OCTAPLEX Octaplex. Uses com lines LCD_COM0LCD_COM7. 29.5.3 LCD_SEGEN - Segment Enable Register 0 1 2 3 4 5 0x000 6 7 8 9 10 11 12 13 14 15 RW Reset SEGEN Access Name 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x008 Bit Position 31 Offset 516 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 9:0 SEGEN 0x000 RW Segment Enable Determines which segment lines are enabled. Each bit represents a group of 4 segment lines. To enable segment lines X to X+3, set bit X/4, i.e. to enable output on segment lines 4,5,6 and 7, set bit 1. Each LCD segment pin can also be individually disabled by setting the pin to any other state than DISABLED in the GPIO pin configuration. 29.5.4 LCD_BACTRL - Blink and Animation Control Register (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p. 20) . Access 0 0 RW BLINKEN 1 2 RW 0 0 RW AEN BLANK 3 4 0x0 RW AREGASC 5 6 0x0 RW AREGBSC 7 0 RW ALOGSEL 8 9 10 11 12 13 14 0 RW FCEN Name 15 0x0 RW FCTOP Access FCPRESC RW Reset 16 17 18 19 20 21 0x00 22 23 24 25 26 27 28 29 30 0x00C Bit Position 31 Offset Bit Name Reset Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 23:18 FCTOP 0x00 RW Frame Counter Top Value These bits contain the Top Value for the Frame Counter: CLKEVENT = CLKFC / (1 + FCTOP[5:0]). 17:16 FCPRESC 0x0 RW Frame Counter Prescaler These bits controls the prescaling value for the Frame Counter input clock. Value Mode Description 0 DIV1 CLKFC = CLKFRAME / 1 1 DIV2 CLKFC = CLKFRAME / 2 2 DIV4 CLKFC = CLKFRAME / 4 3 DIV8 CLKFC = CLKFRAME / 8 15:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 8 FCEN 0 RW Frame Counter Enable When this bit is set, the frame counter is enabled. 7 ALOGSEL 0 RW Animate Logic Function Select When this bit is set, the animation registers are AND'ed together. When this bit is cleared, the animation registers are OR'ed together. 6:5 Value Mode Description 0 AND AREGA and AREGB AND'ed 1 OR AREGA and AREGB OR'ed AREGBSC 0x0 RW Animate Register B Shift Control These bits controls the shift operation that is performed on Animation register B. 4:3 Value Mode Description 0 NOSHIFT No Shift operation on Animation Register B 1 SHIFTLEFT Animation Register B is shifted left 2 SHIFTRIGHT Animation Register B is shifted right AREGASC 0x0 RW Animate Register A Shift Control These bits controls the shift operation that is performed on Animation register A. Value Mode Description 0 NOSHIFT No Shift operation on Animation Register A 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 517 www.silabs.com ...the world's most energy friendly microcontrollers Bit 2 Name Reset Access Description Value Mode Description 1 SHIFTLEFT Animation Register A is shifted left 2 SHIFTRIGHT Animation Register A is shifted right AEN 0 RW Animation Enable When this bit is set, the animate function is enabled. 1 BLANK 0 RW Blank Display When this bit is set, all segment output waveforms are configured to blank the LCD display. The Segment Data Registers are not affected when writing this bit. 0 Value Description 0 Display is not "blanked" 1 Display is "blanked" BLINKEN 0 RW Blink Enable When this bit is set, the Blink function is enabled. Every "ON" segment will alternate between on and off at every Frame Counter Event. 29.5.5 LCD_STATUS - Status Register Name Access 0 R BLINK ASTATE R Access 1 2 0x0 3 4 5 6 7 0 Reset 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x010 Bit Position 31 Offset Bit Name Reset Description 31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 8 BLINK 0 R Blink State This bits indicates the blink status. If this bit is 1, all segments are off. If this bit is 0, the segments(LCD_SEGDxn) which are set to 1 are on. 7:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 3:0 ASTATE 0x0 R Current Animation State Contains the current animation state (0-15). 29.5.6 LCD_AREGA - Animation Register A (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p. 20) . 0 1 2 3 4 0x00 5 6 7 8 9 10 11 12 13 14 15 RW Reset AREGA Access Name 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x014 17 Bit Position Offset 518 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 7:0 AREGA 0x00 RW Animation Register A Data This register contains the A data for generating animation pattern. 29.5.7 LCD_AREGB - Animation Register B (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p. 20) . 0 1 2 3 4 0x00 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x018 Bit Position 31 Offset RW Reset AREGB Access Name Bit Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 7:0 AREGB 0x00 RW Animation Register B Data This register contains the B data for generating animation pattern. 29.5.8 LCD_IF - Interrupt Flag Register 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x01C Bit Position 31 Offset R Access FC Name Bit Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 0 FC 0 R Frame Counter Interrupt Flag Set when Frame Counter is zero. 29.5.9 LCD_IFS - Interrupt Flag Set Register 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 W1 Access FC Name 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 15 0 Reset 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x020 Bit Position 31 Offset 519 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 0 FC 0 W1 Frame Counter Interrupt Flag Set Write to 1 to set FC interrupt flag. 29.5.10 LCD_IFC - Interrupt Flag Clear Register W1 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x024 Bit Position 31 Offset Access FC Name Bit Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 0 FC 0 W1 Frame Counter Interrupt Flag Clear Write to 1 to clear FC interrupt flag. 29.5.11 LCD_IEN - Interrupt Enable Register 0 1 2 RW 0 Reset 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x028 Bit Position 31 Offset Access FC Name Bit Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 0 FC 0 RW Frame Counter Interrupt Enable Set to enable interrupt on frame counter interrupt flag. 29.5.12 LCD_SEGD0L - Segment Data Low Register 0 (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p. 20) . 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 520 www.silabs.com ...the world's most energy friendly microcontrollers 0 1 2 3 4 5 6 7 8 9 10 11 12 0x000000 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x040 Bit Position 31 Offset RW Reset SEGD0L Access Name Bit Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 23:0 SEGD0L 0x000000 RW COM0 Segment Data Low This register contains segment data for segment lines 0-23 for COM0. 29.5.13 LCD_SEGD1L - Segment Data Low Register 1 (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p. 20) . 0 1 2 3 4 5 6 7 8 9 10 11 0x000000 12 13 14 15 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x044 17 Bit Position Offset RW Reset SEGD1L Access Name Bit Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 23:0 SEGD1L 0x000000 RW COM1 Segment Data Low This register contains segment data for segment lines 0-23 for COM1. 29.5.14 LCD_SEGD2L - Segment Data Low Register 2 (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p. 20) . 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 521 www.silabs.com ...the world's most energy friendly microcontrollers 0 1 2 3 4 5 6 7 8 9 10 11 12 0x000000 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x048 Bit Position 31 Offset RW Reset SEGD2L Access Name Bit Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 23:0 SEGD2L 0x000000 RW COM2 Segment Data Low This register contains segment data for segment lines 0-23 for COM2. 29.5.15 LCD_SEGD3L - Segment Data Low Register 3 (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p. 20) . 0 1 2 3 4 5 6 7 8 9 10 11 0x000000 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x04C Bit Position 31 Offset RW Reset SEGD3L Access Name Bit Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 23:0 SEGD3L 0x000000 RW COM3 Segment Data Low This register contains segment data for segment lines 0-23 for COM3. 29.5.16 LCD_FREEZE - Freeze Register 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 RW REGFREEZE Access Name 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 15 0 Reset 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x060 Bit Position 31 Offset 522 www.silabs.com ...the world's most energy friendly microcontrollers Bit Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 0 REGFREEZE 0 RW Register Update Freeze When set, the update of the LCD is postponed until this bit is cleared. Use this bit to update several registers simultaneously. Value Mode Description 0 UPDATE Each write access to an LCD register is updated into the Low Frequency domain as soon as possible. 1 FREEZE The LCD is not updated with the new written value. 29.5.17 LCD_SYNCBUSY - Synchronization Busy Register Access 0 0 R CTRL 1 2 R 0 0 R AREGA BACTRL 3 0 R AREGB 4 0 R SEGD0L 6 7 5 0 R SEGD1L 0 R SEGD2L 0 R SEGD3L 8 9 10 11 12 13 14 15 16 0 R SEGD4L 17 R SEGD5L 0 18 19 R SEGD6L Name R Access SEGD7L 0 Reset 0 20 21 22 23 24 25 26 27 28 29 30 0x064 Bit Position 31 Offset Bit Name Reset Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 19 SEGD7L 0 R SEGD7L Register Busy Set when the value written to SEGD7L is being synchronized. 18 SEGD6L 0 R SEGD6L Register Busy Set when the value written to SEGD6L is being synchronized. 17 SEGD5L 0 R SEGD5L Register Busy Set when the value written to SEGD5L is being synchronized. 16 SEGD4L 0 R SEGD4L Register Busy Set when the value written to SEGD4L is being synchronized. 15:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 7 SEGD3L 0 R SEGD3L Register Busy Set when the value written to SEGD3L is being synchronized. 6 SEGD2L 0 R SEGD2L Register Busy Set when the value written to SEGD2L is being synchronized. 5 SEGD1L 0 R SEGD1L Register Busy Set when the value written to SEGD1L is being synchronized. 4 SEGD0L 0 R SEGD0L Register Busy Set when the value written to SEGD0L is being synchronized. 3 AREGB 0 R AREGB Register Busy Set when the value written to AREGB is being synchronized. 2 AREGA 0 R AREGA Register Busy Set when the value written to AREGA is being synchronized. 1 BACTRL 0 R BACTRL Register Busy Set when the value written to BACTRL is being synchronized. 0 CTRL 0 R CTRL Register Busy Set when the value written to CTRL is being synchronized. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 523 www.silabs.com ...the world's most energy friendly microcontrollers 29.5.18 LCD_SEGD4L - Segment Data Low Register 4 (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p. 20) . 0 1 2 3 4 5 6 7 8 9 10 11 12 0x000000 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x0CC Bit Position 31 Offset RW Reset SEGD4L Access Name Bit Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 23:0 SEGD4L 0x000000 RW COM4 Segment Data This register contains segment data for segment lines 0-23 for COM4. 29.5.19 LCD_SEGD5L - Segment Data Low Register 5 (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p. 20) . 0 1 2 3 4 5 6 7 8 9 10 11 0x000000 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x0D0 Bit Position 31 Offset RW Reset SEGD5L Access Name Bit Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 23:0 SEGD5L 0x000000 RW COM5 Segment Data This register contains segment data for segment lines 0-23 for COM5. 29.5.20 LCD_SEGD6L - Segment Data Low Register 6 (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p. 20) . 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 524 www.silabs.com ...the world's most energy friendly microcontrollers 0 1 2 3 4 5 6 7 8 9 10 11 12 0x000000 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x0D4 Bit Position 31 Offset RW Reset SEGD6L Access Name Bit Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 23:0 SEGD6L 0x000000 RW COM6 Segment Data This register contains segment data for segment lines 0-23 for COM6. 29.5.21 LCD_SEGD7L - Segment Data Low Register 7 (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p. 20) . 0 1 2 3 4 5 6 7 8 9 10 11 0x000000 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x0D8 Bit Position 31 Offset RW Reset SEGD7L Access Name Bit Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 23:0 SEGD7L 0x000000 RW COM7 Segment Data This register contains segment data for segment lines 0-23 for COM7. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 525 www.silabs.com ...the world's most energy friendly microcontrollers 30 Revision History 30.1 Revision 1.20 July 2nd, 2014 Added QFP part numbers to Product Overview table. Updated current numbers and voltage supply range. Moved chapter "Device Revision" to section 3. 30.2 Revision 1.10 August 22nd, 2013 Corrected UART data frame rate. Corrected MSC_WDATA description. Corrected CMU IFS description. Updated OPAMP register description. Corrected 3 Opamp Differential Amplifier gain programming bits. Corrected Opamp Cascaded gain equations. Corrected alternative location number for LEAURT and I2C. Updated CMU LFA/LFAE and LFB/LFBE CLKSEL description. Updated info page size for Flash memory. Updated DI page table with family part number and corrected the address of AUXHFRCO calibration value. Updated package types. Updated LETIMER Async Support in Reflex Producers table. Updated the I2C Clock Mode table and added the Maximum Data Hold Time formula. Added the minimum HFPERCLK requirement for I2C Slave Operation. Added a new register access type RW1H. Updated RMU Reset Cause Register Interpretation table. Updated CMU_CALCNT description. Updated DMA_CHENC register description. Updated description of number of wait-states for Immediate Synchronization. Updated description of the Excite Phase timing in LESENSE. Updated the LETIMER PRS description. Updated OPAMP description. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 526 www.silabs.com ...the world's most energy friendly microcontrollers Added LPFMODE recommendation for the ADC Input Filtering. Updated the LETIMER description for usage in EM3. Updated the RTC description for usage in EM3. Updated WRITEONCE bitfield description in MSC_WRITECMD register. Updated the MSC_TIMEBASE register description. Updated the DMA access description. Document changed status from "Preliminary". Updated trademark, disclaimer and contact information. Other minor corrections. 30.3 Revision 1.00 May 19th, 2011 Added information about backpowering the MCU if Vdd drops below SCL and SDA lines voltage. Added information on ACMP warm up with LPREF. Changed formula in VDDLEVEL bitfield in ACMPn_INPUTSEL. Added sine wave minimum amplitude to BUFEXTCLK. Changed description of IRQERASEABORT. Updated description of WARMUPMODE in ADC section. Added documentation for DMA_CHREQSTATUS, DMA_CHSREQSTATUS. Renamed DMA_WAITSTATUS to DMA_CHWAITSTATUS and updated bit fields. Updated general description of bus system. Updated frequency limitations when clocking TIMER from external source. Updated information on disabling of individual LCD segment lines. Added LETIMER and LESENSE to asyncheronous support table. Updated gain settings for 3 diff Opamp mode. Update description of OPAMP output to ADC. Updated description of the Low Pass Filter on the input of the Opamps. Corrected COM4-COM7 SEG line placement. Corrected I2S Mono waveform. Corrected the I2C Clock Modes FAST value to 14:9. Corrected EFM32TG Microcontroller Series table. Updated HFXO/LFXO description. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 527 www.silabs.com ...the world's most energy friendly microcontrollers Updated EM0-EM4 current consumption. 30.4 Revision 0.90 December 21th, 2010 Major updates to all chapters. 30.5 Revision 0.80 October 1st, 2010 Initial preliminary revision. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 528 www.silabs.com ...the world's most energy friendly microcontrollers A Abbreviations A.1 Abbreviations This section lists abbreviations used in this document. Table A.1. Abbreviations Abbreviation Description ACMP Analog Comparator ADC Analog to Digital Converter AHB AMBA Advanced High-performance Bus. AMBA is short for "Advanced Microcontroller Bus Architecture". APB AMBA Advanced Peripheral Bus. AMBA is short for "Advanced Microcontroller Bus Architecture". ALE Address Latch Enable AUXHFRCO Auxiliary High Frequency RC Oscillator. CC Compare / Capture CLK Clock CMD Command CMU Clock Management Unit CTRL Control DAC Digital to Analog Converter DBG Debug DMA Direct Memory Access DRD Dual Role Device EFM Energy Friendly Microcontroller EM Energy Mode EM0 Energy Mode 0 (also called active mode) EM1 to EM4 Energy Mode 1 to Energy Mode 4 (also called low energy modes) EMU Energy Management Unit ENOB Effective Number of Bits FS Full-speed GPIO General Purpose Input / Output HFRCO High Frequency RC Oscillator HFXO High Frequency Crystal Oscillator HW Hardware 2 I C Inter-Integrated Circuit interface LCD Liquid Crystal Display LESENSE Low Energy Sensor Interface LETIMER Low Energy Timer LEUART Low Energy Universal Asynchronous Receiver Transmitter 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 529 www.silabs.com ...the world's most energy friendly microcontrollers Abbreviation Description LFRCO Low Frequency RC Oscillator LFXO Low Frequency Crystal Oscillator LS Low-speed MAC Media Access Controller NVIC Nested Vector Interrupt Controller OPA/OPAMP Operational Amplifier OSR Oversampling Ratio OTG On-the-go PCNT Pulse Counter PGA Programmable Gain Array PHY Physical Layer PRS Peripheral Reflex System PSRR Power Supply Rejection Ratio PWM Pulse Width Modulation RC Resistance and Capacitance RMU Reset Management Unit RTC Real Time Clock SAR Successive Approximation Register SOF Start of Frame SPI Serial Peripheral Interface SW Software THD Total Harmonic Distortion USART Universal Synchronous Asynchronous Receiver Transmitter USB Universal Serial Bus VCMP Voltage supply Comparator WDOG Watchdog timer XTAL Crystal 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 530 www.silabs.com ...the world's most energy friendly microcontrollers B Disclaimer and Trademarks B.1 Disclaimer Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. Silicon Laboratories products are generally not intended for military applications. Silicon Laboratories products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons. B.2 Trademark Information Silicon Laboratories Inc., Silicon Laboratories, Silicon Labs, SiLabs and the Silicon Labs logo, CMEMS®, EFM, EFM32, EFR, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZMac®, EZRadio®, EZRadioPRO®, DSPLL®, ISOmodem®, Precision32®, ProSLIC®, SiPHY®, USBXpress® and others are trademarks or registered trademarks of Silicon Laboratories Inc. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other products or brand names mentioned herein are trademarks of their respective holders. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 531 www.silabs.com ...the world's most energy friendly microcontrollers C Contact Information Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Please visit the Silicon Labs Technical Support web page: http://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 532 www.silabs.com ...the world's most energy friendly microcontrollers Table of Contents 1. Energy Friendly Microcontrollers .................................................................................................................. 2 1.1. Typical Applications ......................................................................................................................... 2 1.2. EFM32TG Development ................................................................................................................... 2 2. About This Document ................................................................................................................................ 3 2.1. Conventions ................................................................................................................................... 3 2.2. Related Documentation .................................................................................................................... 4 3. System Overview ...................................................................................................................................... 5 3.1. Introduction .................................................................................................................................... 5 3.2. Features ....................................................................................................................................... 5 3.3. Block Diagram ............................................................................................................................... 6 3.4. Energy Modes ................................................................................................................................ 7 3.5. Product Overview ........................................................................................................................... 8 3.6. Device Revision ............................................................................................................................ 10 4. System Processor .................................................................................................................................... 11 4.1. Introduction .................................................................................................................................. 11 4.2. Features ...................................................................................................................................... 11 4.3. Functional Description .................................................................................................................... 12 5. Memory and Bus System .......................................................................................................................... 14 5.1. Introduction .................................................................................................................................. 14 5.2. Functional Description .................................................................................................................... 15 5.3. Access to Low Energy Peripherals (Asynchronous Registers) ................................................................ 20 5.4. Flash .......................................................................................................................................... 23 5.5. SRAM ......................................................................................................................................... 23 5.6. Device Information (DI) Page .......................................................................................................... 23 6. DBG - Debug Interface ............................................................................................................................. 25 6.1. Introduction .................................................................................................................................. 25 6.2. Features ...................................................................................................................................... 25 6.3. Functional Description .................................................................................................................... 25 6.4. Debug Lock and Device Erase ........................................................................................................ 26 6.5. Register Map ............................................................................................................................... 28 6.6. Register Description ...................................................................................................................... 28 7. MSC - Memory System Controller ............................................................................................................. 30 7.1. Introduction .................................................................................................................................. 30 7.2. Features ...................................................................................................................................... 31 7.3. Functional Description .................................................................................................................... 31 7.4. Register Map ............................................................................................................................... 37 7.5. Register Description ...................................................................................................................... 37 8. DMA - DMA Controller ............................................................................................................................. 46 8.1. Introduction .................................................................................................................................. 46 8.2. Features ...................................................................................................................................... 46 8.3. Block Diagram .............................................................................................................................. 47 8.4. Functional Description .................................................................................................................... 48 8.5. Examples .................................................................................................................................... 65 8.6. Register Map ............................................................................................................................... 67 8.7. Register Description ...................................................................................................................... 68 9. RMU - Reset Management Unit ................................................................................................................. 85 9.1. Introduction .................................................................................................................................. 85 9.2. Features ...................................................................................................................................... 85 9.3. Functional Description .................................................................................................................... 85 9.4. Register Map ............................................................................................................................... 89 9.5. Register Description ...................................................................................................................... 89 10. EMU - Energy Management Unit .............................................................................................................. 91 10.1. Introduction ................................................................................................................................ 91 10.2. Features .................................................................................................................................... 91 10.3. Functional Description .................................................................................................................. 92 10.4. Register Map .............................................................................................................................. 97 10.5. Register Description ..................................................................................................................... 97 11. CMU - Clock Management Unit ............................................................................................................... 99 11.1. Introduction ................................................................................................................................ 99 11.2. Features .................................................................................................................................... 99 11.3. Functional Description ................................................................................................................ 100 11.4. Register Map ............................................................................................................................ 109 11.5. Register Description ................................................................................................................... 110 12. WDOG - Watchdog Timer ...................................................................................................................... 130 12.1. Introduction ............................................................................................................................... 130 12.2. Features .................................................................................................................................. 130 12.3. Functional Description ................................................................................................................ 130 12.4. Register Map ............................................................................................................................ 132 12.5. Register Description ................................................................................................................... 132 13. PRS - Peripheral Reflex System ............................................................................................................. 135 13.1. Introduction ............................................................................................................................... 135 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 533 www.silabs.com ...the world's most energy friendly microcontrollers 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 13.2. Features .................................................................................................................................. 13.3. Functional Description ................................................................................................................ 13.4. Register Map ............................................................................................................................ 13.5. Register Description ................................................................................................................... 2 I C - Inter-Integrated Circuit Interface ....................................................................................................... 14.1. Introduction ............................................................................................................................... 14.2. Features .................................................................................................................................. 14.3. Functional Description ................................................................................................................ 14.4. Register Map ............................................................................................................................ 14.5. Register Description ................................................................................................................... USART - Universal Synchronous Asynchronous Receiver/Transmitter ............................................................ 15.1. Introduction ............................................................................................................................... 15.2. Features .................................................................................................................................. 15.3. Functional Description ................................................................................................................ 15.4. Register Map ............................................................................................................................ 15.5. Register Description ................................................................................................................... LEUART - Low Energy Universal Asynchronous Receiver/Transmitter ............................................................ 16.1. Introduction ............................................................................................................................... 16.2. Features .................................................................................................................................. 16.3. Functional Description ................................................................................................................ 16.4. Register Map ............................................................................................................................ 16.5. Register Description ................................................................................................................... TIMER - Timer/Counter ......................................................................................................................... 17.1. Introduction ............................................................................................................................... 17.2. Features .................................................................................................................................. 17.3. Functional Description ................................................................................................................ 17.4. Register Map ............................................................................................................................ 17.5. Register Description ................................................................................................................... RTC - Real Time Counter ...................................................................................................................... 18.1. Introduction ............................................................................................................................... 18.2. Features .................................................................................................................................. 18.3. Functional Description ................................................................................................................ 18.4. Register Map ............................................................................................................................ 18.5. Register Description ................................................................................................................... LETIMER - Low Energy Timer ................................................................................................................ 19.1. Introduction ............................................................................................................................... 19.2. Features .................................................................................................................................. 19.3. Functional Description ................................................................................................................ 19.4. Register Map ............................................................................................................................ 19.5. Register Description ................................................................................................................... PCNT - Pulse Counter .......................................................................................................................... 20.1. Introduction ............................................................................................................................... 20.2. Features .................................................................................................................................. 20.3. Functional Description ................................................................................................................ 20.4. Register Map ............................................................................................................................ 20.5. Register Description ................................................................................................................... LESENSE - Low Energy Sensor Interface ................................................................................................. 21.1. Introduction ............................................................................................................................... 21.2. Features .................................................................................................................................. 21.3. Functional description ................................................................................................................. 21.4. Register Map ............................................................................................................................ 21.5. Register Description ................................................................................................................... ACMP - Analog Comparator ................................................................................................................... 22.1. Introduction ............................................................................................................................... 22.2. Features .................................................................................................................................. 22.3. Functional Description ................................................................................................................ 22.4. Register Map ............................................................................................................................ 22.5. Register Description ................................................................................................................... VCMP - Voltage Comparator .................................................................................................................. 23.1. Introduction ............................................................................................................................... 23.2. Features .................................................................................................................................. 23.3. Functional Description ................................................................................................................ 23.4. Register Map ............................................................................................................................ 23.5. Register Description ................................................................................................................... ADC - Analog to Digital Converter ........................................................................................................... 24.1. Introduction ............................................................................................................................... 24.2. Features .................................................................................................................................. 24.3. Functional Description ................................................................................................................ 24.4. Register Map ............................................................................................................................ 24.5. Register Description ................................................................................................................... DAC - Digital to Analog Converter ........................................................................................................... 25.1. Introduction ............................................................................................................................... 25.2. Features .................................................................................................................................. 25.3. Functional Description ................................................................................................................ 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 534 135 135 140 140 145 145 145 146 167 167 179 179 179 180 205 205 225 225 225 226 237 237 251 251 251 252 266 267 285 285 285 286 289 289 294 294 294 295 308 308 317 317 317 317 323 323 332 332 332 333 348 349 378 378 378 379 383 383 389 389 389 390 393 393 397 397 397 398 408 408 421 421 421 422 www.silabs.com ...the world's most energy friendly microcontrollers 25.4. Register Map ............................................................................................................................ 25.5. Register Description ................................................................................................................... 26. OPAMP - Operational Amplifier ............................................................................................................... 26.1. Introduction ............................................................................................................................... 26.2. Features .................................................................................................................................. 26.3. Functional Description ................................................................................................................ 26.4. Register Description ................................................................................................................... 26.5. Register Map ............................................................................................................................ 27. AES - Advanced Encryption Standard Accelerator ...................................................................................... 27.1. Introduction ............................................................................................................................... 27.2. Features .................................................................................................................................. 27.3. Functional Description ................................................................................................................ 27.4. Register Map ............................................................................................................................ 27.5. Register Description ................................................................................................................... 28. GPIO - General Purpose Input/Output ...................................................................................................... 28.1. Introduction ............................................................................................................................... 28.2. Features .................................................................................................................................. 28.3. Functional Description ................................................................................................................ 28.4. Register Map ............................................................................................................................ 28.5. Register Description ................................................................................................................... 29. LCD - Liquid Crystal Display Driver ......................................................................................................... 29.1. Introduction ............................................................................................................................... 29.2. Features .................................................................................................................................. 29.3. Functional Description ................................................................................................................ 29.4. Register Map ............................................................................................................................ 29.5. Register Description ................................................................................................................... 30. Revision History ................................................................................................................................... 30.1. Revision 1.20 ............................................................................................................................ 30.2. Revision 1.10 ............................................................................................................................ 30.3. Revision 1.00 ............................................................................................................................ 30.4. Revision 0.90 ............................................................................................................................ 30.5. Revision 0.80 ............................................................................................................................ A. Abbreviations ........................................................................................................................................ A.1. Abbreviations .............................................................................................................................. B. Disclaimer and Trademarks ..................................................................................................................... B.1. Disclaimer .................................................................................................................................. B.2. Trademark Information ................................................................................................................. C. Contact Information ................................................................................................................................ C.1. ............................................................................................................................................... 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 535 427 427 442 442 442 443 452 452 453 453 453 453 457 457 465 465 465 466 473 474 490 490 490 491 514 514 526 526 526 527 528 528 529 529 531 531 531 532 532 www.silabs.com ...the world's most energy friendly microcontrollers List of Figures 3.1. Block Diagram of EFM32TG .................................................................................................................... 7 3.2. Energy Mode Indicator ............................................................................................................................. 7 3.3. Revision Number Extraction .................................................................................................................... 10 4.1. Interrupt Operation ................................................................................................................................ 12 5.1. EFM32TG Bus System .......................................................................................................................... 15 5.2. System Address Space .......................................................................................................................... 16 5.3. Write operation to Low Energy Peripherals ................................................................................................ 21 5.4. Read operation from Low Energy Peripherals ............................................................................................. 22 6.1. AAP - Authentication Access Port ............................................................................................................ 26 6.2. Device Unlock ...................................................................................................................................... 27 6.3. AAP Expansion .................................................................................................................................... 27 7.1. Instruction Cache .................................................................................................................................. 34 8.1. DMA Block Diagram .............................................................................................................................. 47 8.2. Polling flowchart .................................................................................................................................... 50 8.3. Ping-pong example ................................................................................................................................ 52 8.4. Memory scatter-gather example ............................................................................................................... 55 8.5. Peripheral scatter-gather example ............................................................................................................ 57 8.6. Memory map for 8 channels, including the alternate data structure ................................................................. 59 8.7. Detailed memory map for the 8 channels, including the alternate data structure ................................................. 60 8.8. channel_cfg bit assignments ................................................................................................................... 61 9.1. RMU Reset Input Sources and Connections. .............................................................................................. 86 9.2. RMU Power-on Reset Operation .............................................................................................................. 87 9.3. RMU Brown-out Detector Operation .......................................................................................................... 88 10.1. EMU Overview .................................................................................................................................... 92 10.2. EMU Energy Mode Transitions .............................................................................................................. 93 11.1. CMU Overview .................................................................................................................................. 101 11.2. CMU Switching from HFRCO to HFXO before HFXO is ready .................................................................... 104 11.3. CMU Switching from HFRCO to HFXO after HFXO is ready ....................................................................... 105 11.4. HFXO Pin Connection ........................................................................................................................ 105 11.5. LFXO Pin Connection ......................................................................................................................... 106 11.6. HW-support for RC Oscillator Calibration ................................................................................................ 107 11.7. Single Calibration (CONT=0) ................................................................................................................ 107 11.8. Continuous Calibration (CONT=1) ......................................................................................................... 107 13.1. PRS Overview ................................................................................................................................... 136 13.2. TIMER0 overflow starting ADC0 single conversions through PRS channel 5. ................................................. 139 2 14.1. I C Overview .................................................................................................................................... 146 2 14.2. I C-Bus Example ............................................................................................................................... 146 2 14.3. I C START and STOP Conditions ......................................................................................................... 147 2 2 14.4. I C Bit Transfer on I C-Bus ................................................................................................................. 147 2 14.5. I C Single Byte Write to Slave ............................................................................................................. 148 2 14.6. I C Double Byte Read from Slave ......................................................................................................... 148 2 14.7. I C Single Byte Write, then Repeated Start and Single Byte Read ............................................................... 148 2 14.8. I C Master Transmitter/Slave Receiver with 10-bit Address ........................................................................ 149 2 14.9. I C Master Receiver/Slave Transmitter with 10-bit Address ........................................................................ 149 2 14.10. I C Master State Machine .................................................................................................................. 153 2 14.11. I C Slave State Machine ................................................................................................................... 160 15.1. USART Overview ............................................................................................................................... 180 15.2. USART Asynchronous Frame Format .................................................................................................... 181 15.3. USART Transmit Buffer Operation ........................................................................................................ 185 15.4. USART Receive Buffer Operation ......................................................................................................... 187 15.5. USART Sampling of Start and Data Bits ................................................................................................ 188 15.6. USART Sampling of Stop Bits when Number of Stop Bits are 1 or More ....................................................... 189 15.7. USART Local Loopback ...................................................................................................................... 190 15.8. USART Half Duplex Communication with External Driver ........................................................................... 191 15.9. USART Transmission of Large Frames .................................................................................................. 192 15.10. USART Transmission of Large Frames, MSBF ...................................................................................... 192 15.11. USART Reception of Large Frames ..................................................................................................... 193 15.12. USART ISO 7816 Data Frame Without Error ......................................................................................... 194 15.13. USART ISO 7816 Data Frame With Error ............................................................................................. 195 15.14. USART SmartCard Stop Bit Sampling .................................................................................................. 195 15.15. USART SPI Timing .......................................................................................................................... 197 15.16. USART Standard I2S waveform .......................................................................................................... 199 15.17. USART Standard I2S waveform (reduced accuracy) ............................................................................... 200 15.18. USART Left-justified I2S waveform ...................................................................................................... 200 15.19. USART Right-justified I2S waveform .................................................................................................... 200 15.20. USART Mono I2S waveform .............................................................................................................. 201 15.21. USART Example RZI Signal for a given Asynchronous USART Frame ....................................................... 203 16.1. LEUART Overview ............................................................................................................................. 226 16.2. LEUART Asynchronous Frame Format .................................................................................................. 227 16.3. LEUART Transmitter Overview ............................................................................................................. 229 16.4. LEUART Receiver Overview ................................................................................................................ 231 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 536 www.silabs.com ...the world's most energy friendly microcontrollers 16.5. LEUART Local Loopback .................................................................................................................... 16.6. LEUART Half Duplex Communication with External Driver ......................................................................... 16.7. LEUART - NRZ vs. RZI ...................................................................................................................... 17.1. TIMER Block Overview ....................................................................................................................... 17.2. TIMER Hardware Timer/Counter Control ................................................................................................ 17.3. TIMER Clock Selection ....................................................................................................................... 17.4. TIMER Connections ........................................................................................................................... 17.5. TIMER TOP Value Update Functionality ................................................................................................. 17.6. TIMER Quadrature Encoded Inputs ....................................................................................................... 17.7. TIMER Quadrature Decoder Configuration .............................................................................................. 17.8. TIMER X2 Decoding Mode .................................................................................................................. 17.9. TIMER X4 Decoding Mode .................................................................................................................. 17.10. TIMER Input Pin Logic ...................................................................................................................... 17.11. TIMER Input Capture Buffer Functionality ............................................................................................. 17.12. TIMER Output Compare/PWM Buffer Functionality ................................................................................. 17.13. TIMER Input Capture ........................................................................................................................ 17.14. TIMER Period and/or Pulse width Capture ............................................................................................ 17.15. TIMER Block Diagram Showing Comparison Functionality ........................................................................ 17.16. TIMER Output Logic ......................................................................................................................... 17.17. TIMER Up-count Frequency Generation ............................................................................................... 17.18. TIMER Up-count PWM Generation ...................................................................................................... 17.19. TIMER CC out in 2x mode ................................................................................................................ 17.20. TIMER Up/Down-count PWM Generation .............................................................................................. 17.21. TIMER CC out in 2x mode ................................................................................................................ 18.1. RTC Overview ................................................................................................................................... 19.1. LETIMER Overview ............................................................................................................................ 19.2. LETIMER State Machine for Free-running Mode ...................................................................................... 19.3. LETIMER One-shot Repeat State Machine ............................................................................................. 19.4. LETIMER Buffered Repeat State Machine .............................................................................................. 19.5. LETIMER Double Repeat State Machine ................................................................................................ 19.6. LETIMER Simple Waveforms Output ..................................................................................................... 19.7. LETIMER Repeated Counting .............................................................................................................. 19.8. LETIMER Dual Output ........................................................................................................................ 19.9. LETIMER Triggered Operation ............................................................................................................. 19.10. LETIMER Continuous Operation ......................................................................................................... 19.11. LETIMER LETIMERn_CNT Not Initialized to 0 ....................................................................................... 20.1. PCNT Overview ................................................................................................................................. 20.2. PCNT Quadrature Coding ................................................................................................................... 20.3. PCNT Direction Change Interrupt (DIRCNG) Generation ........................................................................... 21.1. LESENSE block diagram ..................................................................................................................... 21.2. Scan sequence ................................................................................................................................. 21.3. Timing diagram, short excitation ........................................................................................................... 21.4. Pin sequencing .................................................................................................................................. 21.5. Scan result and interrupt generation ...................................................................................................... 21.6. Sensor scan and decode sequence ...................................................................................................... 21.7. Decoder state transition evaluation ........................................................................................................ 21.8. Decoder hysteresis ............................................................................................................................ 21.9. Circular result buffer ........................................................................................................................... 21.10. Capacitive sense setup ..................................................................................................................... 21.11. LC sensor setup .............................................................................................................................. 21.12. LC sensor oscillations ....................................................................................................................... 21.13. FSM example 1 ............................................................................................................................... 21.14. FSM example 2 ............................................................................................................................... 22.1. ACMP Overview ................................................................................................................................ 22.2. 20 mV Hysteresis Selected .................................................................................................................. 22.3. Capacitive Sensing Set-up ................................................................................................................... 23.1. VCMP Overview ................................................................................................................................ 23.2. VCMP 20 mV Hysteresis Enabled ......................................................................................................... 24.1. ADC Overview .................................................................................................................................. 24.2. ADC Conversion Timing ...................................................................................................................... 24.3. ADC Analog Power Consumption With Different WARMUPMODE Settings .................................................... 24.4. ADC RC Input Filter Configuration ........................................................................................................ 24.5. ADC Bias Programming ...................................................................................................................... 24.6. ADC Conversion Tailgating .................................................................................................................. 25.1. DAC Overview .................................................................................................................................. 25.2. DAC Bias Programming ...................................................................................................................... 25.3. DAC Sine Mode ................................................................................................................................ 26.1. OPAMP System Overview ................................................................................................................... 26.2. OPAMP Overview .............................................................................................................................. 26.3. Opamp Output Stage Overview ............................................................................................................ 26.4. Voltage Follower Unity Gain Overview ................................................................................................... 26.5. Inverting input PGA Overview .............................................................................................................. 26.6. Non-inverting PGA Overview ................................................................................................................ 26.7. Cascaded Inverting PGA Overview ....................................................................................................... 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 537 234 234 236 252 254 254 255 255 256 256 257 257 258 259 259 260 260 261 261 262 262 263 264 264 286 295 297 298 299 300 302 302 303 304 305 306 318 319 322 333 335 335 337 338 338 340 341 342 344 344 345 346 346 379 381 382 390 391 399 400 401 402 403 404 422 424 425 443 444 445 446 447 447 448 www.silabs.com ...the world's most energy friendly microcontrollers 26.8. Cascaded Non-inverting PGA Overview ................................................................................................. 26.9. Two Op-amp Differential Amplifier Overview ........................................................................................... 26.10. Three Op-amp Differential Amplifier Overview ........................................................................................ 26.11. Dual Buffer ADC Driver Overview ....................................................................................................... 27.1. AES Key and Data Definitions .............................................................................................................. 27.2. AES Data and Key Orientation as Defined in the Advanced Encryption Standard ............................................ 27.3. AES Data and Key Register Operation .................................................................................................. 28.1. Pin Configuration ............................................................................................................................... 28.2. Tristated Output with Optional Pull-up or Pull-down .................................................................................. 28.3. Push-Pull Configuration ....................................................................................................................... 28.4. Open-drain ....................................................................................................................................... 28.5. EM4 Wake-up Logic ........................................................................................................................... 28.6. Pin n Interrupt Generation ................................................................................................................... 29.1. LCD Block Diagram ........................................................................................................................... 29.2. LCD Low-power Waveform for LCD_COM0 in Quadruples Multiplex Mode, 1/3 Bias ........................................ 29.3. LCD Normal Waveform for LCD_COM0 in Quadruples Multiplex Mode, 1/3 Bias ............................................ 29.4. LCD Static Bias and Multiplexing - LCD_COM0 ....................................................................................... 29.5. LCD 1/2 Bias and Duplex Multiplexing - LCD_COM0 ................................................................................ 29.6. LCD 1/2 Bias and Duplex Multiplexing - LCD_COM1 ................................................................................ 29.7. LCD 1/2 Bias and Duplex Multiplexing - LCD_SEG0 ................................................................................. 29.8. LCD 1/2 Bias and Duplex Multiplexing - LCD_SEG0 Connection ................................................................. 29.9. LCD 1/2 Bias and Duplex Multiplexing - LCD_SEG0-LCD_COM0 ................................................................ 29.10. LCD 1/2 Bias and Duplex Multiplexing - LCD_SEG0-LCD_COM1 .............................................................. 29.11. LCD 1/3 Bias and Duplex Multiplexing - LCD_COM0 .............................................................................. 29.12. LCD 1/3 Bias and Duplex Multiplexing - LCD_COM1 .............................................................................. 29.13. LCD 1/3 Bias and Duplex Multiplexing - LCD_SEG0 ............................................................................... 29.14. LCD 1/3 Bias and Duplex Multiplexing - LCD_SEG0 Connection ............................................................... 29.15. LCD 1/3 Bias and Duplex Multiplexing - LCD_SEG0-LCD_COM0 .............................................................. 29.16. LCD 1/3 Bias and Duplex Multiplexing - LCD_SEG0-LCD_COM1 .............................................................. 29.17. LCD 1/2 Bias and Triplex Multiplexing - LCD_COM0 ............................................................................... 29.18. LCD 1/2 Bias and Triplex Multiplexing - LCD_COM1 ............................................................................... 29.19. LCD 1/2 Bias and Triplex Multiplexing - LCD_COM2 ............................................................................... 29.20. LCD 1/2 Bias and Triplex Multiplexing - LCD_SEG0 ............................................................................... 29.21. LCD 1/2 Bias and Triplex Multiplexing - LCD_SEG0 Connection ................................................................ 29.22. LCD 1/2 Bias and Triplex Multiplexing - LCD_SEG0-LCD_COM0 .............................................................. 29.23. LCD 1/2 Bias and Triplex Multiplexing - LCD_SEG0-LCD_COM1 .............................................................. 29.24. LCD 1/2 Bias and Triplex Multiplexing - LCD_SEG0-LCD_COM2 .............................................................. 29.25. LCD 1/3 Bias and Triplex Multiplexing - LCD_COM0 ............................................................................... 29.26. LCD 1/3 Bias and Triplex Multiplexing - LCD_COM1 ............................................................................... 29.27. LCD 1/3 Bias and Triplex Multiplexing - LCD_COM2 ............................................................................... 29.28. LCD 1/3 Bias and Triplex Multiplexing - LCD_SEG0 ............................................................................... 29.29. LCD 1/3 Bias and Triplex Multiplexing - LCD_SEG0 Connection ................................................................ 29.30. LCD 1/3 Bias and Triplex Multiplexing - LCD_SEG0-LCD_COM0 .............................................................. 29.31. LCD 1/3 Bias and Triplex Multiplexing - LCD_SEG0-LCD_COM1 .............................................................. 29.32. LCD 1/3 Bias and Triplex Multiplexing - LCD_SEG0-LCD_COM2 .............................................................. 29.33. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_COM0 ........................................................................ 29.34. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_COM1 ........................................................................ 29.35. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_COM2 ........................................................................ 29.36. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_COM3 ........................................................................ 29.37. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_SEG0 ......................................................................... 29.38. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_SEG0 Connection ......................................................... 29.39. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_SEG0-LCD_COM0 ........................................................ 29.40. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_SEG0-LCD_COM1 ........................................................ 29.41. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_SEG0-LCD_COM2 ........................................................ 29.42. LCD 1/3 Bias and Quadruplex Multiplexing- LCD_SEG0-LCD_COM3 ......................................................... 29.43. LCD Clock System in LCD Driver ........................................................................................................ 29.44. LCD Block Diagram of the Animation Circuit ......................................................................................... 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 538 449 450 451 452 454 454 455 467 468 469 469 470 471 491 493 493 493 494 494 494 494 495 495 495 496 496 496 497 497 497 497 498 498 498 498 499 499 499 500 500 500 500 501 501 501 502 502 502 502 503 503 503 504 504 504 510 512 www.silabs.com ...the world's most energy friendly microcontrollers List of Tables 2.1. Register Access Types ............................................................................................................................ 3 3.1. Energy Mode Description ......................................................................................................................... 8 3.2. EFM32TG Microcontroller Series ............................................................................................................... 8 3.3. Minor Revision Number Interpretation ....................................................................................................... 10 4.1. Interrupt Request Lines (IRQ) .................................................................................................................. 12 5.1. Memory System Core Peripherals ............................................................................................................ 17 5.2. Memory System Low Energy Peripherals ................................................................................................... 18 5.3. Memory System Peripherals .................................................................................................................... 19 5.4. Device Information Page Contents ........................................................................................................... 23 7.1. MSC Flash Memory Mapping .................................................................................................................. 32 7.2. Lock Bits Page Structure ........................................................................................................................ 32 8.1. AHB bus transfer arbitration interval ......................................................................................................... 49 8.2. DMA channel priority ............................................................................................................................. 49 8.3. DMA cycle types ................................................................................................................................... 51 8.4. channel_cfg for a primary data structure, in memory scatter-gather mode ......................................................... 54 8.5. channel_cfg for a primary data structure, in peripheral scatter-gather mode ...................................................... 56 8.6. Address bit settings for the channel control data structure ............................................................................. 59 8.7. src_data_end_ptr bit assignments ............................................................................................................ 60 8.8. dst_data_end_ptr bit assignments ............................................................................................................ 61 8.9. channel_cfg bit assignments ................................................................................................................... 61 8.10. DMA cycle of six words using a word increment ........................................................................................ 64 8.11. DMA cycle of 12 bytes using a halfword increment .................................................................................... 65 9.1. RMU Reset Cause Register Interpretation ................................................................................................. 87 10.1. EMU Energy Mode Overview ................................................................................................................. 94 10.2. EMU Entering a Low Energy Mode ......................................................................................................... 95 10.3. EMU Wakeup Triggers from Low Energy Modes ....................................................................................... 96 13.1. Reflex Producers ............................................................................................................................... 137 13.2. Reflex Consumers ............................................................................................................................. 138 2 2 14.1. I C Reserved I C Addresses ................................................................................................................ 148 2 14.2. I C High and Low Periods for Low CLKDIV ............................................................................................ 150 2 14.3. I C Clock Mode ................................................................................................................................. 151 2 14.4. I C Interactions in Prioritized Order ....................................................................................................... 154 2 14.5. I C Master Transmitter ........................................................................................................................ 156 2 14.6. I C Master Receiver ........................................................................................................................... 158 2 14.7. I C STATE Values ............................................................................................................................. 159 2 14.8. I C Transmission Status ...................................................................................................................... 159 2 14.9. I C Slave Transmitter ......................................................................................................................... 162 2 14.10. I C - Slave Receiver ......................................................................................................................... 163 2 14.11. I C Bus Error Response .................................................................................................................... 164 15.1. USART Asynchronous vs. Synchronous Mode ........................................................................................ 181 15.2. USART Pin Usage ............................................................................................................................. 181 15.3. USART Data Bits ............................................................................................................................... 182 15.4. USART Stop Bits ............................................................................................................................... 182 15.5. USART Parity Bits ............................................................................................................................. 183 15.6. USART Oversampling ......................................................................................................................... 183 15.7. USART Baud Rates @ 4MHz Peripheral Clock ....................................................................................... 184 15.8. USART SPI Modes ............................................................................................................................ 196 15.9. USART I2S Modes ............................................................................................................................ 199 15.10. USART IrDA Pulse Widths ................................................................................................................. 204 16.1. LEUART Parity Bit ............................................................................................................................. 227 16.2. LEUART Baud Rates ......................................................................................................................... 228 17.1. TIMER Counter Response in X2 Decoding Mode ..................................................................................... 257 17.2. TIMER Counter Response in X4 Decoding Mode ..................................................................................... 257 17.3. TIMER Events ................................................................................................................................... 265 18.1. RTC Resolution Vs Overflow ............................................................................................................... 287 19.1. LETIMER Repeat Modes ..................................................................................................................... 296 19.2. LETIMER Underflow Output Actions ...................................................................................................... 301 20.1. PCNT QUAD Mode Counter Control Function ......................................................................................... 320 21.1. LESENSE scan configuration selection .................................................................................................. 334 21.2. LESENSE excitation pin mapping ......................................................................................................... 336 21.3. LESENSE decoder configuration .......................................................................................................... 346 21.4. LESENSE decoder configuration .......................................................................................................... 347 22.1. Bias Configuration .............................................................................................................................. 380 23.1. Bias Configuration .............................................................................................................................. 390 24.1. ADC Single Ended Conversion ............................................................................................................. 404 24.2. ADC Differential Conversion ................................................................................................................ 405 24.3. Oversampling Result Shifting and Resolution .......................................................................................... 405 24.4. ADC Results Representation ................................................................................................................ 406 24.5. Calibration Register Effect ................................................................................................................... 407 26.1. General Opamp Mode Configuration ..................................................................................................... 446 26.2. Voltage Follower Unity Gain Configuration .............................................................................................. 446 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 539 www.silabs.com ...the world's most energy friendly microcontrollers 26.3. Inverting input PGA Configuration ......................................................................................................... 26.4. Non-inverting PGA Configuration .......................................................................................................... 26.5. Cascaded Inverting PGA Configuration .................................................................................................. 26.6. Cascaded Non-inverting PGA Configuration ............................................................................................ 26.7. OPA0/OPA1 Differential Amplifier Configuration ....................................................................................... 26.8. OPA1/OPA2 Differential Amplifier Configuration ....................................................................................... 26.9. Three Opamp Differential Amplifier Gain Programming .............................................................................. 26.10. Three Opamp Differential Amplifier Configuration ................................................................................... 26.11. Dual Buffer ADC Driver Configuration .................................................................................................. 28.1. Pin Configuration ............................................................................................................................... 28.2. EM4 WU Register bits to pin mapping ................................................................................................... 29.1. LCD Mux Settings .............................................................................................................................. 29.2. LCD BIAS Settings ............................................................................................................................ 29.3. LCD Wave Settings ............................................................................................................................ 29.4. LCD Contrast .................................................................................................................................... 29.5. LCD Contrast Function ....................................................................................................................... 29.6. LCD Principle of Contrast Adjustment for Different Bias Settings. ................................................................ 29.7. LCD VLCD ......................................................................................................................................... 29.8. LCD VBOOST Frequency ...................................................................................................................... 29.9. LCD Frame rate Conversion Table ........................................................................................................ 29.10. LCD Update Data Control (UDCTRL) Bits ............................................................................................. 29.11. DSC BIAS Encoding ......................................................................................................................... 29.12. FCPRESC ...................................................................................................................................... 29.13. LCD Animation Shift Register ............................................................................................................. 29.14. LCD Animation Pattern ...................................................................................................................... 29.15. LCD Animation Example .................................................................................................................... A.1. Abbreviations ...................................................................................................................................... 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 540 447 447 448 449 450 450 451 451 452 467 470 492 492 493 505 505 506 507 507 508 509 509 510 511 511 512 529 www.silabs.com ...the world's most energy friendly microcontrollers List of Examples 8.1. DMA Transfer ....................................................................................................................................... 66 15.1. USART Multi-processor Mode Example .................................................................................................. 193 19.1. LETIMER Triggered Output Generation .................................................................................................. 304 19.2. LETIMER Continuous Output Generation ............................................................................................... 305 19.3. LETIMER PWM Output ....................................................................................................................... 306 19.4. LETIMER PWM Output ....................................................................................................................... 306 27.1. AES Cipher Block Chaining ................................................................................................................. 456 28.1. GPIO Interrupt Example ...................................................................................................................... 472 29.1. LCD Event Frequency Example ............................................................................................................ 510 29.2. LCD Animation Enable Example ........................................................................................................... 513 29.3. LCD Animation Dependence Example ................................................................................................... 513 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 541 www.silabs.com ...the world's most energy friendly microcontrollers List of Equations 5.1. Memory SRAM Area Set/Clear Bit ............................................................................................................ 16 5.2. Memory Peripheral Area Bit Modification ................................................................................................... 17 5.3. Memory Wait Cycles with Clock Equal or Faster than HFCORECLK ............................................................... 20 5.4. Memory Wait Cycles with Clock Slower than CPU ....................................................................................... 20 12.1. WDOG Timeout Equation .................................................................................................................... 131 2 14.1. I C Pull-up Resistor Equation ............................................................................................................... 146 2 14.2. I C Maximum Transmission Rate .......................................................................................................... 150 2 14.3. I C High and Low Cycles Equations ...................................................................................................... 150 14.4. Maximum Data Hold Time ................................................................................................................... 150 15.1. USART Baud Rate ............................................................................................................................. 183 15.2. USART Desired Baud Rate ................................................................................................................. 183 15.3. USART Synchronous Mode Bit Rate ..................................................................................................... 196 15.4. USART Synchronous Mode Clock Division Factor .................................................................................... 196 16.1. LEUART Baud Rate Equation .............................................................................................................. 228 16.2. LEUART CLKDIV Equation .................................................................................................................. 228 16.3. LEUART Optimal Sampling Point .......................................................................................................... 232 16.4. LEUART Actual Sampling Point ............................................................................................................ 232 17.1. TIMER Rotational Position Equation ...................................................................................................... 257 17.2. TIMER Up-count Frequency Generation Equation .................................................................................... 262 17.3. TIMER Up-count PWM Resolution Equation ............................................................................................ 262 17.4. TIMER Up-count PWM Frequency Equation ............................................................................................ 262 17.5. TIMER Up-count Duty Cycle Equation ................................................................................................... 263 17.6. TIMER 2x PWM Resolution Equation .................................................................................................... 263 17.7. TIMER 2x Mode PWM Frequency Equation( Up-count) ............................................................................. 263 17.8. TIMER 2x Mode Duty Cycle Equation .................................................................................................... 263 17.9. TIMER Up/Down-count PWM Resolution Equation ................................................................................... 264 17.10. TIMER Up/Down-count PWM Frequency Equation .................................................................................. 264 17.11. TIMER Up/Down-count Duty Cycle Equation ......................................................................................... 264 17.12. TIMER 2x PWM Resolution Equation ................................................................................................... 264 17.13. TIMER 2x Mode PWM Frequency Equation( Up/Down-count) ................................................................... 265 17.14. TIMER 2x Mode Duty Cycle Equation .................................................................................................. 265 18.1. RTC Frequency Equation .................................................................................................................... 286 19.1. LETIMER Clock Frequency .................................................................................................................. 300 20.1. Absolute position with hysteresis and even TOP value .............................................................................. 320 20.2. Absolute position with hysteresis and odd TOP value ............................................................................... 320 21.1. Scan frequency ................................................................................................................................. 335 22.1. VDD Scaled ....................................................................................................................................... 381 23.1. VCMP VDD Trigger Level .................................................................................................................... 391 24.1. ADC Total Conversion Time (in ADC_CLK cycles) Per Output .................................................................... 399 24.2. ADC Temperature Measurement .......................................................................................................... 402 25.1. DAC Clock Prescaling ........................................................................................................................ 423 25.2. DAC Single Ended Output Voltage ........................................................................................................ 424 25.3. DAC Differential Output Voltage ........................................................................................................... 424 25.4. DAC Sine Generation ......................................................................................................................... 425 29.1. LCD Frame rate Calculation ................................................................................................................ 508 29.2. LCD Event Frequency Equation ............................................................................................................ 510 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20 542 www.silabs.com