EFM32TG840F32-D-QFN64

EFM32 Gecko Family EFM32TG Data Sheet The EFM32 Gecko MCUs are the world’s most energy-friendly microcontrollers. KEY FEATURES The EFM32TG offers unmatched performance and ultra low power consumption in both active and sleep modes. EFM32TG devices consume as little as 0.6 μA in Stop mode and 150 μA/MHz in Run mode. It also features autonomous peripherals, high overall chip and analog integration, and the performance of the industry standard 32-bit ARM CortexM3 processor, making it perfect for battery-powered systems and systems with high-performance, low-energy requirements. • Industrial and home automation • Alarm and security systems • Health and fitness applications Core / Memory Clock Management ARM CortexTM M3 processor Flash Program Memory RAM Memory • Ultra low power operation • 0.6 μA current in Stop (EM3), with brown-out detection and RAM retention • 51 μA/MHz in EM1 • 150 μA/MHz in Run mode (EM0) • Fast wake-up time of 2 µs EFM32TG applications include the following: • Smart metering • Water metering • Gas metering • ARM Cortex-M3 at 32 MHz Debug Interface DMA Controller High Frequency Crystal Oscillator High Frequency RC Oscillator Auxiliary High Freq. RC Osc. Low Freq. RC Oscillator Low Frequency Crystal Oscillator Watchdog Oscillator • Hardware cryptography (AES) • Up to 32 kB of Flash and 4 kB of RAM Energy Management Voltage Regulator Voltage Comparator Power-on Reset Brown-out Detector Security Hardware AES 32-bit bus Peripheral Reflex System Serial Interfaces USART Low Energy UARTTM I2C I/O Ports External Interrupts Pin Reset Timers and Triggers General Purpose I/O Analog Interfaces Timer/Counter LESENSE ADC DAC Low Energy Timer Real Time Counter Operational Amplifier Analog Comparator Pulse Counter Watchdog Timer LCD Controller Lowest power mode with peripheral operational: EM0 - Active EM1 - Sleep silabs.com | Building a more connected world. EM2 – Deep Sleep EM3 - Stop EM4 - Shutoff Rev. 2.11 EFM32TG Data Sheet Feature List 1. Feature List • ARM Cortex-M3 CPU platform • High Performance 32-bit processor @ up to 32 MHz • Wake-up Interrupt Controller • SysTick System Timer • Flexible Energy Management System • 20 nA @ 3 V Shutoff Mode • 0.6 µA @ 3 V Stop Mode, including Power-on Reset, Brown-out Detector, RAM and CPU retention • 1.0 µA @ 3 V Deep Sleep Mode, including RTC with 32.768 kHz oscillator, Power-on Reset, Brown-out Detector, RAM and CPU retention • 51 µA/MHz @ 3 V Sleep Mode • 150 µA/MHz @ 3 V Run Mode, with code executed from flash • 32/16/8 KB Flash • 4/2 KB RAM • Up to 56 General Purpose I/O pins • Configurable push-pull, open-drain, pull-up/down, input filter, drive strength • Configurable peripheral I/O locations • 16 asynchronous external interrupts • Output state retention and wake-up from Shutoff Mode • 8 Channel DMA Controller • 8 Channel Peripheral Reflex System (PRS) for autonomous inter- peripheral signaling • Hardware AES with 128/256-bit keys in 54/75 cycles • Timers/Counters • 2× 16-bit Timer/Counter • 2×3 Compare/Capture/PWM channels • 16-bit Low Energy Timer • 1× 24-bit Real-Time Counter • 1× 16-bit Pulse Counter • Watchdog Timer with dedicated RC oscillator @ 50 nA • Integrated LCD Controller for up to 8×20 segments • Voltage boost, adjustable contrast and autonomous animation • Communication interfaces • Up to 2× Universal Synchronous/Asynchronous Receiver/ Transmitter • UART/SPI/SmartCard (ISO 7816)/IrDA/I2S • Low Energy UART • Autonomous operation with DMA in Deep Sleep Mode 2 • I C Interface with SMBus support • Address recognition in Stop Mode • Ultra low power precision analog peripherals • 12-bit 1 Msamples/s Analog to Digital Converter • 8 single ended channels/4 differential channels • On-chip temperature sensor • 12-bit 500 ksamples/s Digital to Analog Converter • Up to 2× Analog Comparator • Capacitive sensing with up to 8 inputs • 3× Operational Amplifier • 6.1 MHz GBW, Rail-to-rail, Programmable Gain • Supply Voltage Comparator • Low Energy Sensor Interface (LESENSE) • Autonomous sensor monitoring in Deep Sleep Mode • Wide range of sensors supported, including LC sensors and capacitive buttons • Ultra efficient Power-on Reset and Brown-Out Detector silabs.com | Building a more connected world. Rev. 2.11 | 2 EFM32TG Data Sheet Feature List • 2-pin Serial Wire Debug interface • 1-pin Serial Wire Viewer • Pre-Programmed UART Bootloader • Temperature range -40 to 85 ºC • Single power supply 1.98 to 3.8 V • Packages: • BGA48 • QFN24 • QFN32 • QFN64 • TQFP48 • TQFP64 silabs.com | Building a more connected world. Rev. 2.11 | 3 EFM32TG Data Sheet Ordering Information 2. Ordering Information The following table shows the available EFM32TG devices. Table 2.1. Ordering Information Flash (kB) RAM (kB) Max Speed (MHz) Supply Voltage (V) Temperature (ºC) Package EFM32TG108F4-D-QFN24 4 2 32 1.98 - 3.8 -40 - 85 QFN24 EFM32TG108F8-D-QFN24 8 2 32 1.98 - 3.8 -40 - 85 QFN24 EFM32TG108F16-D-QFN24 16 4 32 1.98 - 3.8 -40 - 85 QFN24 EFM32TG108F32-D-QFN24 32 4 32 1.98 - 3.8 -40 - 85 QFN24 EFM32TG110F4-D-QFN24 4 2 32 1.98 - 3.8 -40 - 85 QFN24 EFM32TG110F8-D-QFN24 8 2 32 1.98 - 3.8 -40 - 85 QFN24 EFM32TG110F16-D-QFN24 16 4 32 1.98 - 3.8 -40 - 85 QFN24 EFM32TG110F32-D-QFN24 32 4 32 1.98 - 3.8 -40 - 85 QFN24 EFM32TG210F8-D-QFN32 8 2 32 1.98 - 3.8 -40 - 85 QFN32 EFM32TG210F16-D-QFN32 16 4 32 1.98 - 3.8 -40 - 85 QFN32 EFM32TG210F32-D-QFN32 32 4 32 1.98 - 3.8 -40 - 85 QFN32 EFM32TG222F8-D-QFP48 8 2 32 1.98 - 3.8 -40 - 85 TQFP48 EFM32TG222F16-D-QFP48 16 4 32 1.98 - 3.8 -40 - 85 TQFP48 EFM32TG222F32-D-QFP48 32 4 32 1.98 - 3.8 -40 - 85 TQFP48 EFM32TG225F8-D-BGA48 8 2 32 1.98 - 3.8 -40 - 85 BGA48 EFM32TG225F16-D-BGA48 16 4 32 1.98 - 3.8 -40 - 85 BGA48 EFM32TG225F32-D-BGA48 32 4 32 1.98 - 3.8 -40 - 85 BGA48 EFM32TG230F8-D-QFN64 8 2 32 1.98 - 3.8 -40 - 85 QFN64 EFM32TG230F16-D-QFN64 16 4 32 1.98 - 3.8 -40 - 85 QFN64 EFM32TG230F32-D-QFN64 32 4 32 1.98 - 3.8 -40 - 85 QFN64 EFM32TG232F8-D-QFP64 8 2 32 1.98 - 3.8 -40 - 85 TQFP64 EFM32TG232F16-D-QFP64 16 4 32 1.98 - 3.8 -40 - 85 TQFP64 EFM32TG232F32-D-QFP64 32 4 32 1.98 - 3.8 -40 - 85 TQFP64 EFM32TG822F8-D-QFP48 8 2 32 1.98 - 3.8 -40 - 85 TQFP48 EFM32TG822F16-D-QFP48 16 4 32 1.98 - 3.8 -40 - 85 TQFP48 EFM32TG822F32-D-QFP48 32 4 32 1.98 - 3.8 -40 - 85 TQFP48 EFM32TG825F8-D-BGA48 8 2 32 1.98 - 3.8 -40 - 85 BGA48 EFM32TG825F16-D-BGA48 16 4 32 1.98 - 3.8 -40 - 85 BGA48 EFM32TG825F32-D-BGA48 32 4 32 1.98 - 3.8 -40 - 85 BGA48 EFM32TG840F8-D-QFN64 8 2 32 1.98 - 3.8 -40 - 85 QFN64 EFM32TG840F16-D-QFN64 16 4 32 1.98 - 3.8 -40 - 85 QFN64 EFM32TG840F32-D-QFN64 32 4 32 1.98 - 3.8 -40 - 85 QFN64 Ordering Code silabs.com | Building a more connected world. Rev. 2.11 | 4 EFM32TG Data Sheet Ordering Information Flash (kB) RAM (kB) Max Speed (MHz) Supply Voltage (V) Temperature (ºC) Package EFM32TG842F8-D-QFP64 8 2 32 1.98 - 3.8 -40 - 85 TQFP64 EFM32TG842F16-D-QFP64 16 4 32 1.98 - 3.8 -40 - 85 TQFP64 EFM32TG842F32-D-QFP64 32 4 32 1.98 - 3.8 -40 - 85 TQFP64 Ordering Code EFM32 TG 842 F 32 – D – QFP 64 R Reel (Optional) Pin Count Package Revision Memory Size in kB Memory Type (Flash) Feature Set Code Gecko Energy Friendly Microcontroller 32-bit Figure 2.1. Ordering Code Decoder Adding the suffix 'R' to the part number (e.g. EFM32TG842F32-D-QFP64R) denotes reel. Visit http://www.silabs.com for information on global distributors and representatives. silabs.com | Building a more connected world. Rev. 2.11 | 5 Table of Contents 1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3. System Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 System Introduction . . . . . . . . . . . . . . . . . . . 3.1.1 ARM Cortex-M3 Core . . . . . . . . . . . . . . . . . 3.1.2 Debug Interface (DBG) . . . . . . . . . . . . . . . . . 3.1.3 Memory System Controller (MSC) . . . . . . . . . . . . . 3.1.4 Direct Memory Access Controller (DMA) . . . . . . . . . . . 3.1.5 Reset Management Unit (RMU) . . . . . . . . . . . . . . 3.1.6 Energy Management Unit (EMU) . . . . . . . . . . . . . 3.1.7 Clock Management Unit (CMU) . . . . . . . . . . . . . . 3.1.8 Watchdog (WDOG) . . . . . . . . . . . . . . . . . . 3.1.9 Peripheral Reflex System (PRS) . . . . . . . . . . . . . 3.1.10 Inter-Integrated Circuit Interface (I2C) . . . . . . . . . . . 3.1.11 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) 3.1.12 Pre-Programmed UART Bootloader . . . . . . . . . . . . 3.1.13 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) 3.1.14 Timer/Counter (TIMER) . . . . . . . . . . . . . . . . 3.1.15 Real Time Counter (RTC) . . . . . . . . . . . . . . . 3.1.16 Low Energy Timer (LETIMER) . . . . . . . . . . . . . . 3.1.17 Pulse Counter (PCNT) . . . . . . . . . . . . . . . . 3.1.18 Analog Comparator (ACMP) . . . . . . . . . . . . . . 3.1.19 Voltage Comparator (VCMP) . . . . . . . . . . . . . . 3.1.20 Analog to Digital Converter (ADC) . . . . . . . . . . . . 3.1.21 Digital to Analog Converter (DAC) . . . . . . . . . . . . 3.1.22 Operational Amplifier (OPAMP) . . . . . . . . . . . . . 3.1.23 Low Energy Sensor Interface (LESENSE) . . . . . . . . . . 3.1.24 Advanced Encryption Standard Accelerator (AES) . . . . . . . 3.1.25 General Purpose Input/Output (GPIO) . . . . . . . . . . . 3.1.26 Liquid Crystal Display Driver (LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 .10 .10 .10 .11 .11 .11 .11 .11 .11 .11 .11 .11 .11 .12 .12 .12 .12 .12 .12 .12 .12 .12 .12 .13 .13 .13 3.2 Configuration Summary 3.2.1 EFM32TG108 . . 3.2.2 EFM32TG110 . . 3.2.3 EFM32TG210 . . 3.2.4 EFM32TG222 . . 3.2.5 EFM32TG225 . . 3.2.6 EFM32TG230 . . 3.2.7 EFM32TG232 . . 3.2.8 EFM32TG822 . . 3.2.9 EFM32TG825 . . 3.2.10 EFM32TG840 . 3.2.11 EFM32TG842 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 .14 .15 .16 .17 .18 .19 .20 .21 .22 .23 .24 3.3 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . .25 . . . 4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 27 silabs.com | Building a more connected world. Rev. 2.11 | 6 4.1 Test Conditions . . . . . . . . 4.1.1 Typical Values . . . . . . 4.1.2 Minimum and Maximum Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 .27 .27 4.2 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . .27 4.3 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . .27 4.4 Current Consumption . . . . 4.4.1 EM2 Current Consumption 4.4.2 EM3 Current Consumption 4.4.3 EM4 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 .29 .29 .30 4.5 Transition between Energy Modes . . . . . . . . . . . . . . . . . . . . . . .30 4.6 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 4.7 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 4.8 General Purpose Input Output . . . . . . . . . . . . . . . . . . . . . . . . .32 4.9 Oscillators . . 4.9.1 LFXO. . . 4.9.2 HFXO . . 4.9.3 LFRCO . . 4.9.4 HFRCO . . 4.9.5 AUXHFRCO 4.9.6 ULFRCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 .40 .40 .41 .42 .46 .46 4.10 Analog Digital Converter (ADC) . 4.10.1 Typical Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 .53 4.11 Digital Analog Converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . .57 4.12 Operational Amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . .59 4.13 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . . . . . .64 4.14 Voltage Comparator (VCMP) . . . . . . . . . . . . . . . . . . . . . . . . .66 4.15 LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 4.16 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 4.17 Digital Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.1 EFM32TG108 (QFN24) . . . . 5.1.1 Pinout . . . . . . . . 5.1.2 Alternate Functionality Pinout 5.1.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 .71 .74 .76 5.2 EFM32TG110 (QFN24) . . . . 5.2.1 Pinout . . . . . . . . 5.2.2 Alternate Functionality Pinout 5.2.3 GPIO Pinout Overview . . . 5.2.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 .77 .80 .82 .83 5.3 EFM32TG210 (QFN32) . . . . 5.3.1 Pinout . . . . . . . . 5.3.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 .84 .87 silabs.com | Building a more connected world. Rev. 2.11 | 7 5.3.3 GPIO Pinout Overview . . 5.3.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 .90 5.4 EFM32TG222 (TQFP48) . . . 5.4.1 Pinout . . . . . . . . 5.4.2 Alternate Functionality Pinout 5.4.3 GPIO Pinout Overview . . . 5.4.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 .91 .95 .98 .98 5.5 EFM32TG225 (BGA48) . . . . . . . . . . . . . . . . . . . . . . . . . . .99 5.5.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 5.5.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . 103 . 5.5.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 106 5.5.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . .106 5.6 EFM32TG230 (QFN64) . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.6.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 . 07 5.6.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . 112 . 5.6.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 116 5.6.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . .116 5.7 EFM32TG232 (TQFP64) . . . . . . . . . . . . . . . . . . . . . . . . 117 . 5.7.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 . 17 5.7.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . 122 . 5.7.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 126 5.7.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . .126 5.8 EFM32TG822 (TQFP48) . . . . . . . . . . . . . . . . . . . . . . . . 127 . 5.8.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 . 27 5.8.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . 131 . 5.8.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 135 5.8.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . .135 5.9 EFM32TG825 (BGA48) . . . . . . . . . . . . . . . . . . . . . . . . . . 136 5.9.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 . 36 5.9.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . 140 . 5.9.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 144 5.9.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . .144 5.10 EFM32TG840 (QFN64) . . . . . . . . . . . . . . . . . . . . . . . . 145 . 5.10.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 5.10.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .150 5.10.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 1 . 55 5.10.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 155 5.11 EFM32TG842 (TQFP64) . . . . . . . . . . . . . . . . . . . . . . . . .156 5.11.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 5.11.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .160 5.11.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 1 . 65 5.11.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 165 6. BGA48 Package Specifications 6.1 BGA48 Package Dimensions 6.2 BGA48 PCB Layout . . silabs.com | Building a more connected world. . . . . . . . . . . . . . . . . . . . . . . . 166 . . . . . . . . . . . . . . . . . . . . . . . . . 166 . . . . . . . . . . . . . . . . . . . . . . . .167 Rev. 2.11 | 8 6.3 BGA48 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . .169 7. QFN24 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . 170 7.1 QFN24 Package Dimensions 7.2 QFN24 PCB Layout . . 7.3 QFN24 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . 170 . . . . . . . . . . . . . . . . . . . . . . . . .171 . . . . . . . . . . . . . . . . . . . . . . . . .173 8. QFN32 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . 174 8.1 QFN32 Package Dimensions 8.2 QFN32 PCB Layout . . 8.3 QFN32 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . 174 . . . . . . . . . . . . . . . . . . . . . . . . .175 . . . . . . . . . . . . . . . . . . . . . . . . .177 9. QFN64 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . 178 9.1 QFN64 Package Dimensions 9.2 QFN64 PCB Layout . . 9.3 QFN64 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . 178 . . . . . . . . . . . . . . . . . . . . . . . . .180 . . . . . . . . . . . . . . . . . . . . . . . . .182 10. TQFP48 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . 183 10.1 TQFP48 Package Dimensions 10.2 TQFP48 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . .183 . . . . . . . . . . . . . . . . . . . . . . . .185 . . . . . . . . . . . . . . . . . . . . . . . 1. 87 10.3 TQFP48 Package Marking 11. TQFP64 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . 188 11.1 TQFP64 Package Dimensions 11.2 TQFP64 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . .188 . . . . . . . . . . . . . . . . . . . . . . . .190 . . . . . . . . . . . . . . . . . . . . . . . 1. 92 11.3 TQFP64 Package Marking 12. Chip Revision, Solder Information, Errata 12.1 Chip Revision . . . . 12.2 Soldering Information 12.3 Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 . . .193 . 193 . 13. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 silabs.com | Building a more connected world. Rev. 2.11 | 9 EFM32TG Data Sheet System Summary 3. System Summary 3.1 System Introduction The EFM32 MCUs are the world’s most energy friendly microcontrollers. With a unique combination of the powerful 32-bit ARM CortexM3, innovative low energy techniques, short wake-up time from energy saving modes, and a wide selection of peripherals, the EFM32TG microcontroller is well suited for any battery operated application as well as other systems requiring high performance and low-energy consumption. This section gives a short introduction to each of the modules in general terms and also shows a summary of the configuration for the EFM32TG devices. For a complete feature set and in-depth information on the modules, refer to the EFM32TG Reference Manual. A block diagram of the EFM32TG is shown in the following figure. Core / Memory Clock Management ARM CortexTM M3 processor Flash Program Memory Debug Interface RAM Memory DMA Controller High Frequency Crystal Oscillator High Frequency RC Oscillator Auxiliary High Freq. RC Osc. Low Freq. RC Oscillator Low Frequency Crystal Oscillator Watchdog Oscillator Energy Management Voltage Regulator Voltage Comparator Power-on Reset Brown-out Detector Security Hardware AES 32-bit bus Peripheral Reflex System Serial Interfaces USART I2C Low Energy UARTTM I/O Ports External Interrupts Pin Reset Timers and Triggers General Purpose I/O Analog Interfaces Timer/Counter LESENSE ADC DAC Low Energy Timer Real Time Counter Operational Amplifier Analog Comparator Pulse Counter Watchdog Timer LCD Controller Lowest power mode with peripheral operational: EM0 - Active EM1 - Sleep EM2 – Deep Sleep EM3 - Stop EM4 - Shutoff Figure 3.1. Block Diagram 3.1.1 ARM Cortex-M3 Core The ARM Cortex-M3 includes a 32-bit RISC processor which can achieve as much as 1.25 Dhrystone MIPS/MHz. A wake-up Interrupt Controller handling interrupts triggered while the CPU is asleep. The EFM32 implementation of the Cortex-M3 is described in detail in EFM32TG Reference Manual. 3.1.2 Debug Interface (DBG) This device includes hardware debug support through a 2-pin serial-wire debug interface. In addition there is also a 1-wire Serial Wire Viewer pin which can be used to output profiling information, data trace and software-generated messages. 3.1.3 Memory System Controller (MSC) The Memory System Controller (MSC) is the program memory unit of the EFM32TG microcontroller. The flash memory is readable and writable from both the Cortex-M3 and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code is normally written to the main block. Additionally, the information block is available for special user data and flash lock bits. There is also a read-only page in the information block containing system and device calibration data. Read and write operations are supported in the energy modes EM0 and EM1. silabs.com | Building a more connected world. Rev. 2.11 | 10 EFM32TG Data Sheet System Summary 3.1.4 Direct Memory Access Controller (DMA) The Direct Memory Access (DMA) controller performs memory operations independently of the CPU. This has the benefit of reducing the energy consumption and the workload of the CPU, and enables the system to stay in low energy modes when moving for instance data from the USART to RAM or from the External Bus Interface to a PWM-generating timer. The DMA controller uses the PL230 µDMA controller licensed from ARM. 3.1.5 Reset Management Unit (RMU) The RMU is responsible for handling the reset functionality of the EFM32TG. 3.1.6 Energy Management Unit (EMU) The Energy Management Unit (EMU) manage all the low energy modes (EM) in EFM32TG microcontrollers. Each energy mode manages if the CPU and the various peripherals are available. The EMU can also be used to turn off the power to unused SRAM blocks. 3.1.7 Clock Management Unit (CMU) The Clock Management Unit (CMU) is responsible for controlling the oscillators and clocks on-board the EFM32TG. The CMU provides the capability to turn on and off the clock on an individual basis to all peripheral modules in addition to enable/disable and configure the available oscillators. The high degree of flexibility enables software to minimize energy consumption in any specific application by not wasting power on peripherals and oscillators that are inactive. 3.1.8 Watchdog (WDOG) The purpose of the watchdog timer is to generate a reset in case of a system failure, to increase application reliability. The failure may e.g. be caused by an external event, such as an ESD pulse, or by a software failure. 3.1.9 Peripheral Reflex System (PRS) The Peripheral Reflex System (PRS) system is a network which lets the different peripheral module communicate directly with each other without involving the CPU. Peripheral modules which send out Reflex signals are called producers. The PRS routes these reflex signals to consumer peripherals which apply actions depending on the data received. The format for the Reflex signals is not given, but edge triggers and other functionality can be applied by the PRS. 3.1.10 Inter-Integrated Circuit Interface (I2C) The I2C module provides an interface between the MCU and a serial I2C-bus. It is capable of acting as both a master and a slave, and supports multi-master buses. Both standard-mode, fast-mode and fastmode plus speeds are supported, allowing transmission rates all the way from 10 kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also provided to allow implementation of an SMBus compliant system. The interface provided to software by the I2C module, allows both fine-grained control of the transmission process and close to automatic transfers. Automatic recognition of slave addresses is provided in all energy modes. 3.1.11 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) The Universal Synchronous Asynchronous serial Receiver and Transmitter (USART) is a very flexible serial I/O module. It supports full duplex asynchronous UART communication as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with ISO7816 SmartCards, IrDA, and I2S devices. 3.1.12 Pre-Programmed UART Bootloader The bootloader presented in application note AN0003 is pre-programmed in the device at factory. Autobaud and destructive write are supported. The autobaud feature, interface and commands are described further in the application note. 3.1.13 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) The unique LEUARTTM, the Low Energy UART, is a UART that allows two-way UART communication on a strict power budget. Only a 32.768 kHz clock is needed to allow UART communication up to 9600 baud/ s. The LEUART includes all necessary hardware support to make asynchronous serial communication possible with minimum of software intervention and energy consumption. silabs.com | Building a more connected world. Rev. 2.11 | 11 EFM32TG Data Sheet System Summary 3.1.14 Timer/Counter (TIMER) The 16-bit general purpose Timer has 3 compare/capture channels for input capture and compare/Pulse- Width Modulation (PWM) output. 3.1.15 Real Time Counter (RTC) The Real Time Counter (RTC) contains a 24-bit counter and is clocked either by a 32.768 kHz crystal oscillator, or a 32.768 kHz RC oscillator. In addition to energy modes EM0 and EM1, the RTC is also available in EM2. This makes it ideal for keeping track of time since the RTC is enabled in EM2 where most of the device is powered down. 3.1.16 Low Energy Timer (LETIMER) The unique LETIMERTM, the Low Energy Timer, is a 16-bit timer that is available in energy mode EM2 in addition to EM1 and EM0. Because of this, it can be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of waveforms with minimal software intervention. It is also connected to the Real Time Counter (RTC), and can be configured to start counting on compare matches from the RTC. 3.1.17 Pulse Counter (PCNT) The Pulse Counter (PCNT) can be used for counting pulses on a single input or to decode quadrature encoded inputs. It runs off either the internal LFACLK or the PCNTn_S0IN pin as external clock source. The module may operate in energy mode EM0 - EM3. 3.1.18 Analog Comparator (ACMP) The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is higher. Inputs can either be one of the selectable internal references or from external pins. Response time and thereby also the current consumption can be configured by altering the current supply to the comparator. 3.1.19 Voltage Comparator (VCMP) The Voltage Supply Comparator is used to monitor the supply voltage from software. An interrupt can be generated when the supply falls below or rises above a programmable threshold. Response time and thereby also the current consumption can be configured by altering the current supply to the comparator. 3.1.20 Analog to Digital Converter (ADC) The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to one million samples per second. The integrated input mux can select inputs from 8 external pins and 6 internal signals. 3.1.21 Digital to Analog Converter (DAC) The Digital to Analog Converter (DAC) can convert a digital value to an analog output voltage. The DAC is fully differential rail-to-rail, with 12-bit resolution. It has two single-ended output buffers which can be combined into one differential output. The DAC may be used for a number of different applications such as sensor interfaces or sound output. 3.1.22 Operational Amplifier (OPAMP) The EFM32TG features up to three Operational Amplifiers. The Operational Amplifier is a versatile general purpose amplifier with railto-rail differential input and rail-to-rail single-ended output. The input can be set to pin, DAC or OPAMP, whereas the output can be pin, OPAMP or ADC. The current is programmable and the OPAMP has various internal configurations such as unity gain, programmable gain using internal resistors etc. 3.1.23 Low Energy Sensor Interface (LESENSE) The Low Energy Sensor Interface (LESENSETM), is a highly configurable sensor interface with support for up to 8 individually configurable sensors. By controlling the analog comparators and DAC, LESENSE is capable of supporting a wide range of sensors and measurement schemes, and can for instance measure LC sensors, resistive sensors and capacitive sensors. LESENSE also includes a programmable FSM which enables simple processing of measurement results without CPU intervention. LESENSE is available in energy mode EM2, in addition to EM0 and EM1, making it ideal for sensor monitoring in applications with a strict energy budget. silabs.com | Building a more connected world. Rev. 2.11 | 12 EFM32TG Data Sheet System Summary 3.1.24 Advanced Encryption Standard Accelerator (AES) The AES accelerator performs AES encryption and decryption with 128-bit or 256-bit keys. Encrypting or decrypting one 128-bit data block takes 52 HFCORECLK cycles with 128-bit keys and 75 HFCORECLK cycles with 256-bit keys. The AES module is an AHB slave which enables efficient access to the data and key registers. All write accesses to the AES module must be 32-bit operations, i.e. 8- or 16-bit operations are not supported. 3.1.25 General Purpose Input/Output (GPIO) In the EFM32TG, there are up to 56 General Purpose Input/Output (GPIO) pins, which are divided into ports with up to 16 pins each. These pins can individually be configured as either an output or input. More advanced configurations like open-drain, filtering and drive strength can also be configured individually for the pins. The GPIO pins can also be overridden by peripheral pin connections, like Timer PWM outputs or USART communication, which can be routed to several locations on the device. The GPIO supports up to 16 asynchronous external pin interrupts, which enables interrupts from any pin on the device. Also, the input value of a pin can be routed through the Peripheral Reflex System to other peripherals. 3.1.26 Liquid Crystal Display Driver (LCD) The LCD driver is capable of driving a segmented LCD display with up to 8x20 segments. A voltage boost function enables it to provide the LCD display with higher voltage than the supply voltage for the device. In addition, an animation feature can run custom animations on the LCD display without any CPU intervention. The LCD driver can also remain active even in Energy Mode 2 and provides a Frame Counter interrupt that can wake-up the device on a regular basis for updating data. silabs.com | Building a more connected world. Rev. 2.11 | 13 EFM32TG Data Sheet System Summary 3.2 Configuration Summary 3.2.1 EFM32TG108 The features of the EFM32TG108 is a subset of the feature set described in the EFM32TG Reference Manual. The following table describes device specific implementation of the features. Table 3.1. EFM32TG108 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA I2C0 Full configuration I2C0_SDA, I2C0_SCL USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS LEUART0 Full configuration LEU0_TX, LEU0_RX TIMER0 Full configuration TIM0_CC[2:0] TIMER1 Full configuration TIM1_CC[2:0] RTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0] ACMP0 Full configuration ACMP0_CH[1:0], ACMP0_O ACMP1 Full configuration ACMP1_CH[1:0], ACMP1_O VCMP Full configuration NA GPIO 17 pins Available pins are shown in 5.1.3 GPIO Pinout Overview silabs.com | Building a more connected world. Rev. 2.11 | 14 EFM32TG Data Sheet System Summary 3.2.2 EFM32TG110 The features of the EFM32TG110 is a subset of the feature set described in the EFM32TG Reference Manual. The following table describes device specific implementation of the features. Table 3.2. EFM32TG110 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA I2C0 Full configuration I2C0_SDA, I2C0_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS LEUART0 Full configuration LEU0_TX, LEU0_RX TIMER0 Full configuration TIM0_CC[2:0] TIMER1 Full configuration TIM1_CC[2:0] RTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0] ACMP0 Full configuration ACMP0_CH[1:0], ACMP0_O ACMP1 Full configuration ACMP1_CH[1:0], ACMP1_O VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:6] DAC0 Full configuration DAC0_OUT[0], DAC0_OUTxALT OPAMP Full configuration Outputs: OPAMP_OUT0, OPAMP_OUT0ALT, OPAMP_OUT1ALT, Inputs: OPAMP_P1, OPAMP_N1 AES Full configuration NA GPIO 17 pins Available pins are shown in 5.2.3 GPIO Pinout Overview silabs.com | Building a more connected world. Rev. 2.11 | 15 EFM32TG Data Sheet System Summary 3.2.3 EFM32TG210 The features of the EFM32TG210 is a subset of the feature set described in the EFM32TG Reference Manual. The following table describes device specific implementation of the features. Table 3.3. EFM32TG210 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA I2C0 Full configuration I2C0_SDA, I2C0_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS LEUART0 Full configuration LEU0_TX, LEU0_RX TIMER0 Full configuration TIM0_CC[2:0] TIMER1 Full configuration TIM1_CC[2:0] RTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0] ACMP0 Full configuration ACMP0_CH[1:0], ACMP0_O ACMP1 Full configuration ACMP1_CH[7:5], ACMP1_O VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:4] DAC0 Full configuration DAC0_OUT[0], DAC0_OUTxALT OPAMP Full configuration Outputs: OPAMP_OUT0, OPAMP_OUT0ALT, OPAMP_OUT1ALT, OPAMP_OUT2, Inputs: OPAMP_P1, OPAMP_N1, OPAMP_P2 AES Full configuration NA GPIO 24 pins Available pins are shown in 5.3.3 GPIO Pinout Overview silabs.com | Building a more connected world. Rev. 2.11 | 16 EFM32TG Data Sheet System Summary 3.2.4 EFM32TG222 The features of the EFM32TG222 is a subset of the feature set described in the EFM32TG Reference Manual. The following table describes device specific implementation of the features. Table 3.4. EFM32TG222 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA I2C0 Full configuration I2C0_SDA, I2C0_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS LEUART0 Full configuration LEU0_TX, LEU0_RX TIMER0 Full configuration TIM0_CC[2:0] TIMER1 Full configuration TIM1_CC[2:0] RTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0] ACMP0 Full configuration ACMP0_CH[4:0], ACMP0_O ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:4] DAC0 Full configuration DAC0_OUT[1], DAC0_OUTxALT OPAMP Full configuration Outputs: OPAMP_OUT0, OPAMP_OUT0ALT, OPAMP_OUT1ALT, OPAMP_OUT2, Inputs: OPAMP_P0, OPAMP_P1, OPAMP_N1, OPAMP_P2 AES Full configuration NA GPIO 37 pins Available pins are shown in 5.4.3 GPIO Pinout Overview silabs.com | Building a more connected world. Rev. 2.11 | 17 EFM32TG Data Sheet System Summary 3.2.5 EFM32TG225 The features of the EFM32TG225 is a subset of the feature set described in the EFM32TG Reference Manual. The following table describes device specific implementation of the features. Table 3.5. EFM32TG225 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA I2C0 Full configuration I2C0_SDA, I2C0_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS LEUART0 Full configuration LEU0_TX, LEU0_RX TIMER0 Full configuration TIM0_CC[2:0] TIMER1 Full configuration TIM1_CC[2:0] RTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0] ACMP0 Full configuration ACMP0_CH[3:0], ACMP0_O ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:4] DAC0 Full configuration DAC0_OUT[0], DAC0_OUTxALT OPAMP Full configuration Outputs: OPAMP_OUT0, OPAMP_OUT0ALT, OPAMP_OUT1ALT, OPAMP_OUT2, Inputs: OPAMP_P0, OPAMP_P1, OPAMP_N1, OPAMP_P2 AES Full configuration NA GPIO 37 pins Available pins are shown in 5.5.3 GPIO Pinout Overview silabs.com | Building a more connected world. Rev. 2.11 | 18 EFM32TG Data Sheet System Summary 3.2.6 EFM32TG230 The features of the EFM32TG230 is a subset of the feature set described in the EFM32TG Reference Manual. The following table describes device specific implementation of the features. Table 3.6. EFM32TG230 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA I2C0 Full configuration I2C0_SDA, I2C0_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS LEUART0 Full configuration LEU0_TX, LEU0_RX TIMER0 Full configuration TIM0_CC[2:0] TIMER1 Full configuration TIM1_CC[2:0] RTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0] ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:0] DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx AES Full configuration NA GPIO 56 pins Available pins are shown in 5.6.3 GPIO Pinout Overview silabs.com | Building a more connected world. Rev. 2.11 | 19 EFM32TG Data Sheet System Summary 3.2.7 EFM32TG232 The features of the EFM32TG232 is a subset of the feature set described in the EFM32TG Reference Manual. The following table describes device specific implementation of the features. Table 3.7. EFM32TG232 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA I2C0 Full configuration I2C0_SDA, I2C0_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS LEUART0 Full configuration LEU0_TX, LEU0_RX TIMER0 Full configuration TIM0_CC[2:0] TIMER1 Full configuration TIM1_CC[2:0] RTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0] ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:0] DAC0 Full configuration DAC0_OUT[0], DAC0_OUTxALT OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx AES Full configuration NA GPIO 53 pins Available pins are shown in 5.7.3 GPIO Pinout Overview silabs.com | Building a more connected world. Rev. 2.11 | 20 EFM32TG Data Sheet System Summary 3.2.8 EFM32TG822 The features of the EFM32TG822 is a subset of the feature set described in the EFM32TG Reference Manual. The following table describes device specific implementation of the features. Table 3.8. EFM32TG822 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA I2C0 Full configuration I2C0_SDA, I2C0_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS LEUART0 Full configuration LEU0_TX, LEU0_RX TIMER0 Full configuration TIM0_CC[2:0] TIMER1 Full configuration TIM1_CC[2:0] RTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0] ACMP0 Full configuration ACMP0_CH[4], ACMP0_O ACMP1 Full configuration ACMP1_CH[7:5], ACMP1_O VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:4] DAC0 Full configuration DAC0_OUT[0], DAC0_OUTxALT OPAMP Full configuration Outputs: OPAMP_OUT0, OPAMP_OUT1ALT, OPAMP_OUT2, Inputs: OPAMP_P0, OPAMP_P1, OPAMP_N1, OPAMP_P2 AES Full configuration NA GPIO 37 pins Available pins are shown in 5.8.3 GPIO Pinout Overview LCD Full configuration LCD_SEG[10:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N, LCD_BEXT silabs.com | Building a more connected world. Rev. 2.11 | 21 EFM32TG Data Sheet System Summary 3.2.9 EFM32TG825 The features of the EFM32TG825 is a subset of the feature set described in the EFM32TG Reference Manual. The following table describes device specific implementation of the features. Table 3.9. EFM32TG825 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA I2C0 Full configuration I2C0_SDA, I2C0_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS LEUART0 Full configuration LEU0_TX, LEU0_RX TIMER0 Full configuration TIM0_CC[2:0] TIMER1 Full configuration TIM1_CC[2:0] RTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0] ACMP0 Full configuration ACMP0_CH[4], ACMP0_O ACMP1 Full configuration ACMP1_CH[7:5], ACMP1_O VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:4] DAC0 Full configuration DAC0_OUT[0], DAC0_OUTxALT OPAMP Full configuration Outputs: OPAMP_OUT0, OPAMP_OUT1ALT, OPAMP_OUT2, Inputs: OPAMP_P0, OPAMP_P1, OPAMP_N1, OPAMP_P2 AES Full configuration NA GPIO 37 pins Available pins are shown in 5.9.3 GPIO Pinout Overview LCD Full configuration LCD_SEG[10:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N, LCD_BEXT silabs.com | Building a more connected world. Rev. 2.11 | 22 EFM32TG Data Sheet System Summary 3.2.10 EFM32TG840 The features of the EFM32TG840 is a subset of the feature set described in the EFM32TG Reference Manual. The following table describes device specific implementation of the features. Table 3.10. EFM32TG840 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA I2C0 Full configuration I2C0_SDA, I2C0_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS LEUART0 Full configuration LEU0_TX, LEU0_RX TIMER0 Full configuration TIM0_CC[2:0] TIMER1 Full configuration TIM1_CC[2:0] RTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0] ACMP0 Full configuration ACMP0_CH[7:4], ACMP0_O ACMP1 Full configuration ACMP1_CH[7:4], ACMP1_O VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:0] DAC0 Full configuration DAC0_OUT[0], DAC0_OUTxALT OPAMP Full configuration Outputs: OPAMP_OUT0, OPAMP_OUT0ALT, OPAMP_OUT1ALT, OPAMP_OUT2, Inputs: OPAMP_Px, OPAMP_Nx AES Full configuration NA GPIO 56 pins Available pins are shown in 5.10.3 GPIO Pinout Overview LCD Full configuration LCD_SEG[19:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N, LCD_BEXT silabs.com | Building a more connected world. Rev. 2.11 | 23 EFM32TG Data Sheet System Summary 3.2.11 EFM32TG842 The features of the EFM32TG842 is a subset of the feature set described in the EFM32TG Reference Manual. The following table describes device specific implementation of the features. Table 3.11. EFM32TG842 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA I2C0 Full configuration I2C0_SDA, I2C0_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS LEUART0 Full configuration LEU0_TX, LEU0_RX TIMER0 Full configuration TIM0_CC[2:0] TIMER1 Full configuration TIM1_CC[2:0] RTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0] ACMP0 Full configuration ACMP0_CH[7:4], ACMP0_O ACMP1 Full configuration ACMP1_CH[7:4], ACMP1_O VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:0] DAC0 Full configuration DAC0_OUT[0], DAC0_OUTxALT OPAMP Full configuration Outputs: OPAMP_OUT0, OPAMP_OUT0ALT, OPAMP_OUT1ALT, OPAMP_OUT2, Inputs: OPAMP_Px, OPAMP_Nx AES Full configuration NA GPIO 53 pins Available pins are shown in 5.11.3 GPIO Pinout Overview LCD Full configuration LCD_SEG[17:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N, LCD_BEXT silabs.com | Building a more connected world. Rev. 2.11 | 24 EFM32TG Data Sheet System Summary 3.3 Memory Map The EFM32TG memory map is shown in the following figure, with RAM and Flash sizes for the largest memory configuration. Figure 3.2. System Address Space with Core and Code Space Listing silabs.com | Building a more connected world. Rev. 2.11 | 25 EFM32TG Data Sheet System Summary Figure 3.3. System Address Space with Peripheral Listing silabs.com | Building a more connected world. Rev. 2.11 | 26 EFM32TG Data Sheet Electrical Characteristics 4. Electrical Characteristics 4.1 Test Conditions 4.1.1 Typical Values The typical data are based on TAMB=25°C and VDD=3.0 V, as defined in 4.3 General Operating Conditions, unless otherwise specified. 4.1.2 Minimum and Maximum Values The minimum and maximum values represent the worst conditions of ambient temperature, supply voltage and frequencies, as defined in 4.3 General Operating Conditions, unless otherwise specified. 4.2 Absolute Maximum Ratings The absolute maximum ratings are stress ratings, and functional operation under such conditions are not guaranteed. Stress beyond the limits specified in the following table may affect the device reliability or cause permanent damage to the device. Functional operating conditions are given in 4.3 General Operating Conditions. Table 4.1. Absolute Maximum Ratings Parameter Symbol Storage temperature range TSTG Maximum soldering temperature TS External main supply voltage VDDMAX Voltage on any I/O pin VIOPIN Current per I/O pin (sink) Current per I/O pin (source) Test Condition Min Typ Max Unit -40 — 150 °C — — 260 °C 0 — 3.8 V -0.3 — VDD+0.3 V IIOMAX_SINK — — 100 mA IIOMAX_SOURCE — — -100 mA Latest IPC/JEDEC JSTD-020 Standard 4.3 General Operating Conditions Table 4.2. General Operating Conditions Parameter Symbol Min Typ Max Unit Ambient temperature range TAMB -40 — 85 °C Operating supply voltage VDDOP 1.98 — 3.8 V Internal APB clock frequency fAPB — — 32 MHz Internal AHB clock frequency fAHB — — 32 MHz silabs.com | Building a more connected world. Rev. 2.11 | 27 EFM32TG Data Sheet Electrical Characteristics 4.4 Current Consumption Table 4.3. Current Consumption Parameter EM0 current. No prescaling. Running prime number calculation code from Flash. (Production test condition = 14 MHz) EM1 current (Production test condition = 14 MHz) Symbol IEM0 IEM1 EM2 current IEM2 EM3 current IEM3 EM4 current IEM4 silabs.com | Building a more connected world. Test Condition Min Typ Max Unit 32 MHz HFXO, all peripheral clocks disabled, VDD= 3.0 V — 157 — µA/MHz 28 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V — 150 170 µA/MHz 21 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V — 153 172 µA/MHz 14 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V — 155 175 µA/MHz 11 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V — 157 178 µA/MHz 6.6 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V — 162 183 µA/MHz 1.2 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V — 200 240 µA/MHz 32 MHz HFXO, all peripheral clocks disabled, VDD= 3.0 V — 53 — µA/MHz 28 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V — 51 57 µA/MHz 21 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V — 55 59 µA/MHz 14 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V — 56 61 µA/MHz 11 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V — 58 63 µA/MHz 6.6 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V — 63 68 µA/MHz 1.2 MHz HFRCO. all peripheral clocks disabled, VDD= 3.0 V — 100 122 µA/MHz EM2 current with RTC prescaled to 1 Hz, 32.768 kHz LFRCO, VDD= 3.0 V, TAMB=25ºC — 1.0 1.2 µA EM2 current with RTC prescaled to 1 Hz, 32.768 kHz LFRCO, VDD= 3.0 V, TAMB=85ºC — 2.4 5.0 µA VDD= 3.0 V, TAMB=25ºC — 0.59 1.0 µA VDD= 3.0 V, TAMB=85ºC — 2.0 4.5 µA VDD= 3.0 V, TAMB=25ºC — 0.02 0.055 µA VDD= 3.0 V, TAMB=85ºC — 0.25 0.70 µA Rev. 2.11 | 28 EFM32TG Data Sheet Electrical Characteristics 4.4.1 EM2 Current Consumption Figure 4.1. EM2 Current Consumption, RTC prescaled to 1 kHz, 32.768 kHz LFRCO 4.4.2 EM3 Current Consumption Figure 4.2. EM3 Current Consumption silabs.com | Building a more connected world. Rev. 2.11 | 29 EFM32TG Data Sheet Electrical Characteristics 4.4.3 EM4 Current Consumption Figure 4.3. EM4 Current Consumption 4.5 Transition between Energy Modes The transition times are measured from the trigger to the first clock edge in the CPU. Table 4.4. Energy Modes Transitions Parameter Symbol Min Typ Max Unit Transition time from EM1 to EM0 tEM10 — 0 — HFCORECLK cycles Transition time from EM2 to EM0 tEM20 — 2 — µs Transition time from EM3 to EM0 tEM30 — 2 — µs Transition time from EM4 to EM0 tEM40 — 163 — µs silabs.com | Building a more connected world. Rev. 2.11 | 30 EFM32TG Data Sheet Electrical Characteristics 4.6 Power Management The EFM32TG requires the AVDD_x, VDD_DREG and IOVDD_x pins to be connected together (with optional filter) at the PCB level. For practical schematic recommendations, please see the application note, AN0002 EFM32 Hardware Design Considerations. Table 4.5. Power Management Parameter Symbol BOD threshold on falling external supply voltage Test Condition Min Typ Max Unit VBODextthr- 1.74 — 1.96 V BOD threshold on rising external supply voltage VBODextthr+ — 1.85 1.98 V Power-on Reset (POR) threshold on rising external supply voltage VPORthr+ — — 1.98 V Delay from reset is released un- tRESET til program execution starts Applies to Power-on Reset, Brownout Reset and pin reset. — 163 — µs Voltage regulator decoupling capacitor. X5R capacitor recommended. Apply between DECOUPLE pin and GROUND — 1 — µF Min Typ Max Unit 20000 — — cycles — — 21 cycles TAMB