EFM8 Busy Bee Family
EFM8BB1 Data Sheet
The EFM8BB1, part of the Busy Bee family of MCUs, is a multipurpose line of 8-bit microcontrollers with a comprehensive feature
set in small packages.
KEY FEATURES
These devices offer high-value by integrating advanced analog and communication peripherals into small packages, making them ideal for space-constrained applications.
With an efficient 8051 core, enhanced pulse-width modulation, and precision analog, the
EFM8BB1 family is also optimal for embedded applications.
• Up to 18 multifunction, 5 V tolerant I/O
pins
• One 12-bit Analog to Digital converter
(ADC)
• Two low-current analog comparators
EFM8BB1 applications include the following:
• Integrated temperature sensor
• Medical equipment
• Lighting systems
• I/O port expander
• Motor control
• Consumer electronics
• Sensor controllers
• Pipelined 8-bit C8051 core with 25 MHz
maximum operating frequency
• 3-channel enhanced PWM / PCA
• Four 16-bit timers
• UART, SPI and SMBus/I2C
• Priority crossbar for flexible pin mapping
Core / Memory
Clock Management
CIP-51 8051 Core
(25 MHz)
Flash Program
Memory
RAM Memory
Debug Interface
with C2
(up to 512 bytes)
(up to 8 KB)
External CMOS
Oscillator
Energy Management
High Frequency
RC Oscillator
Internal LDO
Regulator
Low Frequency
RC Oscillator
Power-On Reset
Brown-Out Detector
8-bit SFR bus
Serial Interfaces
UART
SPI
I2C / SMBus
I/O Ports
External
Interrupts
Pin Reset
General Purpose I/O
Timers and Triggers
16-bit
Timers
PCA/PWM
Watchdog Timer
Analog Interfaces
ADC
Analog
Comparators
Security
16-bit CRC
Internal Voltage Reference
Lowest power mode with peripheral operational:
Normal
Idle
Shutdown
silabs.com | Building a more connected world.
Rev. 1.6
EFM8BB1 Data Sheet
Feature List
1. Feature List
The EFM8BB1 highlighted features are listed below.
• Core:
• Pipelined CIP-51 Core
• Fully compatible with standard 8051 instruction set
• 70% of instructions execute in 1-2 clock cycles
• 25 MHz maximum operating frequency
• Memory:
• Up to 8 kB flash memory, in-system re-programmable
from firmware.
• Up to 512 bytes RAM (including 256 bytes standard 8051
RAM and 256 bytes on-chip XRAM)
• Power:
• Internal LDO regulator for CPU core voltage
• Power-on reset circuit and brownout detectors
• I/O: Up to 18 total multifunction I/O pins:
• All pins 5 V tolerant under bias
• Flexible peripheral crossbar for peripheral routing
• 5 mA source, 12.5 mA sink allows direct drive of LEDs
• Clock Sources:
• Internal 24.5 MHz oscillator with ±2% accuracy
• Internal 80 kHz low-frequency oscillator
• External CMOS clock option
• Timers/Counters and PWM:
• 3-channel programmable counter array (PCA) supporting
PWM, capture/compare, and frequency output modes
• 4 x 16-bit general-purpose timers
• Independent watchdog timer, clocked from the low frequency oscillator
• Communications and Digital Peripherals:
• UART
• SPI™ Master / Slave
• SMBus™/I2C™ Master / Slave
• 16-bit CRC unit, supporting automatic CRC of flash at 256byte boundaries
• Analog:
• 12-Bit Analog-to-Digital Converter (ADC)
• 2 x Low-current analog comparators with adjustable reference
• On-Chip, Non-Intrusive Debugging
• Full memory and register inspection
• Four hardware breakpoints, single-stepping
• Pre-loaded UART bootloader
• Temperature range -40 to 85 ºC or -40 to 125 ºC
• Single power supply 2.2 to 3.6 V
• QSOP24, SOIC16, and QFN20 packages
With on-chip power-on reset, voltage supply monitor, watchdog timer, and clock oscillator, the EFM8BB1 devices are truly standalone
system-on-a-chip solutions. The flash memory is reprogrammable in-circuit, providing non-volatile data storage and allowing field upgrades of the firmware. The on-chip debugging interface (C2) allows non-intrusive (uses no on-chip resources), full speed, in-circuit
debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory
and registers, setting breakpoints, single stepping, and run and halt commands. All analog and digital peripherals are fully functional
while debugging. Each device is specified for 2.2 to 3.6 V operation and is AEC-Q100 qualified. Both the G-grade and I-grade devices
are available in 20-pin QFN, 16-pin SOIC or 24-pin QSOP packages, and A-grade devices are available in the 20-pin QFN package. All
package options are lead-free and RoHS compliant.
silabs.com | Building a more connected world.
Rev. 1.6 | 2
EFM8BB1 Data Sheet
Ordering Information
2. Ordering Information
EFM8 BB1 0 F 8 G – A – QSOP24 R
Tape and Reel (Optional)
Package Type
Revision
Temperature Grade G (-40 to +85), I (-40 to +125), A (-40 to +125, Automotive Grade)
Flash Memory Size – 8 KB
Memory Type (Flash)
Family Feature Set
Busy Bee 1 Family
Silicon Labs EFM8 Product Line
Figure 2.1. EFM8BB1 Part Numbering
All EFM8BB1 family members have the following features:
• CIP-51 Core running up to 25 MHz
• Two Internal Oscillators (24.5 MHz and 80 kHz)
• SMBus / I2C
• SPI
• UART
• 3-Channel Programmable Counter Array (PWM, Clock Generation, Capture/Compare)
• 4 16-bit Timers
• 2 Analog Comparators
• 12-bit Analog-to-Digital Converter with integrated multiplexer, voltage reference, and temperature sensor
• 16-bit CRC Unit
• AEC-Q100 qualified
• Pre-loaded UART bootloader
In addition to these features, each part number in the EFM8BB1 family has a set of features that vary across the product line. The
product selection guide shows the features available on each family member.
Flash Memory (kB)
RAM (Bytes)
Digital Port I/Os (Total)
ADC0 Channels
Comparator 0 Inputs
Comparator 1 Inputs
Pb-free
Temperature Range
Package
EFM8BB10F8G-A-QSOP24
8
512
18
16
8
8
Yes
-40 to +85 C
QSOP24
EFM8BB10F8G-A-QFN20
8
512
16
15
8
7
Yes
-40 to +85 C
QFN20
EFM8BB10F8G-A-SOIC16
8
512
13
12
6
6
Yes
-40 to +85 C
SOIC16
EFM8BB10F4G-A-QFN20
4
512
16
15
8
7
Yes
-40 to +85 C
QFN20
EFM8BB10F2G-A-QFN20
2
256
16
15
8
7
Yes
-40 to +85 C
QFN20
silabs.com | Building a more connected world.
(RoHS Compliant)
Ordering Part Number
Table 2.1. Product Selection Guide
Rev. 1.6 | 3
EFM8BB1 Data Sheet
Digital Port I/Os (Total)
ADC0 Channels
Comparator 0 Inputs
Comparator 1 Inputs
Pb-free
512
18
16
8
8
Yes
-40 to +125 C QSOP24
EFM8BB10F8I-A-QFN20
8
512
16
15
8
7
Yes
-40 to +125 C QFN20
EFM8BB10F8I-A-SOIC16
8
512
13
12
6
6
Yes
-40 to +125 C SOIC16
EFM8BB10F4I-A-QFN20
4
512
16
15
8
7
Yes
-40 to +125 C QFN20
EFM8BB10F2I-A-QFN20
2
256
16
15
8
7
Yes
-40 to +125 C QFN20
EFM8BB10F8A-A-QFN20
8
512
16
15
8
7
Yes
-40 to +125 C QFN20
EFM8BB10F4A-A-QFN20
4
512
16
15
8
7
Yes
-40 to +125 C QFN20
EFM8BB10F2A-A-QFN20
2
256
16
15
8
7
Yes
-40 to +125 C QFN20
Package
RAM (Bytes)
8
Temperature Range
Flash Memory (kB)
EFM8BB10F8I-A-QSOP24
(RoHS Compliant)
Ordering Part Number
Ordering Information
The A-grade (i.e. EFM8BB10F8A-A-QFN20) devices receive full automotive quality production status, including AEC-Q100 qualification, registration with International Material Data System (IMDS), and Part Production Approval Process (PPAP) documentation. PPAP
documentation is available at www.silabs.com with a registered and NDA approved user account.
silabs.com | Building a more connected world.
Rev. 1.6 | 4
Table of Contents
1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Introduction.
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. 7
3.2 Power
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. 8
3.3 I/O.
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3.4 Clocking .
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3.5 Counters/Timers and PWM .
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. 9
3.6 Communications and Other Digital Peripherals .
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.10
3.7 Analog .
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3.8 Reset Sources
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.12
3.9 Debugging .
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.12
3.10 Bootloader
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.13
4. Electrical Specifications
. . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1 Electrical Characteristics . . . . . . .
4.1.1 Recommended Operating Conditions .
4.1.2 Power Consumption. . . . . . .
4.1.3 Reset and Supply Monitor . . . . .
4.1.4 Flash Memory . . . . . . . . .
4.1.5 Internal Oscillators . . . . . . .
4.1.6 External Clock Input . . . . . . .
4.1.7 ADC . . . . . . . . . . . .
4.1.8 Voltage Reference . . . . . . .
4.1.9 Temperature Sensor . . . . . .
4.1.10 1.8 V Internal LDO Voltage Regulator
4.1.11 Comparators . . . . . . . . .
4.1.12 Port I/O . . . . . . . . . .
4.1.13 SMBus . . . . . . . . . . .
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.15
.15
.16
.18
.19
.19
.20
.21
.22
.23
.23
.24
.26
.27
4.2 Thermal Conditions .
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.29
4.3 Absolute Maximum Ratings .
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.29
4.4 Typical Performance Curves .
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.30
5. Typical Connection Diagrams
. . . . . . . . . . . . . . . . . . . . . . . . 34
5.1 Power
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.34
5.2 Debug
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.34
5.3 Other Connections .
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.35
6. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1 EFM8BB1x-QSOP24 Pin Definitions .
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.36
6.2 EFM8BB1x-QFN20 Pin Definitions .
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.39
silabs.com | Building a more connected world.
.
Rev. 1.6 | 5
6.3 EFM8BB1x-SOIC16 Pin Definitions
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.42
7. QSOP24 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . 44
7.1 QSOP24 Package Dimensions .
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.44
7.2 QSOP24 PCB Land Pattern .
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.46
7.3 QSOP24 Package Marking .
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.47
8. QFN20 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . .
48
8.1 QFN20 Package Dimensions
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.48
8.2 QFN20 PCB Land Pattern
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.50
8.3 QFN20 Package Marking .
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.51
9. SOIC16 Package Specifications
. . . . . . . . . . . . . . . . . . . . . . . 52
9.1 SOIC16 Package Dimensions
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.52
9.2 SOIC16 PCB Land Pattern .
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.54
9.3 SOIC16 Package Marking .
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.55
10. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
56
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10.1 Revision 1.6 .
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.56
10.2 Revision 1.5 .
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.56
10.3 Revision 1.4 .
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.56
10.4 Revision 1.3 .
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.56
10.5 Revision 1.2 .
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.56
10.6 Revision 1.1 .
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.56
silabs.com | Building a more connected world.
Rev. 1.6 | 6
EFM8BB1 Data Sheet
System Overview
3. System Overview
3.1 Introduction
Power On
Reset
CIP-51 8051 Controller
Core
Reset
C2CK/RSTb
Port I/O Configuration
Digital Peripherals
8/4/2 KB ISP Flash
Program Memory
Debug /
Programming
Hardware
UART
Timers 0,
1, 2, 3
256 Byte SRAM
I2C /
SMBus
256 Byte XRAM
Power Nets
VDD
Internal 1.8 V
LDO
GND
SPI
Port 1
Drivers
P1.n
Port 2
Driver
P2.n
CRC
Independent
Watchdog Timer
SYSCLK
System Clock
Configuration
Crossbar Control
SFR
Bus
Analog Peripherals
Internal
Reference
VDD
VREF
24.5 MHz
2%
Oscillator
CMOS
Oscillator
Input
VDD
12/10 bit
ADC
AMUX
Low-Freq.
Oscillator
EXTCLK
P0.n
Priority
Crossbar
Decoder
3-ch PCA
C2D
Port 0
Drivers
Temp
Sensor
+
-+
2 Comparators
Figure 3.1. Detailed EFM8BB1 Block Diagram
This section describes the EFM8BB1 family at a high level. For more information on each module including register definitions, see the
EFM8BB1 Reference Manual.
silabs.com | Building a more connected world.
Rev. 1.6 | 7
EFM8BB1 Data Sheet
System Overview
3.2 Power
All internal circuitry draws power from the VDD supply pin. External I/O pins are powered from the VIO supply voltage (or VDD on devices without a separate VIO connection), while most of the internal circuitry is supplied by an on-chip LDO regulator. Control over the
device power can be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral can be disabled when
not in use and placed in low power mode. Digital peripherals, such as timers and serial buses, have their clocks gated off and draw little
power when they are not in use.
Table 3.1. Power Modes
Power Mode
Details
Mode Entry
Wake-Up Sources
Normal
Core and all peripherals clocked and fully operational
—
—
Set IDLE bit in PCON0
Any interrupt
Idle
• Core halted
• All peripherals clocked and fully operational
• Code resumes execution on wake event
Stop
• All internal power nets shut down
• Pins retain state
• Exit on any reset source
1. Clear STOPCF bit in
REG0CN
2. Set STOP bit in
PCON0
Shutdown
• All internal power nets shut down
• Pins retain state
• Exit on pin or power-on reset
1. Set STOPCF bit in
REG0CN
2. Set STOP bit in
PCON0
Any reset source
• RSTb pin reset
• Power-on reset
3.3 I/O
Digital and analog resources are externally available on the device’s multi-purpose I/O pins. Port pins P0.0-P1.7 can be defined as general-purpose I/O (GPIO), assigned to one of the internal digital resources through the crossbar or dedicated channels, or assigned to an
analog function. Port pins P2.0 and P2.1 can be used as GPIO. Additionally, the C2 Interface Data signal (C2D) is shared with P2.0.
•
•
•
•
•
Up to 18 multi-functions I/O pins, supporting digital and analog functions.
Flexible priority crossbar decoder for digital peripheral assignment.
Two drive strength settings for each port.
Two direct-pin interrupt sources with dedicated interrupt vectors (INT0 and INT1).
Up to 16 direct-pin interrupt sources with shared interrupt vector (Port Match).
3.4 Clocking
The CPU core and peripheral subsystem may be clocked by both internal and external oscillator resources. By default, the system
clock comes up running from the 24.5 MHz oscillator divided by 8.
•
•
•
•
•
Provides clock to core and peripherals.
24.5 MHz internal oscillator (HFOSC0), accurate to ±2% over supply and temperature corners.
80 kHz low-frequency oscillator (LFOSC0).
External CMOS clock input (EXTCLK).
Clock divider with eight settings for flexible clock scaling: Divide the selected clock source by 1, 2, 4, 8, 16, 32, 64, or 128.
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Rev. 1.6 | 8
EFM8BB1 Data Sheet
System Overview
3.5 Counters/Timers and PWM
Programmable Counter Array (PCA0)
The programmable counter array (PCA) provides multiple channels of enhanced timer and PWM functionality while requiring less CPU
intervention than standard counter/timers. The PCA consists of a dedicated 16-bit counter/timer and one 16-bit capture/compare module for each channel. The counter/timer is driven by a programmable timebase that has flexible external and internal clocking options.
Each capture/compare module may be configured to operate independently in one of five modes: Edge-Triggered Capture, Software
Timer, High-Speed Output, Frequency Output, or Pulse-Width Modulated (PWM) Output. Each capture/compare module has its own
associated I/O line (CEXn) which is routed through the crossbar to port I/O when enabled.
•
•
•
•
•
•
•
•
•
•
16-bit time base
Programmable clock divisor and clock source selection
Up to three independently-configurable channels
8, 9, 10, 11 and 16-bit PWM modes (center or edge-aligned operation)
Output polarity control
Frequency output mode
Capture on rising, falling or any edge
Compare function for arbitrary waveform generation
Software timer (internal compare) mode
Can accept hardware “kill” signal from comparator 0
Timers (Timer 0, Timer 1, Timer 2, and Timer 3)
Several counter/timers are included in the device: two are 16-bit counter/timers compatible with those found in the standard 8051, and
the rest are 16-bit auto-reload timers for timing peripherals or for general purpose use. These timers can be used to measure time intervals, count external events and generate periodic interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary
modes of operation. The other timers offer both 16-bit and split 8-bit timer functionality with auto-reload and capture capabilities.
Timer 0 and Timer 1 include the following features:
• Standard 8051 timers, supporting backwards-compatibility with firmware and hardware.
• Clock sources include SYSCLK, SYSCLK divided by 12, 4, or 48, the External Clock divided by 8, or an external pin.
• 8-bit auto-reload counter/timer mode
• 13-bit counter/timer mode
• 16-bit counter/timer mode
• Dual 8-bit counter/timer mode (Timer 0)
Timer 2 and Timer 3 are 16-bit timers including the following features:
• Clock sources include SYSCLK, SYSCLK divided by 12, or the External Clock divided by 8.
• 16-bit auto-reload timer mode
• Dual 8-bit auto-reload timer mode
• External pin capture (Timer 2)
• LFOSC0 capture (Timer 3)
Watchdog Timer (WDT0)
The device includes a programmable watchdog timer (WDT) running off the low-frequency oscillator. A WDT overflow forces the MCU
into the reset state. To prevent the reset, the WDT must be restarted by application software before overflow. If the system experiences
a software or hardware malfunction preventing the software from restarting the WDT, the WDT overflows and causes a reset. Following
a reset, the WDT is automatically enabled and running with the default maximum time interval. If needed, the WDT can be disabled by
system software or locked on to prevent accidental disabling. Once locked, the WDT cannot be disabled until the next system reset.
The state of the RST pin is unaffected by this reset.
The Watchdog Timer has the following features:
• Programmable timeout interval
• Runs from the low-frequency oscillator
• Lock-out feature to prevent any modification until a system reset
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Rev. 1.6 | 9
EFM8BB1 Data Sheet
System Overview
3.6 Communications and Other Digital Peripherals
Universal Asynchronous Receiver/Transmitter (UART0)
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support
allows a wide range of clock sources to generate standard baud rates. Received data buffering allows UART0 to start reception of a
second incoming data byte before software has finished reading the previous data byte.
The UART module provides the following features:
• Asynchronous transmissions and receptions.
• Baud rates up to SYSCLK/2 (transmit) or SYSCLK/8 (receive).
• 8- or 9-bit data.
• Automatic start and stop generation.
• Single-byte FIFO on transmit and receive.
Serial Peripheral Interface (SPI0)
The serial peripheral interface (SPI) module provides access to a flexible, full-duplex synchronous serial bus. The SPI can operate as a
master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single SPI bus. The slave-select
(NSS) signal can be configured as an input to select the SPI in slave mode, or to disable master mode operation in a multi-master
environment, avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can also be
configured as a firmware-controlled chip-select output in master mode, or disabled to reduce the number of pins required. Additional
general purpose port I/O pins can be used to select multiple slave devices in master mode.
The SPI module includes the following features:
• Supports 3- or 4-wire operation in master or slave modes.
• Supports external clock frequencies up to SYSCLK / 2 in master mode and SYSCLK / 10 in slave mode.
• Support for four clock phase and polarity options.
• 8-bit dedicated clock clock rate generator.
• Support for multiple masters on the same data lines.
System Management Bus / I2C (SMB0)
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specification, version 1.1, and compatible with the I2C serial bus.
The SMBus module includes the following features:
• Standard (up to 100 kbps) and Fast (400 kbps) transfer speeds.
• Support for master, slave, and multi-master modes.
• Hardware synchronization and arbitration for multi-master mode.
• Clock low extending (clock stretching) to interface with faster masters.
• Hardware support for 7-bit slave and general call address recognition.
• Firmware support for 10-bit slave address decoding.
• Ability to inhibit all slave states.
• Programmable data setup/hold times.
16-bit CRC (CRC0)
The cyclic redundancy check (CRC) module performs a CRC using a 16-bit polynomial. CRC0 accepts a stream of 8-bit data and posts
the 16-bit result to an internal register. In addition to using the CRC block for data manipulation, hardware can automatically CRC the
flash contents of the device.
The CRC module is designed to provide hardware calculations for flash memory verification and communications protocols. The CRC
module supports the standard CCITT-16 16-bit polynomial (0x1021), and includes the following features:
• Support for CCITT-16 polynomial
• Byte-level bit reversal
• Automatic CRC of flash contents on one or more 256-byte blocks
• Initial seed selection of 0x0000 or 0xFFFF
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Rev. 1.6 | 10
EFM8BB1 Data Sheet
System Overview
3.7 Analog
12-Bit Analog-to-Digital Converter (ADC0)
The ADC is a successive-approximation-register (SAR) ADC with 12-, 10-, and 8-bit modes, integrated track-and hold and a programmable window detector. The ADC is fully configurable under software control via several registers. The ADC may be configured to
measure different signals using the analog multiplexer. The voltage reference for the ADC is selectable between internal and external
reference sources.
•
•
•
•
•
•
•
•
•
•
•
Up to 16 external inputs.
Single-ended 12-bit and 10-bit modes.
Supports an output update rate of 200 ksps samples per second in 12-bit mode or 800 ksps samples per second in 10-bit mode.
Operation in low power modes at lower conversion speeds.
Asynchronous hardware conversion trigger, selectable between software, external I/O and internal timer sources.
Output data window comparator allows automatic range checking.
Support for burst mode, which produces one set of accumulated data per conversion-start trigger with programmable power-on settling and tracking time.
Conversion complete and window compare interrupts supported.
Flexible output data formatting.
Includes an internal fast-settling reference with two levels (1.65 V and 2.4 V) and support for external reference and signal ground.
Integrated temperature sensor.
Low Current Comparators (CMP0, CMP1)
Analog comparators are used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is higher.
External input connections to device I/O pins and internal connections are available through separate multiplexers on the positive and
negative inputs. Hysteresis, response time, and current consumption may be programmed to suit the specific needs of the application.
The comparator module includes the following features:
• Up to 8 external positive inputs.
• Up to 8 external negative inputs.
• Additional input options:
• Internal connection to LDO output.
• Direct connection to GND.
• Synchronous and asynchronous outputs can be routed to pins via crossbar.
• Programmable hysteresis between 0 and ±20 mV
• Programmable response time.
• Interrupts generated on rising, falling, or both edges.
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Rev. 1.6 | 11
EFM8BB1 Data Sheet
System Overview
3.8 Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur:
• The core halts program execution.
• Module registers are initialized to their defined reset values unless the bits reset only with a power-on reset.
• External port pins are forced to a known state.
• Interrupts and timers are disabled.
All registers are reset to the predefined values noted in the register descriptions unless the bits only reset with a power-on reset. The
contents of RAM are unaffected during a reset; any previously stored data is preserved as long as power is not lost. The Port I/O latches are reset to 1 in open-drain mode. Weak pullups are enabled during and after the reset. For Supply Monitor and power-on resets,
the RSTb pin is driven low until the device exits the reset state. On exit from the reset state, the program counter (PC) is reset, and the
system clock defaults to an internal oscillator. The Watchdog Timer is enabled, and program execution begins at location 0x0000.
Reset sources on the device include the following:
• Power-on reset
• External reset pin
• Comparator reset
• Software-triggered reset
• Supply monitor reset (monitors VDD supply)
• Watchdog timer reset
• Missing clock detector reset
• Flash error reset
3.9 Debugging
The EFM8BB1 devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow flash programming and in-system debugging with the production part installed in the end application. The C2 interface uses a clock signal (C2CK) and a bi-directional C2 data
signal (C2D) to transfer information between the device and a host system. See the C2 Interface Specification for details on the C2
protocol.
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Rev. 1.6 | 12
EFM8BB1 Data Sheet
System Overview
3.10 Bootloader
All devices come pre-programmed with a UART bootloader. This bootloader resides in the code security page, which is the last last
page of code flash; it can be erased if it is not needed.
The byte before the Lock Byte is the Bootloader Signature Byte. Setting this byte to a value of 0xA5 indicates the presence of the bootloader in the system. Any other value in this location indicates that the bootloader is not present in flash.
When a bootloader is present, the device will jump to the bootloader vector after any reset, allowing the bootloader to run. The bootloader then determines if the device should stay in bootload mode or jump to the reset vector located at 0x0000. When the bootloader
is not present, the device will jump to the reset vector of 0x0000 after any reset.
More information about the bootloader protocol and usage can be found in AN945: EFM8 Factory Bootloader User Guide. Application
notes can be found on the Silicon Labs website (www.silabs.com/8bit-appnotes) or within Simplicity Studio by using the [Application
Notes] tile.
0xFFFF
Reserved
0x1FFF
Lock Byte
0x1FFE
Bootloader Signature Byte
0x1FFD
Security Page
512 Bytes
0x1E00
Bootloader
0x2000
Bootloader Vector
8 KB Flash
(16 x 512 Byte pages)
0x0000
Reset Vector
Figure 3.2. Flash Memory Map with Bootloader—8 KB Devices
Table 3.2. Summary of Pins for Bootloader Communication
Bootloader
Pins for Bootload Communication
UART
TX – P0.4
RX – P0.5
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Rev. 1.6 | 13
EFM8BB1 Data Sheet
System Overview
Table 3.3. Summary of Pins for Bootload Mode Entry
Device Package
Pin for Bootload Mode Entry
QSOP24
P2.0 / C2D
QFN20
P2.0 / C2D
SOIC16
P2.0 / C2D
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Rev. 1.6 | 14
EFM8BB1 Data Sheet
Electrical Specifications
4. Electrical Specifications
4.1 Electrical Characteristics
All electrical parameters in all tables are specified under the conditions listed in Table 4.1 Recommended Operating Conditions on page
15, unless stated otherwise.
4.1.1 Recommended Operating Conditions
Table 4.1. Recommended Operating Conditions
Parameter
Symbol
Operating Supply Voltage on VDD
VDD
System Clock Frequency
fSYSCLK
Operating Ambient Temperature
TA
Test Condition
Min
Typ
Max
Unit
2.2
—
3.6
V
0
—
25
MHz
G-grade devices
–40
—
85
°C
I-grade or A-grade devices
-40
—
125
°C
Note:
1. All voltages with respect to GND
2. GPIO levels are undefined whenever VDD is less than 1 V.
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Rev. 1.6 | 15
EFM8BB1 Data Sheet
Electrical Specifications
4.1.2 Power Consumption
Table 4.2. Power Consumption
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
FSYSCLK = 24.5 MHz2
—
4.45
4.85
mA
FSYSCLK = 1.53 MHz2
—
915
1150
μA
FSYSCLK = 80 kHz3 , TA = 25 °C
—
250
290
μA
FSYSCLK = 80 kHz3
—
250
380
μA
FSYSCLK = 24.5 MHz2
—
2.05
2.3
mA
FSYSCLK = 1.53 MHz2
—
550
700
μA
FSYSCLK = 80 kHz3 , TA = 25 °C
—
125
130
μA
FSYSCLK = 80 kHz3
—
125
200
μA
TA = 25 °C
—
105
120
μA
TA = -40 to +85 °C
—
105
170
μA
—
0.2
—
μA
FSYSCLK = 24.5 MHz2
—
4.45
5.25
mA
FSYSCLK = 1.53 MHz2
—
915
1600
μA
FSYSCLK = 80 kHz3 , TA = 25 °C
—
250
290
μA
FSYSCLK = 80 kHz3
—
250
725
μA
FSYSCLK = 24.5 MHz2
—
2.05
2.6
mA
FSYSCLK = 1.53 MHz2
—
550
1000
μA
FSYSCLK = 80 kHz3 , TA = 25 °C
—
125
130
μA
FSYSCLK = 80 kHz3
—
125
550
μA
TA = 25 °C
—
105
120
μA
TA = -40 to +125 °C
—
105
270
μA
—
0.2
—
μA
—
155
—
µA
—
3.5
—
µA
Digital Core Supply Current (G-grade devices, -40 °C to +85 °C)
Normal Mode—Full speed with
code executing from flash
Idle Mode—Core halted with peripherals running
IDD
IDD
Stop Mode—Core halted and all
clocks stopped,Internal LDO On,
Supply monitor off.
IDD
Shutdown Mode—Core halted and
all clocks stopped,Internal LDO
Off, Supply monitor off.
IDD
Digital Core Supply Current (I-grade or A-grade devices, -40 °C to +125 °C)
Normal Mode—Full speed with
code executing from flash
Idle Mode—Core halted with peripherals running
IDD
IDD
Stop Mode—Core halted and all
clocks stopped,Internal LDO On,
Supply monitor off.
IDD
Shutdown Mode—Core halted and
all clocks stopped,Internal LDO
Off, Supply monitor off.
IDD
Analog Peripheral Supply Currents (-40 °C to +125 °C)
High-Frequency Oscillator
IHFOSC
Operating at 24.5 MHz,
TA = 25 °C
Low-Frequency Oscillator
ILFOSC
Operating at 80 kHz,
TA = 25 °C
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Rev. 1.6 | 16
EFM8BB1 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
ADC0 Always-on4
IADC
800 ksps, 10-bit conversions or
—
845
1200
µA
—
425
580
µA
200 ksps, VDD = 3.0 V
—
370
—
µA
100 ksps, VDD = 3.0 V
—
185
—
µA
10 ksps, VDD = 3.0 V
—
19
—
µA
200 ksps, VDD = 3.0 V
—
490
—
µA
100 ksps, VDD = 3.0 V
—
245
—
µA
10 ksps, VDD = 3.0 V
—
23
—
µA
100 ksps, VDD = 3.0 V
—
530
—
µA
50 ksps, VDD = 3.0 V
—
265
—
µA
10 ksps, VDD = 3.0 V
—
53
—
µA
100 ksps, VDD = 3.0 V,
—
950
—
µA
—
420
—
µA
—
85
—
µA
Normal Power Mode
—
680
790
µA
Low Power Mode
—
160
210
µA
—
75
120
µA
CPMD = 11
—
0.5
—
µA
CPMD = 10
—
3
—
µA
CPMD = 01
—
10
—
µA
CPMD = 00
—
25
—
µA
—
15
20
µA
200 ksps, 12-bit conversions
Normal bias settings
VDD = 3.0 V
250 ksps, 10-bit conversions or
62.5 ksps 12-bit conversions
Low power bias settings
VDD = 3.0 V
ADC0 Burst Mode, 10-bit single
conversions, external reference
ADC0 Burst Mode, 10-bit single
conversions, internal reference,
Low power bias settings
ADC0 Burst Mode, 12-bit single
conversions, external reference
ADC0 Burst Mode, 12-bit single
conversions, internal reference
IADC
IADC
IADC
IADC
Normal bias
50 ksps, VDD = 3.0 V,
Low power bias
10 ksps, VDD = 3.0 V,
Low power bias
Internal ADC0 Reference, Alwayson5
IVREFFS
Temperature Sensor
ITSENSE
Comparator 0 (CMP0),
ICMP
Comparator 1 (CMP1)
Voltage Supply Monitor (VMON0)
IVMON
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Rev. 1.6 | 17
EFM8BB1 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Note:
1. Currents are additive. For example, where IDD is specified and the mode is not mutually exclusive, enabling the functions increases supply current by the specified amount.
2. Includes supply current from internal regulator, supply monitor, and High Frequency Oscillator.
3. Includes supply current from internal regulator, supply monitor, and Low Frequency Oscillator.
4. ADC0 always-on power excludes internal reference supply current.
5. The internal reference is enabled as-needed when operating the ADC in burst mode to save power.
4.1.3 Reset and Supply Monitor
Table 4.3. Reset and Supply Monitor
Parameter
Symbol
VDD Supply Monitor Threshold
VVDDM
Power-On Reset (POR) Threshold
VPOR
Test Condition
Min
Typ
Max
Unit
1.851
1.95
2.1
V
Rising Voltage on VDD
—
1.4
—
V
Falling Voltage on VDD
0.75
—
1.36
V
VDD Ramp Time
tRMP
Time to VDD ≥ 2.2 V
10
—
—
µs
Reset Delay from POR
tPOR
Relative to VDD ≥ VPOR
3
10
31
ms
Time between release of reset
source and code execution
—
39
—
µs
15
—
—
µs
—
0.625
1.2
ms
Reset Delay from non-POR source tRST
RST Low Time to Generate Reset
tRSTL
Missing Clock Detector Response
Time (final rising edge to reset)
tMCD
Missing Clock Detector Trigger
Frequency
FMCD
—
7.5
13.5
kHz
VDD Supply Monitor Turn-On Time
tMON
—
2
—
µs
FSYSCLK > 1 MHz
Note:
1. MCU core, digital logic, flash memory, and RAM operation is guaranteed down to the minimum VDD Supply Monitor Threshold.
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Rev. 1.6 | 18
EFM8BB1 Data Sheet
Electrical Specifications
4.1.4 Flash Memory
Table 4.4. Flash Memory
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Write Time1 ,2
tWRITE
One Byte,
19
20
21
µs
5.2
5.35
5.5
ms
VDD Voltage During Programming3 VPROG
2.2
—
3.6
V
Endurance (Write/Erase Cycles)
NWE
20k
100k
—
Cycles
CRC Calculation Time
tCRC
—
11
—
µs
FSYSCLK = 24.5 MHz
Erase Time1 ,2
tERASE
One Page,
FSYSCLK = 24.5 MHz
One 256-Byte Block
SYSCLK = 24.5 MHz
Note:
1. Does not include sequencing time before and after the write/erase operation, which may be multiple SYSCLK cycles.
2. The internal High-Frequency Oscillator has a programmable output frequency using the HFO0CAL register, which is factory programmed to 24.5 MHz. If user firmware adjusts the oscillator speed, it must be between 22 and 25 MHz during any flash write or
erase operation. It is recommended to write the HFO0CAL register back to its reset value when writing or erasing flash.
3. Flash can be safely programmed at any voltage above the supply monitor threshold (VVDDM).
4. Data Retention Information is published in the Quarterly Quality and Reliability Report.
4.1.5 Internal Oscillators
Table 4.5. Internal Oscillators
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
High Frequency Oscillator 0 (24.5 MHz)
Oscillator Frequency
fHFOSC0
Full Temperature and Supply
Range
24
24.5
25
MHz
Power Supply Sensitivity
PSSHFOS
TA = 25 °C
—
0.5
—
%/V
TSHFOSC0 VDD = 3.0 V
—
40
—
ppm/°C
Oscillator Frequency
fLFOSC
75
80
85
kHz
Power Supply Sensitivity
PSSLFOSC TA = 25 °C
—
0.05
—
%/V
Temperature Sensitivity
TSLFOSC
—
65
—
ppm/°C
C0
Temperature Sensitivity
Low Frequency Oscillator (80 kHz)
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Full Temperature and Supply
Range
VDD = 3.0 V
Rev. 1.6 | 19
EFM8BB1 Data Sheet
Electrical Specifications
4.1.6 External Clock Input
Table 4.6. External Clock Input
Parameter
Symbol
External Input CMOS Clock
Test Condition
Min
Typ
Max
Unit
fCMOS
0
—
25
MHz
External Input CMOS Clock High
Time
tCMOSH
18
—
—
ns
External Input CMOS Clock Low
Time
tCMOSL
18
—
—
ns
Frequency (at EXTCLK pin)
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Rev. 1.6 | 20
EFM8BB1 Data Sheet
Electrical Specifications
4.1.7 ADC
Table 4.7. ADC
Parameter
Symbol
Test Condition
Resolution
Nbits
12 Bit Mode
12
Bits
10 Bit Mode
10
Bits
Throughput Rate
fS
(High Speed Mode)
Throughput Rate
fS
(Low Power Mode)
Tracking Time
tTRK
Power-On Time
tPWR
SAR Clock Frequency
fSAR
Min
Typ
Max
Unit
12 Bit Mode
—
—
200
ksps
10 Bit Mode
—
—
800
ksps
12 Bit Mode
—
—
62.5
ksps
10 Bit Mode
—
—
250
ksps
High Speed Mode
230
—
—
ns
Low Power Mode
450
—
—
ns
1.2
—
—
µs
—
—
6.25
MHz
—
—
12.5
MHz
—
—
4
MHz
High Speed Mode,
Reference is 2.4 V internal
High Speed Mode,
Reference is not 2.4 V internal
Low Power Mode
Conversion Time
tCNV
10-Bit Conversion,
1.1
µs
SAR Clock = 12.25 MHz,
System Clock = 24.5 MHz.
Sample/Hold Capacitor
CSAR
Gain = 1
—
5
—
pF
Gain = 0.5
—
2.5
—
pF
Input Pin Capacitance
CIN
—
20
—
pF
Input Mux Impedance
RMUX
—
550
—
Ω
Voltage Reference Range
VREF
1
—
VDD
V
Input Voltage Range*
VIN
Gain = 1
0
—
VREF
V
Gain = 0.5
0
—
2xVREF
V
—
70
—
dB
12 Bit Mode
—
±1
±2.3
LSB
10 Bit Mode
—
±0.2
±0.6
LSB
12 Bit Mode
–1
±0.7
1.9
LSB
10 Bit Mode
—
±0.2
±0.6
LSB
12 Bit Mode, VREF = 1.65 V
–3
0
3
LSB
10 Bit Mode, VREF = 1.65 V
–2
0
2
LSB
—
0.004
—
LSB/°C
Power Supply Rejection Ratio
PSRRADC
DC Performance
Integral Nonlinearity
INL
Differential Nonlinearity (Guaranteed Monotonic)
DNL
Offset Error
EOFF
Offset Temperature Coefficient
TCOFF
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Rev. 1.6 | 21
EFM8BB1 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Slope Error
EM
12 Bit Mode
—
±0.02
±0.1
%
10 Bit Mode
—
±0.06
±0.24
%
Dynamic Performance 10 kHz Sine Wave Input 1dB below full scale, Max throughput, using AGND pin
Signal-to-Noise
Signal-to-Noise Plus Distortion
SNR
SNDR
Total Harmonic Distortion (Up to
5th Harmonic)
THD
Spurious-Free Dynamic Range
SFDR
12 Bit Mode
61
66
—
dB
10 Bit Mode
53
60
—
dB
12 Bit Mode
61
66
—
dB
10 Bit Mode
53
60
—
dB
12 Bit Mode
—
71
—
dB
10 Bit Mode
—
70
—
dB
12 Bit Mode
—
–79
—
dB
10 Bit Mode
—
–74
—
dB
Note:
1. Absolute input pin voltage is limited by the VDD supply.
4.1.8 Voltage Reference
Table 4.8. Voltage Reference
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
VREFFS
1.65 V Setting
1.62
1.65
1.68
V
2.4 V Setting, VDD ≥ 2.6 V
2.35
2.4
2.45
V
Internal Fast Settling Reference
Output Voltage
(Full Temperature and Supply
Range)
Temperature Coefficient
TCREFFS
—
50
—
ppm/°C
Turn-on Time
tREFFS
—
—
1.5
µs
Power Supply Rejection
PSRRREF
—
400
—
ppm/V
—
5
—
µA
FS
External Reference
Input Current
IEXTREF
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Rev. 1.6 | 22
EFM8BB1 Data Sheet
Electrical Specifications
4.1.9 Temperature Sensor
Table 4.9. Temperature Sensor
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Offset
VOFF
TA = 0 °C
—
757
—
mV
Offset Error1
EOFF
TA = 0 °C
—
17
—
mV
Slope
M
—
2.85
—
mV/°C
Slope Error1
EM
—
70
—
µV/°C
Linearity
—
0.5
—
°C
Turn-on Time
—
1.8
—
µs
Min
Typ
Max
Unit
1.74
1.8
1.85
V
Note:
1. Represents one standard deviation from the mean.
4.1.10 1.8 V Internal LDO Voltage Regulator
Table 4.10. 1.8V Internal LDO Voltage Regulator
Parameter
Output Voltage
Symbol
VOUT_1.8V
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Test Condition
Rev. 1.6 | 23
EFM8BB1 Data Sheet
Electrical Specifications
4.1.11 Comparators
Table 4.11. Comparators
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Response Time, CPMD = 00
(Highest Speed)
tRESP0
+100 mV Differential
—
100
—
ns
–100 mV Differential
—
150
—
ns
Response Time, CPMD = 11 (Low- tRESP3
est Power)
+100 mV Differential
—
1.5
—
µs
–100 mV Differential
—
3.5
—
µs
Positive Hysterisis
CPHYP = 00
—
0.4
—
mV
CPHYP = 01
—
8
—
mV
CPHYP = 10
—
16
—
mV
CPHYP = 11
—
32
—
mV
CPHYN = 00
—
-0.4
—
mV
CPHYN = 01
—
–8
—
mV
CPHYN = 10
—
–16
—
mV
CPHYN = 11
—
–32
—
mV
CPHYP = 00
—
0.5
—
mV
CPHYP = 01
—
6
—
mV
CPHYP = 10
—
12
—
mV
CPHYP = 11
—
24
—
mV
CPHYN = 00
—
-0.5
—
mV
CPHYN = 01
—
–6
—
mV
CPHYN = 10
—
–12
—
mV
CPHYN = 11
—
–24
—
mV
CPHYP = 00
—
0.7
—
mV
CPHYP = 01
—
4.5
—
mV
CPHYP = 10
—
9
—
mV
CPHYP = 11
—
18
—
mV
CPHYN = 00
—
-0.6
—
mV
CPHYN = 01
—
–4.5
—
mV
CPHYN = 10
—
–9
—
mV
CPHYN = 11
—
–18
—
mV
CPHYP = 00
—
1.5
—
mV
CPHYP = 01
—
4
—
mV
CPHYP = 10
—
8
—
mV
CPHYP = 11
—
16
—
mV
HYSCP+
Mode 0 (CPMD = 00)
Negative Hysterisis
HYSCP-
Mode 0 (CPMD = 00)
Positive Hysterisis
HYSCP+
Mode 1 (CPMD = 01)
Negative Hysterisis
HYSCP-
Mode 1 (CPMD = 01)
Positive Hysterisis
HYSCP+
Mode 2 (CPMD = 10)
Negative Hysterisis
HYSCP-
Mode 2 (CPMD = 10)
Positive Hysteresis
HYSCP+
Mode 3 (CPMD = 11)
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EFM8BB1 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Negative Hysteresis
HYSCP-
Mode 3 (CPMD = 11)
Min
Typ
Max
Unit
CPHYN = 00
—
-1.5
—
mV
CPHYN = 01
—
–4
—
mV
CPHYN = 10
—
–8
—
mV
CPHYN = 11
—
–16
—
mV
Input Range (CP+ or CP–)
VIN
-0.25
—
VDD+0.25
V
Input Pin Capacitance
CCP
—
7.5
—
pF
Common-Mode Rejection Ratio
CMRRCP
—
70
—
dB
Power Supply Rejection Ratio
PSRRCP
—
72
—
dB
Input Offset Voltage
VOFF
-10
0
10
mV
Input Offset Tempco
TCOFF
—
3.5
—
µV/°C
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Rev. 1.6 | 25
EFM8BB1 Data Sheet
Electrical Specifications
4.1.12 Port I/O
Table 4.12. Port I/O
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output High Voltage (Low Drive)1
VOH
IOH = –1 mA
VDD – 0.7
—
—
V
Output High Voltage (High Drive)1
VOH
IOH = –3 mA
VDD – 0.7
—
—
V
Output Low Voltage (Low Drive)1
VOL
IOL = 1.4 mA
—
—
0.6
V
Output Low Voltage (High Drive)1
VOL
IOL = 8.5 mA
—
—
0.6
V
Output Low Voltage (High Drive)1
VOL
IOL = 10 mA
—
0.25
0.33
V
—
0.23
0.31
V
-10 °C ≤ TA ≤ 60 °C
VDD = 3.0 V
Guaranteed by characterization
Output Low Voltage (High Drive)1
VOL
IOL = 10 mA
-10 °C ≤ TA ≤ 60 °C
VDD = 3.6 V
Guaranteed by characterization
Input High Voltage
VIH
VDD – 0.6
—
—
V
Input Low Voltage
VIL
—
—
0.6
V
Pin Capacitance
CIO
—
7
—
pF
Weak Pull-Up Current
IPU
VDD = 3.6
–30
–20
–10
µA
Input Leakage (Pullups off or Analog)
ILK
GND < VIN < VDD
–1.1
—
1.1
µA
Input Leakage Current with VIN
above VDD
ILK
VDD < VIN < VDD+2.0 V
0
5
150
µA
(VIN = 0 V)
Note:
1. See Figure 4.6 Typical VOH Curves on page 33 and Figure 4.7 Typical VOL Curves on page 33 for more information.
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EFM8BB1 Data Sheet
Electrical Specifications
4.1.13 SMBus
Table 4.13. SMBus Peripheral Timing Performance (Master Mode)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Standard Mode (100 kHz Class)
I2C Operating Frequency
fI2C
0
—
702
kHz
SMBus Operating Frequency
fSMB
401
—
702
kHz
Bus Free Time Between STOP and tBUF
START Conditions
9.4
—
—
µs
Hold Time After (Repeated)
START Condition
tHD:STA
4.7
—
—
µs
Repeated START Condition Setup
Time
tSU:STA
9.4
—
—
µs
STOP Condition Setup Time
tSU:STO
9.4
—
—
µs
Data Hold Time
tHD:DAT
4893
—
—
ns
Data Setup Time
tSU:DAT
4483
—
—
ns
Detect Clock Low Timeout
tTIMEOUT
25
—
—
ms
Clock Low Period
tLOW
4.7
—
—
µs
Clock High Period
tHIGH
9.4
—
504
µs
Fast Mode (400 kHz Class)
I2C Operating Frequency
fI2C
0
—
2552
kHz
SMBus Operating Frequency
fSMB
401
—
2552
kHz
Bus Free Time Between STOP and tBUF
START Conditions
2.6
—
—
µs
Hold Time After (Repeated)
START Condition
tHD:STA
1.3
—
—
µs
Repeated START Condition Setup
Time
tSU:STA
2.6
—
—
µs
STOP Condition Setup Time
tSU:STO
2.6
—
—
µs
Data Hold Time
tHD:DAT
4893
—
—
ns
Data Setup Time
tSU:DAT
4483
—
—
ns
Detect Clock Low Timeout
tTIMEOUT
25
—
—
ms
Clock Low Period
tLOW
1.3
—
—
µs
Clock High Period
tHIGH
2.6
—
504
µs
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EFM8BB1 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Note:
1. The minimum SMBus frequency is limited by the maximum Clock High Period requirement of the SMBus specification.
2. The maximum I2C and SMBus frequencies are limited by the minimum Clock Low Period requirements of their respective specifications. The maximum frequency cannot be achieved with all combinations of oscillators and dividers available, but the effective
frequency must not exceed 256 kHz.
3. Data setup and hold timing at 25 MHz or lower with EXTHOLD set to 1.
4. SMBus has a maximum requirement of 50 µs for Clock High Period. Operating frequencies lower than 40 kHz will be longer than
50 µs. I2C can support periods longer than 50 µs.
Table 4.14. SMBus Peripheral Timing Formulas (Master Mode)
Parameter
Symbol
Clocks
SMBus Operating Frequency
fSMB
fCSO / 3
Bus Free Time Between STOP and START Conditions
tBUF
2 / fCSO
Hold Time After (Repeated) START Condition
tHD:STA
1 / fCSO
Repeated START Condition Setup Time
tSU:STA
2 / fCSO
STOP Condition Setup Time
tSU:STO
2 / fCSO
Clock Low Period
tLOW
1 / fCSO
Clock High Period
tHIGH
2 / fCSO
Note:
1. fCSO is the SMBus peripheral clock source overflow frequency.
tLOW
SCL
VIH
VIL
tHD:STA
SDA
tHD:DAT
tHIGH
tSU:DAT
tSU:STA
tSU:STO
VIH
VIL
tBUF
P
S
S
P
Figure 4.1. SMBus Peripheral Timing Diagram (Master Mode)
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Rev. 1.6 | 28
EFM8BB1 Data Sheet
Electrical Specifications
4.2 Thermal Conditions
Table 4.15. Thermal Conditions
Parameter
Symbol
Test Condition
Thermal Resistance (Junction to
Ambient)
θJA
Thermal Resistance (Junction to
Case)
θJC
Min
Typ
Max
Unit
SOIC-16 Packages
—
70
—
°C/W
QFN-20 Packages
—
60
—
°C/W
QSOP-24 Packages
—
65
—
°C/W
QFN-20 Packages
─
28.86
─
°C/W
Note:
1. Thermal resistance assumes a multi-layer PCB with any exposed pad soldered to a PCB pad.
4.3 Absolute Maximum Ratings
Stresses above those listed in Table 4.16 Absolute Maximum Ratings on page 29 may cause permanent damage to the device. This
is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation
listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. For
more information on the available quality and reliability data, see the Quality and Reliability Monitor Report at http://www.silabs.com/
support/quality/pages/default.aspx.
Table 4.16. Absolute Maximum Ratings
Parameter
Symbol
Ambient Temperature Under Bias
Min
Max
Unit
TBIAS
–55
125
°C
Storage Temperature
TSTG
–65
150
°C
Voltage on VDD
VDD
GND–0.3
4.2
V
Voltage on I/O pins or RST
VIN
VDD ≥ 3.3 V
GND–0.3
5.8
V
V < 3.3 V
GND–0.3
VDD+2.5
V
—
200
mA
Total Current Sunk into Supply Pin
Test Condition
IVDD
DD
Total Current Sourced out of Ground
Pin
IGND
200
—
mA
Current Sourced or Sunk by Any I/O
Pin or RSTb
IIO
-100
100
mA
Operating Junction Temperature
TJ
TA = -40 °C to 85 °C
–40
105
°C
TA = -40 °C to 125 °C (I-grade or Agrade parts only)
-40
130
°C
Exposure to maximum rating conditions for extended periods may affect device reliability.
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Rev. 1.6 | 29
EFM8BB1 Data Sheet
Electrical Specifications
4.4 Typical Performance Curves
Figure 4.2. Typical Operating Supply Current using HFOSC0
Figure 4.3. Typical Operating Supply Current using LFOSC
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Rev. 1.6 | 30
EFM8BB1 Data Sheet
Electrical Specifications
Figure 4.4. Typical ADC0 and Internal Reference Supply Current in Burst Mode
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Rev. 1.6 | 31
EFM8BB1 Data Sheet
Electrical Specifications
Figure 4.5. Typical ADC0 Supply Current in Normal (always-on) Mode
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Rev. 1.6 | 32
EFM8BB1 Data Sheet
Electrical Specifications
Figure 4.6. Typical VOH Curves
Figure 4.7. Typical VOL Curves
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Rev. 1.6 | 33
EFM8BB1 Data Sheet
Typical Connection Diagrams
5. Typical Connection Diagrams
5.1 Power
Figure 5.1 Power Connection Diagram on page 34 shows a typical connection diagram for the power pins of the EFM8BB1 devices.
2.2-3.6 V (in)
1 µF and 0.1 µF bypass
capacitors required for
the power pins placed
as close to the pins as
possible.
EFM8BB1
Device
VDD
GND
Figure 5.1. Power Connection Diagram
5.2 Debug
The diagram below shows a typical connection diagram for the debug connections pins. The pin sharing resistors are only required if
the functionality on the C2D (a GPIO pin) and the C2CK (RSTb) is routed to external circuitry. For example, if the RSTb pin is connected to an external switch with debouncing filter or if the GPIO sharing with the C2D pin is connected to an external circuit, the pin sharing resistors and connections to the debug adapter must be placed on the hardware. Otherwise, these components and connections
can be omitted.
For more information on debug connections, see the example schematics and information available in application note, AN124: Pin
Sharing Techniques for the C2 Interface. Application notes can be found on the Silicon Labs website (http://www.silabs.com/8bit-appnotes) or in Simplicity Studio.
VDD
EFM8BB1 Device
C2CK
1k
1k
External
System
1k
(if pin sharing)
C2D
(if pin sharing)
1k
1k
GND
Debug Adapter
Figure 5.2. Debug Connection Diagram
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Rev. 1.6 | 34
EFM8BB1 Data Sheet
Typical Connection Diagrams
5.3 Other Connections
Other components or connections may be required to meet the system-level requirements. Application note, "AN203: 8-bit MCU Printed
Circuit Board Design Notes", contains detailed information on these connections. Application Notes can be accessed on the Silicon
Labs website (www.silabs.com/8bit-appnotes).
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Rev. 1.6 | 35
EFM8BB1 Data Sheet
Pin Definitions
6. Pin Definitions
6.1 EFM8BB1x-QSOP24 Pin Definitions
N/C
1
24
N/C
P0.2
2
23
P0.3
P0.1
3
22
P0.4
P0.0
4
21
P0.5
GND
5
20
P0.6
VDD
6
19
P0.7
RSTb / C2CK
7
18
P1.0
C2D / P2.0
8
17
P1.1
P1.7
9
16
P1.2
P1.6
10
15
P1.3
P1.5
11
14
P1.4
P2.1
12
13
N/C
24 pin QSOP
(Top View)
Figure 6.1. EFM8BB1x-QSOP24 Pinout
Table 6.1. Pin Definitions for EFM8BB1x-QSOP24
Pin
Pin Name
Description
1
N/C
No Connection
2
P0.2
Multifunction I/O
Crossbar Capability
Additional Digital
Functions
Analog Functions
Yes
P0MAT.2
ADC0.2
INT0.2
CMP0P.2
INT1.2
CMP0N.2
Number
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EFM8BB1 Data Sheet
Pin Definitions
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
P0.1
Multifunction I/O
Yes
P0MAT.1
ADC0.1
INT0.1
CMP0P.1
INT1.1
CMP0N.1
Number
3
AGND
4
P0.0
Multifunction I/O
Yes
P0MAT.0
ADC0.0
INT0.0
CMP0P.0
INT1.0
CMP0N.0
VREF
5
GND
Ground
6
VDD
Supply Power Input
7
RSTb /
Active-low Reset /
C2CK
C2 Debug Clock
P2.0 /
Multifunction I/O /
C2D
C2 Debug Data
P1.7
Multifunction I/O
8
9
Yes
P1MAT.7
ADC0.15
CMP1P.7
CMP1N.7
10
P1.6
Multifunction I/O
Yes
P1MAT.6
ADC0.14
CMP1P.6
CMP1N.6
11
P1.5
Multifunction I/O
Yes
P1MAT.5
ADC0.13
CMP1P.5
CMP1N.5
12
P2.1
Multifunction I/O
13
N/C
No Connection
14
P1.4
Multifunction I/O
Yes
P1MAT.4
ADC0.12
CMP1P.4
CMP1N.4
15
P1.3
Multifunction I/O
Yes
P1MAT.3
ADC0.11
CMP1P.3
CMP1N.3
16
P1.2
Multifunction I/O
Yes
P1MAT.2
ADC0.10
CMP1P.2
CMP1N.2
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EFM8BB1 Data Sheet
Pin Definitions
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
P1.1
Multifunction I/O
Yes
P1MAT.1
ADC0.9
Number
17
CMP1P.1
CMP1N.1
18
P1.0
Multifunction I/O
Yes
P1MAT.0
ADC0.8
CMP1P.0
CMP1N.0
19
20
P0.7
P0.6
Multifunction I/O
Multifunction I/O
Yes
Yes
P0MAT.7
ADC0.7
INT0.7
CMP0P.7
INT1.7
CMP0N.7
P0MAT.6
ADC0.6
CNVSTR
CMP0P.6
INT0.6
CMP0N.6
INT1.6
21
22
23
P0.5
P0.4
P0.3
Multifunction I/O
Multifunction I/O
Multifunction I/O
Yes
Yes
Yes
P0MAT.5
ADC0.5
INT0.5
CMP0P.5
INT1.5
CMP0N.5
P0MAT.4
ADC0.4
INT0.4
CMP0P.4
INT1.4
CMP0N.4
P0MAT.3
ADC0.3
EXTCLK
CMP0P.3
INT0.3
CMP0N.3
INT1.3
24
N/C
No Connection
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Rev. 1.6 | 38
EFM8BB1 Data Sheet
Pin Definitions
RSTb / C2CK
5
P0.3
P0.4
P0.5
19
18
17
GND
6
P1.6
P2.0 / C2D
(Top View)
10
4
P1.3
VDD
16
20 pin QFN
9
3
P1.4
GND
8
2
P1.5
P0.0
P0.2
1
7
P0.1
20
6.2 EFM8BB1x-QFN20 Pin Definitions
P0.6
15
P0.7
14
P1.0
13
P1.1
12
GND
11
P1.2
Figure 6.2. EFM8BB1x-QFN20 Pinout
Table 6.2. Pin Definitions for EFM8BB1x-QFN20
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
P0.1
Multifunction I/O
Yes
P0MAT.1
ADC0.1
INT0.1
CMP0P.1
INT1.1
CMP0N.1
Number
1
AGND
2
P0.0
Multifunction I/O
Yes
P0MAT.0
ADC0.0
INT0.0
CMP0P.0
INT1.0
CMP0N.0
VREF
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EFM8BB1 Data Sheet
Pin Definitions
Pin
Pin Name
Description
3
GND
Ground
4
VDD
Supply Power Input
5
RSTb /
Active-low Reset /
C2CK
C2 Debug Clock
P2.0 /
Multifunction I/O /
C2D
C2 Debug Data
P1.6
Multifunction I/O
Crossbar Capability
Additional Digital
Functions
Analog Functions
Yes
P1MAT.6
ADC0.14
Number
6
7
CMP1P.6
CMP1N.6
8
P1.5
Multifunction I/O
Yes
P1MAT.5
ADC0.13
CMP1P.5
CMP1N.5
9
P1.4
Multifunction I/O
Yes
P1MAT.4
ADC0.12
CMP1P.4
CMP1N.4
10
P1.3
Multifunction I/O
Yes
P1MAT.3
ADC0.11
CMP1P.3
CMP1N.3
11
P1.2
Multifunction I/O
Yes
P1MAT.2
ADC0.10
CMP1P.2
CMP1N.2
12
GND
Ground
13
P1.1
Multifunction I/O
Yes
P1MAT.1
ADC0.9
CMP1P.1
CMP1N.1
14
P1.0
Multifunction I/O
Yes
P1MAT.0
ADC0.8
CMP1P.0
CMP1N.0
15
16
P0.7
P0.6
Multifunction I/O
Multifunction I/O
Yes
Yes
P0MAT.7
ADC0.7
INT0.7
CMP0P.7
INT1.7
CMP0N.7
P0MAT.6
ADC0.6
CNVSTR
CMP0P.6
INT0.6
CMP0N.6
INT1.6
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EFM8BB1 Data Sheet
Pin Definitions
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
P0.5
Multifunction I/O
Yes
P0MAT.5
ADC0.5
INT0.5
CMP0P.5
INT1.5
CMP0N.5
P0MAT.4
ADC0.4
INT0.4
CMP0P.4
INT1.4
CMP0N.4
P0MAT.3
ADC0.3
EXTCLK
CMP0P.3
INT0.3
CMP0N.3
Number
17
18
19
P0.4
P0.3
Multifunction I/O
Multifunction I/O
Yes
Yes
INT1.3
20
Center
P0.2
GND
Multifunction I/O
Yes
P0MAT.2
ADC0.2
INT0.2
CMP0P.2
INT1.2
CMP0N.2
Ground
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Rev. 1.6 | 41
EFM8BB1 Data Sheet
Pin Definitions
6.3 EFM8BB1x-SOIC16 Pin Definitions
P0.2
1
16
P0.3
P0.1
2
15
P0.4
P0.0
3
14
P0.5
GND
4
13
P0.6
VDD
5
12
P0.7
RSTb / C2CK
6
11
P1.0
P2.0 / C2D
7
10
P1.1
P1.3
8
9
P1.2
16 pin SOIC
(Top View)
Figure 6.3. EFM8BB1x-SOIC16 Pinout
Table 6.3. Pin Definitions for EFM8BB1x-SOIC16
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
P0.2
Multifunction I/O
Yes
P0MAT.2
ADC0.2
INT0.2
CMP0P.2
INT1.2
CMP0N.2
P0MAT.1
ADC0.1
INT0.1
CMP0P.1
INT1.1
CMP0N.1
P0MAT.0
ADC0.0
INT0.0
CMP0P.0
INT1.0
CMP0N.0
Number
1
2
3
P0.1
P0.0
Multifunction I/O
Multifunction I/O
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Yes
Yes
Rev. 1.6 | 42
EFM8BB1 Data Sheet
Pin Definitions
Pin
Pin Name
Description
4
GND
Ground
5
VDD
Supply Power Input
6
RSTb /
Active-low Reset /
C2CK
C2 Debug Clock
P2.0 /
Multifunction I/O /
C2D
C2 Debug Data
P1.3
Multifunction I/O
Crossbar Capability
Additional Digital
Functions
Analog Functions
Yes
P1MAT.3
ADC0.11
Number
7
8
CMP1P.5
CMP1N.5
9
P1.2
Multifunction I/O
Yes
P1MAT.2
ADC0.10
CMP1P.4
CMP1N.4
10
P1.1
Multifunction I/O
Yes
P1MAT.1
ADC0.9
CMP1P.3
CMP1N.3
11
P1.0
Multifunction I/O
Yes
P1MAT.0
ADC0.8
CMP1P.2
CMP1N.2
12
13
P0.7
P0.6
Multifunction I/O
Multifunction I/O
Yes
Yes
P0MAT.7
ADC0.7
INT0.7
CMP1P.1
INT1.7
CMP1N.1
P0MAT.6
ADC0.6
CNVSTR
CMP1P.0
INT0.6
CMP1N.0
INT1.6
14
15
16
P0.5
P0.4
P0.3
Multifunction I/O
Multifunction I/O
Multifunction I/O
Yes
Yes
Yes
P0MAT.5
ADC0.5
INT0.5
CMP0P.5
INT1.5
CMP0N.5
P0MAT.4
ADC0.4
INT0.4
CMP0P.4
INT1.4
CMP0N.4
P0MAT.3
ADC0.3
EXTCLK
CMP0P.3
INT0.3
CMP0N.3
INT1.3
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Rev. 1.6 | 43
EFM8BB1 Data Sheet
QSOP24 Package Specifications
7. QSOP24 Package Specifications
7.1 QSOP24 Package Dimensions
Figure 7.1. QSOP24 Package Drawing
Table 7.1. QSOP24 Package Dimensions
Dimension
Min
Typ
Max
A
—
—
1.75
A1
0.10
—
0.25
b
0.20
—
0.30
c
0.10
—
0.25
D
8.65 BSC
E
6.00 BSC
E1
3.90 BSC
e
0.635 BSC
L
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0.40
—
1.27
Rev. 1.6 | 44
EFM8BB1 Data Sheet
QSOP24 Package Specifications
Dimension
theta
Min
Typ
Max
0º
—
8º
aaa
0.20
bbb
0.18
ccc
0.10
ddd
0.10
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-137, variation AE.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Rev. 1.6 | 45
EFM8BB1 Data Sheet
QSOP24 Package Specifications
7.2 QSOP24 PCB Land Pattern
Figure 7.2. QSOP24 PCB Land Pattern Drawing
Table 7.2. QSOP24 PCB Land Pattern Dimensions
Dimension
Min
Max
C
5.20
5.30
E
0.635 BSC
X
0.30
0.40
Y
1.50
1.60
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This land pattern design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A No-Clean, Type-3 solder paste is recommended.
8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Rev. 1.6 | 46
EFM8BB1 Data Sheet
QSOP24 Package Specifications
7.3 QSOP24 Package Marking
EFM8
PPPPPPPP #
TTTTTTYYWW
Figure 7.3. QSOP24 Package Marking
The package marking consists of:
• PPPPPPPP – The part number designation.
• TTTTTT – A trace or manufacturing code.
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
• # – The device revision (A, B, etc.).
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Rev. 1.6 | 47
EFM8BB1 Data Sheet
QFN20 Package Specifications
8. QFN20 Package Specifications
8.1 QFN20 Package Dimensions
Figure 8.1. QFN20 Package Drawing
Table 8.1. QFN20 Package Dimensions
Dimension
Min
Typ
Max
A
0.70
0.75
0.80
A1
0.00
0.02
0.05
A3
0.20 REF
b
0.18
0.25
0.30
c
0.25
0.30
0.35
D
D2
3.00 BSC
1.6
1.70
e
0.50 BSC
E
3.00 BSC
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1.80
Rev. 1.6 | 48
EFM8BB1 Data Sheet
QFN20 Package Specifications
Dimension
Min
Typ
Max
E2
1.60
1.70
1.80
f
L
2.50 BSC
0.30
K
R
0.40
0.50
0.25 REF
0.09
0.125
aaa
0.15
bbb
0.10
ccc
0.10
ddd
0.05
eee
0.08
fff
0.10
0.15
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. The drawing complies with JEDEC MO-220.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Rev. 1.6 | 49
EFM8BB1 Data Sheet
QFN20 Package Specifications
8.2 QFN20 PCB Land Pattern
Figure 8.2. QFN20 PCB Land Pattern Drawing
Table 8.2. QFN20 PCB Land Pattern Dimensions
Dimension
Min
Max
C1
3.10
C2
3.10
C3
2.50
C4
2.50
E
0.50
X1
0.30
X2
0.25
0.35
X3
1.80
Y1
0.90
Y2
Y3
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0.25
0.35
1.80
Rev. 1.6 | 50
EFM8BB1 Data Sheet
QFN20 Package Specifications
Dimension
Min
Max
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
6. The stencil thickness should be 0.125 mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
8. A 2 x 2 array of 0.75 mm openings on a 0.95 mm pitch should be used for the center pad to assure proper paste volume.
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
8.3 QFN20 Package Marking
PPPP
PPPP
TTTTTT
YYWW #
Figure 8.3. QFN20 Package Marking
The package marking consists of:
• PPPPPPPP – The part number designation.
• TTTTTT – A trace or manufacturing code.
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
• # – The device revision (A, B, etc.).
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Rev. 1.6 | 51
EFM8BB1 Data Sheet
SOIC16 Package Specifications
9. SOIC16 Package Specifications
9.1 SOIC16 Package Dimensions
Figure 9.1. SOIC16 Package Drawing
Table 9.1. SOIC16 Package Dimensions
Dimension
Min
Typ
Max
A
—
—
1.75
A1
0.10
—
0.25
A2
1.25
—
—
b
0.31
—
0.51
c
0.17
—
0.25
D
9.90 BSC
E
6.00 BSC
E1
3.90 BSC
e
1.27 BSC
L
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0.40
—
1.27
Rev. 1.6 | 52
EFM8BB1 Data Sheet
SOIC16 Package Specifications
Dimension
Min
L2
Typ
Max
0.25 BSC
h
0.25
—
0.50
θ
0º
—
8º
aaa
0.10
bbb
0.20
ccc
0.10
ddd
0.25
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Rev. 1.6 | 53
EFM8BB1 Data Sheet
SOIC16 Package Specifications
9.2 SOIC16 PCB Land Pattern
Figure 9.2. SOIC16 PCB Land Pattern Drawing
Table 9.2. SOIC16 PCB Land Pattern Dimensions
Dimension
Feature
(mm)
Pad Column Spacing
5.40
E
Pad Row Pitch
1.27
X1
Pad Width
0.60
Y1
Pad Length
1.55
C1
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N for Density Level B (Median Land Protrusion).
3. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
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Rev. 1.6 | 54
EFM8BB1 Data Sheet
SOIC16 Package Specifications
9.3 SOIC16 Package Marking
EFM8
PPPPPPPP #
TTTTTTYYWW
Figure 9.3. SOIC16 Package Marking
The package marking consists of:
• PPPPPPPP – The part number designation.
• TTTTTT – A trace or manufacturing code.
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
• # – The device revision (A, B, etc.).
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Rev. 1.6 | 55
EFM8BB1 Data Sheet
Revision History
10. Revision History
10.1 Revision 1.6
March 13th, 2017
Updated the language in 1. Feature List to clarify the package offerings for each of the different temperature grades.
Corrected the application note number for AN124: Pin Sharing Techniques for the C2 Interface in 5.2 Debug.
10.2 Revision 1.5
October 7th, 2016
Added A-grade parts.
Added specifications for 4.1.13 SMBus.
Added bootloader pinout information to 3.10 Bootloader.
Added CRC Calculation Time to 4.1.4 Flash Memory.
Added Thermal Resistance (Junction to Case) for QFN20 packages to 4.2 Thermal Conditions.
Added a note linking to the Typical VOH and VOL Performance graphs in 4.1.12 Port I/O.
Added 4.1.10 1.8 V Internal LDO Voltage Regulator.
Added a note to 3.1 Introduction referencing the Reference Manual.
10.3 Revision 1.4
April 22nd, 2016
Added a reference to AN945: EFM8 Factory Bootloader User Guide in 3.10 Bootloader.
Added I-grade devices.
Added a note that all GPIO values are undefined when VDD is below 1 V to 4.1.1 Recommended Operating Conditions.
Adjusted the Total Current Sunk into Supply Pin and Total Current Sourced out of Ground Pin specifications in 4.3 Absolute Maximum
Ratings.
10.4 Revision 1.3
January 7th, 2016
Added 5.2 Debug.
Updated 3.10 Bootloader to include information about the bootloader implementation.
10.5 Revision 1.2
Updated Port I/O specifications in 4.1.12 Port I/O to include new VOL specifications.
Added a note to Table 4.3 Reset and Supply Monitor on page 18 regarding guaranteed operation.
Updated package diagram and landing diagram specifications for the QFN20 package.
10.6 Revision 1.1
Initial release.
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Rev. 1.6 | 56
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