EFM8UB30F40G-A-QFN20R

D KEY FEATURES • Pipelined 8-bit C8051 core with 48 MHz maximum operating frequency N ew The EFM8UB3, part of the Universal Bee family of MCUs, is a multi-purpose line of 8-bit microcontrollers with USB feature set in small packages. es ig ns EFM8 Universal Bee Family EFM8UB3 Data Sheet These devices offer high value by integrating an innovative energy-smart USB peripheral interface, charger detect circuit, 8 kV ESD protection, and enhanced high speed communication interfaces into small packages, making them ideal for space-constrained USB applications. With an efficient 8051 core and precision analog, the EFM8UB3 family is also optimal for embedded applications. Core / Memory om Debug Interface with C2 ec RAM Memory 3328 bytes R N ot SMBus USB SPI • Six 16-bit timers • UART and SMBus master/slave • Priority crossbar for flexible pin mapping Energy Management External CMOS Oscillator High Frequency 48 MHz RC Oscillator Internal LDO Regulator Power-On Reset Low Frequency RC Oscillator High Frequency 24.5 MHz RC Oscillator Brown-Out Detector 5 V-to 3.3 V LDO Regulator 8-bit SFR bus Serial Interfaces UART • One 12-bit ADC and two analog comparators with internal voltage DAC as reference input Clock Management CIP-51 8051 Core (48 MHz) Flash Memory 40 KB • USB charger detect circuit (USB-BCS 1.2 compliant) • Consumer electronics • USB Type-C converters • USB Type-C billboard/alternate mode m en de d • USB I/O controls • Docking stations/USB hubs • Dongles • Low Energy USB with full- and low-speed support saves up to 90% of the USB energy fo r EFM8UB3 applications include the following: • Up to 17 multifunction I/O pins I/O Ports External Interrupts General Purpose I/O Pin Reset Pin Wakeup Timers and Triggers Analog Interfaces Timers 0/1/2 PCA/PWM ADC Charger Det Watchdog Timer Timer 3/4/5 Internal Voltage Reference Comparator 1 4 x Configurable Logic Units Security 16-bit CRC Comparator 0 Lowest power mode with peripheral operational: Normal Idle Suspend silabs.com | Building a more connected world. Snooze Shutdown Rev. 1.1 EFM8UB3 Data Sheet Feature List 1. Feature List The EFM8UB3 highlighted features are listed below. es ig ns • Power Management • 5 V-input LDO regulator for direct connection to USB supply • External LDO is needed for USB-C VBUS powered applications that require more than 5 V. • Internal low dropout (LDO) regulator for CPU core voltage • Power-on reset and brownout detect circuit • Multiple power modes supported to minimize power consumption while maintaining performance • General-Purpose I/O • Up to 17 pins • VIO + 2.5 V tolerant; push-pull or open-drain D N ew • • Priority crossbar to support flexible digital peripheral pin assignments Timers/Counters/PWM • 6 general purpose 16-bit counters/timers • 16-bit Programmable Counter Array (PCA) with 3 channels of PWM, capture/compare, or frequency output capability, and hardware kill/safe state capability • Independent watchdog timer, clocked from the low frequency oscillator Communication Interfaces and Digital Peripherals • UART, up to 3 Mbaud • SMBus (1 Mbps) • USB 2.0-compliant full speed with integrated low-power transceiver, 4 bidirectional endpoints and dedicated 1024byte buffer • 16-bit CRC unit, supporting automatic CRC of flash at 256byte boundaries Single Voltage Supply • (VREGIN shorted to VDD): 2.3 to 3.6 V • (VREGIN not shorted to VDD): 2.7 to 5.25 V Pre-loaded USB Bootloader Package Options: QFN20, QFN24, QSOP24 Temperature Range: -40 to +85 °C • • • • • ec om m en de d fo r • High-speed CIP-51 MCU Core • Pipelined instruction architecture; executes 70% of instruction set in 1 or 2 system clocks • Up to 48 MIPS throughput with 48 MHz clock • Uses standard 8051 instruction set • Expanded interrupt handler • Memory • 40 KB Flash • Flash is in-system programmable in 512-byte sectors • 3328 bytes RAM, including: • 256 bytes standard 8051 RAM • 2048 bytes on-chip XRAM • 1024 bytes of USB buffer • On-chip Debug • On-chip debug circuitry facilitates full speed, non-intrusive in-system debug (no emulator required) • Provides 4 hardware breakpoints, single stepping, inspect/ modify memory and registers • 12-bit Analog-to-Digital Converter • Multiple selectable inputs • Up to 800 ksps 10-bit mode • Precise Internal VREF 1.65 V or external VREF supported • Clock Sources • 48 MHz ± 1.5% precision internal oscillator and ±0.25% using USB clock recovery • 24.5 MHz low power internal oscillator with ±2% accuracy • 80 kHz low-frequency, low power internal oscillator (LFO) • External CMOS clock option • Flexible clock divider: Reduce frequency by up to 128x from any clock source • 2 x Analog Comparators • Multiplexed selectable inputs • Integrated 6-bit programmable reference voltage selectable as comparator input channel • Programmable hysteresis and response time • 400 nA current consumption in low power mode N ot R With on-chip power-on reset, voltage supply monitor, watchdog timer, and clock oscillator, the EFM8UB3 devices are truly standalone system-on-a-chip solutions. The flash memory is reprogrammable in-circuit, providing nonvolatile data storage and allowing field upgrades of the firmware. The on-chip debugging interface (C2) allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, and run and halt commands. All analog and digital peripherals are fully functional while debugging. Devices are available in 20-pin QFN, 24-pin QFN, or 24-pin QSOP packages. All package options are lead-free and RoHS compliant. silabs.com | Building a more connected world. Rev. 1.1 | 2 EFM8UB3 Data Sheet Ordering Information 2. Ordering Information EFM8 UB3 0 F 40 G – A – QFN24 R Tape and Reel (Optional) es ig ns Package Type Revision Temperature Grade G (-40 to +85) Flash Memory Size – 40 KB Memory Type (Flash) Family Feature Set D Universal Bee 3 Family Silicon Labs EFM8 Product Line N ew Figure 2.1. EFM8UB3 Part Numbering m en de d fo r All EFM8UB3 family members have the following features: • CIP-51 Core running up to 48 MHz • Three Internal Oscillators (48 MHz, 24.5 MHz, and 80 kHz) • USB Full/Low speed Function Controller • SMBus • SPI • UART • 3-Channel Programmable Counter Array (PWM, Clock Generation, Capture/Compare) • Six 16-bit Timers • Four Configurable Logic Units • 2 Analog Comparators • 12-bit Analog-to-Digital Converter with integrated multiplexer, voltage reference, and temperature sensor • 16-bit CRC Unit • Pre-loaded USB bootloader Comparator 1 Inputs Temperature Range Package 8 Yes -40 to +85 °C QSOP24 EFM8UB31F40G-A-QFN24 40 3328 17 16 8 8 Yes -40 to +85 °C QFN24 EFM8UB30F40G-A-QFN20 40 3328 13 12 8 4 Yes -40 to +85 °C QFN20 R N ot silabs.com | Building a more connected world. (RoHS Compliant) Comparator 0 Inputs 8 Pb-free ADC0 Channels 16 I/Os (Total) 17 Digital Port 3328 ec 40 Part Number EFM8UB31F40G-A-QSOP24 Ordering RAM (Bytes) Table 2.1. Product Selection Guide Flash Memory (kB) om In addition to these features, each part number in the EFM8UB3 family has a set of features that vary across the product line. The product selection guide shows the features available on each family member. Rev. 1.1 | 3 Table of Contents 1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . . . . . . . . . . . . . . . . . . . . 3.2 Power . . . . . . . . . . . . . . . . . . . . . . . 3.3 I/O. . . . . . . . . . . . . . . . . . . . . . . . 3.4 Clocking . . . . . . . . . . . . . . . . . . . . . . . 3.5 Counters/Timers and PWM . . . . . . . . . . . . . . . . 3.6 Communications and Other Digital Peripherals . . . . . . . . . . 3.7 Analog . . . . . . . . . . 3.8 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 Debugging . . . . . . . . . . . . . . . 3.10 Bootloader . . . . . . . . . . . . . . . . . . . . . 6 . . . . . . . . . 7 . . . . . . . . . 7 . . . . . . . . . 8 . . . . . . . . . 8 . . . . . . . . .10 . . . . . . . . .12 . . . . . . . . . . . . . . . .13 . . . . . . . . . . . . . . . .13 . . . . . . . . . . . . . . . .14 . . . . . . . . . . . . . . . . . . . . . . . . . . 16 fo r 4. Electrical Specifications . D . . . N ew 3.1 Introduction. es ig ns 3. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 .16 .17 .19 .20 .20 .21 .21 .22 .23 .24 .24 .24 .25 .26 .27 .28 .29 4.2 Thermal Conditions . R ec om m en de d 4.1 Electrical Characteristics . . . . . . . 4.1.1 Recommended Operating Conditions . 4.1.2 Power Consumption. . . . . . . 4.1.3 Reset and Supply Monitor . . . . . 4.1.4 Flash Memory . . . . . . . . . 4.1.5 Power Management Timing . . . . 4.1.6 Internal Oscillators . . . . . . . 4.1.7 External Clock Input . . . . . . . 4.1.8 ADC . . . . . . . . . . . . 4.1.9 Voltage Reference . . . . . . . 4.1.10 Temperature Sensor . . . . . . 4.1.11 5 V Voltage Regulator. . . . . . 4.1.12 1.8 V Internal LDO Voltage Regulator 4.1.13 Comparators . . . . . . . . . 4.1.14 Configurable Logic . . . . . . . 4.1.15 Port I/O . . . . . . . . . . 4.1.16 USB Transceiver . . . . . . . 4.1.17 SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 4.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . .32 N ot . . 5. Typical Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 5.2 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 5.3 Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 5.4 Other Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 silabs.com | Building a more connected world. Rev. 1.1 | 4 6. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 . . . . . . . . . . . . . . . . . . . . .38 6.2 EFM8UB3x-QFN24 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . .42 6.3 EFM8UB3x-QFN20 . . . . . . . . . . . . . . . . . . . . . . .46 7. QFN24 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . 49 . . . . . 7.1 QFN24 Package Dimensions . . . . . . . . . . . . . . . . 7.2 PCB Land Pattern . . . . . . . . . . . . . . . . . . . 7.3 Package Marking . . . . . . . . . . . . . . . . . . . . es ig ns 6.1 EFM8UB3x-QSOP24 Pin Definitions . . . . . . . . . .49 . . . . . . . . .51 . . . . . . . . .52 8. QSOP24 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . 53 . . . . . . . . . . . . . . . . . . . . . . .53 8.2 PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 8.3 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 9. QFN20 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . 57 . . . . . . . 9.2 QFN20 PCB Land Pattern . . . . . . . . . 9.3 QFN20 Package Marking . . . . . . . . . . . N ew . . . . . . . . . . . . . . . . . . .57 . . . . . . . . . . . . . . . .59 . . . . . . . . . . . . . . . .60 10. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 N ot R ec om m en de d fo r 9.1 QFN20 Package Dimensions . D 8.1 Package Dimensions silabs.com | Building a more connected world. Rev. 1.1 | 5 EFM8UB3 Data Sheet System Overview 3. System Overview 3.1 Introduction Digital Peripherals Reset 40 KB ISP Flash Program Memory UART1 256 Byte SRAM Timers 0, 1, 2, 3, 4, 5 Power-On Reset SYSCLK CRC SFR Bus CMOS Oscillator Input 24.5 MHz 2% Oscillator USB Peripheral D+ DVBUS Full / Low Speed Transceiver om 1 KB RAM P1.n Port 2 Drivers P2.n Internal Reference m en de d Clock Recovery Port 1 Drivers Crossbar Control VDD VREF VDD 12/10 bit ADC AMUX Voltage Regulators Config. Logic Units (4) P0.n Analog Peripherals 48 MHz 1.5% Oscillator Power Net N ew SPI System Clock Configuration EXTCLK D I2C / SMBus Low Freq. Oscillator GND Priority Crossbar Decoder 2048 Byte XRAM Independent Watchdog Timer VREGIN Port 0 Drivers 3-ch PCA Supply Monitor VDD Port I/O Configuration fo r C2CK/RSTb CIP-51 8051 Controller Core es ig ns Debug / C2D Programming Hardware Controller Charge Detection Low Power Temp Sensor + -+ 2 Comparators Figure 3.1. Detailed EFM8UB3 Block Diagram ec This section describes the EFM8UB3 family at a high level. N ot R For more information on the device packages and pinout, electrical specifications, and typical connection diagrams, see the EFM8UB3 Data Sheet. For more information on each module including register definitions, see the EFM8UB3 Reference Manual. For more information on any errata, see the EFM8UB3 Errata. silabs.com | Building a more connected world. Rev. 1.1 | 6 EFM8UB3 Data Sheet System Overview 3.2 Power Control over the device power consumption can be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral can be disabled when not in use and placed in low power mode. Digital peripherals, such as timers and serial buses, have their clocks gated off and draw little power when they are not in use. Table 3.1. Power Modes Details Mode Entry Normal Core and all peripherals clocked and fully operational — Wake-Up Sources es ig ns Power Mode — • Core halted • All peripherals clocked and fully operational • Code resumes execution on wake event Suspend • • • • • Core and peripheral clocks halted HFOSC0 and HFOSC1 oscillators stopped Regulators in normal bias mode for fast wake Timer 3 and 4 may clock from LFOSC0 Code resumes execution on wake event Stop • • • • • All internal power nets shut down 5V regulator remains active (if enabled) Internal 1.8 V LDO on Pins retain state Exit on any reset source Snooze • Core and peripheral clocks halted • HFOSC0 and HFOSC1 oscillators stopped • Regulators in low bias current mode for energy savings • Timer 3 and 4 may clock from LFOSC0 • Code resumes execution on wake event 1. Switch SYSCLK to HFOSC0 2. Set SNOOZE bit in PCON1 • • • • • Shutdown • • • • • 1. Set STOPCF bit in REG0CN 2. Set STOP bit in PCON0 • RSTb pin reset • Power-on reset USB0 Bus Activity Timer 4 Event SPI0 Activity Port Match Event Comparator 0 Falling Edge • CLUn Interrupt-Enabled Event N ew D • • • • • Any reset source m en de d fo r 1. Clear STOPCF bit in REG0CN 2. Set STOP bit in PCON0 USB0 Bus Activity Timer 4 Event SPI0 Activity Port Match Event Comparator 0 Falling Edge • CLUn Interrupt-Enabled Event ec om 1. Switch SYSCLK to HFOSC0 2. Set SUSPEND bit in PCON1 R 3.3 I/O All internal power nets shut down 5V regulator remains active (if enabled) Internal 1.8 V LDO off to save energy Pins retain state Exit on pin or power-on reset Set IDLE bit in PCON0 Any interrupt Idle N ot Digital and analog resources are externally available on the device’s multi-purpose I/O pins. Port pins P0.0-P1.6 can be defined as general-purpose I/O (GPIO), assigned to one of the internal digital resources through the crossbar or dedicated channels, or assigned to an analog function. Port pins P2.0 and P2.1 can be used as GPIO. Additionally, the C2 Interface Data signal (C2D) is shared with P2.0. The port control block offers the following features: • Up to 17 multi-functions I/O pins, supporting digital and analog functions. • Flexible priority crossbar decoder for digital peripheral assignment. • Two drive strength settings for each port. • Two direct-pin interrupt sources with dedicated interrupt vectors (INT0 and INT1). • Up to 17 direct-pin interrupt sources with shared interrupt vector (Port Match). silabs.com | Building a more connected world. Rev. 1.1 | 7 EFM8UB3 Data Sheet System Overview 3.4 Clocking The clock control system offers the following features: • Provides clock to core and peripherals. • 24.5 MHz internal oscillator (HFOSC0), accurate to ±2% over supply and temperature corners. • 48 MHz internal oscillator (HFOSC1), accurate to ±1.5% over supply and temperature corners. • 80 kHz low-frequency oscillator (LFOSC0). • External CMOS clock input (EXTCLK). • Clock divider with eight settings for flexible clock scaling: • Divide the selected clock source by 1, 2, 4, 8, 16, 32, 64, or 128. • HFOSC0 and HFOSC1 include 1.5x pre-scalers for further flexibility. D 3.5 Counters/Timers and PWM es ig ns The CPU core and peripheral subsystem may be clocked by both internal and external oscillator resources. By default, the system clock comes up running from the 24.5 MHz oscillator divided by 8. N ew Programmable Counter Array (PCA0) The programmable counter array (PCA) provides multiple channels of enhanced timer and PWM functionality while requiring less CPU intervention than standard counter/timers. The PCA consists of a dedicated 16-bit counter/timer and one 16-bit capture/compare module for each channel. The counter/timer is driven by a programmable timebase that has flexible external and internal clocking options. Each capture/compare module may be configured to operate independently in one of five modes: Edge-Triggered Capture, Software Timer, High-Speed Output, Frequency Output, or Pulse-Width Modulated (PWM) Output. Each capture/compare module has its own associated I/O line (CEXn) which is routed through the crossbar to port I/O when enabled. m en de d fo r 16-bit time base Programmable clock divisor and clock source selection Up to three independently-configurable channels 8, 9, 10, 11 and 16-bit PWM modes (center or edge-aligned operation) Output polarity control Frequency output mode Capture on rising, falling or any edge Compare function for arbitrary waveform generation Software timer (internal compare) mode Can accept hardware “kill” signal from comparator 0 or comparator 1 N ot R ec om • • • • • • • • • • silabs.com | Building a more connected world. Rev. 1.1 | 8 EFM8UB3 Data Sheet System Overview Timers (Timer 0, Timer 1, Timer 2, Timer 3, Timer 4, and Timer 5) Several counter/timers are included in the device: two are 16-bit counter/timers compatible with those found in the standard 8051, and the rest are 16-bit auto-reload timers for timing peripherals or for general purpose use. These timers can be used to measure time intervals, count external events and generate periodic interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary modes of operation. The other timers offer both 16-bit and split 8-bit timer functionality with auto-reload and capture capabilities. es ig ns Timer 0 and Timer 1 include the following features: • Standard 8051 timers, supporting backwards-compatibility with firmware and hardware. • Clock sources include SYSCLK, SYSCLK divided by 12, 4, or 48, the External Clock divided by 8, or an external pin. • 8-bit auto-reload counter/timer mode • 13-bit counter/timer mode • 16-bit counter/timer mode • Dual 8-bit counter/timer mode (Timer 0) fo r N ew D Timer 2, Timer 3, Timer 4, and Timer 5 are 16-bit timers including the following features: • Clock sources for all timers include SYSCLK, SYSCLK divided by 12, or the External Clock divided by 8 • LFOSC0 divided by 8 may be used to clock Timer 3 and Timer 4 in active or suspend/snooze power modes • Timer 4 is a low-power wake source, and can be chained together with Timer 3 • 16-bit auto-reload timer mode • Dual 8-bit auto-reload timer mode • External pin capture • LFOSC0 capture • Comparator 0 capture • USB Start-of-Frame (SOF) capture • Configurable Logic output capture Watchdog Timer (WDT0) m en de d The device includes a programmable watchdog timer (WDT) running off the low-frequency oscillator. A WDT overflow forces the MCU into the reset state. To prevent the reset, the WDT must be restarted by application software before overflow. If the system experiences a software or hardware malfunction preventing the software from restarting the WDT, the WDT overflows and causes a reset. Following a reset, the WDT is automatically enabled and running with the default maximum time interval. If needed, the WDT can be disabled by system software or locked on to prevent accidental disabling. Once locked, the WDT cannot be disabled until the next system reset. The state of the RST pin is unaffected by this reset. N ot R ec om The Watchdog Timer has the following features: • Programmable timeout interval • Runs from the low-frequency oscillator • Lock-out feature to prevent any modification until a system reset silabs.com | Building a more connected world. Rev. 1.1 | 9 EFM8UB3 Data Sheet System Overview 3.6 Communications and Other Digital Peripherals Universal Serial Bus (USB0) D N ew The USB0 module includes the following features: • Full and Low Speed functionality. • Implements 4 bidirectional endpoints. • Low Energy Mode to reduce active supply current based on bus bandwidth. • USB 2.0 compliant USB peripheral support (no host capability). • Direct module access to 1 KB of RAM for FIFO memory. • Clock recovery to meet USB clocking requirements with no external components. • Charger detection circuitry with automatic detection of SDP, CDP, and DCP interfaces. • D+ and D- can be routed to ADC input to support ACM and proprietary charger architectures. es ig ns The USB0 peripheral provides a full-speed USB 2.0 compliant device controller and PHY with additional Low Energy USB features. The device supports both full-speed (12MBit/s) and low speed (1.5MBit/s) operation, and includes a dedicated USB oscillator with clock recovery mechanism for crystal-free operation. No external components are required. The USB function controller (USB0) consists of a Serial Interface Engine (SIE), USB transceiver (including matching resistors and configurable pull-up resistors), and 1 KB FIFO block. The Low Energy Mode ensures the current consumption is optimized and enables USB communication on a strict power budget. Universal Asynchronous Receiver/Transmitter (UART1) UART1 is an asynchronous, full duplex serial port offering a variety of data formatting options. A dedicated baud rate generator with a 16-bit timer and selectable prescaler is included, which can generate a wide range of baud rates. A received data FIFO allows UART1 to receive multiple bytes before data is lost and an overflow occurs. m en de d fo r UART1 provides the following features: • Asynchronous transmissions and receptions. • Dedicated baud rate generator supports baud rates up to SYSCLK/2 (transmit) or SYSCLK/8 (receive). • 5, 6, 7, 8, or 9 bit data. • Automatic start and stop generation. • Automatic parity generation and checking. • Four byte FIFO on transmit and receive. • Auto-baud detection. • LIN break and sync field detection. • CTS / RTS hardware flow control. Serial Peripheral Interface (SPI0) R Supports 3- or 4-wire master or slave modes. Supports external clock frequencies up to 12 Mbps in master or slave mode. Support for all clock phase and polarity modes. 8-bit programmable clock rate (master). Programmable receive timeout (slave). Two byte FIFO on transmit and receive. Can operate in suspend or snooze modes and wake the CPU on reception of a byte. Support for multiple masters on the same data lines. N ot • • • • • • • • ec om The serial peripheral interface (SPI) module provides access to a flexible, full-duplex synchronous serial bus. The SPI can operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input to select the SPI in slave mode, or to disable master mode operation in a multi-master environment, avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can also be configured as a firmware-controlled chip-select output in master mode, or disabled to reduce the number of pins required. Additional general purpose port I/O pins can be used to select multiple slave devices in master mode. silabs.com | Building a more connected world. Rev. 1.1 | 10 EFM8UB3 Data Sheet System Overview System Management Bus / I2C (SMB0) D The SMBus module includes the following features: • Standard (up to 100 kbps), Fast (400 kbps), and Fast Mode Plus (1 Mbps) transfer speeds • Support for master, slave, and multi-master modes • Hardware synchronization and arbitration for multi-master mode • Clock low extending (clock stretching) to interface with faster masters • Hardware support for 7-bit slave and general call address recognition • Firmware support for 10-bit slave address decoding • Ability to inhibit all slave states • Programmable data setup/hold times • Transmit and receive FIFOs (two-byte) to help increase throughput in faster applications es ig ns The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specification, version 1.1, and compatible with the I2C serial bus. 16-bit CRC (CRC0) N ew The cyclic redundancy check (CRC) module performs a CRC using a 16-bit polynomial. CRC0 accepts a stream of 8-bit data and posts the 16-bit result to an internal register. In addition to using the CRC block for data manipulation, hardware can automatically CRC the flash contents of the device. fo r The CRC module is designed to provide hardware calculations for flash memory verification and communications protocols. The CRC module supports the standard CCITT-16 16-bit polynomial (0x1021), and includes the following features: • Support for CCITT-16 polynomial • Byte-level bit reversal • Automatic CRC of flash contents on one or more 256-byte blocks • Initial seed selection of 0x0000 or 0xFFFF m en de d Configurable Logic Units (CLU0, CLU1, CLU2, and CLU3) The Configurable Logic block consists of multiple Configurable Logic Units (CLUs). CLUs are flexible logic functions which may be used for a variety of digital functions, such as replacing system glue logic, aiding in the generation of special waveforms, or synchronizing system event triggers. N ot R ec om • Four configurable logic units (CLUs), with direct-pin and internal logic connections • Each unit supports 256 different combinatorial logic functions (AND, OR, XOR, muxing, etc.) and includes a clocked flip-flop for synchronous operations • Units may be operated synchronously or asynchronously • May be cascaded together to perform more complicated logic functions • Can operate in conjunction with serial peripherals such as UART and SPI or timing peripherals such as timers and PCA channels • Can be used to synchronize and trigger multiple on-chip resources (ADC, Timers, etc.) • Asynchronous output may be used to wake from low-power states silabs.com | Building a more connected world. Rev. 1.1 | 11 EFM8UB3 Data Sheet System Overview 3.7 Analog 12-Bit Analog-to-Digital Converter (ADC0) • • • • D • • Up to 16 external inputs. Single-ended 12-bit and 10-bit modes. Supports an output update rate of 200 ksps samples per second in 12-bit mode or 800 ksps samples per second in 10-bit mode. Operation in low power modes at lower conversion speeds. Asynchronous hardware conversion trigger, selectable between software, external I/O, internal timer sources, and configurable logic (CLU) sources. Output data window comparator allows automatic range checking. Support for burst mode, which produces one set of accumulated data per conversion-start trigger with programmable power-on settling and tracking time. Conversion complete and window compare interrupts supported. Flexible output data formatting. Includes an internal fast-settling reference with two levels (1.65 V and 2.4 V) and support for external reference and signal ground. Integrated temperature sensor. N ew • • • • • es ig ns The ADC is a successive-approximation-register (SAR) ADC with 12-, 10-, and 8-bit modes, integrated track-and hold and a programmable window detector. The ADC is fully configurable under software control via several registers. The ADC may be configured to measure different signals using the analog multiplexer. The voltage reference for the ADC is selectable between internal and external reference sources. Low Current Comparators (CMP0, CMP1) fo r Analog comparators are used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is higher. External input connections to device I/O pins and internal connections are available through separate multiplexers on the positive and negative inputs. Hysteresis, response time, and current consumption may be programmed to suit the specific needs of the application. N ot R ec om m en de d The comparator includes the following features: • Up to 8 (CMP0) or 8 (CMP1) external positive inputs • Up to 8 (CMP0) or 8 (CMP1) external negative inputs • Additional input options: • Internal connection to LDO output • Direct connection to GND • Direct connection to VDD • Dedicated 6-bit reference DAC • Synchronous and asynchronous outputs can be routed to pins via crossbar • Programmable hysteresis between 0 and ±20 mV • Programmable response time • Interrupts generated on rising, falling, or both edges • PWM output kill feature silabs.com | Building a more connected world. Rev. 1.1 | 12 EFM8UB3 Data Sheet System Overview 3.8 Reset Sources es ig ns Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: • The core halts program execution. • Module registers are initialized to their defined reset values unless the bits reset only with a power-on reset. • External port pins are forced to a known state. • Interrupts and timers are disabled. All registers are reset to the predefined values noted in the register descriptions unless the bits only reset with a power-on reset. The contents of RAM are unaffected during a reset; any previously stored data is preserved as long as power is not lost. The Port I/O latches are reset to 1 in open-drain mode. Weak pullups are enabled during and after the reset. For Supply Monitor and power-on resets, the RSTb pin is driven low until the device exits the reset state. On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to an internal oscillator. The Watchdog Timer is enabled, and program execution begins at location 0x0000. N ew D Reset sources on the device include: • Power-on reset • External reset pin • Comparator reset • Software-triggered reset • Supply monitor reset (monitors VDD supply) • Watchdog timer reset • Missing clock detector reset • Flash error reset • USB reset fo r 3.9 Debugging N ot R ec om m en de d The EFM8UB3 devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow flash programming and in-system debugging with the production part installed in the end application. The C2 interface uses a clock signal (C2CK) and a bi-directional C2 data signal (C2D) to transfer information between the device and a host system. See the C2 Interface Specification for details on the C2 protocol. silabs.com | Building a more connected world. Rev. 1.1 | 13 EFM8UB3 Data Sheet System Overview 3.10 Bootloader All devices come pre-programmed with a USB bootloader. This bootloader resides in the code security page and last pages of code flash; it can be erased if it is not needed. The byte before the Lock Byte is the Bootloader Signature Byte. Setting this byte to a value of 0xA5 indicates the presence of the bootloader in the system. Any other value in this location indicates that the bootloader is not present in flash. es ig ns When a bootloader is present, the device will jump to the bootloader vector after any reset, allowing the bootloader to run. The bootloader then determines if the device should stay in bootload mode or jump to the reset vector located at 0x0000. When the bootloader is not present, the device will jump to the reset vector of 0x0000 after any reset. More information about the bootloader protocol and usage can be found in AN945: EFM8 Factory Bootloader User Guide. Application notes can be found on the Silicon Labs website (www.silabs.com/8bit-appnotes) or within Simplicity Studio in the [Documentation] area. 0xFFFF D 0xFFFE 64 Bytes 0xFFC0 0xFFFF Memory Lock Read-Only Read-Only Reserved N ew 64 Bytes 0xFBFE Bootloader Signature Byte 0xFBFD Security Page 512 Bytes m en de d 0xFA00 fo r Lock Byte Bootloader 128-bit UUID 0xFBFF 0xFFD0 0xFFCF 0xFFC0 Bootloader Vector 0x9DFF om 0x9A00 Bootloader Reserved 40 KB Flash ec (79 x 512 Byte pages) N ot R 0x0000 Reset Vector Figure 3.2. Flash Memory Map with Bootloader—40 KB Devices Table 3.2. Summary of Pins for Bootloader Communication Bootloader Pins for Bootload Communication USB VBUS D+ D- silabs.com | Building a more connected world. Rev. 1.1 | 14 EFM8UB3 Data Sheet System Overview Table 3.3. Summary of Pins for Bootload Mode Entry Pin for Bootload Mode Entry QFN24 P2.0 / C2D QSOP24 P2.0 / C2D QFN20 P2.0 / C2D N ot R ec om m en de d fo r N ew D es ig ns Device Package silabs.com | Building a more connected world. Rev. 1.1 | 15 EFM8UB3 Data Sheet Electrical Specifications 4. Electrical Specifications 4.1 Electrical Characteristics Table 4.1. Recommended Operating Conditions Parameter Symbol Operating Supply Voltage on VDD Test Condition Min VDD 2.3 1 VIO 1.71 Operating Supply Voltage on VIO 3, 4 Operating Supply Voltage on VRE- VREGIN GIN 1 System Clock Frequency fSYSCLK Operating Ambient Temperature TA Max Unit — 3.6 V VDD V — N ew 1 Typ D 4.1.1 Recommended Operating Conditions es ig ns All electrical parameters in all tables are specified under the conditions listed in 4.1.1 Recommended Operating Conditions, unless stated otherwise. 3.0 1 — 5.5 V 0 — 48 MHz -40 — 85 °C m en de d fo r Note: 1. Standard USB compliance tests require 3.0 V on VDD for compliant operation. If using the internal regulator to supply this voltage on VDD, the minimum regulator input voltage is 3.7 V. 2. All voltages with respect to GND. 3. On devices without a VIO pin, VIO = VDD. N ot R ec om 4. GPIO levels are undefined whenever VIO is less than 1 V. silabs.com | Building a more connected world. Rev. 1.1 | 16 EFM8UB3 Data Sheet Electrical Specifications 4.1.2 Power Consumption Table 4.2. Power Consumption Parameter Symbol Test Condition Min Typ Max Unit Suspend Mode-Core halted and high frequency clocks stopped, Supply monitor off. IDD Snooze Mode-Core halted and high frequency clocks stopped. Regulator in low-power state, Supply monitor off. IDD 9.6 10.5 mA 4.6 5.3 mA 616 — μA 131 — μA 7.1 7.8 mA — D IDD — FSYSCLK = 24.5 MHz (HFOSC0) 2 — FSYSCLK = 1.53 MHz (HFOSC0) 2 — FSYSCLK = 80 kHz 3 — FSYSCLK = 48 MHz (HFOSC1) 2 — FSYSCLK = 24.5 MHz (HFOSC0) 2 3.4 3.9 mA FSYSCLK = 1.53 MHz (HFOSC0) 2 — 550 — μA FSYSCLK = 80 kHz 3 — 139 — μA — 125 — μA — 120 — μA — 25 — μA — 20 — μA LFO Running LFO Stopped LFO Running m en de d LFO Stopped fo r Idle Mode-Core halted with peripherals running FSYSCLK = 48 MHz (HFOSC1) 2 N ew Normal Mode-Full speed with code IDD executing from flash es ig ns Digital Core Supply Current Stop Mode—Core halted and all clocks stopped,Internal LDO On, Supply monitor off. IDD — 120 — μA Shutdown Mode—Core halted and all clocks stopped,Internal LDO Off, Supply monitor off. IDD — 0.35 — μA — 122 — μA — 910 — μA — 4.2 — μA Analog Peripheral Supply Currents IHFOSC0 om High-Frequency Oscillator 0 ec High-Frequency Oscillator 1 ILFOSC TA = 25 °C Operating at 48 MHz, TA = 25 °C Operating at 80 kHz, TA = 25 °C N ot R Low-Frequency Oscillator IHFOSC1 Operating at 24.5 MHz, silabs.com | Building a more connected world. Rev. 1.1 | 17 EFM8UB3 Data Sheet Parameter ADC0 Always-on 4 Symbol Test Condition IADC 800 ksps, 10-bit conversions or Min Typ Max Unit — 850 1085 μA — es ig ns Electrical Specifications 200 ksps, 12-bit conversions Normal bias settings 250 ksps, 10-bit conversions or 62.5 ksps 12-bit conversions Low power bias settings VDD = 3.0 V ADC0 Burst Mode, 10-bit single conversions, internal reference, Low power bias settings IADC IADC 200 ksps, VDD = 3.0 V — 100 ksps, VDD = 3.0 V — 10 ksps, VDD = 3.0 V — μA 193 — μA 20 — μA μA — 250 — μA — 25.5 — μA — 520 — μA 50 ksps, VDD = 3.0 V — 260 — μA 10 ksps, VDD = 3.0 V — 53 — μA 100 ksps, VDD = 3.0 V, — 970 — μA — 425 — μA — 86 — μA Normal Power Mode — 690 765 μA Low Power Mode — 166 195 μA — 68 110 μA CPMD = 11 — 0.5 — μA CPMD = 10 — 3 — μA CPMD = 01 — 9.1 — μA CPMD = 00 — 24.2 — μA 100 ksps, VDD = 3.0 V fo r IADC — — m en de d ADC0 Burst Mode, 12-bit single conversions, internal reference 385 495 100 ksps, VDD = 3.0 V IADC μA — 200 ksps, VDD = 3.0 V 10 ksps, VDD = 3.0 V ADC0 Burst Mode, 12-bit single conversions, external reference 545 N ew ADC0 Burst Mode, 10-bit single conversions, external reference 420 D VDD = 3.0 V Normal bias 50 ksps, VDD = 3.0 V, Low power bias 10 ksps, VDD = 3.0 V, Low power bias IVREFFS Temperature Sensor ITSENSE ec om Internal ADC0 Reference, Alwayson 5 ICMP N ot R Comparator 0 (CMP0, CMP1) Comparator Reference6 ICPREF — 25.3 — μA Voltage Supply Monitor (VMON0) IVMON — 14 20 μA silabs.com | Building a more connected world. Rev. 1.1 | 18 EFM8UB3 Data Sheet Electrical Specifications Parameter 5V Regulator Symbol Test Condition IVREG Normal Mode Min Typ Max Unit — 260 375 μA — 67 123 μA (SUSEN = 0, BIASENB = 0) Suspend Mode — (BIASENB = 1) Disabled — (BIASENB = 1, REG1ENB = 1) IUSB Low Energy Mode, 64 byte 1ms IN Interrupt transfers — Low Energy Mode, 64 byte 1ms OUT Interrupt transfers — 16 μA 2.5 — nA 850 — μA — μA — μA 250 N ew USB (USB0) Full-Speed 1.8 D Bias Disabled es ig ns (SUSEN = 1, BIASENB = 0) Low Energy Mode, Idle (SOF only) — 50 m en de d fo r Note: 1. Currents are additive. For example, where IDD is specified and the mode is not mutually exclusive, enabling the functions increases supply current by the specified amount. 2. Includes supply current from internal LDO regulator, supply monitor, and High Frequency Oscillator. 3. Includes supply current from internal LDO regulator, supply monitor, and Low Frequency Oscillator. 4. ADC0 always-on power excludes internal reference supply current. 5. The internal reference is enabled as-needed when operating the ADC in burst mode to save power. 6. This value is the current sourced from the pin or supply selected as the full-scale reference to the comparator DAC. 4.1.3 Reset and Supply Monitor Table 4.3. Reset and Supply Monitor Parameter Power-On Reset (POR) Threshold ec VDD Ramp Time VPOR Min Typ Max Unit 2.16 2.23 2.29 V Rising Voltage on VDD — 1.2 — V Falling Voltage on VDD 0.75 — 1.36 V tRMP Time to VDD > 2.3 V 10 — — μs tPOR Relative to VDD > VPOR 3 10 31 ms Time between release of reset source and code execution — 50 — μs 15 — — μs — 0.625 1.2 ms R Reset Delay from POR Test Condition VVDDM om VDD Supply Monitor Threshold Symbol Reset Delay from non-POR source tRST tRSTL Missing Clock Detector Response Time (final rising edge to reset) tMCD Missing Clock Detector Trigger Frequency FMCD — 7.5 13.5 kHz VDD Supply Monitor Turn-On Time tMON — 2 — μs N ot RST Low Time to Generate Reset silabs.com | Building a more connected world. FSYSCLK >1 MHz Rev. 1.1 | 19 EFM8UB3 Data Sheet Electrical Specifications 4.1.4 Flash Memory Write Time1 , 2 Symbol Test Condition Min Typ Max Units tWRITE One Byte, 19 20 21 μs 5.2 5.35 5.5 ms 5 V Voltage Regulator used 2.7 — 5.5 V 5 V Voltage Regulator bypassed 2.3 — 3.6 V 100k — Cycles 5.5 — µs FSYSCLK = 24.5 MHz tERASE Erase Time1 , 2 One Page, FSYSCLK = 24.5 MHz Endurance (Write/Erase Cycles) NWE CRC Calculation Time tCRC 20k One 256-Byte Block SYSCLK = 48 MHz — N ew VDD Voltage During Programming 3 VPROG es ig ns Parameter D Table 4.4. Flash Memory fo r Note: 1. Does not include sequencing time before and after the write/erase operation, which may be multiple SYSCLK cycles. 2. The internal High-Frequency Oscillator 0 has a programmable output frequency, which is factory programmed to 24.5 MHz. If user firmware adjusts the oscillator speed, it must be between 22 and 25 MHz during any flash write or erase operation. It is recommended to write the HFO0CAL register back to its reset value when writing or erasing flash. 3. Flash can be safely programmed at any voltage above the supply monitor threshold (VVDDM). m en de d 4. Data Retention Information is published in the Quarterly Quality and Reliability Report. 4.1.5 Power Management Timing Table 4.5. Power Management Timing Parameter Idle Mode Wake-up Time tSUS- SYSCLK = HFOSC0 PENDWK CLKDIV = 0x00 tSLEEPWK SYSCLK = HFOSC0 Min Typ Max Units 2 — 3 SYSCLKs — 170 — ns — 12 — µs CLKDIV = 0x00 N ot R ec Snooze Mode Wake-up Time Test Condition tIDLEWK om Suspend Mode Wake-up Time Symbol silabs.com | Building a more connected world. Rev. 1.1 | 20 EFM8UB3 Data Sheet Electrical Specifications 4.1.6 Internal Oscillators Table 4.6. Internal Oscillators Parameter Symbol Test Condition Min Typ Max Unit Oscillator Frequency fHFOSC0 Full Temperature and Supply Range 24 24.5 25 MHz Power Supply Sensitivity PSSHFOS TA = 25 °C — 0.5 — %/V 40 — ppm/°C 47.3 D es ig ns High Frequency Oscillator 0 (24.5 MHz) 48 48.7 MHz — 0.02 — %/V — 45 — ppm/°C 75 80 85 kHz — 0.05 — %/V — 65 — ppm/°C Min Typ Max Unit 0 — 48 MHz tCMOSH 9 — — ns tCMOSL 9 — — ns C0 Temperature Sensitivity TSHFOSC0 VDD = 3.0 V — High Frequency Oscillator 1 (48 MHz) fHFOSC1 Full Temperature and Supply Range Power Supply Sensitivity PSSHFOS TA = 25 °C N ew Oscillator Frequency C1 Temperature Sensitivity TSHFOSC1 VDD = 3.0 V Low Frequency Oscillator (80 kHz) fLFOSC Power Supply Sensitivity PSSLFOSC TA = 25 °C Temperature Sensitivity TSLFOSC VDD = 3.0 V m en de d 4.1.7 External Clock Input Full Temperature and Supply Range fo r Oscillator Frequency Table 4.7. External Clock Input Parameter fCMOS om External Input CMOS Clock Symbol Test Condition Frequency (at EXTCLK pin) ec External Input CMOS Clock High Time N ot R External Input CMOS Clock Low Time silabs.com | Building a more connected world. Rev. 1.1 | 21 EFM8UB3 Data Sheet Electrical Specifications 4.1.8 ADC Table 4.8. ADC Test Condition Nbits 12 Bit Mode Min (High Speed Mode) Throughput Rate fS (Low Power Mode) Tracking Time tTRK Power-On Time tPWR SAR Clock Frequency fSAR 12 Bit Mode — 10 Bit Mode — 12 Bit Mode — 10 Bit Mode — High Speed Mode 230 Low Power Mode 450 High Speed Mode, Reference is 2.4 V internal High Speed Mode, Unit Bits 10 Bits — 200 ksps — 800 ksps — 62.5 ksps — 250 ksps — — ns — — ns N ew fS Max 12 10 Bit Mode Throughput Rate Typ es ig ns Resolution Symbol D Parameter 1.2 — — μs — — 6.25 MHz — — 12.5 MHz — — 4 MHz fo r Reference is not 2.4 V internal Low Power Mode tCNV 10-Bit Conversion, m en de d Conversion Time 1.1 μs SAR Clock = 12.25 MHz, System Clock = 24.5 MHz. Sample/Hold Capacitor Input Pin Capacitance Input Mux Impedance Gain = 1 — 5 — pF Gain = 0.5 — 2.5 — pF CIN — 20 — pF RMUX — 550 — Ω VREF 1 — VDD V Gain = 1 0 — VREF V Gain = 0.5 0 — 2xVREF V — 70 — dB 12 Bit Mode — ±1 ±2.3 LSB 10 Bit Mode — ±0.2 ±0.6 LSB 12 Bit Mode -1 ±0.7 1.9 LSB 10 Bit Mode — ±0.2 ±0.6 LSB 12 Bit Mode, VREF = 1.65 V -3 0 3 LSB 10 Bit Mode, VREF = 1.65 V -2 0 2 LSB — 0.004 — LSB/°C om Voltage Reference Range CSAR ec Input Voltage Range 1 Power Supply Rejection Ratio VIN PSRRADC R DC Performance N ot Integral Nonlinearity INL Differential Nonlinearity (Guaranteed Monotonic) DNL Offset Error EOFF Offset Temperature Coefficient TCOFF silabs.com | Building a more connected world. Rev. 1.1 | 22 EFM8UB3 Data Sheet Electrical Specifications Parameter Slope Error Symbol Test Condition Min Typ Max Unit EM 12 Bit Mode — ±0.02 ±0.1 % 10 Bit Mode — ±0.06 ±0.24 % — dB Dynamic Performance 10 kHz Sine Wave Input 1dB below full scale, Max throughput, using AGND pin Signal-to-Noise Plus Distortion SNDR Total Harmonic Distortion (Up to 5th Harmonic) THD Spurious-Free Dynamic Range SFDR 12 Bit Mode 61 10 Bit Mode 53 12 Bit Mode 61 10 Bit Mode 53 12 Bit Mode — 10 Bit Mode — 12 Bit Mode — 10 Bit Mode — 61 — dB 66 — dB 61 — dB 76 — dB 73 — dB -80 — dB -76 — dB N ew Note: 1. Absolute input pin voltage is limited by the VDD supply. 66 es ig ns SNR D Signal-to-Noise fo r 4.1.9 Voltage Reference Table 4.9. Voltage Reference Symbol Test Condition Min Typ Max Unit VREFFS 1.65 V Setting 1.62 1.65 1.68 V 2.4 V Setting, VDD > 2.6 V 2.34 2.4 2.45 V TCREFFS — 50 — ppm/°C tREFFS — — 1.5 μs PSRRREF — 400 — ppm/V — 8 — μA m en de d Parameter Internal Fast Settling Reference Output Voltage (Full Temperature and Supply Range) Temperature Coefficient Turn-on Time om Power Supply Rejection FS External Reference IEXTREF Sample Rate = 800 ksps; VREF = 3.0 V N ot R ec Input Current silabs.com | Building a more connected world. Rev. 1.1 | 23 EFM8UB3 Data Sheet Electrical Specifications 4.1.10 Temperature Sensor Parameter Min Typ Max Unit TA = 0 °C — 757 — mV TA = 0 °C — es ig ns Table 4.10. Temperature Sensor Symbol Test Condition Offset VOFF Offset Error 1 EOFF Slope M Slope Error 1 EM 17 — mV — 2.85 — mV/°C — 70 — μV/° 0.5 — °C 1.8 — μs — Turn-on Time — D Linearity N ew Note: 1. Represents one standard deviation from the mean. 4.1.11 5 V Voltage Regulator Parameter Output Voltage on VDD 2 Output Current 2 Dropout Voltage Symbol Test Condition Min Typ Max Unit VREGIN USB in use 3.7 — 5.5 V USB not in use 3.0 — 5.5 V Regulation range (VREGIN ≥ 4.1V) 3.1 3.4 3.6 V Dropout range (VREGIN < 4.1V) — VREGIN – VDROPOUT — V IREGOUT — — 100 mA VDROPOUT Output Current = 100 mA — — 0.7 V m en de d Input Voltage Range 1 fo r Table 4.11. 5V Voltage Regulator VREGOUT ec om Note: 1. Input range to meet the Output Voltage on VDD specification. If the 5 V voltage regulator is not used, VREGIN should be tied to VDD. 2. Output current is total regulator output, including any current required by the device. N ot R 4.1.12 1.8 V Internal LDO Voltage Regulator Parameter Output Voltage Table 4.12. 1.8V Internal LDO Voltage Regulator Symbol VOUT_1.8V silabs.com | Building a more connected world. Test Condition Min Typ Max Unit 1.77 1.84 1.92 V Rev. 1.1 | 24 EFM8UB3 Data Sheet Electrical Specifications 4.1.13 Comparators Typ Max Unit +100 mV Differential, VCM = 1.65 V — 250 — ns -100 mV Differential, VCM = 1.65 V — Response Time, CPMD = 11 (Low- tRESP3 est Power) +100 mV Differential, VCM = 1.65 V Positive Hysteresis Response Time, CPMD = 00 (Highest Speed) Symbol Test Condition tRESP0 HYSCP+ Mode 0 (CPMD = 00) Negative Hysteresis HYSCP- 213 — ns — 1.06 — μs -100 mV Differential, VCM = 1.65 V — 3.4 — μs CPHYP = 00 — 0.3 — mV CPHYP = 01 — 8.55 — mV CPHYP = 10 — 17.1 — mV CPHYP = 11 — 33.6 — mV N ew Parameter D Min es ig ns Table 4.13. Comparators CPHYN = 00 — -0.3 — mV — -8.55 — mV — -17.1 — mV — -34.2 — mV — 1.2 — mV — 4.9 — mV — 10.4 — mV CPHYP = 11 — 20.8 — mV CPHYN = 00 — -1.2 — mV CPHYN = 01 — -4.9 — mV CPHYN = 10 — -10 — mV CPHYN = 11 — -20.8 — mV -0.25 — VDD+0.25 V VDD V CPHYN = 01 Mode 0 (CPMD = 00) CPHYN = 10 Positive Hysteresis HYSCP+ CPHYP = 00 CPHYP = 01 Mode 3 (CPMD = 11) Negative Hysteresis Mode 3 (CPMD = 11) HYSCP- VIN om Input Range (CP+ or CP-) m en de d CPHYP = 10 fo r CPHYN = 11 Direct comparator input Reference DAC input 1.2 Nbits Reference DAC Input Impedance RCPREF — 2.75 — MΩ Input Pin Capacitance CCP — 7.5 — pF Common-Mode Rejection Ratio CMRRCP — 68.5 — dB Power Supply Rejection Ratio PSRRCP — 65 — dB Input Offset Voltage VOFF -11 -1.8 10 mV Input Offset Tempco TCOFF — 3.5 — μV/° N ot R ec Reference DAC Resolution silabs.com | Building a more connected world. 6 TA = 25 °C bits Rev. 1.1 | 25 EFM8UB3 Data Sheet Electrical Specifications 4.1.14 Configurable Logic Table 4.14. Configurable Logic Test Condition Propagation Delay through LUT tDLY_LUT Through single CLU Min Typ Max Unit — — 38.7 ns Using an external pin Through single CLU — Using an internal connection Propagation Delay through D flipflop clock tDLY_DFF Through single CLU — Using an external pin Through single CLU — Clocking Frequency FCLK 1 or 2 CLUs Cascaded 5.0 ns — 38.7 ns 1.4 5.6 ns — — 48 MHz — — 48 MHz N ot R ec om m en de d fo r 3 or 4 CLUs Cascaded 1.6 N ew Using an internal connection es ig ns Symbol D Parameter silabs.com | Building a more connected world. Rev. 1.1 | 26 EFM8UB3 Data Sheet Electrical Specifications 4.1.15 Port I/O Table 4.15. Port I/O Output High Voltage (Low Drive) Output Low Voltage (Low Drive) Input High Voltage VOH VOL VOH VOL Min Typ Max Unit IOH = -7 mA, VIO ≥ 3.0 V VIO - 0.7 — — V IOH = -3.3 mA, 2.3 V ≤ VIO < 3.0 V VIO x 0.8 IOL = 13.5 mA, VIO ≥ 3.0 V — IOL = 7 mA, 2.3 V ≤ VIO < 3.0 V — — V — 0.6 V — VIO x 0.2 V — — V — — V — 0.6 V — VIO x 0.2 V — — V — 0.3 x V VIO - 0.7 IOH = -2.25 mA, 2.3 V ≤ VIO < 3.0 V VIO x 0.8 — IOL = 3.5 mA, 2.3 V ≤ VIO < 3.0 V — VIH 0.7 x (all port pins including VBUS) VIO VIL — (all port pins including VBUS) Pin Capacitance CIO Weak Pull-Up Current IPU m en de d VIO = 3.6 fo r Input Low Voltage (VIN = 0 V) — IOH = -4.75 mA, VIO ≥ 3.0 V IOL = 6.5 mA, VIO ≥ 3.0 V es ig ns Output Low Voltage (High Drive) Test Condition D Output High Voltage (High Drive) Symbol N ew Parameter Input Leakage (Pullups off or Analog) ILK GND < VIN < VIO Input Leakage Current with VIN above VIO ILK VIO < VIN < VIO+2.0 V VIO — 7 — pF -30 -20 -10 μA -1.1 — 1.1 μA 0 5 60 μA N ot R ec om Note: 1. On devices without a VIO pin, VIO = VDD. silabs.com | Building a more connected world. Rev. 1.1 | 27 EFM8UB3 Data Sheet Electrical Specifications 4.1.16 USB Transceiver Symbol Test Condition Min Typ Output High Voltage VOH VDD ≥3.0V 2.8 Output Low Voltage VOL VDD ≥3.0V — Output Crossover Point VCRS Output Impedance ZDRV es ig ns Table 4.16. USB Transceiver Parameter Max Unit Pull-up Resistance RPU 1.3 Driving High 28 Driving Low 28 Full Speed (D+ Pull-up) 1.425 Output Rise Time TR Low Speed Full Speed Output Fall Time TF Low Speed Differential Input VDI m en de d Sensitivity | (D+) - (D-) | fo r Full Speed Receiver Differential Input Common Mode Range VCM Input Leakage Current IL — V — 0.8 V — 2.0 V 36 44 Ω 36 44 1.575 kΩ 1.5 N ew Low Speed (D- Pull-up) — D Transmitter Pullups Disabled 75 — 300 ns 4 — 20 ns 75 — 300 ns 4 — 20 ns 0.2 — — V 0.8 — 2.5 V — 3.3 V m en de d fo r VIO < 3.3 V N ew D Ambient Temperature Under Bias N ot R ec om Note: 1. Exposure to maximum rating conditions for extended periods may affect device reliability. 2. On devices without a VIO pin, VIO = VDD. silabs.com | Building a more connected world. Rev. 1.1 | 32 EFM8UB3 Data Sheet Typical Connection Diagrams 5. Typical Connection Diagrams 5.1 Power es ig ns The figure below shows a typical connection diagram for the power pins of the EFM8UB3 devices when the internal regulator used and USB is connected (bus-powered). EFM8UB3 Device 3.4 V (out) VREGIN VDD N ew 4.7 µF and 0.1 µF bypass capacitors required for each power pin placed as close to the pins as possible. Voltage Regulator D USB 5 V (in) fo r GND N ot R ec om m en de d Figure 5.1. Connection Diagram with Voltage Regulator Used and USB Connected (Bus-Powered) silabs.com | Building a more connected world. Rev. 1.1 | 33 EFM8UB3 Data Sheet Typical Connection Diagrams The figure below shows a typical connection diagram for the power pins of the EFM8UB3 devices when the internal regulator used and USB is connected (self-powered). EFM8UB3 Device 3.7-5.25 V (in) VREGIN VDD es ig ns 3.4 V (out) N ew D 4.7 µF and 0.1 µF bypass capacitors required for each power pin placed as close to the pins as possible. Voltage Regulator GND Figure 5.2. Connection Diagram with Voltage Regulator Used and USB Connected (Self-Powered) m en de d fo r The figure below shows a typical connection diagram for the power pins of the EFM8UB3 devices when the internal 5 V-to-3.3 V regulator is not used. EFM8UB3 Device 2.3-3.6 V (in) VDD GND Figure 5.3. Connection Diagram with Voltage Regulator Not Used (Self-Powered) N ot R ec om 4.7 µF and 0.1 µF bypass capacitors required for each power pin placed as close to the pins as possible. VREGIN Voltage Regulator silabs.com | Building a more connected world. Rev. 1.1 | 34 EFM8UB3 Data Sheet Typical Connection Diagrams 5.2 USB Figure 5.4 Bus-Powered Connection Diagram for USB Pins on page 35 shows a typical connection bus-powered diagram for the USB pins of the EFM8UB3 devices including ESD protection diodes on the USB pins. Bypass capacitors on VREGIN and VDD are required as discussed in 5.1 Power, but are not shown in the figure. es ig ns Note: The VBUS pin is not required as a sensing pin for proper operation in bus-powered configurations. Rather than using VBUS as a sensing pin, it is recommended to use the VBUS pin only as a GPIO by clearing VBUSEN and VBUSIE to 0 in the USB0CF register. To do this using the USB stack, set the device to use bus-powered mode. EFM8UB3 Device VBUS VREGIN D+ D+ D- N ew D- USB D USB Connector Signal GND fo r SP0503BAHT or equivalent USB ESD protection diodes (Recommended) m en de d GND N ot R ec om Figure 5.4. Bus-Powered Connection Diagram for USB Pins silabs.com | Building a more connected world. Rev. 1.1 | 35 EFM8UB3 Data Sheet Typical Connection Diagrams Figure 5.5 Self-Powered Connection Diagram for USB Pins on page 36 shows a typical connection self-powered diagram for the USB pins of the EFM8UB3 devices including ESD protection diodes on the USB pins. es ig ns Note: There are two relevant restrictions on the VBUS pin voltage in this self-powered configuration. The first is the absolute maximum voltage on the VBUS pin, which is defined as V IO + 2.5 V in Table 4.20 Absolute Maximum Ratings on page 32. The second is the Input High Voltage (VIH) for VBUS to detect when the device is connected to a bus, which is defined as 0.7 x VIO in 4.1.15 Port I/O. For selfpowered systems where VDD and VIO may be unpowered when VBUS is connected to 4.4 V to 5.5 V, a resistor divider (or functionallyequivalent circuit) on VBUS is required to meet these specifications and ensure reliable device operation. In this case, the current limitation of the resistor divider prevents overstress on the pin, even though the VIO + 2.5 V specification is not strictly met. 22.1 kΩ EFM8UB3 Device VBUS USB Connector P2.1 / VBUS D+ D 47.5 kΩ N ew D+ D- USB D- Signal GND m en de d fo r SP0503BAHT or equivalent USB ESD protection diodes (Recommended) GND N ot R ec om Figure 5.5. Self-Powered Connection Diagram for USB Pins silabs.com | Building a more connected world. Rev. 1.1 | 36 EFM8UB3 Data Sheet Typical Connection Diagrams 5.3 Debug The diagram below shows a typical connection diagram for the debug connections pins. The pin sharing resistors are only required if the functionality on the C2D (a GPIO pin) and the C2CK (RSTb) is routed to external circuitry. For example, if the RSTb pin is connected to an external switch with debouncing filter or if the GPIO sharing with the C2D pin is connected to an external circuit, the pin sharing resistors and connections to the debug adapter must be placed on the hardware. Otherwise, these components and connections can be omitted. es ig ns For more information on debug connections, see the example schematics and information available in AN124: Pin Sharing Techniques for the C2 Interface. Application notes can be found on the Silicon Labs website (http://www.silabs.com/8bit-appnotes) or in Simplicity Studio. VDD EFM8UB3 Device External System C2CK 1k 1k D 1k N ew (if pin sharing) (if pin sharing) C2D 1k fo r GND 1k m en de d Debug Adapter Figure 5.6. Debug Connection Diagram 5.4 Other Connections N ot R ec om Other components or connections may be required to meet the system-level requirements. Application Note AN203: 8-bit MCU Printed Circuit Board Design Notes contains detailed information on these connections. Application Notes can be accessed on the Silicon Labs website (www.silabs.com/8bit-appnotes). silabs.com | Building a more connected world. Rev. 1.1 | 37 EFM8UB3 Data Sheet Pin Definitions 6. Pin Definitions es ig ns 6.1 EFM8UB3x-QSOP24 Pin Definitions 1 24 P0.3 P0.1 2 23 P0.4 P0.0 3 22 P0.5 GND 4 21 D+ 5 20 P0.7 D- 6 19 P1.0 VIO 7 18 P1.1 VDD 8 17 P1.2 VREGIN 9 16 P1.3 P2.1 / VBUS 10 15 P1.4 RSTb / C2CK 11 14 P1.5 P2.0 / C2D 12 13 P1.6 D P0.2 N ew P0.6 24 pin QSOP Figure 6.1. EFM8UB3x-QSOP24 Pinout N ot R ec om m en de d fo r (Top View) silabs.com | Building a more connected world. Rev. 1.1 | 38 EFM8UB3 Data Sheet Pin Definitions Table 6.1. Pin Definitions for EFM8UB3x-QSOP24 Description Crossbar Capability Additional Digital Functions Analog Functions P0.2 Multifunction I/O Yes P0MAT.2 ADC0.2 Number 1 INT0.2 INT1.2 CLU2B.7 CLU3B.6 CLU0OUT 2 P0.1 Multifunction I/O Yes P0MAT.1 CMP0P.2 CMP0N.2 N ew INT0.1 es ig ns Pin Name ADC0.1 D Pin CMP0P.1 INT1.1 CMP0N.1 CLU0A.6 AGND CLU3A.7 P0.0 Multifunction I/O Yes P0MAT.0 ADC0.0 INT0.0 CMP0P.0 INT1.0 CMP0N.0 4 GND 5 D+ 6 D- 7 VIO 8 VDD m en de d fo r 3 VREF Ground ADC0.19 USB Data Positive ADC0.28 USB Data Negative ADC0.29 I/O Power Input Supply Power Input / ADC0.18 5V Regulator Output VREGIN 10 P2.1 ec RSTb / R 11 13 Multifunction I/O VBUS ADC0.24 CMP1P.13 CMP1N.13 Active-low Reset / C2CK C2 Debug Clock P2.0 / Multifunction I/O / C2D C2 Debug Data P1.6 Multifunction I/O N ot 12 5V Regulator Input om 9 Yes CLU0A.7 ADC0.14 CMP1P.6 CMP1N.6 silabs.com | Building a more connected world. Rev. 1.1 | 39 EFM8UB3 Data Sheet Pin Definitions Pin Pin Name Description Crossbar Capability P1.5 Multifunction I/O Yes Number 12 Additional Digital Functions Analog Functions ADC0.13 CMP1P.5 15 P1.4 Multifunction I/O Yes P1MAT.4 es ig ns CMP1N.5 ADC0.12 CMP1P.4 CMP1N.4 16 P1.3 Multifunction I/O Yes P1MAT.3 ADC0.11 CMP1P.3 20 P1.0 Multifunction I/O P0.7 P0.6 Yes Yes Multifunction I/O Multifunction I/O Yes Yes P0.5 P1MAT.1 ADC0.10 CMP1P.2 CMP1N.2 ADC0.9 CMP1P.1 CMP1N.1 P1MAT.0 ADC0.8 CLU0B.6 CMP1P.0 CLU2A.7 CMP1N.0 CLU3OUT P0MAT.7 ADC0.7 INT0.7 CMP0P.7 INT1.7 CMP0N.7 CLU1A.7 CLU3A.6 P0MAT.6 ADC0.6 CNVSTR CMP0P.6 INT0.6 CMP0N.6 INT1.6 R N ot 22 P1MAT.2 N ew Multifunction I/O ec 21 P1.1 Yes fo r 19 Multifunction I/O m en de d 18 P1.2 om 17 D CMP1N.3 CLU1B.6 CLU2OUT Multifunction I/O Yes P0MAT.5 ADC0.5 INT0.5 CMP0P.5 INT1.5 CMP0N.5 UART1_RX CLU1B.7 CLU2A.6 silabs.com | Building a more connected world. Rev. 1.1 | 40 EFM8UB3 Data Sheet Pin Definitions Description Crossbar Capability Additional Digital Functions Analog Functions P0.4 Multifunction I/O Yes P0MAT.4 ADC0.4 INT0.4 CMP0P.4 INT1.4 CMP0N.4 Number 23 CLU0B.7 CLU2B.6 CLU1OUT UART1_TX 24 P0.3 Multifunction I/O Yes P0MAT.3 EXTCLK ADC0.3 CMP0P.3 CMP0N.3 N ew INT0.3 es ig ns Pin Name D Pin INT1.3 CLU1A.6 N ot R ec om m en de d fo r CLU3B.7 silabs.com | Building a more connected world. Rev. 1.1 | 41 EFM8UB3 Data Sheet Pin Definitions P0.2 P0.3 P0.4 P0.5 P0.6 23 22 21 20 19 1 18 GND 2 17 D+ 3 D- 4 VIO 5 P0.7 P1.0 D P0.0 es ig ns P0.1 24 6.2 EFM8UB3x-QFN24 Pin Definitions fo r (Top View) 16 P1.1 15 P1.2 14 P1.3 13 P1.4 N ew 24 pin QFN Pin Name 9 10 11 RSTb / C2CK P2.0 / C2D P1.6 8 VREGIN P2.1 / VBUS 7 m en de d om ec R Pin Figure 6.2. EFM8UB3x-QFN24 Pinout Table 6.2. Pin Definitions for EFM8UB3x-QFN24 Description Crossbar Capability Additional Digital Functions Analog Functions Multifunction I/O Yes P0MAT.0 ADC0.0 INT0.0 CMP0P.0 INT1.0 CMP0N.0 N ot Number 1 P0.0 P1.5 6 VDD 12 GND VREF 2 GND Ground silabs.com | Building a more connected world. ADC0.19 Rev. 1.1 | 42 EFM8UB3 Data Sheet Pin Definitions Pin Name Description Crossbar Capability 3 D+ USB Data Positive ADC0.28 4 D- USB Data Negative ADC0.29 5 VIO I/O Power Input 6 VDD Supply Power Input / Number Additional Digital Functions ADC0.18 5V Regulator Output 7 VREGIN 5V Regulator Input 8 P2.1 Multifunction I/O Analog Functions es ig ns Pin VBUS ADC0.24 CMP1P.13 12 13 14 P2.0 / Multifunction I/O / C2D C2 Debug Data P1.6 Multifunction I/O P1.5 Multifunction I/O P1.4 Multifunction I/O P1.3 P1.2 N ew C2 Debug Clock Yes Yes CLU0A.7 Multifunction I/O Multifunction I/O Yes Yes R P1.1 N ot 16 17 P1.0 ADC0.14 CMP1P.6 CMP1N.6 ADC0.13 CMP1P.5 CMP1N.5 P1MAT.4 ADC0.12 CMP1P.4 CMP1N.4 P1MAT.3 ADC0.11 CMP1P.3 CMP1N.3 Yes P1MAT.2 ec 15 C2CK fo r 11 Active-low Reset / m en de d 10 RSTb / om 9 D CMP1N.13 ADC0.10 CMP1P.2 CMP1N.2 Multifunction I/O Yes P1MAT.1 ADC0.9 CMP1P.1 CMP1N.1 Multifunction I/O Yes P1MAT.0 ADC0.8 CLU0B.6 CMP1P.0 CLU2A.7 CMP1N.0 CLU3OUT silabs.com | Building a more connected world. Rev. 1.1 | 43 EFM8UB3 Data Sheet Pin Definitions Description Crossbar Capability Additional Digital Functions Analog Functions P0.7 Multifunction I/O Yes P0MAT.7 ADC0.7 INT0.7 CMP0P.7 INT1.7 CMP0N.7 Number 18 CLU1A.7 CLU3A.6 19 P0.6 Multifunction I/O Yes P0MAT.6 CNVSTR INT0.6 INT1.6 ADC0.6 CMP0P.6 CMP0N.6 N ew CLU1B.6 es ig ns Pin Name D Pin CLU2OUT 20 P0.5 Multifunction I/O Yes P0MAT.5 ADC0.5 INT0.5 CMP0P.5 INT1.5 CMP0N.5 fo r UART1_RX CLU1B.7 P0.3 Multifunction I/O Multifunction I/O N ot R ec 22 P0.4 om 21 m en de d CLU2A.6 silabs.com | Building a more connected world. Yes Yes P0MAT.4 ADC0.4 INT0.4 CMP0P.4 INT1.4 CMP0N.4 CLU0B.7 CLU2B.6 CLU1OUT UART1_TX P0MAT.3 ADC0.3 EXTCLK CMP0P.3 INT0.3 CMP0N.3 INT1.3 CLU1A.6 CLU3B.7 Rev. 1.1 | 44 EFM8UB3 Data Sheet Pin Definitions Description Crossbar Capability Additional Digital Functions Analog Functions P0.2 Multifunction I/O Yes P0MAT.2 ADC0.2 INT0.2 CMP0P.2 INT1.2 CMP0N.2 Number 23 CLU2B.7 CLU3B.6 CLU0OUT 24 P0.1 Multifunction I/O Yes P0MAT.1 INT0.1 INT1.1 ADC0.1 CMP0P.1 CMP0N.1 AGND N ew CLU0A.6 es ig ns Pin Name D Pin CLU3A.7 GND Ground N ot R ec om m en de d fo r Center silabs.com | Building a more connected world. Rev. 1.1 | 45 EFM8UB3 Data Sheet Pin Definitions 2 GND 3 D+ 4 D- 5 GND 6 14 8 9 10 RSTb / C2CK P2.0 / C2D m en de d P2.1 / VBUS 7 (Top View) P0.7 P1.0 N ew 20 pin QFN VREGIN VDD 15 es ig ns P0.5 17 P0.0 P0.6 D P0.4 18 16 fo r P0.3 19 1 P0.2 P0.1 20 6.3 EFM8UB3x-QFN20 13 P1.1 12 GND 11 P1.2 om Figure 6.3. EFM8UB3x-QFN20 Pinout Pin Name Number P0.1 Description Crossbar Capability Additional Digital Functions Analog Functions Multifunction I/O Yes P0MAT.1 ADC0.1 INT0.1 CMP0P.1 INT1.1 CMP0N.1 CLU0A.6 AGND N ot R 1 ec Pin Table 6.3. Pin Definitions for EFM8UB3x-QFN20 silabs.com | Building a more connected world. CLU3A.7 Rev. 1.1 | 46 EFM8UB3 Data Sheet Pin Definitions Pin Pin Name Description Crossbar Capability Additional Digital Functions Analog Functions P0.0 Multifunction I/O Yes P0MAT.0 ADC0.0 INT0.0 CMP0P.0 INT1.0 CMP0N.0 2 es ig ns Number VREF 3 GND Ground 4 D+ USB Data Positive 5 D- USB Data Negative 6 VDD Supply Power Input / ADC0.19 ADC0.28 ADC0.29 ADC0.18 5V Regulator Input 8 P2.1 Multifunction I/O 11 Active-low Reset / C2CK C2 Debug Clock P2.0 / Multifunction I/O / C2D C2 Debug Data P1.2 12 GND 13 P1.1 P1.0 Multifunction I/O Yes Multifunction I/O Multifunction I/O R P0.7 CMP1P.13 CMP1N.13 P1MAT.2 ADC0.10 CMP1P.2 CMP1N.2 Yes Yes P1MAT.1 ADC0.9 CMP1P.1 CMP1N.1 P1MAT.0 ADC0.8 CLU0B.6 CMP1P.0 CLU2A.7 CMP1N.0 CLU3OUT Multifunction I/O N ot 15 ADC0.24 Ground ec 14 m en de d 10 RSTb / om 9 VBUS N ew VREGIN fo r 7 D 5V Regulator Output silabs.com | Building a more connected world. Yes P0MAT.7 ADC0.7 INT0.7 CMP0P.7 INT1.7 CMP0N.7 CLU1A.7 CLU3A.6 Rev. 1.1 | 47 EFM8UB3 Data Sheet Pin Definitions Description Crossbar Capability Additional Digital Functions Analog Functions P0.6 Multifunction I/O Yes P0MAT.6 ADC0.6 CNVSTR CMP0P.6 INT0.6 CMP0N.6 Number 16 INT1.6 CLU1B.6 CLU2OUT 17 P0.5 Multifunction I/O Yes P0MAT.5 INT0.5 INT1.5 ADC0.5 CMP0P.5 N ew UART1_RX es ig ns Pin Name CMP0N.5 D Pin CLU1B.7 CLU2A.6 P0.4 Multifunction I/O Yes P0MAT.4 ADC0.4 INT0.4 CMP0P.4 INT1.4 CMP0N.4 fo r 18 CLU0B.7 P0.3 P0.2 Multifunction I/O N ot R ec 20 Multifunction I/O om 19 m en de d CLU2B.6 Center GND Yes CLU1OUT UART1_TX P0MAT.3 ADC0.3 EXTCLK CMP0P.3 INT0.3 CMP0N.3 INT1.3 CLU1A.6 CLU3B.7 Yes P0MAT.2 ADC0.2 INT0.2 CMP0P.2 INT1.2 CMP0N.2 CLU2B.7 CLU3B.6 CLU0OUT Ground silabs.com | Building a more connected world. Rev. 1.1 | 48 EFM8UB3 Data Sheet QFN24 Package Specifications 7. QFN24 Package Specifications m en de d fo r N ew D es ig ns 7.1 QFN24 Package Dimensions Figure 7.1. QFN24 Package Drawing Table 7.1. QFN24 Package Dimensions Dimension A A1 om b D E E2 R e Typ Max 0.70 0.75 0.80 0.00 — 0.05 0.18 0.25 0.30 4.00 BSC 2.35 ec D2 Min 2.45 2.55 0.50 BSC 4.00 BSC 2.35 2.45 2.55 0.30 0.40 0.50 aaa — — 0.10 bbb — — 0.10 ccc — — 0.08 ddd — — 0.10 N ot L silabs.com | Building a more connected world. Rev. 1.1 | 49 EFM8UB3 Data Sheet QFN24 Package Specifications Dimension Min Typ Max N ot R ec om m en de d fo r N ew D es ig ns Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC Solid State Outline MO-220. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. silabs.com | Building a more connected world. Rev. 1.1 | 50 EFM8UB3 Data Sheet QFN24 Package Specifications 7.2 PCB Land Pattern es i gn C2 s X1 fo r N ew D Y2 Y1 C0.25 m en de d E X2 ec om C1 C1 Table 7.2. PCB Land Pattern Dimensions Min Max 3.90 3.90 N ot C2 R Dimension Figure 7.2. PCB Land Pattern Drawing E 0.50 X1 0.30 X2 2.55 Y1 0.85 Y2 2.55 silabs.com | Building a more connected world. Rev. 1.1 | 51 EFM8UB3 Data Sheet QFN24 Package Specifications Dimension Min Max D es ig ns Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. 3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. 4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. The stencil thickness should be 0.125 mm (5 mils). 6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 7. A 2 x 2 array of 0.9 mm square openings on a 1.2 mm pitch should be used for the center pad. 8. A No-Clean, Type-3 solder paste is recommended. 9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. N ew 7.3 Package Marking m en de d fo r PPPPPPPP TTTTTT YYWW # Figure 7.3. Package Marking N ot R ec om The package marking consists of: • PPPPPPPP – The part number designation. • TTTTTT – A trace or manufacturing code. • YY – The last 2 digits of the assembly year. • WW – The 2-digit workweek when the device was assembled. • # – The device revision (A, B, etc.). silabs.com | Building a more connected world. Rev. 1.1 | 52 EFM8UB3 Data Sheet QSOP24 Package Specifications 8. QSOP24 Package Specifications ec om m en de d fo r N ew D es ig ns 8.1 Package Dimensions Table 8.1. Package Dimensions Min Typ Max — — 1.75 0.10 — 0.25 b 0.20 — 0.30 c 0.10 — 0.25 A N ot A1 R Dimension Figure 8.1. Package Drawing D 8.65 BSC E 6.00 BSC E1 3.90 BSC e 0.635 BSC L silabs.com | Building a more connected world. 0.40 — 1.27 Rev. 1.1 | 53 EFM8UB3 Data Sheet QSOP24 Package Specifications theta Min Typ Max 0º — 8º aaa 0.20 bbb 0.18 ccc 0.10 ddd 0.10 es ig ns Dimension N ot R ec om m en de d fo r N ew D Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MO-137, variation AE. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. silabs.com | Building a more connected world. Rev. 1.1 | 54 EFM8UB3 Data Sheet QSOP24 Package Specifications fo r N ew D es ig ns 8.2 PCB Land Pattern m en de d Figure 8.2. PCB Land Pattern Drawing Table 8.2. PCB Land Pattern Dimensions Dimension C E om X Y Min Max 5.20 5.30 0.635 BSC 0.30 0.40 1.50 1.60 N ot R ec Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This land pattern design is based on the IPC-7351 guidelines. 3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. 4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. The stencil thickness should be 0.125 mm (5 mils). 6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 7. A No-Clean, Type-3 solder paste is recommended. 8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. silabs.com | Building a more connected world. Rev. 1.1 | 55 EFM8UB3 Data Sheet QSOP24 Package Specifications PPPPPPPP # TTTTTTYYWW N ot R ec om m en de d fo r The package marking consists of: • PPPPPPPP – The part number designation. • TTTTTT – A trace or manufacturing code. • YY – The last 2 digits of the assembly year. • WW – The 2-digit workweek when the device was assembled. • # – The device revision (A, B, etc.). N ew Figure 8.3. Package Marking D EFM8 es ig ns 8.3 Package Marking silabs.com | Building a more connected world. Rev. 1.1 | 56 EFM8UB3 Data Sheet QFN20 Package Specifications 9. QFN20 Package Specifications ec om m en de d fo r N ew D es ig ns 9.1 QFN20 Package Dimensions Figure 9.1. QFN20 Package Drawing Table 9.1. QFN20 Package Dimensions Min Typ Max A 0.70 0.75 0.80 0.00 0.02 0.05 A1 R Dimension N ot A3 0.20 REF b 0.18 0.25 0.30 c 0.25 0.30 0.35 D D2 3.00 BSC 1.6 1.70 e 0.50 BSC E 3.00 BSC silabs.com | Building a more connected world. 1.80 Rev. 1.1 | 57 EFM8UB3 Data Sheet QFN20 Package Specifications Dimension Min Typ Max E2 1.60 1.70 1.80 f 2.50 BSC L 0.30 0.40 R 0.09 0.125 aaa 0.15 bbb 0.10 ccc 0.10 ddd 0.05 eee 0.08 fff 0.10 es ig ns 0.25 REF 0.15 D K 0.50 N ot R ec om m en de d fo r N ew Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. The drawing complies with JEDEC MO-220. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. silabs.com | Building a more connected world. Rev. 1.1 | 58 EFM8UB3 Data Sheet QFN20 Package Specifications m en de d fo r N ew D es ig ns 9.2 QFN20 PCB Land Pattern Figure 9.2. QFN20 PCB Land Pattern Drawing Table 9.2. QFN20 PCB Land Pattern Dimensions Dimension Min om C1 C2 E X1 X2 R C4 3.10 3.10 2.50 2.50 ec C3 Max 0.50 0.30 0.25 0.35 1.80 Y1 0.90 N ot X3 Y2 Y3 silabs.com | Building a more connected world. 0.25 0.35 1.80 Rev. 1.1 | 59 EFM8UB3 Data Sheet QFN20 Package Specifications Dimension Min Max D es ig ns Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. 4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. 5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 6. The stencil thickness should be 0.125 mm (5 mils). 7. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 8. A 2 x 2 array of 0.75 mm openings on a 0.95 mm pitch should be used for the center pad to assure proper paste volume. 9. A No-Clean, Type-3 solder paste is recommended. 10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. N ew 9.3 QFN20 Package Marking m en de d fo r PPPP PPPP TTTTTT YYWW # Figure 9.3. QFN20 Package Marking N ot R ec om The package marking consists of: • PPPPPPPP – The part number designation. • TTTTTT – A trace or manufacturing code. • YY – The last 2 digits of the assembly year. • WW – The 2-digit workweek when the device was assembled. • # – The device revision (A, B, etc.). silabs.com | Building a more connected world. Rev. 1.1 | 60 EFM8UB3 Data Sheet Revision History 10. Revision History October 20th, 2017 • Updated the front page diagram to indicate USB and SPI are available in Snooze mode. • Updated the front page and 1. Feature List to refer to two analog comparators. • Corrected the number of I/O mentioned on the front page. • Added "Pre-programmed USB Bootloader" to 1. Feature List. • Updated I/O tolerance range to VIO + 2.5 V in 1. Feature List. • • • • • • • D N ew • fo r • Updated 3.1 Introduction to mention all device documentation. Updated 3.2 Power to remove mention of the I2C Slave peripheral. Added bootloader pinout information to 3.10 Bootloader. Corrected the application note number for AN124: Pin Sharing Techniques for the C2 Interface in 5.3 Debug. Added a note to Table 4.2 Power Consumption on page 17 providing more information about the Comparator Reference specification. Added maximum specifications to 4.1.14 Configurable Logic Propagation Delay through LUT (internal connection) and Propagation Delay through D flip-flop clock (internal connection). Updated 4.1.15 Port I/O to refer to VIO instead of VDD for I/O specifications. Also added a note that VIO = VDD on devices without a VIO pin. Added specifications for 4.1.17 SMBus. Updated 4.3 Absolute Maximum Ratings to correct the GPIO pin associated with VBUS and update the maximum specfications to be relative to VIO, not VDD. Added a VIO specification to 4.3 Absolute Maximum Ratings. Updated text and figures in 5.1 Power to remove mention of the VBUS pin. Updated the title of Figure 5.3 Connection Diagram with Voltage Regulator Not Used (Self-Powered) on page 34 to include "SelfPowered". Updated to show a resistor divider on VBUS in Figure 5.5 Self-Powered Connection Diagram for USB Pins on page 36. Also added two notes regarding VBUS. Updated the revision history format. m en de d • • • • • es ig ns Revision 1.1 Revision 1.0 N ot R ec om July 20th, 2017 • Initial release. silabs.com | Building a more connected world. Rev. 1.1 | 61 es ig ns D N ew fo r One-click access to MCU and wireless tools, documentation, software, source code libraries & more. Available for Windows, Mac and Linux! om IoT Portfolio www.silabs.com/IoT m en de d Simplicity Studio SW/HW www.silabs.com/simplicity Quality www.silabs.com/quality Support and Community community.silabs.com N ot R ec Disclaimer Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. 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