EFR32MG1P132F256IM32-C0R

The single-die solution provides industry-leading energy efficiency, ultra-fast wakeup times, a scalable power amplifier, and no-compromise MCU features. Mighty Gecko applications include: fo r Connected Home Lighting Health and Wellness Metering Building Automation and Security m en de d • • • • • Core / Memory Flash Program Memory Debug Interface DMA Controller D • 12-channel Peripheral Reflex System enabling autonomous interaction of MCU peripherals • Autonomous Hardware Crypto Accelerator and Random Number Generator • Integrated PA with up to 19 dBm (2.4 GHz) or 20 dBm (Sub-GHz) TX power • Robust peripheral set and up to 32 GPIO Energy Management Other High Frequency Crystal Oscillator High Frequency RC Oscillator Voltage Regulator Voltage Monitor CRYPTO Low Frequency RC Oscillator Auxiliary High Frequency RC Oscillator DC-DC Converter Power-On Reset CRC Low Frequency Crystal Oscillator Ultra Low Frequency RC Oscillator Brown-Out Detector FRC DEMOD Frequency Synthesizer To RF Frontend Circuits IFADC I/O Ports Timers and Triggers Analog I/F USART External Interrupts Timer/Counter Protocol Timer ADC Low Energy UARTTM General Purpose I/O Low Energy Timer Watchdog Timer Analog Comparator I2C Pin Reset Pulse Counter Real Time Counter and Calendar IDAC AGC CRC PGA BUFC Serial Interfaces RAC R N ot BALUN 2.4 GHz RF Frontend: LNA, PA, I/Q Mixer • Supports Zigbee, Thread and Bluetooth Low Energy Peripheral Reflex System Radio Transceiver Sub-GHz RF Frontend: LNA, PA, I/Q Mixer • 256 kB of flash and 32 kB of RAM 32-bit bus ec RAM Memory • 32-bit ARM® Cortex®-M4 core with 40 MHz maximum operating frequency • Integrated balun for 2.4 GHz Clock Management Memory Protection Unit om ARM CortexTM M4 processor with DSP extensions and FPU KEY FEATURES N ew The Mighty Gecko multi-protocol family of SoCs is part of the Wireless Gecko portfolio. Mighty Gecko SoCs are ideal for enabling energy-friendly multi-protocol, multi-band networking for IoT devices. es ig ns EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet MOD Pin Wakeup Cryotimer Lowest power mode with peripheral operational: EM0—Active EM1—Sleep silabs.com | Building a more connected world. EM2—Deep Sleep EM3—Stop Copyright © 2022 by Silicon Laboratories EM4—Hibernate EM4—Shutoff Rev. 1.5 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Feature List 1. Feature List The EFR32MG1 highlighted features are listed below. fo r N ew D es ig ns • Wide selection of MCU peripherals • 12-bit 1 Msps SAR Analog to Digital Converter (ADC) • 2 × Analog Comparator (ACMP) • Digital to Analog Current Converter (IDAC) • Up to 32 pins connected to analog channels (APORT) shared between analog peripherals • Up to 32 General Purpose I/O pins with output state retention and asynchronous interrupts • 8 Channel DMA Controller • 12 Channel Peripheral Reflex System (PRS) • 2 × 16-bit Timer/Counter • 3 or 4 Compare/Capture/PWM channels • 32-bit Real Time Counter and Calendar • 16-bit Low Energy Timer for waveform generation • 32-bit Ultra Low Energy Timer/Counter for periodic wake-up from any Energy Mode • 16-bit Pulse Counter with asynchronous operation • Watchdog Timer with dedicated RC oscillator • 2 × Universal Synchronous/Asynchronous Receiver/Transmitter (UART/SPI/SmartCard (ISO 7816)/IrDA/I2S) • Low Energy UART (LEUART™) • • I2C interface with SMBus support and address recognition in EM3 Stop Wide Operating Range • 1.85 V to 3.8 V single power supply • Integrated DC-DC, down to 1.8 V output with up to 200 mA load current for system • Standard (-40 °C to 85 °C) and Extended (-40 °C to 125 °C) temperature grades available Support for Internet Security • General Purpose CRC • Random Number Generator • Hardware Cryptographic Acceleration for AES 128/256, SHA-1, SHA-2 (SHA-224 and SHA-256) and ECC QFN32 5x5 mm Package QFN48 7x7 mm Package om m en de d • Low Power Wireless System-on-Chip • High Performance 32-bit 40 MHz ARM Cortex®-M4 with DSP instruction and floating-point unit for efficient signal processing • 256 kB flash program memory • 32 kB RAM data memory • 2.4 GHz and Sub-GHz radio operation • Transmit power: • 2.4 GHz radio: Up to 19 dBm • Sub-GHz radio: Up to 20 dBm • Low Energy Consumption • 9.8 mA RX current at 250 kbps, DSSS-OQPSK, 2.4 GHz • 8.7 mA RX current at 1 Mbps, GFSK, 2.4 GHz • 7.6 mA RX current at 38.4 kbps, GFSK, 169 MHz • 8.2 mA TX current at 0 dBm output power at 2.4 GHz • 34.5 mA TX current at 14 dBm output power at 868 MHz • 63 μA/MHz in Active Mode (EM0) • 2.2 μA EM2 DeepSleep current (4 kB RAM retention and RTCC running from LFRCO) • High Receiver Performance • -92.5 dBm sensitivity at 1 Mbit/s GFSK, 2.4 GHz • -99 dBm sensitivity at 250 kbps DSSS-OQPSK, 2.4 GHz • -126.4 dBm sensitivity at 600 bps, GFSK, 915 MHz • -121.4 dBm sensitivity at 2.4 kbps, GFSK, 868 MHz • -107 dBm sensitivity at 4.8 kbps, OOK, 433 MHz • -111.9 dBm sensitivity at 38.4 kbps, GFSK, 169 MHz • Supported Modulation Formats • 2/4 (G)FSK with fully configurable shaping • BPSK / DBPSK TX • OOK / ASK • Shaped OQPSK / (G)MSK • Configurable DSSS and FEC • Supported Protocols • Zigbee • Thread • Bluetooth® Low Energy • • • N ot R ec • Proprietary Protocols • Wireless M-Bus • Selected IEEE 802.15.4g SUN-FSK PHYs • Low Power Wide Area Networks • Suitable for Systems Targeting Compliance With: • FCC Part 90.210 Mask D, FCC part 15.247, 15.231, 15.249 • ETSI Category I Operation, EN 300 220, EN 300 328 • ARIB T-108, T-96 • China regulatory silabs.com | Building a more connected world. Rev. 1.5 | 2 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Ordering Information 2. Ordering Information Table 2.1. Ordering Information EFR32MG1P233F256GM48-C0 Frequency Band @ Max TX Power Flash (kB) RAM (kB) GPIO Package Temp Range Bluetooth LE 2.4 GHz @ 19 dBm 256 32 28 QFN48 -40 to +85°C Zigbee Sub-GHz @ 20 dBm 256 32 28 QFN48 -40 to +125°C Thread EFR32MG1P233F256IM48-C0 Bluetooth LE 2.4 GHz @ 19 dBm Zigbee Sub-GHz @ 20 dBm D Proprietary EFR32MG1P232F256GM48-C0 Bluetooth LE 2.4 GHz @ 19 dBm 32 31 QFN48 -40 to +85°C 256 32 31 QFN48 -40 to +125°C 2.4 GHz @ 19 dBm 256 32 16 QFN32 -40 to +85°C 2.4 GHz @ 19 dBm 256 32 16 QFN32 -40 to +125°C Sub-GHz @ 20 dBm 256 32 32 QFN48 -40 to +85°C Bluetooth LE 2.4 GHz @ 16.5 dBm 256 32 28 QFN48 -40 to +85°C Zigbee Sub-GHz @ 16.5 dBm Zigbee Proprietary Bluetooth LE 256 fo r Thread EFR32MG1P232F256IM48-C0 N ew Thread Proprietary es ig ns Ordering Code Protocol Stack 2.4 GHz @ 19 dBm m en de d Zigbee Thread Proprietary EFR32MG1P232F256GM32-C0 Bluetooth LE Zigbee Thread om Proprietary EFR32MG1P232F256IM32-C0 Bluetooth LE ec Zigbee R EFR32MG1P231F256GM48-C0 N ot EFR32MG1P133F256GM48-C0 Thread Proprietary Zigbee Proprietary Thread Proprietary silabs.com | Building a more connected world. Rev. 1.5 | 3 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Ordering Information Ordering Code Protocol Stack EFR32MG1P132F256GM48-C0 Bluetooth LE Frequency Band @ Max TX Power Flash (kB) RAM (kB) GPIO Package Temp Range 2.4 GHz @ 16.5 dBm 256 32 31 QFN48 -40 to +85°C 2.4 GHz @ 16.5 dBm 256 32 31 QFN48 -40 to +125°C 2.4 GHz @ 16.5 dBm 256 32 16 QFN32 -40 to +85°C Zigbee EFR32MG1P132F256IM48-C0 Bluetooth LE Zigbee Thread Proprietary EFR32MG1P132F256GM32-C0 Bluetooth LE N ew Zigbee Thread Proprietary EFR32MG1P132F256IM32-C0 Bluetooth LE 2.4 GHz @ 16.5 dBm 32 16 QFN32 -40 to +125°C 256 32 32 QFN48 -40 to +85°C 2.4 GHz @ 19 dBm 256 32 31 QFN48 -40 to +85°C 2.4 GHz @ 19 dBm 256 32 31 QFN48 -40 to +125°C 2.4 GHz @ 19 dBm 256 32 16 QFN32 -40 to +85°C 2.4 GHz @ 16.5 dBm 256 32 31 QFN48 -40 to +85°C 2.4 GHz @ 16.5 dBm 256 32 16 QFN32 -40 to +85°C 2.4 GHz @ 8 dBm 256 32 31 QFN48 -40 to +85°C 2.4 GHz @ 8 dBm 256 32 16 QFN32 -40 to +85°C Proprietary Zigbee Sub-GHz @ 16.5 dBm m en de d EFR32MG1P131F256GM48-C0 256 fo r Zigbee Thread D Proprietary es ig ns Thread Proprietary EFR32MG1B232F256GM48-C0 Zigbee Thread EFR32MG1B232F256IM48-C0 Zigbee Thread EFR32MG1B232F256GM32-C0 Zigbee om Thread EFR32MG1B132F256GM48-C0 Zigbee ec Thread R EFR32MG1B132F256GM32-C0 N ot EFR32MG1V132F256GM48-C0 EFR32MG1V132F256GM32-C0 Zigbee Thread Zigbee Thread Zigbee Thread silabs.com | Building a more connected world. Rev. 1.5 | 4 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Ordering Information EFR32 X G 1 P 132 F 256 G M 32 – C0 R Tape and Reel (Optional) Pin Count Package – M (QFN), J (CSP) es ig ns Revision Temperature Grade – G (-40 to +85 °C), -I (-40 to +125 °C) Flash Memory Size in kB Memory Type (Flash) N ew Performance Grade – P (Performance), B (Basic), V (Value) D Feature Set Code – r2r1r0 r2: Reserved r1: RF Type – 3 (TRX), 2 (RX), 1 (TX) r0: Frequency Band – 1 (Sub-GHz), 2 (2.4 GHz), 3 (Dual-Band) Series Gecko Family – M (Mighty), B (Blue), F (Flex) fo r Wireless Gecko 32-bit N ot R ec om m en de d Figure 2.1. Ordering Code Key silabs.com | Building a more connected world. Rev. 1.5 | 5 Table of Contents 1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 Radio . . . . . . . . . . . . 3.2.1 Antenna Interface . . . . . . 3.2.2 Fractional-N Frequency Synthesizer 3.2.3 Receiver Architecture . . . . . 3.2.4 Transmitter Architecture . . . . 3.2.5 Wake on Radio . . . . . . . 3.2.6 Flexible Frame Handling . . . . 3.2.7 Packet and State Trace . . . . 3.2.8 Data Buffering . . . . . . . . 3.2.9 Radio Controller (RAC). . . . . 3.2.10 Random Number Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 .10 .10 .10 .10 .11 .11 .11 .11 .11 .11 3.3 Power . . . . . . . . . . . 3.3.1 Energy Management Unit (EMU) 3.3.2 DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 .12 .12 3.4 General Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . .12 3.5 Clocking . . . . . . . . . . 3.5.1 Clock Management Unit (CMU) . 3.5.2 Internal and External Oscillators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 .12 .12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 .13 .13 .13 .13 .13 .13 3.7 Communications and Other Digital Peripherals . . . . . . . . . . 3.7.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) . 3.7.2 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) . 3.7.3 Inter-Integrated Circuit Interface (I2C) . . . . . . . . . . . . 3.7.4 Peripheral Reflex System (PRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 .13 .14 .14 .14 3.8 Security Features . . . . . . . . . . . . . . . 3.8.1 General Purpose Cyclic Redundancy Check (GPCRC) . 3.8.2 Crypto Accelerator (CRYPTO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 .14 .14 3.9 Analog. . . . . . . . . . . . . . 3.9.1 Analog Port (APORT) . . . . . . . 3.9.2 Analog Comparator (ACMP) . . . . . 3.9.3 Analog to Digital Converter (ADC) . . . 3.9.4 Digital to Analog Current Converter (IDAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 .14 .14 .15 .15 . . . N ot R ec om 3.6 Counters/Timers and PWM . . . . . . . . . 3.6.1 Timer/Counter (TIMER) . . . . . . . . 3.6.2 Real Time Counter and Calendar (RTCC) . . 3.6.3 Low Energy Timer (LETIMER) . . . . . . 3.6.4 Ultra Low Power Wake-up Timer (CRYOTIMER) 3.6.5 Pulse Counter (PCNT) . . . . . . . . . 3.6.6 Watchdog Timer (WDOG) . . . . . . . . D . N ew . fo r . m en de d 3.1 Introduction . es ig ns 3. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 silabs.com | Building a more connected world. . . . . . . . . . . . . . . . . . . . . . . . . . Rev. 1.5 | 6 . . . . . . . . . . . . . . . . .15 3.11 Core and Memory . . . . . . . . . . . . 3.11.1 Processor Core . . . . . . . . . . . . 3.11.2 Memory System Controller (MSC) . . . . . 3.11.3 Linked Direct Memory Access Controller (LDMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 .15 .15 .15 3.12 Memory Map . . . . . . . . .16 . . . . . . . . . . . . . . . . . . . . . . . 3.13 Configuration Summary . . . . . . . . . . . . . . . . . 4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . 4.2 Typical Performance Curves 4.2.1 Supply Current . . . 4.2.2 DC-DC Converter . . 4.2.3 Internal Oscillators . . 4.2.4 2.4 GHz Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . m en de d fo r . . . . . . . . . . . . . . . . . . . . . . ec om . . . . . . . . . . R 5. Typical Connection Diagrams . . . . . . N ot 5.2 RF Matching Networks 5.3 Other Connections. . . . . . . . . .17 . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1 Electrical Characteristics . . . . . . . . 4.1.1 Absolute Maximum Ratings . . . . . . 4.1.2 Operating Conditions . . . . . . . . 4.1.3 Thermal Characteristics . . . . . . . 4.1.4 DC-DC Converter . . . . . . . . . 4.1.5 Current Consumption . . . . . . . . 4.1.6 Wake Up Times . . . . . . . . . . 4.1.7 Brown Out Detector (BOD) . . . . . . 4.1.8 Frequency Synthesizer . . . . . . . . 4.1.9 2.4 GHz RF Transceiver Characteristics . . 4.1.10 Sub-GHz RF Transceiver Characteristics . 4.1.11 Modem. . . . . . . . . . . . . 4.1.12 Oscillators . . . . . . . . . . . 4.1.13 Flash Memory Characteristics . . . . . 4.1.14 General-Purpose I/O (GPIO) . . . . . 4.1.15 Voltage Monitor (VMON) . . . . . . . 4.1.16 Analog to Digital Converter (ADC) . . . 4.1.17 Analog Comparator (ACMP) . . . . . 4.1.18 Current Digital to Analog Converter (IDAC) 4.1.19 Pulse Counter (PCNT) . . . . . . . 4.1.20 I2C . . . . . . . . . . . . . . 4.1.21 USART SPI . . . . . . . . . . . 5.1 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 .19 .21 .23 .24 .26 .32 .33 .34 .35 .44 .68 .69 .73 .74 .76 .77 .79 .81 .83 .83 .86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 .89 .91 .93 .99 . . . . . . . . . . . . . . . . . . . . . . . .101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D . . N ew . . es ig ns 3.10 Reset Management Unit (RMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 . . .103 . 104 6. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.1 QFN48 2.4 GHz and Sub-GHz Device Pinout. . . . . . . . . . . . . . . . . . . 105 6.2 QFN48 2.4 GHz Device Pinout . . . . . . . . . . . . . . . . . . 107 . 6.3 QFN48 Sub-GHz Device Pinout silabs.com | Building a more connected world. . . . . . . . . . . . . . . . . . . . . . . . . . . .109 Rev. 1.5 | 7 6.4 QFN32 2.4 GHz Device Pinout 6.5 GPIO Functionality Table . . . . . . . . . . . . . . . . . . . . . . . . 111 . . . . . . . . . . . . . . . . . . . . . . . 1 . 13 6.6 Alternate Functionality Overview . . 6.7 Analog Port (APORT) Client Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 . .130 7.1 QFN48 Package Dimensions 7.2 QFN48 PCB Land Pattern . 7.3 QFN48 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . es ig ns 7. QFN48 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . 134 . . . . . . . . 134 . . . . . . . .136 . . . . . . . . .138 8.1 QFN32 Package Dimensions 8.2 QFN32 PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 . . . . .141 . . . . . . . . . . . . . . . . . .143 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 N ot R ec om m en de d fo r 9. Revision History . . N ew 8.3 QFN32 Package Marking . . D 8. QFN32 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . 139 silabs.com | Building a more connected world. Rev. 1.5 | 8 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet System Overview 3. System Overview 3.1 Introduction es ig ns The EFR32 product family combines an energy-friendly MCU with a highly integrated radio transceiver. The devices are well suited for any battery operated application as well as other systems requiring high performance and low energy consumption. This section gives a short introduction to the full radio and MCU system. The detailed functional description can be found in the EFR32xG1 Reference Manual. A block diagram of the EFR32MG1 family is shown in Figure 3.1 Detailed EFR32MG1 Block Diagram on page 9. The diagram shows a superset of features available on the family, which vary by OPN. For more information about specific device features, consult 2. Ordering Information. Radio Transciever Port I/O Configuration 2G4RF_ION BALUN PA Q Frequency Synthesizer To RF Frontend Circuits AGC MOD Up to 256 KB ISP Flash Program Memory IOVDD Up to 32 KB RAM Voltage Monitor Memory Protection Unit DVDD Floating Point Unit bypass VREGSW DC-DC Converter DECOUPLE DMA Controller Voltage Regulator Serial Wire Debug / Programming Watchdog Timer VSS VREGVSS RFVSS PAVSS Brown Out / Power-On Reset ULFRCO AUXHFRCO A A H P B B CRC Analog Peripherals Internal Reference om Port C Drivers PCn Port D Drivers PDn VDD VREF Port F Drivers PFn 12-bit ADC VDD Temp Sensor + Analog Comparator Figure 3.1. Detailed EFR32MG1 Block Diagram R 3.2 Radio ec HFXTAL_N LFXO HFXO PBn IDAC LFRCO LFXTAL_P / N Port B Drivers I2C HFRCO HFXTAL_P PAn CRYPTO Clock Management Reset Management Unit RESETn USART LEUART m en de d VREGVDD Port A Drivers Port Mapper fo r RFVDD AVDD PCNT RTC / RTCC ARM Cortex-M4 Core Energy Management PAVDD IOVDD CRYOTIMER N ew I Input MUX 2G4RF_IOP D TIMER 2.4 GHz RF LNA FRC IFADC PGA Q Digital Peripherals LETIMER RAC PA BUFC DEMOD LNA CRC SUBGRF_IP SUBGRF_IN SUBGRF_OP SUBGRF_ON APORT Sub-GHz RF I N ot The Mighty Gecko family features a highly configurable radio transceiver supporting a wide range of wireless protocols, including Zigbee, Thread, BLE and proprietary. silabs.com | Building a more connected world. Rev. 1.5 | 9 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet System Overview 3.2.1 Antenna Interface The EFR32MG1 family includes devices which support both single-band and dual-band RF communication over separate physical RF interfaces. The 2.4 GHz antenna interface consists of two pins (2G4RF_IOP and 2G4RF_ION) that interface directly to the on-chip BALUN. The 2G4RF_ION pin should be grounded externally. es ig ns The sub-GHz antenna interface consists of a differential transmit interface (pins SUBGRF_OP and SUBGRF_ON) and a differential receive interface (pinsSUBGRF_IP and SUBGRF_IN). The external components and power supply connections for the antenna interface typical applications are shown in the RF Matching Networks section. 3.2.2 Fractional-N Frequency Synthesizer D The EFR32MG1 contains a high performance, low phase noise, fully integrated fractional-N frequency synthesizer. The synthesizer is used in receive mode to generate the LO frequency used by the down-conversion mixer. It is also used in transmit mode to directly generate the modulated RF carrier. N ew The fractional-N architecture provides excellent phase noise performance combined with frequency resolution better than 100 Hz, with low energy consumption. The synthesizer has fast frequency settling which allows very short receiver and transmitter wake up times to optimize system energy consumption. 3.2.3 Receiver Architecture fo r The EFR32MG1 uses a low-IF receiver architecture, consisting of a Low-Noise Amplifier (LNA) followed by an I/Q down-conversion mixer, employing a crystal reference. The I/Q signals are further filtered and amplified before being sampled by the IF analog-to-digital converter (IFADC). The IF frequency is configurable from 150 kHz to 1371 kHz. The IF can further be configured for high-side or low-side injection, providing flexibility with respect to known interferers at the image frequency. m en de d The Automatic Gain Control (AGC) block adjusts the receiver gain to optimize performance and avoid saturation for excellent selectivity and blocking performance. The 2.4 GHz radio is calibrated at production to improve image rejection performance. The sub-GHz radio can be calibrated on-demand by the user for the desired frequency band. Demodulation is performed in the digital domain. The demodulator performs configurable decimation and channel filtering to allow receive bandwidths ranging from 0.1 to 2530 kHz. High carrier frequency and baud rate offsets are tolerated by active estimation and compensation. Advanced features supporting high quality communication under adverse conditions include forward error correction by block and convolutional coding as well as Direct Sequence Spread Spectrum (DSSS) for 2.4 GHz and sub-GHz bands. A Received Signal Strength Indicator (RSSI) is available for signal quality metrics, for level-based proximity detection, and for RF channel access by Collision Avoidance (CA) or Listen Before Talk (LBT) algorithms. An RSSI capture value is associated with each received frame and the dynamic RSSI measurement can be monitored throughout reception. ec om The EFR32MG1 features integrated support for antenna diversity to mitigate the problem of frequency-selective fading due to multipath propagation and improve link budget. Support for antenna diversity is available for specific PHY configurations in 2.4 GHz and sub-GHz bands. Internal configurable hardware controls an external switch for automatic switching between antennae during RF receive detection operations. R Note: Due to the shorter preamble of 802.15.4 and BLE packets, RX diversity is not supported. 3.2.4 Transmitter Architecture N ot The EFR32MG1 uses a direct-conversion transmitter architecture. For constant envelope modulation formats, the modulator controls phase and frequency modulation in the frequency synthesizer. Transmit symbols or chips are optionally shaped by a digital shaping filter. The shaping filter is fully configurable, including the BT product, and can be used to implement Gaussian or Raised Cosine shaping. Carrier Sense Multiple Access - Collision Avoidance (CSMA-CA) or Listen Before Talk (LBT) algorithms can be automatically timed by the EFR32MG1. These algorithms are typically defined by regulatory standards to improve inter-operability in a given bandwidth between devices that otherwise lack synchronized RF channel access. silabs.com | Building a more connected world. Rev. 1.5 | 10 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet System Overview 3.2.5 Wake on Radio The Wake on Radio feature allows flexible, autonomous RF sensing, qualification, and demodulation without required MCU activity, using a subsystem of the EFR32MG1 including the Radio Controller (RAC), Peripheral Reflex System (PRS), and Low Energy peripherals. 3.2.6 Flexible Frame Handling 3.2.7 Packet and State Trace m en de d fo r N ew D es ig ns EFR32MG1 has an extensive and flexible frame handling support for easy implementation of even complex communication protocols. The Frame Controller (FRC) supports all low level and timing critical tasks together with the Radio Controller and Modulator/Demodulator: • Highly adjustable preamble length • Up to 2 simultaneous synchronization words, each up to 32 bits and providing separate interrupts • Frame disassembly and address matching (filtering) to accept or reject frames • Automatic ACK frame assembly and transmission • Fully flexible CRC generation and verification: • Multiple CRC values can be embedded in a single frame • 8, 16, 24 or 32-bit CRC value • Configurable CRC bit and byte ordering • Selectable bit-ordering (least significant or most significant bit first) • Optional data whitening • Optional Forward Error Correction (FEC), including convolutional encoding / decoding and block encoding / decoding • Half rate convolutional encoder and decoder with constraint lengths from 2 to 7 and optional puncturing • Optional symbol interleaving, typically used in combination with FEC • Symbol coding, such as Manchester or DSSS, or biphase space encoding using FEC hardware • UART encoding over air, with start and stop bit insertion / removal • Test mode support, such as modulated or unmodulated carrier output • Received frame timestamping The EFR32MG1 Frame Controller has a packet and state trace unit that provides valuable information during the development phase. It features: • Non-intrusive trace of transmit data, receive data and state information • Data observability on a single-pin UART data output, or on a two-pin SPI data output • Configurable data output bitrate / baudrate • Multiplexed transmitted data, received data and state / meta information in a single serial data stream om 3.2.8 Data Buffering ec The EFR32MG1 features an advanced Radio Buffer Controller (BUFC) capable of handling up to 4 buffers of adjustable size from 64 bytes to 4096 bytes. Each buffer can be used for RX, TX or both. The buffer data is located in RAM, enabling zero-copy operations. 3.2.9 Radio Controller (RAC) N ot R The Radio Controller controls the top level state of the radio subsystem in the EFR32MG1. It performs the following tasks: • Precisely-timed control of enabling and disabling of the receiver and transmitter circuitry • Run-time calibration of receiver, transmitter and frequency synthesizer • Detailed frame transmission timing, including optional LBT or CSMA-CA 3.2.10 Random Number Generator The Frame Controller (FRC) implements a random number generator that uses entropy gathered from noise in the RF receive chain. The data is suitable for use in cryptographic applications. Output from the random number generator can be used either directly or as a seed or entropy source for software-based random number generator algorithms such as Fortuna. silabs.com | Building a more connected world. Rev. 1.5 | 11 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet System Overview 3.3 Power The EFR32MG1 has an Energy Management Unit (EMU) and efficient integrated regulators to generate internal supply voltages. Only a single external supply voltage is required, from which all internal voltages are created. An optional integrated DC-DC buck regulator can be utilized to further reduce the current consumption. The DC-DC regulator requires one external inductor and one external capacitor. es ig ns AVDD and VREGVDD need to be 1.85 V or higher for the MCU to operate across all conditions; however the rest of the system will operate down to 1.62 V, including the digital supply and I/O. This means that the device is fully compatible with 1.8 V components. Running from a sufficiently high supply, the device can use the DC-DC to regulate voltage not only for itself, but also for other PCB components, supplying up to a total of 200 mA. 3.3.1 Energy Management Unit (EMU) D The Energy Management Unit manages transitions of energy modes in the device. Each energy mode defines which peripherals and features are available and the amount of current the device consumes. The EMU can also be used to turn off the power to unused RAM blocks, and it contains control registers for the DC-DC regulator and the Voltage Monitor (VMON). The VMON is used to monitor multiple supply voltages. It has multiple channels which can be programmed individually by the user to determine if a sensed supply has fallen below a chosen threshold. 3.3.2 DC-DC Converter 3.4 General Purpose Input/Output (GPIO) fo r N ew The DC-DC buck converter covers a wide range of load currents and provides up to 90% efficiency in energy modes EM0, EM1, EM2 and EM3, and can supply up to 200 mA to the device and surrounding PCB components. Patented RF noise mitigation allows operation of the DC-DC converter without degrading sensitivity of radio components. Protection features include programmable current limiting, short-circuit protection, and dead-time protection. The DC-DC converter may also enter bypass mode when the input voltage is too low for efficient operation. In bypass mode, the DC-DC input supply is internally connected directly to its output through a low resistance switch. Bypass mode also supports in-rush current limiting to prevent input supply voltage droops due to excessive output current transients. m en de d EFR32MG1 has up to 32 General Purpose Input/Output pins. Each GPIO pin can be individually configured as either an output or input. More advanced configurations including open-drain, open-source, and glitch-filtering can be configured for each individual GPIO pin. The GPIO pins can be overridden by peripheral connections, like SPI communication. Each peripheral connection can be routed to several GPIO pins on the device. The input value of a GPIO pin can be routed through the Peripheral Reflex System to other peripherals. The GPIO subsystem supports asynchronous external pin interrupts. 3.5 Clocking 3.5.1 Clock Management Unit (CMU) om The Clock Management Unit controls oscillators and clocks in the EFR32MG1. Individual enabling and disabling of clocks to all peripherals is performed by the CMU. The CMU also controls enabling and configuration of the oscillators. A high degree of flexibility allows software to optimize energy consumption in any specific application by minimizing power dissipation in unused peripherals and oscillators. ec 3.5.2 Internal and External Oscillators N ot R The EFR32MG1 supports two crystal oscillators and fully integrates four RC oscillators, listed below. • A high frequency crystal oscillator (HFXO) with integrated load capacitors, tunable in small steps, provides a precise timing reference for the MCU. Crystal frequencies in the range from 38 to 40 MHz are supported. An external clock source such as a TCXO can also be applied to the HFXO input for improved accuracy over temperature. • A 32.768 kHz crystal oscillator (LFXO) provides an accurate timing reference for low energy modes. • An integrated high frequency RC oscillator (HFRCO) is available for the MCU system, when crystal accuracy is not required. The HFRCO employs fast startup at minimal energy consumption combined with a wide frequency range. • An integrated auxilliary high frequency RC oscillator (AUXHFRCO) is available for timing the general-purpose ADC and the Serial Wire Viewer port with a wide frequency range. • An integrated low frequency 32.768 kHz RC oscillator (LFRCO) can be used as a timing reference in low energy modes, when crystal accuracy is not required. • An integrated ultra-low frequency 1 kHz RC oscillator (ULFRCO) is available to provide a timing reference at the lowest energy consumption in low energy modes. silabs.com | Building a more connected world. Rev. 1.5 | 12 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet System Overview 3.6 Counters/Timers and PWM 3.6.1 Timer/Counter (TIMER) es ig ns TIMER peripherals keep track of timing, count events, generate PWM outputs and trigger timed actions in other peripherals through the PRS system. The core of each TIMER is a 16-bit counter with up to 4 compare/capture channels. Each channel is configurable in one of three modes. In capture mode, the counter state is stored in a buffer at a selected input event. In compare mode, the channel output reflects the comparison of the counter to a programmed threshold value. In PWM mode, the TIMER supports generation of pulse-width modulation (PWM) outputs of arbitrary waveforms defined by the sequence of values written to the compare registers, with optional dead-time insertion available in timer unit TIMER_0 only. 3.6.2 Real Time Counter and Calendar (RTCC) D The Real Time Counter and Calendar (RTCC) is a 32-bit counter providing timekeeping in all energy modes. The RTCC includes a Binary Coded Decimal (BCD) calendar mode for easy time and date keeping. The RTCC can be clocked by any of the on-board lowfrequency oscillators with the exception of the AUXHFRCO, and it is capable of providing system wake-up at user defined instances. When receiving frames, the RTCC value can be used for timestamping. The RTCC includes 128 bytes of general purpose data retention, allowing easy and convenient data storage in all energy modes down to EM4H. N ew 3.6.3 Low Energy Timer (LETIMER) 3.6.4 Ultra Low Power Wake-up Timer (CRYOTIMER) fo r The unique LETIMER is a 16-bit timer that is available in energy mode EM0 Active, EM1 Sleep, EM2 Deep Sleep, and EM3 Stop. This allows it to be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of waveforms with minimal software intervention. The LETIMER is connected to the Real Time Counter and Calendar (RTCC), and can be configured to start counting on compare matches from the RTCC. 3.6.5 Pulse Counter (PCNT) m en de d The CRYOTIMER is a 32-bit counter that is capable of running in all energy modes. It can be clocked by either the 32.768 kHz crystal oscillator (LFXO), the 32.768 kHz RC oscillator (LFRCO), or the 1 kHz RC oscillator (ULFRCO). It can provide periodic Wakeup events and PRS signals which can be used to wake up peripherals from any energy mode. The CRYOTIMER provides a wide range of interrupt periods, facilitating flexible ultra-low energy operation. The Pulse Counter (PCNT) peripheral can be used for counting pulses on a single input or to decode quadrature encoded inputs. The clock for PCNT is selectable from either an external source on pin PCTNn_S0IN or from an internal timing reference, selectable from among any of the internal oscillators, except the AUXHFRCO. The peripheral may operate in energy mode EM0 Active, EM1 Sleep, EM2 Deep Sleep, and EM3 Stop. om 3.6.6 Watchdog Timer (WDOG) ec The watchdog timer can act both as an independent watchdog or as a watchdog synchronous with the CPU clock. It has windowed monitoring capabilities, and can generate a reset or different interrupts depending on the failure mode of the system. The watchdog can also monitor autonomous systems driven by PRS. R 3.7 Communications and Other Digital Peripherals 3.7.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) N ot The Universal Synchronous/Asynchronous Receiver/Transmitter is a flexible serial I/O interface. It supports full duplex asynchronous UART communication with hardware flow control as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with devices supporting: • ISO7816 SmartCards • IrDA • I2S silabs.com | Building a more connected world. Rev. 1.5 | 13 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet System Overview 3.7.2 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) The unique LEUARTTM provides two-way UART communication on a strict power budget. Only a 32.768 kHz clock is needed to allow UART communication up to 9600 baud. The LEUART includes all necessary hardware to make asynchronous serial communication possible with a minimum of software intervention and energy consumption. 3.7.3 Inter-Integrated Circuit Interface (I2C) es ig ns The I2C interface enables communication between the MCU and a serial I2C bus. It is capable of acting as both a master and a slave and supports multi-master buses. Standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates from 10 kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also available, allowing implementation of an SMBus-compliant system. The interface provided to software by the I2C peripheral allows precise timing control of the transmission process and highly automated transfers. Automatic recognition of slave addresses is provided in active and low energy modes. 3.7.4 Peripheral Reflex System (PRS) N ew D The Peripheral Reflex System provides a communication network between different peripherals without software involvement. Peripherals producing Reflex signals are called producers. The PRS routes Reflex signals from producers to consumer peripherals, which in turn perform actions in response. Edge triggers and other functionality such as simple logic operations (AND, OR, NOT) can be applied by the PRS to the signals. The PRS allows peripheral to act autonomously without waking the MCU core, saving power. 3.8 Security Features 3.8.1 General Purpose Cyclic Redundancy Check (GPCRC) m en de d 3.8.2 Crypto Accelerator (CRYPTO) fo r The GPCRC block implements a Cyclic Redundancy Check (CRC) function. It supports both 32-bit and 16-bit polynomials. The supported 32-bit polynomial is 0x04C11DB7 (IEEE 802.3), while the 16-bit polynomial can be programmed to any value, depending on the needs of the application. The Crypto Accelerator is a fast and energy-efficient autonomous hardware encryption and decryption accelerator. EFR32 devices support AES encryption and decryption with 128- or 256-bit keys, ECC over both GF(P) and GF(2m), SHA-1 and SHA-2 (SHA-224 and SHA-256). Supported block cipher modes of operation for AES include: ECB, CTR, CBC, PCBC, CFB, OFB, GCM, CBC-MAC, GMAC and CCM. Supported ECC NIST recommended curves include P-192, P-224, P-256, K-163, K-233, B-163 and B-233. The CRYPTO block is tightly linked to the Radio Buffer Controller (BUFC) enabling fast and efficient autonomous cipher operations on data buffer content. It allows fast processing of GCM (AES), ECC and SHA with little CPU intervention. ec 3.9 Analog om CRYPTO also provides trigger signals for DMA read and write operations. 3.9.1 Analog Port (APORT) N ot R The Analog Port (APORT) is an analog interconnect matrix allowing access to many analog peripherals on a flexible selection of pins. Each APORT bus consists of analog switches connected to a common wire. Since many clients can operate differentially, buses are grouped by X/Y pairs. 3.9.2 Analog Comparator (ACMP) The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is higher. Inputs are selected from among internal references and external pins. The tradeoff between response time and current consumption is configurable by software. Two 6-bit reference dividers allow for a wide range of internally-programmable reference sources. The ACMP can also be used to monitor the supply voltage. An interrupt can be generated when the supply falls below or rises above the programmable threshold. silabs.com | Building a more connected world. Rev. 1.5 | 14 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet System Overview 3.9.3 Analog to Digital Converter (ADC) The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to 1 Msps. The output sample resolution is configurable and additional resolution is possible using integrated hardware for averaging over multiple samples. The ADC includes integrated voltage references and an integrated temperature sensor. Inputs are selectable from a wide range of sources, including pins configurable as either single-ended or differential. es ig ns 3.9.4 Digital to Analog Current Converter (IDAC) The IDAC can source or sink a configurable constant current. This current can be driven on an output pin or routed to the selected ADC input pin for capacitive sensing. The full-scale current is programmable between 0.05 µA and 64 µA with several ranges consisting of various step sizes. 3.10 Reset Management Unit (RMU) D The RMU is responsible for handling reset of the EFR32MG1. A wide range of reset sources are available, including several power supply monitors, pin reset, software controlled reset, core lockup reset, and watchdog reset. N ew 3.11 Core and Memory 3.11.1 Processor Core m en de d fo r The ARM Cortex-M processor includes a 32-bit RISC processor integrating the following features and tasks in the system: • ARM Cortex-M4 RISC processor achieving 1.25 Dhrystone MIPS/MHz • Memory Protection Unit (MPU) supporting up to 8 memory segments • Up to 256 kB flash program memory • Up to 32 kB RAM data memory • Configuration and event handling of all peripherals • 2-pin Serial-Wire debug interface 3.11.2 Memory System Controller (MSC) The Memory System Controller (MSC) is the program memory unit of the microcontroller. The flash memory is readable and writable from both the Cortex-M and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code is normally written to the main block, whereas the information block is available for special user data and flash lock bits. There is also a read-only page in the information block containing system and device calibration data. Read and write operations are supported in energy modes EM0 Active and EM1 Sleep. 3.11.3 Linked Direct Memory Access Controller (LDMA) N ot R ec om The Linked Direct Memory Access (LDMA) controller allows the system to perform memory operations independently of software. This reduces both energy consumption and software workload. The LDMA allows operations to be linked together and staged, enabling sophisticated operations to be implemented. silabs.com | Building a more connected world. Rev. 1.5 | 15 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet System Overview 3.12 Memory Map m en de d fo r N ew D es ig ns The EFR32MG1 memory map is shown in the figures below. RAM and flash sizes are for the largest memory configuration. N ot R ec om Figure 3.2. EFR32MG1 Memory Map — Core Peripherals and Code Space silabs.com | Building a more connected world. Rev. 1.5 | 16 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet m en de d fo r N ew D es ig ns System Overview Figure 3.3. EFR32MG1 Memory Map — Peripherals 3.13 Configuration Summary Module R USART0 ec om The features of the EFR32MG1 are a subset of the feature set described in the device reference manual. The table below describes device specific implementation of the features. Remaining modules support full configuration. N ot USART1 TIMER0 TIMER1 silabs.com | Building a more connected world. Table 3.1. Configuration Summary Configuration Pin Connections IrDA US0_TX, US0_RX, US0_CLK, US0_CS SmartCard I2S US1_TX, US1_RX, US1_CLK, US1_CS SmartCard with DTI TIM0_CC[2:0], TIM0_CDTI[2:0] TIM1_CC[3:0] Rev. 1.5 | 17 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4. Electrical Specifications 4.1 Electrical Characteristics All electrical parameters in all tables are specified under the following conditions, unless stated otherwise: • Typical values are based on TAMB=25 °C and VDD= 3.3 V, by production test and/or technology characterization. es ig ns • Radio performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output power-specific external RF impedance-matching networks for interfacing to a 50 Ω antenna. • Minimum and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature, unless stated otherwise. N ot R ec om m en de d fo r N ew D Refer to 4.1.2.1 General Operating Conditions for more details about operational supply and temperature limits. silabs.com | Building a more connected world. Rev. 1.5 | 18 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.1 Absolute Maximum Ratings Stresses above those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and reliability data, see the Quality and Reliability Monitor Report at http://www.silabs.com/support/quality/pages/default.aspx. Symbol Test Condition Storage temperature range TSTG -50 Voltage on any supply pin VDDMAX -0.3 Voltage ramp rate on any supply pin VDDRAMPMAX DC voltage on any GPIO pin VDIGPIN — Voltage differential between RF pins (2G4RF_IOP 2G4RF_ION) VMAXDIFF2G4 Absolute voltage on RF pins 2G4RF_IOP and 2G4RF_ION VMAX2G4 Absolute voltage on SubGHz RF pins VMAXSUBG Unit — 150 °C — 3.8 V — 1 V / µs Min of 5.25 and IOVDD +2 V — N ew PRFMAX2G4 Max — IOVDD+0.3 V -0.3 — 1.4 V — — 10 dBm -50 — 50 mV -0.3 — 3.8 V Pins SUBGRF_OP and SUBGRF_ON -0.3 — 3.8 V Pins SUBGRF_IP and SUBGRF_IN, -0.3 — 0.3 V fo r Input RF level on pins 2G4RF_IOP and 2G4RF_ION Typ -0.3 m en de d VHFXOPIN -0.3 5V tolerant GPIO pins1 2 3 Standard GPIO pins Voltage on HFXO pins Min D Parameter es ig ns Table 4.1. Absolute Maximum Ratings Source — — 200 mA Total current into VSS ground lines IVSSMAX Sink — — 200 mA Current per I/O pin IIOMAX Sink — — 50 mA Source — — 50 mA Sink — — 200 mA Source — — 200 mA -G grade devices -40 — 105 °C -I grade devices -40 — 125 °C ec om Total current into VDD power IVDDMAX lines R Current for all I/O pins N ot Junction temperature IIOALLMAX TJ silabs.com | Building a more connected world. Rev. 1.5 | 19 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit N ot R ec om m en de d fo r N ew D es ig ns Note: 1. When a GPIO pin is routed to the analog module through the APORT, the maximum voltage = IOVDD. 2. Valid for IOVDD in valid operating range or when IOVDD is undriven (high-Z). If IOVDD is connected to a low-impedance source below the valid operating range (e.g. IOVDD shorted to VSS), the pin voltage maximum is IOVDD + 0.3 V, to avoid exceeding the maximum IO current specifications. 3. To operate above the IOVDD supply rail, over-voltage tolerance must be enabled according to the GPIO_Px_OVTDIS register. Pins with over-voltage tolerance disabled have the same limits as Standard GPIO. silabs.com | Building a more connected world. Rev. 1.5 | 20 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.2 Operating Conditions N ot R ec om m en de d fo r N ew D es ig ns When assigning supply sources, the following requirements must be observed: • VREGVDD must be greater than or equal to AVDD, DVDD, RFVDD, PAVDD and all IOVDD supplies. • VREGVDD = AVDD • DVDD ≤ AVDD • IOVDD ≤ AVDD • RFVDD ≤ AVDD • PAVDD ≤ AVDD silabs.com | Building a more connected world. Rev. 1.5 | 21 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.2.1 General Operating Conditions Table 4.2. General Operating Conditions Symbol Test Condition Min Typ Max Unit Operating ambient temperature range1 TA -G temperature grade -40 25 85 °C -I temperature grade -40 25 125 °C AVDD supply voltage2 VAVDD 3.3 3.8 V VREGVDD operating supply voltage2 3 VVREGVDD 3.3 3.8 V 3.3 3.8 V 3.3 3.8 V — 200 mA 2.4 DCDC in bypass, 50mA load 1.85 DCDC not in use. DVDD externally shorted to VREGVDD 1.85 DCDC in bypass, T ≤ 85 °C VRFVDD DVDD operating supply voltage VDVDD PAVDD operating supply voltage VPAVDD DECOUPLE output capacitor4 — 100 mA 1.62 — VVREGVDD V 1.62 — VVREGVDD V 1.62 — VVREGVDD V 1.62 — VVREGVDD V 0.75 1.0 2.75 µF — — 0.1 V MODE = WS0 — — 26 MHz MODE = WS1 — — 40 MHz MODE = WS0 — — 26 MHz MODE = WS1 — — 40 MHz All IOVDD pins m en de d IOVDD operating supply volt- VIOVDD age — fo r DCDC in bypass, T > 85 °C RFVDD operating supply voltage CDECOUPLE Difference between AVDD dVDD and VREGVDD, ABS(AVDDVREGVDD)2 HFCLK frequency fCORE om HFCORECLK frequency fHFCLK — D IVREGVDD DCDC in regulation N ew VREGVDD current 1.85 es ig ns Parameter R ec Note: 1. The maximum limit on TA may be lower due to device self-heating, which depends on the power dissipation of the specific application. TA (max) = TJ (max) - (THETAJA x PowerDissipation). Refer to the Absolute Maximum Ratings table and the Thermal Characteristics table for TJ and THETAJA. N ot 2. VREGVDD must be tied to AVDD. Both VREGVDD and AVDD minimum voltages must be satisfied for the part to operate. 3. The minimum voltage required in bypass mode is calculated using RBYP from the DCDC specification table. Requirements for other loads can be calculated as VDVDD_min+ILOAD * RBYP_max. 4. The system designer should consult the characteristic specs of the capacitor used on DECOUPLE to ensure its capacitance value stays within the specified bounds across temperature and DC bias. silabs.com | Building a more connected world. Rev. 1.5 | 22 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.3 Thermal Characteristics Symbol Test Condition Min Typ Max Unit Thermal resistance, QFN48 Package THETAJA_QFN48 2-Layer PCB, Air velocity = 0 m/s — 64.5 — °C/W 2-Layer PCB, Air velocity = 1 m/s — 51.6 — °C/W 2-Layer PCB, Air velocity = 2 m/s — 47.7 — °C/W 4-Layer PCB, Air velocity = 0 m/s — 26.2 — °C/W 4-Layer PCB, Air velocity = 1 m/s — 23.1 — °C/W 4-Layer PCB, Air velocity = 2 m/s — 22.1 — °C/W THETAJA_QFN32 2-Layer PCB, Air velocity = 0 m/s — 79 — °C/W 2-Layer PCB, Air velocity = 1 m/s — 62.2 — °C/W 2-Layer PCB, Air velocity = 2 m/s — 54.1 — °C/W 4-Layer PCB, Air velocity = 0 m/s — 32 — °C/W 4-Layer PCB, Air velocity = 1 m/s — 28.1 — °C/W 4-Layer PCB, Air velocity = 2 m/s — 26.9 — °C/W N ot R ec om m en de d fo r N ew Thermal resistance, QFN32 Package es ig ns Parameter D Table 4.3. Thermal Characteristics silabs.com | Building a more connected world. Rev. 1.5 | 23 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.4 DC-DC Converter Test conditions: L_DCDC=4.7 µH (Murata LQH3NPN4R7MM0L), C_DCDC=1.0 µF (Murata GRM188R71A105KA61D), V_DCDC_I=3.3 V, V_DCDC_O=1.8 V, I_DCDC_LOAD=50 mA, Heavy Drive configuration, F_DCDC_LN=7 MHz, unless otherwise indicated. Table 4.4. DC-DC Converter Symbol Test Condition Min Input voltage range VDCDC_I Bypass mode, IDCDC_LOAD = 50 mA 1.85 Low noise (LN) mode, 1.8 V output, IDCDC_LOAD = 100 mA, or Low power (LP) mode, 1.8 V output, IDCDC_LOAD = 10 mA 2.4 Low noise (LN) mode, 1.8 V output, IDCDC_LOAD = 200 mA 2.6 ACCDC Regulation window2 WINREG Unit VVREGVDD_ V MAX — VVREGVDD_ V MAX — VVREGVDD_ V D Regulation DC accuracy — 1.8 — VVREGVDD V Low Noise (LN) mode, 1.8 V target output 1.7 — 1.9 V Low Power (LP) mode, LPCMPBIAS3 = 0, 1.8 V target output, IDCDC_LOAD ≤ 75 µA 1.63 — 2.2 V Low Power (LP) mode, LPCMPBIAS3 = 3, 1.8 V target output, IDCDC_LOAD ≤ 10 mA 1.63 — 2.1 V N ew VDCDC_O Max MAX m en de d fo r Output voltage programmable range1 Typ es ig ns Parameter VR Radio disabled — 3 — mVpp Output voltage under/overshoot VOV CCM Mode (LNFORCECCM3 = 1), Load changes between 0 mA and 100 mA — — 150 mV DCM Mode (LNFORCECCM3 = 0), Load changes between 0 mA and 10 mA — — 150 mV Overshoot during LP to LN CCM/DCM mode transitions compared to DC level in LN mode — 200 — mV Undershoot during BYP/LP to LN CCM (LNFORCECCM3 = 1) mode transitions compared to DC level in LN mode — 50 — mV Undershoot during BYP/LP to LN DCM (LNFORCECCM3 = 0) mode transitions compared to DC level in LN mode — 125 — mV N ot R ec om Steady-state output ripple DC line regulation VREG Input changes between VVREGVDD_MAX and 2.4 V — 0.1 — % DC load regulation IREG Load changes between 0 mA and 100 mA in CCM mode — 0.1 — % silabs.com | Building a more connected world. Rev. 1.5 | 24 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications Min Typ Max Unit Max load current ILOAD_MAX Low noise (LN) mode, Heavy Drive4, T ≤ 85 °C — — 200 mA Low noise (LN) mode, Heavy Drive4, T > 85 °C — — 100 mA Low noise (LN) mode, Medium Drive4 — — 100 mA Low noise (LN) mode, Light Drive4 — Low power (LP) mode, LPCMPBIAS3 = 0 — Low power (LP) mode, LPCMPBIAS3 = 3 — CDCDC 25% tolerance 1 DCDC nominal output induc- LDCDC tor 20% tolerance DCDC nominal output capacitor Resistance in Bypass mode es ig ns Test Condition — 50 mA — 75 µA — 10 mA D Symbol 1 4.7 µF 4.7 4.7 4.7 µH — 1.2 2.5 Ω N ew Parameter RBYP fo r Note: 1. Due to internal dropout, the DC-DC output will never be able to reach its input voltage, VVREGVDD. N ot R ec om m en de d 2. LP mode controller is a hysteretic controller that maintains the output voltage within the specified limits. 3. In the EMU_DCDCMISCCTRL register. 4. Drive levels are defined by configuration of the PFETCNT and NFETCNT registers. Light Drive: PFETCNT=NFETCNT=3; Medium Drive: PFETCNT=NFETCNT=7; Heavy Drive: PFETCNT=NFETCNT=15. silabs.com | Building a more connected world. Rev. 1.5 | 25 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.5 Current Consumption 4.1.5.1 Current Consumption 3.3 V without DC-DC Converter Parameter Symbol Min 38.4 MHz crystal, CPU running while loop from flash1 — 38 MHz HFRCO, CPU running Prime from flash — 38 MHz HFRCO, CPU running while loop from flash — Typ Max Unit 130 — µA/MHz 88 — µA/MHz 105 µA/MHz 100 — 112 — µA/MHz 26 MHz HFRCO, CPU running while loop from flash — 102 106 µA/MHz 1 MHz HFRCO, CPU running while loop from flash — 222 350 µA/MHz 38.4 MHz crystal1 — 65 — µA/MHz 38 MHz HFRCO — 35 38 µA/MHz 26 MHz HFRCO — 37 41 µA/MHz 1 MHz HFRCO — 157 275 µA/MHz Full 32 kB RAM retention and RTCC running from LFXO — 3.3 — µA 1 bank (4 kB) RAM retention and RTCC running from LFRCO — 3 6.3 µA Full 32 kB RAM retention and CRYOTIMER running from ULFRCO — 2.8 6 µA IEM4H 128 byte RAM retention, RTCC running from LFXO — 1.1 — µA 128 byte RAM retention, CRYOTIMER running from ULFRCO — 0.65 — µA 128 byte RAM retention, no RTCC — 0.65 1.3 µA No RAM retention, no RTCC — 0.04 0.11 µA Current consumption in EM1 IEM1 mode with all peripherals disabled Current consumption in EM2 IEM2 mode om Current consumption in EM3 IEM3 mode R ec Current consumption in EM4H mode IEM4S N ot Current consumption in EM4S mode fo r 38 MHz HFRCO, CPU running CoreMark from flash m en de d N ew Current consumption in EM0 IACTIVE mode with all peripherals disabled Test Condition D Table 4.5. Current Consumption 3.3 V without DC-DC Converter es ig ns Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = RFVDD = PAVDD = 3.3 V. T = 25 °C. EMU_PWRCFG_PWRCFG=NODCDC. EMU_DCDCCTRL_DCDCMODE=BYPASS. Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 °C. Note: 1. CMU_HFXOCTRL_LOWPOWER=0. silabs.com | Building a more connected world. Rev. 1.5 | 26 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.5.2 Current Consumption 3.3 V using DC-DC Converter Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD = 1.8 V DC-DC output. T = 25 °C. Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 °C. Table 4.6. Current Consumption 3.3 V using DC-DC Converter Min — 38 MHz HFRCO, CPU running Prime from flash — 38 MHz HFRCO, CPU running while loop from flash — 38 MHz HFRCO, CPU running CoreMark from flash — 26 MHz HFRCO, CPU running while loop from flash Max Unit 88 — µA/MHz 63 — µA/MHz 71 — µA/MHz 78 — µA/MHz — 76 — µA/MHz 38.4 MHz crystal, CPU running while loop from flash2 — 98 — µA/MHz 38 MHz HFRCO, CPU running Prime from flash — 75 — µA/MHz 38 MHz HFRCO, CPU running while loop from flash — 81 — µA/MHz 38 MHz HFRCO, CPU running CoreMark from flash — 88 — µA/MHz 26 MHz HFRCO, CPU running while loop from flash — 94 — µA/MHz Current consumption in EM1 IEM1_DCM mode with all peripherals disabled, DCDC in Low Noise DCM mode1 38.4 MHz crystal2 — 49 — µA/MHz 38 MHz HFRCO — 32 — µA/MHz 26 MHz HFRCO — 38 — µA/MHz Current consumption in EM2 IEM2 mode, DCDC in LP mode4 Full RAM retention and RTCC running from LFXO — 2.5 — µA 1 bank (4 kB) RAM retention and RTCC running from LFRCO — 2.2 — µA Current consumption in EM3 IEM3 mode Full 32 kB RAM retention and CRYOTIMER running from ULFRCO — 2.1 — µA Current consumption in EM4H mode 128 byte RAM retention, RTCC running from LFXO — 0.86 — µA 128 byte RAM retention, CRYOTIMER running from ULFRCO — 0.58 — µA 128 byte RAM retention, no RTCC — 0.58 — µA No RAM retention, no RTCC — 0.04 — µA N ot R ec om m en de d fo r Current consumption in EM0 IACTIVE_CCM mode with all peripherals disabled, DCDC in Low Noise CCM mode3 38.4 MHz crystal, CPU running while loop from flash2 Typ N ew Current consumption in EM0 IACTIVE_DCM mode with all peripherals disabled, DCDC in Low Noise DCM mode1 Test Condition es ig ns Symbol D Parameter Current consumption in EM4S mode IEM4H IEM4S silabs.com | Building a more connected world. Rev. 1.5 | 27 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit N ot R ec om m en de d fo r N ew D es ig ns Note: 1. DCDC Low Noise DCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=3.0 MHz (RCOBAND=0), ANASW=DVDD. 2. CMU_HFXOCTRL_LOWPOWER=0. 3. DCDC Low Noise CCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=6.4 MHz (RCOBAND=4), ANASW=DVDD. 4. DCDC Low Power Mode = Medium Drive (PFETCNT=NFETCNT=7), LPOSCDIV=1, LPCMPBIAS=0, LPCLIMILIMSEL=1, ANASW=DVDD. silabs.com | Building a more connected world. Rev. 1.5 | 28 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.5.3 Current Consumption 1.85 V without DC-DC Converter Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = RFVDD = PAVDD = 1.85 V. T = 25 °C. EMU_PWRCFG_PWRCFG=NODCDC. EMU_DCDCCTRL_DCDCMODE=BYPASS. Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 °C. Current consumption in EM0 IACTIVE mode with all peripherals disabled Test Condition Min 38.4 MHz crystal, CPU running while loop from flash1 — 38 MHz HFRCO, CPU running Prime from flash — 38 MHz HFRCO, CPU running while loop from flash — 38 MHz HFRCO, CPU running CoreMark from flash — Typ Max Unit 131 — µA/MHz 88 — µA/MHz 100 — µA/MHz — µA/MHz es ig ns Symbol 112 N ew Parameter D Table 4.7. Current Consumption 1.85 V without DC-DC Converter — 102 — µA/MHz 1 MHz HFRCO, CPU running while loop from flash — 220 — µA/MHz 38.4 MHz crystal1 — 65 — µA/MHz 38 MHz HFRCO — 35 — µA/MHz 26 MHz HFRCO — 37 — µA/MHz 1 MHz HFRCO — 154 — µA/MHz Full 32 kB RAM retention and RTCC running from LFXO — 3.2 — µA 1 bank (4 kB) RAM retention and RTCC running from LFRCO — 2.8 — µA Current consumption in EM3 IEM3 mode Full 32 kB RAM retention and CRYOTIMER running from ULFRCO — 2.7 — µA Current consumption in EM4H mode 128 byte RAM retention, RTCC running from LFXO — 1 — µA 128 byte RAM retention, RTCC running from LFXO, serial flash in deep power down — 0.62 — µA 128 byte RAM retention, CRYOTIMER running from ULFRCO — 0.62 — µA no RAM retention, no RTCC — 0.02 — µA m en de d Current consumption in EM1 IEM1 mode with all peripherals disabled Current consumption in EM2 IEM2 mode om IEM4H ec R Current consumption in EM4S mode fo r 26 MHz HFRCO, CPU running while loop from flash IEM4S N ot Note: 1. CMU_HFXOCTRL_LOWPOWER=0. silabs.com | Building a more connected world. Rev. 1.5 | 29 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.5.4 Current Consumption Using Radio 3.3 V with DC-DC Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD. T = 25 °C. Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 °C. Table 4.8. Current Consumption Using Radio 3.3 V with DC-DC Test Condition Min Current consumption in receive mode, active packet reception (MCU in EM1 @ 38.4 MHz, peripheral clocks disabled), T ≤ 85 °C IRX_ACTIVE 500 kbit/s, 2GFSK, F = 915 MHz, Radio clock prescaled by 4 — 38.4 kbit/s, 2GFSK, F = 868 MHz, Radio clock prescaled by 4 — 38.4 kbit/s, 2GFSK, F = 490 MHz, Radio clock prescaled by 4 — 50 kbit/s, 2GFSK, F = 433 MHz, Radio clock prescaled by 4 — 38.4 kbit/s, 2GFSK, F = 315 MHz, Radio clock prescaled by 4 Typ Unit 10 mA 8.1 10 mA 7.9 10 mA 7.7 10 mA — 7.9 10 mA 38.4 kbit/s, 2GFSK, F = 169 MHz, Radio clock prescaled by 4 — 7.6 10 mA 1 Mbit/s, 2GFSK, F = 2.4 GHz, Radio clock prescaled by 4 — 8.7 — mA 802.15.4 receiving frame, F = 2.4 GHz, Radio clock prescaled by 3 — 9.8 — mA 500 kbit/s, 2GFSK, F = 915 MHz, Radio clock prescaled by 4 — — 10.8 mA 38.4 kbit/s, 2GFSK, F = 868 MHz, Radio clock prescaled by 4 — — 10.5 mA 38.4 kbit/s, 2GFSK, F = 490 MHz, Radio clock prescaled by 4 — — 10.8 mA 50 kbit/s, 2GFSK, F = 433 MHz, Radio clock prescaled by 4 — — 10.5 mA 38.4 kbit/s, 2GFSK, F = 315 MHz, Radio clock prescaled by 4 — — 10.9 mA 38.4 kbit/s, 2GFSK, F = 169 MHz, Radio clock prescaled by 4 — — 10.2 mA fo r N ew 8.4 m en de d IRX_ACTIVE_HT N ot R ec om Current consumption in receive mode, active packet reception (MCU in EM1 @ 38.4 MHz, peripheral clocks disabled), T > 85 °C Max es ig ns Symbol D Parameter silabs.com | Building a more connected world. Rev. 1.5 | 30 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications Min Typ Max Unit Current consumption in transmit mode (MCU in EM1 @ 38.4 MHz, peripheral clocks disabled), T ≤ 85 °C ITX F = 915 MHz, CW, 20 dBm match, External PA supply = 3.3V — 80.2 104 mA F = 915 MHz, CW, 14 dBm match, External PA supply connected to DCDC output — 35.5 40.9 mA F = 868 MHz, CW, 20 dBm match, External PA supply = 3.3V — 84.9 114 mA F = 868 MHz, CW, 14 dBm match, External PA supply connected to DCDC output — 34.5 42 mA F = 490 MHz, CW, 20 dBm match, External PA supply = 3.3V — 82.8 112 mA F = 433 MHz, CW, 10 dBm match, External PA supply connected to DC-DC output — 19.5 22.1 mA es ig ns Test Condition D Symbol N ew Parameter — 32.3 37.8 mA F = 315 MHz, CW, 14 dBm match, External PA supply connected to DCDC output — 32.5 39.4 mA F = 169 MHz, CW, 20 dBm match, External PA supply = 3.3V — 80.2 106.9 mA F = 2.4 GHz, CW, 0 dBm output power, Radio clock prescaled by 3 — 8.2 — mA F = 2.4 GHz, CW, 3 dBm output power — 16.5 — mA F = 2.4 GHz, CW, 8 dBm output power — 23.3 — mA F = 2.4 GHz, CW, 10.5 dBm output power — 32.7 — mA F = 2.4 GHz, CW, 16.5 dBm output power, PAVDD connected directly to external 3.3V supply — 83.9 — mA F = 2.4 GHz, CW, 19.5 dBm output power, PAVDD connected directly to external 3.3V supply — 126.7 — mA N ot R ec om m en de d fo r F = 433 MHz, CW, 14 dBm match, External PA supply connected to DCDC output silabs.com | Building a more connected world. Rev. 1.5 | 31 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications Min Typ Max Unit Current consumption in transmit mode (MCU in EM1 @ 38.4 MHz, peripheral clocks disabled), T > 85 °C ITX_HT F = 915 MHz, CW, 20 dBm match, External PA supply = 3.3V — — 108.5 mA F = 915 MHz, CW, 14 dBm match, External PA supply connected to DCDC output — — 42.9 mA F = 868 MHz, CW, 20 dBm match, External PA supply = 3.3V — — 118.2 mA F = 868 MHz, CW, 14 dBm match, External PA supply connected to DCDC output — — 42 mA F = 490 MHz, CW, 20 dBm match, External PA supply = 3.3V — — 117 mA F = 433 MHz, CW, 10 dBm match, External PA supply connected to DC-DC output — — 23 mA es ig ns Test Condition D Symbol N ew Parameter — — 37.8 mA F = 315 MHz, CW, 14 dBm match, External PA supply connected to DCDC output — — 39.4 mA — — 110.7 mA Min Typ Max Unit — 3 — AHB Clocks Code execution from flash — 10.7 — µs Code execution from RAM — 3 — µs Code execution from flash — 10.7 — µs Code execution from RAM — 3 — µs tEM4H_WU Executing from flash — 60 — µs tEM4S_WU Executing from flash — 290 — µs fo r F = 433 MHz, CW, 14 dBm match, External PA supply connected to DCDC output 4.1.6 Wake Up Times m en de d F = 169 MHz, CW, 20 dBm match, External PA supply = 3.3V Table 4.9. Wake Up Times Symbol Wake up time from EM1 tEM1_WU Wake up from EM2 tEM2_WU om Parameter tEM3_WU ec Wake up from EM3 R Wake up from EM4H1 Wake up from EM4S1 Test Condition N ot Note: 1. Time from wake up request until first instruction is executed. Wakeup results in device reset. silabs.com | Building a more connected world. Rev. 1.5 | 32 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.7 Brown Out Detector (BOD) Table 4.10. Brown Out Detector (BOD) Symbol Test Condition Min Typ Max Unit DVDD BOD threshold VDVDDBOD DVDD rising — — 1.62 V DVDD falling 1.35 — — V 24 — mV 2.4 — µs — 1.85 V — — V VDVDDBOD_HYST — DVDD BOD response time tDVDDBOD_DELAY Supply drops at 0.1V/µs rate — AVDD BOD threshold VAVDDBOD AVDD rising — AVDD falling 1.62 VAVDDBOD_HYST — 21 — mV AVDD BOD response time tAVDDBOD_DELAY Supply drops at 0.1V/µs rate — 2.4 — µs EM4 BOD threshold VEM4DBOD — — 1.7 V 1.45 — — V — 46 — mV — 300 — µs N ew AVDD BOD hysteresis D DVDD BOD hysteresis es ig ns Parameter AVDD rising AVDD falling EM4 BOD response time tEM4BOD_DELAY Supply drops at 0.1V/µs rate fo r VEM4BOD_HYST N ot R ec om m en de d EM4 BOD hysteresis silabs.com | Building a more connected world. Rev. 1.5 | 33 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.8 Frequency Synthesizer Table 4.11. Frequency Synthesizer Symbol Test Condition Min Typ Max Unit RF synthesizer frequency range fRANGE 2400 - 2483.5 MHz 2400 — 2483.5 MHz 779 - 956 MHz 779 — 956 MHz 390 - 574 MHz 390 — 574 MHz 195 - 358 MHz 195 — 358 MHz 110 - 191 MHz 110 — 191 MHz — 73 Hz 2400 - 2483.5 MHz — 779 - 956 MHz — D fRES — 24 Hz 390 - 574 MHz — — 12.2 Hz — — 7.3 Hz — — 4.6 Hz — — 73 Hz — — 24 Hz 390 - 574 MHz — — 12.2 Hz 195 - 358 MHz — — 7.3 Hz 110 - 191 MHz — — 4.6 Hz 2400 - 2483.5 MHz — — 1677 kHz 779 - 956 MHz — — 559 kHz 390 - 574 MHz — — 280 kHz 195 - 358 MHz — — 167 kHz 110 - 191 MHz — — 105 kHz 195 - 358 MHz 110 - 191 MHz dfRES 2400 - 2483.5 MHz 779 - 956 MHz dfMAX N ot R ec om Maximum frequency deviation with 38.4 MHz crystal m en de d fo r Frequency deviation resolution with 38.4 MHz crystal N ew LO tuning frequency resolution with 38.4 MHz crystal es ig ns Parameter silabs.com | Building a more connected world. Rev. 1.5 | 34 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.9 2.4 GHz RF Transceiver Characteristics 4.1.9.1 RF Transmitter General Characteristics for 2.4 GHz Band Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD. RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 2.45 GHz. Symbol Test Condition Min Maximum TX power1 POUTMAX 19 dBm-rated part numbers. PAVDD connected directly to external 3.3V supply2 — 16 dBm-rated part numbers. PAVDD connected directly to external 3.3V supply — 8 dBm-rated part numbers — Typ Max Unit 19.5 — dBm 16.5 — dBm 8 — dBm -30 — dBm N ew D Parameter es ig ns Table 4.12. RF Transmitter General Characteristics for 2.4 GHz Band POUTMIN CW Output power step size POUTSTEP -5 dBm< Output power < 0 dBm — 1 — dB 0 dBm < output power < POUTMAX — 0.5 — dB — 4.5 — dB 1.85 V < VVREGVDD < 3.3 V using DC-DC converter — 2.2 — dB From -40 to +85 °C, PAVDD connected to DC-DC output — 1.5 — dB From -40 to +125 °C, PAVDD connected to DC-DC output — 2.2 — dB From -40 to +85 °C, PAVDD connected to external supply — 1.5 — dB From -40 to +125 °C, PAVDD connected to external supply — 3.4 — dB Over RF tuning frequency range — 0.4 — dB 2400 — 2483.5 MHz POUTVAR_T om Output power variation vs temperature at POUTMAX POUTVAR_V ec Output power variation vs RF POUTVAR_F frequency at POUTMAX RF tuning frequency range 1.85 V < VVREGVDD < 3.3 V, PAVDD connected directly to external supply, for output power > 10.5 dBm. m en de d Output power variation vs supply at POUTMAX fo r Minimum active TX Power FRANGE N ot R Note: 1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices covered in this datasheet can be found in the Max TX Power column of the Ordering Information Table. 2. For Bluetooth, the Maximum TX power on Channel 2456 is limited to +15 dBm to comply with In-band Spurious emissions. silabs.com | Building a more connected world. Rev. 1.5 | 35 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.9.2 RF Receiver General Characteristics for 2.4 GHz Band Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD. RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 2.45 GHz. Table 4.13. RF Receiver General Characteristics for 2.4 GHz Band RF tuning frequency range FRANGE Receive mode maximum spurious emission SPURRX Test Condition Min 2400 — 1 GHz to 12 GHz — Max spurious emissions dur- SPURRX_FCC ing active receive mode, per FCC Part 15.109(a) 216 MHz to 960 MHz, Conducted Measurement — Above 960 MHz, Conducted Measurement — 1% PER sensitivity 2 Mbps 2GFSK signal1 — SENS2GFSK 250 kbps 2GFSK signal — Max Unit — 2483.5 MHz -57 — dBm -47 — dBm -55.2 — dBm -47.2 — dBm -89.2 — dBm — dBm N ew 30 MHz to 1 GHz Typ es ig ns Symbol D Parameter -99.1 N ot R ec om m en de d fo r Note: 1. Channel at 2420 MHz will have degraded sensitivity. Sensitivity could be as high as -83 dBm on this channel. silabs.com | Building a more connected world. Rev. 1.5 | 36 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.9.3 RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4GHz Band, 1 Mbps Data Rate Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD. RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4MHz. RF center frequency 2.45 GHz. Maximum duty cycle of 85%. Test Condition Max Unit Transmit 6dB bandwidth TXBW 10 dBm — 740 — kHz Power spectral density limit PSDLIMIT Per FCC part 15.247 at 10 dBm — -6.5 — dBm/ 3kHz Per FCC part 15.247 at 20 dBm — -2.6 — dBm/ 3kHz Per ETSI 300.328 at 10 dBm/1 MHz — 10 — dBm Occupied channel bandwidth OCPETSI328 per ETSI EN300.328 99% BW at highest and lowest channels in band, 10 dBm — 1.1 — MHz In-band spurious emissions, with allowed exceptions1 At ± 2 MHz, 10 dBm — -39.8 — dBm — -42.1 — dBm — — -20 dBm At ± 3 MHz, 20 dBm2 — — -30 dBm 2nd,3rd, 5, 6, 8, 9,10 harmonics; continuous transmission of modulated carrier — -47 — dBm Per FCC part 15.205/15.209, Above 2.483 GHz or below 2.4 GHz; continuous transmission of CW carrier, Restricted Bands3 — -47 — dBm Per FCC part 15.247, Above 2.483 GHz or below 2.4 GHz; continuous transmission of CW carrier, Non-Restricted Bands — -26 — dBc [2400-BW to 2400] MHz, [2483.5 to 2483.5+BW] MHz — -16 — dBm [2400-2BW to 2400-BW] MHz, [2483.5+BW to 2483.5+2BW] MHz per ETSI 300.328 — -26 — dBm 47-74 MHz,87.5-108 MHz, 174-230 MHz, 470-862 MHz — -60 — dBm 25-1000 MHz — -42 — dBm 1-12 GHz — -36 — dBm At ± 3 MHz, 10 dBm SPURHRM_FCC Spurious emissions out-ofband, excluding harmonics captured in SPURHARM,FCC. Emissions taken at POUTMAX, PAVDD connected to external 3.3 V supply SPUROOB_FCC Spurious emissions out-ofband; per ETSI 300.328 SPURETSI328 ec om m en de d Emissions of harmonics outof-band, per FCC part 15.247 fo r At ± 2 MHz, 20 dBm2 Min N ot R Spurious emissions per ETSI SPURETSI440 EN300.440 es ig ns Symbol N ew Parameter SPURINB Typ D Table 4.14. RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4GHz Band, 1 Mbps Data Rate Note: 1. Per Bluetooth Core_5.0, Vol.6 Part A, Section 3.2.2, exceptions are allowed in up to three bands of 1 MHz width, centered on a frequency which is an integer multiple of 1 MHz. These exceptions shall have an absolute value of -20 dBm or less. 2. For 2456 MHz, a maximum output power of 15 dBm is used to achieve this value. 3. For 2480 MHz, a maximum duty cycle of 20% is used to achieve this value. silabs.com | Building a more connected world. Rev. 1.5 | 37 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.9.4 RF Receiver Characteristics for Bluetooth Low Energy in the 2.4GHz Band, 1 Mbps Data Rate Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD. RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4MHz. RF center frequency 2.45 GHz. Table 4.15. RF Receiver Characteristics for Bluetooth Low Energy in the 2.4GHz Band, 1 Mbps Data Rate Test Condition Min Max usable receiver input level, 0.1% BER SAT Signal is reference signal1. Packet length is 20 bytes. — Sensitivity, 0.1% BER2 SENS Signal is reference signal1. Using DC-DC converter. — With non-ideal signals as specified in RF-PHY.TS.4.2.2, section 4.6.1. — Signal to co-channel interfer- C/ICC er, 0.1% BER Desired signal 3 dB above reference sensitivity. — N+1 adjacent channel selec- C/I1+ tivity, 0.1% BER, with allowable exceptions. Desired is reference signal at -67 dBm Interferer is reference signal at +1 MHz offset. Desired frequency 2402 MHz ≤ Fc ≤ 2480 MHz — N-1 adjacent channel selec- C/I1tivity, 0.1% BER, with allowable exceptions. Desired is reference signal at -67 dBm Interferer is reference signal at -1 MHz offset. Desired frequency 2402 MHz ≤ Fc ≤ 2480 MHz Alternate selectivity, 0.1% BER, with allowable exceptions. Desired is reference signal at -67 dBm C/I2 Alternate selectivity, 0.1% BER, with allowable exceptions. Desired is reference signal at -67 dBm C/I3 Typ Max Unit es ig ns Symbol 10 — dBm -92.5 — dBm -92 — dBm D Parameter — dB -3 — dB — -0.5 — dB Interferer is reference signal at ± 2 MHz offset. Desired frequency 2402 MHz ≤ Fc ≤ 2480 MHz — -43 — dB Interferer is reference signal at ± 3 MHz offset. Desired frequency 2404 MHz ≤ Fc ≤ 2480 MHz — -46.7 — dB Selectivity to image frequen- C/IIM cy, 0.1% BER. Desired is reference signal at -67 dBm Interferer is reference signal at image frequency with 1 MHz precision — -38.7 — dB Selectivity to image frequency ± 1 MHz, 0.1% BER. Desired is reference signal at -67 dBm Interferer is reference signal at image frequency ± 1 MHz with 1 MHz precision — -48.2 — dB Interferer frequency 30 MHz ≤ f ≤ 2000 MHz -5 — — dBm Interferer frequency 2003 MHz ≤ f ≤ 2399 MHz4 -10 — — dBm Interferer frequency 2484 MHz ≤ f ≤ 2997 MHz -10 — — dBm Interferer frequency 3 GHz ≤ f ≤ 6 GHz -10 — — dBm Interferer frequency 6 GHz ≤ f ≤ 12.75 GHz -17 — — dBm Per Core_4.1, Vol 6, Part A, Section 4.4 with n = 3 — -25.8 — dBm N ew fo r m en de d ec om C/IIM+1 N ot R Blocking, less than 0.1% BLOCKOOB BER. Desired is -67dBm BLE reference signal at 2426MHz. Interferer is CW in OOB range3 Intermodulation performance IM silabs.com | Building a more connected world. 8.3 Rev. 1.5 | 38 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit N ot R ec om m en de d fo r N ew D es ig ns Note: 1. Reference signal is defined 2GFSK at -67 dBm, Modulation index = 0.5, BT = 0.5, Bit rate = 1 Mbps, desired data = PRBS9; interferer data = PRBS15; frequency accuracy better than 1 ppm. 2. Receive sensitivity on Bluetooth Low Energy channel 26 is -86 dBm. 3. Interferer max power limited by equipment capabilities and path loss. Minimum specified at 25 °C. 4. Except -13 dBm at Desired Frequency - Crystal Frequency. silabs.com | Building a more connected world. Rev. 1.5 | 39 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.9.5 RF Transmitter Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD. RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 2.45 GHz. Maximum duty cycle of 66%. Symbol Test Condition Min Max Unit Error vector magnitude (offset EVM), per 802.15.4-2011, not including 2415 MHz channel1 EVM Average across frequency. Signal is DSSS-OQPSK reference packet2 — 5.5 — % rms Power spectral density limit PSDLIMIT Relative, at carrier ± 3.5 MHz, output power at POUTMAX — -26 — dBc/ 100kHz Absolute, at carrier ± 3.5 MHz, output power at POUTMAX3 — -36 — dBm/ 100kHz Per FCC part 15.247, output power at POUTMAX — -4.2 — dBm/ 3kHz ETSI — 12 — dBm — 2.25 — MHz — -45.8 — dBm N ew Parameter es ig ns Typ D Table 4.16. RF Transmitter Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band 99% BW at highest and lowest channels in band Spurious emissions of harSPURHRM_FCC_ monics in restricted bands R per FCC Part 15.205/15.209, Emissions taken at POUTMAX, PAVDD connected to external 3.3 V supply, Test Frequency is 2450 MHz Continuous transmission of modulated carrier Spurious emissions of harSPURHRM_FCC_ monics in non-restricted NRR bands per FCC Part 15.247/15.35, Emissions taken at POUTMAX, PAVDD connected to external 3.3 V supply, Test Frequency is 2450 MHz Continuous transmission of modulated carrier — -26 — dBc Spurious emissions out-ofband (above 2.483 GHz or below 2.4 GHz) in restricted bands, per FCC part 15.205/15.209, Emissions taken at POUTMAX, PAVDD connected to external 3.3 V supply, Test Frequency = 2450 MHz Restricted bands 30-88 MHz; continuous transmission of modulated carrier — -52 — dBm Restricted bands 88-216 MHz; continuous transmission of modulated carrier — -62 — dBm Restricted bands 216-960 MHz; continuous transmission of modulated carrier — -57 — dBm Restricted bands >960 MHz; continuous transmission of modulated carrier4 — -48 — dBm om m en de d fo r Occupied channel bandwidth OCPETSI328 per ETSI EN300.328 SPUROOB_FCC_ N ot R ec R silabs.com | Building a more connected world. Rev. 1.5 | 40 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications Test Condition Min Typ Max Unit -26 — dBc Above 2.483 GHz or below 2.4 GHz; continuous transmission of modulated carrier — Spurious emissions out-ofband; per ETSI 300.3285 [2400-BW to 2400], [2483.5 to 2483.5+BW]; — [2400-2BW to 2400-BW], [2483.5+BW to 2483.5+2BW]; per ETSI 300.328 — 47-74 MHz,87.5-108 MHz, 174-230 MHz, 470-862 MHz — 25-1000 MHz, excluding above frequencies — SPURETSI328 Spurious emissions per ETSI SPURETSI440 EN300.4405 -16 — dBm -26 — dBm -60 — dBm — dBm — dBm -42 N ew SPUROOB_FCC_ Spurious emissions out-ofband in non-restricted bands NR per FCC Part 15.247, Emissions taken at POUTMAX, PAVDD connected to external 3.3 V supply, Test Frequency = 2450 MHz es ig ns Symbol D Parameter 1G-14G — -36 N ot R ec om m en de d fo r Note: 1. Typical EVM for the 2415 MHz channel is 7.9%. 2. Reference packet is defined as 20 octet PSDU, modulated according to 802.15.4-2011 DSSS-OQPSK in the 2.4GHz band, with pseudo-random packet data content. 3. For 2415 MHz, a maximum duty cycle of 50% is used to achieve this value. 4. For 2480 MHz, a maximum duty cycle of 20% is used to achieve this value. 5. Specified at maximum power output level of 10 dBm. silabs.com | Building a more connected world. Rev. 1.5 | 41 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.9.6 RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD. RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 2.45 GHz. Table 4.17. RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band Test Condition Min Max usable receiver input level, 1% PER SAT Signal is reference signal1. Packet length is 20 octets. — Sensitivity, 1% PER2 SENS Signal is reference signal. Packet length is 20 octets. Using DC-DC converter. — Signal is reference signal. Packet length is 20 octets. Without DCDC converter. — Typ Max Unit es ig ns Symbol 10 — dBm -99 — dBm -99 — dBm D Parameter — dB CCR Desired signal 3 dB above sensitivity limit — High-side adjacent channel rejection, 1% PER. Desired is reference signal at 3dB above reference sensitivity level3 ACRP1 Interferer is reference signal at +1 channel-spacing. — 33.75 — dB Interferer is filtered reference signal4 at +1 channel-spacing. — 52.2 — dB Interferer is CW at +1 channelspacing5. — 58.6 — dB Interferer is reference signal at -1 channel-spacing. — 35 — dB Interferer is filtered reference signal4 at -1 channel-spacing. — 54.7 — dB Interferer is CW at -1 channelspacing. — 60.1 — dB Interferer is reference signal at ± 2 channel-spacing — 45.9 — dB Interferer is filtered reference signal4 at ± 2 channel-spacing — 56.8 — dB Interferer is CW at ± 2 channelspacing — 65.5 — dB Interferer is CW in image band5 — 49.3 — dB Blocking rejection of all other BLOCK channels. 1% PER, Desired is reference signal at 3dB above reference sensitivity level3. Interferer is reference signal Interferer frequency < Desired frequency - 3 channel-spacing — 57.2 — dB Interferer frequency > Desired frequency + 3 channel-spacing — 57.9 — dB Blocking rejection of 802.11g BLOCK80211G signal centered at +12MHz or -13MHz6 Desired is reference signal at 6dB above reference sensitivity level3 — 51.6 — dB ACR2 om Alternate channel rejection, 1% PER. Desired is reference signal at 3dB above reference sensitivity level3 fo r ACRM1 m en de d Low-side adjacent channel rejection, 1% PER. Desired is reference signal at 3dB above reference sensitivity level3 N ot R ec Image rejection , 1% PER, IR Desired is reference signal at 3dB above reference sensitivity level3 -2.6 N ew Co-channel interferer rejection, 1% PER silabs.com | Building a more connected world. Rev. 1.5 | 42 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications Symbol Min Typ Max Unit RSSIMAX Upper limit of input power range over which RSSI resolution is maintained — — 5 dBm RSSIMIN Lower limit of input power range over which RSSI resolution is maintained -98 — — dBm RSSI resolution RSSIRES RSSI accuracy in the linear region as defined by 802.15.4-2003 RSSILIN Test Condition over RSSIMIN to RSSIMAX — — es ig ns Parameter 0.25 — dB +/-1 — dB N ot R ec om m en de d fo r N ew D Note: 1. Reference signal is defined as O-QPSK DSSS per 802.15.4, Frequency range = 2400-2483.5 MHz, Symbol rate = 62.5 ksymbols/s. 2. Receive sensitivity on 802.15.4 channel 14 is -98 dBm 3. Reference sensitivity level is -85 dBm. 4. Filter is characterized as a symmetric bandpass centered on the adjacent channel having a 3dB bandwidth of 4.6 MHz and stopband rejection better than 26 dB beyond 3.15 MHz from the adjacent carrier. 5. Due to low-IF frequency, there is some overlap of adjacent channel and image channel bands. Adjacent channel CW blocker tests place the Interferer center frequency at the Desired frequency ± 5 MHz on the channel raster, whereas the image rejection test places the CW interferer near the image frequency of the Desired signal carrier, regardless of the channel raster. 6. This is an IEEE 802.11b/g ERP-PBCC 22 MBit/s signal as defined by the IEEE 802.11 specification and IEEE 802.11g addendum. silabs.com | Building a more connected world. Rev. 1.5 | 43 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications N ot R ec om m en de d fo r N ew D es ig ns 4.1.10 Sub-GHz RF Transceiver Characteristics silabs.com | Building a more connected world. Rev. 1.5 | 44 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.10.1 Sub-GHz RF Transmitter characteristics for 915 MHz Band Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 915 MHz. Table 4.18. Sub-GHz RF Transmitter characteristics for 915 MHz Band Symbol RF tuning frequency range FRANGE Maximum TX Power1 POUTMAX Test Condition Min 902 External PA supply = 3.3V, 20 dBm output power setting 17.7 External PA supply connected to DC-DC output, 14 dBm output power setting 10.4 Max Unit — 930 MHz 20.3 24.5 dBm 13.8 17.6 dBm -45.5 — dBm 0.5 — dB POUTMIN Output power step size POUTSTEP output power > 0 dBm Output power variation vs supply at POUTMAX POUTVAR_V 1.8 V < VVREGVDD < 3.3 V, External PA supply = 3.3 V, T = 25 °C — 4.8 — dB 1.8 V < VVREGVDD < 3.3 V, External PA supply connected to DCDC output, T = 25 °C — 1.9 — dB -40 to +85 °C with External PA supply = 3.3 V — 0.6 1.3 dB -40 to +125 °C with External PA supply = 3.3 V — 0.8 1.6 dB -40 to +85 °C with External PA supply connected to DC-DC output — 0.7 1.4 dB -40 to +125 °C with External PA supply connected to DC-DC output — 1.0 1.9 dB External PA supply = 3.3 V, T = 25 °C — 0.2 0.6 dB External PA supply connected to DC-DC output, T = 25 °C — 0.3 0.6 dB SPURHARM_FCC In restricted bands, per FCC Part 15.205 / 15.209 — -64.6 -47 dBm — -64.2 -42 dBc N ew fo r m en de d POUTVAR_T — om Output power variation vs RF POUTVAR_F frequency _20 In non-restricted bands, per FCC Part 15.247 N ot R ec Spurious emissions of harmonics at 20 dBm output power, Conducted measurement, 20dBm match, External PA supply = 3.3V, Test Frequency = 915 MHz D Minimum active TX Power Output power variation vs temperature, peak to peak — Typ es ig ns Parameter silabs.com | Building a more connected world. Rev. 1.5 | 45 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications Typ Max Unit In non-restricted bands, per FCC Part 15.247 — -76.2 -66 dBc In restricted bands (30-88 MHz), per FCC Part 15.205 / 15.209 — -68.8 -56 dBm In restricted bands (88-216 MHz), per FCC Part 15.205 / 15.209 — -67.7 -62 dBm In restricted bands (216-960 MHz), per FCC Part 15.205 / 15.209 — In restricted bands (>960 MHz), per FCC Part 15.205 / 15.209 — -69.1 -58 dBm -54.6 -42.4 dBm -75.2 -60 dBm -49 dBc SPURHARM_FCC In restricted bands, per FCC Part 15.205 / 15.209 _14 — In non-restricted bands, per FCC Part 15.247 — In non-restricted bands, per FCC Part 15.247 — -87.5 -66 dBc In restricted bands (30-88 MHz), per FCC Part 15.205 / 15.209 — -74.2 -56 dBm In restricted bands (88-216 MHz), per FCC Part 15.205 / 15.209 — -73.1 -67 dBm In restricted bands (216-960 MHz), per FCC Part 15.205 / 15.209 — -74.3 -58 dBm In restricted bands (>960 MHz), per FCC Part 15.205 / 15.209 — -60.2 -49 dBm m en de d Spurious emissions out-ofSPUROOB_FCC_ band at 14 dBm output pow- 14 er, Conducted measurement, 14dBm match, External PA supply connected to DC-DC output, Test Frequency = 915 MHz -69 N ew Spurious emissions of harmonics at 14 dBm output power, Conducted measurement, 14dBm match, External PA supply connected to DC-DC output, Test Frequency = 915 MHz Min es ig ns SPUROOB_FCC_ Spurious emissions out-ofband at 20 dBm output pow- 20 er, Conducted measurement, 20dBm match, External PA supply = 3.3V, Test Frequency = 915 MHz Test Condition D Symbol fo r Parameter N ot R ec om Note: 1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices covered in this datasheet can be found in the Max TX Power column of the Ordering Information Table. silabs.com | Building a more connected world. Rev. 1.5 | 46 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.10.2 Sub-GHz RF Receiver Characteristics for 915 MHz Band Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 915 MHz. Table 4.19. Sub-GHz RF Receiver Characteristics for 915 MHz Band Symbol Tuning frequency range FRANGE Test Condition Min 902 Typ Max Unit es ig ns Parameter — 930 MHz — 10 dBm Desired is reference 500 kbps GFSK signal1 — Sensitivity Desired is reference 4.8 kbps OOK signal2, 20% PER, T ≤ 85 °C — -104.7 -100.7 dBm Desired is reference 4.8 kbps OOK signal2, 20% PER, T > 85 °C — — -99.5 dBm Desired is reference 600 bps GFSK signal3, 0.1% BER — -126.4 — dBm Desired is reference 50 kbps GFSK signal4, 0.1% BER, T ≤ 85 °C — -107.5 -104.2 dBm Desired is reference 50 kbps GFSK signal4, 0.1% BER, T > 85 °C — — -103 dBm Desired is reference 100 kbps GFSK signal5, 0.1% BER, T ≤ 85 °C — -105.1 -101.5 dBm Desired is reference 100 kbps GFSK signal5, 0.1% BER, T > 85 °C — — -101.3 dBm Desired is reference 500 kbps GFSK signal1, 0.1% BER, T ≤ 85 °C — -97.7 -93.2 dBm Desired is reference 500 kbps GFSK signal1, 0.1% BER, T > 85 °C — — -93 dBm Desired is reference 400 kbps 4GFSK signal6, 1% PER, T ≤ 85 °C — -90.9 -87.5 dBm Desired is reference 400 kbps 4GFSK signal6, 1% PER, T > 85 °C — — -86.9 dBm N ot R ec om m en de d fo r N ew SENS D Max usable input level, 0.1% SAT500K BER silabs.com | Building a more connected world. Rev. 1.5 | 47 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications Adjacent channel selectivity, Interferer is CW at ± 1 × channel-spacing C/I1 Typ Max Unit Desired is 4.8 kbps OOK signal2 at 3dB above sensitivity level, 20% PER — 43.7 — dB Desired is 600 bps GFSK signal3 at 3dB above sensitivity level, 0.1% BER — 65.76 — dB Desired is 50 kbps GFSK signal4 at 3dB above sensitivity level, 0.1% BER — 48.24 — dB Desired is 100 kbps GFSK signal5 at 3dB above sensitivity level, 0.1% BER — 51.1 — dB Desired is 500 kbps GFSK signal1 at 3dB above sensitivity level, 0.1% BER — 47 — dB Desired is 400 kbps 4GFSK signal6 at 3dB above sensitivity level, 0.1% BER — 35.9 — dB Desired is 4.8 kbps OOK signal2 at 3dB above sensitivity level, 20% PER — 57.2 — dB Desired is 600 bps GFSK signal3 at 3dB above sensitivity level, 0.1% BER — 71.76 — dB Desired is 50 kbps GFSK signal4 at 3dB above sensitivity level, 0.1% BER — 53.6 — dB Desired is 100 kbps GFSK signal5 at 3dB above sensitivity level, 0.1% BER — 56.9 — dB Desired is 500 kbps GFSK signal1 at 3dB above sensitivity level, 0.1% BER — 53.6 — dB Desired is 400 kbps 4GFSK signal6 at 3dB above sensitivity level, 0.1% BER — 44 — dB N ot R ec om m en de d fo r Alternate channel selectivity, C/I2 Interferer is CW at ± 2 × channel-spacing Min es ig ns Test Condition D Symbol N ew Parameter silabs.com | Building a more connected world. Rev. 1.5 | 48 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications Image rejection, Interferer is CW at image frequency C/IIMAGE C/IBLOCKER Intermod selectivity, 0.1% BER. CW interferers at 400 kHz and 800 kHz offsets C/IIM Typ Max Unit Desired is 4.8 kbps OOK signal2 at 3dB above sensitivity level, 20% PER — 41.2 — dB Desired is 50 kbps GFSK signal4 at 3dB above sensitivity level, 0.1% BER — 52.4 — dB Desired is 100 kbps GFSK signal5 at 3dB above sensitivity level, 0.1% BER — 50.35 — dB Desired is 500 kbps GFSK signal1 at 3dB above sensitivity level, 0.1% BER — 46.2 — dB Desired is 400 kbps 4GFSK signal6 at 3dB above sensitivity level, 0.1% BER — 35.9 — dB Interferer CW at Desired ± 1 MHz — 58.7 — dB Interferer CW at Desired ± 2 MHz — 60.9 — dB Interferer CW at Desired ± 10 MHz — 76.4 — dB Desired is 100 kbps GFSK signal5 at 3dB above sensitivity level — 46.1 — dB — — 5 dBm -98 — — dBm Over RSSIMIN to RSSIMAX range — 0.25 — dBm Max spurious emissions dur- SPURRX_FCC ing active receive mode, per FCC Part 15.109(a) 216-960 MHz — -77.7 -49.2 dBm Above 960 MHz — -62.7 -51.7 dBm Max spurious emissions dur- SPURRX_ARIB ing active receive mode,per ARIB STD-T108 Section 3.3 Below 710 MHz, RBW=100kHz — -77.7 -60 dBm 710-900 MHz, RBW=1MHz — -75.8 -61 dBm 900-915 MHz, RBW=100kHz — -85.4 -61 dBm 915-930 MHz, RBW=100kHz — -85.6 -55 dBm 930-1000 MHz, RBW=100kHz — -85.1 -60 dBm Above 1000 MHz, RBW=1MHz — -57.9 -47 dBm fo r Blocking selectivity, 0.1% BER. Desired is 100 kbps GFSK signal at 3dB above sensitivity level Min es ig ns Test Condition D Symbol N ew Parameter m en de d Upper limit of input power RSSIMAX range over which RSSI resolution is maintained Lower limit of input power RSSIMIN range over which RSSI resolution is maintained RSSIRES N ot R ec om RSSI resolution silabs.com | Building a more connected world. Rev. 1.5 | 49 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit N ot R ec om m en de d fo r N ew D es ig ns Note: 1. Definition of reference signal is 500 kbps 2GFSK, BT=0.5, Δf = 175 kHz, RX channel BW = 2524.8 kHz, channel spacing = 1 MHz. 2. Definition of reference signal is 4.8 kbps OOK, RX channel BW = 315.6 kHz, channel spacing = 500 kHz. 3. Definition of reference signal is 600 bps 2GFSK, BT=0.5, Δf = 0.3 kHz, RX channel BW = 1262 Hz, channel spacing = 300 kHz. 4. Definition of reference signal is 50 kbps 2GFSK, BT=0.5, Δf = 25 kHz, RX channel BW = 120.229 kHz, channel spacing = 200 kHz. 5. Definition of reference signal is 100 kbps 2GFSK, BT=0.5, Δf = 50 kHz, RX channel BW = 210.4 kHz, channel spacing = 400 kHz. 6. Definition of reference signal is 400 kbps 4GFSK, BT=0.5, inner deviation = 33.3 kHz, RX channel BW = 336.64 kHz, channel spacing = 600 kHz. silabs.com | Building a more connected world. Rev. 1.5 | 50 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.10.3 Sub-GHz RF Transmitter characteristics for 868 MHz Band Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 868 MHz. Table 4.20. Sub-GHz RF Transmitter characteristics for 868 MHz Band FRANGE Maximum TX Power1 POUTMAX Min 863 External PA supply = 3.3V, 20 dBm output power setting, T ≤ 85 °C 16.6 External PA supply = 3.3V, 20 dBm output power setting, T > 85 °C — External PA supply connected to DC-DC output, 14 dBm output power setting 10 POUTMIN Output power step size POUTSTEP output power > 0 dBm Output power variation vs supply at POUTMAX POUTVAR_V 1.8 V < VVREGVDD < 3.3 V, External PA supply = 3.3 V, T = 25 °C om ec Output power variation vs RF POUTVAR_F frequency — 876 MHz 19.6 23 dBm — 23.7 dBm 17.5 dBm 14.7 — dBm — 0.5 — dB — 5 — dB 1.8 V < VVREGVDD < 3.3 V, External PA supply connected to DCDC output, T = 25 °C — 2 — dB -40 to +85 °C with External PA supply = 3.3 V — 0.6 0.9 dB -40 to +125 °C with External PA supply = 3.3 V — 0.8 1.3 dB -40 to +85 °C with External PA supply connected to DC-DC output — 0.5 1.2 dB -40 to +125 °C with External PA supply connected to DC-DC output — 0.7 1.5 dB External PA supply = 3.3 V, T = 25 °C — 0.2 0.6 dB External PA supply connected to DC-DC output, T = 25 °C — 0.2 0.8 dB — -44 -30 dBm Spurious emissions of harSPURHARM_ETSI Per ETSI EN 300-220, Section monics, Conducted meas7.8.2.1 urement, External PA supply connected to DC-DC output, Test Frequency = 868 MHz N ot R Unit -43.5 m en de d POUTVAR_T Max — fo r Minimum active TX Power Output power variation vs temperature, peak to peak Typ es ig ns RF tuning frequency range Test Condition D Symbol N ew Parameter silabs.com | Building a more connected world. Rev. 1.5 | 51 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications Symbol Test Condition Min Typ Max Unit Spurious emissions out-ofband, Conducted measurement, External PA supply connected to DC-DC output, Test Frequency = 868 MHz SPUROOB_ETSI Per ETSI EN 300-220, Section 7.8.2.1 (47-74 MHz, 87.5-118 MHz, 174-230 MHz, and 470-862 MHz) — -61.7 -55.7 dBm Per ETSI EN 300-220, Section 7.8.2.1 (other frequencies below 1 GHz) — -64.2 -43.5 dBm Per ETSI EN 300-220, Section 7.8.2.1 (frequencies above 1 GHz) — es ig ns Parameter -59.9 -30 dBm N ot R ec om m en de d fo r N ew D Note: 1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices covered in this datasheet can be found in the Max TX Power column of the Ordering Information Table. silabs.com | Building a more connected world. Rev. 1.5 | 52 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.10.4 Sub-GHz RF Receiver Characteristics for 868 MHz Band Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 868 MHz. Table 4.21. Sub-GHz RF Receiver Characteristics for 868 MHz Band Symbol Tuning frequency range FRANGE Test Condition Min 863 Typ Max Unit es ig ns Parameter — 876 MHz — 10 dBm — 10 dBm -121.4 -116.5 dBm -105.4 dBm Desired is reference 2.4 kbps GFSK signal1 — Max usable input level, 0.1% SAT38k4 BER Desired is reference 38.4 kbps GFSK signal2 — Sensitivity Desired is reference 2.4 kbps GFSK signal1, 0.1% BER — Desired is reference 38.4 kbps GFSK signal2, 0.1% BER, T ≤ 85 °C — Desired is reference 38.4 kbps GFSK signal2, 0.1% BER, T > 85 °C — — -105.2 dBm Desired is reference 500 kbps GFSK signal3, 0.1% BER — -95.1 — dBm Desired is 2.4 kbps GFSK signal1 at 3dB above sensitivity level, 0.1% BER 48.5 57.7 — dB Desired is 38.4kbps GFSK signal2 at 3dB above sensitivity level, 0.1% BER 36.4 44.9 — dB Desired is 2.4kbps GFSK signal1 at 3dB above sensitivity level, 0.1% BER — 59.1 — dB Desired is 38.4kbps GFSK signal2 at 3dB above sensitivity level, 0.1% BER — 47.7 — dB Desired is 2.4kbps GFSK signal1 at 3dB above sensitivity level, 0.1% BER — 47.5 — dB Desired is 38.4kbps GFSK signal2 at 3dB above sensitivity level, 0.1% BER — 47.2 — dB Interferer CW at Desired ± 1 MHz — 71.9 — dB Interferer CW at Desired ± 2 MHz — 77.9 — dB Interferer CW at Desired ± 10 MHz — 90.9 — dB — — 5 dBm -109.2 C/I1 m en de d Adjacent channel selectivity, Interferer is CW at ± 1 × channel-spacing om Alternate channel selectivity, C/I2 Interferer is CW at ± 2 × channel-spacing C/IIMAGE R ec Image rejection, Interferer is CW at image frequency C/IBLOCKER N ot Blocking selectivity, 0.1% BER. Desired is 2.4 kbps GFSK signal1 at 3 dB above sensitivity level fo r N ew SENS D Max usable input level, 0.1% SAT2k4 BER Upper limit of input power RSSIMAX range over which RSSI resolution is maintained silabs.com | Building a more connected world. Rev. 1.5 | 53 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Parameter Symbol Min Typ Max Unit -98 — — dBm Over RSSIMIN to RSSIMAX range — 0.25 — dBm 30 MHz to 1 GHz — -77.1 -69 dBm 1 GHz to 12 GHz — es ig ns Electrical Specifications Test Condition RSSIMIN Lower limit of input power range over which RSSI resolution is maintained RSSI resolution RSSIRES Max spurious emissions dur- SPURRX ing active receive mode -59.9 -50 dBm N ot R ec om m en de d fo r N ew D Note: 1. Definition of reference signal is 2.4 kbps 2GFSK, BT=0.5, Δf = 1.2 kHz, RX channel BW = 5.05 kHz, channel spacing = 12.5 kHz. 2. Definition of reference signal is 38.4 kbps 2GFSK, BT=0.5, Δf = 20 kHz, RX channel BW = 84.16 kHz, channel spacing = 100 kHz. 3. Definition of reference signal is 500 kbps 2GFSK, BT=0.5, Δf = 125 kHz, RX channel BW = 841.6 kHz. silabs.com | Building a more connected world. Rev. 1.5 | 54 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.10.5 Sub-GHz RF Transmitter characteristics for 490 MHz Band Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 490 MHz. Table 4.22. Sub-GHz RF Transmitter characteristics for 490 MHz Band Symbol Test Condition Min RF tuning frequency range FRANGE Maximum TX Power1 POUTMAX Minimum active TX Power POUTMIN Output power step size POUTSTEP output power > 0 dBm — Output power variation vs supply, peak to peak POUTVAR_V at 20 dBm;1.8 V < VVREGVDD < 3.3 V, External PA supply connected directly to external supply, T = 25 °C — Output power variation vs temperature, peak to peak POUTVAR_T -40 to +85 °C at 20 dBm 470 -40 to +125 °C at 20 dBm Unit 510 MHz 21.1 23 dBm -44.9 — dBm 0.5 — dB 4.3 — dB D 18.5 Max — N ew External PA supply = 3.3V Typ es ig ns Parameter — 0.2 0.9 dB — 0.3 1.3 dB — 0.2 0.4 dB T = 25 °C Harmonic emissions, 20 dBm output power setting, 490 MHz Per China SRW Requirement, Section 2.1, frequencies below 1GHz — -41.3 -34.9 dBm Per China SRW Requirement, Section 2.1, frequencies above 1GHz — -47.2 -36 dBm Per China SRW Requirement, Section 3 (48.5-72.5MHz, 76-108MHz, 167-223MHz, 470-556MHz, and 606-798MHz) — -57.5 — dBm Per China SRW Requirement, Section 2.1 (other frequencies below 1GHz) — -58.5 — dBm Per China SRW Requirement, Section 2.1 (frequencies above 1GHz) — -47.9 — dBm m en de d SPURHARM_CN fo r Output power variation vs RF POUTVAR_F frequency om Spurious emissions, 20 dBm SPUROOB_CN output power setting, 490 MHz N ot R ec Note: 1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices covered in this datasheet can be found in the Max TX Power column of the Ordering Information Table. silabs.com | Building a more connected world. Rev. 1.5 | 55 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.10.6 Sub-GHz RF Receiver Characteristics for 490 MHz Band Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 490 MHz. Table 4.23. Sub-GHz RF Receiver Characteristics for 490 MHz Band Symbol Tuning frequency range FRANGE Test Condition Min 470 Typ Max Unit es ig ns Parameter — 510 MHz — 10 dBm — 10 dBm -122.2 — dBm -108.9 dBm Desired is reference 2.4 kbps GFSK signal1 — Max usable input level, 0.1% SAT38k4 BER Desired is reference 38.4 kbps GFSK signal2 — Sensitivity Desired is reference 2.4 kbps GFSK signal1, 0.1% BER — Desired is reference 38.4 kbps GFSK signal2, 0.1% BER, T ≤ 85 °C — Desired is reference 38.4 kbps GFSK signal2, 0.1% BER, T > 85 °C — — -107.9 dBm Desired is reference 10 kbps GFSK signal3, 0.1% BER, T ≤ 85 °C — -117.5 -114.8 dBm Desired is reference 10 kbps GFSK signal3, 0.1% BER, T > 85 °C — — -113.9 dBm Desired is reference 100 kbps GFSK signal4, 0.1% BER, T ≤ 85 °C — -107.6 -104.7 dBm Desired is reference 100 kbps GFSK signal4, 0.1% BER, T > 85 °C — — -104 dBm Desired is 2.4 kbps GFSK signal1 at 3dB above sensitivity level, 0.1% BER 48 58.4 — dB Desired is 38.4kbps GFSK signal2 at 3dB above sensitivity level, 0.1% BER 38.3 47.5 — dB Desired is 2.4kbps GFSK signal1 at 3dB above sensitivity level, 0.1% BER — 60.8 — dB Desired is 38.4kbps GFSK signal2 at 3dB above sensitivity level, 0.1% BER — 51.7 — dB Desired is 2.4kbps GFSK signal1 at 3dB above sensitivity level, 0.1% BER — 60.9 — dB Desired is 38.4kbps GFSK signal2 at 3dB above sensitivity level, 0.1% BER — 53 — dB -111.7 C/I1 ec om Adjacent channel selectivity, Interferer is CW at ± 1 × channel-spacing m en de d fo r N ew SENS D Max usable input level, 0.1% SAT2k4 BER N ot R Alternate channel selectivity, C/I2 Interferer is CW at ± 2 × channel-spacing Image rejection, Interferer is CW at image frequency C/IIMAGE silabs.com | Building a more connected world. Rev. 1.5 | 56 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications Test Condition Min Typ Max Unit Blocking selectivity, 0.1% BER. Desired is 2.4 kbps GFSK signal1 at 3 dB above sensitivity level C/IBLOCKER Interferer CW at Desired ± 1 MHz — 71.9 — dB Interferer CW at Desired ± 2 MHz — 74.1 — dB Interferer CW at Desired ± 10 MHz — 87.9 — dB RSSIMAX Upper limit of input power range over which RSSI resolution is maintained — — 5 dBm RSSIMIN Lower limit of input power range over which RSSI resolution is maintained -98 — — dBm 0.25 — dBm -84.7 -54 dBm -66.8 -54 dBm RSSI resolution RSSIRES Max spurious emissions dur- SPURRX ing active receive mode Over RSSIMIN to RSSIMAX range — 30 MHz to 1 GHz — 1 GHz to 12 GHz — es ig ns Symbol D Parameter N ot R ec om m en de d fo r N ew Note: 1. Definition of reference signal is 2.4 kbps 2GFSK, BT=0.5, Δf = 1.2 kHz, RX channel BW = 5.05 kHz, channel spacing = 12.5 kHz. 2. Definition of reference signal is 38.4 kbps 2GFSK, BT=0.5, Δf = 20 kHz, RX channel BW = 84.16 kHz, channel spacing = 100 kHz. 3. Definition of reference signal is 10 kbps 2GFSK, BT=0.5, Δf = 5 kHz, RX channel BW = 21.04 kHz. 4. Definition of reference signal is 100 kbps 2GFSK, BT=0.5, Δf = 50 kHz, RX channel BW = 210.4 kHz. silabs.com | Building a more connected world. Rev. 1.5 | 57 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.10.7 Sub-GHz RF Transmitter characteristics for 433 MHz Band Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD. RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 433 MHz. Table 4.24. Sub-GHz RF Transmitter characteristics for 433 MHz Band FRANGE Maximum TX Power1 POUTMAX Minimum active TX Power POUTMIN Output power step size POUTSTEP Min 426 Max Unit — 445 MHz 14.3 18 dBm 10.7 14 dBm — -42 — dBm — 0.5 — dB External PA supply connected to DC-DC output, 14dBm output power 11 External PA supply connected to DC-DC output, 10dBm output power 7 output power > 0 dBm Typ es ig ns RF tuning frequency range Test Condition D Symbol N ew Parameter At 10 dBm;1.8 V < VVREGVDD < 3.3 V, External PA supply = DCDC output, T = 25 °C — 1.7 — dB Output power variation vs temperature, peak to peak, Pout= 10dBm -40 to +85C at 10dBm — 0.5 1.2 dB -40 to +125C at 10dBm — 0.7 1.7 dB T = 25 °C — 0.2 0.6 dB POUTVAR_T Output power variation vs RF POUTVAR_F frequency, Pout = 10dBm fo r Output power variation vs POUTVAR_V supply, peak to peak, Pout = 10dBm SPURHARM_FCC In restricted bands, per FCC Part 15.205 / 15.209 — -61.2 -47 dBm In non-restricted bands, per FCC Part 15.231 — -68.5 -26 dBc Spurious emissions out-ofband FCC, Conducted measurement, 14dBm match, External PA supply connected to DC-DC output, Test Frequency = 434 MHz SPUROOB_FCC In non-restricted bands, per FCC Part 15.231 — -86.2 -26 dBc In restricted bands (30-88 MHz), per FCC Part 15.205 / 15.209 — -71.9 -52 dBm In restricted bands (88-216 MHz), per FCC Part 15.205 / 15.209 — -70.2 -62 dBm In restricted bands (216-960 MHz), per FCC Part 15.205 / 15.209 — -60.5 -54.5 dBm In restricted bands (>960 MHz), per FCC Part 15.205 / 15.209 — -57.7 -46 dBm SPURHARM_ETSI Per ETSI EN 300-220, Section 7.8.2.1 (frequencies below 1Ghz) — -57.3 -36 dBm Per ETSI EN 300-220, Section 7.8.2.1 (frequencies above 1Ghz) — -84.5 -36 dBm R ec om m en de d Spurious emissions of harmonics FCC, Conducted measurement, 14dBm match, External PA supply connected to DC-DC output, Test Frequency = 434 MHz N ot Spurious emissions of harmonics ETSI, Conducted measurement, 14dBm match, External PA supply connected to DC-DC output, Test Frequency = 434 MHz silabs.com | Building a more connected world. Rev. 1.5 | 58 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications Symbol Test Condition Min Typ Max Unit Spurious emissions out-ofband ETSI, Conducted measurement, 14dBm match, External PA supply connected to DC-DC output, Test Frequency = 434 MHz SPUROOB_ETSI Per ETSI EN 300-220, Section 7.8.2.1 (47-74 MHz, 87.5-118 MHz, 174-230 MHz, and 470-862 MHz) — -65.1 -60 dBm Per ETSI EN 300-220, Section 7.8.2.1 (other frequencies below 1 GHz) — -63.9 -42 dBm Per ETSI EN 300-220, Section 7.8.2.1 (frequencies above 1 GHz) — es ig ns Parameter -56.8 -36 dBm N ot R ec om m en de d fo r N ew D Note: 1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices covered in this datasheet can be found in the Max TX Power column of the Ordering Information Table. silabs.com | Building a more connected world. Rev. 1.5 | 59 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.10.8 Sub-GHz RF Receiver Characteristics for 433 MHz Band Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 433 MHz. Table 4.25. Sub-GHz RF Receiver Characteristics for 433 MHz Band Symbol Tuning frequency range FRANGE Test Condition Min 426 Typ Max Unit es ig ns Parameter — 445 MHz — 10 dBm — 10 dBm -107 — dBm -105 dBm Desired is reference 2.4 kbps GFSK signal1 — Max usable input level, 0.1% SAT50k BER Desired is reference 50 kbps GFSK signal2 — Sensitivity Desired is reference 4.8 kbps OOK signal3, 20% PER — Desired is reference 100 kbps GFSK signal4, 0.1% BER, T ≤ 85 °C — Desired is reference 100 kbps GFSK signal4, 0.1% BER, T > 85 °C — — -104 dBm Desired is reference 50 kbps GFSK signal2, 0.1% BER, T ≤ 85 °C — -110 -107.2 dBm Desired is reference 50 kbps GFSK signal2, 0.1% BER, T > 85 °C — — -106.6 dBm Desired is reference 2.4 kbps GFSK signal1, 0.1% BER — -122.3 — dBm Desired is reference 9.6 kbps GFSK signal5, 1% PER, T ≤ 85 °C — -109.4 -106.2 dBm Desired is reference 9.6 kbps GFSK signal5, 1% PER, T > 85 °C — — -105.7 dBm Desired is 4.8 kbps OOK signal3 at 3dB above sensitivity level, 20% PER — 46 — dB Desired is 100 kbps GFSK signal4 at 3dB above sensitivity level, 0.1% BER 24.8 33.4 — dB Desired is 2.4 kbps GFSK signal1 at 3dB above sensitivity level, 0.1% BER 47 59.1 — dB Desired is 50 kbps GFSK signal2 at 3dB above sensitivity level, 0.1% BER 45.6 50.7 — dB — 31.2 — dB -107.5 C/I1 N ot R ec om Adjacent channel selectivity, Interferer is CW at ± 1 × channel-spacing m en de d fo r N ew SENS D Max usable input level, 0.1% SAT2k4 BER silabs.com | Building a more connected world. Desired is 9.6 kbps 4GFSK signal5 at 3dB above sensitivity level, 1% PER Rev. 1.5 | 60 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications C/IIMAGE Typ Max Unit Desired is 4.8 kbps OOK signal3 at 3dB above sensitivity level, 20% PER — 56.8 — dB Desired is 100 kbps GFSK signal4 at 3dB above sensitivity level, 0.1% BER — 56.2 — dB Desired is 2.4 kbps GFSK signal1 at 3dB above sensitivity level, 0.1% BER — Desired is 50 kbps GFSK signal2 at 3dB above sensitivity level, 0.1% BER — Desired is 9.6 kbps 4GFSK signal5 at 3dB above sensitivity level, 1% PER — 62.2 — dB 57.4 — dB 47.8 — dB Desired is 4.8 kbps OOK signal3 at 3dB above sensitivity level, 20% PER — 42.2 — dB Desired is 100 kbps GFSK signal4 at 3dB above sensitivity level, 0.1% BER — 50 — dB Desired is 2.4 kbps GFSK signal1 at 3dB above sensitivity level, 0.1% BER — 52.3 — dB Desired is 50 kbps GFSK signal2 at 3dB above sensitivity level, 0.1% BER — 53 — dB Desired is 9.6 kbps 4GFSK signal5 at 3dB above sensitivity level, 1% PER — 45 — dB Interferer CW at Desired ± 1 MHz — 73.8 — dB Interferer CW at Desired ± 2 MHz — 75.7 — dB Interferer CW at Desired ± 10 MHz — 89.9 — dB Desired is 2.4 kbps GFSK signal1 at 3dB above sensitivity level — 59.1 — dB Upper limit of input power RSSIMAX range over which RSSI resolution is maintained — — 5 dBm Lower limit of input power RSSIMIN range over which RSSI resolution is maintained -98 — — dBm Over RSSIMIN to RSSIMAX range — 0.25 — dBm 216-960 MHz — -83.5 -57 dBm Above 960 MHz — -62.5 -52 dBm m en de d fo r Image rejection, Interferer is CW at image frequency Min es ig ns Alternate channel selectivity, C/I2 Interferer is CW at ± 2 × channel-spacing Test Condition D Symbol N ew Parameter C/IBLOCKER Intermod selectivity, 0.1% BER. CW interferers at 12.5 kHz and 25 kHz offsets C/IIM N ot R ec om Blocking selectivity, 0.1% BER. Desired is 2.4 kbps GFSK signal1 at 3dB above sensitivity level RSSI resolution RSSIRES Max spurious emissions dur- SPURRX_FCC ing active receive mode, per FCC Part 15.109(a) silabs.com | Building a more connected world. Rev. 1.5 | 61 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications Symbol Test Condition Min Typ Max Unit Max spurious emissions dur- SPURRX_ETSI ing active receive mode, per ETSI 300-220 Section 8.6 Below 1000 MHz — -84.6 -57 dBm Above 1000 MHz — -59.7 -52 dBm Max spurious emissions dur- SPURRX_ARIB ing active receive mode, per ARIB STD T67 Section 3.3(5) Below 710 MHz, RBW=100kHz — -83.6 -57 dBm es ig ns Parameter N ot R ec om m en de d fo r N ew D Note: 1. Definition of reference signal is 2.4 kbps 2GFSK, BT=0.5, Δf = 1.2 kHz, RX channel BW = 5.05 kHz, channel spacing = 12.5 kHz. 2. Definition of reference signal is 50 kbps 2GFSK, BT=0.5, Δf = 25 kHz, RX channel BW = 120.229 kHz, channel spacing = 200 kHz. 3. Definition of reference signal is 4.8 kbps OOK, RX channel BW = 315.6 kHz, channel spacing = 500 kHz. 4. Definition of reference signal is 100 kbps 2GFSK, BT=0.5, Δf = 50 kHz, RX channel BW = 210.4 kHz, channel spacing = 200 kHz. 5. Definition of reference signal is 9.6 kbps 4GFSK, BT=0.5, inner deviation = 0.8 kHz, RX channel BW = 9.989 kHz, channel spacing = 12.5 kHz. silabs.com | Building a more connected world. Rev. 1.5 | 62 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.10.9 Sub-GHz RF Transmitter characteristics for 315 MHz Band Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 315 MHz. Table 4.26. Sub-GHz RF Transmitter characteristics for 315 MHz Band FRANGE Maximum TX Power1 POUTMAX Min 195 External PA supply connected to DC-DC output, T ≤ 85 °C 10.8 External PA supply connected to DC-DC output, T > 85 °C 10.5 Typ Max Unit es ig ns RF tuning frequency range Test Condition — 358 MHz 15.3 17 dBm — — dBm -43.9 — dBm POUTMIN Output power step size POUTSTEP output power > 0 dBm — 0.5 — dB Output power variation vs supply POUTVAR_V 1.8 V < VVREGVDD < 3.3 V, External PA supply = DC-DC output, T = 25 °C — 1.8 — dB Output power variation vs temperature POUTVAR_T -40 to +85C — 0.5 1.2 dB — 0.7 1.5 dB — 0.1 0.7 dB SPURHARM_FCC In restricted bands, per FCC Part 15.205 / 15.209 — -53.8 -47 dBm In non-restricted bands, per FCC Part 15.231 — -63.4 -26 dBc In non-restricted bands, per FCC Part 15.231 — -76.6 -26 dBc In restricted bands (30-88 MHz), per FCC Part 15.205 / 15.209 — -71.8 -51 dBm In restricted bands (88-216 MHz), per FCC Part 15.205 / 15.209 — -70.2 -61 dBm In restricted bands (216-960 MHz), per FCC Part 15.205 / 15.209 — -68.2 -57 dBm In restricted bands (>960 MHz), per FCC Part 15.205 / 15.209 — -57.5 -46 dBm R ec om Spurious emissions out-ofSPUROOB_FCC band at 14 dBm output power, Conducted measurement, 14dBm match, External PA supply connected to DC-DC output, Test Frequency = 303 MHz T = 25 °C fo r -40 to +125C Output power variation vs RF POUTVAR_F frequency Spurious emissions of harmonics at 14 dBm output power, Conducted measurement, 14dBm match, External PA supply connected to DC-DC output, Test Frequency = 303 MHz N ew Minimum active TX Power D Symbol m en de d Parameter N ot Note: 1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices covered in this datasheet can be found in the Max TX Power column of the Ordering Information Table. silabs.com | Building a more connected world. Rev. 1.5 | 63 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.10.10 Sub-GHz RF Receiver Characteristics for 315 MHz Band Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD. RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 315 MHz. Table 4.27. Sub-GHz RF Receiver Characteristics for 315 MHz Band Symbol Tuning frequency range FRANGE Test Condition Min 195 Typ Max Unit es ig ns Parameter — 358 MHz — 10 dBm — 10 dBm -123.5 -120.7 dBm Desired is reference 2.4 kbps GFSK signal1 — Max usable input level, 0.1% SAT38k4 BER Desired is reference 38.4 kbps GFSK signal2 — Sensitivity Desired is reference 2.4 kbps GFSK signal1, 0.1% BER, T ≤ 85 °C — Desired is reference 2.4 kbps GFSK signal1, 0.1% BER, T > 85 °C — — -120 dBm Desired is reference 38.4 kbps GFSK signal2, 0.1% BER, T ≤ 85 °C — -111.4 -108.6 dBm Desired is reference 38.4 kbps GFSK signal2, 0.1% BER, T > 85 °C — — -107.9 dBm Desired is reference 500 kbps GFSK signal3, 0.1% BER, T ≤ 85 °C — -97.2 -94.6 dBm Desired is reference 500 kbps GFSK signal3, 0.1% BER, T > 85 °C — — -93.9 dBm Desired is 2.4 kbps GFSK signal1 at 3dB above sensitivity level, 0.1% BER 54.1 64.2 — dB Desired is 38.4kbps GFSK signal2 at 3dB above sensitivity level, 0.1% BER 46 50 — dB Desired is 2.4kbps GFSK signal1 at 3dB above sensitivity level, 0.1% BER — 66 — dB Desired is 38.4kbps GFSK signal2 at 3dB above sensitivity level2, 0.1% BER — 54 — dB Desired is 2.4kbps GFSK signal1 at 3dB above sensitivity level, 0.1% BER — 54.4 — dB Desired is 38.4kbps GFSK signal2 at 3dB above sensitivity level, 0.1% BER — 51.9 — dB C/I1 om Adjacent channel selectivity, Interferer is CW at ± 1 × channel-spacing m en de d fo r N ew SENS D Max usable input level, 0.1% SAT2k4 BER N ot R ec Alternate channel selectivity, C/I2 Interferer is CW at ± 2 × channel-spacing Image rejection, Interferer is CW at image frequency C/IIMAGE silabs.com | Building a more connected world. Rev. 1.5 | 64 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications Test Condition Min Typ Max Unit Blocking selectivity, 0.1% BER. Desired is 2.4 kbps GFSK signal1 at 3 dB above sensitivity level C/IBLOCKER Interferer CW at Desired ± 1 MHz — 74.9 — dB Interferer CW at Desired ± 2 MHz — 76.7 — dB 72.6 93.1 — dB RSSIMAX Upper limit of input power range over which RSSI resolution is maintained — — 5 dBm RSSIMIN Lower limit of input power range over which RSSI resolution is maintained -98 — — dBm 0.25 — dBm -87.4 -55 dBm -76.7 -47 dBm RSSI resolution Interferer CW at Desired ± 10 MHz RSSIRES — 216-960 MHz — Above 960MHz — N ew Max spurious emissions dur- SPURRX_FCC ing active receive mode, per FCC Part 15.109(a) Over RSSIMIN to RSSIMAX range es ig ns Symbol D Parameter N ot R ec om m en de d fo r Note: 1. Definition of reference signal is 2.4 kbps 2GFSK, BT=0.5, Δf = 1.2 kHz, RX channel BW = 5.05 kHz, channel spacing = 12.5 kHz. 2. Definition of reference signal is 38.4 kbps 2GFSK, BT=0.5, Δf = 20 kHz, RX channel BW = 84.16 kHz, channel spacing = 100 kHz. 3. Definition of reference signal is 500 kbps 2GFSK, BT=0.5, Δf = 125 kHz, RX channel BW = 841.6 kHz. silabs.com | Building a more connected world. Rev. 1.5 | 65 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.10.11 Sub-GHz RF Transmitter Characteristics for 169 MHz Band Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 169 MHz. Table 4.28. Sub-GHz RF Transmitter Characteristics for 169 MHz Band Test Condition RF tuning frequency range FRANGE Maximum TX Power1 POUTMAX Minimum active TX Power POUTMIN Output power step size POUTSTEP output power > 0 dBm — Output power variation vs supply, peak to peak POUTVAR_V 1.8 V < VVREGVDD < 3.3 V, External PA supply = 3.3 V, T = 25 °C — Output power variation vs temperature, peak to peak POUTVAR_T -40 to +85 °C at 20 dBm — 169 18.4 Max Unit — 170 MHz 20.4 23.3 dBm -42.6 — dBm 0.5 — dB 4.8 — dB 1.2 dB 0.6 0.8 1.5 dB Per ETSI EN 300-220, Section 7.8.2.1 (47-74 MHz, 87.5-118 MHz, 174-230 MHz, and 470-862 MHz) — -49.3 -36 dBm Per ETSI EN 300-220, Section 7.8.2.1 (other frequencies below 1 GHz) — -58.2 -53 dBm Per ETSI EN 300-220, Section 7.8.2.1 (frequencies above 1 GHz) — -38.9 25.4 dBm Per ETSI EN 300-220, Section 7.8.2.1 (47-74 MHz, 87.5-118 MHz, 174-230 MHz, and 470-862 MHz) — -61.8 -36 dBm Per ETSI EN 300-220, Section 7.8.2.1 (other frequencies below 1 GHz) — -62 -54 dBm Per ETSI EN 300-220, Section 7.8.2.1 (frequencies above 1 GHz) — -47.6 -41.1 dBm fo r — m en de d om Spurious emissions out-ofSPUROOB_ETSI band, Conducted measurement, External PA supply = 3.3 V, Test Frequency = 169 MHz Typ N ew External PA supply = 3.3 V -40 to +125 °C at 20 dBm Spurious emissions of harSPURHARM_ETSI monics, Conducted measurement, External PA supply = 3.3 V, Test Frequency = 169 MHz Min es ig ns Symbol D Parameter N ot R ec Note: 1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices covered in this datasheet can be found in the Max TX Power column of the Ordering Information Table. silabs.com | Building a more connected world. Rev. 1.5 | 66 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.10.12 Sub-GHz RF Receiver Characteristics for 169 MHz Band Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 169 MHz. Table 4.29. Sub-GHz RF Receiver Characteristics for 169 MHz Band Symbol Tuning frequency range FRANGE Test Condition Min 169 Typ Max Unit es ig ns Parameter — 170 MHz — 10 dBm — 10 dBm -124 — dBm -108 dBm Desired is reference 2.4 kbps GFSK signal1 — Max usable input level, 0.1% SAT38k4 BER Desired is reference 38.4 kbps GFSK signal2 — Sensitivity Desired is reference 2.4 kbps GFSK signal1, 0.1% BER — Desired is reference 38.4 kbps GFSK signal2, 0.1% BER, T ≤ 85 °C — Desired is reference 38.4 kbps GFSK signal2, 0.1% BER, T > 85 °C — — -108.5 dBm Desired is reference 500 kbps GFSK signal3, 0.1% BER, T ≤ 85 °C — -97.7 -94.6 dBm Desired is reference 500 kbps GFSK signal3, 0.1% BER, T > 85 °C — — -94 dBm Desired is 2.4 kbps GFSK signal1 at 3dB above sensitivity level, 0.1% BER — 65 — dB Desired is 38.4kbps GFSK signal1 at 3dB above sensitivity level, 0.1% BER 43.3 50.4 — dB Desired is 2.4kbps GFSK signal1 at 3dB above sensitivity level, 0.1% BER — 67.9 — dB Desired is 38.4kbps GFSK signal2 at 3dB above sensitivity level, 0.1% BER — 55.5 — dB Desired is 2.4kbps GFSK signal1 at 3dB above sensitivity level, 0.1% BER — 54.6 — dB Desired is 38.4kbps GFSK signal2 at 3dB above sensitivity level, 0.1% BER — 51 — dB Interferer CW at Desired ± 1 MHz — 74.2 — dB Interferer CW at Desired ± 2 MHz 68.7 76 — dB 80 90.6 — dB -111.9 Adjacent channel selectivity, Interferer is CW at ± 1 x channel-spacing m en de d fo r N ew SENS D Max usable input level, 0.1% SAT2k4 BER C/I1 ec om Alternate channel selectivity, C/I2 Interferer is CW at ± 2 x channel-spacing C/IIMAGE N ot R Image rejection, Interferer is CW at image frequency Blocking selectivity, 0.1% BER. Desired is 2.4 kbps GFSK signal1 at 3 dB above sensitivity level C/IBLOCKER silabs.com | Building a more connected world. Interferer CW at Desired ± 10 MHz Rev. 1.5 | 67 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications Symbol Min Typ Max Unit RSSIMAX Upper limit of input power range over which RSSI resolution is maintained — — 5 dBm RSSIMIN Lower limit of input power range over which RSSI resolution is maintained -98 — — dBm RSSI resolution RSSIRES Max spurious emissions dur- SPURRX ing active receive mode Test Condition Over RSSIMIN to RSSIMAX range — 30 MHz to 1 GHz — 1 GHz to 12 GHz — es ig ns Parameter 0.25 — dBm -83.7 -63 dBm -58.8 -50 dBm N ew D Note: 1. Definition of reference signal is 2.4 kbps 2GFSK, BT=0.5, Δf = 1.2 kHz, RX channel BW = 5.05 kHz, channel spacing = 12.5 kHz. 2. Definition of reference signal is 38.4 kbps 2GFSK, BT=0.5, Δf = 20 kHz, RX channel BW = 84.16 kHz, channel spacing = 100 kHz. 3. Definition of reference signal is 500 kbps 2GFSK, BT=0.5, Δf = 125 kHz, RX channel BW = 841.6 kHz. 4.1.11 Modem fo r Table 4.30. Modem Symbol Test Condition Min Typ Max Unit Receive bandwidth BWRX Configurable range with 38.4 MHz crystal 0.1 — 2530 kHz IF frequency fIF Configurable range with 38.4 MHz crystal. Selected steps available. 150 — 1371 kHz DSSS symbol length SLDSSS Configurable in steps of 1 chip 2 — 32 chips DSSS bits per symbol BPSDSSS Configurable 1 — 4 bits/ symbol N ot R ec om m en de d Parameter silabs.com | Building a more connected world. Rev. 1.5 | 68 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.12 Oscillators 4.1.12.1 Low-Frequency Crystal Oscillator (LFXO) Typ Max Unit — 32.768 — kHz ESRLFXO — — 70 kΩ Supported range of crystal load capacitance 1 CLFXO_CL 6 — 18 pF On-chip tuning cap range 2 CLFXO_T 8 D Crystal frequency fLFXO Supported crystal equivalent series resistance (ESR) Test Condition Min — 40 pF On-chip tuning cap step size SSLFXO — 0.25 — pF Current consumption after startup 3 ILFXO ESR = 70 kOhm, CL = 7 pF, GAIN4 = 2, AGC4 = 1 — 273 — nA Start- up time tLFXO ESR = 70 kOhm, CL = 7 pF, GAIN4 = 2 — 308 — ms On each of LFXTAL_N and LFXTAL_P pins N ew Symbol fo r Parameter es ig ns Table 4.31. Low-Frequency Crystal Oscillator (LFXO) N ot R ec om m en de d Note: 1. Total load capacitance as seen by the crystal. 2. The effective load capacitance seen by the crystal will be CLFXO_T /2. This is because each XTAL pin has a tuning cap and the two caps will be seen in series by the crystal. 3. Block is supplied by AVDD if ANASW = 0, or DVDD if ANASW=1 in EMU_PWRCTRL register. 4. In CMU_LFXOCTRL register. silabs.com | Building a more connected world. Rev. 1.5 | 69 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.12.2 High-Frequency Crystal Oscillator (HFXO) Parameter Symbol Test Condition Typ Max Unit Crystal frequency fHFXO 38.4 MHz required for radio transciever operation 38 38.4 40 MHz Supported crystal equivalent series resistance (ESR) ESRHFXO_38M4 Crystal frequency 38.4 MHz — — 60 Ω Supported range of crystal load capacitance 1 CHFXO_CL — 12 pF On-chip tuning cap range 2 CHFXO_T 20 25 pF On-chip tuning capacitance step SSHFXO — pF Startup time tHFXO 38.4 MHz, ESR = 50 Ohm, CL = 10 pF — 300 — µs Frequency tolerance for the crystal FTHFXO 38.4 MHz, ESR = 50 Ohm, CL = 10 pF -40 — 40 ppm es ig ns Min D Table 4.32. High-Frequency Crystal Oscillator (HFXO) 6 On each of HFXTAL_N and HFXTAL_P pins 9 0.04 N ew — m en de d fo r Note: 1. Total load capacitance as seen by the crystal. 2. The effective load capacitance seen by the crystal will be CHFXO_T /2. This is because each XTAL pin has a tuning cap and the two caps will be seen in series by the crystal. 4.1.12.3 Low-Frequency RC Oscillator (LFRCO) Table 4.33. Low-Frequency RC Oscillator (LFRCO) Symbol Test Condition Oscillation frequency fLFRCO ec om Parameter tLFRCO Current consumption 2 ILFRCO N ot R Startup time Min Typ Max Unit ENVREF1 = 1, T ≤ 85 °C 30.474 32.768 34.243 kHz ENVREF1 = 1, T > 85 °C 30.474 — 39.7 kHz ENVREF1 = 0, T ≤ 85 °C 30.474 32.768 33.915 kHz — 500 — µs ENVREF = 1 in CMU_LFRCOCTRL — 342 — nA ENVREF = 0 in CMU_LFRCOCTRL — 494 — nA Note: 1. In CMU_LFRCOCTRL register. 2. Block is supplied by AVDD if ANASW = 0, or DVDD if ANASW=1 in EMU_PWRCTRL register. silabs.com | Building a more connected world. Rev. 1.5 | 70 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.12.4 High-Frequency RC Oscillator (HFRCO) Table 4.34. High-Frequency RC Oscillator (HFRCO) Symbol Test Condition Min Typ Max Unit Frequency accuracy fHFRCO_ACC At production calibrated frequencies, across supply voltage and temperature -2.5 — 2.5 % Start-up time tHFRCO fHFRCO ≥ 19 MHz — 300 — ns 4 < fHFRCO < 19 MHz — 1 — µs fHFRCO ≤ 4 MHz — 2.5 — µs fHFRCO = 38 MHz — 204 228 µA fHFRCO = 32 MHz — 171 190 µA fHFRCO = 26 MHz D IHFRCO N ew Current consumption on all supplies es ig ns Parameter — 147 164 µA — 126 138 µA — 110 120 µA — 100 110 µA fHFRCO = 7 MHz — 81 91 µA fHFRCO = 4 MHz — 33 35 µA fHFRCO = 2 MHz — 31 35 µA fHFRCO = 1 MHz — 30 35 µA — 0.8 — % fHFRCO = 19 MHz fHFRCO = 16 MHz m en de d fo r fHFRCO = 13 MHz Coarse trim step size (% of period) SSHFRCO_COARS Fine trim step size (% of period) SSHFRCO_FINE — 0.1 — % Period jitter PJHFRCO — 0.2 — % RMS N ot R ec om E silabs.com | Building a more connected world. Rev. 1.5 | 71 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.12.5 Auxiliary High-Frequency RC Oscillator (AUXHFRCO) Table 4.35. Auxiliary High-Frequency RC Oscillator (AUXHFRCO) Symbol Test Condition Min Typ Max Unit Frequency accuracy fAUXHFRCO_ACC At production calibrated frequencies, across supply voltage and temperature -2.5 — 2.5 % Start-up time tAUXHFRCO fAUXHFRCO ≥ 19 MHz — 300 — ns 4 < fAUXHFRCO < 19 MHz — 1 — µs fAUXHFRCO ≤ 4 MHz — 2.5 — µs fAUXHFRCO = 38 MHz — 204 — µA fAUXHFRCO = 32 MHz — 171 — µA fAUXHFRCO = 26 MHz — 147 — µA — 126 — µA — 110 — µA — 100 — µA fAUXHFRCO = 7 MHz — 81 — µA fAUXHFRCO = 4 MHz — 33 — µA fAUXHFRCO = 2 MHz — 31 — µA fAUXHFRCO = 1 MHz — 30 — µA — 0.8 — % — 0.1 — % — 0.2 — % RMS Min Typ Max Unit 0.95 1 1.07 kHz fAUXHFRCO = 19 MHz fAUXHFRCO = 16 MHz m en de d fo r fAUXHFRCO = 13 MHz Coarse trim step size (% of period) CO_COARSE Fine trim step size (% of period) CO_FINE Period jitter PJAUXHFRCO D IAUXHFRCO N ew Current consumption on all supplies es ig ns Parameter SSAUXHFR- om SSAUXHFR- ec 4.1.12.6 Ultra-low Frequency RC Oscillator (ULFRCO) Table 4.36. Ultra-low Frequency RC Oscillator (ULFRCO) Symbol Oscillation frequency fULFRCO Test Condition N ot R Parameter silabs.com | Building a more connected world. Rev. 1.5 | 72 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.13 Flash Memory Characteristics1 Table 4.37. Flash Memory Characteristics1 Symbol Flash erase cycles before failure ECFLASH Flash data retention RETFLASH tW_PROG Min Typ Max Unit 10000 — — cycles — — years — — years 26 40 µs 68 82 µs T ≤ 85 °C 10 T ≤ 125 °C 10 Burst write, 128 words, average time per word 20 Single word 57 tPERASE 20 27 40 ms Mass erase time3 tMERASE 20 27 40 ms Device erase time4 5 tDERASE — 60 74 ms — 60 78 ms — — 3 mA — — 5 mA — — 3 mA N ew Page erase time2 D Word (32-bit) programming time Test Condition es ig ns Parameter T ≤ 85 °C T ≤ 125 °C IERASE Erase current6 Page Erase IWRITE Write current6 fo r Mass or Device Erase N ot R ec om m en de d Note: 1. Flash data retention information is published in the Quarterly Quality and Reliability Report. 2. From setting the ERASEPAGE bit in MSC_WRITECMD to 1 until the BUSY bit in MSC_STATUS is cleared to 0. Internal setup and hold times for flash control signals are included. 3. Mass erase is issued by the CPU and erases all flash. 4. Device erase is issued over the AAP interface and erases all flash, SRAM, the Lock Bit (LB) page, and the User data page Lock Word (ULW). 5. From setting the DEVICEERASE bit in AAP_CMD to 1 until the ERASEBUSY bit in AAP_STATUS is cleared to 0. Internal setup and hold times for flash control signals are included. 6. Measured at 25 °C. silabs.com | Building a more connected world. Rev. 1.5 | 73 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.14 General-Purpose I/O (GPIO) Symbol Test Condition Input low voltage VIL VIH Output high voltage relative to IOVDD VOH Typ Max Unit GPIO pins — — IOVDD*0.3 V RESETn — — AVDD*0.3 V — — V — — V — — V — V GPIO pins IOVDD*0.7 RESETn AVDD*0.7 Sourcing 3 mA, IOVDD ≥ 3 V, IOVDD*0.8 DRIVESTRENGTH1 = WEAK IOVDD*0.6 — N ew Sourcing 1.2 mA, IOVDD ≥ 1.62 V, es ig ns Parameter Input high voltage Min D Table 4.38. General-Purpose I/O (GPIO) DRIVESTRENGTH1 = WEAK Sourcing 20 mA, IOVDD ≥ 3 V, IOVDD*0.8 — — V IOVDD*0.6 — — V — — IOVDD*0.2 V — — IOVDD*0.4 V — — IOVDD*0.2 V — — IOVDD*0.4 V All GPIO except LFXO pins, GPIO ≤ IOVDD, T ≤ 85 °C — 0.1 30 nA LFXO Pins, GPIO ≤ IOVDD, T ≤ 85 °C — 0.1 50 nA All GPIO except LFXO pins, GPIO ≤ IOVDD, T > 85 °C — — 110 nA LFXO Pins, GPIO ≤ IOVDD, T > 85 °C — — 250 nA IOVDD < GPIO ≤ IOVDD + 2 V — 3.3 15 µA 30 43 65 kΩ 20 25 35 ns DRIVESTRENGTH1 = STRONG fo r Sourcing 8 mA, IOVDD ≥ 1.62 V, DRIVESTRENGTH1 = STRONG Sinking 3 mA, IOVDD ≥ 3 V, DRIVESTRENGTH1 = WEAK m en de d Output low voltage relative to VOL IOVDD Sinking 1.2 mA, IOVDD ≥ 1.62 V, DRIVESTRENGTH1 = WEAK Sinking 20 mA, IOVDD ≥ 3 V, DRIVESTRENGTH1 = STRONG om Sinking 8 mA, IOVDD ≥ 1.62 V, IIOLEAK N ot R ec Input leakage current Input leakage current on 5VTOL pads above IOVDD I5VTOLLEAK I/O pin pull-up/pull-down resistor RPUD Pulse width of pulses retIOGLITCH moved by the glitch suppression filter silabs.com | Building a more connected world. DRIVESTRENGTH1 = STRONG Rev. 1.5 | 74 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications Parameter Symbol Test Condition Output fall time, From 70% to 30% of VIO tIOOF CL = 50 pF, Min Typ Max Unit — 1.8 — ns — 4.5 — ns DRIVESTRENGTH1 = STRONG, DRIVESTRENGTH1 = WEAK, SLEWRATE1 = 0x6 Output rise time, From 30% to 70% of VIO tIOOR CL = 50 pF, — DRIVESTRENGTH1 = STRONG, SLEWRATE = 0x61 CL = 50 pF, — 2.2 — ns D CL = 50 pF, es ig ns SLEWRATE1 = 0x6 — ns — ns 7.4 SLEWRATE1 = 0x6 TRESET — N ot R ec om m en de d Note: 1. In GPIO_Pn_CTRL register. 100 fo r RESETn low time to ensure pin reset N ew DRIVESTRENGTH1 = WEAK, silabs.com | Building a more connected world. Rev. 1.5 | 75 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.15 Voltage Monitor (VMON) Test Condition Supply current (including I_SENSE) IVMON ISENSE Typ Max Unit In EM0 or EM1, 1 supply monitored — 5.8 8.26 µA In EM0 or EM1, 4 supplies monitored — 11.8 16.8 µA In EM2, EM3 or EM4, 1 channel active and above threshold — 62 — nA In EM2, EM3 or EM4, 1 channel active and below threshold — 62 — nA In EM2, EM3 or EM4, All channels active and above threshold — — nA In EM2, EM3 or EM4, All channels active and below threshold — 99 — nA In EM0 or EM1 — 2 — µA — 2 — nA 1.62 — 3.4 V — 200 — mV — 20 — mV — 460 — ns — 26 — mV Threshold range VVMON_RANGE Threshold step size NVMON_STESP Coarse m en de d Fine fo r In EM2, EM3 or EM4 tVMON_RES Hysteresis VVMON_HYST Supply drops at 1V/µs rate 99 N ot R ec om Response time es ig ns Symbol N ew Parameter Loading of monitored supply Min D Table 4.39. Voltage Monitor (VMON) silabs.com | Building a more connected world. Rev. 1.5 | 76 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.16 Analog to Digital Converter (ADC) Specified at 1 Msps, ADCCLK = 16 MHz, BIASPROG = 0, GPBIASACC = 0, unless otherwise indicated. Table 4.40. Analog to Digital Converter (ADC) Resolution VRESOLUTION Input voltage range1 VADCIN Test Condition Single ended Min Typ Max Unit 6 — 12 Bits — VFS V — VFS/2 V — VAVDD V 80 — dB 80 — dB — Differential -VFS/2 Input range of external refer- VADCREFIN_P ence voltage, single ended and differential 1 PSRRADC At DC — Analog input common mode rejection ratio CMRRADC At DC — Current from all supplies, us- IADC_CONTINUing internal reference buffer. OUS_LP Continuous operation. WARMUPMODE3 = KEEPADCWARM N ew Power supply rejection2 es ig ns Symbol D Parameter — 301 350 µA 250 ksps / 4 MHz ADCCLK, BIASPROG = 6, GPBIASACC = 1 4 — 149 — µA 62.5 ksps / 1 MHz ADCCLK, BIASPROG = 15, GPBIASACC = 1 4 — 91 — µA Current from all supplies, us- IADC_NORMAL_LP 35 ksps / 16 MHz ADCCLK, BIAing internal reference buffer. SPROG = 0, GPBIASACC = 1 4 Duty-cycled operation. WAR5 ksps / 16 MHz ADCCLK BIAMUPMODE3 = NORMAL SPROG = 0, GPBIASACC = 1 4 — 51 — µA — 9 — µA Current from all supplies, us- IADC_STANDing internal reference buffer. BY_LP Duty-cycled operation. AWARMUPMODE3 = KEEPINSTANDBY or KEEPINSLOWACC 125 ksps / 16 MHz ADCCLK, BIASPROG = 0, GPBIASACC = 1 4 — 117 — µA 35 ksps / 16 MHz ADCCLK, BIASPROG = 0, GPBIASACC = 1 4 — 79 — µA 1 Msps / 16 MHz ADCCLK, BIASPROG = 0, GPBIASACC = 0 4 — 345 — µA 250 ksps / 4 MHz ADCCLK, BIASPROG = 6, GPBIASACC = 0 4 — 191 — µA 62.5 ksps / 1 MHz ADCCLK, BIASPROG = 15, GPBIASACC = 0 4 — 132 — µA Current from all supplies, us- IADC_NORMAL_HP 35 ksps / 16 MHz ADCCLK, BIAing internal reference buffer. SPROG = 0, GPBIASACC = 0 4 Duty-cycled operation. WAR5 ksps / 16 MHz ADCCLK BIAMUPMODE3 = NORMAL SPROG = 0, GPBIASACC = 0 4 — 102 — µA — 17 — µA m en de d fo r 1 Msps / 16 MHz ADCCLK, BIASPROG = 0, GPBIASACC = 1 4 N ot R ec om Current from all supplies, us- IADC_CONTINUing internal reference buffer. OUS_HP Continuous operation. WARMUPMODE3 = KEEPADCWARM Current from all supplies, us- IADC_STANDing internal reference buffer. BY_HP Duty-cycled operation. AWARMUPMODE3 = KEEPINSTANDBY or KEEPINSLOWACC 125 ksps / 16 MHz ADCCLK, BIASPROG = 0, GPBIASACC = 0 4 — 162 — µA 35 ksps / 16 MHz ADCCLK, BIASPROG = 0, GPBIASACC = 0 4 — 123 — µA Current from HFPERCLK HFPERCLK = 16 MHz — 140 — µA IADC_CLK silabs.com | Building a more connected world. Rev. 1.5 | 77 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications Min Typ Max Unit fADCCLK — — 16 MHz Throughput rate fADCRATE — — 1 Msps Conversion time5 tADCCONV 6 bit — 7 — cycles 8 bit — 9 — cycles 12 bit — WARMUPMODE3 = NORMAL — WARMUPMODE3 = KEEPINSTANDBY — WARMUPMODE3 = KEEPINSLOWACC — Internal reference6, differential measurement 58 Startup time of reference generator and ADC core SNDR at 1Msps and fIN = 10kHz tADCSTART SNDRADC es ig ns ADC clock frequency Test Condition 13 — cycles — 5 µs — 2 µs — 1 µs D Symbol — dB 67 N ew Parameter — 68 — dB Spurious-free dynamic range SFDRADC (SFDR) 1 MSamples/s, 10 kHz full-scale sine wave — 75 — dB Differential non-linearity (DNL) DNLADC 12 bit resolution, No missing codes -1 — 2 LSB Integral non-linearity (INL), End point method INLADC 12 bit resolution -6 — 6 LSB Offset error VADCOFFSETERR -3 0.25 3 LSB Gain error in ADC VADCGAIN Using internal reference — -0.2 3.5 % Using external reference — -1 — % — -1.84 — mV/°C m en de d Temperature sensor slope fo r External reference7, differential measurement VTS_SLOPE N ot R ec om Note: 1. The absolute voltage allowed at any ADC input is dictated by the power rail supplied to on-chip circuitry, and may be lower than the effective full scale voltage. All ADC inputs are limited to the ADC supply (AVDD or DVDD depending on EMU_PWRCTRL_ANASW). Any ADC input routed through the APORT will further be limited by the IOVDD supply to the pin. 2. PSRR is referenced to AVDD when ANASW=0 and to DVDD when ANASW=1 in EMU_PWRCTRL. 3. In ADCn_CNTL register. 4. In ADCn_BIASPROG register. 5. Derived from ADCCLK. 6. Internal reference option used corresponds to selection 2V5 in the SINGLECTRL_REF or SCANCTRL_REF register field. The differential input range with this configuration is ± 1.25 V. Typical value is characterized using full-scale sine wave input. Minimum value is production-tested using sine wave input at 1.5 dB lower than full scale. 7. External reference is 1.25 V applied externally to ADCnEXTREFP, with the selection CONF in the SINGLECTRL_REF or SCANCTRL_REF register field and VREFP in the SINGLECTRLX_VREFSEL or SCANCTRLX_VREFSEL field. The differential input range with this configuration is ± 1.25 V. silabs.com | Building a more connected world. Rev. 1.5 | 78 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.17 Analog Comparator (ACMP) Table 4.41. Analog Comparator (ACMP) Symbol Test Condition Input voltage range VACMPIN ACMPVDD = ACMPn_CTRL_PWRSEL 1 Supply voltage VACMPVDD BIASPROG2 ≤ 0x10 or FULLBIAS2 = 0 1.85 0x10 < BIASPROG2 ≤ 0x20 and FULLBIAS2 = 1 2.1 BIASPROG2 = 0x10, FULLBIAS2 =0 — BIASPROG2 = 0x20, FULLBIAS2 =1 — VLP selected as input using 2.5 V Reference / 4 (0.625 V) — VLP selected as input using VDD ec R N ot silabs.com | Building a more connected world. 0 — VACMPVDD V — VVREGVDD_ V MAX — VVREGVDD_ V MAX — nA 74 95 µA 50 — nA — 20 — nA VBDIV selected as input using 1.25 V reference / 1 — 4.1 — µA VADIV selected as input using VDD/1 — 2.4 — µA HYSTSEL4 = HYST0 -1.75 0 1.75 mV HYSTSEL4 = HYST1 10 18 26 mV HYSTSEL4 = HYST2 21 32 46 mV HYSTSEL4 = HYST3 27 44 63 mV HYSTSEL4 = HYST4 32 55 80 mV HYSTSEL4 = HYST5 38 65 100 mV HYSTSEL4 = HYST6 43 77 121 mV HYSTSEL4 = HYST7 47 86 148 mV HYSTSEL4 = HYST8 -4 0 4 mV HYSTSEL4 = HYST9 -27 -18 -10 mV HYSTSEL4 = HYST10 -47 -32 -18 mV HYSTSEL4 = HYST11 -64 -43 -27 mV HYSTSEL4 = HYST12 -78 -54 -32 mV HYSTSEL4 = HYST13 -93 -64 -37 mV HYSTSEL4 = HYST14 -113 -74 -42 mV HYSTSEL4 = HYST15 -135 -85 -47 mV m en de d VACMPHYST om Hysteresis (VCM = 1.25 V, BIASPROG2 = 0x10, FULLBIAS2 = 1) Unit 306 fo r Current consumption of inter- IACMPREF nal voltage reference3 Max D IACMP Typ N ew Active current not including voltage reference3 Min es ig ns Parameter Rev. 1.5 | 79 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications Symbol Test Condition Min Typ Max Unit Comparator delay5 tACMPDELAY BIASPROG2 = 0x10, FULLBIAS2 =0 — 3.7 — µs BIASPROG2 = 0x20, FULLBIAS2 =1 — 35 — ns -35 — 35 mV Offset voltage VACMPOFFSET BIASPROG2 =0x10, FULLBIAS2 =1 Reference voltage VACMPREF Internal 1.25 V reference 1 Internal 2.5 V reference 2 CSRESSEL6 = 0 1.47 V 2.5 2.8 V — infinite — kΩ CSRESSEL6 = 1 — 15 — kΩ CSRESSEL6 = 2 — 27 — kΩ CSRESSEL6 = 3 — 39 — kΩ CSRESSEL6 = 4 CSRESSEL6 = 5 CSRESSEL6 = 6 — 51 — kΩ — 102 — kΩ — 164 — kΩ — 239 — kΩ fo r CSRESSEL6 = 7 D 1.25 N ew Capacitive sense internal re- RCSRES sistance es ig ns Parameter m en de d Note: 1. ACMPVDD is a supply chosen by the setting in ACMPn_CTRL_PWRSEL and may be IOVDD, AVDD or DVDD. 2. In ACMPn_CTRL register. 3. The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference. IACMPTOTAL = IACMP + IACMPREF. N ot R ec om 4. In ACMPn_HYSTERESIS registers. 5. ± 100 mV differential drive. 6. In ACMPn_INPUTSEL register. silabs.com | Building a more connected world. Rev. 1.5 | 80 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.18 Current Digital to Analog Converter (IDAC) Table 4.42. Current Digital to Analog Converter (IDAC) NIDAC_RANGES Output current IIDAC_OUT Linear steps within each range NIDAC_STEPS Step size SSIDAC — 4 — ranges 1.6 RANGSEL1 = RANGE2 0.5 RANGSEL1 = RANGE3 2 — — RANGSEL1 = RANGE0 — 1.6 µA — 4.7 µA — 16 µA — 64 µA 32 — steps — nA 50 — 100 — nA — 500 — nA — 2 — µA EM0 or EM1, AVDD=3.3 V, T = 25 °C -2 — 2 % EM0 or EM1, Across operating temperature range -18 — 22 % EM2 or EM3, Source mode, RANGSEL1 = RANGE0, AVDD=3.3 V, T = 25 °C — -2 — % EM2 or EM3, Source mode, RANGSEL1 = RANGE1, AVDD=3.3 V, T = 25 °C — -1.7 — % EM2 or EM3, Source mode, RANGSEL1 = RANGE2, AVDD=3.3 V, T = 25 °C — -0.8 — % EM2 or EM3, Source mode, RANGSEL1 = RANGE3, AVDD=3.3 V, T = 25 °C — -0.5 — % EM2 or EM3, Sink mode, RANGSEL1 = RANGE0, AVDD=3.3 V, T = 25 °C — -0.7 — % EM2 or EM3, Sink mode, RANGSEL1 = RANGE1, AVDD=3.3 V, T = 25 °C — -0.6 — % EM2 or EM3, Sink mode, RANGSEL1 = RANGE2, AVDD=3.3 V, T = 25 °C — -0.5 — % EM2 or EM3, Sink mode, RANGSEL1 = RANGE3, AVDD=3.3 V, T = 25 °C — -0.5 — % Output within 1% of steady state value — 5 — µs fo r m en de d om ec R N ot silabs.com | Building a more connected world. Unit RANGSEL1 = RANGE1 RANGSEL1 = RANGE3 tIDAC_SU Max 0.05 RANGSEL1 = RANGE2 Start up time Typ RANGSEL1 = RANGE0 RANGSEL1 = RANGE1 Total accuracy, STEPSEL1 = ACCIDAC 0x10 Min es ig ns Number of ranges Test Condition D Symbol N ew Parameter Rev. 1.5 | 81 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications Current consumption2 IIDAC Typ Max Unit Range setting is changed — 5 — µs Step value is changed — 1 — µs EM0 or EM1 Source mode, excluding output current, Across operating temperature range — 8.9 13 µA EM0 or EM1 Sink mode, excluding output current, Across operating temperature range — EM2 or EM3 Source mode, excluding output current, T = 25 °C — EM2 or EM3 Sink mode, excluding output current, T = 25 °C — EM2 or EM3 Source mode, excluding output current, T ≥ 85 °C — 16 µA 1.04 — µA 1.08 — µA — µA 8.9 — 12 — µA RANGESEL1=0, output voltage = min(VIOVDD, VAVDD2-100 mV) — 0.04 — % RANGESEL1=1, output voltage = min(VIOVDD, VAVDD2-100 mV) — 0.02 — % RANGESEL1=2, output voltage = min(VIOVDD, VAVDD2-150 mV) — 0.02 — % RANGESEL1=3, output voltage = min(VIOVDD, VAVDD2-250 mV) — 0.02 — % RANGESEL1=0, output voltage = 100 mV — 0.18 — % RANGESEL1=1, output voltage = 100 mV — 0.12 — % RANGESEL1=2, output voltage = 150 mV — 0.08 — % RANGESEL1=3, output voltage = 250 mV — 0.02 — % m en de d om Output voltage compliance in ICOMP_SINK sink mode, sink current change relative to current sunk at IOVDD 12 EM2 or EM3 Sink mode, excluding output current, T ≥ 85 °C fo r Output voltage compliance in ICOMP_SRC source mode, source current change relative to current sourced at 0 V Min es ig ns Settling time, (output settled tIDAC_SETTLE within 1% of steady state value), Test Condition D Symbol N ew Parameter N ot R ec Note: 1. In IDAC_CURPROG register. 2. The IDAC is supplied by either AVDD, DVDD, or IOVDD based on the setting of ANASW in the EMU_PWRCTRL register and PWRSEL in the IDAC_CTRL register. Setting PWRSEL to 1 selects IOVDD. With PWRSEL cleared to 0, ANASW selects between AVDD (0) and DVDD (1). silabs.com | Building a more connected world. Rev. 1.5 | 82 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.19 Pulse Counter (PCNT) Table 4.43. Pulse Counter (PCNT) Symbol Test Condition Min Typ Max Unit Input frequency FIN Asynchronous Single and Quadrature Modes — — 10 MHz Sampled Modes with Debounce filter set to 0. — — 8 kHz 4.1.20 I2C N ew D 4.1.20.1 I2C Standard-mode (Sm)1 es ig ns Parameter Table 4.44. I2C Standard-mode (Sm)1 SCL clock frequency2 fSCL SCL clock low time tLOW SCL clock high time tHIGH SDA set-up time tSU_DAT SDA hold time3 Repeated START condition set-up time Test Condition Min Typ Max Unit 0 — 100 kHz 4.7 — — µs 4 — — µs 250 — — ns tHD_DAT 100 — 3450 ns tSU_STA 4.7 — — µs (Repeated) START condition tHD_STA hold time 4 — — µs STOP condition set-up time tSU_STO 4 — — µs Bus free time between a STOP and START condition tBUF 4.7 — — µs fo r Symbol om m en de d Parameter N ot R ec Note: 1. For CLHR set to 0 in the I2Cn_CTRL register. 2. For the minimum HFPERCLK frequency required in Standard-mode, refer to the I2C chapter in the reference manual. 3. The maximum SDA hold time (tHD_DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW). silabs.com | Building a more connected world. Rev. 1.5 | 83 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.20.2 I2C Fast-mode (Fm)1 Symbol SCL clock frequency2 Typ Max Unit fSCL 0 — 400 kHz SCL clock low time tLOW 1.3 — — µs SCL clock high time tHIGH 0.6 — — µs SDA set-up time tSU_DAT 100 — — ns SDA hold time3 tHD_DAT 100 — 900 ns Repeated START condition set-up time tSU_STA 0.6 — — µs (Repeated) START condition tHD_STA hold time 0.6 — — µs 0.6 — — µs 1.3 — — µs STOP condition set-up time tSU_STO Bus free time between a STOP and START condition tBUF Test Condition N ew Parameter es ig ns Min D Table 4.45. I2C Fast-mode (Fm)1 N ot R ec om m en de d fo r Note: 1. For CLHR set to 1 in the I2Cn_CTRL register. 2. For the minimum HFPERCLK frequency required in Fast-mode, refer to the I2C chapter in the reference manual. 3. The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW). silabs.com | Building a more connected world. Rev. 1.5 | 84 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.20.3 I2C Fast-mode Plus (Fm+)1 Symbol SCL clock frequency2 Typ Max Unit fSCL 0 — 1000 kHz SCL clock low time tLOW 0.5 — — µs SCL clock high time tHIGH 0.26 — — µs SDA set-up time tSU_DAT 50 — — ns SDA hold time tHD_DAT 100 — — ns Repeated START condition set-up time tSU_STA 0.26 — — µs (Repeated) START condition tHD_STA hold time 0.26 — — µs 0.26 — — µs 0.5 — — µs STOP condition set-up time tSU_STO Bus free time between a STOP and START condition tBUF Test Condition N ew Parameter es ig ns Min D Table 4.46. I2C Fast-mode Plus (Fm+)1 N ot R ec om m en de d fo r Note: 1. For CLHR set to 0 or 1 in the I2Cn_CTRL register. 2. For the minimum HFPERCLK frequency required in Fast-mode Plus, refer to the I2C chapter in the reference manual. silabs.com | Building a more connected world. Rev. 1.5 | 85 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.1.21 USART SPI SPI Master Timing Parameter Symbol Test Condition Min SCLK period 1 2 3 tSCLK CS to MOSI 1 2 tCS_MO -9 SCLK to MOSI 1 2 tSCLK_MO -6 MISO setup time 1 2 tSU_MI Max Unit — — ns — 10 ns — 6.5 ns — — ns IOVDD = 1.62 V 60 IOVDD = 3.0 V 40 — — ns -13 — — ns N ew tH_MI MISO hold time 1 2 Typ D 2* tHFPERCLK es ig ns Table 4.47. SPI Master Timing Note: 1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0). 2. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD). tCS_MO m en de d CS fo r 3. tHFPERCLK is one period of the selected HFPERCLK. tSCKL_MO SCLK CLKPOL = 0 tSCLK SCLK CLKPOL = 1 MOSI tSU_MI tH_MI om MISO N ot R ec Figure 4.1. SPI Master Timing Diagram (SMSDELAY = 0) silabs.com | Building a more connected world. Rev. 1.5 | 86 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications CS tCS_MO tSCLK_MO SCLK CLKPOL = 0 CLKPOL = 1 MOSI tSU_MI tH_MI MISO N ot R ec om m en de d fo r N ew D Figure 4.2. SPI Master Timing Diagram (SMSDELAY = 1) es ig ns tSCLK SCLK silabs.com | Building a more connected world. Rev. 1.5 | 87 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications SPI Slave Timing Symbol SCLK period 1 2 3 Test Condition Typ Max Unit tSCLK 6* tHFPERCLK — — ns SCLK high time1 2 3 tSCLK_HI 2.5 * tHFPERCLK — — ns SCLK low time1 2 3 tSCLK_LO 2.5 * tHFPERCLK — — ns CS active to MISO 1 2 tCS_ACT_MI 4 — 70 ns CS disable to MISO 1 2 tCS_DIS_MI 4 — 50 ns MOSI setup time 1 2 tSU_MO 8 — — ns MOSI hold time 1 2 3 tH_MO 7 — — ns SCLK to MISO 1 2 3 tSCLK_MI 10 + 1.5 * tHFPERCLK — 65 + 2.5 * tHFPERCLK ns N ew Parameter es ig ns Min D Table 4.48. SPI Slave Timing CS SCLK CLKPOL = 0 SCLK CLKPOL = 1 tCS_ACT_MI om MOSI m en de d 3. tHFPERCLK is one period of the selected HFPERCLK. fo r Note: 1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0). 2. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD). tSCLK_HI tSU_MO tCS_DIS_MI tSCLK_LO tSCLK tH_MO tSCLK_MI Figure 4.3. SPI Slave Timing Diagram R ec MISO N ot 4.2 Typical Performance Curves Typical performance curves indicate typical characterized performance under the stated conditions. silabs.com | Building a more connected world. Rev. 1.5 | 88 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications N ew D es ig ns 4.2.1 Supply Current ec om m en de d fo r Figure 4.4. EM0 Active Mode Typical Supply Current vs. Temperature R Figure 4.5. EM1 Sleep Mode Typical Supply Current vs. Temperature N ot Typical supply current for EM2, EM3 and EM4H using standard software libraries from Silicon Laboratories. silabs.com | Building a more connected world. Rev. 1.5 | 89 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Figure 4.6. EM2, EM3, EM4H and EM4S Typical Supply Current vs. Temperature N ot R ec om m en de d fo r N ew D es ig ns Electrical Specifications silabs.com | Building a more connected world. Rev. 1.5 | 90 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications 4.2.2 DC-DC Converter N ot R ec om m en de d fo r N ew D es ig ns Default test conditions: CCM mode, LDCDC = 4.7 μH, CDCDC = 1.0 μF, VDCDC_I = 3.3 V, VDCDC_O = 1.8 V, FDCDC_LN = 7 MHz Figure 4.7. DC-DC Converter Typical Performance Characteristics silabs.com | Building a more connected world. Rev. 1.5 | 91 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications DVDD 50mV/div offset:1.8V 100mA VSW ILOAD 2V/div offset:1.8V 1mA 10μs/div 100μs/div N ot R ec om m en de d fo r N ew Figure 4.8. DC-DC Converter Transition Waveforms D DVDD 60mV/div offset:1.8V es ig ns Load Step Response in LN (CCM) mode (Heavy Drive) LN (CCM) and LP mode transition (load: 5mA) silabs.com | Building a more connected world. Rev. 1.5 | 92 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications N ew D es ig ns 4.2.3 Internal Oscillators Figure 4.10. HFRCO and AUXHFRCO Typical Performance at 32 MHz N ot R ec om m en de d fo r Figure 4.9. HFRCO and AUXHFRCO Typical Performance at 38 MHz silabs.com | Building a more connected world. Rev. 1.5 | 93 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet N ew D es ig ns Electrical Specifications ec om m en de d fo r Figure 4.11. HFRCO and AUXHFRCO Typical Performance at 26 MHz N ot R Figure 4.12. HFRCO and AUXHFRCO Typical Performance at 19 MHz silabs.com | Building a more connected world. Rev. 1.5 | 94 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet N ew D es ig ns Electrical Specifications ec om m en de d fo r Figure 4.13. HFRCO and AUXHFRCO Typical Performance at 16 MHz N ot R Figure 4.14. HFRCO and AUXHFRCO Typical Performance at 13 MHz silabs.com | Building a more connected world. Rev. 1.5 | 95 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet N ew D es ig ns Electrical Specifications ec om m en de d fo r Figure 4.15. HFRCO and AUXHFRCO Typical Performance at 7 MHz N ot R Figure 4.16. HFRCO and AUXHFRCO Typical Performance at 4 MHz silabs.com | Building a more connected world. Rev. 1.5 | 96 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet N ew D es ig ns Electrical Specifications ec om m en de d fo r Figure 4.17. HFRCO and AUXHFRCO Typical Performance at 2 MHz N ot R Figure 4.18. HFRCO and AUXHFRCO Typical Performance at 1 MHz silabs.com | Building a more connected world. Rev. 1.5 | 97 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet N ew D es ig ns Electrical Specifications Figure 4.20. ULFRCO Typical Performance at 1 kHz N ot R ec om m en de d fo r Figure 4.19. LFRCO Typical Performance at 32.768 kHz silabs.com | Building a more connected world. Rev. 1.5 | 98 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Electrical Specifications N ot R ec om m en de d fo r N ew D es ig ns 4.2.4 2.4 GHz Radio Figure 4.21. 2.4 GHz RF Transmitter Output Power silabs.com | Building a more connected world. Rev. 1.5 | 99 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet N ew D es ig ns Electrical Specifications N ot R ec om m en de d fo r Figure 4.22. 2.4 GHz RF Receiver Sensitivity silabs.com | Building a more connected world. Rev. 1.5 | 100 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Typical Connection Diagrams 5. Typical Connection Diagrams 5.1 Power Typical power supply connections for direct supply, without using the internal DC-DC converter, are shown in the following figure. VDD + – VREGVDD AVDD VREGSW es ig ns Main Supply IOVDD HFXTAL_N VREGVSS HFXTAL_P DVDD LFXTAL_N D LFXTAL_P DECOUPLE PAVDD N ew RFVDD Figure 5.1. EFR32MG1 Typical Application Circuit: Direct Supply Configuration without DC-DC converter fo r Typical power supply circuits using the internal DC-DC converter are shown below. The MCU operates from the DC-DC converter supply. For low RF transmit power applications less than 13dBm, the RF PA may be supplied by the DC-DC converter. For OPNs supporting high power RF transmission, the RF PA must be directly supplied by VDD for RF transmit power greater than 13 dBm. m en de d VDD Main Supply + – VREGVDD VDCDC VREGSW VREGVSS IOVDD HFXTAL_N HFXTAL_P LFXTAL_N LFXTAL_P DECOUPLE RFVDD PAVDD R ec om DVDD AVDD N ot Figure 5.2. EFR32MG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC) silabs.com | Building a more connected world. Rev. 1.5 | 101 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Typical Connection Diagrams VDD + – VREGVDD VDCDC AVDD VREGSW IOVDD HFXTAL_N VREGVSS HFXTAL_P DVDD LFXTAL_N LFXTAL_P DECOUPLE PAVDD D RFVDD es ig ns Main Supply N ot R ec om m en de d fo r N ew Figure 5.3. EFR32MG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDD) silabs.com | Building a more connected world. Rev. 1.5 | 102 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Typical Connection Diagrams 5.2 RF Matching Networks 4-Element Match for 2.4GHz Band 2-Element Match for 2.4GHz Band PAVDD PAVDD L0 2G4RF_ION 50Ω N ew C0 2G4RF_ION L1 2G4RF_IOP 50Ω 2G4RF_IOP L0 D PAVDD PAVDD es ig ns Typical RF matching network circuit diagrams are shown in Figure 5.4 Typical 2.4 GHz RF impedance-matching network circuits on page 103 for applications in the 2.4GHz band, and in Figure 5.5 Typical Sub-GHz RF impedance-matching network circuits on page 103 for applications in the sub-GHz band. Application-specific component values can be found in application notes AN923: EFR32 subGHz Matching Guide and AN930: EFR32 2.4 GHz Matching Guide. For low RF transmit power applications less than 13dBm, the twoelement match is recommended. For OPNs supporting high power RF transmission, the four-element match is recommended for high RF transmit power (> 13dBm). As an addition resource, application note AN1081: Integrated Passive Devices for EFR32 Sub-GHz RF Matching provides a list of supported Integrated Passive Devices (IPDs) along with design and layout considerations that can further simplify the external RF matching network for sub-GHz applications. C0 C1 fo r Figure 5.4. Typical 2.4 GHz RF impedance-matching network circuits Sub-GHz Match Topology I (169-500 MHz) m en de d PAVDD L1 L2 C0 SUBGRF_IN L3 C5 L5 L6 L7 50Ω C2 C4 L0 C7 C8 C9 C10 C3 SUBGRF_IP C1 SUBGRF_ON ec om SUBGRF_OP L4 C0 C6 BAL1 Sub-GHz Match Topology 2 (500-915 MHz) L3 PAVDD L5 L6 50Ω R SUBGRF_IN L0 C4 C7 C8 C9 N ot SUBGRF_IP C1 L4 BAL1 SUBGRF_ON SUBGRF_OP Figure 5.5. Typical Sub-GHz RF impedance-matching network circuits silabs.com | Building a more connected world. Rev. 1.5 | 103 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Typical Connection Diagrams 5.3 Other Connections N ot R ec om m en de d fo r N ew D es ig ns Other components or connections may be required to meet the system-level requirements. Application Note AN0002: "Hardware Design Considerations" contains detailed information on these connections. Application Notes can be accessed on the Silicon Labs website (www.silabs.com/32bit-appnotes). silabs.com | Building a more connected world. Rev. 1.5 | 104 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Pin Definitions 6. Pin Definitions om m en de d fo r N ew D es ig ns 6.1 QFN48 2.4 GHz and Sub-GHz Device Pinout Figure 6.1. QFN48 2.4 GHz and Sub-GHz Device Pinout R ec The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 6.5 GPIO Functionality Table or 6.6 Alternate Functionality Overview. N ot Pin Name Pin(s) Table 6.1. QFN48 2.4 GHz and Sub-GHz Device Pinout Description Pin Name Pin(s) Description VSS 0 Ground PF0 1 GPIO (5V) PF1 2 GPIO (5V) PF2 3 GPIO (5V) PF3 4 GPIO (5V) PF4 5 GPIO (5V) PF5 6 GPIO (5V) PF6 7 GPIO (5V) PF7 8 GPIO (5V) RFVDD 9 Radio power supply HFXTAL_N 10 High Frequency Crystal input pin. HFXTAL_P 11 High Frequency Crystal output pin. silabs.com | Building a more connected world. Rev. 1.5 | 105 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Pin Definitions Pin Name Pin(s) Description Pin Name Pin(s) Description SUBGRF_OP 13 Sub GHz Differential RF output, positive path. SUBGRF_IP 15 Sub GHz Differential RF input, positive path. 12 SUBGRF_ON 14 Sub GHz Differential RF output, negative path. SUBGRF_IN 16 Sub GHz Differential RF input, negative path. RFVSS 17 Radio Ground PAVSS 18 Power Amplifier (PA) voltage regulator VSS 2G4RF_ION 19 2.4 GHz Differential RF input/output, negative path. This pin should be externally grounded. 2G4RF_IOP 20 2.4 GHz Differential RF input/output, positive path. PAVDD 21 Power Amplifier (PA) voltage regulator VDD input PD13 22 GPIO (5V) PD14 23 GPIO (5V) PD15 24 GPIO (5V) PA0 25 GPIO PA1 26 GPIO PA2 27 GPIO (5V) PA3 28 GPIO (5V) PA4 29 GPIO (5V) PA5 30 GPIO (5V) PB11 31 GPIO (5V) PB12 32 GPIO (5V) PB13 33 GPIO (5V) AVDD 34 Analog power supply. PB14 35 GPIO PB15 36 GPIO VREGVSS 37 Voltage regulator VSS VREGSW 38 DCDC regulator switching node VREGVDD 39 Voltage regulator VDD input DVDD 40 Digital power supply. DECOUPLE 41 Decouple output for on-chip voltage regulator. An external decoupling capacitor is required at this pin. IOVDD 42 Digital IO power supply. PC6 43 GPIO (5V) PC7 44 GPIO (5V) PC8 45 GPIO (5V) PC9 46 GPIO (5V) PC10 47 GPIO (5V) PC11 48 GPIO (5V) om m en de d fo r N ew D es ig ns RESETn Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. N ot R ec Note: 1. GPIO with 5V tolerance are indicated by (5V). 2. The pins PA2, PA3, PA4, PB11, PB12, PB13, PD13, PD14, and PD15 will not be 5V tolerant on all future devices. In order to preserve upgrade options with full hardware compatibility, do not use these pins with 5V domains. silabs.com | Building a more connected world. Rev. 1.5 | 106 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Pin Definitions m en de d fo r N ew D es ig ns 6.2 QFN48 2.4 GHz Device Pinout om Figure 6.2. QFN48 2.4 GHz Device Pinout ec The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 6.5 GPIO Functionality Table or 6.6 Alternate Functionality Overview. Pin(s) R Pin Name Table 6.2. QFN48 2.4 GHz Device Pinout Description Pin Name Pin(s) Description 0 Ground PF0 1 GPIO (5V) PF1 2 GPIO (5V) PF2 3 GPIO (5V) PF3 4 GPIO (5V) PF4 5 GPIO (5V) PF5 6 GPIO (5V) PF6 7 GPIO (5V) PF7 8 GPIO (5V) RFVDD 9 Radio power supply HFXTAL_N 10 High Frequency Crystal input pin. HFXTAL_P 11 High Frequency Crystal output pin. N ot VSS silabs.com | Building a more connected world. Rev. 1.5 | 107 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Pin Definitions Pin Name Pin(s) Description Pin Name Pin(s) Description NC 13 No Connect. PAVSS 15 Power Amplifier (PA) voltage regulator VSS 12 RFVSS 14 Radio Ground 2G4RF_ION 16 2.4 GHz Differential RF input/output, negative path. This pin should be externally grounded. 2G4RF_IOP 17 2.4 GHz Differential RF input/output, positive path. PAVDD 18 Power Amplifier (PA) voltage regulator VDD input PD10 19 GPIO (5V) PD11 20 GPIO (5V) PD12 21 GPIO (5V) PD13 22 GPIO (5V) PD14 23 GPIO (5V) PD15 24 GPIO (5V) PA0 25 GPIO PA1 26 GPIO PA2 27 GPIO (5V) PA3 28 GPIO (5V) PA4 29 GPIO (5V) PA5 30 GPIO (5V) PB11 31 GPIO (5V) PB12 32 GPIO (5V) PB13 33 GPIO (5V) AVDD 34 Analog power supply. PB15 36 GPIO VREGSW 38 DVDD fo r N ew D es ig ns RESETn Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. 35 GPIO VREGVSS 37 Voltage regulator VSS DCDC regulator switching node VREGVDD 39 Voltage regulator VDD input 40 Digital power supply. DECOUPLE 41 Decouple output for on-chip voltage regulator. An external decoupling capacitor is required at this pin. IOVDD 42 Digital IO power supply. PC6 43 GPIO (5V) PC7 44 GPIO (5V) PC8 45 GPIO (5V) PC9 46 GPIO (5V) PC10 47 GPIO (5V) PC11 48 GPIO (5V) om m en de d PB14 N ot R ec Note: 1. GPIO with 5V tolerance are indicated by (5V). 2. The pins PA2, PA3, PA4, PB11, PB12, PB13, PD13, PD14, and PD15 will not be 5V tolerant on all future devices. In order to preserve upgrade options with full hardware compatibility, do not use these pins with 5V domains. silabs.com | Building a more connected world. Rev. 1.5 | 108 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Pin Definitions m en de d fo r N ew D es ig ns 6.3 QFN48 Sub-GHz Device Pinout om Figure 6.3. QFN48 Sub-GHz Device Pinout ec The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 6.5 GPIO Functionality Table or 6.6 Alternate Functionality Overview. Pin(s) R Pin Name Table 6.3. QFN48 Sub-GHz Device Pinout Description Pin Name Pin(s) Description 0 Ground PF0 1 GPIO (5V) PF1 2 GPIO (5V) PF2 3 GPIO (5V) PF3 4 GPIO (5V) PF4 5 GPIO (5V) PF5 6 GPIO (5V) PF6 7 GPIO (5V) PF7 8 GPIO (5V) RFVDD 9 Radio power supply HFXTAL_N 10 High Frequency Crystal input pin. HFXTAL_P 11 High Frequency Crystal output pin. N ot VSS silabs.com | Building a more connected world. Rev. 1.5 | 109 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Pin Definitions Pin Name Pin(s) Description Pin Name Pin(s) Description SUBGRF_OP 13 Sub GHz Differential RF output, positive path. SUBGRF_IP 15 Sub GHz Differential RF input, positive path. RFVSS 17 Radio Ground 12 SUBGRF_ON 14 Sub GHz Differential RF output, negative path. SUBGRF_IN 16 Sub GHz Differential RF input, negative path. PD9 18 GPIO (5V) PD10 19 GPIO (5V) PD11 20 GPIO (5V) PD12 21 GPIO (5V) PD13 22 GPIO (5V) PD14 23 GPIO (5V) PD15 24 GPIO (5V) PA0 25 GPIO PA1 26 GPIO PA2 27 GPIO (5V) PA3 28 GPIO (5V) PA4 29 GPIO (5V) PA5 30 GPIO (5V) PB11 31 GPIO (5V) PB12 32 GPIO (5V) PB13 33 GPIO (5V) AVDD 34 Analog power supply. PB14 35 GPIO PB15 36 GPIO VREGSW 38 DCDC regulator switching node DVDD 40 Digital power supply. IOVDD 42 PC7 fo r N ew D es ig ns RESETn Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. 37 Voltage regulator VSS VREGVDD 39 Voltage regulator VDD input DECOUPLE 41 Decouple output for on-chip voltage regulator. An external decoupling capacitor is required at this pin. Digital IO power supply. PC6 43 GPIO (5V) 44 GPIO (5V) PC8 45 GPIO (5V) PC9 46 GPIO (5V) PC10 47 GPIO (5V) PC11 48 GPIO (5V) m en de d VREGVSS N ot R ec om Note: 1. GPIO with 5V tolerance are indicated by (5V). 2. The pins PA2, PA3, PA4, PB11, PB12, PB13, PD13, PD14, and PD15 will not be 5V tolerant on all future devices. In order to preserve upgrade options with full hardware compatibility, do not use these pins with 5V domains. silabs.com | Building a more connected world. Rev. 1.5 | 110 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Pin Definitions m en de d fo r N ew D es ig ns 6.4 QFN32 2.4 GHz Device Pinout om Figure 6.4. QFN32 2.4 GHz Device Pinout ec The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 6.5 GPIO Functionality Table or 6.6 Alternate Functionality Overview. Pin(s) R Pin Name Table 6.4. QFN32 2.4 GHz Device Pinout Description Pin Name Pin(s) Description 0 Ground PF0 1 GPIO (5V) PF1 2 GPIO (5V) PF2 3 GPIO (5V) PF3 4 GPIO (5V) RFVDD 5 Radio power supply HFXTAL_N 6 High Frequency Crystal input pin. HFXTAL_P 7 High Frequency Crystal output pin. 8 Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. RFVSS 9 Radio Ground N ot VSS RESETn silabs.com | Building a more connected world. Rev. 1.5 | 111 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Pin Definitions Pin Name Pin(s) Description Pin Name Pin(s) Description 11 2.4 GHz Differential RF input/output, negative path. This pin should be externally grounded. PAVDD 13 Power Amplifier (PA) voltage regulator VDD input GPIO (5V) PD14 15 GPIO (5V) 16 GPIO (5V) PA0 17 GPIO PA1 18 GPIO PB11 19 GPIO (5V) PB12 20 GPIO (5V) PB13 21 GPIO (5V) AVDD 22 Analog power supply. PB14 23 GPIO PB15 24 GPIO VREGVSS 25 Voltage regulator VSS VREGSW 26 DCDC regulator switching node VREGVDD 27 Voltage regulator VDD input DVDD 28 Digital power supply. DECOUPLE 29 Decouple output for on-chip voltage regulator. An external decoupling capacitor is required at this pin. IOVDD 30 Digital IO power supply. PC10 31 GPIO (5V) PC11 32 GPIO (5V) 2G4RF_IOP 12 2.4 GHz Differential RF input/output, positive path. PD13 14 PD15 D Power Amplifier (PA) voltage regulator VSS N ew 10 es ig ns 2G4RF_ION PAVSS N ot R ec om m en de d fo r Note: 1. GPIO with 5V tolerance are indicated by (5V). 2. The pins PB11, PB12, PB13, PD13, PD14, and PD15 will not be 5V tolerant on all future devices. In order to preserve upgrade options with full hardware compatibility, do not use these pins with 5V domains. silabs.com | Building a more connected world. Rev. 1.5 | 112 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Pin Definitions 6.5 GPIO Functionality Table A wide selection of alternate functionality is available for multiplexing to various pins. The following table shows the name of each GPIO pin, followed by the functionality available on that pin. Refer to 6.6 Alternate Functionality Overview for a list of GPIO locations available for each function. GPIO Name Pin Alternate Functionality / Description Communication Radio Other BUSDY BUSCX ADC0_EXTN TIM0_CC0 #0 TIM0_CC1 #31 TIM0_CC2 #30 TIM0_CDTI0 #29 TIM0_CDTI1 #28 TIM0_CDTI2 #27 TIM1_CC0 #0 TIM1_CC1 #31 TIM1_CC2 #30 TIM1_CC3 #29 LETIM0_OUT0 #0 LETIM0_OUT1 #31 PCNT0_S0IN #0 PCNT0_S1IN #31 US0_TX #0 US0_RX #31 US0_CLK #30 US0_CS #29 US0_CTS #28 US0_RTS #27 US1_TX #0 US1_RX #31 US1_CLK #30 US1_CS #29 US1_CTS #28 US1_RTS #27 LEU0_TX #0 LEU0_RX #31 I2C0_SDA #0 I2C0_SCL #31 FRC_DCLK #0 FRC_DOUT #31 FRC_DFRAME #30 MODEM_DCLK #0 MODEM_DIN #31 MODEM_DOUT #30 MODEM_ANT0 #29 MODEM_ANT1 #28 CMU_CLK1 #0 PRS_CH6 #0 PRS_CH7 #10 PRS_CH8 #9 PRS_CH9 #8 ACMP0_O #0 ACMP1_O #0 TIM0_CC0 #1 TIM0_CC1 #0 TIM0_CC2 #31 TIM0_CDTI0 #30 TIM0_CDTI1 #29 TIM0_CDTI2 #28 TIM1_CC0 #1 TIM1_CC1 #0 TIM1_CC2 #31 TIM1_CC3 #30 LETIM0_OUT0 #1 LETIM0_OUT1 #0 PCNT0_S0IN #1 PCNT0_S1IN #0 US0_TX #1 US0_RX #0 US0_CLK #31 US0_CS #30 US0_CTS #29 US0_RTS #28 US1_TX #1 US1_RX #0 US1_CLK #31 US1_CS #30 US1_CTS #29 US1_RTS #28 LEU0_TX #1 LEU0_RX #0 I2C0_SDA #1 I2C0_SCL #0 FRC_DCLK #1 FRC_DOUT #0 FRC_DFRAME #31 MODEM_DCLK #1 MODEM_DIN #0 MODEM_DOUT #31 MODEM_ANT0 #30 MODEM_ANT1 #29 CMU_CLK0 #0 PRS_CH6 #1 PRS_CH7 #0 PRS_CH8 #10 PRS_CH9 #9 ACMP0_O #1 ACMP1_O #1 US0_TX #2 US0_RX #1 US0_CLK #0 US0_CS #31 US0_CTS #30 US0_RTS #29 US1_TX #2 US1_RX #1 US1_CLK #0 US1_CS #31 US1_CTS #30 US1_RTS #29 LEU0_TX #2 LEU0_RX #1 I2C0_SDA #2 I2C0_SCL #1 FRC_DCLK #2 FRC_DOUT #1 FRC_DFRAME #0 MODEM_DCLK #2 MODEM_DIN #1 MODEM_DOUT #0 MODEM_ANT0 #31 MODEM_ANT1 #30 PRS_CH6 #2 PRS_CH7 #1 PRS_CH8 #0 PRS_CH9 #10 ACMP0_O #2 ACMP1_O #2 om N ot R ec BUSDY BUSCX silabs.com | Building a more connected world. TIM0_CC0 #2 TIM0_CC1 #1 TIM0_CC2 #0 TIM0_CDTI0 #31 TIM0_CDTI1 #30 TIM0_CDTI2 #29 TIM1_CC0 #2 TIM1_CC1 #1 TIM1_CC2 #0 TIM1_CC3 #31 LETIM0_OUT0 #2 LETIM0_OUT1 #1 PCNT0_S0IN #2 PCNT0_S1IN #1 fo r N ew D Timers BUSCY BUSDX ADC0_EXTP PA1 PA2 Analog m en de d PA0 es ig ns Table 6.5. GPIO Functionality Table Rev. 1.5 | 113 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Pin Definitions GPIO Name Pin Alternate Functionality / Description Radio Other BUSCY BUSDX TIM0_CC0 #3 TIM0_CC1 #2 TIM0_CC2 #1 TIM0_CDTI0 #0 TIM0_CDTI1 #31 TIM0_CDTI2 #30 TIM1_CC0 #3 TIM1_CC1 #2 TIM1_CC2 #1 TIM1_CC3 #0 LETIM0_OUT0 #3 LETIM0_OUT1 #2 PCNT0_S0IN #3 PCNT0_S1IN #2 US0_TX #3 US0_RX #2 US0_CLK #1 US0_CS #0 US0_CTS #31 US0_RTS #30 US1_TX #3 US1_RX #2 US1_CLK #1 US1_CS #0 US1_CTS #31 US1_RTS #30 LEU0_TX #3 LEU0_RX #2 I2C0_SDA #3 I2C0_SCL #2 FRC_DCLK #3 FRC_DOUT #2 FRC_DFRAME #1 MODEM_DCLK #3 MODEM_DIN #2 MODEM_DOUT #1 MODEM_ANT0 #0 MODEM_ANT1 #31 PRS_CH6 #3 PRS_CH7 #2 PRS_CH8 #1 PRS_CH9 #0 ACMP0_O #3 ACMP1_O #3 GPIO_EM4WU8 BUSDY BUSCX TIM0_CC0 #4 TIM0_CC1 #3 TIM0_CC2 #2 TIM0_CDTI0 #1 TIM0_CDTI1 #0 TIM0_CDTI2 #31 TIM1_CC0 #4 TIM1_CC1 #3 TIM1_CC2 #2 TIM1_CC3 #1 LETIM0_OUT0 #4 LETIM0_OUT1 #3 PCNT0_S0IN #4 PCNT0_S1IN #3 US0_TX #4 US0_RX #3 US0_CLK #2 US0_CS #1 US0_CTS #0 US0_RTS #31 US1_TX #4 US1_RX #3 US1_CLK #2 US1_CS #1 US1_CTS #0 US1_RTS #31 LEU0_TX #4 LEU0_RX #3 I2C0_SDA #4 I2C0_SCL #3 FRC_DCLK #4 FRC_DOUT #3 FRC_DFRAME #2 MODEM_DCLK #4 MODEM_DIN #3 MODEM_DOUT #2 MODEM_ANT0 #1 MODEM_ANT1 #0 PRS_CH6 #4 PRS_CH7 #3 PRS_CH8 #2 PRS_CH9 #1 ACMP0_O #4 ACMP1_O #4 BUSCY BUSDX R ec om PA5 N ot PB11 BUSCY BUSDX silabs.com | Building a more connected world. N ew D es ig ns Communication m en de d PA4 Timers fo r PA3 Analog TIM0_CC0 #5 TIM0_CC1 #4 TIM0_CC2 #3 TIM0_CDTI0 #2 TIM0_CDTI1 #1 TIM0_CDTI2 #0 TIM1_CC0 #5 TIM1_CC1 #4 TIM1_CC2 #3 TIM1_CC3 #2 LETIM0_OUT0 #5 LETIM0_OUT1 #4 PCNT0_S0IN #5 PCNT0_S1IN #4 US0_TX #5 US0_RX #4 US0_CLK #3 US0_CS #2 US0_CTS #1 US0_RTS #0 US1_TX #5 US1_RX #4 US1_CLK #3 US1_CS #2 US1_CTS #1 US1_RTS #0 LEU0_TX #5 LEU0_RX #4 I2C0_SDA #5 I2C0_SCL #4 FRC_DCLK #5 FRC_DOUT #4 FRC_DFRAME #3 MODEM_DCLK #5 MODEM_DIN #4 MODEM_DOUT #3 MODEM_ANT0 #2 MODEM_ANT1 #1 PRS_CH6 #5 PRS_CH7 #4 PRS_CH8 #3 PRS_CH9 #2 ACMP0_O #5 ACMP1_O #5 TIM0_CC0 #6 TIM0_CC1 #5 TIM0_CC2 #4 TIM0_CDTI0 #3 TIM0_CDTI1 #2 TIM0_CDTI2 #1 TIM1_CC0 #6 TIM1_CC1 #5 TIM1_CC2 #4 TIM1_CC3 #3 LETIM0_OUT0 #6 LETIM0_OUT1 #5 PCNT0_S0IN #6 PCNT0_S1IN #5 US0_TX #6 US0_RX #5 US0_CLK #4 US0_CS #3 US0_CTS #2 US0_RTS #1 US1_TX #6 US1_RX #5 US1_CLK #4 US1_CS #3 US1_CTS #2 US1_RTS #1 LEU0_TX #6 LEU0_RX #5 I2C0_SDA #6 I2C0_SCL #5 FRC_DCLK #6 FRC_DOUT #5 FRC_DFRAME #4 MODEM_DCLK #6 MODEM_DIN #5 MODEM_DOUT #4 MODEM_ANT0 #3 MODEM_ANT1 #2 PRS_CH6 #6 PRS_CH7 #5 PRS_CH8 #4 PRS_CH9 #3 ACMP0_O #6 ACMP1_O #6 Rev. 1.5 | 114 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Pin Definitions GPIO Name Pin Alternate Functionality / Description Radio Other BUSDY BUSCX TIM0_CC0 #7 TIM0_CC1 #6 TIM0_CC2 #5 TIM0_CDTI0 #4 TIM0_CDTI1 #3 TIM0_CDTI2 #2 TIM1_CC0 #7 TIM1_CC1 #6 TIM1_CC2 #5 TIM1_CC3 #4 LETIM0_OUT0 #7 LETIM0_OUT1 #6 PCNT0_S0IN #7 PCNT0_S1IN #6 US0_TX #7 US0_RX #6 US0_CLK #5 US0_CS #4 US0_CTS #3 US0_RTS #2 US1_TX #7 US1_RX #6 US1_CLK #5 US1_CS #4 US1_CTS #3 US1_RTS #2 LEU0_TX #7 LEU0_RX #6 I2C0_SDA #7 I2C0_SCL #6 FRC_DCLK #7 FRC_DOUT #6 FRC_DFRAME #5 MODEM_DCLK #7 MODEM_DIN #6 MODEM_DOUT #5 MODEM_ANT0 #4 MODEM_ANT1 #3 PRS_CH6 #7 PRS_CH7 #6 PRS_CH8 #5 PRS_CH9 #4 ACMP0_O #7 ACMP1_O #7 BUSCY BUSDX TIM0_CC0 #8 TIM0_CC1 #7 TIM0_CC2 #6 TIM0_CDTI0 #5 TIM0_CDTI1 #4 TIM0_CDTI2 #3 TIM1_CC0 #8 TIM1_CC1 #7 TIM1_CC2 #6 TIM1_CC3 #5 LETIM0_OUT0 #8 LETIM0_OUT1 #7 PCNT0_S0IN #8 PCNT0_S1IN #7 US0_TX #8 US0_RX #7 US0_CLK #6 US0_CS #5 US0_CTS #4 US0_RTS #3 US1_TX #8 US1_RX #7 US1_CLK #6 US1_CS #5 US1_CTS #4 US1_RTS #3 LEU0_TX #8 LEU0_RX #7 I2C0_SDA #8 I2C0_SCL #7 FRC_DCLK #8 FRC_DOUT #7 FRC_DFRAME #6 MODEM_DCLK #8 MODEM_DIN #7 MODEM_DOUT #6 MODEM_ANT0 #5 MODEM_ANT1 #4 PRS_CH6 #8 PRS_CH7 #7 PRS_CH8 #6 PRS_CH9 #5 ACMP0_O #8 ACMP1_O #8 DBG_SWO #1 GPIO_EM4WU9 BUSDY BUSCX LFXTAL_N N ot R ec om PB14 PB15 BUSCY BUSDX LFXTAL_P silabs.com | Building a more connected world. N ew D es ig ns Communication m en de d PB13 Timers fo r PB12 Analog TIM0_CC0 #9 TIM0_CC1 #8 TIM0_CC2 #7 TIM0_CDTI0 #6 TIM0_CDTI1 #5 TIM0_CDTI2 #4 TIM1_CC0 #9 TIM1_CC1 #8 TIM1_CC2 #7 TIM1_CC3 #6 LETIM0_OUT0 #9 LETIM0_OUT1 #8 PCNT0_S0IN #9 PCNT0_S1IN #8 US0_TX #9 US0_RX #8 US0_CLK #7 US0_CS #6 US0_CTS #5 US0_RTS #4 US1_TX #9 US1_RX #8 US1_CLK #7 US1_CS #6 US1_CTS #5 US1_RTS #4 LEU0_TX #9 LEU0_RX #8 I2C0_SDA #9 I2C0_SCL #8 FRC_DCLK #9 FRC_DOUT #8 FRC_DFRAME #7 MODEM_DCLK #9 MODEM_DIN #8 MODEM_DOUT #7 MODEM_ANT0 #6 MODEM_ANT1 #5 CMU_CLK1 #1 PRS_CH6 #9 PRS_CH7 #8 PRS_CH8 #7 PRS_CH9 #6 ACMP0_O #9 ACMP1_O #9 TIM0_CC0 #10 TIM0_CC1 #9 TIM0_CC2 #8 TIM0_CDTI0 #7 TIM0_CDTI1 #6 TIM0_CDTI2 #5 TIM1_CC0 #10 TIM1_CC1 #9 TIM1_CC2 #8 TIM1_CC3 #7 LETIM0_OUT0 #10 LETIM0_OUT1 #9 PCNT0_S0IN #10 PCNT0_S1IN #9 US0_TX #10 US0_RX #9 US0_CLK #8 US0_CS #7 US0_CTS #6 US0_RTS #5 US1_TX #10 US1_RX #9 US1_CLK #8 US1_CS #7 US1_CTS #6 US1_RTS #5 LEU0_TX #10 LEU0_RX #9 I2C0_SDA #10 I2C0_SCL #9 FRC_DCLK #10 FRC_DOUT #9 FRC_DFRAME #8 MODEM_DCLK #10 MODEM_DIN #9 MODEM_DOUT #8 MODEM_ANT0 #7 MODEM_ANT1 #6 CMU_CLK0 #1 PRS_CH6 #10 PRS_CH7 #9 PRS_CH8 #8 PRS_CH9 #7 ACMP0_O #10 ACMP1_O #10 Rev. 1.5 | 115 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Pin Definitions GPIO Name Pin Alternate Functionality / Description Radio Other BUSBY BUSAX TIM0_CC0 #11 TIM0_CC1 #10 TIM0_CC2 #9 TIM0_CDTI0 #8 TIM0_CDTI1 #7 TIM0_CDTI2 #6 TIM1_CC0 #11 TIM1_CC1 #10 TIM1_CC2 #9 TIM1_CC3 #8 LETIM0_OUT0 #11 LETIM0_OUT1 #10 PCNT0_S0IN #11 PCNT0_S1IN #10 US0_TX #11 US0_RX #10 US0_CLK #9 US0_CS #8 US0_CTS #7 US0_RTS #6 US1_TX #11 US1_RX #10 US1_CLK #9 US1_CS #8 US1_CTS #7 US1_RTS #6 LEU0_TX #11 LEU0_RX #10 I2C0_SDA #11 I2C0_SCL #10 FRC_DCLK #11 FRC_DOUT #10 FRC_DFRAME #9 MODEM_DCLK #11 MODEM_DIN #10 MODEM_DOUT #9 MODEM_ANT0 #8 MODEM_ANT1 #7 CMU_CLK0 #2 PRS_CH0 #8 PRS_CH9 #11 PRS_CH10 #0 PRS_CH11 #5 ACMP0_O #11 ACMP1_O #11 BUSAY BUSBX TIM0_CC0 #12 TIM0_CC1 #11 TIM0_CC2 #10 TIM0_CDTI0 #9 TIM0_CDTI1 #8 TIM0_CDTI2 #7 TIM1_CC0 #12 TIM1_CC1 #11 TIM1_CC2 #10 TIM1_CC3 #9 LETIM0_OUT0 #12 LETIM0_OUT1 #11 PCNT0_S0IN #12 PCNT0_S1IN #11 US0_TX #12 US0_RX #11 US0_CLK #10 US0_CS #9 US0_CTS #8 US0_RTS #7 US1_TX #12 US1_RX #11 US1_CLK #10 US1_CS #9 US1_CTS #8 US1_RTS #7 LEU0_TX #12 LEU0_RX #11 I2C0_SDA #12 I2C0_SCL #11 FRC_DCLK #12 FRC_DOUT #11 FRC_DFRAME #10 MODEM_DCLK #12 MODEM_DIN #11 MODEM_DOUT #10 MODEM_ANT0 #9 MODEM_ANT1 #8 CMU_CLK1 #2 PRS_CH0 #9 PRS_CH9 #12 PRS_CH10 #1 PRS_CH11 #0 ACMP0_O #12 ACMP1_O #12 US0_TX #13 US0_RX #12 US0_CLK #11 US0_CS #10 US0_CTS #9 US0_RTS #8 US1_TX #13 US1_RX #12 US1_CLK #11 US1_CS #10 US1_CTS #9 US1_RTS #8 LEU0_TX #13 LEU0_RX #12 I2C0_SDA #13 I2C0_SCL #12 FRC_DCLK #13 FRC_DOUT #12 FRC_DFRAME #11 MODEM_DCLK #13 MODEM_DIN #12 MODEM_DOUT #11 MODEM_ANT0 #10 MODEM_ANT1 #9 PRS_CH0 #10 PRS_CH9 #13 PRS_CH10 #2 PRS_CH11 #1 ACMP0_O #13 ACMP1_O #13 om BUSBY BUSAX D N ew N ot R ec PC8 TIM0_CC0 #13 TIM0_CC1 #12 TIM0_CC2 #11 TIM0_CDTI0 #10 TIM0_CDTI1 #9 TIM0_CDTI2 #8 TIM1_CC0 #13 TIM1_CC1 #12 TIM1_CC2 #11 TIM1_CC3 #10 LETIM0_OUT0 #13 LETIM0_OUT1 #12 PCNT0_S0IN #13 PCNT0_S1IN #12 es ig ns Communication m en de d PC7 Timers fo r PC6 Analog silabs.com | Building a more connected world. Rev. 1.5 | 116 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Pin Definitions GPIO Name Pin Alternate Functionality / Description Radio Other BUSAY BUSBX TIM0_CC0 #14 TIM0_CC1 #13 TIM0_CC2 #12 TIM0_CDTI0 #11 TIM0_CDTI1 #10 TIM0_CDTI2 #9 TIM1_CC0 #14 TIM1_CC1 #13 TIM1_CC2 #12 TIM1_CC3 #11 LETIM0_OUT0 #14 LETIM0_OUT1 #13 PCNT0_S0IN #14 PCNT0_S1IN #13 US0_TX #14 US0_RX #13 US0_CLK #12 US0_CS #11 US0_CTS #10 US0_RTS #9 US1_TX #14 US1_RX #13 US1_CLK #12 US1_CS #11 US1_CTS #10 US1_RTS #9 LEU0_TX #14 LEU0_RX #13 I2C0_SDA #14 I2C0_SCL #13 FRC_DCLK #14 FRC_DOUT #13 FRC_DFRAME #12 MODEM_DCLK #14 MODEM_DIN #13 MODEM_DOUT #12 MODEM_ANT0 #11 MODEM_ANT1 #10 PRS_CH0 #11 PRS_CH9 #14 PRS_CH10 #3 PRS_CH11 #2 ACMP0_O #14 ACMP1_O #14 BUSBY BUSAX TIM0_CC0 #15 TIM0_CC1 #14 TIM0_CC2 #13 TIM0_CDTI0 #12 TIM0_CDTI1 #11 TIM0_CDTI2 #10 TIM1_CC0 #15 TIM1_CC1 #14 TIM1_CC2 #13 TIM1_CC3 #12 LETIM0_OUT0 #15 LETIM0_OUT1 #14 PCNT0_S0IN #15 PCNT0_S1IN #14 US0_TX #15 US0_RX #14 US0_CLK #13 US0_CS #12 US0_CTS #11 US0_RTS #10 US1_TX #15 US1_RX #14 US1_CLK #13 US1_CS #12 US1_CTS #11 US1_RTS #10 LEU0_TX #15 LEU0_RX #14 I2C0_SDA #15 I2C0_SCL #14 FRC_DCLK #15 FRC_DOUT #14 FRC_DFRAME #13 MODEM_DCLK #15 MODEM_DIN #14 MODEM_DOUT #13 MODEM_ANT0 #12 MODEM_ANT1 #11 CMU_CLK1 #3 PRS_CH0 #12 PRS_CH9 #15 PRS_CH10 #4 PRS_CH11 #3 ACMP0_O #15 ACMP1_O #15 GPIO_EM4WU12 US0_TX #16 US0_RX #15 US0_CLK #14 US0_CS #13 US0_CTS #12 US0_RTS #11 US1_TX #16 US1_RX #15 US1_CLK #14 US1_CS #13 US1_CTS #12 US1_RTS #11 LEU0_TX #16 LEU0_RX #15 I2C0_SDA #16 I2C0_SCL #15 FRC_DCLK #16 FRC_DOUT #15 FRC_DFRAME #14 MODEM_DCLK #16 MODEM_DIN #15 MODEM_DOUT #14 MODEM_ANT0 #13 MODEM_ANT1 #12 CMU_CLK0 #3 PRS_CH0 #13 PRS_CH9 #16 PRS_CH10 #5 PRS_CH11 #4 ACMP0_O #16 ACMP1_O #16 DBG_SWO #3 om BUSAY BUSBX D N ew N ot R ec PC11 TIM0_CC0 #16 TIM0_CC1 #15 TIM0_CC2 #14 TIM0_CDTI0 #13 TIM0_CDTI1 #12 TIM0_CDTI2 #11 TIM1_CC0 #16 TIM1_CC1 #15 TIM1_CC2 #14 TIM1_CC3 #13 LETIM0_OUT0 #16 LETIM0_OUT1 #15 PCNT0_S0IN #16 PCNT0_S1IN #15 es ig ns Communication m en de d PC10 Timers fo r PC9 Analog silabs.com | Building a more connected world. Rev. 1.5 | 117 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Pin Definitions GPIO Name Pin Alternate Functionality / Description Radio Other BUSCY BUSDX TIM0_CC0 #17 TIM0_CC1 #16 TIM0_CC2 #15 TIM0_CDTI0 #14 TIM0_CDTI1 #13 TIM0_CDTI2 #12 TIM1_CC0 #17 TIM1_CC1 #16 TIM1_CC2 #15 TIM1_CC3 #14 LETIM0_OUT0 #17 LETIM0_OUT1 #16 PCNT0_S0IN #17 PCNT0_S1IN #16 US0_TX #17 US0_RX #16 US0_CLK #15 US0_CS #14 US0_CTS #13 US0_RTS #12 US1_TX #17 US1_RX #16 US1_CLK #15 US1_CS #14 US1_CTS #13 US1_RTS #12 LEU0_TX #17 LEU0_RX #16 I2C0_SDA #17 I2C0_SCL #16 FRC_DCLK #17 FRC_DOUT #16 FRC_DFRAME #15 MODEM_DCLK #17 MODEM_DIN #16 MODEM_DOUT #15 MODEM_ANT0 #14 MODEM_ANT1 #13 CMU_CLK0 #4 PRS_CH3 #8 PRS_CH4 #0 PRS_CH5 #6 PRS_CH6 #11 ACMP0_O #17 ACMP1_O #17 BUSDY BUSCX TIM0_CC0 #18 TIM0_CC1 #17 TIM0_CC2 #16 TIM0_CDTI0 #15 TIM0_CDTI1 #14 TIM0_CDTI2 #13 TIM1_CC0 #18 TIM1_CC1 #17 TIM1_CC2 #16 TIM1_CC3 #15 LETIM0_OUT0 #18 LETIM0_OUT1 #17 PCNT0_S0IN #18 PCNT0_S1IN #17 US0_TX #18 US0_RX #17 US0_CLK #16 US0_CS #15 US0_CTS #14 US0_RTS #13 US1_TX #18 US1_RX #17 US1_CLK #16 US1_CS #15 US1_CTS #14 US1_RTS #13 LEU0_TX #18 LEU0_RX #17 I2C0_SDA #18 I2C0_SCL #17 FRC_DCLK #18 FRC_DOUT #17 FRC_DFRAME #16 MODEM_DCLK #18 MODEM_DIN #17 MODEM_DOUT #16 MODEM_ANT0 #15 MODEM_ANT1 #14 CMU_CLK1 #4 PRS_CH3 #9 PRS_CH4 #1 PRS_CH5 #0 PRS_CH6 #12 ACMP0_O #18 ACMP1_O #18 US0_TX #19 US0_RX #18 US0_CLK #17 US0_CS #16 US0_CTS #15 US0_RTS #14 US1_TX #19 US1_RX #18 US1_CLK #17 US1_CS #16 US1_CTS #15 US1_RTS #14 LEU0_TX #19 LEU0_RX #18 I2C0_SDA #19 I2C0_SCL #18 FRC_DCLK #19 FRC_DOUT #18 FRC_DFRAME #17 MODEM_DCLK #19 MODEM_DIN #18 MODEM_DOUT #17 MODEM_ANT0 #16 MODEM_ANT1 #15 PRS_CH3 #10 PRS_CH4 #2 PRS_CH5 #1 PRS_CH6 #13 ACMP0_O #19 ACMP1_O #19 om BUSCY BUSDX D N ew N ot R ec PD11 TIM0_CC0 #19 TIM0_CC1 #18 TIM0_CC2 #17 TIM0_CDTI0 #16 TIM0_CDTI1 #15 TIM0_CDTI2 #14 TIM1_CC0 #19 TIM1_CC1 #18 TIM1_CC2 #17 TIM1_CC3 #16 LETIM0_OUT0 #19 LETIM0_OUT1 #18 PCNT0_S0IN #19 PCNT0_S1IN #18 es ig ns Communication m en de d PD10 Timers fo r PD9 Analog silabs.com | Building a more connected world. Rev. 1.5 | 118 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Pin Definitions GPIO Name Pin Alternate Functionality / Description Radio Other BUSDY BUSCX TIM0_CC0 #20 TIM0_CC1 #19 TIM0_CC2 #18 TIM0_CDTI0 #17 TIM0_CDTI1 #16 TIM0_CDTI2 #15 TIM1_CC0 #20 TIM1_CC1 #19 TIM1_CC2 #18 TIM1_CC3 #17 LETIM0_OUT0 #20 LETIM0_OUT1 #19 PCNT0_S0IN #20 PCNT0_S1IN #19 US0_TX #20 US0_RX #19 US0_CLK #18 US0_CS #17 US0_CTS #16 US0_RTS #15 US1_TX #20 US1_RX #19 US1_CLK #18 US1_CS #17 US1_CTS #16 US1_RTS #15 LEU0_TX #20 LEU0_RX #19 I2C0_SDA #20 I2C0_SCL #19 FRC_DCLK #20 FRC_DOUT #19 FRC_DFRAME #18 MODEM_DCLK #20 MODEM_DIN #19 MODEM_DOUT #18 MODEM_ANT0 #17 MODEM_ANT1 #16 PRS_CH3 #11 PRS_CH4 #3 PRS_CH5 #2 PRS_CH6 #14 ACMP0_O #20 ACMP1_O #20 BUSCY BUSDX TIM0_CC0 #21 TIM0_CC1 #20 TIM0_CC2 #19 TIM0_CDTI0 #18 TIM0_CDTI1 #17 TIM0_CDTI2 #16 TIM1_CC0 #21 TIM1_CC1 #20 TIM1_CC2 #19 TIM1_CC3 #18 LETIM0_OUT0 #21 LETIM0_OUT1 #20 PCNT0_S0IN #21 PCNT0_S1IN #20 US0_TX #21 US0_RX #20 US0_CLK #19 US0_CS #18 US0_CTS #17 US0_RTS #16 US1_TX #21 US1_RX #20 US1_CLK #19 US1_CS #18 US1_CTS #17 US1_RTS #16 LEU0_TX #21 LEU0_RX #20 I2C0_SDA #21 I2C0_SCL #20 FRC_DCLK #21 FRC_DOUT #20 FRC_DFRAME #19 MODEM_DCLK #21 MODEM_DIN #20 MODEM_DOUT #19 MODEM_ANT0 #18 MODEM_ANT1 #17 PRS_CH3 #12 PRS_CH4 #4 PRS_CH5 #3 PRS_CH6 #15 ACMP0_O #21 ACMP1_O #21 US0_TX #22 US0_RX #21 US0_CLK #20 US0_CS #19 US0_CTS #18 US0_RTS #17 US1_TX #22 US1_RX #21 US1_CLK #20 US1_CS #19 US1_CTS #18 US1_RTS #17 LEU0_TX #22 LEU0_RX #21 I2C0_SDA #22 I2C0_SCL #21 FRC_DCLK #22 FRC_DOUT #21 FRC_DFRAME #20 MODEM_DCLK #22 MODEM_DIN #21 MODEM_DOUT #20 MODEM_ANT0 #19 MODEM_ANT1 #18 CMU_CLK0 #5 PRS_CH3 #13 PRS_CH4 #5 PRS_CH5 #4 PRS_CH6 #16 ACMP0_O #22 ACMP1_O #22 GPIO_EM4WU4 om BUSDY BUSCX D N ew N ot R ec PD14 TIM0_CC0 #22 TIM0_CC1 #21 TIM0_CC2 #20 TIM0_CDTI0 #19 TIM0_CDTI1 #18 TIM0_CDTI2 #17 TIM1_CC0 #22 TIM1_CC1 #21 TIM1_CC2 #20 TIM1_CC3 #19 LETIM0_OUT0 #22 LETIM0_OUT1 #21 PCNT0_S0IN #22 PCNT0_S1IN #21 es ig ns Communication m en de d PD13 Timers fo r PD12 Analog silabs.com | Building a more connected world. Rev. 1.5 | 119 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Pin Definitions GPIO Name Pin Alternate Functionality / Description Radio Other BUSCY BUSDX TIM0_CC0 #23 TIM0_CC1 #22 TIM0_CC2 #21 TIM0_CDTI0 #20 TIM0_CDTI1 #19 TIM0_CDTI2 #18 TIM1_CC0 #23 TIM1_CC1 #22 TIM1_CC2 #21 TIM1_CC3 #20 LETIM0_OUT0 #23 LETIM0_OUT1 #22 PCNT0_S0IN #23 PCNT0_S1IN #22 US0_TX #23 US0_RX #22 US0_CLK #21 US0_CS #20 US0_CTS #19 US0_RTS #18 US1_TX #23 US1_RX #22 US1_CLK #21 US1_CS #20 US1_CTS #19 US1_RTS #18 LEU0_TX #23 LEU0_RX #22 I2C0_SDA #23 I2C0_SCL #22 FRC_DCLK #23 FRC_DOUT #22 FRC_DFRAME #21 MODEM_DCLK #23 MODEM_DIN #22 MODEM_DOUT #21 MODEM_ANT0 #20 MODEM_ANT1 #19 CMU_CLK1 #5 PRS_CH3 #14 PRS_CH4 #6 PRS_CH5 #5 PRS_CH6 #17 ACMP0_O #23 ACMP1_O #23 DBG_SWO #2 BUSBY BUSAX TIM0_CC0 #24 TIM0_CC1 #23 TIM0_CC2 #22 TIM0_CDTI0 #21 TIM0_CDTI1 #20 TIM0_CDTI2 #19 TIM1_CC0 #24 TIM1_CC1 #23 TIM1_CC2 #22 TIM1_CC3 #21 LETIM0_OUT0 #24 LETIM0_OUT1 #23 PCNT0_S0IN #24 PCNT0_S1IN #23 US0_TX #24 US0_RX #23 US0_CLK #22 US0_CS #21 US0_CTS #20 US0_RTS #19 US1_TX #24 US1_RX #23 US1_CLK #22 US1_CS #21 US1_CTS #20 US1_RTS #19 LEU0_TX #24 LEU0_RX #23 I2C0_SDA #24 I2C0_SCL #23 FRC_DCLK #24 FRC_DOUT #23 FRC_DFRAME #22 MODEM_DCLK #24 MODEM_DIN #23 MODEM_DOUT #22 MODEM_ANT0 #21 MODEM_ANT1 #20 PRS_CH0 #0 PRS_CH1 #7 PRS_CH2 #6 PRS_CH3 #5 ACMP0_O #24 ACMP1_O #24 DBG_SWCLKTCK US0_TX #25 US0_RX #24 US0_CLK #23 US0_CS #22 US0_CTS #21 US0_RTS #20 US1_TX #25 US1_RX #24 US1_CLK #23 US1_CS #22 US1_CTS #21 US1_RTS #20 LEU0_TX #25 LEU0_RX #24 I2C0_SDA #25 I2C0_SCL #24 FRC_DCLK #25 FRC_DOUT #24 FRC_DFRAME #23 MODEM_DCLK #25 MODEM_DIN #24 MODEM_DOUT #23 MODEM_ANT0 #22 MODEM_ANT1 #21 PRS_CH0 #1 PRS_CH1 #0 PRS_CH2 #7 PRS_CH3 #6 ACMP0_O #25 ACMP1_O #25 DBG_SWDIOTMS om BUSAY BUSBX D N ew N ot R ec PF1 TIM0_CC0 #25 TIM0_CC1 #24 TIM0_CC2 #23 TIM0_CDTI0 #22 TIM0_CDTI1 #21 TIM0_CDTI2 #20 TIM1_CC0 #25 TIM1_CC1 #24 TIM1_CC2 #23 TIM1_CC3 #22 LETIM0_OUT0 #25 LETIM0_OUT1 #24 PCNT0_S0IN #25 PCNT0_S1IN #24 es ig ns Communication m en de d PF0 Timers fo r PD15 Analog silabs.com | Building a more connected world. Rev. 1.5 | 120 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Pin Definitions GPIO Name Pin Alternate Functionality / Description Radio Other BUSBY BUSAX TIM0_CC0 #26 TIM0_CC1 #25 TIM0_CC2 #24 TIM0_CDTI0 #23 TIM0_CDTI1 #22 TIM0_CDTI2 #21 TIM1_CC0 #26 TIM1_CC1 #25 TIM1_CC2 #24 TIM1_CC3 #23 LETIM0_OUT0 #26 LETIM0_OUT1 #25 PCNT0_S0IN #26 PCNT0_S1IN #25 US0_TX #26 US0_RX #25 US0_CLK #24 US0_CS #23 US0_CTS #22 US0_RTS #21 US1_TX #26 US1_RX #25 US1_CLK #24 US1_CS #23 US1_CTS #22 US1_RTS #21 LEU0_TX #26 LEU0_RX #25 I2C0_SDA #26 I2C0_SCL #25 FRC_DCLK #26 FRC_DOUT #25 FRC_DFRAME #24 MODEM_DCLK #26 MODEM_DIN #25 MODEM_DOUT #24 MODEM_ANT0 #23 MODEM_ANT1 #22 CMU_CLK0 #6 PRS_CH0 #2 PRS_CH1 #1 PRS_CH2 #0 PRS_CH3 #7 ACMP0_O #26 ACMP1_O #26 DBG_TDO DBG_SWO #0 GPIO_EM4WU0 BUSAY BUSBX TIM0_CC0 #27 TIM0_CC1 #26 TIM0_CC2 #25 TIM0_CDTI0 #24 TIM0_CDTI1 #23 TIM0_CDTI2 #22 TIM1_CC0 #27 TIM1_CC1 #26 TIM1_CC2 #25 TIM1_CC3 #24 LETIM0_OUT0 #27 LETIM0_OUT1 #26 PCNT0_S0IN #27 PCNT0_S1IN #26 US0_TX #27 US0_RX #26 US0_CLK #25 US0_CS #24 US0_CTS #23 US0_RTS #22 US1_TX #27 US1_RX #26 US1_CLK #25 US1_CS #24 US1_CTS #23 US1_RTS #22 LEU0_TX #27 LEU0_RX #26 I2C0_SDA #27 I2C0_SCL #26 FRC_DCLK #27 FRC_DOUT #26 FRC_DFRAME #25 MODEM_DCLK #27 MODEM_DIN #26 MODEM_DOUT #25 MODEM_ANT0 #24 MODEM_ANT1 #23 CMU_CLK1 #6 PRS_CH0 #3 PRS_CH1 #2 PRS_CH2 #1 PRS_CH3 #0 ACMP0_O #27 ACMP1_O #27 DBG_TDI US0_TX #28 US0_RX #27 US0_CLK #26 US0_CS #25 US0_CTS #24 US0_RTS #23 US1_TX #28 US1_RX #27 US1_CLK #26 US1_CS #25 US1_CTS #24 US1_RTS #23 LEU0_TX #28 LEU0_RX #27 I2C0_SDA #28 I2C0_SCL #27 FRC_DCLK #28 FRC_DOUT #27 FRC_DFRAME #26 MODEM_DCLK #28 MODEM_DIN #27 MODEM_DOUT #26 MODEM_ANT0 #25 MODEM_ANT1 #24 PRS_CH0 #4 PRS_CH1 #3 PRS_CH2 #2 PRS_CH3 #1 ACMP0_O #28 ACMP1_O #28 om BUSBY BUSAX D N ew N ot R ec PF4 TIM0_CC0 #28 TIM0_CC1 #27 TIM0_CC2 #26 TIM0_CDTI0 #25 TIM0_CDTI1 #24 TIM0_CDTI2 #23 TIM1_CC0 #28 TIM1_CC1 #27 TIM1_CC2 #26 TIM1_CC3 #25 LETIM0_OUT0 #28 LETIM0_OUT1 #27 PCNT0_S0IN #28 PCNT0_S1IN #27 es ig ns Communication m en de d PF3 Timers fo r PF2 Analog silabs.com | Building a more connected world. Rev. 1.5 | 121 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Pin Definitions GPIO Name Pin Alternate Functionality / Description Radio Other BUSAY BUSBX TIM0_CC0 #29 TIM0_CC1 #28 TIM0_CC2 #27 TIM0_CDTI0 #26 TIM0_CDTI1 #25 TIM0_CDTI2 #24 TIM1_CC0 #29 TIM1_CC1 #28 TIM1_CC2 #27 TIM1_CC3 #26 LETIM0_OUT0 #29 LETIM0_OUT1 #28 PCNT0_S0IN #29 PCNT0_S1IN #28 US0_TX #29 US0_RX #28 US0_CLK #27 US0_CS #26 US0_CTS #25 US0_RTS #24 US1_TX #29 US1_RX #28 US1_CLK #27 US1_CS #26 US1_CTS #25 US1_RTS #24 LEU0_TX #29 LEU0_RX #28 I2C0_SDA #29 I2C0_SCL #28 FRC_DCLK #29 FRC_DOUT #28 FRC_DFRAME #27 MODEM_DCLK #29 MODEM_DIN #28 MODEM_DOUT #27 MODEM_ANT0 #26 MODEM_ANT1 #25 PRS_CH0 #5 PRS_CH1 #4 PRS_CH2 #3 PRS_CH3 #2 ACMP0_O #29 ACMP1_O #29 BUSBY BUSAX TIM0_CC0 #30 TIM0_CC1 #29 TIM0_CC2 #28 TIM0_CDTI0 #27 TIM0_CDTI1 #26 TIM0_CDTI2 #25 TIM1_CC0 #30 TIM1_CC1 #29 TIM1_CC2 #28 TIM1_CC3 #27 LETIM0_OUT0 #30 LETIM0_OUT1 #29 PCNT0_S0IN #30 PCNT0_S1IN #29 US0_TX #30 US0_RX #29 US0_CLK #28 US0_CS #27 US0_CTS #26 US0_RTS #25 US1_TX #30 US1_RX #29 US1_CLK #28 US1_CS #27 US1_CTS #26 US1_RTS #25 LEU0_TX #30 LEU0_RX #29 I2C0_SDA #30 I2C0_SCL #29 FRC_DCLK #30 FRC_DOUT #29 FRC_DFRAME #28 MODEM_DCLK #30 MODEM_DIN #29 MODEM_DOUT #28 MODEM_ANT0 #27 MODEM_ANT1 #26 CMU_CLK1 #7 PRS_CH0 #6 PRS_CH1 #5 PRS_CH2 #4 PRS_CH3 #3 ACMP0_O #30 ACMP1_O #30 US0_TX #31 US0_RX #30 US0_CLK #29 US0_CS #28 US0_CTS #27 US0_RTS #26 US1_TX #31 US1_RX #30 US1_CLK #29 US1_CS #28 US1_CTS #27 US1_RTS #26 LEU0_TX #31 LEU0_RX #30 I2C0_SDA #31 I2C0_SCL #30 FRC_DCLK #31 FRC_DOUT #30 FRC_DFRAME #29 MODEM_DCLK #31 MODEM_DIN #30 MODEM_DOUT #29 MODEM_ANT0 #28 MODEM_ANT1 #27 CMU_CLK0 #7 PRS_CH0 #7 PRS_CH1 #6 PRS_CH2 #5 PRS_CH3 #4 ACMP0_O #31 ACMP1_O #31 GPIO_EM4WU1 om BUSAY BUSBX D N ew N ot R ec PF7 TIM0_CC0 #31 TIM0_CC1 #30 TIM0_CC2 #29 TIM0_CDTI0 #28 TIM0_CDTI1 #27 TIM0_CDTI2 #26 TIM1_CC0 #31 TIM1_CC1 #30 TIM1_CC2 #29 TIM1_CC3 #28 LETIM0_OUT0 #31 LETIM0_OUT1 #30 PCNT0_S0IN #31 PCNT0_S1IN #30 es ig ns Communication m en de d PF6 Timers fo r PF5 Analog silabs.com | Building a more connected world. Rev. 1.5 | 122 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Pin Definitions 6.6 Alternate Functionality Overview A wide selection of alternate functionality is available for multiplexing to various pins. The following table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings and the associated GPIO pin. Refer to 6.5 GPIO Functionality Table for a list of functions available on each GPIO pin. Table 6.6. Alternate Functionality Overview LOCATION 0-3 4-7 8 - 11 12 - 15 16 - 19 20 - 23 ACMP0_O 0: PA0 1: PA1 2: PA2 3: PA3 4: PA4 5: PA5 6: PB11 7: PB12 8: PB13 9: PB14 10: PB15 11: PC6 12: PC7 13: PC8 14: PC9 15: PC10 16: PC11 17: PD9 18: PD10 19: PD11 20: PD12 21: PD13 22: PD14 23: PD15 ACMP1_O 0: PA0 1: PA1 2: PA2 3: PA3 4: PA4 5: PA5 6: PB11 7: PB12 8: PB13 9: PB14 10: PB15 11: PC6 12: PC7 13: PC8 14: PC9 15: PC10 16: PC11 17: PD9 18: PD10 19: PD11 0: PA0 CMU_CLK1 0: PA0 1: PB14 2: PC7 3: PC10 24: PF0 25: PF1 26: PF2 27: PF3 28 - 31 28: PF4 29: PF5 30: PF6 31: PF7 24: PF0 25: PF1 26: PF2 27: PF3 28: PF4 29: PF5 30: PF6 31: PF7 Description Analog comparator ACMP0, digital output. Analog comparator ACMP1, digital output. Analog to digital converter ADC0 external reference input negative pin. Analog to digital converter ADC0 external reference input positive pin. 4: PD9 5: PD14 6: PF2 7: PF7 Clock Management Unit, clock output number 0. 4: PD10 5: PD15 6: PF3 7: PF6 Clock Management Unit, clock output number 1. om CMU_CLK0 0: PA1 1: PB15 2: PC6 3: PC11 m en de d 0: PA1 ADC0_EXTP 20: PD12 21: PD13 22: PD14 23: PD15 fo r ADC0_EXTN 24 - 27 N ew Functionality D Alternate es ig ns Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0. ec 0: PF0 Note that this function is enabled to the pin out of reset, and has a built-in pull down. N ot R DBG_SWCLKTCK Debug-interface Serial Wire clock input and JTAG Test Clock. silabs.com | Building a more connected world. Rev. 1.5 | 123 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Pin Definitions Alternate LOCATION Functionality 0-3 4-7 8 - 11 12 - 15 16 - 19 20 - 23 24 - 27 28 - 31 0: PF1 Debug-interface Serial Wire data input / output and JTAG Test Mode Select. es ig ns DBG_SWDIOTMS Note that this function is enabled to the pin out of reset, and has a built-in pull up. D 0: PF2 1: PB13 2: PD15 3: PC11 N ew DBG_SWO fo r 0: PF3 0: PF2 om DBG_TDO Debug-interface JTAG Test Data In. Debug-interface JTAG Test Data Out. Note that this function becomes available after the first valid JTAG command is received. 4: PA4 5: PA5 6: PB11 7: PB12 8: PB13 9: PB14 10: PB15 11: PC6 12: PC7 13: PC8 14: PC9 15: PC10 16: PC11 17: PD9 18: PD10 19: PD11 20: PD12 21: PD13 22: PD14 23: PD15 24: PF0 25: PF1 26: PF2 27: PF3 28: PF4 29: PF5 30: PF6 31: PF7 Frame Controller, Data Sniffer Clock. 0: PA2 1: PA3 2: PA4 3: PA5 4: PB11 5: PB12 6: PB13 7: PB14 8: PB15 9: PC6 10: PC7 11: PC8 12: PC9 13: PC10 14: PC11 15: PD9 16: PD10 17: PD11 18: PD12 19: PD13 20: PD14 21: PD15 22: PF0 23: PF1 24: PF2 25: PF3 26: PF4 27: PF5 28: PF6 29: PF7 30: PA0 31: PA1 Frame Controller, Data Sniffer Frame active 0: PA1 1: PA2 2: PA3 3: PA4 4: PA5 5: PB11 6: PB12 7: PB13 8: PB14 9: PB15 10: PC6 11: PC7 12: PC8 13: PC9 14: PC10 15: PC11 16: PD9 17: PD10 18: PD11 19: PD12 20: PD13 21: PD14 22: PD15 23: PF0 24: PF1 25: PF2 26: PF3 27: PF4 28: PF5 29: PF6 30: PF7 31: PA0 Frame Controller, Data Sniffer Output. ec FRC_DOUT Note that this function is not enabled after reset, and must be enabled by software to be used. 0: PA0 1: PA1 2: PA2 3: PA3 R N ot FRC_DFRAME Debug-interface Serial Wire viewer Output. Note that this function becomes available after the first valid JTAG command is received, and has a built-in pull up when JTAG is active. m en de d DBG_TDI FRC_DCLK Description 0: PF2 GPIO_EM4WU0 silabs.com | Building a more connected world. Pin can be used to wake the system up from EM4 Rev. 1.5 | 124 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Pin Definitions Alternate LOCATION Functionality 0-3 4-7 8 - 11 12 - 15 16 - 19 20 - 23 24 - 27 28 - 31 0: PF7 Description Pin can be used to wake the system up from EM4 GPIO_EM4WU1 es ig ns 0: PD14 Pin can be used to wake the system up from EM4 GPIO_EM4WU4 0: PA3 Pin can be used to wake the system up from EM4 GPIO_EM4WU8 D 0: PB13 N ew GPIO_EM4WU9 0: PC10 GPIO_EM4WU12 Pin can be used to wake the system up from EM4 Pin can be used to wake the system up from EM4 4: PA5 5: PB11 6: PB12 7: PB13 8: PB14 9: PB15 10: PC6 11: PC7 12: PC8 13: PC9 14: PC10 15: PC11 16: PD9 17: PD10 18: PD11 19: PD12 20: PD13 21: PD14 22: PD15 23: PF0 24: PF1 25: PF2 26: PF3 27: PF4 28: PF5 29: PF6 30: PF7 31: PA0 I2C0 Serial Clock Line input / output. I2C0_SDA 0: PA0 1: PA1 2: PA2 3: PA3 4: PA4 5: PA5 6: PB11 7: PB12 8: PB13 9: PB14 10: PB15 11: PC6 12: PC7 13: PC8 14: PC9 15: PC10 16: PC11 17: PD9 18: PD10 19: PD11 20: PD12 21: PD13 22: PD14 23: PD15 24: PF0 25: PF1 26: PF2 27: PF3 28: PF4 29: PF5 30: PF6 31: PF7 I2C0 Serial Data input / output. LETIM0_OUT0 0: PA0 1: PA1 2: PA2 3: PA3 4: PA4 5: PA5 6: PB11 7: PB12 8: PB13 9: PB14 10: PB15 11: PC6 12: PC7 13: PC8 14: PC9 15: PC10 16: PC11 17: PD9 18: PD10 19: PD11 20: PD12 21: PD13 22: PD14 23: PD15 24: PF0 25: PF1 26: PF2 27: PF3 28: PF4 29: PF5 30: PF6 31: PF7 Low Energy Timer LETIM0, output channel 0. LETIM0_OUT1 0: PA1 1: PA2 2: PA3 3: PA4 4: PA5 5: PB11 6: PB12 7: PB13 8: PB14 9: PB15 10: PC6 11: PC7 12: PC8 13: PC9 14: PC10 15: PC11 16: PD9 17: PD10 18: PD11 19: PD12 20: PD13 21: PD14 22: PD15 23: PF0 24: PF1 25: PF2 26: PF3 27: PF4 28: PF5 29: PF6 30: PF7 31: PA0 Low Energy Timer LETIM0, output channel 1. 0: PA1 1: PA2 2: PA3 3: PA4 4: PA5 5: PB11 6: PB12 7: PB13 8: PB14 9: PB15 10: PC6 11: PC7 12: PC8 13: PC9 14: PC10 15: PC11 16: PD9 17: PD10 18: PD11 19: PD12 20: PD13 21: PD14 22: PD15 23: PF0 24: PF1 25: PF2 26: PF3 27: PF4 28: PF5 29: PF6 30: PF7 31: PA0 LEUART0 Receive input. 0: PA0 1: PA1 2: PA2 3: PA3 4: PA4 5: PA5 6: PB11 7: PB12 8: PB13 9: PB14 10: PB15 11: PC6 12: PC7 13: PC8 14: PC9 15: PC10 16: PC11 17: PD9 18: PD10 19: PD11 20: PD12 21: PD13 22: PD14 23: PD15 24: PF0 25: PF1 26: PF2 27: PF3 28: PF4 29: PF5 30: PF6 31: PF7 m en de d om R ec LEU0_RX N ot LEU0_TX fo r I2C0_SCL 0: PA1 1: PA2 2: PA3 3: PA4 0: PB14 LFXTAL_N silabs.com | Building a more connected world. LEUART0 Transmit output. Also used as receive input in half duplex communication. Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin. Rev. 1.5 | 125 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Pin Definitions Alternate LOCATION Functionality 0-3 4-7 8 - 11 12 - 15 16 - 19 20 - 23 24 - 27 28 - 31 0: PB15 Description Low Frequency Crystal (typically 32.768 kHz) positive pin. LFXTAL_P MODEM antenna control output 0, used for antenna diversity. 28: PA0 29: PA1 30: PA2 31: PA3 MODEM antenna control output 1, used for antenna diversity. 28: PF4 29: PF5 30: PF6 31: PF7 MODEM data clock out. 24: PF1 25: PF2 26: PF3 27: PF4 28: PF5 29: PF6 30: PF7 31: PA0 MODEM data in. 20: PD14 21: PD15 22: PF0 23: PF1 24: PF2 25: PF3 26: PF4 27: PF5 28: PF6 29: PF7 30: PA0 31: PA1 MODEM data out. 16: PC11 17: PD9 18: PD10 19: PD11 20: PD12 21: PD13 22: PD14 23: PD15 24: PF0 25: PF1 26: PF2 27: PF3 28: PF4 29: PF5 30: PF6 31: PF7 Pulse Counter PCNT0 input number 0. 16: PD9 17: PD10 18: PD11 19: PD12 20: PD13 21: PD14 22: PD15 23: PF0 24: PF1 25: PF2 26: PF3 27: PF4 28: PF5 29: PF6 30: PF7 31: PA0 Pulse Counter PCNT0 input number 1. 8: PC6 9: PC7 10: PC8 11: PC9 12: PC10 13: PC11 14: PD9 15: PD10 16: PD11 17: PD12 18: PD13 19: PD14 20: PD15 21: PF0 22: PF1 23: PF2 24: PF3 25: PF4 26: PF5 27: PF6 MODEM_ANT1 0: PA4 1: PA5 2: PB11 3: PB12 4: PB13 5: PB14 6: PB15 7: PC6 8: PC7 9: PC8 10: PC9 11: PC10 12: PC11 13: PD9 14: PD10 15: PD11 16: PD12 17: PD13 18: PD14 19: PD15 20: PF0 21: PF1 22: PF2 23: PF3 24: PF4 25: PF5 26: PF6 27: PF7 MODEM_DCLK 0: PA0 1: PA1 2: PA2 3: PA3 4: PA4 5: PA5 6: PB11 7: PB12 8: PB13 9: PB14 10: PB15 11: PC6 12: PC7 13: PC8 14: PC9 15: PC10 16: PC11 17: PD9 18: PD10 19: PD11 20: PD12 21: PD13 22: PD14 23: PD15 24: PF0 25: PF1 26: PF2 27: PF3 MODEM_DIN 0: PA1 1: PA2 2: PA3 3: PA4 4: PA5 5: PB11 6: PB12 7: PB13 8: PB14 9: PB15 10: PC6 11: PC7 12: PC8 13: PC9 14: PC10 15: PC11 16: PD9 17: PD10 18: PD11 19: PD12 20: PD13 21: PD14 22: PD15 23: PF0 MODEM_DOUT 0: PA2 1: PA3 2: PA4 3: PA5 4: PB11 5: PB12 6: PB13 7: PB14 8: PB15 9: PC6 10: PC7 11: PC8 12: PC9 13: PC10 14: PC11 15: PD9 16: PD10 17: PD11 18: PD12 19: PD13 PCNT0_S0IN 0: PA0 1: PA1 2: PA2 3: PA3 4: PA4 5: PA5 6: PB11 7: PB12 8: PB13 9: PB14 10: PB15 11: PC6 12: PC7 13: PC8 14: PC9 15: PC10 PCNT0_S1IN 0: PA1 1: PA2 2: PA3 3: PA4 4: PA5 5: PB11 6: PB12 7: PB13 8: PB14 9: PB15 10: PC6 11: PC7 12: PC8 13: PC9 14: PC10 15: PC11 PRS_CH0 0: PF0 1: PF1 2: PF2 3: PF3 4: PF4 5: PF5 6: PF6 7: PF7 8: PC6 9: PC7 10: PC8 11: PC9 12: PC10 13: PC11 N ew fo r m en de d om D MODEM_ANT0 4: PB12 5: PB13 6: PB14 7: PB15 es ig ns 28: PF7 29: PA0 30: PA1 31: PA2 0: PA3 1: PA4 2: PA5 3: PB11 Peripheral Reflex System PRS, channel 0. 0: PF1 1: PF2 2: PF3 3: PF4 4: PF5 5: PF6 6: PF7 7: PF0 Peripheral Reflex System PRS, channel 1. 0: PF2 1: PF3 2: PF4 3: PF5 4: PF6 5: PF7 6: PF0 7: PF1 Peripheral Reflex System PRS, channel 2. PRS_CH3 0: PF3 1: PF4 2: PF5 3: PF6 4: PF7 5: PF0 6: PF1 7: PF2 PRS_CH4 0: PD9 1: PD10 2: PD11 3: PD12 4: PD13 5: PD14 6: PD15 R ec PRS_CH1 N ot PRS_CH2 silabs.com | Building a more connected world. 8: PD9 9: PD10 10: PD11 11: PD12 12: PD13 13: PD14 14: PD15 Peripheral Reflex System PRS, channel 3. Peripheral Reflex System PRS, channel 4. Rev. 1.5 | 126 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Pin Definitions Alternate LOCATION 8 - 11 PRS_CH5 0: PD10 1: PD11 2: PD12 3: PD13 4: PD14 5: PD15 6: PD9 PRS_CH6 0: PA0 1: PA1 2: PA2 3: PA3 4: PA4 5: PA5 6: PB11 7: PB12 8: PB13 9: PB14 10: PB15 11: PD9 PRS_CH7 0: PA1 1: PA2 2: PA3 3: PA4 4: PA5 5: PB11 6: PB12 7: PB13 8: PB14 9: PB15 10: PA0 PRS_CH8 0: PA2 1: PA3 2: PA4 3: PA5 4: PB11 5: PB12 6: PB13 7: PB14 8: PB15 9: PA0 10: PA1 PRS_CH9 0: PA3 1: PA4 2: PA5 3: PB11 4: PB12 5: PB13 6: PB14 7: PB15 8: PA0 9: PA1 10: PA2 11: PC6 PRS_CH10 0: PC6 1: PC7 2: PC8 3: PC9 4: PC10 5: PC11 PRS_CH11 0: PC7 1: PC8 2: PC9 3: PC10 4: PC11 5: PC6 TIM0_CC0 0: PA0 1: PA1 2: PA2 3: PA3 TIM0_CC1 0: PA1 1: PA2 2: PA3 3: PA4 12 - 15 16 - 19 20 - 23 24 - 27 28 - 31 Description Peripheral Reflex System PRS, channel 5. 12: PD10 13: PD11 14: PD12 15: PD13 16: PD14 17: PD15 es ig ns 4-7 Peripheral Reflex System PRS, channel 6. Peripheral Reflex System PRS, channel 7. D 0-3 16: PC11 m en de d Peripheral Reflex System PRS, channel 8. Peripheral Reflex System PRS, channel 9. Peripheral Reflex System PRS, channel 10. fo r 12: PC7 13: PC8 14: PC9 15: PC10 N ew Functionality Peripheral Reflex System PRS, channel 11. 8: PB13 9: PB14 10: PB15 11: PC6 12: PC7 13: PC8 14: PC9 15: PC10 16: PC11 17: PD9 18: PD10 19: PD11 20: PD12 21: PD13 22: PD14 23: PD15 24: PF0 25: PF1 26: PF2 27: PF3 28: PF4 29: PF5 30: PF6 31: PF7 Timer 0 Capture Compare input / output channel 0. 4: PA5 5: PB11 6: PB12 7: PB13 8: PB14 9: PB15 10: PC6 11: PC7 12: PC8 13: PC9 14: PC10 15: PC11 16: PD9 17: PD10 18: PD11 19: PD12 20: PD13 21: PD14 22: PD15 23: PF0 24: PF1 25: PF2 26: PF3 27: PF4 28: PF5 29: PF6 30: PF7 31: PA0 Timer 0 Capture Compare input / output channel 1. 0: PA2 1: PA3 2: PA4 3: PA5 4: PB11 5: PB12 6: PB13 7: PB14 8: PB15 9: PC6 10: PC7 11: PC8 12: PC9 13: PC10 14: PC11 15: PD9 16: PD10 17: PD11 18: PD12 19: PD13 20: PD14 21: PD15 22: PF0 23: PF1 24: PF2 25: PF3 26: PF4 27: PF5 28: PF6 29: PF7 30: PA0 31: PA1 Timer 0 Capture Compare input / output channel 2. 0: PA3 1: PA4 2: PA5 3: PB11 4: PB12 5: PB13 6: PB14 7: PB15 8: PC6 9: PC7 10: PC8 11: PC9 12: PC10 13: PC11 14: PD9 15: PD10 16: PD11 17: PD12 18: PD13 19: PD14 20: PD15 21: PF0 22: PF1 23: PF2 24: PF3 25: PF4 26: PF5 27: PF6 28: PF7 29: PA0 30: PA1 31: PA2 Timer 0 Complimentary Dead Time Insertion channel 0. TIM0_CDTI1 0: PA4 1: PA5 2: PB11 3: PB12 4: PB13 5: PB14 6: PB15 7: PC6 8: PC7 9: PC8 10: PC9 11: PC10 12: PC11 13: PD9 14: PD10 15: PD11 16: PD12 17: PD13 18: PD14 19: PD15 20: PF0 21: PF1 22: PF2 23: PF3 24: PF4 25: PF5 26: PF6 27: PF7 28: PA0 29: PA1 30: PA2 31: PA3 Timer 0 Complimentary Dead Time Insertion channel 1. TIM0_CDTI2 0: PA5 1: PB11 2: PB12 3: PB13 4: PB14 5: PB15 6: PC6 7: PC7 8: PC8 9: PC9 10: PC10 11: PC11 12: PD9 13: PD10 14: PD11 15: PD12 16: PD13 17: PD14 18: PD15 19: PF0 20: PF1 21: PF2 22: PF3 23: PF4 24: PF5 25: PF6 26: PF7 27: PA0 28: PA1 29: PA2 30: PA3 31: PA4 Timer 0 Complimentary Dead Time Insertion channel 2. R ec TIM0_CC2 om 4: PA4 5: PA5 6: PB11 7: PB12 N ot TIM0_CDTI0 silabs.com | Building a more connected world. Rev. 1.5 | 127 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Pin Definitions Alternate LOCATION 12 - 15 16 - 19 20 - 23 4: PA4 5: PA5 6: PB11 7: PB12 8: PB13 9: PB14 10: PB15 11: PC6 12: PC7 13: PC8 14: PC9 15: PC10 16: PC11 17: PD9 18: PD10 19: PD11 20: PD12 21: PD13 22: PD14 23: PD15 24: PF0 25: PF1 26: PF2 27: PF3 28: PF4 29: PF5 30: PF6 31: PF7 Timer 1 Capture Compare input / output channel 0. TIM1_CC1 0: PA1 1: PA2 2: PA3 3: PA4 4: PA5 5: PB11 6: PB12 7: PB13 8: PB14 9: PB15 10: PC6 11: PC7 12: PC8 13: PC9 14: PC10 15: PC11 16: PD9 17: PD10 18: PD11 19: PD12 20: PD13 21: PD14 22: PD15 23: PF0 24: PF1 25: PF2 26: PF3 27: PF4 28: PF5 29: PF6 30: PF7 31: PA0 Timer 1 Capture Compare input / output channel 1. TIM1_CC2 0: PA2 1: PA3 2: PA4 3: PA5 4: PB11 5: PB12 6: PB13 7: PB14 8: PB15 9: PC6 10: PC7 11: PC8 12: PC9 13: PC10 14: PC11 15: PD9 16: PD10 17: PD11 18: PD12 19: PD13 20: PD14 21: PD15 22: PF0 23: PF1 24: PF2 25: PF3 26: PF4 27: PF5 28: PF6 29: PF7 30: PA0 31: PA1 Timer 1 Capture Compare input / output channel 2. TIM1_CC3 0: PA3 1: PA4 2: PA5 3: PB11 4: PB12 5: PB13 6: PB14 7: PB15 8: PC6 9: PC7 10: PC8 11: PC9 12: PC10 13: PC11 14: PD9 15: PD10 16: PD11 17: PD12 18: PD13 19: PD14 20: PD15 21: PF0 22: PF1 23: PF2 24: PF3 25: PF4 26: PF5 27: PF6 28: PF7 29: PA0 30: PA1 31: PA2 Timer 1 Capture Compare input / output channel 3. US0_CLK 0: PA2 1: PA3 2: PA4 3: PA5 4: PB11 5: PB12 6: PB13 7: PB14 8: PB15 9: PC6 10: PC7 11: PC8 12: PC9 13: PC10 14: PC11 15: PD9 16: PD10 17: PD11 18: PD12 19: PD13 20: PD14 21: PD15 22: PF0 23: PF1 24: PF2 25: PF3 26: PF4 27: PF5 28: PF6 29: PF7 30: PA0 31: PA1 USART0 clock input / output. US0_CS 0: PA3 1: PA4 2: PA5 3: PB11 4: PB12 5: PB13 6: PB14 7: PB15 8: PC6 9: PC7 10: PC8 11: PC9 12: PC10 13: PC11 14: PD9 15: PD10 16: PD11 17: PD12 18: PD13 19: PD14 20: PD15 21: PF0 22: PF1 23: PF2 24: PF3 25: PF4 26: PF5 27: PF6 28: PF7 29: PA0 30: PA1 31: PA2 USART0 chip select input / output. US0_CTS 0: PA4 1: PA5 2: PB11 3: PB12 4: PB13 5: PB14 6: PB15 7: PC6 8: PC7 9: PC8 10: PC9 11: PC10 12: PC11 13: PD9 14: PD10 15: PD11 16: PD12 17: PD13 18: PD14 19: PD15 20: PF0 21: PF1 22: PF2 23: PF3 24: PF4 25: PF5 26: PF6 27: PF7 28: PA0 29: PA1 30: PA2 31: PA3 USART0 Clear To Send hardware flow control input. US0_RTS 0: PA5 1: PB11 2: PB12 3: PB13 4: PB14 5: PB15 6: PC6 7: PC7 8: PC8 9: PC9 10: PC10 11: PC11 12: PD9 13: PD10 14: PD11 15: PD12 16: PD13 17: PD14 18: PD15 19: PF0 20: PF1 21: PF2 22: PF3 23: PF4 24: PF5 25: PF6 26: PF7 27: PA0 28: PA1 29: PA2 30: PA3 31: PA4 USART0 Request To Send hardware flow control output. 4: PA5 5: PB11 6: PB12 7: PB13 8: PB14 9: PB15 10: PC6 11: PC7 12: PC8 13: PC9 14: PC10 15: PC11 16: PD9 17: PD10 18: PD11 19: PD12 20: PD13 21: PD14 22: PD15 23: PF0 24: PF1 25: PF2 26: PF3 27: PF4 28: PF5 29: PF6 30: PF7 31: PA0 USART0 Asynchronous Receive. 4: PA4 5: PA5 6: PB11 7: PB12 8: PB13 9: PB14 10: PB15 11: PC6 12: PC7 13: PC8 14: PC9 15: PC10 16: PC11 17: PD9 18: PD10 19: PD11 20: PD12 21: PD13 22: PD14 23: PD15 24: PF0 25: PF1 26: PF2 27: PF3 28: PF4 29: PF5 30: PF6 31: PF7 USART0 Asynchronous Transmit. Also used as receive input in half duplex communication. om 0: PA1 1: PA2 2: PA3 3: PA4 ec US0_RX R 0: PA0 1: PA1 2: PA2 3: PA3 28 - 31 D TIM1_CC0 0: PA0 1: PA1 2: PA2 3: PA3 24 - 27 N ot US0_TX US1_CLK Description es ig ns 8 - 11 N ew 4-7 fo r 0-3 m en de d Functionality USART0 Synchronous mode Master Input / Slave Output (MISO). USART0 Synchronous mode Master Output / Slave Input (MOSI). 0: PA2 1: PA3 2: PA4 3: PA5 4: PB11 5: PB12 6: PB13 7: PB14 silabs.com | Building a more connected world. 8: PB15 9: PC6 10: PC7 11: PC8 12: PC9 13: PC10 14: PC11 15: PD9 16: PD10 17: PD11 18: PD12 19: PD13 20: PD14 21: PD15 22: PF0 23: PF1 24: PF2 25: PF3 26: PF4 27: PF5 28: PF6 29: PF7 30: PA0 31: PA1 USART1 clock input / output. Rev. 1.5 | 128 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Pin Definitions Alternate LOCATION US1_CS 0: PA3 1: PA4 2: PA5 3: PB11 4: PB12 5: PB13 6: PB14 7: PB15 US1_CTS 0: PA4 1: PA5 2: PB11 3: PB12 US1_RTS US1_RX 12 - 15 16 - 19 20 - 23 8: PC6 9: PC7 10: PC8 11: PC9 12: PC10 13: PC11 14: PD9 15: PD10 16: PD11 17: PD12 18: PD13 19: PD14 20: PD15 21: PF0 22: PF1 23: PF2 24: PF3 25: PF4 26: PF5 27: PF6 28: PF7 29: PA0 30: PA1 31: PA2 USART1 chip select input / output. 4: PB13 5: PB14 6: PB15 7: PC6 8: PC7 9: PC8 10: PC9 11: PC10 12: PC11 13: PD9 14: PD10 15: PD11 16: PD12 17: PD13 18: PD14 19: PD15 20: PF0 21: PF1 22: PF2 23: PF3 24: PF4 25: PF5 26: PF6 27: PF7 28: PA0 29: PA1 30: PA2 31: PA3 USART1 Clear To Send hardware flow control input. 0: PA5 1: PB11 2: PB12 3: PB13 4: PB14 5: PB15 6: PC6 7: PC7 8: PC8 9: PC9 10: PC10 11: PC11 12: PD9 13: PD10 14: PD11 15: PD12 16: PD13 17: PD14 18: PD15 19: PF0 20: PF1 21: PF2 22: PF3 23: PF4 24: PF5 25: PF6 26: PF7 27: PA0 28: PA1 29: PA2 30: PA3 31: PA4 USART1 Request To Send hardware flow control output. 0: PA1 1: PA2 2: PA3 3: PA4 4: PA5 5: PB11 6: PB12 7: PB13 8: PB14 9: PB15 10: PC6 11: PC7 12: PC8 13: PC9 14: PC10 15: PC11 16: PD9 17: PD10 18: PD11 19: PD12 20: PD13 21: PD14 22: PD15 23: PF0 24: PF1 25: PF2 26: PF3 27: PF4 0: PA0 1: PA1 2: PA2 3: PA3 4: PA4 5: PA5 6: PB11 7: PB12 8: PB13 9: PB14 10: PB15 11: PC6 12: PC7 13: PC8 14: PC9 15: PC10 16: PC11 17: PD9 18: PD10 19: PD11 20: PD12 21: PD13 22: PD14 23: PD15 24: PF0 25: PF1 26: PF2 27: PF3 28 - 31 Description 28: PF5 29: PF6 30: PF7 31: PA0 USART1 Asynchronous Receive. 28: PF4 29: PF5 30: PF6 31: PF7 USART1 Asynchronous Transmit. Also used as receive input in half duplex communication. USART1 Synchronous mode Master Input / Slave Output (MISO). USART1 Synchronous mode Master Output / Slave Input (MOSI). N ot R ec om m en de d US1_TX 24 - 27 es ig ns 8 - 11 D 4-7 N ew 0-3 fo r Functionality silabs.com | Building a more connected world. Rev. 1.5 | 129 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Pin Definitions 6.7 Analog Port (APORT) Client Maps N ew DY DX CY CX D PC6 PC7 PC8 PC9 PC10 PC11 es ig ns The Analog Port (APORT) is an infrastructure used to connect chip pins with on-chip analog clients such as analog comparators, ADCs, DACs, etc. The APORT consists of a set of shared buses, switches, and control logic needed to configurably implement the signal routing. Figure 6.5 APORT Connection Diagram on page 130 shows the APORT routing for this device family (note that available features may vary by part number). A complete description of APORT functionality can be found in the Reference Manual. PF0 PF1 PF2 POS PF3 1X 2X 3X 4X 1X 2X 3X 4X ACMP1 NEG PF5 PF6 1Y 2Y 3Y 4Y PF7 1X 2X 3X 4X NEG m en de d AX AY BX BY POS 1Y 2Y 3Y 4Y fo r ACMP0 PF4 POS ADC0 NEG PB15 PB14 PB13 PB12 PB11 PA5 PA4 PA3 PA2 1Y 2Y 3Y 4Y ADC_EXTP PA1 EXTP EXTN ADC_EXTN PA0 PD15 1X 1Y ec om IDAC0 APORTnX, APORTnY AX, BY, … BUSAX, BUSBY, ... PD14 PD13 PD12 PD11 PD10 PD9 N ot R nX, nY Figure 6.5. APORT Connection Diagram Client maps for each analog circuit using the APORT are shown in the following tables. The maps are organized by bus, and show the peripheral's port connection, the shared bus, and the connection from specific bus channel numbers to GPIO pins. In general, enumerations for the pin selection field in an analog peripheral's register can be determined by finding the desired pin connection in the table and then combining the value in the Port column (APORT__), and the channel identifier (CH__). For example, if pin silabs.com | Building a more connected world. Rev. 1.5 | 130 N ot PB14 PB11 PB11 PB13 PB15 PB15 PB13 BUSCY BUSDX silabs.com | Building a more connected world. PD10 PD12 PD14 PA0 PA2 PA4 PD9 PD11 PD13 PD15 PA1 PA3 PA5 PD9 PD11 PD13 PD15 PA1 PA3 PA5 m en de d PB12 om ec R BUSDY PD10 PD12 PD14 PA0 PA2 PA4 fo r PB12 PB14 BUSCX PC6 PC8 PC10 PC7 PC9 PC7 PC9 PC11 PF1 PF3 PF5 PF7 BUSAY PC8 PC10 PF0 PF2 PF4 PF6 BUSAX PC6 es ig ns D PC11 PF1 PF3 PF5 PF7 BUSBX N ew PF0 PF2 PF4 PF6 BUSBY CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15 CH16 CH17 CH18 CH19 CH20 CH21 CH22 CH23 CH24 CH25 CH26 CH27 CH28 CH29 CH30 CH31 Bus APORT4Y APORT4X APORT3Y APORT3X APORT2Y APORT2X APORT1Y APORT1X Port EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Pin Definitions PF7 is available on port APORT2X as CH23, the register field enumeration to connect to PF7 would be APORT2XCH23. The shared bus used by this connection is indicated in the Bus column. Table 6.7. ACMP0 Bus and Pin Mapping Rev. 1.5 | 131 N ot PB12 PB14 PB11 silabs.com | Building a more connected world. PD10 PD12 PD14 PA0 PA2 PA4 PD9 PD11 PD13 PD15 PA1 PA3 PA5 PD9 PD11 PD13 PD15 PA1 PA3 PA5 PF0 PF2 PF4 PF6 BUSBY PD10 PD12 PD14 PA0 PA2 PC6 PC8 PC10 N ew PA4 PB12 PB14 BUSCX fo r PB11 PB13 PB15 PB15 PB13 BUSCY BUSDX m en de d om ec R BUSDY PC7 PC9 PC11 PF1 PF3 PF5 PF7 BUSAY PC8 PC10 PF0 PF2 PF4 PF6 BUSAX PC6 es ig ns PC7 D PC9 PC11 PF1 PF3 PF5 PF7 BUSBX CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15 CH16 CH17 CH18 CH19 CH20 CH21 CH22 CH23 CH24 CH25 CH26 CH27 CH28 CH29 CH30 CH31 Bus APORT4Y APORT4X APORT3Y APORT3X APORT2Y APORT2X APORT1Y APORT1X Port EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Pin Definitions Table 6.8. ACMP1 Bus and Pin Mapping Rev. 1.5 | 132 silabs.com | Building a more connected world. PD9 PD11 PD13 PD15 PA1 PA3 PA5 PB11 PB13 PB15 BUSCY PD10 PD12 PD14 PA0 PA2 PA4 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15 CH16 CH17 CH18 CH19 CH20 CH21 CH22 CH23 CH24 CH25 CH26 CH27 CH28 PB12 PB14 BUSDY PB11 PD10 PD12 PD14 PA0 PA2 PA4 PD9 PD11 PD13 PD15 PA1 PA3 PA5 PD9 PD11 PD13 PD15 PA1 PA3 PA5 PD10 PD12 PD14 PA0 PA2 PC6 PC8 PC10 PF0 PF2 PF4 PF6 BUSBY N ew PA4 PB12 PB14 BUSCX fo r PB11 PB13 PB15 PB15 PB13 BUSCY BUSDX PC7 PC9 PC11 PF1 PF3 PF5 PF7 BUSAY PC8 PC10 PF0 PF2 PF4 PF6 BUSAX PC6 es ig ns PC7 D PC9 PC11 PF1 PF3 PF5 PF7 BUSBX CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15 CH16 CH17 CH18 CH19 CH20 CH21 CH22 CH23 CH24 CH25 CH26 CH27 CH28 CH29 CH30 CH31 Bus APORT4Y APORT4X APORT3Y APORT3X APORT2Y APORT2X APORT1Y APORT1X Port m en de d om CH29 CH30 CH31 Bus ec PB12 PB14 R BUSCX APORT1Y APORT1X Port N ot EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Pin Definitions Table 6.9. ADC0 Bus and Pin Mapping Table 6.10. IDAC0 Bus and Pin Mapping Rev. 1.5 | 133 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet QFN48 Package Specifications 7. QFN48 Package Specifications Figure 7.1. QFN48 Package Drawing N ot R ec om m en de d fo r N ew D es ig ns 7.1 QFN48 Package Dimensions silabs.com | Building a more connected world. Rev. 1.5 | 134 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet QFN48 Package Specifications Table 7.1. QFN48 Package Dimensions Min Typ Max A 0.80 0.85 0.90 A1 0.00 0.02 0.05 0.20 REF b 0.18 0.25 D 6.90 7.00 E 6.90 7.00 D2 4.60 4.70 E2 4.60 4.70 0.50 BSC L 0.30 K 0.20 R 0.09 7.10 7.10 4.80 N ew e 0.30 D A3 es ig ns Dimension aaa 4.80 0.40 0.50 — — — 0.14 0.15 0.10 fo r bbb ccc 0.10 0.05 m en de d ddd eee fff 0.08 0.10 N ot R ec om Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VKKD-4. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. silabs.com | Building a more connected world. Rev. 1.5 | 135 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet QFN48 Package Specifications Figure 7.2. QFN48 PCB Land Pattern Drawing N ot R ec om m en de d fo r N ew D es ig ns 7.2 QFN48 PCB Land Pattern silabs.com | Building a more connected world. Rev. 1.5 | 136 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet QFN48 Package Specifications Table 7.2. QFN48 PCB Land Pattern Dimensions Typ S1 6.01 S 6.01 L1 4.70 W1 4.70 e 0.50 W 0.26 L 0.86 es ig ns Dimension fo r N ew D Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. 3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. 4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. The stencil thickness should be 0.125 mm (5 mils). 6. The ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads. 7. A 4x4 array of 0.75 mm square openings on a 1.00 mm pitch can be used for the center ground pad. 8. A No-Clean, Type-3 solder paste is recommended. 9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. N ot R ec om m en de d Note: Above notes and stencil design are shared as recommendations only. A customer or user may find it necessary to use different parameters and fine tune their SMT process as required for their application and tooling. silabs.com | Building a more connected world. Rev. 1.5 | 137 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet QFN48 Package Specifications D fo r N ew EFR32 PPPPPPPPP YYWWTTTTTT # es ig ns 7.3 QFN48 Package Marking m en de d Figure 7.3. QFN48 Package Marking N ot R ec om The package marking consists of: • PPPPPPPPP – The part number designation. 1. Family Code (B | M | F) 2. G (Gecko) 3. Series (1, 2,...) 4. Performance Grade (P | B | V) 5. Feature Code (1, 2,...) 6. TRX Code (3 = TXRX | 2= RX | 1 = TX) 7. Band (1 = Sub-GHz | 2 = 2.4 GHz | 3 = Dual-band) 8. Flash (J = 1024K | H = 512K | G = 256K | F = 128K | E = 64K | D = 32K) 9. Temperature Grade (G = -40 to 85 | I = -40 to 125) • YY – The last 2 digits of the assembly year. • WW – The 2-digit workweek when the device was assembled. • TTTTTT – A trace or manufacturing code. The first letter is the device revision. • # – Bootloader revision number. silabs.com | Building a more connected world. Rev. 1.5 | 138 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet QFN32 Package Specifications 8. QFN32 Package Specifications Figure 8.1. QFN32 Package Drawing N ot R ec om m en de d fo r N ew D es ig ns 8.1 QFN32 Package Dimensions silabs.com | Building a more connected world. Rev. 1.5 | 139 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet QFN32 Package Specifications Table 8.1. QFN32 Package Dimensions Min Typ Max A 0.80 0.85 0.90 A1 0.00 0.02 0.05 0.20 REF b 0.18 0.25 D/E 4.90 5.00 D2/E2 3.40 3.50 E 0.50 BSC 0.30 0.40 K 0.20 — R 0.09 5.10 3.60 N ew L 0.30 D A3 es ig ns Dimension — aaa 0.50 — 0.14 0.15 bbb 0.10 ccc 0.10 0.05 fo r ddd eee 0.08 0.10 m en de d fff N ot R ec om Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VKKD-4. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. silabs.com | Building a more connected world. Rev. 1.5 | 140 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet QFN32 Package Specifications fo r N ew D es ig ns 8.2 QFN32 PCB Land Pattern N ot R ec om m en de d Figure 8.2. QFN32 PCB Land Pattern Drawing silabs.com | Building a more connected world. Rev. 1.5 | 141 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet QFN32 Package Specifications Table 8.2. QFN32 PCB Land Pattern Dimensions Typ S1 4.01 S 4.01 L1 3.50 W1 3.50 e 0.50 W 0.26 L 0.86 es ig ns Dimension fo r N ew D Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. 3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. 4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. The stencil thickness should be 0.125 mm (5 mils). 6. The ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads. 7. A 3x3 array of 0.85 mm square openings on a 1.00 mm pitch can be used for the center ground pad. 8. A No-Clean, Type-3 solder paste is recommended. 9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. N ot R ec om m en de d Note: Above notes and stencil design are shared as recommendations only. A customer or user may find it necessary to use different parameters and fine tune their SMT process as required for their application and tooling. silabs.com | Building a more connected world. Rev. 1.5 | 142 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet QFN32 Package Specifications D N ew EFR32 PPPPPPPPP YYWWTTTTTT es ig ns 8.3 QFN32 Package Marking Figure 8.3. QFN32 Package Marking N ot R ec om m en de d fo r The package marking consists of: • PPPPPPPPP – The part number designation. 1. Family Code (B | M | F) 2. G (Gecko) 3. Series (1, 2,...) 4. Performance Grade (P | B | V) 5. Feature Code (1, 2,...) 6. TRX Code (3 = TXRX | 2= RX | 1 = TX) 7. Band (1 = Sub-GHz | 2 = 2.4 GHz | 3 = Dual-band) 8. Flash (J = 1024K | H = 512k | G = 256K | F = 128K | E = 64K | D = 32K) 9. Temperature Grade (G = -40 to 85 | I = -40 to 125) • YY – The last 2 digits of the assembly year. • WW – The 2-digit workweek when the device was assembled. • TTTTTT – A trace or manufacturing code. The first letter is the device revision. silabs.com | Building a more connected world. Rev. 1.5 | 143 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Revision History 9. Revision History Revision 1.5 • • • • • • In the front page block diagram, updated the lowest energy mode for LETIMER. Removed Wake on Radio feature from 1. Feature List. Updated 3.6.2 Real Time Counter and Calendar (RTCC) to remove AUXHFRCO as a clock source. Updated 3.6.3 Low Energy Timer (LETIMER) lowest energy mode. Updated 4.1.1 Absolute Maximum Ratings absolute voltage of sub-GHz and 2.4 GHz RF pins.. In 4.1.10.1 Sub-GHz RF Transmitter characteristics for 915 MHz Band: • Corrected FCC reference for non-restricted bands in: • SPURHARM_FCC_20 • SPUROOB_FCC_20 D • SPURHARM_FCC_14 es ig ns June, 2022 • Updated maximum specification for restricted bands (30-88 MHz) in: • SPUROOB_FCC_20 • SPUROOB_FCC_14 N ew • SPUROOB_FCC_14 m en de d fo r • Added timing specifications for RESETn low time and clarified VIL and VIH logic levels for RESETn pins in Table 4.38 General-Purpose I/O (GPIO) on page 74. • Removed BIASPROG = 1, FULLBIAS = 0 specifications from Table 4.41 Analog Comparator (ACMP) on page 79. • Added Figure 4.2 SPI Master Timing Diagram (SMSDELAY = 1) on page 87. • In 5.2 RF Matching Networks, added document references for component values and added document reference to IPD solutions. • Added a note to Table 7.2 QFN48 PCB Land Pattern Dimensions on page 137 and Table 8.2 QFN32 PCB Land Pattern Dimensions on page 142. • Updated feature code in 7.3 QFN48 Package Marking and 8.3 QFN32 Package Marking. • Removed all references to RFSENSE. Revision 1.4 October, 2018 om N ot • • • ec • • 2. Ordering Information - Added OPN for QFN48 sub-GHz devices. 4.1.2.1 General Operating Conditions - Removed voltage scaling footnote from DECOUPLE output capacitor specification. 4.1.5 Current Consumption - Removed “across supply voltage" from header. 4.1.10 Sub-GHz RF Transceiver Characteristics - Replaced "PAVDD" with "External PA Supply". 4.1.10.10 Sub-GHz RF Receiver Characteristics for 315 MHz Band & 4.1.10.6 Sub-GHz RF Receiver Characteristics for 490 MHz Band - Corrected tuning frequency range units from "dBM" to "MHz". 4.1.10.2 Sub-GHz RF Receiver Characteristics for 915 MHz Band - Replaced "GFSK" with "4GFSK" for 400 kbps test condition. 4.1.15 Voltage Monitor (VMON) - Replaced "1 supply monitored" with "1 channel active" and replaced "4 supplies monitored" with "all channels active" in VMON supply current test conditions. Table 4.40 Analog to Digital Converter (ADC) on page 77 - Minor wording and typographical error fixes. Table 4.41 Analog Comparator (ACMP) on page 79 - Minor wording and typographical error fixes. 6.3 QFN48 Sub-GHz Device Pinout - Added GPIO pinout information for QFN48 sub-GHz devices. R • • • • • silabs.com | Building a more connected world. Rev. 1.5 | 144 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Revision History Revision 1.3 April, 2018 • Table 3.1 Configuration Summary on page 17: Corrected USART1 features (removed IrDA). • Table 4.6 Current Consumption 3.3 V using DC-DC Converter on page 27: • Typical values for IEM2 updated to 2.5 and 2.2 uA per errata CUR_E201. • Typical value for IEM3 updated to 2.1 uA per errata CUR_E201. N ot R ec om m en de d fo r N ew D es ig ns • Table 4.15 RF Receiver Characteristics for Bluetooth Low Energy in the 2.4GHz Band, 1 Mbps Data Rate on page 38: typical value for SENS updated to -92.5 dBm per errata RADIO_E206. • Table 4.17 RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band on page 42: Typical values for SENS updated to -99 dBm per errata RADIO_E201. silabs.com | Building a more connected world. Rev. 1.5 | 145 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Revision History Revision 1.2 November, 2017 Applied latest formatting, style, and sequence guidelines. Updated front page with new title and messaging. "Bluetooth Smart" changed to "Bluetooth Low Energy" Added high-temperature (-I grade) part numbers and associated sections / specifications. Parameter Names, Symbol Names, and Test Conditions throughout electrical specification tables updated for consistency across all EFR32xG1x product families. • Electrical specification changes not related to formatting consistency, typographical errors, or the addition of high-temperature part numbers are listed below. • 4.1.1 Absolute Maximum Ratings: • VDDMAX: Min value changed from 0 to -0.3 V. es ig ns • • • • • • Removed PRFMAXSUBG, VMAXDIFFSUBG, and DeltaVDD specifications. • Added footnotes to clarify VDIGPIN specification for 5V tolerant GPIO. N ew • Table 4.2 General Operating Conditions on page 22: • Added CDECOUPLE and fHFCLK specifications. D • Split VMAXSUBG into separate line items for SUBGRF_OP/SUBGRF_ON and SUBGRF_IP/SUBGRF_IN. • VMAXSUBG for SUBGRF_IP/SUBGRF_IN: Min = -0.3 V, Max = +0.3 V. • Added footnote for additional information on peak current during voltage scaling operations. • Table 4.6 Current Consumption 3.3 V using DC-DC Converter on page 27: • IEM1: CCM Mode specifications removed from table. m en de d fo r • Low Power Mode footnote corrected from "LPBIAS=3" to "LPCMPBIAS=0", and "LPCILIMSEL" to "LPCLIMILIMSEL". • 4.1.9.3 RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4GHz Band, 1 Mbps Data Rate: • TXBW: Test Condition at 10 dBm added. • Footnote referring to Bluetooth Core specification updated to "Bluetooth Core_5.0..." from "Bluetooth Core_4.2..." • Table 4.17 RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band on page 42: RSSIMAX value placed in Max column and RSSIMIN value placed in Min column. • Table 4.19 Sub-GHz RF Receiver Characteristics for 915 MHz Band on page 47: 100kbps reference signal footnote corrected to show 400 kHz channel spacing instead of 200 kHz. • Table 4.34 HFRCO on page 71 and Table 4.35 AUXHFRCO on page 72 tables separated (specifications are identical for this product). • Table 4.37 Flash Memory Characteristics1 on page 73: om • Added single-word programming time and clarified existing specification as per-word timing for a 128-word burst write. • Added footnotes to clarify mass, device, and page erase timing conditions. • Table 4.39 Voltage Monitor (VMON) on page 76: IVMON specifications for EM2/3/4 separated into above threshold and below threshold conditions. • Table 4.40 Analog to Digital Converter (ADC) on page 77 • VADCIN specification changed to reference VFS instead of VREF. N ot R ec • Input referred ADC noise specification removed. • Footnotes added to clarify internal and external reference configurations. • Table 4.41 Analog Comparator (ACMP) on page 79: Text explaining total ACMP current calculation brought into table as a footnote. • 4.1.21 USART SPI: • SPI Master Timing: Updated with relaxed values. • SPI Slave Timing: Corrected tSCLK Min value to "6 * tHFPERCLK" from "2 * tHFPERCLK". • • • • • • • Updated remainder of specifications to match formatting and common specs in all EFR32xG1x product families. Added PCNT electrical specifications table: Table 4.43 Pulse Counter (PCNT) on page 83. 4.2 Typical Performance Curves: Added data for >85C operation. 5.2 RF Matching Networks: Removed redundant paragraph in introduction. Added section 5.3 Other Connections. Condensed pinout tables and moved detailed GPIO functionality information to . Added Figure 6.5 APORT Connection Diagram on page 130. silabs.com | Building a more connected world. Rev. 1.5 | 146 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Revision History • Corrected flash designator description in Package Marking sections. Revision 1.1 2016-Oct-26 D es ig ns • Ordering Information: Removed Encryption column. All products in family include full encryption capabilites. Previously EFR32MG1V devices listed as "AES only". • System Overview Sections: Minor wording and typographical error fixes. • Electrical Characteristics: Minor wording and typographical error fixes. • "Sub-GHz Receiver Characteristics for 433 MHz Band" table in Electrical Characteristics: Corrected Sensitivity spec error where data for 50 kbps and 2.4 kbps were swapped. • "HFRCO and AUXHFRCO" table in Electrical Characteristics: f_HFRCO symbol changed to f_HFRCO_ACC. • Pinout tables: APORT channel details removed from "Analog" column. This information is now found in the APORT client map sections. • Updated APORT client map sections. Revision 1.0 N ew 2016-Jul-22 R ec om m en de d fo r • Electrical Characteristics: Minimum and maximum value statement changed to cover full operating temperature range. • Finalized Specification Tables. Tables with condition/min/typ/max or footnote changes include: • Absolute Maximum Ratings • General Operating Conditions • DC-DC Converter • Current Consumption Using Radio 3.3V with DC-DC • RF Transmitter General Characteristics for 2.4 GHz Band • RF Receiver General Characteristics for 2.4 GHz Band • RF Receiver Characteristics for Bluetooth Smart in the 2.4 GHz Band • RF Transmitter Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band • RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band • Sub-GHz RF Transmitter characteristics for 868 MHz Band • Sub-GHz RF Transmitter characteristics for 490 MHz Band • Sub-GHz RF Receiver characteristics for 490 MHz Band • Sub-GHz RF Receiver characteristics for 433 MHz Band • HFRCO and AUXHFRCO • ADC • IDAC • Updated Typical Performance Graphs. • Added external ground note to 2G4RF_ION pin descriptions. • Added note for 5V tolerance to pinout GPIO Overview sections. • Updated OPN decoder with latest revision. • Updated Package Marking text with latest descriptions. Revision 0.97 N ot 2016-06-06 • Added dual-band and sub-GHz OPNs. Revision 0.951 2016-06-03 • Electrical specification tables updated with additional characterization data. silabs.com | Building a more connected world. Rev. 1.5 | 147 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Revision History Revision 0.95 2016-04-11 es ig ns • All OPNs changed to rev C0. Note the following: • All OPNs ending in -B0 are Engineering Samples based on an older revision of silicon and are being removed from the OPN table. These older revisions should be used for evaluation only and will not be supported for production. • OPNs ending in -C0 are the Current Revision of Silicon and are intended for production. • Electrical specification tables updated with latest characterization data and production test limits. Revision 0.9 2016-01-12 D • Updated electrical specifications with latest characterization data. • Added thermal characteristics table. • Updated OPN decoder figure to include extended family options. 2015-12-01 • Engineering samples note added to ordering information table. • Updated electrcal specifications with latest available data. fo r Revision 0.75 2015-11-3 m en de d Consolidated individual device datasheets into single-family document. Re-formatted ordering information table and OPN decoder. Updated block diagrams for front page and system overview. Removed extraneous sections from DC-DC and wake-on-radio from system overview. Updated table formatting for electrical specifications to tech pubs standards. Updated electrcal specifications with latest available data. Added I2C and USART SPI timing tables. Moved DC-DC graph to typical performance curves. Updated APORT tables and APORT references to correct nomenclature. N ot R ec om • • • • • • • • • N ew Revision 0.8 silabs.com | Building a more connected world. Rev. 1.5 | 148 EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet Revision History Revision 0.7 2015-08-31 N ot R ec om m en de d fo r N ew D es ig ns Outcome of comprehensive review cycle of EFR32BG Datasheets. Major changes span the following sections • Section 2: Ordering Information • Section 3.3.4: Receiver Architecture • Section 3.3.5: Transmitter Architecture • Section 4: Electrical Characteristics • Section 4.3.1: General Operating Conditions • Section 4.4: DC-DC Converter • Section 4.5: Current Consumption • Section 4.9.1: RF Transmitter Characteristics for 2.4 GHz Band • Section 4.9.2: RF Receiver General Characteristics for 2.4 GHz Band • Section 4.9.3: RF Transmitter Characteristics for Bluetooth Smart in 2.4 GHz Band • Section 4.9.4: RF Receiver Characteristics for Bluetooth Smart in 2.4 GHz Band • Section 4.11.1: LFXO • Section 4.11.2: HFXO • Section 4.12: GPIO • Section 4.13: VMON • Section 4.14: ADC • Section 4.15: IDAC • Section 4.16: Analog Comparator • Section 5: Application Circuits • Section 6.5: QFNxx Package • Section 6.7: QFNxx Package Marking silabs.com | Building a more connected world. Rev. 1.5 | 149 es ig ns Simplicity Studio IoT Portfolio www.silabs.com/IoT m en de d fo r N ew D One-click access to MCU and wireless tools, documentation, software, source code libraries & more. Available for Windows, Mac and Linux! SW/HW www.silabs.com/simplicity Quality www.silabs.com/quality Support & Community www.silabs.com/community N ot R ec om Disclaimer Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and “Typical” parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. 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