EM359x
High-Performance, Integrated ZigBee/802.15.4 System-on-Chip Family
Exceptional RF Performance
- Normal mode link budget up to 103 dB; configurable up
Complete System-on-Chip
- 32-bit ARM® Cortex -M3 processor
- 2.4 GHz IEEE 802.15.4-2003 transceiver & lower MAC
- 256 or 512 kB flash, with optional read protection
- 32 or 64 kB RAM memory
- AES128 encryption accelerator
- Flexible ADC, UART/SPI/TWI serial communications,
to 110 dB
–102 dBm (1% PER, 20 byte packet)
- +3 dB normal mode output power; configurable up to
+8 dBm
and general purpose timers
- Optional USB serial communications
- 32 highly configurable GPIOs with Schmitt trigger inputs
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1.0 A without/1.25 A with sleep timer
RF_TX_ALT_P,N
PA
DAC
SYNTH
LNA
IF
ADC
HF crystal
OSC
Internal HF
RC-OSC
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OSCB
VDD_CORE
1.25V
Regulator
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nRESET
1.8V
Regulator
Rev 1.0 9/14
General
Purpose
ADC
POR
LF crystal
OSC
Calibration
ADC
USB
Device
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VREG_OUT
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crystal
- Support for external power amplifier
- 8x8 mm 56-pin QFN package
MAC
+
Baseband
Data
RAM
32/64 kB
Program Flash
256/512 kB
2nd level
Interrupt
controller
ARM® CortexTM-M3
CPU with NVIC
and MPU
Packet Trace
Bias
OSCA
1.25 V regulators
- Optional 32.768 kHz crystal for higher timer accuracy
- Low external component count with single 24 MHz
TX_ACTIVE
PA
RF_P,N
Application Flexibility
- Single voltage operation: 2.1–3.6 V with internal 1.8 and
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PA select
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point; Data Watchpoint & Trace; Instrumentation Trace
Macrocell
- Low-frequency internal RC oscillator for low-power sleep
processor start-up from sleep
Innovative network and processor debug
- Packet Trace Port for non-intrusive packet trace with
- Serial Wire/JTAG interface
- Standard ARM debug capabilities: Flash Patch & Break-
Low power consumption, advanced management
- RX Current (w/ CPU): 27 mA
- TX Current (w/ CPU, +3 dBm TX): 31 mA
- Low deep sleep current, with retained RAM and GPIO:
timing
- Robust Wi-Fi and Bluetooth coexistence
Ember development tools
Industry-leading ARM® Cortex -M3 processor
- Leading 32-bit processing performance
- Highly efficient Thumb-2 instruction set
- Operation at 6, 12, or 24 MHz
- Flexible Nested Vectored Interrupt Controller
- High-frequency internal RC oscillator for fast (110 µs)
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- –100 dBm normal RX sensitivity; configurable to
Internal LF
RC-OSC
General
purpose
timers
GPIO
registers
UART/SPI/
TWI
CPU debug TPIU/
ITM/FPB/DWT/
ETM
Always
Powered
Domain
Watchdog
Chip
manager
Encryption
acclerator
SWCLK, JTCK
Serial Wire
and JTAG
debug
Sleep
timer
GPIO multiplexor switch
PA[7:0], PB[7:0], PC[7:0], PD[4:1], PE[3:0]
Copyright © 2014 by Silicon Laboratories
EM359x
EM359x
General Description
The Ember EM359x is a fully integrated System-on-Chip that integrates a 2.4 GHz, IEEE 802.15.4-2003-compliant
transceiver, 32-bit ARM® CortexTM-M3 microprocessor, flash and RAM memory, and peripherals of use to
designers of ZigBee-based systems.
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The transceiver uses an efficient architecture that exceeds the dynamic range requirements imposed by the IEEE
802.15.4-2003 standard by over 15 dB. The integrated receive channel filtering allows for robust co-existence with
other communication standards in the 2.4 GHz spectrum, such as IEEE 802.11-2007 and Bluetooth. The integrated
regulator, VCO, loop filter, and power amplifier keep the external component count low. An optional high
performance radio mode (boost mode) is software-selectable to boost dynamic range.
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The integrated 32-bit ARM® CortexTM-M3 microprocessor is highly optimized for high performance, low power
consumption, and efficient memory utilization. Including an integrated MPU, it supports two different modes of
operation—privileged mode and user mode. This architecture could allow for separation of the networking stack
from the application code, and prevents unwanted modification of restricted areas of memory and registers
resulting in increased stability and reliability of deployed solutions.
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The EM359x has either 256 or 512 kB of embedded flash memory and either 32 or 64 kB of integrated RAM for
data and program storage. The Ember software for the EM359x employs an effective wear-leveling algorithm that
optimizes the lifetime of the embedded flash.
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To maintain the strict timing requirements imposed by the ZigBee and IEEE 802.15.4-2003 standards, the EM359x
integrates a number of MAC functions, AES128 encryption accelerator, and automatic CRC handling into the
hardware. The MAC hardware handles automatic ACK transmission and reception, automatic backoff delay, and
clear channel assessment for transmission, as well as automatic filtering of received packets. The Ember Packet
Trace Interface is also integrated with the MAC, allowing complete, non-intrusive capture of all packets to and from
the EM359x with Ember development tools.
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The EM359x offers a number of advanced power management features that enable long battery life. A highfrequency internal RC oscillator allows the processor core to begin code execution quickly upon waking. Various
deep sleep modes are available with less than 2 µA power consumption while retaining RAM contents. To support
user-defined applications, on-chip peripherals include optional USB, UART, SPI, TWI, ADC, and general-purpose
timers, as well as up to 32 GPIOs. Additionally, an integrated voltage regulator, power-on-reset circuit, and sleep
timer are available.
Finally, the EM359x utilizes standard Serial Wire and JTAG interfaces for powerful software debugging and
programming of the ARM CortexTM-M3 core. The EM359x integrates the standard ARM® system debug
components: Flash Patch and Breakpoint (FPB), Data Watchpoint and Trace (DWT), and Instrumentation Trace
Macrocell (ITM) as well as the advanced Embedded Trace Macrocell (ETM).
Target applications for the EM359x include:
Energy
automation and control
Home automation and control
Security and monitoring
General ZigBee wireless sensor networking
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Building
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Smart
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This technical data sheet details the EM359x features available to customers using it with Ember software.
2
Rev 1.0
EM359x
Ta b l e o f C o n t e n ts
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1. Related Documents and Conventions ...............................................................................5
1.1. Related Documents........................................................................................................5
1.1.1. Ember EM359x Reference Manual........................................................................5
1.1.2. ZigBee Specification ..............................................................................................5
1.1.3. ZigBee PRO Stack Profile .....................................................................................5
1.1.4. ZigBee Stack Profile ..............................................................................................5
1.1.5. Bluetooth Core Specification .................................................................................5
1.1.6. IEEE 802.15.4-2003 ..............................................................................................5
1.1.7. IEEE 802.11g.........................................................................................................5
1.1.8. USB 2.0 Specification ............................................................................................5
1.1.9. ARM® Cortex™-M3 Reference Manual ................................................................5
1.2. Conventions ...................................................................................................................6
2. Typical Connection Diagrams ............................................................................................9
3. Electrical Specifications.................................................................................................... 13
3.1. Absolute Maximum Ratings..........................................................................................13
3.2. Recommended Operating Conditions .......................................................................... 13
3.3. Environmental Characteristics...................................................................................... 14
3.4. DC Electrical Characteristics........................................................................................ 14
3.5. Digital I/O Specifications .............................................................................................. 19
3.6. Non-RF System Electrical Characteristics ................................................................... 20
3.7. RF Electrical Characteristics ........................................................................................ 21
3.7.1. Receive................................................................................................................ 21
3.7.2. Transmit...............................................................................................................24
3.7.3. Synthesizer .......................................................................................................... 26
4. EM359x System Overview.................................................................................................27
4.1. Microprocessor and Memory........................................................................................ 28
4.1.1. ARM® Cortex™-M3 Microprocessor ................................................................... 28
4.1.2. Embedded Memory ............................................................................................. 29
4.2. Interrupt System ........................................................................................................... 29
4.2.1. Nested Vectored Interrupt Controller (NVIC) .......................................................29
4.2.2. Event Manager .................................................................................................... 29
4.2.3.
Memory Protection Unit ............................................................................29
4.3. Radio Module ...............................................................................................................29
4.3.1. Receive (Rx) Path................................................................................................ 29
4.3.2. Transmit (Tx) Path ............................................................................................... 30
4.3.3. Integrated MAC Module....................................................................................... 30
4.3.4. Packet Trace Interface (PTI)................................................................................ 30
4.3.5. Random Number Generator ................................................................................ 30
4.4. System Modules........................................................................................................... 30
4.4.1. Power domains .................................................................................................... 30
4.4.2. Resets.................................................................................................................. 31
4.4.3. Clocks .................................................................................................................. 31
4.4.4. System Timers..................................................................................................... 31
4.4.5. Power Management............................................................................................. 31
Rev 1.0
3
EM359x
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4.5. Integrated Voltage Regulator ....................................................................................... 32
4.6. Peripherals ................................................................................................................... 32
4.6.1. GPIO .................................................................................................................. 32
4.6.2. Serial Controllers .................................................................................................32
4.6.3. USB .................................................................................................................. 33
4.6.4. General Purpose Timers...................................................................................... 33
4.6.5. Analog-to-Digital Converter (ADC) ...................................................................... 34
4.7. Debugging .................................................................................................................... 34
4.7.1. Trace Port Interface Unit (TPIU) .......................................................................... 34
4.7.2. Instrumentation Trace Macrocell (ITM)................................................................ 34
4.7.3. Embedded Trace Macrocell (ETM)...................................................................... 34
4.7.4.
Data Watchpoint and Trace (DWT)........................................................... 34
4.7.5. Flash Patch and Breakpoint (FPB) ...................................................................... 35
4.7.6. Serial Wire and JTAG (SWJ) Interface ................................................................ 35
5. Ordering Information ......................................................................................................... 36
6. Pin Assignments................................................................................................................37
6.1. Packaging..................................................................................................................... 53
6.2. Part Marking ................................................................................................................. 57
Document Change List ........................................................................................................... 58
Contact Information ................................................................................................................ 59
4
Rev 1.0
EM359x
1. Related Documents and Conventions
1.1. Related Documents
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This data sheet accompanies several documents to provide the complete description of the Ember EM359x
devices.
1.1.1. Ember EM359x Reference Manual
The Silicon Laboratories Ember EM359x Reference Manual provides the detailed description for each peripheral
on the EM359x devices.
1.1.2. ZigBee Specification
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The core ZigBee specification (Document 053474) defines ZigBee's smart, cost-effective and energy-efficient
mesh network. It can be downloaded from the ZigBee website (www.zigbee.org). ZigBee Alliance membership is
required.
1.1.3. ZigBee PRO Stack Profile
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The ZigBee PRO Stack Profile specification (Document 074855) is optimized for low power consumption and to
support large networks with thousands of devices. It can be downloaded from the ZigBee website (111.zigbee.org).
ZigBee Alliance membership is required.
1.1.4. ZigBee Stack Profile
1.1.5. Bluetooth Core Specification
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The ZigBee Stack Profile specification (Document 064321) is designed to support smaller networks with hundreds
of devices in a single network. It can be downloaded from the ZigBee website (111.zigbee.org). ZigBee Alliance
membership is required.
The Bluetooth specification is the global short-range wireless standard enabling connectivity for a broad range of
electronic devices. Version 2.1 + EDR (Enhanced Data Rate) can be found here:
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http://www.bluetooth.org/docman/handlers/downloaddoc.ashx?doc_id=241363
1.1.6. IEEE 802.15.4-2003
This standard defines the protocol and compatible interconnection for data communication devices using low data
rate, low power and low complexity, short-range radio frequency (RF) transmissions in a wireless personal area
network (WPAN). It can be found here:
IEEE 802.15.4-2003 (http://standards.ieee.org/getieee802/download/802.15.4-2003.pdf)
1.1.7. IEEE 802.11g
This version provides changes and additions to support the further higher data rate extension for operation in the
2.4 GHz band. It can be found here:
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http://standards.ieee.org/getieee802/download/802.11g-2003.pdf
1.1.8. USB 2.0 Specification
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The Universal Serial Bus Revision 2.0 specification provides the technical details to understand USB requirements
and design USB compatible products. The main specification (usb_20.pdf) is part of the zipfile found here:
http://www.usb.org/developers/docs/usb_20_101111.zip
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1.1.9. ARM® Cortex™-M3 Reference Manual
ARM-specific features like the Nested Vector Interrupt Controller are described in the ARM® Cortex™-M3
reference documentation. The online reference manual can be found here:
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Rev 1.0
5
EM359x
1.2. Conventions
Abbreviations and acronyms used in this data sheet are explained in Table 1.1
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Table 1.1. Acronyms and Abbreviations
Meaning
ACK
Acknowledgement
ADC
Analog to Digital Converter
AES
Advanced Encryption Standard
AGC
Automatic Gain Control
AHB
Advanced High Speed Bus
APB
Advanced Peripheral Bus
CBC-MAC
Cipher Block Chaining—Message Authentication Code
CCA
Clear Channel Assessment
CCM
Counter with CBC-MAC Mode for AES encryption
CCM*
Improved Counter with CBC-MAC Mode for AES encryption
CIB
Customer Information Block
CLK1K
1 kHz Clock
CLK32K
32.768 kHz Crystal Clock
Central Processing Unit
CRC
Cyclic Redundancy Check
CSMA-CA
Carrier Sense Multiple Access-Collision Avoidance
CTR
Counter Mode
CTS
Clear to Send
Differential Non-Linearity
DMA
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DNL
Direct Memory Access
DWT
Data Watchpoint and Trace
Electrically Erasable Programmable Read Only Memory
Event Manager
ENOB
effective number of bits
ESD
Electro Static Discharge
ESR
Equivalent Series Resistance
ETR
External Trigger Input
FCLK
ARM® CortexTM-M3 CPU Clock
FIB
Fixed Information Block
FIFO
First-in, First-out
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CPU
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Acronym/Abbreviation
Rev 1.0
EM359x
FPB
Flash Patch and Breakpoint
GPIO
General Purpose I/O (pins)
HF
High Frequency
2
Inter-Integrated Circuit
IDE
Integrated Development Environment
IF
Intermediate Frequency
IEEE
Institute of Electrical and Electronics Engineers
INL
Integral Non-linearity
ITM
Instrumentation Trace Macrocell
JTAG
Joint Test Action Group
LF
Low Frequency
LNA
Low Noise Amplifier
LQI
Link Quality Indicator
LSB
Least significant bit
MAC
Medium Access Control
MFB
Main Flash Block
Metal Oxide Semiconductor (P-channel or N-channel)
MOSI
Master out, slave in
MPU
Memory Protection Unit
MSB
Most significant bit
Moisture Sensitivity Level
NACK
National Institute of Standards and Technology
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Negative Acknowledge
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MSL
OPM
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Master in, slave out
MOS
NVIC
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MISO
NMI
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Table 1.1. Acronyms and Abbreviations
Non-Maskable Interrupt
Nested Vectored Interrupt Controller
One-Pulse Mode
Offset-Quadrature Phase Shift Keying
OSC24M
High Frequency Crystal Oscillator
OSC32K
Low-Frequency 32.768 kHz Oscillator
OSCHF
High-Frequency Internal RC Oscillator
OSCRC
Low-Frequency RC Oscillator
PA
Power Amplifier
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Rev 1.0
7
EM359x
Table 1.1. Acronyms and Abbreviations
Peripheral clock
PER
Packet Error Rate
PHY
Physical Layer
PLL
Phase-Locked Loop
POR
Power-On-Reset
PRNG
Pseudo Random Number Generator
PSD
Power Spectral Density
PTI
Packet Trace Interface
PWM
Pulse Width Modulation
QFN
Quad Flat Pack
RAM
Random Access Memory
RC
Resistive/Capacitive
RF
Radio Frequency
RMS
Root Mean Square
RoHS
Restriction of Hazardous Substances
RSSI
Receive Signal Strength Indicator
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RTS
Request to Send
Rx
Receive
SYSCLK
System clock
SDFR
Spurious Free Dynamic Range
SFD
Start Frame Delimiter
SINAD
Signal-to-noise and distortion ratio
Serial Peripheral Interface
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SPI
Serial Wire and JTAG Interface
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SWJ
THD
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PCLK
Total Harmonic Distortion
True random number generator
TWI
Two Wire serial interface
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TRNG
Transmit
UART
Universal Asynchronous Receiver/Transmitter
UEV
Update event
USB
Universal Serial Bus
VCO
Voltage Controlled Oscillator
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Rev 1.0
EM359x
2. Typical Connection Diagrams
Figure 2.1 illustrates the typical application circuit.
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Note: The circuit shown in Figure 2.1 is for example purposes only. For a complete reference design, please download one of
the latest Ember Hardware Reference Designs from the Silicon Labs website (www.silabs.com/zigbee-support).
The Balun provides an impedance transformation from the antenna to the EM359x for both TX and RX modes.
L4, along with the PCB trace parasitics and the ceramic balun impedence, provide the optimal RF path for
maximum transmit power and receive sensitivity for the EM359x system.
The harmonic filter (L5, L6, C7, C8 and C9) provides additional suppression of the second harmonic, which
increases the margin over the FCC limit.
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The 24 MHz crystal, Y2, with loading capacitors is required and provides the high-frequency crystal oscillator
source for the EM359x’s main system clock. The optional 32.768 kHz crystal, Y1, with loading capacitors
generates a highly accurate low-frequency crystal oscillator for use with peripherals, but it is not mandatory as the
low-frequency internal RC oscillator can be used.
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Loading capacitance and ESR (C3 and R3) provides proper loading for the internal 1.8 V regulator.
Loading capacitance C4 provides proper loading for the internal 1.25 V regulator, no ESR is required because it is
contained within the chip.
Resistor R7 reduces the operating voltage of the flash memory. This reduces current consumption and improves
sensitivity by 1 dB when compared to not using it.
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An antenna impedance matched to 50 is required.
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Various decoupling capacitors are required, these should be placed as close to their corresponding pins as
possible. For values and locations see one of the Silicon Labs reference designs.
Rev 1.0
9
EM359x
Programming/Debug Interface (Optionally Route to Test Points)
Optional USB (Shown as Bus-Powered Configuration)
VBRD
U1
VBUS
3
VBRD
J2
PB4
PB2
R9
nCS
2
SO/SIO1
3
3
4
3
SI/SIO0
5
6
PB3
PC4
7
5
PB1
PA4
9
1
2
3
4
5
6
7
8
9
2
PC2
4
PC3
R1
JCLK
FB1
10
R1/R2 installed for self-powered
configuration only (VBUS sense)
PA5
J1
C14
VCC
DD+
NC
GND
R6
1
2
3
4
5
R5
D2
TVS
7
6
D1
TVS
C3
Y1
14
PC6
13
nRESET
12
PC5
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C5
L1
AT1
10
9
8
7
L3
Ceramic Balun
5
Harmonic Filter
4
UNBAL
NC
6
DC
GND
BAL-2 BAL-1
L4
5
GND
1
4
2
C11
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1
C10
OSCB
Figure 2.1. Typical Application Circuit
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OSCA
10
L6
1
2
3
L5
3
R7
C15
L2
6
57
OSCB
OSCA
56
VCC_PRE
VDD_SYNTH
55
54
VDD_CORE_1
53
PB5
52
PB5
PB6
51
PB6
PC7
Antenna Interface
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50
43
PB0
PE3
VDD_24MHz
PC4
2
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PC7
15
PC7
17
16
VREG_OUT
VDD_CORE_0
VDD_PADS_0
PA7
18
PD1
19
PA7
PD2
20
PD1
PD3
21
PD2
PB3
22
PD3
PB4
23
PB3
PA0
24
PB4
PA1
25
PA0
26
PC3
PE3
42
RF_N
VDD_VCO
PE2
41
PC4
PC2
49
PC3
VDD_RF
RF_P
PE2
40
JTCK
PB7
PC2
EM359x
PB2
48
39
RF_TX_ALT_P
PB1
PB7
38
JCLK
PA6
PC0
PB2
RF_TX_ALT_N
47
37
VDD_IF
VDD_PADS_2
PC0
36
PB1
PE1
PB0
PA6
NC
VDD_MEM
35
VDD_PADSA
PE0
PC1
34
PD4
46
PE1
PC5
45
33
PA5
PC1
32
PE0
PA1
28
PD4
PC6
NRESET
VDD_PADS_3
31
1
C6
U2
EM359x
PA4
44
PA5
VDD_PADS_1
PA2
27
PA2
PC6
PA3
PA2
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Optional 32kHz
R3
VBRD
30
C13
ESD Protection Diodes
C4
29
PA1
D3
TVS
R4
1V8
PA4
PA0
C12
1V25_CORE
PA3
C2
PA3
R2
8 NRESET
10
1
GND
C1
6
2
OUT
Q1
1
R11
SCLK
GND
PC0
7
nHOLD
nWP
R8
8
VCC
2
PB7
1
9
8
1
U3
R10
VBRD
IN
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Optional Serial Flash
Rev 1.0
BLN1
C7
C8
C9
EM359x
Description
Manufacturer
1
1
ANT1
ANTENNA,
2
1
BLN1
BALUN, CHIP MULTILAYER CERAMIC, 2.4
GHZ. 50/100 OHM, -40C TO 85C, 0805
Wurth 748421245
Johanson 2450BL15B100E
Murata LDB212G4010C-001
TDK HHM1520
3
1
C1
CAPACITOR,
4
1
C2
CAPACITOR,
5
1
C3
CAPACITOR, 2.2 µF, 10 V, X5R, 10%, 0603
6
2
C4, C14
CAPACITOR, 1 µF, 6.3 V, X5R, 10%, 0402
7
3
C5, C12, C13
CAPACITOR, 33 pF, ±5%, 50 V, NPO, 0402
8
3
C6, C10, C11
CAPACITOR, 22 pF, ±5%, 50 V, NPO, 0402
9
2
C7, C9
CAPACITOR, 1 pF, ±0.25 pF, 50 V, 0402, NPO
10
1
C8
CAPACITOR, 1.8pF, ±0.25 pF, 50 V, 0402, NPO
11
1
C15
CAPACITOR, 0.47µF, ±10%, 6.3 V, X5R, 0402
Murata
GRM155R60J474KE19D
12
3
D1, D2, D3
DIODE, TVS, 45 W, 5 V, SOD-882
Vishay
VBUS051BD-HD1-GS08
13
1
FB1
FERRITE BEAD, 60 OHM, 500MA, 0603
Murata BLM18PG600SN1
14
1
J1
CONNECTOR, USB, MICRO B, SMD
FCI 10118192-0001LF
15
1
J2
CONNECTOR, HEADER, SHROUDED, 10
POSITION, DUAL ROW, VERTICAL, 0.050"
Samtec FTSH-105-01-L-DV-K
16
4
L1, L2, L3, L4
INDUCTOR,
17
2
L5, L6
INDUCTOR, 2.7 nH, ±0.3 nH, 0402, MULTILAYER
Murata LQG15HS2N7
18
1
R1
RESISTOR, 100K OHM, 5%, 1/10W, 0402
19
1
R2
RESISTOR, 150K OHM, 5%, 1/16W, 0402
1
R3
RESISTOR, 1 OHM, 5%, 1/16W, 0402
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Item Qty Reference
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Table 2.1. Bill of Materials for Figure 2.1
21
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R4
RESISTOR, 1.5K OHM, 1%, 1/16W, 0402
22
2
R5, R6
RESISTOR, 33 OHM, 1%, 1/10W, 0402
23
1
R7
RESISTOR, 10 OHM, 5%, 1/16W, 0402
24
4
R8, R9, R10, R11
RESISTOR, 100K OHM, 5%, 1/16W, 0402
25
1
Q1
MOSFET, 2N7002, 300MA, 830MW, 60V, TO236-3, SC-59, SOT-23-3
NXP Semiconductor 2N7002
26
1
U1
IC, VOLTAGE REGULATOR,
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Rev 1.0
11
EM359x
Table 2.1. Bill of Materials for Figure 2.1
1
U2
EM3591-RTR/EM3592-RTR/
EM359x, ZIGBEE/802.15.4 RF
TRANSCEIVER, ARM CORTEX-M3, 32 or 64 kB EM3595-RTR/EM3596-RTR/
RAM, 256 or 512 kB FLASH, 56-QFN
EM3597-RTR/EM3598-RTR
28
1
U3
WinBond W25Q80BVSNIG
IC - PROGRAMMABLE MEMORY - BLANK,
SERIAL FLASH, 8M (256K X 32), 2.7 V - 3.6 V, 40 to 85 ºC, 8-SOIC (0.154", 3.90MM WIDTH)
29
1
Y1
CRYSTAL, 32.768 kHz, ±20 ppm INITIAL TOLERANCE AT +25ºC, 12.5 pF
Abracon ABS07-32.768KHZ-T
30
1
Y2
OSCILLATOR, CRYSTAL, 24.000 MHz, 18 pF
LOAD, ±10 PPM TOLERANCE, ±25 PPM STABILITY, -40 TO 85 ºC, AT49
Abracon ABLS-24.000MHZD1X-T
ILSI HC49USM-24.000000M2435
AEL X24M000000S067
N
ot
R
ec
om
m
en
de
d
fo
r
N
ew
D
es
ig
ns
27
12
Rev 1.0
EM359x
3. Electrical Specifications
3.1. Absolute Maximum Ratings
Table 3.1. Absolute Maximum Ratings
Parameter
Test Condition
Min
–0.3
Analog, Memory and Core voltage (VDD_24MHZ,
VDD_VCO, VDD_RF, VDD_IF, VDD_PADSA,
VDD_MEM, VDD_PRE, VDD_SYNTH, VDD_CORE)
–0.3
Voltage on RF_P,N; RF_TX_ALT_P,N
RX signal into a
loss-less balun
Voltage on any GPIO (PA[7:0], PB[7:0], PC[7:0],
PD[4:1], PE[3:0]), SWCLK, nRESET, VREG_OUT
fo
r
Voltage on any GPIO pin (PA4, PA5, PB5, PB6, PB7,
PC1), when used as an input to the general purpose
ADC
m
en
de
d
Storage temperature
Unit
+3.6
V
+2.0
V
–0.3
+3.6
V
—
+15
dBm
–0.3
VDD_PADS
+0.3
V
–0.3
2.0
V
–0.3
VDD_PADSA
+0.3
V
–40
+140
°C
N
ew
RF Input Power
(for max level for correct packet reception see
Table 3.7)
Voltage on OSCA, OSCB, NC
Max
D
Regulator input voltage (VDD_PADS)
es
ig
ns
Table 3.1 lists the absolute maximum ratings for the EM359x.
3.2. Recommended Operating Conditions
Table 3.2 lists the rated operating conditions of the EM359x.
Typ
Max
Unit
om
Parameter
Test Condition
Regulator input voltage (VDD_PADS)
2.1
—
3.6
V
Analog and memory input voltage
(VDD_24MHZ, VDD_VCO, VDD_RF, VDD_IF,
VDD_PADSA, VDD_MEM, VDD_PRE,
VDD_SYNTH)
1.7
1.8
1.9
V
Core input voltage when supplied from internal
regulator (VDD_CORE)
1.18
1.25
1.32
V
Operating temperature range
–40
—
+85
°C
N
ot
R
Min
ec
Table 3.2. Operating Conditions
Rev 1.0
13
EM359x
3.3. Environmental Characteristics
Table 3.3 lists the rated environmental characteristics of the EM359x.
Parameter
Test Condition
Min
Typ
On any pin
—
—
ESD (charged device model)
Non-RF pins
—
—
ESD (charged device model)
RF pins
—
—
ESD (human body model)
Parameter
Test Condition
Regulator input voltage
(VDD_PADS)
Unit
±2
kV
±400
V
±225
V
N
ew
Table 3.4 lists the DC electrical characteristics of the EM359x.
Table 3.4. DC Characteristics
Max
D
3.4. DC Electrical Characteristics
es
ig
ns
Table 3.3. Environmental Characteristics
Min
Typ
Max
Unit
2.1
—
3.6
V
Regulator output or external input
1.7
1.8
1.9
V
Power supply range (VDD_CORE)
Regulator output
1.18
1.25
1.32
V
–40 °C, VDD_PADS=3.6 V
—
0.9
—
A
+25 °C, VDD_PADS=3.6 V
—
1.0
—
A
+85 °C, VDD_PADS=3.6 V
—
2.2
—
A
–40 °C, VDD_PADS=3.6 V
—
1.2
—
A
+25 °C, VDD_PADS=3.6 V
—
1.25
—
A
+85°C, VDD_PADS=3.6 V
—
2.5
—
A
–40 °C, VDD_PADS=3.6 V
—
1.3
—
A
+25 °C, VDD_PADS=3.6 V
—
1.6
—
A
+85 °C, VDD_PADS=3.6 V
—
2.9
—
A
–40 °C, VDD_PADS=3.6 V
—
1.6
—
A
+25 °C, VDD_PADS=3.6 V
—
1.9
—
A
+85 °C, VDD_PADS=3.6 V
—
3.2
—
A
–40 °C, VDD_PADS=3.6 V
—
0.007
—
A
+25 °C, VDD_PADS=3.6 V
—
0.067
—
A
+85 °C, VDD_PADS=3.6 V
—
0.76
—
A
–40 °C, VDD_PADS=3.6 V
—
0.57
—
A
+25 °C, VDD_PADS=3.6 V
—
0.67
—
A
+85 °C, VDD_PADS=3.6 V
—
2.0
—
A
With no debugger activity
—
500
—
A
Deep Sleep Current
m
en
de
d
Quiescent current, internal oscillator disabled, 4 kB RAM retained
fo
r
Power supply range (VDD_MEM)
Quiescent current, including
internal RC oscillator, 4 kB RAM
retained
om
Quiescent current, including
32.768 kHz oscillator, 4 kB RAM
retained
ec
Quiescent current, including
internal RC oscillator and
32.768 kHz oscillator, 4 kB RAM
retained
R
Additional quiescent current per
4 kB block of RAM retained
N
ot
Additional quiescent current when
retained RAM exceeds 32 kB
Simulated deep sleep (debug
mode) current
14
Rev 1.0
EM359x
Test Condition
Min
Typ
Max
Unit
Typ at 25 °C/3.0 V
Max at 85 °C/3.6 V
—
2
3
mA
ARM® CortexTM-M3, RAM, and
flash memory
25 °C, 1.8 V memory and
1.25 V core
ARM® CortexTM-M3 running at 12 MHz
from crystal oscillator
Radio and all peripherals off
—
7.5
—
mA
ARM® CortexTM-M3, RAM, and
flash memory
25 °C, 1.8 V memory and
1.25 V core
ARM® CortexTM-M3 running at 24 MHz
from crystal oscillator
Radio and all peripherals off
D
Table 3.4. DC Characteristics (Continued)
Parameter
—
—
mA
ARM® CortexTM-M3, RAM, and
flash memory sleep current
25 °C, 1.8 V memory and
1.25 V core
®
ARM CortexTM-M3 sleeping, CPU
clock set to 12 MHz from the crystal
oscillator
Radio and all peripherals off
—
4.0
—
mA
ARM® CortexTM-M3, RAM, and
flash memory sleep current
25 °C, 1.8 V memory and
1.25 V core
ARM® CortexTM-M3 sleeping, CPU
clock set to 6 MHz from the high frequency RC oscillator
Radio and all peripherals off
—
2.5
—
mA
Serial controller current
For each controller at maximum data
rate
—
0.2
—
mA
General purpose timer current
For each timer at maximum clock rate
—
0.25
—
mA
General purpose ADC current
At maximum sample rate, DMA enabled
—
1.1
—
mA
Quiescent current, nRESET
asserted
8.5
om
m
en
de
d
fo
r
N
ew
Processor and Peripheral Currents
es
ig
ns
Reset Current
USB active current
R
ec
USB suspended mode current
1
1.8 V memory and 1.25 V core
ARM® CortexTM-M3 sleeping, CPU
clock set to 3 MHz from the high frequency RC oscillator.
Radio and all peripherals off
mA
2.5
mA
RX Current
N
ot
Radio receiver, MAC, and baseband
ARM® CortexTM-M3 sleeping, CPU
clock set to 12 MHz
25 °C, VDD_PADS=3.0 V
Total RX current ( = IRadio receiver,
MAC and baseband, CPU + IRAM, ARM® CortexTM-M3 running at 12 MHz
and Flash memory )
25 °C, VDD_PADS=3.0 V
ARM® CortexTM-M3 running at 24 MHz
Rev 1.0
—
23.5
—
mA
—
25.5
—
mA
—
27.0
—
mA
15
EM359x
Table 3.4. DC Characteristics (Continued)
Min
Typ
Max
Unit
25 °C, VDD_PADS=3.0 V
ARM® CortexTM-M3 running at 12 MHz
—
27.5
—
mA
25 °C, VDD_PADS=3.0 V
ARM CortexTM-M3 running at 24 MHz
—
25 °C and 1.8 V core; max. power out
(+3 dBm typical)
ARM® CortexTM-M3 sleeping, CPU
clock set to 12 MHz
—
®
29.5
—
mA
27.5
—
mA
—
mA
TX Current
Radio transmitter, MAC, and baseband
es
ig
ns
Boost mode total RX current ( =
IRadio receiver, MAC and baseband, CPU+ IRAM, and flash
memory )
Test Condition
D
Parameter
25 °C, VDD_PADS=3.0 V
Total TX current ( = IRadio transmitter, MAC and baseband, CPU +
Maximum power setting (+8 dBm);
IRAM, and flash memory)
ARM® CortexTM-M3 running at 12 MHz
—
25 °C, VDD_PADS=3.0 V
+3 dBm power setting
®
ARM CortexTM-M3 running at 12 MHz
—
29.5
—
mA
25 °C, VDD_PADS=3.0 V
0 dBm power setting
ARM® CortexTM-M3 running at 12 MHz
—
29
—
mA
25 °C, VDD_PADS=3.0 V
Minimum power setting
ARM® CortexTM-M3 running at 12 MHz
—
24
—
mA
25 °C, VDD_PADS=3.0 V
Maximum power setting (+8 dBm)
ARM® CortexTM-M3 running at 24 MHz
—
41
—
mA
25 °C, VDD_PADS=3.0 V
+3 dBm power setting
®
ARM CortexTM-M3 running at 24 MHz
—
31.5
—
mA
25 °C, VDD_PADS=3.0 V
0 dBm power setting
ARM® CortexTM-M3 running at 24 MHz
—
29
—
mA
25 °C, VDD_PADS=3.0 V
Minimum power setting
ARM® CortexTM-M3 running at 24 MHz
—
23.5
—
mA
N
ot
R
ec
om
m
en
de
d
fo
r
N
ew
44
16
Rev 1.0
EM359x
m
en
de
d
fo
r
N
ew
D
es
ig
ns
Figure 3.1 shows the variation of current in transmit mode (with the ARM® CortexTM-M3 running at 12 MHz).
N
ot
R
ec
om
Figure 3.1. Transmit Power Consumption
Rev 1.0
17
EM359x
m
en
de
d
fo
r
N
ew
D
es
ig
ns
Figure 3.2 shows typical output power against power setting on the Silicon Labs reference design.
N
ot
R
ec
om
Figure 3.2. Transmit Output Power
18
Rev 1.0
EM359x
3.5. Digital I/O Specifications
Table 3.5 lists the digital I/O specifications for the EM359x. The digital I/O power (named VDD_PADS) comes from
three dedicated pins (Pins 27, 35, and 44). The voltage applied to these pins sets the I/O voltage.
Parameter
Test Condition
Voltage supply (regulator input voltage)
Min
Typ
Max
Unit
2.1
—
3.6
V
—
0.50 x
VDD_PADS
V
—
0.80 x
VDD_PADS
V
–0.5
μA
VSWIL
Schmitt input threshold going
from high to low
0.42 x
VDD_PADS
High Schmitt switching threshold
VSWIH
Schmitt input threshold going
from low to high
0.62 x
VDD_PADS
Input current for logic 0
IIL
—
Input current for logic 1
IIH
Input pull-down resistor value
RIPD
—
—
+0.5
μA
24
29
34
k
24
29
34
k
0
—
0.18 x
VDD_PADS
V
—
VDD_PADS
V
VOL
(IOL = 4 mA for standard pads,
8 mA for high current pads)
Output voltage for logic 1
VOH
0.82 x
VDD_PADS
(IOH = 4 mA for standard pads,
8 mA for high current pads)
m
en
de
d
fo
r
Output voltage for logic 0
Output source current
(standard current pad)
—
N
ew
RIPU
D
Low Schmitt switching threshold
Input pull-up resistor value
es
ig
ns
Table 3.5. Digital I/O Specifications
IOHS
—
—
4
mA
IOLS
—
—
4
mA
Output source current
high current pad: PA6, PA7, PB6, PB7,
PC0
IOHH
—
—
8
mA
Output sink current
high current pad: PA6, PA7, PB6, PB7,
PC0
IOLH
—
—
8
mA
IOH + IOL
—
—
40
mA
om
Output sink current
(standard current pad)
N
ot
R
ec
Total output current (for I/O Pads)
Rev 1.0
19
EM359x
Table 3.6 lists the nRESET pin specifications for the EM359x. The digital I/O power (named VDD_PADS) comes
from three dedicated pins (Pins 27, 35, and 44). The voltage applied to these pins sets the I/O voltage.
Table 3.6. nReset Pin Specifications
Min
Typ
Max
Unit
Low Schmitt switching threshold
VSWIL
Schmitt input threshold going from
high to low
0.42 x
VDD_PADS
—
0.50 x
VDD_PADS
V
High Schmitt switching threshold
VSWIH
Schmitt input threshold going from
low to high
0.62 x
VDD_PADS
—
0.80 x
VDD_PADS
V
IIH
—
Input pull-up resistor value
RIPU
Pull-up value while the chip is not
reset
24
Input pull-up resistor value
RIPURESET
Pull-up value while the chip is
reset
12
D
—
+0.5
μA
29
34
k
17
k
14.5
fo
r
Input current for logic 1
es
ig
ns
Test Condition
N
ew
Parameter
3.6. Non-RF System Electrical Characteristics
m
en
de
d
Table 3.7 lists the non-RF system level characteristics for the EM359x.
Table 3.7. Non-RF System Electrical Characteristics
Test Condition
Min
Typ
Max
Unit
System wake time from deep
sleep
From wakeup event to first ARM® CortexTM-M3 instruction running from 6 MHz
internal RC clock
Includes supply ramp time and oscillator
startup time
—
110
—
µs
Shutdown time going into deep
sleep
From last ARM® CortexTM-M3 instruction
to deep sleep mode
—
5
—
µs
N
ot
R
ec
om
Parameter
20
Rev 1.0
EM359x
3.7. RF Electrical Characteristics
3.7.1. Receive
Table 3.8 lists the key parameters of the integrated IEEE 802.15.4-2003 receiver on the EM359x.
Table 3.8. Receive Characteristics
Parameter
Test Condition
2400
Typ
Max
Unit
—
2500
MHz
–102
dBm
1% PER, 20 byte packet defined by
IEEE 802.15.4-2003
—
—
Sensitivity
1% PER, 20 byte packet defined by
IEEE 802.15.4-2003
—
–100
—
dBm
High-side adjacent channel rejection
IEEE 802.15.4-2003 interferer signal,
wanted IEEE 802.15.4-2003 signal
at –82 dBm
—
35
—
dB
Low-side adjacent channel rejection
IEEE 802.15.4-2003 interferer signal,
wanted IEEE 802.15.4-2003 signal
at –82 dBm
—
35
—
dB
2nd high-side adjacent channel rejection
IEEE 802.15.4-2003 interferer signal,
wanted IEEE 802.15.4-2003 signal
at –82 dBm
—
46
—
dB
2nd low-side adjacent channel rejection IEEE 802.15.4-2003 interferer signal,
wanted IEEE 802.15.4-2003 signal
at –82 dBm
—
46
—
dB
High-side adjacent channel rejection
Filtered IEEE 802.15.4-2003 interferer signal, wanted IEEE 802.15.42003 signal at –82 dBm
—
39
—
dB
Low-side adjacent channel rejection
Filtered IEEE 802.15.4-2003 interferer signal, wanted IEEE 802.15.42003 signal at –82 dBm
—
47
—
dB
2nd high-side adjacent channel
rejection
Filtered IEEE 802.15.4-2003 interferer signal, wanted IEEE 802.15.42003 signal at –82 dBm
—
49
—
dB
2nd low-side adjacent channel rejection
Filtered IEEE 802.15.4-2003 interferer signal, wanted IEEE 802.15.42003 signal at –82 dBm
—
49
—
dB
High-side adjacent channel rejection
CW interferer signal, wanted IEEE
802.15.4-2003 signal at –82 dBm
—
44
—
dB
Low-side adjacent channel rejection
CW interferer signal, wanted IEEE
802.15.4-2003 signal at –82 dBm
—
47
—
dB
N
ot
R
ec
om
m
en
de
d
fo
r
N
ew
Sensitivity (boost mode)
D
Frequency range
Min
es
ig
ns
Receive measurements were collected with the Silicon Labs EM359x Ceramic Balun Characterization Module
(Version P1) at 2440 MHz. The typical number indicates one standard deviation above the mean, measured at
room temperature (25C). The Min and Max numbers were measured over process corners at room temperature.
Rev 1.0
21
EM359x
Table 3.8. Receive Characteristics (Continued)
Test Condition
Min
Typ
Max
Unit
2nd high-side adjacent channel
rejection
CW interferer signal, wanted IEEE
802.15.4-2003 signal at –82 dBm
—
59
—
dB
2nd low-side adjacent channel rejection
CW interferer signal, wanted IEEE
802.15.4-2003 signal at –82 dBm
—
es
ig
ns
Parameter
59
—
dB
40
—
dB
36
—
dB
—
802.11g rejection centered at +12 MHz IEEE 802.15.4-2003 interferer signal,
or –13 MHz
wanted IEEE 802.15.4-2003 signal
at –82 dBm
—
Maximum input signal level for correct
operation
0
—
—
dBm
—
–6
—
dBc
–120
—
+120
ppm
–120
—
+120
ppm
40
—
—
dB
–90
—
–40
dBm
As defined by IEEE 802.15.4-2003
N
ot
R
ec
om
RSSI Range
m
en
de
d
Relative timing error tolerance
(50% greater than the 2x40 ppm
required by IEEE 802.15.4-2003)
fo
r
IEEE 802.15.4-2003 interferer signal,
wanted IEEE 802.15.4-2003 signal
at –82 dBm
Relative frequency error tolerance
(50% greater than the 2x40 ppm
required by IEEE 802.15.4-2003)
Linear RSSI range
N
ew
Co-channel rejection
22
D
Channel rejection for all other channels IEEE 802.15.4-2003 interferer signal,
wanted IEEE 802.15.4-2003 signal
at –82 dBm
Rev 1.0
EM359x
m
en
de
d
fo
r
N
ew
D
es
ig
ns
Figure 3.3 shows the variation of receive sensitivity with temperature for boost mode and normal mode for a typical
chip.
N
ot
R
ec
om
Figure 3.3. Receive Sensitivity vs. Temperature
Rev 1.0
23
EM359x
3.7.2. Transmit
Table 3.9 lists the key parameters of the integrated IEEE 802.15.4-2003 transmitter on the EM359x.
Table 3.9. Transmit Characteristics
Min
Maximum output power
(boost mode)
At highest boost mode power setting (+8)
—
Maximum output power
At highest normal mode power setting (+3)
Minimum output power
Error vector magnitude
(Offset-EVM)
Max
Unit
8
—
dBm
1
5
—
dBm
At lowest power setting
—
–55
—
dBm
As defined by IEEE 802.15.4-2003,
which sets a 35% maximum
—
5
15
%
–40
—
+40
ppm
–20
—
—
dB
–30
—
—
dBm
Carrier frequency error
3.5 MHz away
PSD mask absolute
3.5 MHz away
N
ot
R
ec
om
m
en
de
d
fo
r
PSD mask relative
24
Typ
D
Test Condition
N
ew
Parameter
es
ig
ns
Transmit measurements were collected with the Silicon Labs EM359x Ceramic Balun Reference Design (Version
A0) at 2440 MHz. The Typical number indicates one standard deviation below the mean, measured at room
temperature (25C). The Min and Max numbers were measured over process corners at room temperature. In
terms of impedance, this reference design presents a 3.9-nH inductor in parallel with a 100:50 Ω balun to the RF
pins.
Rev 1.0
EM359x
m
en
de
d
fo
r
N
ew
D
es
ig
ns
Figure 3.4 shows the variation of transmit power with temperature for maximum boost mode power, and normal
mode for a typical chip.
N
ot
R
ec
om
Figure 3.4. Transmit Power vs. Temperature
Rev 1.0
25
EM359x
3.7.3. Synthesizer
Table 3.10 lists the key parameters of the integrated synthesizer on the EM359x.
Table 3.10. Synthesizer Characteristics
Test Condition
Frequency range
2400
Frequency resolution
—
Relock time
From off
—
Channel change or RX/TX turnaround
(IEEE 802.15.4-2003 defines 192 μs
turnaround time)
—
Max
Unit
—
2500
MHz
11.7
—
kHz
—
100
μs
—
100
μs
—
—
dBc/Hz
–75
N
ew
Phase noise at 100 kHz offset
Typ
D
Lock time
Phase noise at 1 MHz offset
Phase noise at 4 MHz offset
N
ot
R
ec
om
m
en
de
d
fo
r
Phase noise at 10 MHz offset
26
Min
es
ig
ns
Parameter
Rev 1.0
—
–100
—
dBc/Hz
—
–108
—
dBc/Hz
—
–114
—
dBc/Hz
EM359x
4. EM359x System Overview
TX_ACTIVE
PA select
PA
DAC
SYNTH
MAC
+
Baseband
PA
RF_P,N
LNA
IF
ADC
OSCB
VDD_CORE
VREG_OUT
HF crystal
OSC
Internal HF
RC-OSC
1.25V
Regulator
GPIO
registers
General
Purpose
ADC
POR
CPU debug TPIU/
ITM/FPB/DWT/
ETM
Always
Powered
Domain
Encryption
acclerator
Watchdog
UART/SPI/
TWI
Internal LF
RC-OSC
Chip
manager
SWCLK, JTCK
Serial Wire
and JTAG
debug
Sleep
timer
fo
r
LF crystal
OSC
General
purpose
timers
USB
Device
1.8V
Regulator
nRESET
Calibration
ADC
N
ew
OSCA
2nd level
Interrupt
controller
ARM® CortexTM-M3
CPU with NVIC
and MPU
Packet Trace
Bias
Program Flash
256/512 kB
D
RF_TX_ALT_P,N
Data
RAM
32/64 kB
es
ig
ns
Figure 4.1 shows a detailed block diagram of the EM359x.
m
en
de
d
GPIO multiplexor switch
PA[7:0], PB[7:0], PC[7:0], PD[4:1], PE[3:0]
Figure 4.1. EM359x Block Diagram
The EM359x radio receiver is a low-IF, super-heterodyne receiver. The architecture has been chosen to optimize
co-existence with other devices in the 2.4 GHz band (namely Wi-Fi and Bluetooth), and to minimize power
consumption. The receiver uses differential signal paths to reduce sensitivity to noise interference. Following RF
amplification, the signal is downconverted by an image-rejecting mixer, filtered, and then digitized by an ADC.
om
The digital section of the receiver uses a coherent demodulator to generate symbols for the hardware-based MAC.
The digital receiver also contains the analog radio calibration routines, and controls the gain within the receiver
path.
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The radio transmitter uses an efficient architecture in which the data stream directly modulates the VCO frequency.
An integrated PA provides the output power. Digital logic controls Tx path and output power calibration. If the
EM359x is to be used with an external PA, use the TX_ACTIVE or nTX_ACTIVE signal to control the timing of the
external switching logic.
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The integrated 4.8 GHz VCO and loop filter minimize off-chip circuitry. Only a 24 MHz crystal with its loading
capacitors is required to establish the PLL local oscillator signal.
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The MAC interfaces the on-chip RAM to the Rx and Tx baseband modules. The MAC provides hardware-based
IEEE 802.15.4-2003 packet-level filtering. It supplies an accurate symbol time base that minimizes the
synchronization effort of the Ember software and meets the protocol timing requirements. In addition, it provides
timer and synchronization assistance for the IEEE 802.15.4-2003 CSMA-CA algorithm.
The EM359x integrates hardware support for a packet trace module, which allows robust packet-based debug.
This element is a critical component of Ember Desktop, the Ember development environment, and provides
advanced network debug capability when used with the Ember Debug Adapter (ISA3).
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EM359x
The EM359x integrates an ARM® CortexTM-M3 microprocessor, revision r1p1. This industry-leading core provides
32-bit performance and is very power-efficient. It has excellent code density using the ARM® Thumb-2 instruction
set. The processor can be operated at 12 or 24 MHz when using the high-frequency crystal oscillator, or at 6 MHz
or 12 MHz when using the high-frequency internal RC oscillator.
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EM359x parts have either 256 or 512 kB of flash memory and either 32 or 64 kB of RAM on-chip, and the ARM
configurable memory protection unit (MPU).
The EM359x implements both the ARM Serial Wire and JTAG debug interfaces. These interfaces provide real
time, non-intrusive programming and debugging capabilities. Serial Wire and JTAG provide the same functionality,
but are mutually exclusive. The Serial Wire interface uses two pins; the JTAG interface uses five. Serial Wire is
preferred, since it uses fewer pins.
The EM359x contains the ARM® Embedded Trace Macrocell (ETM) to provide advanced real time software
debugging features for complex systems.
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The EM359x contains 32 GPIO pins shared with other peripheral or alternate functions. Because of flexible routing
within the EM359x, external devices can use the alternate functions on a variety of different GPIOs. The integrated
serial controllers SC1 and SC3 can be configured for SPI (master or slave), TWI (master-only), or UART operation,
and the serial controllers SC2 and SC4 can be configured for SPI (master or slave) or TWI (master-only) operation.
The EM359x has an optional integrated USB 2.0-compliant, full-speed (12 Mbps) device peripheral, with an onchip transceiver. It is available on GPIO pins.
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The EM359x has a general purpose ADC which can sample analog signals from six GPIO pins in single-ended or
differential modes. It can also sample the 1.8 V regulated supply VDD_PADSA, the voltage reference VREF, and
GND. The ADC has one voltage range: 0 V to 1.2 V (normal). The ADC has a DMA mode to capture samples and
automatically transfer them into RAM. The integrated voltage reference for the ADC, VREF, can be made available
to external circuitry. An external voltage reference can also be driven into the ADC. The regulator input voltage,
VDD_PADS, cannot be measured using the general purpose ADC, but it can be measured through Ember
software.
The EM359x contains four oscillators: a high-frequency 24 MHz external crystal oscillator, a high-frequency 12
MHz internal RC oscillator, an optional low-frequency 32.768 kHz external crystal oscillator, and a low-frequency
10 kHz internal RC oscillator.
The EM359x has an ultra low power, deep sleep state with a choice of clocking modes. The sleep timer can be
clocked with either the external 32.768 kHz crystal oscillator or with a 1 kHz clock derived from the internal 10 kHz
RC oscillator. Alternatively, all clocks can be disabled for the lowest power mode. In the lowest power mode, only
external events on GPIO pins will wake up the chip. The EM359x has a fast startup time (typically 110 µs) from
deep sleep to the execution of the first ARM® CortexTM-M3 instruction.
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The EM359x contains three power domains. The always-on high voltage supply powers the GPIO pads and critical
chip functions. Regulated low voltage supplies power the rest of the chip. The low voltage supplies are disabled
during deep sleep to reduce power consumption. Integrated voltage regulators generate regulated 1.25 V and 1.8
V voltages from an unregulated supply voltage. The 1.8 V regulator output is decoupled and routed externally to
supply analog blocks, RAM, and flash memories. The 1.25 V regulator output is decoupled externally and supplies
the core logic.
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The following sections summarize features of the EM359x that are addressed in more detail in the Ember EM359x
Reference Manual.
4.1. Microprocessor and Memory
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Refer to chapter 2 in the Ember EM359x Reference Manual for more information.
4.1.1. ARM® Cortex™-M3 Microprocessor
The EM359x integrates the ARM® CortexTM-M3 microprocessor, revision r1p1, developed by ARM Ltd., making
the EM359x a true System-on-Chip solution. The ARM® CortexTM-M3 is an advanced 32-bit modified Harvard
architecture processor that has separate internal program and data buses, but presents a unified program and data
address space to software.
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4.1.2. Embedded Memory
Embedded memory consists of flash memory and RAM.
The EM359x provides a total of either 256 or 512 kB of flash memory (256 kB for EM3591/2 and 512 kB for
EM3595/6/7/8). The flash memory is provided in three separate blocks:
Flash Block (MFB)
Fixed Information Block (FIB)
Customer Information Block (CIB)
The EM359x has either 32 or 64 kB of static RAM on-chip (32 kB for EM3591/2/5/6 and 64 kB for EM3597/8).
Although the ARM® CortexTM-M3 allows bit band accesses to this address region, the standard MPU configuration
does not permit use of the bit-band feature. The RAM is physically connected to the AHB System bus and is
therefore accessible to both the ARM® CortexTM-M3 microprocessor and the debugger. The radio (802.15.4-2003
MAC), general purpose ADC, USB device controller, and the four serial controllers are equipped with DMA
controllers, which allow them to transfer data into and out of RAM autonomously.
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4.2. Interrupt System
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The EM359x’s interrupt system is composed of two parts: a standard ARM® CortexTM-M3 Nested Vectored
Interrupt Controller (NVIC) that provides top-level interrupts, and a proprietary Event Manager (EM) that provides
second-level interrupts. The NVIC and EM provide a simple hierarchy. All second-level interrupts from the EM feed
into top-level interrupts in the NVIC. This two-level hierarchy allows for both fine granular control of interrupt
sources and coarse granular control over entire peripherals, while allowing peripherals to have their own interrupt
vector.
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Refer to chapter 3 in the Ember EM359x Reference Manual for more information.
4.2.1. Nested Vectored Interrupt Controller (NVIC)
4.2.2. Event Manager
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The ARM® CortexTM-M3 Nested Vectored Interrupt Controller (NVIC) facilitates low-latency exception and interrupt
handling. The NVIC and the processor core interface are closely coupled, which enables low-latency interrupt
processing and efficient processing of late-arriving interrupts. The NVIC maintains knowledge of the stacked
(nested) interrupts to enable tail-chaining of interrupts. The NVIC also contains a software-configurable interrupt
prioritization mechanism.
The proprietary Event Manager provides second-level interrupts. The Event Manager takes a large variety of
hardware interrupt sources from the peripherals and merges them into a smaller group of interrupts in the NVIC.
Effectively, all second-level interrupts from a peripheral are “OR’d” together into a single interrupt in the NVIC. In
addition, the Event Manager provides missed indicators for the top-level peripheral interrupts with the register
INT_MISS.
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4.2.3. Memory Protection Unit
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The EM359x includes the ARM® CortexTM-M3 Memory Protection Unit, or MPU. The MPU controls access rights
and characteristics of up to eight address regions, each of which may be divided into eight equal sub-regions.
Refer to the ARM® CortexTM-M3 Technical Reference Manual (DDI 0337A) for a detailed description of the MPU.
4.3. Radio Module
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The radio module consists of an analog front end and digital baseband.
Refer to chapter 4 in the Ember EM359x Reference Manual for more information.
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4.3.1. Receive (Rx) Path
The EM359x Rx path uses a low-IF, super-heterodyne receiver that rejects the image frequency using complex
mixing and polyphase filtering. The filtering within the Rx path improves the EM359x’s co-existence with other 2.4
GHz transceivers such as Zigbee/ 802.15.4-2003, IEEE 802.11-2007, and Bluetooth radios. The digital baseband
also provides gain control of the Rx path, both to enable the reception of small and large wanted signals and to
tolerate large interferers.
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EM359x
4.3.2. Transmit (Tx) Path
The EM359x Tx path produces an O-QPSK-modulated signal using the analog front end and digital baseband. The
area- and power-efficient Tx architecture uses a two-point modulation scheme to modulate the RF signal
generated by the synthesizer. The modulated RF signal is fed to the integrated PA and then out of the EM359x.
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4.3.3. Integrated MAC Module
The EM359x integrates most of the IEEE 802.15.4-2003 MAC requirements in hardware. This allows the ARM®
CortexTM-M3 CPU to provide greater bandwidth to application and network operations. In addition, the hardware
acts as a first-line filter for unwanted packets. The EM359x MAC uses a DMA interface to RAM to further reduce
the overall ARM® CortexTM-M3 CPU interaction when transmitting or receiving packets.
The primary features of the MAC are:
CRC
generation, appending, and checking
timers and interrupts to achieve the MAC symbol timing
Automatic preamble and SFD pre-pending on Tx packets
Address recognition and packet filtering on Rx packets
Automatic acknowledgement transmission
Automatic transmission of packets from memory
Automatic transmission after backoff time if channel is clear (CCA)
Automatic acknowledgement checking
Time stamping received and transmitted messages
Attaching packet information to received packets (LQI, RSSI, gain, time stamp, and packet status)
EEE 802.15.4-2003 timing and slotted/unslotted timing
4.3.4. Packet Trace Interface (PTI)
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The EM359x integrates a true PHY-level PTI with the MAC, allowing complete, non-intrusive capture of all packets
to and from the EM359x with Ember development tools.
4.3.5. Random Number Generator
Thermal noise in the analog circuitry is digitized to provide entropy for a true random number generator (TRNG).
Ember software uses the TRNG to seed a pseudo random number generator (PRNG). The TRNG is also used
directly for cryptographic key generation.
4.4. System Modules
System modules encompass power domains, resets, clocks, system timers, power management, and encryption.
Refer to chapter 5 in the Ember EM359x Reference Manual for more information.
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4.4.1. Power domains
The EM359x contains three power domains:
“always-on domain” containing all logic and analog cells required to manage the EM359x’s power
modes, including the GPIO controller and sleep timer. This domain must remain powered.
A “core domain” containing the CPU, Nested Vectored Interrupt Controller (NVIC), and peripherals. To
save power, this domain can be powered down using a mode called deep sleep. In the EM359x the core
domain also includes the RAM, which by default is powered down in deep sleep. An additional feature of
the RAM is that blocks of RAM cells can optionally be retained in deep sleep. This is configured using a
register, which must be written before entering deep sleep.
A “flash domain” containing the flash memory. This domain is managed by the power management
controller. During deep sleep the flash portion is completely powered down.
The preferred and recommended power configuration is to use the internal regulated power supplies to provide
power to the core and memory domains. Optionally, the on-chip regulators may be left unused, and the core and
memory domains may instead be powered from external supplies.
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Refer to chapter 6 in the Ember EM359x Reference Manual for more information.
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4.4.2. Resets
The EM359x resets are generated from a number of sources. Each of these reset sources feeds into central reset
detection logic that causes various parts of the system to be reset depending on the state of the system and the
nature of the reset event. Reset sources include:
(POR HV and POR LV)
Pin
Watchdog Reset
Software Reset
Option Byte Error
Debug Reset
JRST
Deep Sleep Reset
The EM359x records the last reset condition that generated a restart to the system. The Reset Generation module
responds to reset sources and generates reset signals, which vary based on the reset source and cause.
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Power-On-Resets
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4.4.3. Clocks
The EM359x integrates four oscillators:
12
MHz RC oscillator: Used as the default system clock source when power is applied to the core domain.
MHz crystal oscillator: Requires an external 24 MHz crystal. Used as the system clock source when all
peripherals, including the radio peripheral, require the most accurate clock.
10 kHz RC oscillator: Provided as an internal timing reference
32.768 kHz crystal oscillator: Provided as an optional timing reference for on-chip timers.
4.4.4. System Timers
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The EM359x contains three system timers:
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Timer: Can be enabled to provide protection against software crashes and ARM® CortexTM-M3
CPU lockup.
Sleep Timer: 32-bit timer dedicated to system timing and waking from sleep at specific times.
Watchdog
Event
Timer: An ARM® standard system timer in the NVIC.
4.4.5. Power Management
The EM359x’s power management system is designed to achieve the lowest deep sleep current consumption
possible while still providing flexible wakeup sources, timer activity, and debugger operation. The EM359x has four
main sleep modes:
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Sleep: Puts the CPU into an idle state where execution is suspended until any interrupt occurs. All
power domains remain fully powered and nothing is reset.
Deep Sleep 1: The primary deep sleep state. In this state, the core power domain is fully powered down
and the sleep timer is active.
Deep Sleep 2: The same as Deep Sleep 1 except that the sleep timer is inactive to save power. In this
mode the sleep timer cannot wake up the EM359x.
Deep Sleep 0 (also known as Emulated Deep Sleep): The chip emulates a true deep sleep without
powering down the core domain. Instead, the core domain remains powered and all peripherals except the
system debug components (ITM, DWT, FPB, NVIC) are held in reset. The purpose of this sleep state is to
allow EM359x software to perform a deep sleep cycle while maintaining debug configuration such as
breakpoints.
The deep sleep modes consume less than 2 µA power. When in deep sleep the EM359x can be returned to the
running state in a number of ways. The wake sources are split depending on deep sleep 1 or deep sleep 2.
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Idle
The RAM can optionally be configured to select banks of locations to be non-volatile. In deep sleep those banks
selected are powered by a low leakage internal regulator that remains on during deep sleep, powered from the
always-on supply.
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EM359x
4.5. Integrated Voltage Regulator
Refer to chapter 6 in the Ember EM359x Reference Manual for more information.
4.6. Peripherals
4.6.1. GPIO
The EM359x has 32 multi-purpose GPIO pins, which may be individually configured as:
General
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The EM359x integrates two low dropout regulators to provide 1.8 V and 1.25 V power supplies. The 1V8 regulator
supplies the analog and memories, and the 1V25 regulator supplies the digital core. In deep sleep the voltage
regulators are disabled. An external 1.8 V regulator may replace both internal regulators. The always-on domain
needs to be minimally powered at 2.1 V, and cannot be powered from the external 1.8 V regulator.
purpose output
purpose open-drain output
Alternate output controlled by a peripheral device
Alternate open-drain output controlled by a peripheral device
Analog
General purpose input
General purpose input with pull-up or pull-down resistor
The 32 GPIO pins are grouped into five ports. Each pin has a 4-bit configuration value in its GPIO_PxCFGH/L
register. If a GPIO has two peripherals that can be the source of alternate output mode data, then other registers in
addition to GPIO_PxCFGH/L determine which peripheral controls the output. For some GPIOs the
GPIO_PxCFGH/L configuration will be overridden. These functions are forced when the EM359x is reset and
remain forced until software or an external debugger overrides the forced functions.
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Refer to chapter 7 in the Ember EM359x Reference Manual for more information.
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4.6.2. Serial Controllers
The EM359x has four serial controllers, SC1, SC2, SC3, and SC4, which provide several options for full-duplex
synchronous and asynchronous serial communications.
SPI
(Serial Peripheral Interface), master or slave
TWI (Two Wire serial Interface), master only
UART (Universal Asynchronous Receiver/Transmitter), SC1 and SC3 only
Receive and transmit FIFOs and DMA channels, SPI and UART modes
The SC1, SC2, SC3, and SC4 SPI controllers include an SPI master controller with the following features:
duplex operation
Programmable clock frequency (12 MHz max.)
Programmable clock polarity and phase
Selectable data shift direction (either LSB or MSB first)
Receive and transmit FIFOs
Receive and transmit DMA channels
The SC1, SC2, SC3, and SC4 SPI controllers include a SPI slave controller with these features:
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Full
duplex operation
to 5 Mbps data transfer rate
Programmable clock polarity and clock phase
Selectable data shift direction (either LSB or MSB first)
Slave select input
SC1, SC2, SC3, and SC4 include a Two Wire serial Interface (TWI) master controller with the following features:
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Uses
only two bidirectional GPIO pins
Programmable clock frequency (up to 400 kHz)
Supports both 7-bit and 10-bit addressing
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Compatible
with Philips’ I2C-bus slave devices
The SC1 and SC3 UART supports the following features:
baud rate clock (300 bps to 921.6 kbps)
Data bits (7 or 8)
Parity bits (none, odd, or even)
Stop bits (1 or 2)
False start bit and noise filtering
Receive and transmit FIFOs
Optional RTS/CTS flow control
Receive and transmit DMA channels
Receive and transmit FIFOs allow faster data speeds using byte-at-a-time interrupts. For the highest SPI and
UART speeds, dedicated receive and transmit DMA channels reduce CPU loading and extend the allowable time
to service a serial controller interrupt.
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Flexible
4.6.3. USB
It supports up to six endpoints (in addition to the control endpoint 0). There are five endpoints that can be used as
either interrupt or bulk and one isochronous endpoint.
The USB peripheral is interfaced to the CPU through memory mapped registers for control, and DMA for data. The
USB device generates its own 48 MHz internal clock from the main 24 MHz crystal clock.
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The EM359x, where applicable, fully supports USB suspend and resume modes, and meets the USB specification
suspend current of
