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MGM111 Mighty Gecko Mesh Networking
Module Data Sheet
D
The Silicon Labs Mighty Gecko Module (MGM111) is a fully-integrated, pre-certified
module, enabling rapid development of wireless mesh networking solutions.
KEY FEATURES
• Industry-leading mesh networking
(ZigBee/Thread) and Bluetooth Smart
software and development tools
N
ew
Based on the Silicon Labs EFR32™ Mighty Gecko SoC, the MGM111 combines an energy-efficient, multi-protocol wireless SoC with a proven RF/antenna design and industryleading wireless software stacks. This integration accelerates time-to-market and saves
months of engineering effort and development costs.
In addition, common software and development tools enable seamless migration from a
module to discrete SoC-based design when the time is right.
Core / Memory
Debug Interface
Matching
fo
r
CRYPTO
32.768 kHz
Low Frequency
RC Oscillator
Auxiliary
High Frequency
RC Oscillator
DC-DC
Converter
Power-On Reset
CRC
Low Frequency
Crystal Oscillator
Ultra Low
Frequency
RC Oscillator
Brown-Out
Detector
32-bit bus
Peripheral Reflex System
Serial Interfaces
Radio Transceiver
FRC
DEMOD
RF Frontend
LNA
I
PGA
BALUN
PA
Q
Frequency
Synthesizer
Other
Voltage Monitor
BUFC
R
N
ot
Ext. Antenna
u.FL Connector
(MGM111E)
Energy Management
Voltage
Regulator
USART
Low Energy
UART
IFADC
AGC
RAC
Antenna
• Autonomous Hardware Crypto Accelerator
and Random Number Generator
High Frequency
RC Oscillator
DMA Controller
Chip Antenna
(MGM111A)
• RAM: 32 kB
High Frequency
Crystal Oscillator
CRC
RAM Memory
• Flash memory: 256 kB
38.4 MHz
Memory
Protection Unit
ec
Flash Program
Memory
• RX sensitivity: down to -99 dBm
• Integrated DC-DC Converter
Clock Management
Crystals
om
ARM Cortex M4 Processor
with DSP Extensions and FPU
m
en
de
d
Connected Home
Building Automation
Lighting
Security and Monitoring
Smart Grid / Metering
Industrial Automation
Others
• TX power: up to +10 dBm
• 32-bit ARM® Cortex®-M4 at 40 MHz
MGM111 can be used in a wide variety of applications:
•
•
•
•
•
•
•
• Antenna: internal chip and U.FL variants
MOD
I2 C
I/O Ports
External
Interrupts
General Purpose
I/O
Pin Reset
Timers and Triggers
Timer/Counter
Low Energy Timer
Analog I/F
Protocol Timer
ADC
Watchdog Timer
Analog
Comparator
Pulse Counter
RTCC
IDAC
Cryotimer
Pin Wakeup
Lowest power mode with peripheral operational:
EM0— Active
EM1— Sleep
silabs.com | Building a more connected world.
EM2— Deep Sleep
EM3— Stop
Copyright © 2022 by Silicon Laboratories
EM4— Hibernate
EM4— Shutoff
Rev. 1.1
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Feature List
1. Feature List
• Timers: RTCC, Low Energy Timer, Pulse Counter
• 12-channel Peripheral Reflex System (PRS)
• Up to 25 GPIO with interrupts
Analog Peripherals
• ADC (12-bit, 1 Msps, 326 µA)
• Current-mode Digital to Analog Converter (IDAC)
• 2 x Analog Comparator (ACMP)
Energy Efficient Low Power Modes
• Energy Mode 2 (Deep Sleep) Current: 2.5 µA
es
ig
ns
• Low Energy UART (LEUART™)
• I2C peripheral interface (address recognition down to EM3)
•
•
•
•
•
•
•
IEEE 802.15.4
Data Rate / Modulation: 250 kbps DSSS-OQPSK
+10 dBm Programmable TX Power
-99 dBm RX Sensitivity
9.8 mA RX current
8.2 mA TX current (at +0 dBm)
Support for SoC and Network Co-Processor (NCP) architectures with SPI/UART host support
• Serial and Over-The-Air (OTA) bootloaders
D
Digital Peripherals
• 2 x USART (UART, SPI, IrDA, I2S)
ZigBee and Thread Features
N
ew
• ARM Cortex®-M4 + Floating Point Unit
• Up to 40 MHz Clock Speed
• Low Active Mode Current: 63 μA/MHz
• 256 kB flash, 32 kB SRAM
• Advanced hardware cryptographic engine with support for
AES-128/-256, ECC, SHA-1, SHA-256, and a Random Number Generator
• 8 Channel DMA Controller
Radio Features
• 2.4 GHz with integrated balun
• Support for wireless mesh networking (ZigBee/Thread)
• Integrated PA
• Packet Trace Interface (PTI) for non-intrusive packet trace with
Simplicity Studio development tools
• Antenna interface: integrated high-performance chip antenna
fo
r
MCU Features
m
en
de
d
(Full RAM retention and RTCC running from LXFO)
• Ultra-fast wake up: 3 µS down to EM3
• Wide Supply Voltage range of 1.85 to 3.8 V
Environmental & Regulatory
• Operating Temperature: -40 to +85°C
N
ot
R
ec
om
Dimensions
• W x L x H: 12.9 x 15.0 x 2.2 mm
silabs.com | Building a more connected world.
Rev. 1.1 | 2
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Ordering Information
2. Ordering Information
Ordering Code
Description
Max TX
Power
Antenna
Packaging Production Status
MGM111A256V1
Mighty Gecko Module
+10 dBm
Integrated chip antenna
Cut Reel
Integrated chip antenna
Reel
External (U.FL)
Cut Reel
MGM111E256V1
Mighty Gecko Module
+10 dBm
+10 dBm
(1000 pcs)
(100 pcs)
MGM111E256V1R Mighty Gecko Module
+10 dBm
External (U.FL)
Reel
Mighty Gecko Module
MGM111A256V2R Mighty Gecko Module
MGM111E256V2
Mighty Gecko Module
+10 dBm
+10 dBm
+10 dBm
Initial Production / Engineering
Samples (non-certified)
Integrated
Cut Reel
chip antenna
(100 pcs)
Integrated
Reel
Full Production (certified)
N
ew
MGM111A256V2
Initial Production / Engineering
Samples (non-certified)
D
(1000 pcs)
Initial Production / Engineering
Samples (non-certified)
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ns
MGM111A256V1R Mighty Gecko Module
(100 pcs)
Initial Production / Engineering
Samples (non-certified)
chip antenna
(1000 pcs)
External (U.FL)
Cut Reel
Full Production (certified)
Full Production (certified)
MGM111E256V2R Mighty Gecko Module
+10 dBm
fo
r
(100 pcs)
External (U.FL)
Reel
Full Production (certified)
m
en
de
d
(1000 pcs)
SLWRB4300B
MGM111A Radio Board Add- +10 dBm
On for Mesh Networking Kit
(SLWSTK6000A)
Integrated chip antenna
Single unit Initial Production / Engineering
Samples (non-certified)
N
ot
R
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om
Note:
1. IAR license required for ZigBee and Thread software development.
silabs.com | Building a more connected world.
Rev. 1.1 | 3
Table of Contents
1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
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3.3 Power . . . . . . . . . . .
3.3.1 Energy Management Unit (EMU)
3.3.2 DC-DC Converter . . . . .
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3.4 General Purpose Input/Output (GPIO) .
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3.5 Clocking . . . . . . . . . .
3.5.1 Clock Management Unit (CMU) .
3.5.2 Internal Oscillators . . . . .
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3.7 Communications and Other Digital Peripherals . . . . . . . . . .
3.7.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) .
3.7.2 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) .
3.7.3 Inter-Integrated Circuit Interface (I2C) . . . . . . . . . . . .
3.7.4 Peripheral Reflex System (PRS) . . . . . . . . . . . . .
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3.2 Radio . . . . . . . . .
3.2.1 Antenna Interface . . .
3.2.2 Packet and State Trace .
3.2.3 Random Number Generator
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3.6 Counters/Timers and PWM . . . . . . . . .
3.6.1 Timer/Counter (TIMER) . . . . . . . .
3.6.2 Real Time Counter and Calendar (RTCC) . .
3.6.3 Low Energy Timer (LETIMER) . . . . . .
3.6.4 Ultra Low Power Wake-up Timer (CRYOTIMER)
3.6.5 Pulse Counter (PCNT) . . . . . . . . .
3.6.6 Watchdog Timer (WDOG) . . . . . . . .
N
ew
3.1 Introduction .
es
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3. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
ec
3.8 Security Features . . . . . . . . . . . . . . .
3.8.1 GPCRC (General Purpose Cyclic Redundancy Check) .
3.8.2 Crypto Accelerator (CRYPTO) . . . . . . . . .
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.12
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3.10 Reset Management Unit (RMU) .
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.12
3.11 Core and Memory . . . . . . . . . . . .
3.11.1 Processor Core . . . . . . . . . . . .
3.11.2 Memory System Controller (MSC) . . . . .
3.11.3 Linked Direct Memory Access Controller (LDMA)
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3.12 Memory Map .
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3.9 Analog. . . . . . . . . . . . . .
3.9.1 Analog Port (APORT) . . . . . . .
3.9.2 Analog Comparator (ACMP) . . . . .
3.9.3 Analog to Digital Converter (ADC) . . .
3.9.4 Digital to Analog Current Converter (IDAC)
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silabs.com | Building a more connected world.
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Rev. 1.1 | 4
3.13 Configuration Summary
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5. Typical Connection Diagrams
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4.1 Electrical Characteristics . . . . . .
4.1.1 Absolute Maximum Ratings . . . .
4.1.2 General Operating Conditions . . .
4.1.3 DC-DC Converter . . . . . . .
4.1.4 Current Consumption . . . . . .
4.1.5 Wake up times . . . . . . . .
4.1.6 Brown Out Detector . . . . . . .
4.1.7 Frequency Synthesizer Characteristics
4.1.8 2.4 GHz RF Transceiver Characteristics
4.1.9 Oscillators . . . . . . . . . .
4.1.10 Flash Memory Characteristics . . .
4.1.11 GPIO . . . . . . . . . . .
4.1.12 VMON . . . . . . . . . . .
4.1.13 ADC . . . . . . . . . . .
4.1.14 IDAC . . . . . . . . . . .
4.1.15 Analog Comparator (ACMP) . . .
4.1.16 I2C . . . . . . . . . . . .
4.1.17 USART SPI . . . . . . . . .
N
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4. Electrical Specifications
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5.2 Network Co-Processor (NCP) Application with SPI Host .
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5.3 SoC Application
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.43
6. Layout Guidelines
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5.1 Network Co-Processor (NCP) Application with UART Host .
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6.1 Module Placement and Application PCB Layout Guidelines .
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6.2 Effect of Plastic and Metal Materials .
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7. Hardware Design Guidelines
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7.3 Debug and Firmware Updates . .
7.3.1 JTAG. . . . . . . . .
7.3.2 Packet Trace Interface (PTI) .
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7.1 Power Supply Requirements .
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7.2 Reset Functions
8. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.1 Pin Definitions . . .
8.1.1 GPIO Overview .
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8.2 Alternate Functionality Pinout .
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8.3 Analog Port (APORT).
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9. Package Specifications
silabs.com | Building a more connected world.
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Rev. 1.1 | 5
9.1 MGM111 Dimensions.
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11. Certificates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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10.1 Tape and Reel Packaging.
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10. Tape and Reel Specifications . . . . . . . . . . . . . . . . . . . . . . . . 77
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12. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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silabs.com | Building a more connected world.
Rev. 1.1 | 6
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
System Overview
3. System Overview
3.1 Introduction
Radio Transciever
Port I/O Configuration
FRC
Digital Peripherals
LETIMER
LNA
Frequency
Synthesizer
Q
AGC
MOD
TIMER
CRYOTIMER
Port A
Drivers
PCNT
RTC / RTCC
USART
RFVDD
Up to 256 KB ISP Flash
Program Memory
LEUART
IOVDD
Up to 32 KB RAM
Voltage
Monitor
AVDD
Memory Protection Unit
DVDD
Floating Point Unit
bypass
VREGSW
DC-DC
Converter
DMA Controller
Voltage
Regulator
Watchdog
Timer
VSS
Brown Out /
Power-On
Reset
CRC
Internal
Reference
VDD
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ULFRCO
AUXHFRCO
12-bit ADC
LFXTAL_P / N
LFXO
HFXO
HFXTAL_N
Port C
Drivers
PCn
Port D
Drivers
PDn
Port F
Drivers
PFn
VDD
Temp
Sensor
LFRCO
HFRCO
HFXTAL_P
PBn
IDAC
VREF
Clock Management
Reset
Management
Unit
RESETn
CRYPTO
Analog Peripherals
Serial Wire Debug /
Programming
DECOUPLE
VREGVSS
RFVSS
PAVSS
A A
H P
B B
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VREGVDD
Port B
Drivers
I2C
Input MUX
PAVDD
Port
Mapper
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ARM Cortex-M4 Core
Energy Management
PAn
D
PA
RAC
BALUN
CRC
2G4RF_IOP
2G4RF_ION
IOVDD
APORT
IFADC
PGA
BUFC
DEMOD
RF Frontend
I
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This section provides a brief overview of the MGM111 module architecture including both MCU and RF sub-systems. A detailed functional description of the Silicon Lab's EFR32MG1 SoC used inside the module is available in the EFR32MG1 Mighty Gecko Datasheet
and EFR32xG1 Wireless Gecko Reference Manual and a block diagram of the EFR32MG1 SoC is shown in the figure below.
+
Analog Comparator
om
Figure 3.1. Detailed EFR32MG1 Block Diagram
3.2 Radio
ec
The MGM111 features a flexible, multi-protocol radio that supports wireless mesh networking (ZigBee® / Thread) and Bluetooth Smart
protocols.
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3.2.1 Antenna Interface
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ot
The MGM111 module family includes options for either a high-performance, integrated chip-antenna (MGM111A) or external antenna
(MGM111E) via a U.FL connector. The table below includes performance specifications for the integrated chip antenna.
Table 3.1. Antenna Efficiency and Peak Gain (MGM111A)
Parameter
With optimal layout Note
Efficiency
-2 dB to -3 dB
Peak gain
1.0 dBi
silabs.com | Building a more connected world.
Antenna efficiency, gain and radiation pattern are highly dependent on the application PCB layout and mechanical design. Refer
to Chapter 6. Layout Guidelines for PCB layout and antenna integration guidelines for optimal performance.
Rev. 1.1 | 7
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
System Overview
3.2.2 Packet and State Trace
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The MGM111 Frame Controller has a packet and state trace unit that provides valuable information during the development phase. It
features:
• Non-intrusive trace of transmit data, receive data and state information
• Data observability on a single-pin UART data output, or on a two-pin SPI data output
• Configurable data output bitrate / baudrate
• Multiplexed transmitted data, received data and state / meta information in a single serial data stream
3.2.3 Random Number Generator
The Frame Controller (FRC) implements a random number generator that uses entropy gathered from noise in the RF receive chain.
The data is suitable for use in cryptographic applications.
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Output from the random number generator can be used either directly or as a seed or entropy source for software-based random number generator algorithms such as Fortuna.
silabs.com | Building a more connected world.
Rev. 1.1 | 8
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
System Overview
3.3 Power
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The MGM111 has an Energy Management Unit (EMU) and efficient integrated regulators to generate internal supply voltages. Only a
single external supply voltage is required, from which all internal voltages are created. An integrated DC-DC buck regulator is utilized to
further reduce the current consumption.
om
Figure 3.2. MGM111 Power Block
3.3.1 Energy Management Unit (EMU)
R
ec
The Energy Management Unit manages transitions of energy modes in the device. Each energy mode defines which peripherals and
features are available and the amount of current the device consumes. The EMU can also be used to turn off the power to unused RAM
blocks, and it contains control registers for the DC-DC regulator and the Voltage Monitor (VMON). The VMON is used to monitor multiple supply voltages. It has multiple channels which can be programmed individually by the user to determine if a sensed supply has
fallen below a chosen threshold.
N
ot
3.3.2 DC-DC Converter
The DC-DC buck converter covers a wide range of load currents and provides up to 90% efficiency in energy modes EM0, EM1, EM2,
and EM3. Patented RF noise mitigation allows operation of the DC-DC converter without degrading sensitivity of radio components.
Protection features include programmable current limiting, short-circuit protection, and dead-time protection. The DC-DC converter may
also enter bypass mode when the input voltage is too low for efficient operation. In bypass mode, the DC-DC input supply is internally
connected directly to its output through a low resistance switch. Bypass mode also supports in-rush current limiting to prevent input
supply voltage droops due to excessive output current transients.
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Rev. 1.1 | 9
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
System Overview
3.4 General Purpose Input/Output (GPIO)
MGM111 has 25 General Purpose Input/Output pins. Each GPIO pin can be individually configured as either an output or input. More
advanced configurations including open-drain, open-source, and glitch-filtering can be configured for each individual GPIO pin. The
GPIO pins can be overridden by peripheral connections, like SPI communication. Each peripheral connection can be routed to several
GPIO pins on the device. The input value of a GPIO pin can be routed through the Peripheral Reflex System to other peripherals. The
GPIO subsystem supports asynchronous external pin interrupts.
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3.5 Clocking
3.5.1 Clock Management Unit (CMU)
D
The Clock Management Unit controls oscillators and clocks in the MGM111. Individual enabling and disabling of clocks to all peripheral
modules is perfomed by the CMU. The CMU also controls enabling and configuration of the oscillators. A high degree of flexibility allows software to optimize energy consumption in any specific application by minimizing power dissipation in unused peripherals and
oscillators.
3.5.2 Internal Oscillators
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The MGM111 fully integrates two crystal oscillators and four RC oscillators, listed below.
• A 38.4MHz high frequency crystal oscillator (HFXO) provides a precise timing reference for the MCU and radio.
• A 32.768 kHz crystal oscillator (LFXO) provides an accurate timing reference for low energy modes.
• An integrated high frequency RC oscillator (HFRCO) is available for the MCU system, when crystal accuracy is not required. The
HFRCO employs fast startup at minimal energy consumption combined with a wide frequency range.
• An integrated auxilliary high frequency RC oscillator (AUXHFRCO) is available for timing the general-purpose ADC and the Serial
Wire debug port with a wide frequency range.
• An integrated low frequency 32.768 kHz RC oscillator (LFRCO) can be used as a timing reference in low energy modes, when crystal accuracy is not required.
• An integrated ultra-low frequency 1 kHz RC oscillator (ULFRCO) is available to provide a timing reference at the lowest energy consumption in low energy modes.
3.6 Counters/Timers and PWM
3.6.1 Timer/Counter (TIMER)
om
TIMER peripherals keep track of timing, count events, generate PWM outputs and trigger timed actions in other peripherals through the
PRS system. The core of each TIMER is a 16-bit counter with up to 4 compare/capture channels. Each channel is configurable in one
of three modes. In capture mode, the counter state is stored in a buffer at a selected input event. In compare mode, the channel output
reflects the comparison of the counter to a programmed threshold value. In PWM mode, the TIMER supports generation of pulse-width
modulation (PWM) outputs of arbitrary waveforms defined by the sequence of values written to the compare registers, with optional
dead-time insertion available in timer unit TIMER_0 only.
3.6.2 Real Time Counter and Calendar (RTCC)
R
ec
The Real Time Counter and Calendar (RTCC) is a 32-bit counter providing timekeeping in all energy modes. The RTCC includes a
Binary Coded Decimal (BCD) calendar mode for easy time and date keeping. The RTCC can be clocked by any of the on-board oscillators with the exception of the AUXHFRCO, and it is capable of providing system wake-up at user defined instances. When receiving
frames, the RTCC value can be used for timestamping. The RTCC includes 128 bytes of general purpose data retention, allowing easy
and convenient data storage in all energy modes.
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3.6.3 Low Energy Timer (LETIMER)
The unique LETIMER is a 16-bit timer that is available in energy mode EM0 Active, EM1 Sleep, EM2 Deep Sleep, and EM3 Stop. This
allows it to be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed
while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of waveforms with minimal software intervention. The LETIMER is connected to the Real Time Counter and Calendar (RTCC), and can be configured to start counting on compare matches from the RTCC.
silabs.com | Building a more connected world.
Rev. 1.1 | 10
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
System Overview
3.6.4 Ultra Low Power Wake-up Timer (CRYOTIMER)
The CRYOTIMER is a 32-bit counter that is capable of running in all energy modes. It can be clocked by either the 32.768 kHz crystal
oscillator (LFXO), the 32.768 kHz RC oscillator (LFRCO), or the 1 kHz RC oscillator (ULFRCO). It can provide periodic Wakeup events
and PRS signals which can be used to wake up peripherals from any energy mode. The CRYOTIMER provides a wide range of interrupt periods, facilitating flexible ultra-low energy operation.
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3.6.5 Pulse Counter (PCNT)
The Pulse Counter (PCNT) peripheral can be used for counting pulses on a single input or to decode quadrature encoded inputs. The
clock for PCNT is selectable from either an external source on pin PCTNn_S0IN or from an internal timing reference, selectable from
among any of the internal oscillators, except the AUXHFRCO. The module may operate in energy mode EM0 Active, EM1 Sleep, EM2
Deep Sleep, and EM3 Stop.
3.6.6 Watchdog Timer (WDOG)
D
The watchdog timer can act both as an independent watchdog or as a watchdog synchronous with the CPU clock. It has windowed
monitoring capabilities, and can generate a reset or different interrupts depending on the failure mode of the system. The watchdog can
also monitor autonomous systems driven by PRS.
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3.7 Communications and Other Digital Peripherals
3.7.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
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The Universal Synchronous/Asynchronous Receiver/Transmitter is a flexible serial I/O module. It supports full duplex asynchronous
UART communication with hardware flow control as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with devices supporting:
• ISO7816 SmartCards
• IrDA
• I2S
3.7.2 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART)
The unique LEUARTTM provides two-way UART communication on a strict power budget. Only a 32.768 kHz clock is needed to allow
UART communication up to 9600 baud. The LEUART includes all necessary hardware to make asynchronous serial communication
possible with a minimum of software intervention and energy consumption.
3.7.3 Inter-Integrated Circuit Interface (I2C)
ec
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The I2C module provides an interface between the MCU and a serial I2C bus. It is capable of acting as both a master and a slave and
supports multi-master buses. Standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates from 10
kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also available, allowing implementation of an SMBus-compliant system. The
interface provided to software by the I2C module allows precise timing control of the transmission process and highly automated transfers. Automatic recognition of slave addresses is provided in active and low energy modes.
3.7.4 Peripheral Reflex System (PRS)
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The Peripheral Reflex System provides a communication network between different peripheral modules without software involvement.
Peripheral modules producing Reflex signals are called producers. The PRS routes Reflex signals from producers to consumer peripherals which in turn perform actions in response. Edge triggers and other functionality can be applied by the PRS. The PRS allows peripherals to act autonomously without waking the MCU core, saving power.
3.8 Security Features
3.8.1 GPCRC (General Purpose Cyclic Redundancy Check)
The GPCRC module implements a Cyclic Redundancy Check (CRC) function. It supports both 32-bit and 16-bit polynomials. The supported 32-bit polynomial is 0x04C11DB7 (IEEE 802.3), while the 16-bit polynomial can be programmed to any value, depending on the
needs of the application.
silabs.com | Building a more connected world.
Rev. 1.1 | 11
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
System Overview
3.8.2 Crypto Accelerator (CRYPTO)
The Crypto Accelerator is a fast and energy-efficient autonomous hardware encryption and decryption accelerator. It supports AES encryption and decryption with 128- or 256-bit keys and ECC over both GF(P) and GF(2m), SHA-1 and SHA-2 (SHA-224 and SHA-256).
Supported modes of operation for AES include: ECB, CTR, CBC, PCBC, CFB, OFB, CBC-MAC, GMAC and CCM.
Supported ECC NIST recommended curves include P-192, P-224, P-256, K-163, K-233, B-163 and B-233.
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The CRYPTO is tightly linked to the Radio Buffer Controller (BUFC) enabling fast and efficient autonomous cipher operations on data
buffer content. It allows fast processing of GCM (AES), ECC and SHA with little CPU intervention. CRYPTO also provides trigger signals for DMA read and write operations.
3.9 Analog
3.9.1 Analog Port (APORT)
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The Analog Port (APORT) is an analog interconnect matrix allowing access to analog modules ADC, ACMP, and IDAC on a flexible
selection of pins. Each APORT bus consists of analog switches connected to a common wire. Since many clients can operate differentially, buses are grouped by X/Y pairs.
3.9.2 Analog Comparator (ACMP)
3.9.3 Analog to Digital Converter (ADC)
fo
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The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is higher. Inputs are selected from among internal references and external pins. The tradeoff between response time and current consumption
is configurable by software. Two 6-bit reference dividers allow for a wide range of internally-programmable reference sources. The
ACMP can also be used to monitor the supply voltage. An interrupt can be generated when the supply falls below or rises above the
programmable threshold.
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The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to 1 MSamples/s. The
output sample resolution is configurable and additional resolution is possible using integrated hardware for averaging over multiple
samples. The ADC includes integrated voltage references and an integrated temperature sensor. Inputs are selectable from a wide
range of sources, including pins configurable as either single-ended or differential.
3.9.4 Digital to Analog Current Converter (IDAC)
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The Digital to Analog Current Converter can source or sink a configurable constant current. This current can be driven on an output pin
or routed to the selected ADC input pin for capacitive sensing. The current is programmable between 0.05 µA and 64 µA with several
ranges with various step sizes.
3.10 Reset Management Unit (RMU)
ec
The RMU is responsible for handling reset of the MGM111. A wide range of reset sources are available, including several power supply
monitors, pin reset, software controlled reset, core lockup reset and watchdog reset.
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3.11 Core and Memory
3.11.1 Processor Core
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The ARM Cortex-M4F processor includes a 32-bit RISC processor integrating the following features and tasks in the system:
• ARM Cortex-M4F RISC processor achieving 1.25 Dhrystone MIPS/MHz
• Memory Protection Unit (MPU) supporting up to 8 memory segments
• 256 KB flash program memory
• 32 KB RAM data memory
• Configuration and event handling of all modules
• 2-pin Serial-Wire debug interface
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Rev. 1.1 | 12
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
System Overview
3.11.2 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the microcontroller. The flash memory is readable and writable
from both the Cortex-M and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code
is normally written to the main block, whereas the information block is available for special user data and flash lock bits. There is also a
read-only page in the information block containing system and device calibration data. Read and write operations are supported in energy modes EM0 Active and EM1 Sleep.
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3.11.3 Linked Direct Memory Access Controller (LDMA)
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The Linked Direct Memory Access (LDMA) controller allows the system to perform memory operations independently of software. This
reduces both energy consumption and software workload. The LDMA allows operations to be linked together and staged, enabling sophisticated operations to be implemented.
silabs.com | Building a more connected world.
Rev. 1.1 | 13
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
System Overview
3.12 Memory Map
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The MGM111 memory map is shown in the figures below.
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Figure 3.3. MGM111 Memory Map — Core Peripherals and Code Space
silabs.com | Building a more connected world.
Rev. 1.1 | 14
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
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System Overview
Figure 3.4. MGM111 Memory Map — Peripherals
3.13 Configuration Summary
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The features of the MGM111 are a subset of the feature set described in the EFR32xG1 Wireless Gecko Reference Manual. The Pin
Definitions section describes device specific implementation of the features.
silabs.com | Building a more connected world.
Rev. 1.1 | 15
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Electrical Specifications
4. Electrical Specifications
4.1 Electrical Characteristics
All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:
• Typical values are based on TAMB=25 °C and VDD= 3.3 V, by production test and/or technology characterization.
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• Radio performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output power-specific external RF impedance-matching networks for interfacing to a 50 Ω antenna.
• Minimum and maximum values represent the worst conditions across supply voltage, process variation and operating temperature.
Refer to Table 4.2 General Operating Conditions on page 17 for more details about operational supply and temperature limits.
4.1.1 Absolute Maximum Ratings
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Stresses above those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of
the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and reliability data, see the Quality and Reliability Monitor Report at http://www.silabs.com/support/quality/pages/default.aspx.
Table 4.1. Absolute Maximum Ratings
Symbol
Storage temperature range
TSTG
External main supply voltage VDDMAX
External main supply voltage VDDRAMPMAX
ramp rate
Voltage on non-5V tolerant
GPIO pins
VDIGPIN
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Voltage on any 5V tolerant
GPIO pin1
Test Condition
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Parameter
Min
Typ
Max
Unit
-40
—
+85
°C
0
—
3.8
V
—
—
1
V / μs
-0.3
—
Min of 5.25
and VDD+2
V
-0.3
—
VDD+0.3
V
Input RF level
PRFMAX2G4
—
—
10
dBm
Current per I/O pin (sink)
IIOMAX
—
—
50
mA
—
—
50
mA
—
—
200
mA
—
—
200
mA
Current per I/O pin (source)
IIOALLMAX
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Current for all I/O pins (sink)
Current for all I/O pins
(source)
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Note:
1. When a GPIO pin is routed to the analog module through the APORT, the maximum voltage = VDD.
silabs.com | Building a more connected world.
Rev. 1.1 | 16
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Electrical Specifications
4.1.2 General Operating Conditions
Table 4.2. General Operating Conditions
Symbol
Operating temperature range TOP
VDD supply voltage1
VVDD
Test Condition
Min
Typ
Max
Unit
Ambient Temperature
-40
25
85
°C
DCDC in regulation
2.4
DCDC in bypass, 50mA load
1.85
IVDD
DCDC in bypass
—
HFCLK frequency
fCORE
0 wait-states (MODE = WS0) 2
—
1 wait-states (MODE = WS1) 2
—
3.3
3.8
V
3.3
3.8
V
—
200
mA
—
26
MHz
38.4
40
MHz
D
VDD Current
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Parameter
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Note:
1. The minimum voltage required in bypass mode is calculated using RBYP from the DCDC specification table. Requirements for
other loads can be calculated as VVDD_min+ILOAD * RBYP_max
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2. in MSC_READCTRL register
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Rev. 1.1 | 17
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Electrical Specifications
4.1.3 DC-DC Converter
Test conditions: VDCDC_I=3.3 V, VDCDC_O=1.8 V, IDCDC_LOAD=50 mA, Heavy Drive configuration, FDCDC_LN=7 MHz, unless otherwise
indicated.
Test Condition
Min
Input voltage range
VDCDC_I
Bypass mode, IDCDC_LOAD = 50
mA
1.85
Low noise (LN) mode, 1.8 V output, IDCDC_LOAD = 100 mA, or
Low power (LP) mode, 1.8 V output, IDCDC_LOAD = 10 mA
2.4
Low noise (LN) mode, 1.8 V output, IDCDC_LOAD = 200 mA
Max load current
ILOAD_MAX
Unit
—
VVDD_MAX
V
—
VVDD_MAX
V
2.6
—
VVDD_MAX
V
1.8
—
VVREGVDD
V
Low noise (LN) mode, Heavy
Drive 3
—
—
200
mA
Low noise (LN) mode, Medium
Drive 3
—
—
100
mA
Low noise (LN) mode, Light Drive
—
—
50
mA
Low power (LP) mode,
LPCMPBIAS 2 = 0
—
—
75
μA
Low power (LP) mode,
LPCMPBIAS 2 = 3
—
—
10
mA
m
en
de
d
3
fo
r
VDCDC_O
Max
es
ig
ns
Symbol
N
ew
Parameter
Output voltage programmable range 1
Typ
D
Table 4.3. DC-DC Converter
Note:
1. Due to internal dropout, the DC-DC output will never be able to reach its input voltage, VVDD
N
ot
R
ec
om
2. In EMU_DCDCMISCCTRL register
3. Drive levels are defined by configuration of the PFETCNT and NFETCNT registers. Light Drive: PFETCNT=NFETCNT=3; Medium Drive: PFETCNT=NFETCNT=7; Heavy Drive: PFETCNT=NFETCNT=15.
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MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Electrical Specifications
4.1.4 Current Consumption
4.1.4.1 Current Consumption 3.3 V using DC-DC Converter
Parameter
Symbol
Min
38.4 MHz crystal, CPU running
while loop from flash2
—
38 MHz HFRCO, CPU running
Prime from flash
—
38 MHz HFRCO, CPU running
while loop from flash
—
Typ
Max
Unit
88
—
μA/MHz
63
—
μA/MHz
—
μA/MHz
71
N
ew
Current consumption in EM0 IACTIVE
Active mode with all peripherals disabled, DCDC in Low
Noise DCM mode1.
Test Condition
D
Table 4.4. Current Consumption 3.3V with DC-DC
es
ig
ns
Unless otherwise indicated, typical conditions are: VDD = 3.3 V, DC-DC enabled. TOP = 25 °C. Minimum and maximum values in this
table represent the worst conditions across supply voltage and process variation at TOP = 25 °C.
38 MHz HFRCO, CPU running
CoreMark from flash
—
78
—
μA/MHz
26 MHz HFRCO, CPU running
while loop from flash
—
76
—
μA/MHz
38.4 MHz crystal, CPU running
while loop from flash2
—
98
—
μA/MHz
38 MHz HFRCO, CPU running
Prime from flash
—
75
—
μA/MHz
38 MHz HFRCO, CPU running
while loop from flash
—
81
—
μA/MHz
38 MHz HFRCO, CPU running
CoreMark from flash
—
88
—
μA/MHz
26 MHz HFRCO, CPU running
while loop from flash
—
94
—
μA/MHz
38.4 MHz crystal2
—
49
—
μA/MHz
38 MHz HFRCO
—
32
—
μA/MHz
26 MHz HFRCO
—
38
—
μA/MHz
38.4 MHz crystal2
—
61
—
μA/MHz
38 MHz HFRCO
—
45
—
μA/MHz
26 MHz HFRCO
—
58
—
μA/MHz
Full RAM retention and RTCC
running from LFXO
—
2.5
—
μA
4 kB RAM retention and RTCC
running from LFRCO
—
2.2
—
μA
Current consumption in EM3 IEM3
Stop mode
Full RAM retention and CRYOTIMER running from ULFRCO
—
2.1
—
μA
Current consumption in
EM4H Hibernate mode
128 byte RAM retention, RTCC
running from LFXO
—
0.86
—
μA
128 byte RAM retention, CRYOTIMER running from ULFRCO
—
0.58
—
μA
128 byte RAM retention, no RTCC
—
0.58
—
μA
m
en
de
d
fo
r
Current consumption in EM0
Active mode with all peripherals disabled, DCDC in Low
Noise CCM mode3.
om
Current consumption in EM1 IEM1
Sleep mode with all peripherals disabled, DCDC in Low
Noise DCM mode1.
ec
Current consumption in EM1
Sleep mode with all peripherals disabled, DCDC in Low
Noise CCM mode3.
N
ot
R
Current consumption in EM2 IEM2
Deep Sleep mode. DCDC in
Low Power mode4.
IEM4
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MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Current consumption in
EM4S Shutoff mode
IEM4S
no RAM retention, no RTCC
Min
Typ
Max
Unit
—
0.04
—
μA
es
ig
ns
Note:
1. DCDC Low Noise DCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=3.0 MHz (RCOBAND=0), ANASW=DCDC voltage.
2. CMU_HFXOCTRL_LOWPOWER=0
3. DCDC Low Noise CCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=6.4 MHz (RCOBAND=4), ANASW=DCDC voltage.
4. DCDC Low Power Mode = Medium Drive (PFETCNT=NFETCNT=7), LPOSCDIV=1, LPBIAS=3, LPCILIMSEL=1, ANASW=DCDC
voltage.
4.1.4.2 Current Consumption Using Radio
D
Unless otherwise indicated, typical conditions are: VDD = 3.3 V. TOP = 25 °C. Minimum and maximum values in this table represent the
worst conditions across supply voltage and process variation at TOP = 25 °C.
Symbol
Test Condition
Current consumption in receive mode, active packet
reception (MCU in EM1 @
38.4 MHz, peripheral clocks
disabled)
IRX
Current consumption in
transmit mode (MCU in EM1
@ 38.4 MHz, peripheral
clocks disabled)
ITX
Typ
Max
Unit
1 Mbit/s, 2GFSK, F = 2.4 GHz,
Radio clock prescaled by 4
—
8.7
—
mA
802.15.4 receiving frame, F = 2.4
GHz, Radio clock prescaled by 3
—
9.8
—
mA
F = 2.4 GHz, CW, 0 dBm, Radio
clock prescaled by 3
—
8.2
—
mA
—
32.7
—
mA
Min
Typ
Max
Unit
Code execution from flash
—
10.7
—
μs
Code execution from RAM
—
3
—
μs
Executing from flash
—
3
—
AHB
Clocks
Executing from RAM
—
3
—
AHB
Clocks
Executing from flash
—
10.7
—
μs
Executing from RAM
—
3
—
μs
Executing from flash
—
60
—
μs
—
290
—
μs
m
en
de
d
4.1.5 Wake up times
Min
fo
r
Parameter
N
ew
Table 4.5. Current Consumption 3.3 V with DC-DC
F = 2.4 GHz, CW, 10.5 dBm
Table 4.6. Wake up times
Symbol
om
Parameter
tEM2_WU
Wakeup time from EM1
Sleep
tEM1_WU
R
ec
Wake up from EM2 Deep
Sleep
N
ot
Wake up from EM3 Stop
tEM3_WU
Wake up from EM4H Hibernate1
tEM4H_WU
Wake up from EM4S Shutoff1
tEM4S_WU
Test Condition
Note:
1. Time from wakeup request until first instruction is executed. Wakeup results in device reset.
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MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Electrical Specifications
4.1.6 Brown Out Detector
For the table below, see Figure 3.2 MGM111 Power Block on page 9 to see the internal connection and relation between DVDD and
AVDD. The module itself has only one external power supply input (VDD).
Table 4.7. Brown Out Detector
Test Condition
Min
AVDD BOD threshold
VAVDDBOD
AVDD rising
—
AVDD falling
1.62
Typ
Max
Unit
—
1.85
V
—
—
V
21
—
mV
2.4
—
μs
—
1.7
V
es
ig
ns
Symbol
VAVDDBOD_HYST
—
AVDD response time
tAVDDBOD_DELAY Supply drops at 0.1V/μs rate
—
EM4 BOD threshold
VEM4DBOD
AVDD rising
—
AVDD falling
1.45
—
—
V
—
46
—
mV
—
300
—
μs
Min
Typ
Max
Unit
2400
—
2483.5
MHz
—
—
73
Hz
—
—
1677
kHz
EM4 BOD hysteresis
VEM4BOD_HYST
EM4 response time
tEM4BOD_DELAY
N
ew
AVDD BOD hysteresis
D
Parameter
Supply drops at 0.1V/μs rate
fo
r
4.1.7 Frequency Synthesizer Characteristics
Table 4.8. Frequency Synthesizer Characteristics
Symbol
Test Condition
RF Synthesizer Frequency
range
FRANGE_2400
2.4 GHz frequency range
LO tuning frequency resolution
FRES_2400
2400 - 2483.5 MHz
Maximum frequency deviation
ΔFMAX_2400
N
ot
R
ec
om
m
en
de
d
Parameter
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MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Electrical Specifications
4.1.8 2.4 GHz RF Transceiver Characteristics
4.1.8.1 RF Transmitter General Characteristics for the 2.4 GHz Band
es
ig
ns
Unless otherwise indicated, typical conditions are: TOP = 25 °C, VDD = 3.3 V. RF center frequency 2.45 GHz. Measurements are conducted from the antenna feed point.
Table 4.9. RF Transmitter General Characteristics for 2.4 GHz Band
Symbol
Test Condition
Min
Maximum TX power
POUTMAX
Minimum active TX Power
POUTMIN
CW
Output power step size
POUTSTEP
-5 dBm < Output power < 0 dBm
—
0 dBm < output power <
POUTMAX
—
Max
Unit
+10
—
dBm
-30
—
dBm
1
—
dB
0.5
—
dB
N
ew
—
Typ
D
Parameter
POUTVAR_V
1.85 V < VVDD < 3.3 V using DCDC converter
—
2.2
—
dB
Output power variation vs
temperature at POUTMAX
POUTVAR_T
From -40 to +85 °C, DCDC enabled
—
1.5
—
dB
Output power variation vs RF POUTVAR_F
frequency at POUTMAX
Over RF tuning frequency range
—
0.4
—
dB
2400
—
2483.5
MHz
FRANGE
m
en
de
d
RF tuning frequency range
fo
r
Output power variation vs
supply at POUTMAX
4.1.8.2 RF Receiver General Characteristics for the 2.4 GHz Band
Unless otherwise indicated, typical conditions are: TOP = 25 °C,VDD = 3.3 V. RF center frequency 2.440 GHz. Measurements are conducted from the antenna feed point.
Table 4.10. RF Receiver General Characteristics for 2.4 GHz Band
Symbol
RF tuning frequency range
FRANGE
Receive mode maximum
spurious emission
SPURRX
ec
om
Parameter
Min
Typ
Max
Unit
2400
—
2483.5
MHz
30 MHz to 1 GHz
—
-57
—
dBm
1 GHz to 12 GHz
—
-47
—
dBm
216 MHz to 960 MHz, Conducted
Measurement
—
-55.2
—
dBm
Above 960 MHz, Conducted
Measurement
—
-47.2
—
dBm
N
ot
R
Max spurious emissions dur- SPURRX_FCC
ing active receive mode, per
FCC Part 15.109(a)
Test Condition
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MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Electrical Specifications
4.1.8.3 RF Receiver Characteristics for 802.15.4 O-QPSK DSSS in the 2.4 GHz Band
Unless otherwise indicated, typical conditions are: T=25 °C,VDD = 3.3 V. RF center frequency 2.445 GHz. Meaurements are conducted
from the antenna feed point.
Table 4.11. RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
Test Condition
Min
Max usable receiver input
level, 1% PER
SAT
Signal is reference signal1. Packet
length is 20 octets.
—
Sensitivity, 1% PER
SENS
Signal is reference signal. Packet
length is 20 octets. Using DC-DC
converter.
—
Signal is reference signal. Packet
length is 20 octets. DC-DC converter in bypass mode.
—
Typ
Max
Unit
10
—
dBm
-99
—
dBm
-99
—
dBm
es
ig
ns
Symbol
D
Parameter
CCR
Desired signal 10 dB above sensitivity limit
—
-2.6
—
dB
High-side adjacent channel
rejection, 1% PER. Desired
is reference signal at 3dB
above reference sensitivity
level2
ACR+1
Interferer is reference signal at +1
channel-spacing.
—
33.75
—
dB
Interferer is filtered reference signal3 at +1 channel-spacing.
—
52.2
—
dB
Interferer is CW at +1 channelspacing.4
—
58.6
—
dB
Interferer is reference signal at -1
channel-spacing.
—
35
—
dB
Interferer is filtered reference signal3 at -1 channel-spacing.
—
54.7
—
dB
Interferer is CW at -1 channelspacing.
—
60.1
—
dB
Interferer is reference signal at ±2
channel-spacing
—
45.9
—
dB
Interferer is filtered reference signal3 at ±2 channel-spacing
—
56.8
—
dB
Interferer is CW at ±2 channelspacing
—
65.5
—
dB
Image rejection , 1% PER,
IR
Desired is reference signal at
3dB above reference sensitivity level2
Interferer is CW in image band4
—
49.3
—
dB
Blocking rejection of all other BLOCK
channels. 1% PER, Desired
is reference signal at 3dB
above reference sensitivity
level2. Interferer is reference
signal.
Interferer frequency < Desired frequency - 3 channel-spacing
—
57.2
—
dB
Interferer frequency > Desired frequency + 3 channel-spacing
—
57.9
—
dB
Blocking rejection of 802.11g BLOCK80211G
signal centered at +12MHz
or -13MHz
Desired is reference signal at 6dB
above reference sensitivity level2
—
51.6
—
dB
ACR2
N
ot
R
ec
om
Alternate channel rejection,
1% PER. Desired is reference signal at 3dB above
reference sensitivity level2
fo
r
ACR-1
m
en
de
d
Low-side adjacent channel
rejection, 1% PER. Desired
is reference signal at 3dB
above reference sensitivity
level2
N
ew
Co-channel interferer rejection, 1% PER
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MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Electrical Specifications
Symbol
Min
Typ
Max
Unit
RSSIMAX
Upper limit of input power
range over which RSSI resolution is maintained
5
—
—
dBm
RSSIMIN
Lower limit of input power
range over which RSSI resolution is maintained
—
—
-98
dBm
RSSI resolution
RSSIRES
RSSI accuracy in the linear
region as defined by
802.15.4-2003
RSSILIN
Test Condition
over RSSIMIN to RSSIMAX
—
—
es
ig
ns
Parameter
0.25
—
dB
±1
—
dB
N
ot
R
ec
om
m
en
de
d
fo
r
N
ew
D
Note:
1. Reference signal is defined as O-QPSK DSSS per 802.15.4, Frequency range = 2400-2483.5 MHz, Symbol rate = 62.5 ksymbols/s
2. Reference sensitivity level is -85 dBm
3. Filter is characterized as a symmetric bandpass centered on the adjacent channel having a 3dB bandwidth of 4.6 MHz and stopband rejection better than 26 dB beyond 3.15 MHz from the adjacent carrier.
4. Due to low-IF frequency, there is some overlap of adjacent channel and image channel bands. Adjacent channel CW blocker
tests place the Interferer center frequency at the Desired frequency ±5 MHz on the channel raster, whereas the image rejection
test places the CW interferer near the image frequency of the Desired signal carrier, regardless of the channel raster.
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MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Electrical Specifications
4.1.9 Oscillators
4.1.9.1 LFXO
Table 4.12. LFXO
Symbol
Crystal Frequency
fLFXO
Test Condition
Min
—
Crystal Frequency Tolerance
-100
4.1.9.2 HFXO
Symbol
Crystal Frequency
fHFXO
Test Condition
Crystal Frequency Tolerance
Unit
32.768
—
kHz
+100
ppm
Min
Typ
Max
Unit
—
38.4
—
MHz
+40
ppm
N
ew
Parameter
Max
D
Table 4.13. HFXO
Typ
es
ig
ns
Parameter
-40
fo
r
4.1.9.3 LFRCO
Table 4.14. LFRCO
Symbol
Test Condition
Min
Typ
Max
Unit
Oscillation frequency
fLFRCO
ENVREF = 1 in
CMU_LFRCOCTRL
30.474
32.768
34.243
kHz
ENVREF = 0 in
CMU_LFRCOCTRL
30.474
32.768
33.915
kHz
—
500
—
μs
ENVREF = 1 in
CMU_LFRCOCTRL
—
342
—
nA
ENVREF = 0 in
CMU_LFRCOCTRL
—
494
—
nA
m
en
de
d
Parameter
tLFRCO
Current consumption 1
ILFRCO
om
Startup time
N
ot
R
ec
Note:
1. Block is supplied by VDD if ANASW = 0, or DCDC if ANASW=1 in EMU_PWRCTRL register
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MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Electrical Specifications
4.1.9.4 HFRCO and AUXHFRCO
Table 4.15. HFRCO and AUXHFRCO
Symbol
Test Condition
Min
Typ
Max
Unit
Frequency Accuracy
fHFRCO
Any frequency band, across supply voltage and temperature
-2.5
—
2.5
%
Start-up time
tHFRCO
fHFRCO ≥ 19 MHz
—
4 < fHFRCO < 19 MHz
—
fHFRCO ≤ 4 MHz
—
fHFRCO = 38 MHz
—
fHFRCO = 32 MHz
—
fHFRCO = 26 MHz
—
fHFRCO = 19 MHz
—
μs
204
228
μA
171
190
μA
147
164
μA
110
120
μA
—
100
110
μA
—
81
91
μA
fHFRCO = 4 MHz
—
33
35
μA
fHFRCO = 2 MHz
—
31
35
μA
fHFRCO = 1 MHz
—
30
35
μA
Coarse (% of period)
—
0.8
—
%
Fine (% of period)
—
0.1
—
%
—
0.2
—
% RMS
Min
Typ
Max
Unit
0.95
1
1.07
kHz
fo
r
fULFRCO
Table 4.16. ULFRCO
Test Condition
N
ot
R
ec
Oscillation frequency
Symbol
2.5
—
m
en
de
d
om
Parameter
μs
μA
PJHFRCO
4.1.9.5 ULFRCO
—
138
fHFRCO = 7 MHz
Period Jitter
1
126
fHFRCO = 13 MHz
SSHFRCO
ns
—
fHFRCO = 16 MHz
Step size
—
D
IHFRCO
300
N
ew
Current consumption on all
supplies
es
ig
ns
Parameter
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MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Electrical Specifications
4.1.10 Flash Memory Characteristics
Table 4.17. Flash Memory Characteristics1
Flash erase cycles before
failure
ECFLASH
Flash data retention
RETFLASH
10
Word (32-bit) programming
time
tW_PROG
20
Page erase time
tPERASE
20
Mass erase time
tMERASE
20
Device erase time2
tDERASE
Page erase current3
IERASE
Mass or Device erase current3
IWRITE
Write current3
Min
Typ
Max
Unit
10000
—
—
cycles
—
—
years
26
40
μs
27
40
ms
27
40
ms
—
60
74
ms
—
—
3
mA
—
—
5
mA
—
—
3
mA
N
ew
Test Condition
es
ig
ns
Symbol
D
Parameter
N
ot
R
ec
om
m
en
de
d
fo
r
Note:
1. Flash data retention information is published in the Quarterly Quality and Reliability Report.
2. Device erase is issued over the AAP interface and erases all flash, SRAM, the Lock Bit (LB) page, and the User data page Lock
Word (ULW)
3. Measured at 25°C
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MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Electrical Specifications
4.1.11 GPIO
Table 4.18. GPIO
Input low voltage
Test Condition
Min
Typ
Max
Unit
VIOIL
—
—
VDD*0.3
V
Input high voltage
VIOIH
VDD*0.7
Output high voltage relative
to VDD
VIOOH
Sourcing 3 mA, VDD ≥ 3 V,
VDD*0.8
DRIVESTRENGTH1 = WEAK
Sourcing 1.2 mA, VDD ≥ 1.62 V
VDD*0.6
DRIVESTRENGTH1 = WEAK
Sourcing 20 mA, VDD ≥ 3 V,
VDD*0.8
—
—
V
—
—
V
—
—
V
—
V
—
N
ew
DRIVESTRENGTH1 = STRONG
es
ig
ns
Symbol
D
Parameter
Sourcing 8 mA, VDD ≥ 1.62 V
VDD*0.6
—
—
V
—
—
VDD*0.2
V
—
—
VDD*0.4
V
—
—
VDD*0.2
V
—
—
VDD*0.4
V
All GPIO except LFXO pins, GPIO
≤ VDD
—
0.1
30
nA
LFXO Pins, GPIO ≤ VDD
—
0.1
50
nA
VDD < GPIO ≤ VDD + 2 V
—
3.3
15
μA
30
43
65
kΩ
30
43
65
kΩ
20
25
35
ns
—
1.8
—
ns
—
4.5
—
ns
DRIVESTRENGTH1 = STRONG
Sinking 3 mA, VDD ≥ 3 V,
DRIVESTRENGTH1 = WEAK
fo
r
Output low voltage relative to VIOOL
VDD
Sinking 1.2 mA, VDD ≥ 1.62 V
DRIVESTRENGTH1 = WEAK
m
en
de
d
Sinking 20 mA, VDD ≥ 3 V,
DRIVESTRENGTH1 = STRONG
Sinking 8 mA, VDD ≥ 1.62 V
DRIVESTRENGTH1 = STRONG
IIOLEAK
om
Input leakage current
I5VTOLLEAK
I/O pin pull-up resistor
RPU
ec
Input leakage current on
5VTOL pads above VDD
I/O pin pull-down resistor
RPD
R
Pulse width of pulses retIOGLITCH
moved by the glitch suppression filter
N
ot
Output fall time, From 70%
to 30% of VIO
tIOOF
CL = 50 pF,
DRIVESTRENGTH1 = STRONG,
SLEWRATE1 = 0x6
CL = 50 pF,
DRIVESTRENGTH1 = WEAK,
SLEWRATE1 = 0x6
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MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Output rise time, From 30%
to 70% of VIO
tIOOR
CL = 50 pF,
Min
Typ
Max
Unit
—
2.2
—
ns
—
7.4
—
ns
DRIVESTRENGTH1 = STRONG,
CL = 50 pF,
DRIVESTRENGTH1 = WEAK,
SLEWRATE1 = 0x6
RESETn low time to ensure
pin reset
TRESET
100
—
—
ns
4.1.12 VMON
N
ew
D
Note:
1. In GPIO_Pn_CTRL register
es
ig
ns
SLEWRATE = 0x61
Table 4.19. VMON
Symbol
Test Condition
VMON Supply Current
IVMON
Typ
Max
Unit
In EM0 or EM1, 1 supply monitored
—
5.8
8.26
μA
In EM0 or EM1, 4 supplies monitored
—
11.8
16.8
μA
In EM2, EM3 or EM4, 1 supply
monitored
—
62
—
nA
In EM2, EM3 or EM4, 4 supplies
monitored
—
99
—
nA
In EM0 or EM1
—
2
—
μA
In EM2, EM3 or EM4
—
2
—
nA
1.62
—
3.4
V
Coarse
—
200
—
mV
Fine
—
20
—
mV
Supply drops at 1V/μs rate
—
460
—
ns
—
26
—
mV
m
en
de
d
VMON Loading of Monitored ISENSE
Supply
VVMON_RANGE
om
Threshold range
Threshold step size
NVMON_STESP
tVMON_RES
ec
Response time
Min
fo
r
Parameter
VVMON_HYST
N
ot
R
Hysteresis
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MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Electrical Specifications
4.1.13 ADC
Table 4.20. ADC
Resolution
VRESOLUTION
Input voltage range
VADCIN
Test Condition
Single ended
Min
Typ
Max
Unit
6
—
12
Bits
0
Differential
-VREF
Input range of external refer- VADCREFIN_P
ence voltage, single ended
and differential
1
PSRRADC
At DC
—
Analog input common mode
rejection ratio
CMRRADC
At DC
—
1 Msps / 16 MHz ADCCLK,
2*VREF
V
—
VREF
V
—
VAVDD
V
80
—
dB
—
dB
80
—
301
350
μA
—
149
—
μA
—
91
—
μA
—
51
—
μA
—
9
—
μA
—
117
—
μA
—
79
—
μA
—
345
—
μA
250 ksps / 4 MHz ADCCLK, BIASPROG = 6, GPBIASACC = 0 3
—
191
—
μA
62.5 ksps / 1 MHz ADCCLK,
—
132
—
μA
BIASPROG = 0, GPBIASACC = 1
3
250 ksps / 4 MHz ADCCLK, BIASPROG = 6, GPBIASACC = 1 3
fo
r
Current from all supplies, us- IADC_CONTIing internal reference buffer. NOUS_LP
Continous operation. WARMUPMODE2 = KEEPADCWARM
—
N
ew
Power supply rejection1
es
ig
ns
Symbol
D
Parameter
62.5 ksps / 1 MHz ADCCLK,
m
en
de
d
BIASPROG = 15, GPBIASACC =
13
Current from all supplies, us- IADC_NORMAL_LP 35 ksps / 16 MHz ADCCLK,
ing internal reference buffer.
BIASPROG = 0, GPBIASACC = 1
Duty-cycled operation. WAR3
2
MUPMODE = NORMAL
5 ksps / 16 MHz ADCCLK
BIASPROG = 0, GPBIASACC = 1
3
ec
om
Current from all supplies, us- IADC_STANDing internal reference buffer. BY_LP
Duty-cycled operation.
AWARMUPMODE2 = KEEPINSTANDBY or KEEPINSLOWACC
N
ot
R
Current from all supplies, us- IADC_CONTIing internal reference buffer. NOUS_HP
Continous operation. WARMUPMODE2 = KEEPADCWARM
125 ksps / 16 MHz ADCCLK,
BIASPROG = 0, GPBIASACC = 1
3
35 ksps / 16 MHz ADCCLK,
BIASPROG = 0, GPBIASACC = 1
3
1 Msps / 16 MHz ADCCLK,
BIASPROG = 0, GPBIASACC = 0
3
BIASPROG = 15, GPBIASACC =
03
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Rev. 1.1 | 30
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Electrical Specifications
Symbol
Test Condition
Current from all supplies, us- IADC_NORMAL_HP 35 ksps / 16 MHz ADCCLK,
ing internal reference buffer.
BIASPROG = 0, GPBIASACC = 0
Duty-cycled operation. WAR3
2
MUPMODE = NORMAL
5 ksps / 16 MHz ADCCLK
Min
Typ
Max
Unit
—
102
—
μA
—
17
—
μA
BIASPROG = 0, GPBIASACC = 0
3
Current from all supplies, us- IADC_STANDing internal reference buffer. BY_HP
Duty-cycled operation.
AWARMUPMODE2 = KEEPINSTANDBY or KEEPINSLOWACC
125 ksps / 16 MHz ADCCLK,
—
BIASPROG = 0, GPBIASACC = 0
3
35 ksps / 16 MHz ADCCLK,
—
3
ADC Clock Frequency
fADCCLK
Throughput rate
fADCRATE
Conversion time4
tADCCONV
HFPERCLK = 16 MHz
SNDRADC
—
μA
—
μA
—
—
16
MHz
—
—
1
Msps
—
7
—
cycles
—
9
—
cycles
—
13
—
cycles
—
—
5
μs
WARMUPMODE2 = KEEPINSTANDBY
—
—
2
μs
WARMUPMODE2 = KEEPINSLOWACC
—
—
1
μs
Internal reference, 2.5 V full-scale,
differential (-1.25, 1.25)
58
67
—
dB
vrefp_in = 1.25 V direct mode with
2.5 V full-scale, differential
—
68
—
dB
6 bit
WARMUPMODE2 = NORMAL
m
en
de
d
SNDR at 1Msps and fin =
10kHz
123
140
12 bit
tADCSTART
μA
—
8 bit
Startup time of reference
generator and ADC core
—
N
ew
IADC_CLK
fo
r
Current from HFPERCLK
162
D
BIASPROG = 0, GPBIASACC = 0
es
ig
ns
Parameter
SFDRADC
1 MSamples/s, 10 kHz full-scale
sine wave
—
75
—
dB
Input referred ADC noise,
rms
VREF_NOISE
Including quantization noise and
distortion
—
380
—
μV
Offset Error
VADCOFFSETERR
-3
0.25
3
LSB
Gain error in ADC
VADC_GAIN
Using internal reference
—
-0.2
5
%
Using external reference
—
-1
—
%
R
ec
om
Spurious-Free Dynamic
Range (SFDR)
DNLADC
12 bit resolution
-1
—
2
LSB
Integral non-linearity (INL),
End point method
INLADC
12 bit resolution
-6
—
6
LSB
Temperature Sensor Slope
VTS_SLOPE
—
-1.84
—
mV/°C
N
ot
Differential non-linearity
(DNL)
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MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
N
ot
R
ec
om
m
en
de
d
fo
r
N
ew
D
es
ig
ns
Note:
1. PSRR is referenced to AVDD when ANASW=0 and to DVDD when ANASW=1 in EMU_PWRCTRL
2. In ADCn_CNTL register
3. In ADCn_BIASPROG register
4. Derived from ADCCLK
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Rev. 1.1 | 32
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Electrical Specifications
4.1.14 IDAC
Table 4.21. IDAC
NIDAC_RANGES
Output Current
IIDAC_OUT
Linear steps within each
range
NIDAC_STEPS
Step size
SSIDAC
—
4
—
-
1.6
RANGSEL1 = RANGE2
0.5
RANGSEL1 = RANGE3
2
—
—
RANGSEL1 = RANGE0
—
1.6
μA
—
4.7
μA
—
16
μA
—
64
μA
32
—
—
nA
50
—
100
—
nA
—
500
—
nA
—
2
—
μA
EM0 or EM1, AVDD=3.3 V, T = 25
°C
-2
—
2
%
EM0 or EM1
-18
—
22
%
EM2 or EM3, Source mode,
RANGSEL1 = RANGE0,
AVDD=3.3 V, T = 25 °C
—
-2
—
%
EM2 or EM3, Source mode,
RANGSEL1 = RANGE1,
AVDD=3.3 V, T = 25 °C
—
-1.7
—
%
EM2 or EM3, Source mode,
RANGSEL1 = RANGE2,
AVDD=3.3 V, T = 25 °C
—
-0.8
—
%
EM2 or EM3, Source mode,
RANGSEL1 = RANGE3,
AVDD=3.3 V, T = 25 °C
—
-0.5
—
%
EM2 or EM3, Sink mode, RANGSEL1 = RANGE0, AVDD=3.3 V, T
= 25 °C
—
-0.7
—
%
EM2 or EM3, Sink mode, RANGSEL1 = RANGE1, AVDD=3.3 V, T
= 25 °C
—
-0.6
—
%
EM2 or EM3, Sink mode, RANGSEL1 = RANGE2, AVDD=3.3 V, T
= 25 °C
—
-0.5
—
%
EM2 or EM3, Sink mode, RANGSEL1 = RANGE3, AVDD=3.3 V, T
= 25 °C
—
-0.5
—
%
Output within 1% of steady state
value
—
5
—
μs
fo
r
m
en
de
d
om
ec
R
N
ot
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Unit
RANGSEL1 = RANGE1
RANGSEL1 = RANGE3
tIDAC_SU
Max
0.05
RANGSEL1 = RANGE2
Start up time
Typ
RANGSEL1 = RANGE0
RANGSEL1 = RANGE1
Total Accuracy, STEPSEL1 = ACCIDAC
0x10
Min
es
ig
ns
Number of Ranges
Test Condition
D
Symbol
N
ew
Parameter
Rev. 1.1 | 33
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Range setting is changed
—
5
—
μs
Step value is changed
—
1
—
μs
Current consumption in EM0 IIDAC
or EM1 2
Source mode, excluding output
current
—
8.9
13
μA
Sink mode, excluding output current
—
12
16
μA
Source mode, excluding output
current, duty cycle mode, T = 25
°C
—
1.04
—
μA
Sink mode, excluding output current, duty cycle mode, T = 25 °C
—
1.08
—
μA
Source mode, excluding output
current, duty cycle mode, T ≥ 85
°C
—
8.9
—
μA
—
12
—
μA
RANGESEL1=0, output voltage =
min(VIOVDD, VAVDD2-100 mv)
—
0.04
—
%
RANGESEL1=1, output voltage =
min(VIOVDD, VAVDD2-100 mV)
—
0.02
—
%
RANGESEL1=2, output voltage =
min(VIOVDD, VAVDD2-150 mV)
—
0.02
—
%
RANGESEL1=3, output voltage =
min(VIOVDD, VAVDD2-250 mV)
—
0.02
—
%
RANGESEL1=0, output voltage =
100 mV
—
0.18
—
%
RANGESEL1=1, output voltage =
100 mV
—
0.12
—
%
RANGESEL1=2, output voltage =
150 mV
—
0.08
—
%
RANGESEL1=3, output voltage =
250 mV
—
0.02
—
%
m
en
de
d
om
Output voltage compliance in ICOMP_SINK
sink mode, sink current
change relative to current
sunk at IOVDD
D
Sink mode, excluding output current, duty cycle mode, T ≥ 85 °C
fo
r
Output voltage compliance in ICOMP_SRC
source mode, source current
change relative to current
sourced at 0 V
N
ew
Current consumption in EM2
or EM32
es
ig
ns
Settling time, (output settled tIDAC_SETTLE
within 1% of steady state value)
N
ot
R
ec
Note:
1. In IDAC_CURPROG register
2. The IDAC is supplied by either AVDD, DVDD, or IOVDD based on the setting of ANASW in the EMU_PWRCTRL register and
PWRSEL in the IDAC_CTRL register. Setting PWRSEL to 1 selects IOVDD. With PWRSEL cleared to 0, ANASW selects between AVDD (0) and DVDD (1).
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Rev. 1.1 | 34
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Electrical Specifications
4.1.15 Analog Comparator (ACMP)
Table 4.22. ACMP
Test Condition
Input voltage range
VACMPIN
CMPVDD =
ACMPn_CTRL_PWRSEL 1
Supply Voltage
VACMPVDD
BIASPROG2 ≤ 0x10 or FULLBIAS2 = 0
1.85
0x10 < BIASPROG2 ≤ 0x20 and
FULLBIAS2 = 1
2.1
BIASPROG2 = 0x10, FULLBIAS2
=0
—
BIASPROG2 = 0x20, FULLBIAS2
=1
—
VLP selected as input using 2.5 V
Reference / 4 (0.625 V)
—
VLP selected as input using VDD
VBDIV selected as input using
1.25 V reference / 1
Current consumption of inter- IACMPREF
nal voltage reference
om
ec
R
N
ot
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0
—
CMPVDD
V
V
—
VVDD_MAX
V
306
—
nA
95
μA
50
—
nA
—
20
—
nA
—
4.1
—
μA
—
2.4
—
μA
HYSTSEL3 = HYST0
-1.75
0
1.75
mV
HYSTSEL3 = HYST1
10
18
26
mV
HYSTSEL3 = HYST2
21
32
46
mV
HYSTSEL3 = HYST3
27
44
63
mV
HYSTSEL3 = HYST4
32
55
80
mV
HYSTSEL3 = HYST5
38
65
100
mV
HYSTSEL3 = HYST6
43
77
121
mV
HYSTSEL3 = HYST7
47
86
148
mV
HYSTSEL3 = HYST8
-4
0
4
mV
HYSTSEL3 = HYST9
-27
-18
-10
mV
HYSTSEL3 = HYST10
-47
-32
-18
mV
HYSTSEL3 = HYST11
-64
-43
-27
mV
HYSTSEL3 = HYST12
-78
-54
-32
mV
HYSTSEL3 = HYST13
-93
-64
-37
mV
HYSTSEL3 = HYST14
-113
-74
-42
mV
HYSTSEL3 = HYST15
-135
-85
-47
mV
m
en
de
d
VACMPHYST
Unit
VVDD_MAX
VADIV selected as input using
VDD/1
Hysteresis (VCM = 1.25 V,
BIASPROG2 = 0x10, FULLBIAS2 = 1)
Max
74
N
ew
IACMP
Typ
—
fo
r
Active current not including
voltage reference
Min
es
ig
ns
Symbol
D
Parameter
Rev. 1.1 | 35
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Electrical Specifications
Test Condition
Min
Typ
Max
Unit
Comparator delay4
tACMPDELAY
BIASPROG2 = 0x10, FULLBIAS2
=0
—
3.7
—
μs
BIASPROG2 = 0x20, FULLBIAS2
=1
—
35
—
ns
-35
—
35
mV
VACMPOFFSET
BIASPROG2 =0x10, FULLBIAS2
=1
Reference Voltage
VACMPREF
Internal 1.25 V reference
1
Internal 2.5 V reference
2
CSRESSEL5 = 0
—
CSRESSEL5 = 1
—
CSRESSEL5 = 2
—
CSRESSEL5 = 3
—
Capacitive Sense Internal
Resistance
RCSRES
CSRESSEL5 = 4
CSRESSEL5 = 5
CSRESSEL5 = 6
1.47
V
2.5
2.8
V
inf
—
kΩ
15
—
kΩ
27
—
kΩ
39
—
kΩ
—
51
—
kΩ
—
102
—
kΩ
—
164
—
kΩ
—
239
—
kΩ
fo
r
CSRESSEL5 = 7
1.25
N
ew
Offset voltage
es
ig
ns
Symbol
D
Parameter
m
en
de
d
Note:
1. CMPVDD is a supply chosen by the setting in ACMPn_CTRL_PWRSEL and may be VDD or DCDC.
2. In ACMPn_CTRL register.
3. In ACMPn_HYSTERESIS register.
4. ±100 mV differential drive.
5. In ACMPn_INPUTSEL register.
The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference as given as:
IACMPTOTAL = IACMP + IACMPREF
N
ot
R
ec
om
IACMPREF is zero if an external voltage reference is used.
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MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Electrical Specifications
4.1.16 I2C
I2C Standard-mode (Sm)
Table 4.23. I2C Standard-mode (Sm)1
SCL clock frequency2
fSCL
0
SCL clock low time
tLOW
4.7
SCL clock high time
tHIGH
4
SDA set-up time
tSU,DAT
250
SDA hold time3
tHD,DAT
100
Repeated START condition
set-up time
tSU,STA
4.7
(Repeated) START condition tHD,STA
hold time
tSU,STO
Bus free time between a
STOP and START condition
tBUF
Typ
Max
Unit
—
100
kHz
—
—
μs
—
—
μs
—
—
ns
—
3450
ns
—
—
μs
4
—
—
μs
4
—
—
μs
4.7
—
—
μs
fo
r
STOP condition set-up time
Min
es
ig
ns
Test Condition
D
Symbol
N
ew
Parameter
N
ot
R
ec
om
m
en
de
d
Note:
1. For CLHR set to 0 in the I2Cn_CTRL register
2. For the minimum HFPERCLK frequency required in Standard-mode, refer to the I2C chapter in the reference manual
3. The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW)
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Rev. 1.1 | 37
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Electrical Specifications
I2C Fast-mode (Fm)
Table 4.24. I2C Fast-mode (Fm)1
Min
Typ
Max
Unit
fSCL
0
—
400
kHz
SCL clock low time
tLOW
1.3
SCL clock high time
tHIGH
0.6
SDA set-up time
tSU,DAT
100
SDA hold time3
tHD,DAT
100
Repeated START condition
set-up time
tSU,STA
0.6
(Repeated) START condition tHD,STA
hold time
0.6
STOP condition set-up time
tSU,STO
Bus free time between a
STOP and START condition
tBUF
es
ig
ns
SCL clock frequency2
Test Condition
—
—
μs
—
—
μs
—
—
ns
—
900
ns
—
—
μs
D
Symbol
—
μs
—
N
ew
Parameter
0.6
—
—
μs
1.3
—
—
μs
N
ot
R
ec
om
m
en
de
d
fo
r
Note:
1. For CLHR set to 1 in the I2Cn_CTRL register
2. For the minimum HFPERCLK frequency required in Fast-mode, refer to the I2C chapter in the reference manual
3. The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW)
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MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Electrical Specifications
I2C Fast-mode Plus (Fm+)
Table 4.25. I2C Fast-mode Plus (Fm+)1
Min
Typ
Max
Unit
fSCL
0
—
1000
kHz
SCL clock low time
tLOW
0.5
SCL clock high time
tHIGH
0.26
SDA set-up time
tSU,DAT
50
SDA hold time
tHD,DAT
100
Repeated START condition
set-up time
tSU,STA
0.26
(Repeated) START condition tHD,STA
hold time
0.26
STOP condition set-up time
tSU,STO
Bus free time between a
STOP and START condition
tBUF
es
ig
ns
SCL clock frequency2
Test Condition
—
—
μs
—
—
μs
—
—
ns
—
—
ns
—
—
μs
D
Symbol
—
μs
—
N
ew
Parameter
0.26
—
—
μs
0.5
—
—
μs
N
ot
R
ec
om
m
en
de
d
fo
r
Note:
1. For CLHR set to 0 or 1 in the I2Cn_CTRL register
2. For the minimum HFPERCLK frequency required in Fast-mode Plus, refer to the I2C chapter in the reference manual
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Rev. 1.1 | 39
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Electrical Specifications
4.1.17 USART SPI
SPI Master Timing
Symbol
Test Condition
Min
SCLK period 1 2
tSCLK
CS to MOSI 1 2
tCS_MO
0
SCLK to MOSI 1 2
tSCLK_MO
3
MISO setup time 1 2
tSU_MI
MISO hold time 1 2
tH_MI
Typ
Max
Unit
—
—
ns
—
8
ns
—
20
ns
—
—
ns
—
ns
2*
tHFPERCLK
VDD = 3.0 V
37
6
es
ig
ns
Parameter
D
Table 4.26. SPI Master Timing
—
N
ew
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0)
2. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD)
CS
fo
r
tCS_MO
tSCKL_MO
SCLK
CLKPOL = 0
m
en
de
d
tSCLK
SCLK
CLKPOL = 1
MOSI
tH_MI
tSU_MI
MISO
om
Figure 4.1. SPI Master Timing Diagram (SMSDELAY = 0)
ec
CS
tCS_MO
tSCLK_MO
SCLK
N
ot
R
CLKPOL = 0
tSCLK
SCLK
CLKPOL = 1
MOSI
tSU_MI
tH_MI
MISO
Figure 4.2. SPI Master Timing Diagram (SMSDELAY = 1)
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Rev. 1.1 | 40
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Electrical Specifications
SPI Slave Timing
Table 4.27. SPI Slave Timing
Min
Typ
Max
Unit
tSCLK_sl
2*
tHFPERCLK
—
—
ns
SCLK high period1 2
tSCLK_hi
3*
tHFPERCLK
SCLK low period 1 2
tSCLK_lo
3*
tHFPERCLK
CS active to MISO 1 2
tCS_ACT_MI
4
CS disable to MISO 1 2
tCS_DIS_MI
4
MOSI setup time 1 2
tSU_MO
4
MOSI hold time 1 2
tH_MO
SCLK to MISO 1 2
tSCLK_MI
es
ig
ns
SCKL period 1 2
Test Condition
—
—
ns
—
—
ns
—
50
ns
—
50
ns
—
—
ns
D
Symbol
N
ew
Parameter
3+2*
tHFPERCLK
—
—
ns
16 +
tHFPERCLK
—
66 + 2 *
tHFPERCLK
ns
CS
SCLK
CLKPOL = 0
SCLK
CLKPOL = 1
tCS_ACT_MI
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MOSI
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Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0)
2. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD)
tSCLK_HI
tSU_MO
tCS_DIS_MI
tSCLK_LO
tSCLK
tH_MO
tSCLK_MI
Figure 4.3. SPI Slave Timing Diagram
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MISO
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Rev. 1.1 | 41
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Typical Connection Diagrams
5. Typical Connection Diagrams
5.1 Network Co-Processor (NCP) Application with UART Host
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The MGM111 can be controlled over the UART interface as a peripheral to an external host processor. Typical power supply, programming/debug, and host interface connections are shown in the figure below. Refer to AN958: Debugging and Programming Interfaces for
Custom Designs for more details.
Figure 5.1. Connection Diagram: UART NCP Configuration
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5.2 Network Co-Processor (NCP) Application with SPI Host
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The MGM111 can be controlled over the SPI interface as a peripheral to an external host processor. Typical power supply, programming/debug and host interface connections are shown in the figure below. Refer to AN958: Debugging and Programming Interfaces for
Custom Designs for more details.
Figure 5.2. Connection Diagram: SPI NCP Configuration
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MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Typical Connection Diagrams
5.3 SoC Application
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The MGM111 can be used in a standalone SoC configuration with no external host processor. Typical power supply and programming/
debug connections are shown in the figure below. Refer to AN958: Debugging and Programming Interfaces for Custom Designs for
more details. Refer to AN772: Using the Application Bootloader for recommendations on supported serial flash ICs (optional).
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Figure 5.3. Connection Diagram: SoC Configuration
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Rev. 1.1 | 43
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Layout Guidelines
6. Layout Guidelines
For optimal performance of the MGM111A (with intergrated antenna), please follow the PCB layout guidelines and ground plane recommendations indicated in this section.
6.1 Module Placement and Application PCB Layout Guidelines
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Place the module at the edge of the PCB, as shown in the figure below.
Do not place any metal (traces, components, battery, etc.) within the clearance area of the antenna (shown in the figure below).
Connect all ground pads directly to a solid ground plane.
Place the ground vias as close to the ground pads as possible.
Do not place plastic or any other dielectric material in touch with the antenna.
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•
•
•
•
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Figure 6.1. Recommended Application PCB Layout for MGM111A
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Rev. 1.1 | 44
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Layout Guidelines
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The layouts in the next figure will result in severely degraded RF-performance.
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Figure 6.2. Non-optimal Module Placements for MGM111A
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Figure 6.3. Impact of GND Plane Size vs. Range for MGM111A
R
6.2 Effect of Plastic and Metal Materials
Do not place plastic or any other dielectric material in closs proximity to the antenna.
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Any metallic objects in close proximity to the antenna will prevent the antenna from radiating freely. The minimum recommended distance of metallic and/or conductive objects is 10 mm in any direction from the antenna except in the directions of the application PCB
ground planes.
6.3 Locating the Module Close to Human Body
Placing the module in touch or very close to the human body will negatively impact antenna efficiency and reduce range.
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Rev. 1.1 | 45
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Layout Guidelines
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6.4 2D Radiation Pattern Plots
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Figure 6.4. Typical 2D Radiation Pattern – Front View
Figure 6.5. Typical 2D Radiation Pattern – Side View
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Rev. 1.1 | 46
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
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Layout Guidelines
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Figure 6.6. Typical 2D Radiation Pattern – Top View
silabs.com | Building a more connected world.
Rev. 1.1 | 47
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Hardware Design Guidelines
7. Hardware Design Guidelines
The MGM111 is an easy-to-use module with regard to hardware application design but certain design guidelines must be followed to
guarantee optimal performance. These guidelines are listed in the next sub-sections.
7.1 Power Supply Requirements
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Coin cell batteries cannot withstand high peak currents (e.g. higher than 15 mA). If the peak current exceeds 15 mA it’s recommended
to place 47 - 100 µF capacitor in parallel with the coin cell battery to improve the battery life time. Notice that the total current consumption of your application is a combination of the radio, peripherals and MCU current consumption so you must take all of these into account. MGM111 should be powered by a unipolar supply voltage with nominal value of 3.3 V.
7.2 Reset Functions
D
The MGM111 can be reset by three different methods: by pulling the RESET line low, by the internal watchdog timer or software command. The reset state in MGM111 does not provide any power saving functionality and thus is not recommended as a means to conserve power. MGM111 has an internal system power-up reset function. The RESET pin includes an on-chip pull-up resistor and can
therefore be left unconnected if no external reset switch or source is needed.
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7.3 Debug and Firmware Updates
This section contains information on debug and firmware update methods. For additional information, refer to the following application
note: AN958: Debugging and Programming Interfaces for Custom Designs.
7.3.1 JTAG
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It is recommended to expose the JTAG debug pins in your own hardware design for firmware update and debug purposes. The following table lists the required pins for JTAG connection.
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The debug pins have pull-down and pull-up enabled by default, so leaving them enabled may increase current consumption if left connected to supply or ground. If enabling the JTAG pins the module must be power cycled to enable a SWD debug session.
Table 7.1. JTAG Pads
PAD NAME PAD NUMBER JTAG SIGNAL NAME COMMENTS
24
TDI
This pin is disabled after reset. Once enabled the pin has a built-in pull-up.
PF2
23
TDO
This pin is disabled after reset
PF1
22
TMS
Pin is enabled after reset and has a built-in pull-up
PF0
21
TCK
Pin is enabled after reset and has a built-in pull-down
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PF3
7.3.2 Packet Trace Interface (PTI)
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The MGM111 integrates a true PHY-level PTI with the MAC, allowing complete, non-intrusive capture of all packets to and from the
EFR32 Wireless STK development tools.
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Rev. 1.1 | 48
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Pin Definitions
8. Pin Definitions
8.1 Pin Definitions
GND
MGM111
GND
31
2
PD13
TOP VIEW
RESETn
30
3
PD14
VDD
4
PD15
PF7
5
PA0
PF6
6
PA1
PF5
7
PA2
PF4
8
PA3
PF3
24
9
PA4
PF2
23
10
PA5
11
PB11
12
GND
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1
29
28
27
26
PC6
PC7
PC8
PC9
PC10
PC11
13
14
15
16
17 18
19
PF1
22
PF0
21
GND
20
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PB13
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Figure 8.1. MGM111 Pinout
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Rev. 1.1 | 49
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Pin Definitions
Table 8.1. Device Pinout
MGM111
BUSCY [ADC0:
APORT3YCH5
ACMP0:
APORT3YCH5
ACMP1:
APORT3YCH5
IDAC0:
APORT1YCH5]
BUSCX [ADC0:
APORT3XCH6
ACMP0:
APORT3XCH6
ACMP1:
APORT3XCH6
IDAC0:
APORT1XCH6]
BUSDY [ADC0:
APORT4YCH6
ACMP0:
APORT4YCH6
ACMP1:
APORT4YCH6]
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BUSCY [ADC0:
APORT3YCH7
ACMP0:
APORT3YCH7
ACMP1:
APORT3YCH7
IDAC0:
APORT1YCH7]
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PD15
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4
TIM0_CC0 #21
TIM0_CC1 #20
TIM0_CC2 #19
TIM0_CDTI0 #18
TIM0_CDTI1 #17
TIM0_CDTI2 #16
TIM1_CC0 #21
TIM1_CC1 #20
TIM1_CC2 #19
TIM1_CC3 #18 LETIM0_OUT0 #21
LETIM0_OUT1 #20
PCNT0_S0IN #21
PCNT0_S1IN #20
US0_TX #21
US0_RX #20
US0_CLK #19
US0_CS #18
US0_CTS #17
US0_RTS #16
US1_TX #21
US1_RX #20
US1_CLK #19
US1_CS #18
US1_CTS #17
US1_RTS #16
LEU0_TX #21
LEU0_RX #20
I2C0_SDA #21
I2C0_SCL #20
FRC_DCLK #21
FRC_DOUT #20
FRC_DFRAME #19
MODEM_DCLK
#21 MODEM_DIN
#20 MODEM_DOUT #19
MODEM_ANT0
#18 MODEM_ANT1 #17
PRS_CH3 #12
PRS_CH4 #4
PRS_CH5 #3
PRS_CH6 #15
ACMP0_O #21
ACMP1_O #21
TIM0_CC0 #22
TIM0_CC1 #21
TIM0_CC2 #20
TIM0_CDTI0 #19
TIM0_CDTI1 #18
TIM0_CDTI2 #17
TIM1_CC0 #22
TIM1_CC1 #21
TIM1_CC2 #20
TIM1_CC3 #19 LETIM0_OUT0 #22
LETIM0_OUT1 #21
PCNT0_S0IN #22
PCNT0_S1IN #21
US0_TX #22
US0_RX #21
US0_CLK #20
US0_CS #19
US0_CTS #18
US0_RTS #17
US1_TX #22
US1_RX #21
US1_CLK #20
US1_CS #19
US1_CTS #18
US1_RTS #17
LEU0_TX #22
LEU0_RX #21
I2C0_SDA #22
I2C0_SCL #21
FRC_DCLK #22
FRC_DOUT #21
FRC_DFRAME #20
MODEM_DCLK
#22 MODEM_DIN
#21 MODEM_DOUT #20
MODEM_ANT0
#19 MODEM_ANT1 #18
CMU_CLK0 #5
PRS_CH3 #13
PRS_CH4 #5
PRS_CH5 #4
PRS_CH6 #16
ACMP0_O #22
ACMP1_O #22
GPIO_EM4WU4
TIM0_CC0 #23
TIM0_CC1 #22
TIM0_CC2 #21
TIM0_CDTI0 #20
TIM0_CDTI1 #19
TIM0_CDTI2 #18
TIM1_CC0 #23
TIM1_CC1 #22
TIM1_CC2 #21
TIM1_CC3 #20 LETIM0_OUT0 #23
LETIM0_OUT1 #22
PCNT0_S0IN #23
PCNT0_S1IN #22
US0_TX #23
US0_RX #22
US0_CLK #21
US0_CS #20
US0_CTS #19
US0_RTS #18
US1_TX #23
US1_RX #22
US1_CLK #21
US1_CS #20
US1_CTS #19
US1_RTS #18
LEU0_TX #23
LEU0_RX #22
I2C0_SDA #23
I2C0_SCL #22
FRC_DCLK #23
FRC_DOUT #22
FRC_DFRAME #21
MODEM_DCLK
#23 MODEM_DIN
#22 MODEM_DOUT #21
MODEM_ANT0
#20 MODEM_ANT1 #19
CMU_CLK1 #5
PRS_CH3 #14
PRS_CH4 #6
PRS_CH5 #5
PRS_CH6 #17
ACMP0_O #23
ACMP1_O #23
DBG_SWO #2
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PD14
Radio
Other
Ground
BUSDX [ADC0:
APORT4XCH5
ACMP0:
APORT4XCH5
ACMP1:
APORT4XCH5]
3
Communication
BUSDX [ADC0:
APORT4XCH7
ACMP0:
APORT4XCH7
ACMP1:
APORT4XCH7]
silabs.com | Building a more connected world.
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PD13
Timers
D
2
GND
Analog
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Pin #
Pin Alternate Functionality / Description
Rev. 1.1 | 50
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Pin Definitions
Analog
Timers
Communication
Radio
Other
TIM0_CC0 #0
TIM0_CC1 #31
TIM0_CC2 #30
TIM0_CDTI0 #29
TIM0_CDTI1 #28
TIM0_CDTI2 #27
TIM1_CC0 #0
TIM1_CC1 #31
TIM1_CC2 #30
TIM1_CC3 #29 LETIM0_OUT0 #0 LETIM0_OUT1 #31
PCNT0_S0IN #0
PCNT0_S1IN #31
US0_TX #0
US0_RX #31
US0_CLK #30
US0_CS #29
US0_CTS #28
US0_RTS #27
US1_TX #0
US1_RX #31
US1_CLK #30
US1_CS #29
US1_CTS #28
US1_RTS #27
LEU0_TX #0
LEU0_RX #31
I2C0_SDA #0
I2C0_SCL #31
FRC_DCLK #0
FRC_DOUT #31
FRC_DFRAME #30
MODEM_DCLK #0
MODEM_DIN #31
MODEM_DOUT
#30 MODEM_ANT0 #29
MODEM_ANT1
#28
CMU_CLK1 #0
PRS_CH6 #0
PRS_CH7 #10
PRS_CH8 #9
PRS_CH9 #8
ACMP0_O #0
ACMP1_O #0
TIM0_CC0 #1
TIM0_CC1 #0
TIM0_CC2 #31
TIM0_CDTI0 #30
TIM0_CDTI1 #29
TIM0_CDTI2 #28
TIM1_CC0 #1
TIM1_CC1 #0
TIM1_CC2 #31
TIM1_CC3 #30 LETIM0_OUT0 #1 LETIM0_OUT1 #0
PCNT0_S0IN #1
PCNT0_S1IN #0
US0_TX #1
US0_RX #0
US0_CLK #31
US0_CS #30
US0_CTS #29
US0_RTS #28
US1_TX #1
US1_RX #0
US1_CLK #31
US1_CS #30
US1_CTS #29
US1_RTS #28
LEU0_TX #1
LEU0_RX #0
I2C0_SDA #1
I2C0_SCL #0
FRC_DCLK #1
FRC_DOUT #0
FRC_DFRAME #31
MODEM_DCLK #1
MODEM_DIN #0
MODEM_DOUT
#31 MODEM_ANT0 #30
MODEM_ANT1
#29
CMU_CLK0 #0
PRS_CH6 #1
PRS_CH7 #0
PRS_CH8 #10
PRS_CH9 #9
ACMP0_O #1
ACMP1_O #1
TIM0_CC0 #2
TIM0_CC1 #1
TIM0_CC2 #0
TIM0_CDTI0 #31
TIM0_CDTI1 #30
TIM0_CDTI2 #29
TIM1_CC0 #2
TIM1_CC1 #1
TIM1_CC2 #0
TIM1_CC3 #31 LETIM0_OUT0 #2 LETIM0_OUT1 #1
PCNT0_S0IN #2
PCNT0_S1IN #1
US0_TX #2
US0_RX #1
US0_CLK #0
US0_CS #31
US0_CTS #30
US0_RTS #29
US1_TX #2
US1_RX #1
US1_CLK #0
US1_CS #31
US1_CTS #30
US1_RTS #29
LEU0_TX #2
LEU0_RX #1
I2C0_SDA #2
I2C0_SCL #1
FRC_DCLK #2
FRC_DOUT #1
FRC_DFRAME #0
MODEM_DCLK #2
MODEM_DIN #1
MODEM_DOUT #0
MODEM_ANT0
#31 MODEM_ANT1 #30
PRS_CH6 #2
PRS_CH7 #1
PRS_CH8 #0
PRS_CH9 #10
ACMP0_O #2
ACMP1_O #2
ADC0_EXTN
5
PA0
BUSCX [ADC0:
APORT3XCH8
ACMP0:
APORT3XCH8
ACMP1:
APORT3XCH8
IDAC0:
APORT1XCH8]
BUSDY [ADC0:
APORT4YCH8
ACMP0:
APORT4YCH8
ACMP1:
APORT4YCH8]
6
PA1
BUSCY [ADC0:
APORT3YCH9
ACMP0:
APORT3YCH9
ACMP1:
APORT3YCH9
IDAC0:
APORT1YCH9]
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BUSDX [ADC0:
APORT4XCH9
ACMP0:
APORT4XCH9
ACMP1:
APORT4XCH9]
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BUSCX [ADC0:
APORT3XCH10
ACMP0:
APORT3XCH10
ACMP1:
APORT3XCH10
IDAC0:
APORT1XCH10]
PA2
BUSDY [ADC0:
APORT4YCH10
ACMP0:
APORT4YCH10
ACMP1:
APORT4YCH10]
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Pin Name
D
Pin #
Pin Alternate Functionality / Description
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MGM111
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Rev. 1.1 | 51
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Pin Definitions
MGM111
Analog
Timers
Communication
Radio
Other
PA3
BUSCY [ADC0:
APORT3YCH11
ACMP0:
APORT3YCH11
ACMP1:
APORT3YCH11
IDAC0:
APORT1YCH11]
TIM0_CC0 #3
TIM0_CC1 #2
TIM0_CC2 #1
TIM0_CDTI0 #0
TIM0_CDTI1 #31
TIM0_CDTI2 #30
TIM1_CC0 #3
TIM1_CC1 #2
TIM1_CC2 #1
TIM1_CC3 #0 LETIM0_OUT0 #3 LETIM0_OUT1 #2
PCNT0_S0IN #3
PCNT0_S1IN #2
US0_TX #3
US0_RX #2
US0_CLK #1
US0_CS #0
US0_CTS #31
US0_RTS #30
US1_TX #3
US1_RX #2
US1_CLK #1
US1_CS #0
US1_CTS #31
US1_RTS #30
LEU0_TX #3
LEU0_RX #2
I2C0_SDA #3
I2C0_SCL #2
FRC_DCLK #3
FRC_DOUT #2
FRC_DFRAME #1
MODEM_DCLK #3
MODEM_DIN #2
MODEM_DOUT #1
MODEM_ANT0 #0
MODEM_ANT1
#31
PRS_CH6 #3
PRS_CH7 #2
PRS_CH8 #1
PRS_CH9 #0
ACMP0_O #3
ACMP1_O #3
GPIO_EM4WU8
TIM0_CC0 #4
TIM0_CC1 #3
TIM0_CC2 #2
TIM0_CDTI0 #1
TIM0_CDTI1 #0
TIM0_CDTI2 #31
TIM1_CC0 #4
TIM1_CC1 #3
TIM1_CC2 #2
TIM1_CC3 #1 LETIM0_OUT0 #4 LETIM0_OUT1 #3
PCNT0_S0IN #4
PCNT0_S1IN #3
US0_TX #4
US0_RX #3
US0_CLK #2
US0_CS #1
US0_CTS #0
US0_RTS #31
US1_TX #4
US1_RX #3
US1_CLK #2
US1_CS #1
US1_CTS #0
US1_RTS #31
LEU0_TX #4
LEU0_RX #3
I2C0_SDA #4
I2C0_SCL #3
FRC_DCLK #4
FRC_DOUT #3
FRC_DFRAME #2
MODEM_DCLK #4
MODEM_DIN #3
MODEM_DOUT #2
MODEM_ANT0 #1
MODEM_ANT1 #0
PRS_CH6 #4
PRS_CH7 #3
PRS_CH8 #2
PRS_CH9 #1
ACMP0_O #4
ACMP1_O #4
TIM0_CC0 #5
TIM0_CC1 #4
TIM0_CC2 #3
TIM0_CDTI0 #2
TIM0_CDTI1 #1
TIM0_CDTI2 #0
TIM1_CC0 #5
TIM1_CC1 #4
TIM1_CC2 #3
TIM1_CC3 #2 LETIM0_OUT0 #5 LETIM0_OUT1 #4
PCNT0_S0IN #5
PCNT0_S1IN #4
US0_TX #5
US0_RX #4
US0_CLK #3
US0_CS #2
US0_CTS #1
US0_RTS #0
US1_TX #5
US1_RX #4
US1_CLK #3
US1_CS #2
US1_CTS #1
US1_RTS #0
LEU0_TX #5
LEU0_RX #4
I2C0_SDA #5
I2C0_SCL #4
FRC_DCLK #5
FRC_DOUT #4
FRC_DFRAME #3
MODEM_DCLK #5
MODEM_DIN #4
MODEM_DOUT #3
MODEM_ANT0 #2
MODEM_ANT1 #1
PRS_CH6 #5
PRS_CH7 #4
PRS_CH8 #3
PRS_CH9 #2
ACMP0_O #5
ACMP1_O #5
9
PA4
BUSCX [ADC0:
APORT3XCH12
ACMP0:
APORT3XCH12
ACMP1:
APORT3XCH12
IDAC0:
APORT1XCH12]
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BUSDY [ADC0:
APORT4YCH12
ACMP0:
APORT4YCH12
ACMP1:
APORT4YCH12]
om
BUSCY [ADC0:
APORT3YCH13
ACMP0:
APORT3YCH13
ACMP1:
APORT3YCH13
IDAC0:
APORT1YCH13]
PA5
BUSDX [ADC0:
APORT4XCH13
ACMP0:
APORT4XCH13
ACMP1:
APORT4XCH13]
N
ot
R
ec
10
D
BUSDX [ADC0:
APORT4XCH11
ACMP0:
APORT4XCH11
ACMP1:
APORT4XCH11]
N
ew
8
es
ig
ns
Pin Name
fo
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Pin #
Pin Alternate Functionality / Description
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Rev. 1.1 | 52
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Pin Definitions
MGM111
Timers
Communication
Radio
Other
PB11
BUSCY [ADC0:
APORT3YCH27
ACMP0:
APORT3YCH27
ACMP1:
APORT3YCH27
IDAC0:
APORT1YCH27]
TIM0_CC0 #6
TIM0_CC1 #5
TIM0_CC2 #4
TIM0_CDTI0 #3
TIM0_CDTI1 #2
TIM0_CDTI2 #1
TIM1_CC0 #6
TIM1_CC1 #5
TIM1_CC2 #4
TIM1_CC3 #3 LETIM0_OUT0 #6 LETIM0_OUT1 #5
PCNT0_S0IN #6
PCNT0_S1IN #5
US0_TX #6
US0_RX #5
US0_CLK #4
US0_CS #3
US0_CTS #2
US0_RTS #1
US1_TX #6
US1_RX #5
US1_CLK #4
US1_CS #3
US1_CTS #2
US1_RTS #1
LEU0_TX #6
LEU0_RX #5
I2C0_SDA #6
I2C0_SCL #5
FRC_DCLK #6
FRC_DOUT #5
FRC_DFRAME #4
MODEM_DCLK #6
MODEM_DIN #5
MODEM_DOUT #4
MODEM_ANT0 #3
MODEM_ANT1 #2
PRS_CH6 #6
PRS_CH7 #5
PRS_CH8 #4
PRS_CH9 #3
ACMP0_O #6
ACMP1_O #6
TIM0_CC0 #8
TIM0_CC1 #7
TIM0_CC2 #6
TIM0_CDTI0 #5
TIM0_CDTI1 #4
TIM0_CDTI2 #3
TIM1_CC0 #8
TIM1_CC1 #7
TIM1_CC2 #6
TIM1_CC3 #5 LETIM0_OUT0 #8 LETIM0_OUT1 #7
PCNT0_S0IN #8
PCNT0_S1IN #7
US0_TX #8
US0_RX #7
US0_CLK #6
US0_CS #5
US0_CTS #4
US0_RTS #3
US1_TX #8
US1_RX #7
US1_CLK #6
US1_CS #5
US1_CTS #4
US1_RTS #3
LEU0_TX #8
LEU0_RX #7
I2C0_SDA #8
I2C0_SCL #7
FRC_DCLK #8
FRC_DOUT #7
FRC_DFRAME #6
MODEM_DCLK #8
MODEM_DIN #7
MODEM_DOUT #6
MODEM_ANT0 #5
MODEM_ANT1 #4
PRS_CH6 #8
PRS_CH7 #7
PRS_CH8 #6
PRS_CH9 #5
ACMP0_O #8
ACMP1_O #8
DBG_SWO #1
GPIO_EM4WU9
TIM0_CC0 #11
TIM0_CC1 #10
TIM0_CC2 #9
TIM0_CDTI0 #8
TIM0_CDTI1 #7
TIM0_CDTI2 #6
TIM1_CC0 #11
TIM1_CC1 #10
TIM1_CC2 #9
TIM1_CC3 #8 LETIM0_OUT0 #11
LETIM0_OUT1 #10
PCNT0_S0IN #11
PCNT0_S1IN #10
US0_TX #11
US0_RX #10
US0_CLK #9
US0_CS #8
US0_CTS #7
US0_RTS #6
US1_TX #11
US1_RX #10
US1_CLK #9
US1_CS #8
US1_CTS #7
US1_RTS #6
LEU0_TX #11
LEU0_RX #10
I2C0_SDA #11
I2C0_SCL #10
FRC_DCLK #11
FRC_DOUT #10
FRC_DFRAME #9
MODEM_DCLK
#11 MODEM_DIN
#10 MODEM_DOUT #9
MODEM_ANT0 #8
MODEM_ANT1 #7
CMU_CLK0 #2
PRS_CH0 #8
PRS_CH9 #11
PRS_CH10 #0
PRS_CH11 #5
ACMP0_O #11
ACMP1_O #11
12
13
GND
PB13
Ground
BUSCY [ADC0:
APORT3YCH29
ACMP0:
APORT3YCH29
ACMP1:
APORT3YCH29
IDAC0:
APORT1YCH29]
m
en
de
d
BUSDX [ADC0:
APORT4XCH29
ACMP0:
APORT4XCH29
ACMP1:
APORT4XCH29]
om
BUSAX [ADC0:
APORT1XCH6
ACMP0:
APORT1XCH6
ACMP1:
APORT1XCH6]
PC6
BUSBY [ADC0:
APORT2YCH6
ACMP0:
APORT2YCH6
ACMP1:
APORT2YCH6]
N
ot
R
ec
14
D
BUSDX [ADC0:
APORT4XCH27
ACMP0:
APORT4XCH27
ACMP1:
APORT4XCH27]
es
ig
ns
Analog
N
ew
11
Pin Name
fo
r
Pin #
Pin Alternate Functionality / Description
silabs.com | Building a more connected world.
Rev. 1.1 | 53
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Pin Definitions
PC7
PC8
BUSBX [ADC0:
APORT2XCH7
ACMP0:
APORT2XCH7
ACMP1:
APORT2XCH7]
BUSAX [ADC0:
APORT1XCH8
ACMP0:
APORT1XCH8
ACMP1:
APORT1XCH8]
BUSBY [ADC0:
APORT2YCH8
ACMP0:
APORT2YCH8
ACMP1:
APORT2YCH8]
Communication
Radio
Other
TIM0_CC0 #12
TIM0_CC1 #11
TIM0_CC2 #10
TIM0_CDTI0 #9
TIM0_CDTI1 #8
TIM0_CDTI2 #7
TIM1_CC0 #12
TIM1_CC1 #11
TIM1_CC2 #10
TIM1_CC3 #9 LETIM0_OUT0 #12
LETIM0_OUT1 #11
PCNT0_S0IN #12
PCNT0_S1IN #11
US0_TX #12
US0_RX #11
US0_CLK #10
US0_CS #9
US0_CTS #8
US0_RTS #7
US1_TX #12
US1_RX #11
US1_CLK #10
US1_CS #9
US1_CTS #8
US1_RTS #7
LEU0_TX #12
LEU0_RX #11
I2C0_SDA #12
I2C0_SCL #11
FRC_DCLK #12
FRC_DOUT #11
FRC_DFRAME #10
MODEM_DCLK
#12 MODEM_DIN
#11 MODEM_DOUT #10
MODEM_ANT0 #9
MODEM_ANT1 #8
CMU_CLK1 #2
PRS_CH0 #9
PRS_CH9 #12
PRS_CH10 #1
PRS_CH11 #0
ACMP0_O #12
ACMP1_O #12
TIM0_CC0 #13
TIM0_CC1 #12
TIM0_CC2 #11
TIM0_CDTI0 #10
TIM0_CDTI1 #9
TIM0_CDTI2 #8
TIM1_CC0 #13
TIM1_CC1 #12
TIM1_CC2 #11
TIM1_CC3 #10 LETIM0_OUT0 #13
LETIM0_OUT1 #12
PCNT0_S0IN #13
PCNT0_S1IN #12
US0_TX #13
US0_RX #12
US0_CLK #11
US0_CS #10
US0_CTS #9
US0_RTS #8
US1_TX #13
US1_RX #12
US1_CLK #11
US1_CS #10
US1_CTS #9
US1_RTS #8
LEU0_TX #13
LEU0_RX #12
I2C0_SDA #13
I2C0_SCL #12
FRC_DCLK #13
FRC_DOUT #12
FRC_DFRAME #11
MODEM_DCLK
#13 MODEM_DIN
#12 MODEM_DOUT #11
MODEM_ANT0
#10 MODEM_ANT1 #9
PRS_CH0 #10
PRS_CH9 #13
PRS_CH10 #2
PRS_CH11 #1
ACMP0_O #13
ACMP1_O #13
TIM0_CC0 #14
TIM0_CC1 #13
TIM0_CC2 #12
TIM0_CDTI0 #11
TIM0_CDTI1 #10
TIM0_CDTI2 #9
TIM1_CC0 #14
TIM1_CC1 #13
TIM1_CC2 #12
TIM1_CC3 #11 LETIM0_OUT0 #14
LETIM0_OUT1 #13
PCNT0_S0IN #14
PCNT0_S1IN #13
US0_TX #14
US0_RX #13
US0_CLK #12
US0_CS #11
US0_CTS #10
US0_RTS #9
US1_TX #14
US1_RX #13
US1_CLK #12
US1_CS #11
US1_CTS #10
US1_RTS #9
LEU0_TX #14
LEU0_RX #13
I2C0_SDA #14
I2C0_SCL #13
FRC_DCLK #14
FRC_DOUT #13
FRC_DFRAME #12
MODEM_DCLK
#14 MODEM_DIN
#13 MODEM_DOUT #12
MODEM_ANT0
#11 MODEM_ANT1 #10
PRS_CH0 #11
PRS_CH9 #14
PRS_CH10 #3
PRS_CH11 #2
ACMP0_O #14
ACMP1_O #14
m
en
de
d
16
BUSAY [ADC0:
APORT1YCH7
ACMP0:
APORT1YCH7
ACMP1:
APORT1YCH7]
Timers
om
BUSAY [ADC0:
APORT1YCH9
ACMP0:
APORT1YCH9
ACMP1:
APORT1YCH9]
PC9
BUSBX [ADC0:
APORT2XCH9
ACMP0:
APORT2XCH9
ACMP1:
APORT2XCH9]
N
ot
R
ec
17
es
ig
ns
15
Analog
D
Pin Name
N
ew
Pin #
Pin Alternate Functionality / Description
fo
r
MGM111
silabs.com | Building a more connected world.
Rev. 1.1 | 54
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Pin Definitions
PC11
20
GND
BUSAY [ADC0:
APORT1YCH11
ACMP0:
APORT1YCH11
ACMP1:
APORT1YCH11]
BUSBX [ADC0:
APORT2XCH11
ACMP0:
APORT2XCH11
ACMP1:
APORT2XCH11]
PF0
Other
TIM0_CC0 #15
TIM0_CC1 #14
TIM0_CC2 #13
TIM0_CDTI0 #12
TIM0_CDTI1 #11
TIM0_CDTI2 #10
TIM1_CC0 #15
TIM1_CC1 #14
TIM1_CC2 #13
TIM1_CC3 #12 LETIM0_OUT0 #15
LETIM0_OUT1 #14
PCNT0_S0IN #15
PCNT0_S1IN #14
US0_TX #15
US0_RX #14
US0_CLK #13
US0_CS #12
US0_CTS #11
US0_RTS #10
US1_TX #15
US1_RX #14
US1_CLK #13
US1_CS #12
US1_CTS #11
US1_RTS #10
LEU0_TX #15
LEU0_RX #14
I2C0_SDA #15
I2C0_SCL #14
FRC_DCLK #15
FRC_DOUT #14
FRC_DFRAME #13
MODEM_DCLK
#15 MODEM_DIN
#14 MODEM_DOUT #13
MODEM_ANT0
#12 MODEM_ANT1 #11
CMU_CLK1 #3
PRS_CH0 #12
PRS_CH9 #15
PRS_CH10 #4
PRS_CH11 #3
ACMP0_O #15
ACMP1_O #15
GPIO_EM4WU12
TIM0_CC0 #16
TIM0_CC1 #15
TIM0_CC2 #14
TIM0_CDTI0 #13
TIM0_CDTI1 #12
TIM0_CDTI2 #11
TIM1_CC0 #16
TIM1_CC1 #15
TIM1_CC2 #14
TIM1_CC3 #13 LETIM0_OUT0 #16
LETIM0_OUT1 #15
PCNT0_S0IN #16
PCNT0_S1IN #15
US0_TX #16
US0_RX #15
US0_CLK #14
US0_CS #13
US0_CTS #12
US0_RTS #11
US1_TX #16
US1_RX #15
US1_CLK #14
US1_CS #13
US1_CTS #12
US1_RTS #11
LEU0_TX #16
LEU0_RX #15
I2C0_SDA #16
I2C0_SCL #15
FRC_DCLK #16
FRC_DOUT #15
FRC_DFRAME #14
MODEM_DCLK
#16 MODEM_DIN
#15 MODEM_DOUT #14
MODEM_ANT0
#13 MODEM_ANT1 #12
CMU_CLK0 #3
PRS_CH0 #13
PRS_CH9 #16
PRS_CH10 #5
PRS_CH11 #4
ACMP0_O #16
ACMP1_O #16
DBG_SWO #3
TIM0_CC0 #24
TIM0_CC1 #23
TIM0_CC2 #22
TIM0_CDTI0 #21
TIM0_CDTI1 #20
TIM0_CDTI2 #19
TIM1_CC0 #24
TIM1_CC1 #23
TIM1_CC2 #22
TIM1_CC3 #21 LETIM0_OUT0 #24
LETIM0_OUT1 #23
PCNT0_S0IN #24
PCNT0_S1IN #23
US0_TX #24
US0_RX #23
US0_CLK #22
US0_CS #21
US0_CTS #20
US0_RTS #19
US1_TX #24
US1_RX #23
US1_CLK #22
US1_CS #21
US1_CTS #20
US1_RTS #19
LEU0_TX #24
LEU0_RX #23
I2C0_SDA #24
I2C0_SCL #23
BUSAX [ADC0:
APORT1XCH16
ACMP0:
APORT1XCH16
ACMP1:
APORT1XCH16]
FRC_DCLK #24
FRC_DOUT #23
FRC_DFRAME #22
MODEM_DCLK
#24 MODEM_DIN
#23 MODEM_DOUT #22
MODEM_ANT0
#21 MODEM_ANT1 #20
PRS_CH0 #0
PRS_CH1 #7
PRS_CH2 #6
PRS_CH3 #5
ACMP0_O #24
ACMP1_O #24
DBG_SWCLKTCK
#0
BUSBY [ADC0:
APORT2YCH16
ACMP0:
APORT2YCH16
ACMP1:
APORT2YCH16]
N
ot
R
Radio
Ground
ec
21
Communication
es
ig
ns
BUSBY [ADC0:
APORT2YCH10
ACMP0:
APORT2YCH10
ACMP1:
APORT2YCH10]
om
19
BUSAX [ADC0:
APORT1XCH10
ACMP0:
APORT1XCH10
ACMP1:
APORT1XCH10]
Timers
D
PC10
Analog
N
ew
18
Pin Name
m
en
de
d
Pin #
Pin Alternate Functionality / Description
fo
r
MGM111
silabs.com | Building a more connected world.
Rev. 1.1 | 55
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Pin Definitions
PF1
PF2
BUSBX [ADC0:
APORT2XCH17
ACMP0:
APORT2XCH17
ACMP1:
APORT2XCH17]
BUSAX [ADC0:
APORT1XCH18
ACMP0:
APORT1XCH18
ACMP1:
APORT1XCH18]
BUSBY [ADC0:
APORT2YCH18
ACMP0:
APORT2YCH18
ACMP1:
APORT2YCH18]
Communication
Radio
Other
TIM0_CC0 #25
TIM0_CC1 #24
TIM0_CC2 #23
TIM0_CDTI0 #22
TIM0_CDTI1 #21
TIM0_CDTI2 #20
TIM1_CC0 #25
TIM1_CC1 #24
TIM1_CC2 #23
TIM1_CC3 #22 LETIM0_OUT0 #25
LETIM0_OUT1 #24
PCNT0_S0IN #25
PCNT0_S1IN #24
US0_TX #25
US0_RX #24
US0_CLK #23
US0_CS #22
US0_CTS #21
US0_RTS #20
US1_TX #25
US1_RX #24
US1_CLK #23
US1_CS #22
US1_CTS #21
US1_RTS #20
LEU0_TX #25
LEU0_RX #24
I2C0_SDA #25
I2C0_SCL #24
FRC_DCLK #25
FRC_DOUT #24
FRC_DFRAME #23
MODEM_DCLK
#25 MODEM_DIN
#24 MODEM_DOUT #23
MODEM_ANT0
#22 MODEM_ANT1 #21
PRS_CH0 #1
PRS_CH1 #0
PRS_CH2 #7
PRS_CH3 #6
ACMP0_O #25
ACMP1_O #25
DBG_SWDIOTMS
#0
TIM0_CC0 #26
TIM0_CC1 #25
TIM0_CC2 #24
TIM0_CDTI0 #23
TIM0_CDTI1 #22
TIM0_CDTI2 #21
TIM1_CC0 #26
TIM1_CC1 #25
TIM1_CC2 #24
TIM1_CC3 #23 LETIM0_OUT0 #26
LETIM0_OUT1 #25
PCNT0_S0IN #26
PCNT0_S1IN #25
US0_TX #26
US0_RX #25
US0_CLK #24
US0_CS #23
US0_CTS #22
US0_RTS #21
US1_TX #26
US1_RX #25
US1_CLK #24
US1_CS #23
US1_CTS #22
US1_RTS #21
LEU0_TX #26
LEU0_RX #25
I2C0_SDA #26
I2C0_SCL #25
FRC_DCLK #26
FRC_DOUT #25
FRC_DFRAME #24
MODEM_DCLK
#26 MODEM_DIN
#25 MODEM_DOUT #24
MODEM_ANT0
#23 MODEM_ANT1 #22
CMU_CLK0 #6
PRS_CH0 #2
PRS_CH1 #1
PRS_CH2 #0
PRS_CH3 #7
ACMP0_O #26
ACMP1_O #26
DBG_TDO #0
DBG_SWO #0
GPIO_EM4WU0
TIM0_CC0 #27
TIM0_CC1 #26
TIM0_CC2 #25
TIM0_CDTI0 #24
TIM0_CDTI1 #23
TIM0_CDTI2 #22
TIM1_CC0 #27
TIM1_CC1 #26
TIM1_CC2 #25
TIM1_CC3 #24 LETIM0_OUT0 #27
LETIM0_OUT1 #26
PCNT0_S0IN #27
PCNT0_S1IN #26
US0_TX #27
US0_RX #26
US0_CLK #25
US0_CS #24
US0_CTS #23
US0_RTS #22
US1_TX #27
US1_RX #26
US1_CLK #25
US1_CS #24
US1_CTS #23
US1_RTS #22
LEU0_TX #27
LEU0_RX #26
I2C0_SDA #27
I2C0_SCL #26
FRC_DCLK #27
FRC_DOUT #26
FRC_DFRAME #25
MODEM_DCLK
#27 MODEM_DIN
#26 MODEM_DOUT #25
MODEM_ANT0
#24 MODEM_ANT1 #23
CMU_CLK1 #6
PRS_CH0 #3
PRS_CH1 #2
PRS_CH2 #1
PRS_CH3 #0
ACMP0_O #27
ACMP1_O #27
DBG_TDI #0
m
en
de
d
23
BUSAY [ADC0:
APORT1YCH17
ACMP0:
APORT1YCH17
ACMP1:
APORT1YCH17]
Timers
om
BUSAY [ADC0:
APORT1YCH19
ACMP0:
APORT1YCH19
ACMP1:
APORT1YCH19]
PF3
BUSBX [ADC0:
APORT2XCH19
ACMP0:
APORT2XCH19
ACMP1:
APORT2XCH19]
N
ot
R
ec
24
es
ig
ns
22
Analog
D
Pin Name
N
ew
Pin #
Pin Alternate Functionality / Description
fo
r
MGM111
silabs.com | Building a more connected world.
Rev. 1.1 | 56
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Pin Definitions
PF4
PF5
BUSBY [ADC0:
APORT2YCH20
ACMP0:
APORT2YCH20
ACMP1:
APORT2YCH20]
BUSAY [ADC0:
APORT1YCH21
ACMP0:
APORT1YCH21
ACMP1:
APORT1YCH21]
BUSBX [ADC0:
APORT2XCH21
ACMP0:
APORT2XCH21
ACMP1:
APORT2XCH21]
Communication
Radio
Other
TIM0_CC0 #28
TIM0_CC1 #27
TIM0_CC2 #26
TIM0_CDTI0 #25
TIM0_CDTI1 #24
TIM0_CDTI2 #23
TIM1_CC0 #28
TIM1_CC1 #27
TIM1_CC2 #26
TIM1_CC3 #25 LETIM0_OUT0 #28
LETIM0_OUT1 #27
PCNT0_S0IN #28
PCNT0_S1IN #27
US0_TX #28
US0_RX #27
US0_CLK #26
US0_CS #25
US0_CTS #24
US0_RTS #23
US1_TX #28
US1_RX #27
US1_CLK #26
US1_CS #25
US1_CTS #24
US1_RTS #23
LEU0_TX #28
LEU0_RX #27
I2C0_SDA #28
I2C0_SCL #27
FRC_DCLK #28
FRC_DOUT #27
FRC_DFRAME #26
MODEM_DCLK
#28 MODEM_DIN
#27 MODEM_DOUT #26
MODEM_ANT0
#25 MODEM_ANT1 #24
PRS_CH0 #4
PRS_CH1 #3
PRS_CH2 #2
PRS_CH3 #1
ACMP0_O #28
ACMP1_O #28
TIM0_CC0 #29
TIM0_CC1 #28
TIM0_CC2 #27
TIM0_CDTI0 #26
TIM0_CDTI1 #25
TIM0_CDTI2 #24
TIM1_CC0 #29
TIM1_CC1 #28
TIM1_CC2 #27
TIM1_CC3 #26 LETIM0_OUT0 #29
LETIM0_OUT1 #28
PCNT0_S0IN #29
PCNT0_S1IN #28
US0_TX #29
US0_RX #28
US0_CLK #27
US0_CS #26
US0_CTS #25
US0_RTS #24
US1_TX #29
US1_RX #28
US1_CLK #27
US1_CS #26
US1_CTS #25
US1_RTS #24
LEU0_TX #29
LEU0_RX #28
I2C0_SDA #29
I2C0_SCL #28
FRC_DCLK #29
FRC_DOUT #28
FRC_DFRAME #27
MODEM_DCLK
#29 MODEM_DIN
#28 MODEM_DOUT #27
MODEM_ANT0
#26 MODEM_ANT1 #25
PRS_CH0 #5
PRS_CH1 #4
PRS_CH2 #3
PRS_CH3 #2
ACMP0_O #29
ACMP1_O #29
TIM0_CC0 #30
TIM0_CC1 #29
TIM0_CC2 #28
TIM0_CDTI0 #27
TIM0_CDTI1 #26
TIM0_CDTI2 #25
TIM1_CC0 #30
TIM1_CC1 #29
TIM1_CC2 #28
TIM1_CC3 #27 LETIM0_OUT0 #30
LETIM0_OUT1 #29
PCNT0_S0IN #30
PCNT0_S1IN #29
US0_TX #30
US0_RX #29
US0_CLK #28
US0_CS #27
US0_CTS #26
US0_RTS #25
US1_TX #30
US1_RX #29
US1_CLK #28
US1_CS #27
US1_CTS #26
US1_RTS #25
LEU0_TX #30
LEU0_RX #29
I2C0_SDA #30
I2C0_SCL #29
FRC_DCLK #30
FRC_DOUT #29
FRC_DFRAME #28
MODEM_DCLK
#30 MODEM_DIN
#29 MODEM_DOUT #28
MODEM_ANT0
#27 MODEM_ANT1 #26
CMU_CLK1 #7
PRS_CH0 #6
PRS_CH1 #5
PRS_CH2 #4
PRS_CH3 #3
ACMP0_O #30
ACMP1_O #30
m
en
de
d
26
BUSAX [ADC0:
APORT1XCH20
ACMP0:
APORT1XCH20
ACMP1:
APORT1XCH20]
Timers
om
BUSAX [ADC0:
APORT1XCH22
ACMP0:
APORT1XCH22
ACMP1:
APORT1XCH22]
PF6
BUSBY [ADC0:
APORT2YCH22
ACMP0:
APORT2YCH22
ACMP1:
APORT2YCH22]
N
ot
R
ec
27
es
ig
ns
25
Analog
D
Pin Name
N
ew
Pin #
Pin Alternate Functionality / Description
fo
r
MGM111
silabs.com | Building a more connected world.
Rev. 1.1 | 57
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Pin Definitions
MGM111
PF7
29
VDD
30
RESETn
31
GND
BUSAY [ADC0:
APORT1YCH23
ACMP0:
APORT1YCH23
ACMP1:
APORT1YCH23]
BUSBX [ADC0:
APORT2XCH23
ACMP0:
APORT2XCH23
ACMP1:
APORT2XCH23]
Timers
Communication
Radio
Other
TIM0_CC0 #31
TIM0_CC1 #30
TIM0_CC2 #29
TIM0_CDTI0 #28
TIM0_CDTI1 #27
TIM0_CDTI2 #26
TIM1_CC0 #31
TIM1_CC1 #30
TIM1_CC2 #29
TIM1_CC3 #28 LETIM0_OUT0 #31
LETIM0_OUT1 #30
PCNT0_S0IN #31
PCNT0_S1IN #30
US0_TX #31
US0_RX #30
US0_CLK #29
US0_CS #28
US0_CTS #27
US0_RTS #26
US1_TX #31
US1_RX #30
US1_CLK #29
US1_CS #28
US1_CTS #27
US1_RTS #26
LEU0_TX #31
LEU0_RX #30
I2C0_SDA #31
I2C0_SCL #30
FRC_DCLK #31
FRC_DOUT #30
FRC_DFRAME #29
MODEM_DCLK
#31 MODEM_DIN
#30 MODEM_DOUT #29
MODEM_ANT0
#28 MODEM_ANT1 #27
CMU_CLK0 #7
PRS_CH0 #7
PRS_CH1 #6
PRS_CH2 #5
PRS_CH3 #4
ACMP0_O #31
ACMP1_O #31
GPIO_EM4WU1
Module power supply
es
ig
ns
28
Analog
D
Pin Name
N
ew
Pin #
Pin Alternate Functionality / Description
Reset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low
during reset, and let the internal pull-up ensure that reset is released.
Ground
fo
r
8.1.1 GPIO Overview
The GPIO pins are organized as 16-bit ports indicated by letters A through F, and the individual pins on each port are indicated by a
number from 15 down to 0.
Port
Pin
15
Pin
14
Port A
-
-
Port B
Pin
13
Pin
12
Pin
11
Pin
10
-
-
-
-
-
-
-
-
PA5
(5V)
PA4
PA3
PA2
PA1
PA0
PB11
-
-
-
-
-
-
-
-
-
-
-
PC9
(5V)
PC8
(5V)
PC7
(5V)
PC6
(5V)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PB13
-
-
-
om
Port C
Port D
m
en
de
d
Table 8.2. GPIO Pinout
-
PC11 PC10
(5V) (5V)
PD15 PD14 PD13
-
-
ec
Port E
Port F
-
-
Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PF7
(5V)
PF6
(5V)
PF5
(5V)
PF4
(5V)
PF3
(5V)
PF2
(5V)
PF1
(5V)
PF0
(5V)
N
ot
R
Note:
1. GPIO with 5V tolerance are indicated by (5V).
silabs.com | Building a more connected world.
Rev. 1.1 | 58
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Pin Definitions
8.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. The following table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Table 8.3. Alternate Functionality Overview
LOCATION
ACMP0_O
ACMP1_O
0-3
4-7
8 - 11
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
8: PB13
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
11: PC6
8: PB13
11: PC6
12 - 15
16 - 19
12: PC7
13: PC8
14: PC9
15: PC10
16: PC11
12: PC7
13: PC8
14: PC9
15: PC10
16: PC11
21: PD13
22: PD14
23: PD15
0: PA0
0: PA1
2: PC6
3: PC11
0: PA0
CMU_CLK1
2: PC7
3: PC10
5: PD15
6: PF3
7: PF6
N
ot
R
ec
DBG_SWCLKTCK
5: PD14
6: PF2
7: PF7
om
0: PF0
m
en
de
d
ADC0_EXTP
CMU_CLK0
21: PD13
22: PD14
23: PD15
fo
r
ADC0_EXTN
0: PA1
20 - 23
0: PF1
DBG_SWDIOTMS
silabs.com | Building a more connected world.
24 - 27
24: PF0
25: PF1
26: PF2
27: PF3
28 - 31
24: PF0
25: PF1
26: PF2
27: PF3
Description
28: PF4
29: PF5
30: PF6
31: PF7
Analog comparator
ACMP0, digital output.
28: PF4
29: PF5
30: PF6
31: PF7
Analog comparator
ACMP1, digital output.
D
Functionality
N
ew
Alternate
es
ig
ns
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.
Analog to digital
converter ADC0 external reference input negative pin
Analog to digital
converter ADC0 external reference input positive pin
Clock Management
Unit, clock output
number 0.
Clock Management
Unit, clock output
number 1.
Debug-interface
Serial Wire clock
input and JTAG
Test Clock.
Note that this function is enabled to
the pin out of reset,
and has a built-in
pull down.
Debug-interface
Serial Wire data input / output and
JTAG Test Mode
Select.
Note that this function is enabled to
the pin out of reset,
and has a built-in
pull up.
Rev. 1.1 | 59
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0-3
4-7
8 - 11
12 - 15
16 - 19
20 - 23
24 - 27
28 - 31
Debug-interface
Serial Wire viewer
Output.
0: PF2
1: PB13
2: PD15
3: PC11
Note that this function is not enabled
after reset, and
must be enabled by
software to be
used.
es
ig
ns
DBG_SWO
0: PF3
Debug-interface
JTAG Test Data In.
N
ew
D
DBG_TDI
0: PF2
FRC_DOUT
0: PA1
1: PA2
2: PA3
3: PA4
4: PB11
6: PB13
7: PB13
ec
0: PF7
R
GPIO_EM4WU1
0: PD14
N
ot
9: PC6
10: PC7
11: PC8
4: PA5
5: PB11
0: PF2
GPIO_EM4WU0
12: PC7
13: PC8
14: PC9
15: PC10
16: PC11
m
en
de
d
FRC_DFRAME
0: PA2
1: PA3
2: PA4
3: PA5
8: PB13
11: PC6
om
FRC_DCLK
4: PA4
5: PA5
6: PB11
fo
r
DBG_TDO
0: PA0
1: PA1
2: PA2
3: PA3
Description
GPIO_EM4WU4
0: PA3
GPIO_EM4WU8
silabs.com | Building a more connected world.
10: PC6
11: PC7
12: PC9
13: PC10
14: PC11
19: PD13
12: PC8
13: PC9
14: PC10
15: PC11
Note that this function is enabled to
pin out of reset,
and has a built-in
pull up.
Debug-interface
JTAG Test Data
Out.
Note that this function is enabled to
pin out of reset.
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
Frame Controller,
Data Sniffer Clock.
20: PD14
21: PD15
22: PF0
23: PF1
24: PF2
25: PF3
26: PF4
27: PF5
28: PF6
29: PF7
30: PA0
31: PA1
Frame Controller,
Data Sniffer Frame
active
20: PD13
21: PD14
22: PD15
23: PF0
24: PF1
25: PF2
26: PF3
27: PF4
28: PF5
29: PF6
30: PF7
31: PA0
Frame Controller,
Data Sniffer Output.
Pin can be used to
wake the system
up from EM4
Pin can be used to
wake the system
up from EM4
Pin can be used to
wake the system
up from EM4
Pin can be used to
wake the system
up from EM4
Rev. 1.1 | 60
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0-3
4-7
8 - 11
12 - 15
16 - 19
20 - 23
24 - 27
28 - 31
0: PB13
Pin can be used to
wake the system
up from EM4
0: PC10
Pin can be used to
wake the system
up from EM4
GPIO_EM4WU12
LETIM0_OUT1
LEU0_RX
4: PA4
5: PA5
6: PB11
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
5: PB11
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
5: PB11
0: PA0
1: PA1
2: PA2
3: PA3
0: PA4
1: PA5
2: PB11
ec
MODEM_ANT0
0: PA3
1: PA4
2: PA5
3: PB11
R
MODEM_ANT1
N
ot
MODEM_DCLK
MODEM_DIN
MODEM_DOUT
7: PB13
4: PA4
5: PA5
6: PB11
I2C0 Serial Data input / output.
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
Low Energy Timer
LETIM0, output
channel 0.
20: PD13
21: PD14
22: PD15
23: PF0
24: PF1
25: PF2
26: PF3
27: PF4
28: PF5
29: PF6
30: PF7
31: PA0
Low Energy Timer
LETIM0, output
channel 1.
20: PD13
21: PD14
22: PD15
23: PF0
24: PF1
25: PF2
26: PF3
27: PF4
28: PF5
29: PF6
30: PF7
31: PA0
LEUART0 Receive
input.
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
LEUART0 Transmit
output. Also used
as receive input in
half duplex communication.
18: PD13
19: PD14
20: PD15
21: PF0
22: PF1
23: PF2
24: PF3
25: PF4
26: PF5
27: PF6
28: PF7
29: PA0
30: PA1
31: PA2
MODEM antenna
control output 0,
used for antenna
diversity.
17: PD13
18: PD14
19: PD15
20: PF0
21: PF1
22: PF2
23: PF3
24: PF4
25: PF5
26: PF6
27: PF7
28: PA0
29: PA1
30: PA2
31: PA3
MODEM antenna
control output 1,
used for antenna
diversity.
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
MODEM data clock
out.
16: PC11
16: PC11
11: PC6
12: PC7
13: PC8
14: PC9
15: PC10
10: PC6
11: PC7
12: PC8
13: PC9
14: PC10
15: PC11
8: PB13
10: PC6
11: PC7
8: PB13
11: PC6
5: PB13
om
LEU0_TX
28: PF4
29: PF5
30: PF6
31: PF7
12: PC7
13: PC8
14: PC9
15: PC10
8: PB13
11: PC6
7: PB13
I2C0 Serial Clock
Line input / output.
4: PB13
7: PC6
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
5: PB11
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
7: PB13
6: PB13
silabs.com | Building a more connected world.
20: PD13
21: PD14
22: PD15
23: PF0
24: PF1
25: PF2
26: PF3
27: PF4
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
21: PD13
22: PD14
23: PD15
12: PC8
13: PC9
14: PC10
15: PC11
12: PC7
13: PC8
14: PC9
15: PC10
D
0: PA0
1: PA1
2: PA2
3: PA3
7: PB13
10: PC6
11: PC7
28: PF5
29: PF6
30: PF7
31: PA0
12: PC8
13: PC9
14: PC10
15: PC11
N
ew
4: PA5
5: PB11
fo
r
LETIM0_OUT0
0: PA1
1: PA2
2: PA3
3: PA4
m
en
de
d
I2C0_SDA
es
ig
ns
GPIO_EM4WU9
I2C0_SCL
Description
16: PC11
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10
13: PC11
8: PC7
9: PC8
10: PC9
11: PC10
12: PC11
8: PB13
11: PC6
12: PC7
13: PC8
14: PC9
15: PC10
10: PC6
11: PC7
12: PC8
13: PC9
14: PC10
15: PC11
20: PD13
21: PD14
22: PD15
23: PF0
24: PF1
25: PF2
26: PF3
27: PF4
28: PF5
29: PF6
30: PF7
31: PA0
MODEM data in.
12: PC9
13: PC10
14: PC11
20: PD14
21: PD15
22: PF0
23: PF1
24: PF2
25: PF3
26: PF4
27: PF5
28: PF6
29: PF7
30: PA0
31: PA1
MODEM data out.
9: PC6
10: PC7
11: PC8
16: PC11
19: PD13
Rev. 1.1 | 61
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Pin Definitions
LOCATION
0-3
4-7
8 - 11
12 - 15
16 - 19
4: PA4
5: PA5
6: PB11
8: PB13
PCNT0_S0IN
0: PA0
1: PA1
2: PA2
3: PA3
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
5: PB11
16: PC11
11: PC6
12: PC7
13: PC8
14: PC9
15: PC10
7: PB13
10: PC6
11: PC7
12: PC8
13: PC9
14: PC10
15: PC11
PRS_CH0
0: PF0
1: PF1
2: PF2
3: PF3
4: PF4
5: PF5
6: PF6
7: PF7
8: PC6
9: PC7
10: PC8
11: PC9
PRS_CH1
0: PF1
1: PF2
2: PF3
3: PF4
4: PF5
5: PF6
6: PF7
7: PF0
PRS_CH2
0: PF2
1: PF3
2: PF4
3: PF5
4: PF6
5: PF7
6: PF0
7: PF1
PRS_CH3
0: PF3
1: PF4
2: PF5
3: PF6
4: PF7
5: PF0
6: PF1
7: PF2
3: PD13
4: PA5
5: PB11
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
R
N
ot
PRS_CH8
4: PA4
5: PA5
6: PB11
0: PA1
1: PA2
2: PA3
3: PA4
ec
PRS_CH7
0: PA0
1: PA1
2: PA2
3: PA3
om
PRS_CH6
PRS_CH9
0: PA3
1: PA4
2: PA5
3: PB11
PRS_CH10
0: PC6
1: PC7
2: PC8
3: PC9
8: PB13
5: PB13
4: PC10
5: PC11
silabs.com | Building a more connected world.
28: PF4
29: PF5
30: PF6
31: PF7
Pulse Counter
PCNT0 input number 0.
20: PD13
21: PD14
22: PD15
23: PF0
24: PF1
25: PF2
26: PF3
27: PF4
28: PF5
29: PF6
30: PF7
31: PA0
Pulse Counter
PCNT0 input number 1.
N
ew
16: PD14
17: PD15
15: PD13
10: PA0
Peripheral Reflex
System PRS, channel 2.
Peripheral Reflex
System PRS, channel 3.
Peripheral Reflex
System PRS, channel 4.
Peripheral Reflex
System PRS, channel 5.
Peripheral Reflex
System PRS, channel 6.
Peripheral Reflex
System PRS, channel 8.
9: PA0
10: PA1
8: PA0
9: PA1
10: PA2
11: PC6
Peripheral Reflex
System PRS, channel 1.
Peripheral Reflex
System PRS, channel 7.
7: PB13
6: PB13
Description
24: PF0
25: PF1
26: PF2
27: PF3
fo
r
12: PD13
13: PD14
14: PD15
4: PD14
5: PD15
PRS_CH5
28 - 31
Peripheral Reflex
System PRS, channel 0.
4: PD13
5: PD14
6: PD15
PRS_CH4
24 - 27
21: PD13
22: PD14
23: PD15
12: PC10
13: PC11
m
en
de
d
PCNT0_S1IN
20 - 23
D
Functionality
es
ig
ns
Alternate
12: PC7
13: PC8
14: PC9
15: PC10
16: PC11
Peripheral Reflex
System PRS, channel 9.
Peripheral Reflex
System PRS, channel 10.
Rev. 1.1 | 62
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Pin Definitions
Alternate
LOCATION
4: PC11
5: PC6
TIM0_CC0
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
5: PB11
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
TIM0_CC1
TIM0_CC2
TIM0_CDTI0
TIM0_CDTI1
7: PB13
6: PB13
0: PA3
1: PA4
2: PA5
3: PB11
5: PB13
0: PA4
1: PA5
2: PB11
4: PB13
TIM0_CDTI2
0: PA5
1: PB11
3: PB13
TIM1_CC1
0: PA2
1: PA3
2: PA4
3: PA5
ec
TIM1_CC2
0: PA1
1: PA2
2: PA3
3: PA4
0: PA3
1: PA4
2: PA5
3: PB11
R
N
ot
TIM1_CC3
US0_CLK
US0_CS
6: PC6
7: PC7
4: PA4
5: PA5
6: PB11
0: PA2
1: PA3
2: PA4
3: PA5
0: PA3
1: PA4
2: PA5
3: PB11
20 - 23
7: PB13
8: PB13
5: PB13
5: PB13
silabs.com | Building a more connected world.
Description
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
16: PC11
28: PF4
29: PF5
30: PF6
31: PF7
Timer 0 Capture
Compare input /
output channel 0.
28: PF5
29: PF6
30: PF7
31: PA0
Timer 0 Capture
Compare input /
output channel 1.
28: PF6
29: PF7
30: PA0
31: PA1
Timer 0 Capture
Compare input /
output channel 2.
11: PC6
10: PC6
11: PC7
12: PC8
13: PC9
14: PC10
15: PC11
20: PD13
21: PD14
22: PD15
23: PF0
24: PF1
25: PF2
26: PF3
27: PF4
12: PC9
13: PC10
14: PC11
19: PD13
20: PD14
21: PD15
22: PF0
23: PF1
24: PF2
25: PF3
26: PF4
27: PF5
18: PD13
19: PD14
20: PD15
21: PF0
22: PF1
23: PF2
24: PF3
25: PF4
26: PF5
27: PF6
28: PF7
29: PA0
30: PA1
31: PA2
Timer 0 Complimentary Dead Time
Insertion channel 0.
17: PD13
18: PD14
19: PD15
20: PF0
21: PF1
22: PF2
23: PF3
24: PF4
25: PF5
26: PF6
27: PF7
28: PA0
29: PA1
30: PA2
31: PA3
Timer 0 Complimentary Dead Time
Insertion channel 1.
16: PD13
17: PD14
18: PD15
19: PF0
20: PF1
21: PF2
22: PF3
23: PF4
24: PF5
25: PF6
26: PF7
27: PA0
28: PA1
29: PA2
30: PA3
31: PA4
Timer 0 Complimentary Dead Time
Insertion channel 2.
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
Timer 1 Capture
Compare input /
output channel 0.
9: PC6
10: PC7
11: PC8
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10
13: PC11
8: PC7
9: PC8
10: PC9
11: PC10
12: PC11
8: PC8
9: PC9
10: PC10
11: PC11
8: PB13
11: PC6
12: PC7
13: PC8
14: PC9
15: PC10
10: PC6
11: PC7
12: PC8
13: PC9
14: PC10
15: PC11
20: PD13
21: PD14
22: PD15
23: PF0
24: PF1
25: PF2
26: PF3
27: PF4
28: PF5
29: PF6
30: PF7
31: PA0
Timer 1 Capture
Compare input /
output channel 1.
12: PC9
13: PC10
14: PC11
19: PD13
20: PD14
21: PD15
22: PF0
23: PF1
24: PF2
25: PF3
26: PF4
27: PF5
28: PF6
29: PF7
30: PA0
31: PA1
Timer 1 Capture
Compare input /
output channel 2.
18: PD13
19: PD14
20: PD15
21: PF0
22: PF1
23: PF2
24: PF3
25: PF4
26: PF5
27: PF6
28: PF7
29: PA0
30: PA1
31: PA2
Timer 1 Capture
Compare input /
output channel 3.
24: PF2
25: PF3
26: PF4
27: PF5
28: PF6
29: PF7
30: PA0
31: PA1
USART0 clock input / output.
19: PD13
20: PD14
21: PD15
22: PF0
23: PF1
18: PD13
19: PD14
20: PD15
21: PF0
22: PF1
23: PF2
24: PF3
25: PF4
26: PF5
27: PF6
28: PF7
29: PA0
30: PA1
31: PA2
USART0 chip select input / output.
9: PC6
10: PC7
11: PC8
8: PC6
9: PC7
10: PC8
11: PC9
4: PB11
6: PB13
28 - 31
12: PC7
13: PC8
14: PC9
15: PC10
4: PB11
6: PB13
24 - 27
Peripheral Reflex
System PRS, channel 11.
4: PA5
5: PB11
om
TIM1_CC0
0: PA0
1: PA1
2: PA2
3: PA3
16 - 19
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7: PC6
12 - 15
es
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PRS_CH11
0: PC7
1: PC8
2: PC9
3: PC10
8 - 11
D
4-7
N
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0-3
fo
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Functionality
9: PC6
10: PC7
11: PC8
8: PC6
9: PC7
10: PC8
11: PC9
16: PC11
12: PC10
13: PC11
12: PC9
13: PC10
14: PC11
12: PC10
13: PC11
Rev. 1.1 | 63
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Pin Definitions
LOCATION
Functionality
US0_CTS
US0_RTS
0-3
4-7
0: PA4
1: PA5
2: PB11
4: PB13
12 - 15
12: PC11
7: PC6
8: PC7
9: PC8
10: PC9
11: PC10
6: PC6
7: PC7
8: PC8
9: PC9
10: PC10
11: PC11
0: PA5
1: PB11
3: PB13
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
5: PB11
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB13
10: PC6
11: PC7
16 - 19
20 - 23
24 - 27
28 - 31
20: PF0
21: PF1
22: PF2
23: PF3
24: PF4
25: PF5
26: PF6
27: PF7
28: PA0
29: PA1
30: PA2
31: PA3
USART0 Clear To
Send hardware
flow control input.
16: PD13
17: PD14
18: PD15
19: PF0
20: PF1
21: PF2
22: PF3
23: PF4
24: PF5
25: PF6
26: PF7
27: PA0
28: PA1
29: PA2
30: PA3
31: PA4
USART0 Request
To Send hardware
flow control output.
20: PD13
21: PD14
22: PD15
23: PF0
24: PF1
25: PF2
26: PF3
27: PF4
12: PC8
13: PC9
14: PC10
15: PC11
28: PF5
29: PF6
30: PF7
31: PA0
11: PC6
12: PC7
13: PC8
14: PC9
15: PC10
16: PC11
21: PD13
22: PD14
23: PD15
0: PA3
1: PA4
2: PA5
3: PB11
US1_CTS
US1_RTS
0: PA4
1: PA5
2: PB11
ec
R
0: PA1
1: PA2
2: PA3
3: PA4
9: PC6
10: PC7
11: PC8
12: PC9
13: PC10
14: PC11
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10
13: PC11
12: PC11
7: PC6
8: PC7
9: PC8
10: PC9
11: PC10
6: PC6
7: PC7
8: PC8
9: PC9
10: PC10
11: PC11
5: PB13
4: PB13
0: PA5
1: PB11
3: PB13
4: PA5
5: PB11
7: PB13
N
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US1_RX
6: PB13
om
US1_CS
4: PB11
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10: PC6
11: PC7
12: PC8
13: PC9
14: PC10
15: PC11
28: PF4
29: PF5
30: PF6
31: PF7
USART0 Asynchronous Receive.
USART0 Synchronous mode Master
Input / Slave Output (MISO).
USART0 Asynchronous Transmit. Also used as receive
input in half duplex
communication.
USART0 Synchronous mode Master
Output / Slave Input (MOSI).
24: PF2
25: PF3
26: PF4
27: PF5
28: PF6
29: PF7
30: PA0
31: PA1
USART1 clock input / output.
19: PD13
20: PD14
21: PD15
22: PF0
23: PF1
18: PD13
19: PD14
20: PD15
21: PF0
22: PF1
23: PF2
24: PF3
25: PF4
26: PF5
27: PF6
28: PF7
29: PA0
30: PA1
31: PA2
USART1 chip select input / output.
17: PD13
18: PD14
19: PD15
20: PF0
21: PF1
22: PF2
23: PF3
24: PF4
25: PF5
26: PF6
27: PF7
28: PA0
29: PA1
30: PA2
31: PA3
USART1 Clear To
Send hardware
flow control input.
16: PD13
17: PD14
18: PD15
19: PF0
20: PF1
21: PF2
22: PF3
23: PF4
24: PF5
25: PF6
26: PF7
27: PA0
28: PA1
29: PA2
30: PA3
31: PA4
USART1 Request
To Send hardware
flow control output.
20: PD13
21: PD14
22: PD15
23: PF0
24: PF1
25: PF2
26: PF3
27: PF4
28: PF5
29: PF6
30: PF7
31: PA0
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US1_CLK
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US0_TX
0: PA2
1: PA3
2: PA4
3: PA5
24: PF0
25: PF1
26: PF2
27: PF3
N
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8: PB13
Description
17: PD13
18: PD14
19: PD15
D
US0_RX
8 - 11
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Alternate
USART1 Asynchronous Receive.
USART1 Synchronous mode Master
Input / Slave Output (MISO).
Rev. 1.1 | 64
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0-3
4-7
8 - 11
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
8: PB13
11: PC6
12 - 15
16 - 19
20 - 23
12: PC7
13: PC8
14: PC9
15: PC10
16: PC11
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
28 - 31
28: PF4
29: PF5
30: PF6
31: PF7
Description
USART1 Asynchronous Transmit. Also used as receive
input in half duplex
communication.
es
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US1_TX
24 - 27
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USART1 Synchronous mode Master
Output / Slave Input (MOSI).
silabs.com | Building a more connected world.
Rev. 1.1 | 65
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Pin Definitions
8.3 Analog Port (APORT)
The Analog Port (APORT) is an infrastructure used to connect chip pins with on-chip analog clients such as analog comparators, ADCs,
and DACs. The APORT consists of wires, switches, and control needed to configurably implement the routes. Please see the device
Reference Manual for a complete description.
PC6
PC8
PC10
PF0
PF2
PF4
PF6
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BUSAX
PC7
PC9
PC11
PF1
PF3
PF5
PF7
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BUSBY
N
ew
BUSAY
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BUSBX
PD14
PA0
PA2
PA4
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BUSCX
R
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BUSCY
N
ot
PD13
PD15
PA1
PA3
PA5
PB11
PB13
om
BUSDY
BUSDX
1X1Y2X2Y3X3Y4X4Y
ACMP0
1X1Y2X2Y3X3Y4X4Y
ACMP1
1X1Y2X2Y3X3Y4X4Y
ADC0
1X1Y
IDAC0
Figure 8.2. MGM111 APORT
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Rev. 1.1 | 66
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Pin Definitions
Table 8.4. APORT Client Map
Analog Module Channel
APORT1XCH6
ACMP0
BUSAX
PC6
APORT1XCH8
PC8
APORT1XCH10
PC10
APORT1XCH16
PF0
APORT1XCH18
PF2
APORT1XCH20
PF4
APORT1XCH22
PF6
APORT1YCH7
BUSAY
PC7
PC9
N
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APORT1YCH9
APORT1YCH11
PC11
APORT1YCH17
PF1
APORT1YCH19
PF3
APORT1YCH23
APORT2XCH7
BUSBX
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APORT2XCH9
PF5
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APORT1YCH21
ACMP0
ec
PC7
PC9
PC11
APORT2XCH17
PF1
APORT2XCH19
PF3
APORT2XCH21
PF5
APORT2XCH23
PF7
APORT2YCH6
BUSBY
PC6
APORT2YCH8
PC8
APORT2YCH10
PC10
APORT2YCH16
PF0
APORT2YCH18
PF2
APORT2YCH20
PF4
APORT2YCH22
PF6
N
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R
PF7
APORT2XCH11
om
ACMP0
Pin
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ACMP0
Shared Bus
D
Analog Module
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Rev. 1.1 | 67
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Pin Definitions
Analog Module
Analog Module Channel
ACMP0
APORT3XCH2
Shared Bus
Pin
BUSCX
APORT3XCH4
PD14
APORT3XCH8
PA0
APORT3XCH10
PA2
APORT3XCH12
PA4
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APORT3XCH6
APORT3XCH28
APORT3XCH30
ACMP0
APORT3YCH3
BUSCY
PD13
APORT3YCH7
D
APORT3YCH5
APORT3YCH9
PA1
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PD15
APORT3YCH11
PA3
APORT3YCH13
PA5
APORT3YCH29
APORT3YCH31
APORT4XCH3
PB13
BUSDX
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ACMP0
PB11
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APORT3YCH27
PD13
APORT4XCH7
PD15
APORT4XCH9
PA1
APORT4XCH11
PA3
APORT4XCH13
PA5
APORT4XCH27
PB11
APORT4XCH29
PB13
om
APORT4XCH5
APORT4XCH31
APORT4YCH2
N
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R
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ACMP0
BUSDY
APORT4YCH4
APORT4YCH6
PD14
APORT4YCH8
PA0
APORT4YCH10
PA2
APORT4YCH12
PA4
APORT4YCH28
APORT4YCH30
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Rev. 1.1 | 68
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Pin Definitions
Analog Module Channel
APORT1XCH6
APORT1XCH8
PC8
APORT1XCH10
PC10
APORT1XCH16
PF0
APORT1XCH18
PF2
APORT1XCH20
PF4
APORT1XCH22
PF6
APORT1YCH7
BUSAY
PC9
APORT1YCH11
PC11
APORT1YCH17
APORT1YCH19
PF3
PF1
PF5
APORT1YCH23
APORT2XCH9
APORT2XCH11
BUSBX
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APORT2XCH17
PF7
fo
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APORT2XCH7
ec
N
ot
PC9
PC11
PF1
PF3
APORT2XCH21
PF5
APORT2XCH23
PF7
APORT2YCH6
R
ACMP1
PC7
APORT2XCH19
BUSBY
PC6
APORT2YCH8
PC8
APORT2YCH10
PC10
APORT2YCH16
PF0
om
ACMP1
PC7
APORT1YCH9
APORT1YCH21
ACMP1
PC6
D
ACMP1
BUSAX
Pin
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ACMP1
Shared Bus
N
ew
Analog Module
APORT2YCH18
PF2
APORT2YCH20
PF4
APORT2YCH22
PF6
APORT3XCH2
BUSCX
APORT3XCH4
APORT3XCH6
PD14
APORT3XCH8
PA0
APORT3XCH10
PA2
APORT3XCH12
PA4
APORT3XCH28
APORT3XCH30
silabs.com | Building a more connected world.
Rev. 1.1 | 69
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Pin Definitions
Analog Module Channel
ACMP1
APORT3YCH3
Shared Bus
BUSCY
APORT3YCH5
PD13
APORT3YCH7
PD15
APORT3YCH9
PA1
APORT3YCH11
PA3
APORT3YCH13
PA5
APORT3YCH27
PB11
APORT3YCH29
PB13
APORT3YCH31
BUSDX
APORT4XCH5
D
APORT4XCH3
APORT4XCH7
PD15
PD13
N
ew
ACMP1
APORT4XCH9
PA1
APORT4XCH11
PA3
APORT4XCH27
APORT4XCH29
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APORT4XCH31
PA5
fo
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APORT4XCH13
ACMP1
Pin
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ns
Analog Module
APORT4YCH2
PB11
PB13
BUSDY
APORT4YCH4
APORT4YCH6
PD14
APORT4YCH8
PA0
APORT4YCH10
PA2
APORT4YCH12
PA4
om
APORT4YCH28
APORT4YCH30
APORT1XCH6
N
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R
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ADC0
BUSAX
PC6
APORT1XCH8
PC8
APORT1XCH10
PC10
APORT1XCH16
PF0
APORT1XCH18
PF2
APORT1XCH20
PF4
APORT1XCH22
PF6
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Rev. 1.1 | 70
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Pin Definitions
Analog Module Channel
APORT1YCH7
APORT1YCH9
PC9
APORT1YCH11
PC11
APORT1YCH17
PF1
APORT1YCH19
PF3
APORT1YCH21
PF5
APORT1YCH23
PF7
APORT2XCH7
BUSBX
PC9
APORT2XCH11
PC11
APORT2XCH17
APORT2XCH19
PF3
PF1
PF5
APORT2XCH23
APORT2YCH8
APORT2YCH10
BUSBY
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APORT2YCH16
PF7
fo
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APORT2YCH6
ADC0
PC7
APORT2XCH9
APORT2XCH21
ADC0
PC7
D
ADC0
BUSAY
Pin
es
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ns
ADC0
Shared Bus
N
ew
Analog Module
PC6
PC8
PC10
PF0
APORT2YCH18
PF2
APORT2YCH20
PF4
APORT2YCH22
PF6
APORT3XCH2
BUSCX
APORT3XCH4
PD14
APORT3XCH8
PA0
APORT3XCH10
PA2
APORT3XCH12
PA4
APORT3XCH28
APORT3XCH30
N
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om
APORT3XCH6
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Rev. 1.1 | 71
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Pin Definitions
Analog Module Channel
ADC0
APORT3YCH3
Shared Bus
BUSCY
APORT3YCH5
PD13
APORT3YCH7
PD15
APORT3YCH9
PA1
APORT3YCH11
PA3
APORT3YCH13
PA5
APORT3YCH27
PB11
APORT3YCH29
PB13
APORT3YCH31
BUSDX
APORT4XCH5
D
APORT4XCH3
APORT4XCH7
PD15
PD13
N
ew
ADC0
APORT4XCH9
PA1
APORT4XCH11
PA3
APORT4XCH27
APORT4XCH29
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APORT4XCH31
PA5
fo
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APORT4XCH13
ADC0
Pin
es
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ns
Analog Module
APORT4YCH2
PB11
PB13
BUSDY
APORT4YCH4
APORT4YCH6
PD14
APORT4YCH8
PA0
APORT4YCH10
PA2
APORT4YCH12
PA4
om
APORT4YCH28
APORT4YCH30
APORT1XCH2
N
ot
R
ec
IDAC0
BUSCX
APORT1XCH4
APORT1XCH6
PD14
APORT1XCH8
PA0
APORT1XCH10
PA2
APORT1XCH12
PA4
APORT1XCH28
APORT1XCH30
silabs.com | Building a more connected world.
Rev. 1.1 | 72
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Pin Definitions
Analog Module Channel
IDAC0
APORT1YCH3
Shared Bus
Pin
BUSCY
APORT1YCH5
PD13
APORT1YCH7
PD15
APORT1YCH9
PA1
APORT1YCH11
PA3
APORT1YCH13
PA5
APORT1YCH27
PB11
APORT1YCH29
PB13
es
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Analog Module
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D
APORT1YCH31
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Rev. 1.1 | 73
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Package Specifications
9. Package Specifications
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9.1 MGM111 Dimensions
Figure 9.2. MGM111E Package Dimensions
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Figure 9.1. MGM111A Package Dimensions
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Rev. 1.1 | 74
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Package Specifications
9.2 MGM111 Module Footprint
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The figure below shows the Module footprint and PCB dimensions.
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Figure 9.3. MGM111 Footprint
9.3 MGM111 Recommended PCB Land Pattern
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The figure below shows the recommended land pattern. The antenna clearance section is not required for the MGM111E module.
Figure 9.4. MGM111 Recommended PCB Land Pattern
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Rev. 1.1 | 75
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Package Specifications
9.4 MGM111 Package Marking
Figure 9.5. MGM111A Package Marking
Figure 9.6. MGM111E Package Marking
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Mark Description
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The figure below shows the Module markings printed on the RF-shield.
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The package marking consists of:
• MGM111A256V2 - Part number designation
• Model: MGM111A – Model number designation
• MGM111E256V2 - Part number designation
• Model: MGM111E – Model number designation
• QR Code: YYWWMMABCDE
• YY – The last 2 digits of the assembly year
• WW – The 2 digit work week when the device was assembled
• MMABCDE – Silicon Labs unit code
• Trace Code: YYWWTTTTTT
• YY – The last 2 digits of the assembly year
• WW – The 2 digit work week when the device was assembled
• TTTTTT – A trace or manufacturing code. The first letter is the device revision
• Certification-related information (such as the CE Mark, FCC and IC IDs, etc.) is being engraved on the grayed out area, and/or printed on the back side of the module (silkscreen), in accordance with the requirements by regulatory bodies.
silabs.com | Building a more connected world.
Rev. 1.1 | 76
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Tape and Reel Specifications
10. Tape and Reel Specifications
10.1 Tape and Reel Packaging
This section contains information regarding the tape and reel packaging for the MGM111 Mighty Gecko Module.
Reel material: Polystyrene (PS)
Reel diameter: 13 inches (330 mm)
Number of modules per reel: 1000 pcs
Disk deformation, folding whitening and mold imperfections: Not allowed
Disk set: consists of two 13 inch (330 mm) rotary round disks and one central axis (100 mm)
Antistatic treatment: Required
Surface resistivity: 104 - 109 Ω/sq.
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Figure 10.1. Reel Dimensions - Side View
D
•
•
•
•
•
•
•
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10.2 Reel Material and Dimensions
Dimensions [mm]
W0
32.5 ± 0.3
W1
37.1 ± 1.0
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Symbol
silabs.com | Building a more connected world.
Rev. 1.1 | 77
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Tape and Reel Specifications
10.3 Module Orientation and Tape Feed
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The user direction of feed, start and end of tape on reel and orientation of the Modules on the tape are shown in the figures below.
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Figure 10.2. Module Orientation and Feed Direction
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Rev. 1.1 | 78
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Tape and Reel Specifications
10.4 Tape and Reel Box Dimensions
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Figure 10.3. Tape and Reel Box Dimensions
W2
W3
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W4
Dimensions [mm]
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Symbol
368
338
72
10.5 Moisture Sensitivity Level
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Reels are delivered in packing which conforms to MSL3 (Moisture Sensitivity Level 3) requirements.
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Rev. 1.1 | 79
MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Certificates
11. Certificates
11.1 Approved Antenna Types
es
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MGM111E is approved with a standard 2.14 dBi dipole antenna. Any antenna of the same type, similar in-band out of band characteristics and with the same or less gain can be used without reassessment. In case using antenna of a different type and/or higher gain
reassessments and notification to the particular certification authority is required.
11.2 FCC
This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:
1. This device may not cause harmful interference, and
2. This device must accept any interference received, including interference that may cause undesirable operation.
Any changes or modifications not expressly approved by Silicon Labs could void the user’s authority to operate the equipment.
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FCC RF Radiation Exposure Statement:
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This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. End users must follow the specific operating instructions for satisfying RF exposure compliance. This transmittermeets both portable and mobile limits as demonstrated
in the RF Exposure Analysis. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter
except in accordance with FCC multi-transmitter product procedures. As long as the condition above is met, further transmitter testing
will not be required. However, the OEM integrator is still responsible for testing their end-product for any additional compliance requirements required with this module installed (for example, digital device emissions, PC peripheral requirements, etc.).
OEM Responsibilities to comply with FCC Regulations
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The MGM111 Module has been certified for integration into products only by OEM integrators under the following condition:
• The antenna(s) must be installed such that a minimum separation distance of 10.5 mm is maintained between the radiator (antenna)
and all persons at all times.
• The transmitter module must not be co-located or operating in conjunction with any other antenna or transmitter except in accordance with FCC multi-transmitter product procedures.
As long as the conditions above are met, further transmitter testing will not be required. However, the OEM integrator is still responsible
for testing their end-product for any additional compliance requirements required with this module installed (for example, digital device
emissions, PC peripheral requirements, etc.).
Note: In the event that this condition cannot be met (for certain configurations or co-location with another transmitter), then the FCC
authorization is no longer considered valid and the FCC ID cannot be used on the final product. In these circumstances, the OEM integrator will be responsible for re-evaluating the end product (including the transmitter) and obtaining a separate FCC authorization.
End Product Labeling
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The MGM111 Module is labeled with its own FCC ID. If the FCC ID is not visible when the module is installed inside another device,
then the outside of the device into which the module is installed must also display a label referring to the enclosed module. In that case,
the final end product must be labeled in a visible area with the following:
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"Contains Transmitter Module FCC ID: QOQMGM111"
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"Contains FCC ID: QOQMGM111"
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The OEM integrator must not provide information to the end user regarding how to install or remove this RF module or change RF
related parameters in the user manual of the end product.
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MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Certificates
11.3 IC
IC (English)
This radio transmitter has been approved by Industry Canada to operate with the embedded chip antenna. Other antenna types are
strictly prohibited for use with this device.
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This device complies with Industry Canada’s license-exempt RSS standards. Operation is subject to the following two conditions:
1. This device may not cause interference; and
2. This device must accept any interference, including interference that may cause undesired operation of the device.
RF Exposure Statement
Exception from routine SAR evaluation limits are given in RSS-102 Issue 5. MGM111 meets the given requirements when the minimum
separation distance to human body 15 mm. RF exposure or SAR evaluation is not required when the separation distance is 15 mm or
more. If the separation distance is less than 15 mm the OEM integrator is responsible for evaluating the SAR.
OEM Responsibilities to comply with IC Regulations
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The MGM111 Module has been certified for integration into products only by OEM integrators under the following conditions:
• The antenna(s) must be installed such that a minimum separation distance of 15 mm is maintained between the radiator (antenna)
and all persons at all times.
• The transmitter module must not be co-located or operating in conjunction with any other antenna or transmitter.
As long as the two conditions above are met, further transmitter testing will not be required. However, the OEM integrator is still responsible for testing their end-product for any additional compliance requirements required with this module installed (for example, digital
device emissions, PC peripheral requirements, etc.).
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Note: In the event that these conditions cannot be met (for certain configurations or co-location with another transmitter), then the IC
authorization is no longer considered valid and the IC ID cannot be used on the final product. In these circumstances, the OEM integrator will be responsible for re-evaluating the end product (including the transmitter) and obtaining a separate IC authorization.
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End Product Labeling
The MGM111 module is labeled with its own IC ID. If the IC ID is not visible when the module is installed inside another device, then the
outside of the device into which the module is installed must also display a label referring to the enclosed module. In that case, the final
end product must be labeled in a visible area with the following:
"Contains Transmitter Module IC: 5123A-MGM111"
or
"Contains IC: 5123A-MGM111"
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The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module or
change RF related parameters in the user manual of the end product.
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MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Certificates
IC (Français)
Cet émetteur radio (IC : 5123A-MGM111) a reçu l'approbation d'Industrie Canada pour une exploitation avec l'antenne puce incorporée. Il est strictement interdit d'utiliser d'autres types d'antenne avec cet appareil.
Déclaration relative à l'exposition aux radiofréquences (RF)
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Le présent appareil est conforme aux CNR d’Industrie Canada applicables aux appareils radio exempts de licence. L’exploitation est
autorisée aux deux conditions suivantes:
1. L’appareil ne doit pas produire de brouillage; et
2. L’appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible de provoquer un fonctionnement
non désiré de l’appareil.
Responsabilités du FEO ayant trait à la conformité avec les règlements IC
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Les limites applicables à l’exemption de l’évaluation courante du DAS sont énoncées dans le CNR 102, 5e édition. Le module Bluetooth MGM111 répond aux exigences données quand la distance de séparation minimum par rapport au corps humain est de 15 mm.
L'évaluation de l'exposition aux RF ou du DAS n'est pas requise quand la distance de séparation est de 15 mm ou plus. Si la distance
de séparation est inférieure à 15 mm, il incombe à l'intégrateur FEO d'évaluer le DAS.
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Le Module Bluetooth MGM111 a été certifié pour une intégration dans des produits uniquement par les intégrateurs FEO dans les conditions suivantes:
• La ou les antennes doivent être installées de telle façon qu'une distance de séparation minimum de 15 mm soit maintenue entre le
radiateur (antenne) et toute personne à tout moment.
• Le module émetteur ne doit pas être installé au même endroit ou fonctionner conjointement avec toute autre antenne ou émetteur.
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Dès lors que les deux conditions ci-dessus sont respectées, aucun test supplémentaire de l’émetteur n’est obligatoire. Cependant, il
incombe toujours à l'intégrateur FEO de tester la conformité de son produit final vis-à-vis de toute exigence supplémentaire requise
avec ce module installé (par exemple, émissions de dispositifs numériques, exigences relatives aux matériels périphériques PC, etc).
Étiquetage du produit final
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Note: S'il s'avère que ces conditions ne peuvent être respectées (pour certaines configurations ou la colocation avec un autre émetteur), alors l'autorisation IC n'est plus considérée comme valide et l'identifiant IC ne peut plus être employé sur le produit final. Dans
ces circonstances, l'intégrateur FEO aura la responsabilité de réévaluer le produit final (y compris l'émetteur) et d'obtenir une autorisation IC distincte.
L'étiquette du Module MGM111 porte son propre identifiant IC. Si l'identifiant IC n'est pas visible quand le module est installé à l'intérieur d'un autre appareil, alors l'extérieur de l'appareil dans lequel le module est installé doit aussi porter une étiquette faisant référence
au module qu'il contient. Dans ce cas, une étiquette comportant les informations suivantes doit être apposée sur une partie visible du
produit final.
"Contient le module émetteur IC: 5123A-MGM111"
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"Contient IC : 5123A-MGM111"
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L'intégrateur FEO doit être conscient de ne pas fournir d'informations à l'utilisateur final permettant d'installer ou de retirer ce module
RF ou de changer les paramètres liés aux RF dans le mode d'emploi du produit final.
11.4 CE and UKCA - EU and UK
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The MGM111 modules have been tested against the relevant harmonized/designated standards and are in conformity with the essential requirements and other relevant requirements of the EU's Radio Equipment Directive (RED) (2014/53/EU) and of the UK's Radio
Equipment Regulations (RER) (S.I. 2017/1206).
Please notice that every end-product integrating a MGM111 module will need to perform the radio EMC tests on the whole assembly,
according to the ETSI 301 489-x relevant standards.
Furthermore, it is ultimately the responsibility of the manufacturers to ensure the compliance of their end-products as a whole. The specific product assembly is likely to have an impact to RF radiated characteristics, when compared to the bare module. Hence, manufacturers should carefully consider RF radiated testing with the final product assembly, especially taking into account the gain of the external antenna if any, and the possible deviations in the PSD, EIRP and spurious emissions measurements, as defined in the ETSI EN
300 328 standard.
The modules are entitled to carry the CE and UKCA Marks, and a formal Declaration of Conformity (DoC) is available at the product
web page which is reachable starting from https://www.silabs.com/.
silabs.com | Building a more connected world.
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MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Certificates
11.5 KC (South-Korea)
MGM111 Mighty Gecko Mesh Networking Module has certification in South-Korea.
Certification number for MGM111A: MSIP-CRM-BGT-MGM111A
Certification number for MGM111E: MSIP-CRM-BGT-MGM111E
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11.6 AU/NZ
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The MGM111 has been certified to be used in Australia and New Zealand. In order to have a RCM mark on an end product integrating
MGM111, a company must comply with a or b below.
• have a company presence in Australia
• have a company/distributor/agent in Australia that will sponsor the importing of the end product
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MGM111 Mighty Gecko Mesh Networking Module Data Sheet
Revision History
12. Revision History
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October, 2022
• In the front page block diagram, updated the lowest energy mode for LETIMER.
• Updated 3.6.3 Low Energy Timer (LETIMER) lowest energy mode.
• Removed BIASPROG = 1, FULLBIAS = 0 specifications from 4.1.15 Analog Comparator (ACMP).
• Added timing specifications for RESETn low time in Table 4.18 GPIO on page 28.
• Added Figure 4.2 SPI Master Timing Diagram (SMSDELAY = 1) on page 40.
• Updated Figure 9.3 MGM111 Footprint on page 75.
• Updated Figure 9.4 MGM111 Recommended PCB Land Pattern on page 75.
• Added two figures to 9.4 MGM111 Package Marking and updated Mark Description.
• Updated 11.4 CE and UKCA - EU and UK.
• Removed all references to RFSENSE.
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Revision 1.1
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Revision 1.0
• Full Production
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Revision 0.5
• Initial Publication
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Rev. 1.1 | 84
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Disclaimer
Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each
specific device, and “Typical” parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon
Labs reserves the right to make changes without further notice to the product information, specifications, and descriptions herein, and does not give warranties as to the
accuracy or completeness of the included information. Without prior notification, Silicon Labs may update product firmware during the manufacturing process for security or
reliability reasons. Such changes will not alter the specifications or the performance of the product. Silicon Labs shall have no liability for the consequences of use of the information supplied in this document. This document does not imply or expressly grant any license to design or fabricate any integrated circuits. The products are not designed or
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