Si825x Multi-Phase POL-RD
Si825 X M U L T I - PHASE POL R EFERENCE D E S I GN U SER ’ S G UIDE
1. Kit Contents
The non-isolated Si825x Multi-Phase Point of Load (POL) Reference Design contains the following items:
40 Amp Si8250-based Multi-Phase POL Target Board
USB to SMBus™ Bridge Board
USB Debug Adapter
USB Cable
Silicon Laboratories IDE and Product Information CD-ROM. CD content includes the following:
Silicon
Laboratories Integrated Development Environment (IDE)
8051 Development Tools (macro assembler, linker, evaluation C compiler)
Source code examples and register definition files
Multi-Phase POL Firmware Kernel
Application Builder tool suite (waveform editor, compensator, system and MCU wizards)
Keil
SMBus
TM
Monitor Software
Kernel flowcharts and Si825x data sheet
Documentation:
Si825x Multi-Phase POL Reference Design User’s Guide (this document)
Note: The full version of the Kernel when compiled is approximately 14 kB. This exceeds the 4 kB limit of the compiler that is
shipped with the kit’s software development tools. To avoid a compiler limit issue, either buy the full Keil compiler toolset
or compile the limited version of the Kernel.
Rev. 0.2 11/06
Copyright © 2006 by Silicon Laboratories
Si825x Multi-Phase POL-RD
Si825x Multi-Phase POL-RD
2. Hardware Overview
The Si825x Multi-Phase POL Reference Design implements a digitally-controlled POL with a DPWM (digital pulse
width modulation) switching frequency of 391 kHz. The Si8250 Multi-Phase POL Target Board (Figure 1) contains
system power stages and digital control circuits with debug connectors for the Si8250 digital power controller. The
user can also access and control the target board using SMBus.
Power Supply Form Factor
DCR Current
Si825x
Sense Diff Amp
VIN
Driver
VOUT
SMBus Adaptor
Interface (J6)
Serial Debug Interface
C2 Connector (J7)
Bottom View
Top View
Figure 1. Si8250 Multi-Phase POL Target Board
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Si825x Multi-Phase POL-RD
3. Si8250 Multi Phase POL Target Board Stand-Alone Operation
The POL target board comes preloaded with firmware algorithms, and is designed to provide a 3.3 V output with up
to 40 Amps of output current.
To operate the target board as a stand-alone power supply, perform the following steps:
1. Connect a VIN power supply to the VIN terminals (J1 and J2) as shown in Figure 2. Do not yet turn the power
supply on.
2. Connect a load to the VOUT terminals (J3 and J4) as shown in Figure 2. For initial testing, a 2 , 15 W resistor is
recommended. For higher output currents, an electronic load simulator can be used.
3. Turn the VIN supply on. The converter will start up and provide 3.3 V at VOUT.
VOUT
+
VIN
+
Electronic Load
Simulator or
Equivalent
(3.3 V, 40 A max)
Power Supply
(10–15 V, 10 A)
–
–
Top View
Figure 2. Board Power Configuration
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Si825x Multi-Phase POL-RD
4. Development/Debug Operation: Initial Hardware Setup
This section describes the use of the Si8250 Multi-Phase POL Target Board with the Silicon Laboratories
integrated development environment (IDE) and Application Builder tools. To configure the hardware for connection
to the IDE:
1. Connect a VIN power supply to the VIN terminals (J1 and J2) as shown in Figure 2. Do not yet turn the power
supply on.
2. Connect the USB Debug Adaptor’s ribbon cable to the Si8250 Multi-Phase POL Target Board at J7 as shown in
Figure 3.
3. Connect the USB cable to the USB Debug Adapter’s USB input plug.
4. Connect the USB cable from the USB Debug Adapter to a USB port on the PC.
5. Turn the VIN supply on.
Figure 3. Overall View of the Debug Connection (Load not Connected)
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Si825x Multi-Phase POL-RD
5. Development/Debug Operation: Software Setup
The Si825x Multi-Phase POL Reference Design comes with Application Builder software (detailed in "8. Si825x
Application Builder” on page 12), a configurable real-time software Kernel, and a software Kernel compiled
specifically for the Si8250 Multi-Phase POL Target Board.
The Kernel is royalty-free application software for the Si825x family of digital power controllers that greatly reduces
application program development time, effort, and engineering risk. The Application Builder is used to customize
the Kernel and create C-code source level application software for the Si825x end application. The Application
Builder directly modifies the source code in the Kernel, which is then compiled and downloaded to the Si825x. For
more information on the Kernel, see application note “AN271: Si8250 Real-Time Kernel Overview”.
The Multi_Phase_POL directory (SiLabs\Power\Reference_Designs\Multi_Phase_POL\Firmware) contains the
Kernel configured for the Si8250 Multi-Phase POL Target Board.
Kernel software can be loaded/reloaded to the target board using the Silicon Laboratories IDE. Note that hardware
must be set up as detailed in "4. Development/Debug Operation: Initial Hardware Setup” on page 4. Follow the
instructions below to configure and download the Multi_Phase_POL application software for the Si8250 MultiPhase POL Target Board.
Note: A thorough understanding of the IDE is required before one can use the development/Debug Mode of the kit. The IDE is
detailed in "7. Silicon Laboratories Integrated Development Environment".
1. The included CD-ROM contains the Silicon Laboratories Integrated Development Environment (IDE),
Application Builder examples, the PMBus Monitor, Keil software 8051 tools, and additional documentation.
Insert the CD-ROM into your PC’s CD-ROM drive. An installer will automatically launch allowing you to install
the software or read documentation by clicking buttons on the installation panel. If the installer does not
automatically start when you insert the CD-ROM, run autorun.exe found in the root directory of the CD-ROM.
Refer to the ReleaseNotes.txt file on the CD-ROM for the latest information regarding known problems and
restrictions. See "7. Silicon Laboratories Integrated Development Environment” on page 9 for further
information on the development tools.
2. Open the IDE by selecting Silicon LaboratoriesSilicon Laboratories IDE from the PC programs menu.
3. Next, the example project included with the kit is opened. Select ProjectOpen Project... from the IDE
menus. In the Project Workspace window, browse to the
“SiLabs\Power\Reference_Designs\Multi_Phase_POL\Firmware\Multi_phase_POL\Source” directory and
select the *.wsp project file. Press Open to close the window and open the project.
Note: This example will only work with the full version of the Keil compiler. If the demonstration compiler is used, use the
files in “SiLabs\Power\Reference_Designs\Multi_Phase_POL\Firmware\Multi_phase_POL_basic\Source”. This
code will compile to less than 4 kB of code.
4. The Si8250 Multi-Phase POL Target Board has several connection requirements that must be specified before
connecting to the board. Select OptionsConnection Options... from the IDE menu. In the Connection
Options window, select USB Debug Adapter in the Serial Adapter section. Next, select C2 in the Debug
Interface section. The Si825x family of devices use the Silicon Laboratories 2-wire (C2) debug interface. Click
OK to close the window.
5. Click the Connect button in the toolbar or select DebugConnect from the menu to connect to the device.
6. Build the project by clicking on the Build/Make Project button in the toolbar or by selecting ProjectBuild/
Make Project from the menu.
Note: After the project has been built the first time, the Build/Make Project command will only build the files that have
been changed since the previous build. To rebuild all files and project dependencies, click on the Rebuild All button
in the toolbar or select ProjectRebuild All from the menu.
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Si825x Multi-Phase POL-RD
7. Download the project to the target by clicking the Download Code button in the toolbar.
Note: To enable automatic downloading if the program build is successful, select Enable automatic connect/download
after build in the ProjectTarget Build Configuration dialog. If errors occur during the build process, the IDE will
not attempt the download.
8. Connect a load to the VOUT terminals (J3 and J4) as shown in Figure 2 on page 3. For initial testing, a 2 ,
15 W resistor is recommended. For higher output currents, an electronic load simulator can be used.
9. Run the converter firmware by pressing the “Go” button in the IDE toolbar. The converter will start up and
provide 3.3 V at VOUT.
10.Save the project when finished with the debug session to preserve the current target build configuration, editor
settings, and location of all open debug views. To save the project, select ProjectSave Project from the
menu.
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Si825x Multi-Phase POL-RD
6. PMBus Operation
PMBus is a connectivity solution designed for networking multiple power supplies using a single management bus.
The Real-time Kernel provided with the Si825x Multi-Phase POL Reference Design includes optional support for
PMBus. In addition, the Si825x POL design kit also comes with a PMBus Monitor application and USB to SMBus
Bridge Board to manage the power supply through PMBus.
1. The PMBus Monitor software is installed during the initial software setup. (See "5. Development/Debug
Operation: Software Setup” on page 5.)
2. Connect the board as shown in "3. Si8250 Multi Phase POL Target Board Stand-Alone Operation” on page 3.
Note that the PMBus Monitor may also be operated with the USB Debug Adaptor. If this is desired, connect the
target board as shown in "4. Development/Debug Operation: Initial Hardware Setup” on page 4.
3. Drivers must be installed to allow the PMBus Monitor to communicate with the USB to SMBus Bridge Board.
The driver files are located by default in the "Silabs\Power\Si825x AppBuilder\PMBus Monitor\USB-SMBus
Bridge Board Drivers" directory. Run the PreInstaller.exe application. This program will copy the driver files to
the PC's "Program Files" directory and then register the driver files so the board will be recognized when it is
connected. Windows Logo testing warnings may appear. Press the Continue Anyway button.
4. Connect the USB to SMBus Bridge Board to an available USB slot on your PC with a USB cable.
5. Windows will open a Found New Hardware Wizard window. Press Next after selecting the (Recommended)
option. Windows Logo testing warnings may appear. Press the Continue Anyway button. Press "Finish" to
finish installing the USB to SMBus Bridge Board.
6. Connect the Si8250 Multi-Phase POL Target Board to the USB to SMBus Bridge Board as shown in Figure 4.
Figure 4. USB to SMBus Bridge Board Connection (Load not Connected)
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Si825x Multi-Phase POL-RD
7. Open the Application Builder by selecting Silicon LaboratoriesSi825xApplication Builder from the PC
programs menu.
8. Run the PMBus Monitor application by selecting OptionsLaunch PMBus Monitor Tool from the Application
Builder. The window shown in Figure 5 will appear. The PMBus Monitor can be used to control and configure
the target board. The target can be enabled/disabled through the monitor. The PMBus Monitor allows
parameters, such as fault thresholds, to be changed. It also reports operating conditions and problems.
Figure 5. View of the PMBus Monitor
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Si825x Multi-Phase POL-RD
7. Silicon Laboratories Integrated Development Environment
The Silicon Laboratories IDE combines an editor, project manager, code development tools, and a debugger into a
single intuitive environment for code development and in-system debugging. No additional target RAM, program
memory, or communications channels are required. The use of third-party compilers and assemblers is also
supported. This development kit includes the Keil Software A51 macro assembler, BL51 linker, and evaluation
version C51 C compiler. These tools can be used from within the Silicon Laboratories IDE. Figure 6 shows the IDE.
Figure 6. IDE
7.1. System Requirements
Silicon Laboratories IDE requirements are as follows:
Pentium-class host PC running Microsoft Windows 95 or later or Microsoft Windows NT or later.
One available USB port.
64 MB RAM and 40 MB free HD space recommended.
7.2. Assembler and Linker
A full-version Keil A51 macro assembler and BL51 banking linker are included with the development kit and are
installed during IDE installation. The complete assembler and linker reference manual can be found online under
the Help menu in the IDE or in the “SiLabs\MCU\hlp” directory (A51.pdf).
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Si825x Multi-Phase POL-RD
7.3. Evaluation C51 C Compiler
An evaluation version of the Keil C51 C compiler is included with the development kit and is installed during IDE
installation. The evaluation version of the C51 compiler is the same as the full professional version except, that
code size is limited to 4 kB, and the floating point library is not included. The C51 compiler reference manual can
be found under the Help menu in the IDE or in the “SiLabs\MCU\hlp” directory (C51.pdf).
7.4. Using the Keil Software 8051 Tools with the Silicon Laboratories IDE
To perform source-level debugging with the IDE, you must configure the Keil 8051 tools to generate an absolute
object file in the OMF-51 format with object extensions and debug records enabled. You may build the OMF-51
absolute object file by calling the Keil 8051 tools at the command line (e.g. batch file or make file) or by using the
project manager built into the IDE. The default configuration when using the Silicon Laboratories IDE project
manager enables object extension and debug record generation. Refer to application note “AN104: Integrating Keil
8051 Tools Into the Silicon Labs IDE” for additional information on using the Keil 8051 tools with the Silicon
Laboratories IDE.
To build an absolute object file using the Silicon Laboratories IDE project manager, you must first create a project.
A project consists of a set of files, IDE configuration, debug views, and a target build configuration (list of files and
tool configurations used as input to the assembler, compiler, and linker when building an output object file).
The following sections illustrate the steps necessary to manually create a project with one or more source files,
build a program, and download the program to the target in preparation for debugging. (The IDE will automatically
create a single-file project using the currently open and active source file if you select “Build/Make Project” before a
project is defined.)
7.4.1. Creating a New Project
1. Select ProjectNew Project to open a new project and reset all configuration settings to default.
2. Select FileNew File to open an editor window. Create your source file(s) and save the file(s) with a
recognized extension, such as *.c, *.h, or *.asm, to enable color syntax highlighting.
3. Right-click on New Project in the Project Window. Select Add files to project. Select files in the file browser
and click “Open”. Continue adding files until all project files have been added.
4. For each of the files in the Project Window that you want assembled, compiled, and linked into the target build,
right-click on the file name and select Add file to build. Each file will be assembled or compiled as appropriate
(based on file extension) and linked into the build of the absolute object file.
Note: If a project contains a large number of files, the “Group” feature of the IDE can be used to organize them. Right-click
on New Project in the Project Window. Select Add Groups to project. Add predefined groups or add customized
groups. Right-click on the group name and choose Add file to group. Select files to be added. Continue adding files
until all project files have been added.
7.4.2. Building and Downloading the Program for Debugging
1. Once all source files have been added to the target build, build the project by clicking on the “Build/Make
Project” button in the toolbar or selecting ProjectBuild/Make Project from the menu.
Note: After the project has been built the first time, the Build/Make Project command will only build the files that have been
changed since the previous build. To rebuild all files and project dependencies, click on the “Rebuild All” button in the
toolbar or select Project->Rebuild All from the menu.
2. Before connecting to the target device, several connection options may need to be set. Open the “Connection
Options” window by selecting OptionsConnection Options... in the IDE menu. First, select the adapter that
was included with the kit in the “Serial Adapter” section. Next, the correct “Debug Interface” must be selected.
Si825x family devices use the Silicon Laboratories 2-wire (C2) debug interface. Once all the selections are
made, click the OK button to close the window.
3. Click the Connect button in the toolbar or select DebugConnect from the menu to connect to the device.
4. Download the project to the target by clicking the Download Code button in the toolbar.
Note: To enable automatic downloading if the program build is successful, select Enable automatic connect/download
after build in the ProjectTarget Build Configuration dialog. If errors occur during the build process, the IDE will
not attempt the download.
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Si825x Multi-Phase POL-RD
5. When finished with the debug session, save the project to preserve the current target build configuration, editor
settings, and the location of all open debug views. To save the project, select ProjectSave Project As... from
the menu. Create a new name for the project, and click on Save.
7.5. Si825x Debug Mode
The IDE contained in the Si825x Multi-Phase POL Reference Design has an online debug feature that optionally
enables the user to inspect or update special function registers (SFRs) in the Si825x while it is operating. For
example, filter coefficients can be optimized by simply typing in new coefficient values while the supply is
connected to a network analyzer and running. The IDE can also be operated in Standard mode where SFR inspect
and update is allowed only when the Si825x is not running. As shown in Figure 7, the IDE can be set for Online
Debug Mode or Standard Debug mode by clicking on the circled mode switch.
Figure 7. Si825x IDE Debug Modes
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Si825x Multi-Phase POL-RD
8. Si825x Application Builder
In addition to the IDE, the Si825x family is supported with an intuitive toolset that leverages traditional power supply
control design methods minimizing the digital supply design learning curve. The toolset consists of a real-time
firmware Kernel (C-language source code), and the Application Builder (see Figure 8). The Application Builder
includes device peripheral configuration options with the Peripheral Configuration Wizard. Additionally, the
Application Builder tools are used to modify Kernel operations. Three key development tools within the Application
Builder are the DPWM Timing Diagram Editor, the System Parameter Programmer, and the Compensation
Editor. These tools are detailed in the following sections. The flow diagrams for the Kernel are included on the CD.
Figure 8. Si825x Application Builder
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Si825x Multi-Phase POL-RD
8.1. DPWM Timing Diagram Editor
The DPWM Timing Diagram Editor permits designers to generate DPWM initialization code by simply drawing
the timing for their end system. The wizard accommodates up to six output phases and can be used to establish
positive or negative dead-times, relative edges, absolute edges, and other timing required by the end system.
Refer to the Si825x data sheet for a description of the different edges.
This example illustrates how to use the DPWM Timing Diagram Editor to create and simulate the timing for a
single-phase POL as well as generate the initialization code in the Kernel.
1. To open the DPWM Timing Diagram Editor window, open the Application Builder and select System
ConfigurationDPWM Timing Diagram Editor from the menu.
2. To create an absolute edge on Phase 1, hold the mouse above the Phase 1 zero timing line (default) at time tick
10. Then, either double click with the left mouse button or right-click at that point and select Absolute Edge. An
absolute edge at time tick 10 will be created (see Figure 9).
3. To finish the timing for Phase 1, specify hardware modulation using (Cu0). This event edge will be modulated
relative to its absolute edge at time tick 10. To create this edge, hold the mouse above the Phase 1 timing line to
the right of time tick 10 at time tick 60. Either double-click or right-click at that point and select Event (Cu0)
Edge. Next, select the edge to reference by clicking on edge 1 in Phase 1. A relative falling (Cu0) edge will be
created at time tick 60 since u(n) defaults to 50 (see Figure 9).
Figure 9. DPWM Timing Diagram Editor—Phase 1
1. Now, create the timing for Phase 2. For Phase 2, the goal is to create a relative rising edge relative to the falling
edge of Phase 1 and an absolute falling edge on Phase2 at time tick 505. To create the relative rising edge,
hold the mouse above the Phase 2 zero timing line (default) at time tick 100. Then, either double-click with the
left mouse button or right-click at that point and select Relative Edge. Next, select the edge to reference by
clicking on Phase 1’s falling edge. A relative edge at approximately time tick 90 will be created (see Figure 10).
2. To finish the timing for Phase 2, create an absolute falling at time tick 505. To create this edge, hold the mouse
above the Phase 2 timing line at time tick 505. Then, either double-click with the left mouse button or right-click
at that point and select Absolute Edge. An absolute edge at time tick 505 will be created (see Figure 10).
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Si825x Multi-Phase POL-RD
Figure 10. DPWM Timing Diagram Editor—Phase 2
3. Click the Simulate button to display the Simulate Window (see Figure 11). Use the arrows to increase and
decrease the value of u(n). Notice that Phase 1’s edge should modulate with its absolute edge starting at 10
ticks. Phase 2 should also modulate. However, its rising edge starts relative to Phase 1’s falling edge.
Figure 11. DPWM Timing Diagram Editor—Timing Simulator
4. Now that the desired timing for the two-phase system has been created, click on OK. The Application Builder
will automatically extract the correct DPWM timing initialization data for the Kernel. These coefficients can be
saved to a new project file if desired for later use. Click on FileSave Project to save this project. To generate
an IDE project, select FileBuild IDE Project... and select the directory for project generation.
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Si825x Multi-Phase POL-RD
8.2. Compensation Editor
The Compensation Editor is a loop simulation and coefficient generator tool for frequency compensating the
system. To open the Compensation Editor window, open the Application Builder and select System
ConfigurationCompensation Editor from the menu. The Compensation Editor for a buck regulator is shown in
Figure 12. As shown, this tool provides fields for the user to enter power stage parameters, such as the output filter
component and parasitic values; controller parameters, such as PWM frequency and pole/zero locations; and
Si825x-specific data, such as ADC sample frequency. The simulator comes pre-populated with default values for
the Si8250 Half-Bridge Target Board. These model parameters can be changed as desired to accommodate
other buck topologies. To view the gain and phase plots with the default parameters, click on the View Graphs
button, and their plots will be generated a short time later. Moreover, clicking on the View Graphs button, the user
can view different responses of the buck regulator. Sample graphs are shown in Figure 12.
Table 1 shows two frequency responses for the multi-phase POL: one for steady-state operation and one for
operation during a transient. During transients, the Si8250 automatically extends loop bandwidth by writing faster
coefficients to the loop compensation filter (DSP filter engine). This nonlinear control response improves system
transient response, reducing both the magnitude and duration of the output transient.
Table 1. Si8250 Multi-Phase POL Target Board’s Frequency Response
Loop Gain Bandwidth
Phase Margin
Steady-State Response
Transient Response
45 kHz
54º
95 kHz
25º
Figure 12. Compensation Editor, Input/Output Windows
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Si825x Multi-Phase POL-RD
8.3. System Parameter Programmer
The System Setting Programmer allows the designer to input all system settings (UVLO, OV, OCP, etc.) and then
converts these parameters to HEX and populates the resulting initialization code in the Kernel. To open the
System Settings window, open the Application Builder and select System ConfigurationSystem Settings
from the menu (see Figure 13).
.
Figure 13. System Parameters Window
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Si825x Multi-Phase POL-RD
8.4. Peripheral Configuration Wizard
The Peripheral Configuration Wizard can be used to automatically generate initialization code for the Si825x’s onchip peripherals (ADC2, comparator, UART, SMBusTM, etc.). The peripheral windows can be accessed by clicking
on the Peripherals menu in the Application Builder. Figure 14 illustrates the Port I/O window. For more details on
using this wizard, consult the “Help” file by clicking on HelpHelp....
Figure 14. Peripheral Configuration Wizard—Port I/O Window
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Si825x Multi-Phase POL-RD
9. Restoring Factory Defaults
The Si825x Multi-Phase POL Reference Design includes hex files created for the multi-phase POL application.
Downloading these hex files to the Si8250 Multi-Phase POL Target Board will restore the board to its factory
defaults.
9.1. Restoring the Si8250
To download the factory default Si8250 hex file to the target board, perform the following steps:
1. Connect the USB Debug Adaptor’s ribbon cable to the Si8250 Multi-Phase POL Target Board at J7 as shown in
Figure 3 on page 4.
2. Open the IDE by selecting Silicon LaboratoriesSilicon Laboratories IDE from the PC programs menu.
3. The Si8250 Multi-Phase POL Target Board has several connection requirements that need to be specified
before connecting to the board. Select OptionsConnection Options... from the IDE menu. In the
Connection Options window, select USB Debug Adapter in the Serial Adapter section. Next, select C2 in the
Debug Interface section. The Si825x family of devices use the Silicon Laboratories 2-wire (C2) debug interface.
Press OK to close the window.
4. Click the Connect button in the toolbar or select DebugConnect from the menu to connect to the device.
5. Select DebugDownload Object File... from the IDE menus to open the download window.
6. Press the Browse button to open the Download Filename... window.
7. In the List files of type: drop down box, select the Intel-Hex option.
8. Browse to the “SiLabs\Power\Reference_Designs\Multi_Phase_POL\Firmware\multi_phase_POL\hex”
directory and select the *.hex file. Press OK to close the window.
9. Press the Download button to download the file.
10.Click the Disconnect button in the toolbar, or select DebugDisconnect from the menu to disconnect from
the device.
11. Power cycle the device to run the downloaded program.
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10. Si8250 Multi-Phase POL Target Board
The Si8250 Multi-Phase POL Target Board has a Si8250-IQ installed. Refer to Figure 15 for the locations of the
various I/O connectors and major components.
J1, J2
J3, J4
J5, J4
J6
J7
JP1
LED
LED
RESET
VIN, Supply Input power connection 10-15 V, 10 A
VOUT, Supply output connection for load simulator
Alternate VOUT monitoring node
SMBus adapter
Si8250 Debug Interface
Si8250 ENABLE Polarity Select
VIN Power Good Indicator
VOUT Power Good indicator
Si8250 and Target Board Reset
J2
SENSE
-
L1
GND
J6
JP1
DEBUG
C76
C85
Driver
U1
Driver
J4
-
Reset
ENABLE
Power Good
Power In
MULTI PHASE POL
U2
C75
Q2
Q1
C83
AMP
Si825x
C80
Si825x
J5
C78
U4
U3
C82
C71
+
J3
C84
+
J1
VOUT
C79
Q3
Q4
VIN
C81
L2
GND
J7
Top View
Bottom View
Figure 15. Si8250 Multi-Phase POL Target Board
10.1. System Clock Sources
The Si8250-IQ device installed on the target board features a calibrated programmable internal oscillator that is
enabled as the system clock source on reset. After reset, the device operates at a frequency of 80 kHz by default
using the internal low-frequency oscillator but may be configured by software to operate at other frequencies. Refer
to the Si825x family data sheet for more information on configuring the system clock source.
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10.2. Switches and LEDs
One switch is provided on the target board. Switch S1 is connected to the RESET pin of the Si8250. Pressing S1
puts the Si8250 device into its hardware-reset state.
Two LEDs are also provided on the target board. The POWER IN LED is used to indicate that the POL target board
is properly powered. The POWER GOOD LED is used to indicate that VOUT power is being regulated by the
Si8250. See Table 2 for a description of each LED and on board switches.
Table 2. Target Board Switch and LED Descriptions
Label
Reference
Description
RST
S1
POWERIN
LED
Indicates that VIN is operating properly
POWERGOOD
LED
Indicates that VOUT is regulated properly
Si8250 Reset Switch
10.3. VIN (J1, J2)
The user-provided power supply should be connected to connectors J1 and J2 where J2 is the reference. The
power source must be from 10–15 V with at least 10 A maximum output.
Table 3. J1, J2 Pin Descriptions
Jumper #
Description
J1
10–15 V, 10 A
J2
GND
10.4. VOUT (J3, J4)
Connectors J3 and J4 are the dc output from the Si8250 Multi-Phase POL Target Board. A load (preferably
electronic) should be connected here.
Table 4. J3, J4 Pin Descriptions
Jumper #
Description
J3
3.3 V (Nominal), 40 A max
J4
GND
10.5. VOUT (J5, J4)
Connectors J5 and J4 provide an alternate output monitoring note that minimizes output loading while VOUT is
being monitored.
Table 5. J5, J4 Pin Descriptions
20
Jumper #
Description
J5
Alternate VOUT Sense, minimal loading
J4
GND
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10.6. SMBus Connector (J6)
The J6 connector is the SMBus interface connector for the Si8250 Multi-Phase POL Target Board. Table 6 shows
the J6 pin definitions.
Table 6. J6 Pin Descriptions
Pin #
Description
1
SCL
2
DGND
3
SDA
4
DGND
5
SMBA
6
DGND
10.7. Si8250 DEBUG Interface (J7)
The Si8250 DEBUG connector (J7) provides access to the DEBUG (C2) pins of the Si8250 device on the target
board. It is used to connect the USB Debug Adapter to the target board for in-circuit debugging and programming.
Table 7 shows the J7 Si8250 DEBUG pin definitions.
Table 7. P1 Si8250 DEBUG Connector Pin Descriptions
Pin #
Description
1
+2.5 V
2, 3, 9
DGND
4
C2D
7
RST/C2CK
5, 6, 8, 10
Not Connected
10.8. Si8250 ENABLE Polarity Select (JP1)
The JP1 jumper selects the polarity of the reset line for the Si8250. When installed, the reset signal is active high;
otherwise, it is active low.
10.9. Voltage and Current Sense Test Points
The Si8250 Multi-Phase POL Target Board has several test points for VREF, VINSENSE, IIN, VSENSE, all PHn, IPK,
and more. These test points correspond to the respective pins on the Si8250-IQ integrated circuit as well as other
useful inspection points. See “12. Schematics” on page 23.
Rev. 0.2
21
Si825x Multi-Phase POL-RD
11. USB Debug Adapter
The USB Debug Adapter provides the interface between the PC’s USB port and the Si825x’s in-system debug/
programming circuitry. The attached 10-pin DEBUG ribbon cable connects the adapter to the target board and the
target device’s debug interface signals. (The USB Debug Adapter supports both Silicon Laboratories JTAG and C2
debug interfaces.) Power is provided to the adapter from the USB connection to the PC. The USB Debug Adapter
is capable of providing power to a circuit board via pin 10 of the DEBUG connector. The Si8250 Multi-Phase POL
Target Board is not designed to be powered from this source. Table 8 shows the pin definitions for the DEBUG
ribbon cable connector.
Note: The USB Debug Adapter requires a target system clock of 32 kHz or greater.
With the default settings, the USB Debug Adapter can supply up to 100 mA to a target system.
Table 8. USB Debug Adapter DEBUG Connector Pin Descriptions
Pin #
Description
1, 8
Not Connected
2, 3, 9
GND (Ground)
4
TCK (C2D)
5
TMS
6
TDO
7
TDI (C2CK)
10
USB Power
DEBUG
Ribbon Cable
USB DEBUG ADAPTER
Run
Stop
Power
USB Connector
Figure 16. USB Debug Adapter
22
Rev. 0.2
J2
PGND
Rev. 0.2
REM_S
VOUT_S
PGND_S
0R1
0R1
DGND
REM_S
VOUT_S
PGND_S
R7
R8
C22
0.1uF
PGND
0R1
0R1
C4
1uF25V
PGND
C2
1uF25V
R5
R6
PGND
C21
0.1uF
DGND
PGND
Signal AC return
TP7
PH3
PH3
PH4
PH1
PH2
TP6
PH1
-
VIN
470uF25V
C71
VIN
VIN
LM5101AM
VCC
HI
LI
GND
U1
HB
HO
HS
LO
2
3
4
8
SG2
C1
1uF25V
TG1
PH1_PWR
PH2_PWR
R2
CR2
R1
CR1
4R7
BAS16X
4R7
BAS16X
1
5
6
7
SG4
C3
1uF25V
TG3
BAS16X
4R7
DGND
DGND
GNDA
GNDA
4R7
BAS16X
PGND
PGND
R4
CR4
R3
CR3
PHASE2
Cu pours
PHASE1
C73
47uF25V
4
PGND
4
Q4
HAT2165H
G4
Q3
HAT2165H
PH2_PWR
PGND
Q2
HAT2165H
G4
Q1
HAT2165H
PH1_PWR
C75
47uF25V
PH1_PWR
D
S
D
S
plane
PHASE2
plane
PHASE1
PGND
25V X5R C1210
L2
L1
0.95uH
0.95uH
C76
C74
PH2_PWR
47uF25V
6.3V X5R
C1210
NOTE: GNDA plane
NOTE: PGND plane
C85
C84
C83
C82
PGND
PGND
NOTE: PGND plane
6.3V X5R
C1210
NOTE: VOUT PWR plane
C81
C80
C79
C78
Figure 17. Si8250 Multi-Phase POL Target Board Schematic (Power)
NOTE: separate path to
digital GND
NOTE: Analog - Quiet GND
NOTE: high current path
to J2 GND
NOTE: Route as a Differential Pair
HB
HO
HS
LO
2
3
4
8
Note: Cb > 100 * Q Ciss
LM5101AM
VCC
HI
LI
GND
U2
NOTE: Keep PHASE1,2 PH1,2 _PWR and PH1,2 _GND nets short, seperate, use
1
5
6
7
NOTE: 10A high current
path, use plane/pour
47uF25V
J1
5
3
2
1
5
3
2
1
VIN
100uF_Cer
100uF_Cer
+
100uF_Cer
100uF_Cer
NOTE: These nets are connected at a common plane,
they are kept seperate until that connection to
avoid circulating currents between the phases.
100uF_Cer
100uF_Cer
5
3
2
1
5
3
2
1
100uF_Cer
100uF_Cer
NOTE: Trace to VIN sense
network, Place near J1
(1-5V 3.3V nom)
R11
0R1
R10
0R1
J4
J5
-
+
REMOTE_SENSE
PGND
VOUT
R16
10
J3
NOTE: Sense Traces to
VOUT, Place near
J3,J4
NOTE: Remove R11,R10
before final routing
VIN
Si825x Multi-Phase POL-RD
12. Schematics
23
C72
SHDN
1K
R77
NOTE: high current path
to J2 GND
DGND
DGND
PGND
PGND
GNDA
GNDA
1K
R78
NOTE: Analog - Quiet GND
4
5
C25
0.01uF
1K
BYP
OUT
R79
P0.2_SMBA
P0.1_SDA
P0.0_SCL
V2V5
P1.5_PWR_GOOD
P1.6_PWR_IN
PH1
PH2
PH3
PH4
P0.7_PS_EN
RST_C2CK
P1.7_CD
Digital GND
NOTE: separate path to
digital GND
1uF25V
3
U5
LP2985AIM5-2.5
IN
GND
2
1
R12
0R1
P0.6
P0.5
P0.4
P0.3 / XCLK
P0.2
P0.1
P0.0
P1.5
P1.6
PH1
PH2
PH3
PH4
PH5
PH6
P0.7
V2V5
C95
0.1uF
DGND
DGND
4.7uF_6V3
C94
DGND
V2V5
RST / C2CK
P1.7 / C2D
DGND
R21
10uF_6V3
C89
FB1
100M500mA
Digital GND
18
19
20
21
22
23
24
14
15
32
31
30
27
26
25
17
1
16
V2V5
13
28
VDD
VDD
GND
GND
29
12
0
U3
SI-8250
Analog
GND
6
8
10
9
IOSENSE2
TP2
IOSENSE1
TP1
VINSENSE
7
2
VOSENSE1
VOSENSE
TP4
GNDA
1uF
GNDA
VREM
IOUT2
GNDA
DNP
R76
DNP
R75
(DNP)
R74
249
V2V5A
47pF_NPO
C46
V25A
4.7uF_6V3
C90
VREF1V2
IOUT1
GNDA
11
3
0.1uF
C91
Analog GND
C87
TP8
(DNP)
U6
LM4051BIM3-12
IOSENSE2
IOSENSE1
IOSENSE2
DNP
10uF_6V3
DNP
GNDA
C93
R34
GNDA
10uF_6V3
C92
R66
GNDA
215, 0.5%
R69
3.00K, 0.5%
R68
VIN
VIN
VOSENSE1
REM_S
C12
0.01uF
1K
C43
0.01uF
1K
VIN
IOUT2
R32
24K
8
R64
24K
GNDA
IOUT1
14
1uF
C42
6800pF_NPO
C45
TP3
VINSENSE
4.02K, 0.1%
R17
9.31K, 0.5%
R18
REM_S
R36
DNP
R61
VINSENSE
DNP
R23
VOSENSE
IOSENSE1
VINSENSE
VOSENSE
R22
VIN
PGND_S
4.42K, 0.5%
R20
10.2K, 0.5%
R19
VOUT_S
PGND_S
1uF
C31
VOUT_S
13
-
9
-
GNDA
10
+
PGND_S
R35
24K
R31
R65
R67
24K
R63
R33
U4C
TLV2374IPWR
GNDA
12
+
U4D
TLV2374IPWR
1K
1K
1K
1K
7
1
VIN
VIN
2
-
6
-
GNDA
5
+
U4B
TLV2374IPWR
GNDA
3
+
U4A
TLV2374IPWR
VOUT_S
1K
PGND_S
C10
0.1uF
R30
1K
VOUT_S
C41
0.1uF
R62
TLC084CPWPR is TSSOP-20
TLV2374IPW is TSSOP14
Both parts will fit footprint, place device pin 1 to pin 1on board,
un-used pins TLV2374 are NC and TLC084C pins 8-13 are NC
VOSENSE1
Figure 18. Si8250 Multi-Phase POL Target Board Schematic (Control)
DGND
C97
0.1uF
P1.1 / AIN1
4.7uF_6V3
DGND
P1.2
IPK
P1.3 / AIN3
GNDA
C96
P1.4
VSENSE
VREF
P1.0 / AIN0
V2V5A
0.1uF
10uF_6V3
GNDA
C86
C88
V2V5A
4
11
5
VDDA
GNDA
4
4
11
4
11
Rev. 0.2
4
24
11
VIN
PHASE2
PGND_S
VOUT_S
PHASE1
Si825x Multi-Phase POL-RD
DGND
JP1
1
3
5
A
2
4
6
SCL
SDA
SMBA
1uF
R73
R72
200
200
DGND A1
A2
8
D6
A2
V2V5
8
K1
K2
RN2A 24
1
V2V5
RN2B 24
7
2
RN2C 24
6
3
K1
K2
RN2D 24
5
4
P1.5_PWR_GOOD
P1.6_PWR_IN
P0.7_PS_EN
P0.0_SCL
P0.1_SDA
P0.2_SMBA
RN3A
24
1
DGND
24
P0.7_PS_EN
P0.0_SCL
P0.1_SDA
P0.2_SMBA
RN3B
D8
BAS70DW-04TP
8
RST_B
1uF
C32
1
4
DGND
1
3
5
7
9
DGND
V2V5
2
4
6
8
10
604
4
3
1
2
A2
AC2
AC1
C2
A1
RST_C2CK
P1.7_CD
24
RN3D
24
RN3C
DGND
RST_C2CK
P1.7_CD
Note: Orient J10 with Pin 1 to bottom,left
SI-8250_RST
RESET
R70
C1
2
3
J7
SI-8250_DEBUG
DGND DGND
V2V5
0.1uF
C33
Figure 19. Si8250 Multi-Phase POL Target Board Schematic (Debug)
RN1A 24
1
DGND A1
BAS70DW-04TP
RN1B 24
SMBA 7
2
RN1C 24
SDA 6
3
D7
BAS70DW-04TP
RN1D 24
SCL 5
4
EXT_ENABLE
C35
1K
C
C
Green
Green
V2V5
Pgood
DGND
R80
J6
PMBus
V2V5
Pin
A
1K
R71
AC1
A1
V2V5
1
2
AC2
AC1
AC2
Rev. 0.2
AC1
7
2
K1
A2
6
3
4
5
K2
AC2
V2V5
Si825x Multi-Phase POL-RD
25
Si825x Multi-Phase POL-RD
13. Bill of Materials
Table 9. Si825x Multi-Phase POL Reference Design Bill of Materials
Item
Qty
Reference
Part Number
Manufacturer
Description
1
4
CR1,CR2,CR3,CR4
BAS16XV2T1GOSCT-ND
Digi-Key
BAS16X
2
4
C1,C2,C3,C4
587-1248-1-ND
Digi-Key
1 uF, 25 V
3
9
C10,C21,C22,C33,C41,C86,
C91,C95,C97
PCC2277CT-ND
Digi-Key
0.1 uF, 25 V
4
3
C12,C25,C43
478-1227-1-ND
Digi-Key
0.01 uF, 50 V
5
5
C31,C32,C35,C42,C87
PCC1915CT-ND
Digi-Key
1 uF, 6.3 V
6
1
C45
Venkel
6800 pF_NPO
7
1
C46
311-1065-1-ND
Digi-Key
47 pF_NPO
8
1
C71
565-2224-1-ND
Digi-Key
470 uF, 25 V
9
1
C72
PCC1893CT-ND
Digi-Key
1 uF, 25 V
10
4
C73,C74,C75,C76
587-1413-2-ND
Digi-Key
47 uF, 25 V
11
8
C78,C79,C80,C81,C82,C83,
C84,C85
587-1387-2-ND
Digi-Key
100 uF_Cer, 6.3 V
12
4
C88,C89,C92,C93
PCC2395CT-ND
Digi-Key
10 uF, 6.3 V
13
3
C90,C94,C96
PCC2318CT-ND
Digi-Key
4.7 uF, 6.3 V
14
3
D6,D7,D8
BAS70DW-04-DICT-ND
Digi-Key
BAS70DW-04TP
15
1
FB1
240-2362-1-ND
Digi-Key
100M500 mA
16
1
JP1
WM4000-ND
Digi-Key
JUMPER1x2
17
1
J1
2551-2-00-44-00-00-07-0
Bisco
VIN
18
2
J2,J4
2551-2-00-44-00-00-07-0
Bisco
PGND
19
1
J3
2551-2-00-44-00-00-07-0
Bisco
VOUT
20
1
J5
2551-2-00-44-00-00-07-0
Bisco
REMOTE_SENSE
21
1
J6
S4416-ND
Digi-Key
PMBus
22
1
J7
MHB10K-ND
Digi-Key
SI-8250_DEBUG
23
2
L2, L1
871-B82559A951A13
Mouser
0.95 uH
24
2
Pin, Pgood
67-1549-1-ND
Digi-Key
Green
25
4
Q1,Q2,Q3,Q4
SiLabs
HAT2165H
26
1
RESET
P8046SCT-ND
Digi-Key
SI-8250_RST
27
3
RN1,RN2,RN3
Y7240CT-ND
Digi-Key
24, 5%
28
4
R1,R2,R3,R4
P4.7ACT-ND
Digi-Key
4R7, 5%
29
5
R5,R6,R7,R8,R12
P.10AHCT-ND
Digi-Key
0R1, 5%
26
Rev. 0.2
Si825x Multi-Phase POL-RD
Table 9. Si825x Multi-Phase POL Reference Design Bill of Materials (Continued)
Item
Qty
Reference
Part Number
Manufacturer
Description
30
2
R11,R10
P.10AHCT-ND
Digi-Key
0R1, 5%
31
1
R16
P10GCT-ND
Digi-Key
10, 5%
32
1
R17
RR08P4.02KBCT-ND
Digi-Key
4.02 K, 0.1%
33
1
R18
RR08P9.31KDCT-ND
Digi-Key
9.31 K, 0.5%
34
1
R19
RR08P10.2KDCT-ND
Digi-Key
10.2 K, 0.5%
35
1
R20
RN731JTTDK4421B25
Garrett
4.42 K, 0.5%
36
1
R21
P0.0GCT-ND
Digi-Key
0
37
2
R22,R23
Venkel
DNP
38
13
R30,R31,R33,R34,R62,R63,
R65,R66,R71,R77,R78,R79,
R80
P1.00KHCT-ND
Digi-Key
1 K, 1%
39
4
R32,R35,R64,R67
P24KGCT-ND
Digi-Key
24 K, 5%
40
3
R36,R61,R75
41
1
R68
42
1
R69
43
1
R70
44
2
45
DNP
RR08P3.01KDCT-ND
Digi-Key
3.00 K, 0.5%
Digi-Key
215, 0.5%
P604HCT-ND
Digi-Key
604, 1%
R73,R72
P200HCT-ND
Digi-Key
200, 1%
1
R74
P249HCT-ND
(DNP) Digi-Key
249, 5%
46
1
R76
47
1
TP1
5002K-ND
Digi-Key
IOUT1
48
1
TP2
5002K-ND
Digi-Key
IOUT2
49
1
TP3
5002K-ND
Digi-Key
VINSENSE
50
1
TP4
5002K-ND
Digi-Key
VREM
51
1
TP6
5002K-ND
Digi-Key
PH1
52
1
TP7
5002K-ND
Digi-Key
PH3
53
1
TP8
5002K-ND
Digi-Key
V25A
54
2
U1,U2
LM5101M-ND
Digi-Key
LM5101AM
55
1
U3
SiLabs
Si-8250
56
1
U4
595-TLV2374IPWR
Mouser
TLV2374IPWR
57
1
U5
LP2985AIM5-2.5CT-ND
Digikey
LP2985AIM5-2.5
58
1
U6
LM405
(DNP) Digi-Key
LM4051BIM3-12
DNP
Rev. 0.2
27
Si825x Multi-Phase POL-RD
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
Updated board photos in Figure 1, “Si8250 Multi-Phase POL Target Board,” on page 2 and Figure 2, “Board
Power Configuration,” on page 3.
Updated PMBus part number (Item 21) in Section "13. Bill of Materials” on page 26.
28
Rev. 0.2
Si825x Multi-Phase POL-RD
NOTES:
Rev. 0.2
29
Si825x Multi-Phase POL-RD
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: MCUinfo@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
The sale of this product contains no licenses to Power-One’s intellectual property. Contact Power-One, Inc. for appropriate licenses.
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
30
Rev. 0.2
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