Si1010/1/2/3/4/5
Ultra Low Power, 64/32 kB, 10-Bit ADC
MCU with Integrated 240–960 MHz EZRadioPRO® Transceiver
Ultra Low Power: 0.9 to 3.6 V Operation
- Typical sleep mode current < 0.1 µA; retains state and
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10-Bit or 12-Bit Analog to Digital Converter
- Up to 300 ksps
- Up to 18 external inputs
- External pin or internal VREF (no external capacitor
Digital Peripherals
- 12 port I/O plus 3 GPIO pins; Hardware enhanced UART,
D
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Frequency range = 240–960 MHz
Sensitivity = –121 dBm
FSK, GFSK, and OOK modulation
Max output power = +20 dBm (Si1010/1), +13 dBm
(Si1012/3/4/5)
RF power consumption
- 18.5 mA receive
- 18 mA @ +1 dBm transmit
- 30 mA @ +13 dBm transmit
- 85 mA @ +20 dBm transmit (Si1010/1)
Data rate = 0.123 to 256 kbps
Auto-frequency calibration (AFC)
Antenna diversity and transmit/receive switch control
Programmable packet handler
TX and RX 64 byte FIFOs
Frequency hopping capability
On-chip crystal tuning
-
RAM contents over full supply range; fast wakeup of < 2 µs
Less than 600 nA with RTC running
Less than 1 µA with RTC running and radio state retained
On-chip dc-dc converter allows operation down to 0.9 V.
Two built-in brown-out detectors cover sleep and active
modes
required)
Built-in temperature sensor
External conversion start input option
Autonomous burst mode with 16-bit automatic averaging
accumulator
Dual Comparators
- Programmable hysteresis and response time
- Configurable as interrupt or reset source
- Low current (< 0.5 µA)
On-Chip Debug
- On-chip debug circuitry facilitates full-speed, non-intrusive
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EZRadioPRO® Transceiver
SPI, and I2C serial ports available concurrently
Low power 32-bit SmaRTClock
Four general purpose 16-bit counter/timers; six channel
programmable counter array (PCA)
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in-system debug (No emulator required)
- Provides breakpoints, single stepping
- Inspect/modify memory and registers
- Complete development kit
High-Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of instruc-
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Clock Sources
- Precision internal oscillators: 24.5 MHz with ±2% accuracy
supports UART operation; spread-spectrum mode for
reduced EMI; Low power 20 MHz internal oscillator
External oscillator: Crystal, RC, C, CMOS clock
SmaRTClock oscillator: 32.768 kHz crystal or self-oscillate
Can switch between clock sources on-the-fly; useful in
power saving modes and in implementing various power
saving modes
tions in 1 or 2 system clocks
Up to 25 MIPS throughput with 25 MHz clock
Expanded interrupt handler
-
Flash; In-system programmable
Package
- 42-pin LGA (5 x 7 mm)
Temperature Range: –40 to +85 °C
ANALOG
PERIPHERALS
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Rev. 1.2 2/13
12/10-bit
75/300 ksps
ADC
TEMP
SENSOR
VREF
VREG
IREF
+
+
–
–
VOLTAGE
COMPARATORS
DIGITAL I/O
UART
SMBus
SPI
PCA
Timer 0
Timer 1
Timer 2
Timer 3
CRC
Port 0
CROSSBAR
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Memory
- 768 bytes RAM 16 kB (Si1010/2/4) or 8 kB (Si1011/3/5)
EZRadio
PRO
Serial
Interface
Port 1
Port 2
24.5 MHz PRECISION
INTERNAL OSCILLATOR
20 MHz LOW POWER
INTERNAL OSCILLATOR
External Oscillator
HARDWARE smaRTClock
HIGH-SPEED CONTROLLER CORE
16/8 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(25 MIPS)
DEBUG
CIRCUITRY
EZRadioPRO
(240–960 MHz)
768 B SRAM
LNA
PA
Mixer
PGA
ADC
Digital
Modem
Digital
Logic
POR
PLL
Delta
Sigma
Modulator
OSC
WDT
Copyright © 2013 by Silicon Laboratories
Si1010/1/2/3/4/5
Si1010/1/2/3/4/5
Table of Contents
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1. System Overview ..................................................................................................... 20
1.1. Typical Connection Diagram ............................................................................. 24
1.2. CIP-51™ Microcontroller Core .......................................................................... 25
1.2.1. Fully 8051 Compatible .............................................................................. 25
1.2.2. Improved Throughput................................................................................ 25
1.2.3. Additional Features ................................................................................... 25
1.3. Port Input/Output ............................................................................................... 26
1.4. Serial Ports ........................................................................................................ 27
1.5. Programmable Counter Array............................................................................ 27
1.6. SAR ADC with 16-Bit Auto-Averaging Accumulator and Autonomous
Low Power Burst Mode ..................................................................................... 28
1.7. Programmable Current Reference (IREF0)....................................................... 29
1.8. Comparators...................................................................................................... 29
2. Ordering Information ............................................................................................... 31
3. Pinout and Package Definitions ............................................................................. 32
4. Electrical Characteristics ........................................................................................ 43
4.1. Absolute Maximum Specifications..................................................................... 43
4.2. Electrical Characteristics ................................................................................... 44
4.3. EZRadioPRO® Electrical Characteristics .......................................................... 68
4.4. Definition of Test Conditions for the EZRadioPRO Peripheral .......................... 75
5. SAR ADC with 16-Bit Auto-Averaging Accumulator and Autonomous
Low Power Burst Mode........................................................................................... 76
5.1. Output Code Formatting .................................................................................... 77
5.2. Modes of Operation ........................................................................................... 78
5.2.1. Starting a Conversion................................................................................ 78
5.2.2. Tracking Modes......................................................................................... 79
5.2.3. Burst Mode................................................................................................ 80
5.2.4. Settling Time Requirements...................................................................... 82
5.2.5. Gain Setting .............................................................................................. 82
5.3. 8-Bit Mode ......................................................................................................... 83
5.4. 12-Bit Mode ....................................................................................................... 83
5.5. Low Power Mode............................................................................................... 83
5.6. Programmable Window Detector....................................................................... 91
5.6.1. Window Detector In Single-Ended Mode .................................................. 93
5.6.2. ADC0 Specifications ................................................................................. 93
5.7. ADC0 Analog Multiplexer .................................................................................. 94
5.8. Temperature Sensor.......................................................................................... 96
5.8.1. Calibration ................................................................................................. 96
5.9. Voltage and Ground Reference Options ........................................................... 99
5.10. External Voltage References......................................................................... 100
5.11. Internal Voltage References .......................................................................... 100
5.12. Analog Ground Reference............................................................................. 100
5.13. Temperature Sensor Enable ......................................................................... 100
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5.14. Voltage Reference Electrical Specifications .................................................. 101
6. Programmable Current Reference (IREF0).......................................................... 102
6.1. PWM Enhanced Mode..................................................................................... 102
6.2. IREF0 Specifications ....................................................................................... 103
7. Comparators........................................................................................................... 104
7.1. Comparator Inputs........................................................................................... 104
7.2. Comparator Outputs ........................................................................................ 105
7.3. Comparator Response Time ........................................................................... 106
7.4. Comparator Hysteresis.................................................................................... 106
7.5. Comparator Register Descriptions .................................................................. 107
7.6. Comparator0 and Comparator1 Analog Multiplexers ...................................... 111
8. CIP-51 Microcontroller........................................................................................... 114
8.1. Performance .................................................................................................... 114
8.2. Programming and Debugging Support ............................................................ 115
8.3. Instruction Set.................................................................................................. 115
8.3.1. Instruction and CPU Timing .................................................................... 115
8.4. CIP-51 Register Descriptions .......................................................................... 119
9. Memory Organization ............................................................................................ 123
9.1. Program Memory............................................................................................. 123
9.1.1. MOVX Instruction and Program Memory ................................................ 124
9.2. Data Memory ................................................................................................... 124
9.2.1. Internal RAM ........................................................................................... 124
9.2.2. External RAM .......................................................................................... 125
10. On-Chip XRAM ..................................................................................................... 126
10.1. Accessing XRAM........................................................................................... 126
10.1.1. 16-Bit MOVX Example .......................................................................... 126
10.1.2. 8-Bit MOVX Example ............................................................................ 126
10.2. Special Function Registers............................................................................ 126
11. Special Function Registers................................................................................. 128
11.1. SFR Paging ................................................................................................... 129
12. Interrupt Handler.................................................................................................. 134
12.1. Enabling Interrupt Sources ............................................................................ 134
12.2. MCU Interrupt Sources and Vectors.............................................................. 134
12.3. Interrupt Priorities .......................................................................................... 135
12.4. Interrupt Latency............................................................................................ 135
12.5. Interrupt Register Descriptions ...................................................................... 137
12.6. External Interrupts INT0 and INT1................................................................. 144
13. Flash Memory....................................................................................................... 146
13.1. Programming the Flash Memory ................................................................... 146
13.1.1. Flash Lock and Key Functions .............................................................. 146
13.1.2. Flash Erase Procedure ......................................................................... 147
13.1.3. Flash Write Procedure .......................................................................... 147
13.2. Non-Volatile Data Storage............................................................................. 147
13.3. Security Options ............................................................................................ 148
13.4. Determining the Device Part Number at Run Time ....................................... 150
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13.5. Flash Write and Erase Guidelines ................................................................. 151
13.5.1. VDD Maintenance and the VDD Monitor .............................................. 151
13.5.2. PSWE Maintenance .............................................................................. 151
13.5.3. System Clock ........................................................................................ 152
13.6. Minimizing Flash Read Current ..................................................................... 153
14. Power Management ............................................................................................. 157
14.1. Normal Mode ................................................................................................. 158
14.2. Idle Mode....................................................................................................... 158
14.3. Stop Mode ..................................................................................................... 159
14.4. Suspend Mode .............................................................................................. 160
14.5. Sleep Mode ................................................................................................... 161
14.6. Configuring Wakeup Sources........................................................................ 162
14.7. Determining the Event that Caused the Last Wakeup................................... 162
14.8. Power Management Specifications ............................................................... 165
15. Cyclic Redundancy Check Unit (CRC0)............................................................. 166
15.1. 16-Bit CRC Algorithm .................................................................................... 166
15.2. 32-bit CRC Algorithm..................................................................................... 168
15.3. Preparing for a CRC Calculation ................................................................... 169
15.4. Performing a CRC Calculation ...................................................................... 169
15.5. Accessing the CRC0 Result .......................................................................... 169
15.6. CRC0 Bit Reverse Feature............................................................................ 174
16. On-Chip DC-DC Converter (DC0)........................................................................ 175
16.1. Startup Behavior............................................................................................ 176
16.2. High Power Applications ............................................................................ 177
16.3. Pulse Skipping Mode..................................................................................... 177
16.4. Enabling the DC-DC Converter ..................................................................... 177
16.5. Minimizing Power Supply Noise .................................................................... 179
16.6. Selecting the Optimum Switch Size............................................................... 179
16.7. DC-DC Converter Clocking Options .............................................................. 179
16.8. DC-DC Converter Behavior in Sleep Mode ................................................... 180
16.9. Bypass Mode................................................................................................. 180
16.10. Low Power Mode......................................................................................... 181
16.11. Passive Diode Mode.................................................................................... 181
16.12. DC-DC Converter Register Descriptions ..................................................... 182
16.13. DC-DC Converter Specifications ................................................................. 184
17. Voltage Regulator (VREG0)................................................................................. 185
17.1. Voltage Regulator Electrical Specifications ................................................... 185
18. Reset Sources ...................................................................................................... 186
18.1. Power-On (VBAT Supply Monitor) Reset ...................................................... 187
18.2. Power-Fail (VDD_MCU/DC+ Supply Monitor) Reset .................................... 189
18.3. External Reset ............................................................................................... 192
18.4. Missing Clock Detector Reset ....................................................................... 192
18.5. Comparator0 Reset ....................................................................................... 192
18.6. PCA Watchdog Timer Reset ......................................................................... 192
18.7. Flash Error Reset .......................................................................................... 192
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18.8. SmaRTClock (Real Time Clock) Reset ......................................................... 193
18.9. Software Reset .............................................................................................. 193
19. Clocking Sources................................................................................................. 195
19.1. Programmable Precision Internal Oscillator .................................................. 196
19.2. Low Power Internal Oscillator........................................................................ 196
19.3. External Oscillator Drive Circuit..................................................................... 196
19.3.1. External Crystal Mode........................................................................... 196
19.3.2. External RC Mode................................................................................. 198
19.3.3. External Capacitor Mode....................................................................... 199
19.3.4. External CMOS Clock Mode ................................................................. 199
19.4. Special Function Registers for Selecting and Configuring the
System Clock................................................................................................. 200
20. SmaRTClock (Real Time Clock).......................................................................... 204
20.1. SmaRTClock Interface .................................................................................. 204
20.1.1. SmaRTClock Lock and Key Functions.................................................. 205
20.1.2. Using RTC0ADR and RTC0DAT to Access SmaRTClock
Internal Registers.................................................................................. 205
20.1.3. RTC0ADR Short Strobe Feature........................................................... 206
20.1.4. SmaRTClock Interface Autoread Feature ............................................. 206
20.1.5. RTC0ADR Autoincrement Feature........................................................ 207
20.2. SmaRTClock Clocking Sources .................................................................... 210
20.2.1. Using the SmaRTClock Oscillator with a Crystal or
External CMOS Clock ........................................................................... 210
20.2.2. Using the SmaRTClock Oscillator in Self-Oscillate Mode..................... 211
20.2.3. Using the Low Frequency Oscillator (LFO) ........................................... 211
20.2.4. Programmable Load Capacitance......................................................... 211
20.2.5. Automatic Gain Control (Crystal Mode Only) and SmaRTClock
Bias Doubling ........................................................................................ 212
20.2.6. Missing SmaRTClock Detector ............................................................. 213
20.2.7. SmaRTClock Oscillator Crystal Valid Detector ..................................... 214
20.3. SmaRTClock Timer and Alarm Function ....................................................... 214
20.3.1. Setting and Reading the SmaRTClock Timer Value ............................. 214
20.3.2. Setting a SmaRTClock Alarm ............................................................... 214
20.3.3. Software Considerations for using the SmaRTClock
Timer and Alarm ................................................................................... 215
21. Port Input/Output ................................................................................................. 220
21.1. Port I/O Modes of Operation.......................................................................... 221
21.1.1. Port Pins Configured for Analog I/O...................................................... 221
21.1.2. Port Pins Configured For Digital I/O...................................................... 221
21.1.3. Interfacing Port I/O to 5 V and 3.3 V Logic............................................ 222
21.1.4. Increasing Port I/O Drive Strength ........................................................ 222
21.2. Assigning Port I/O Pins to Analog and Digital Functions............................... 222
21.2.1. Assigning Port I/O Pins to Analog Functions ........................................ 222
21.2.2. Assigning Port I/O Pins to Digital Functions.......................................... 223
21.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions ... 223
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21.3. Priority Crossbar Decoder ............................................................................. 224
21.4. Port Match ..................................................................................................... 229
21.5. Special Function Registers for Accessing and Configuring Port I/O ............. 232
22. EZRadioPRO Serial Interface (SPI1)................................................................... 240
22.1. Signal Descriptions........................................................................................ 241
22.1.1. Master Out, Slave In (MOSI)................................................................. 241
22.1.2. Master In, Slave Out (MISO)................................................................. 241
22.1.3. Serial Clock (SCK) ................................................................................ 241
22.1.4. Slave Select (NSS) ............................................................................... 241
22.2. SPI Master Operation on the MCU Core Side............................................... 241
22.3. SPI Slave Operation on the EZRadioPRO Peripheral Side........................... 241
22.4. EZRadioPRO Serial Interface Interrupt Sources ........................................... 244
22.5. Serial Clock Phase and Polarity .................................................................... 244
22.6. SPI Special Function Registers ..................................................................... 245
23. EZRadioPRO® 240–960 MHz Transceiver.......................................................... 250
23.1. EZRadioPRO Operating Modes .................................................................... 250
23.1.1. Operating Mode Control ....................................................................... 251
23.2. Interrupts ...................................................................................................... 254
23.3. System Timing............................................................................................... 255
23.3.1. Frequency Control................................................................................. 256
23.3.2. Frequency Programming....................................................................... 256
23.3.3. Easy Frequency Programming for FHSS.............................................. 258
23.3.4. Automatic State Transition for Frequency Change ............................... 259
23.3.5. Frequency Deviation ............................................................................. 259
23.3.6. Frequency Offset Adjustment................................................................ 260
23.3.7. Automatic Frequency Control (AFC) ..................................................... 260
23.3.8. TX Data Rate Generator ....................................................................... 262
23.4. Modulation Options........................................................................................ 262
23.4.1. Modulation Type.................................................................................... 262
23.4.2. Modulation Data Source........................................................................ 263
23.4.3. PN9 Mode ............................................................................................. 267
23.5. Internal Functional Blocks ............................................................................. 267
23.5.1. RX LNA ................................................................................................. 267
23.5.2. RX I-Q Mixer ......................................................................................... 267
23.5.3. Programmable Gain Amplifier ............................................................... 267
23.5.4. ADC ..................................................................................................... 268
23.5.5. Digital Modem ....................................................................................... 268
23.5.6. Synthesizer ........................................................................................... 269
23.5.7. Power Amplifier ..................................................................................... 270
23.5.8. Crystal Oscillator ................................................................................... 271
23.5.9. Regulators............................................................................................. 271
23.6. Data Handling and Packet Handler ............................................................... 272
23.6.1. RX and TX FIFOs.................................................................................. 272
23.6.2. Packet Configuration............................................................................. 273
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23.6.3. Packet Handler TX Mode ...................................................................... 274
23.6.4. Packet Handler RX Mode...................................................................... 274
23.6.5. Data Whitening, Manchester Encoding, and CRC ................................ 276
23.6.6. Preamble Detector ................................................................................ 277
23.6.7. Preamble Length................................................................................... 277
23.6.8. Invalid Preamble Detector..................................................................... 278
23.6.9. Synchronization Word Configuration..................................................... 278
23.6.10. Receive Header Check ....................................................................... 279
23.6.11. TX Retransmission and Auto TX......................................................... 279
23.7. RX Modem Configuration .............................................................................. 280
23.7.1. Modem Settings for FSK and GFSK ..................................................... 280
23.8. Auxiliary Functions ........................................................................................ 280
23.8.1. Smart Reset .......................................................................................... 280
23.8.2. Output Clock ......................................................................................... 281
23.8.3. General Purpose ADC .......................................................................... 282
23.8.4. Temperature Sensor ............................................................................. 283
23.8.5. Low Battery Detector............................................................................. 285
23.8.6. Wake-Up Timer and 32 kHz Clock Source ........................................... 285
23.8.7. Low Duty Cycle Mode ........................................................................... 287
23.8.8. GPIO Configuration............................................................................... 288
23.8.9. Antenna Diversity .................................................................................. 289
23.8.10. RSSI and Clear Channel Assessment ................................................ 290
23.9. Reference Design.......................................................................................... 290
23.10. Application Notes and Reference Designs .................................................. 293
23.11. Customer Support ....................................................................................... 293
23.12. Register Table and Descriptions ................................................................. 294
23.13. Required Changes to Default Register Values............................................ 296
23. SMBus................................................................................................................... 297
23.1. Supporting Documents .................................................................................. 298
23.2. SMBus Configuration..................................................................................... 298
23.3. SMBus Operation .......................................................................................... 298
23.3.1. Transmitter vs. Receiver ....................................................................... 299
23.3.2. Arbitration.............................................................................................. 299
23.3.3. Clock Low Extension............................................................................. 299
23.3.4. SCL Low Timeout.................................................................................. 299
23.3.5. SCL High (SMBus Free) Timeout ......................................................... 300
23.4. Using the SMBus........................................................................................... 300
23.4.1. SMBus Configuration Register.............................................................. 300
23.4.2. SMB0CN Control Register .................................................................... 304
23.4.3. Hardware Slave Address Recognition .................................................. 306
23.4.4. Data Register ........................................................................................ 309
23.5. SMBus Transfer Modes................................................................................. 309
23.5.1. Write Sequence (Master) ...................................................................... 309
23.5.2. Read Sequence (Master) ...................................................................... 310
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23.5.3. Write Sequence (Slave) ........................................................................ 311
23.5.4. Read Sequence (Slave) ........................................................................ 312
23.6. SMBus Status Decoding................................................................................ 313
24. UART0 ................................................................................................................... 318
24.1. Enhanced Baud Rate Generation.................................................................. 319
24.2. Operational Modes ........................................................................................ 319
24.2.1. 8-Bit UART ............................................................................................ 320
24.2.2. 9-Bit UART ............................................................................................ 320
24.3. Multiprocessor Communications ................................................................... 321
25. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 325
25.1. Signal Descriptions........................................................................................ 326
25.1.1. Master Out, Slave In (MOSI)................................................................. 326
25.1.2. Master In, Slave Out (MISO)................................................................. 326
25.1.3. Serial Clock (SCK) ................................................................................ 326
25.1.4. Slave Select (NSS) ............................................................................... 326
25.2. SPI0 Master Mode Operation ........................................................................ 326
25.3. SPI0 Slave Mode Operation .......................................................................... 328
25.4. SPI0 Interrupt Sources .................................................................................. 329
25.5. Serial Clock Phase and Polarity .................................................................... 329
25.6. SPI Special Function Registers ..................................................................... 331
26. Timers ................................................................................................................... 338
26.1. Timer 0 and Timer 1 ...................................................................................... 340
26.1.1. Mode 0: 13-Bit Counter/Timer............................................................... 340
26.1.2. Mode 1: 16-Bit Counter/Timer............................................................... 341
26.1.3. Mode 2: 8-Bit Counter/Timer with Auto-Reload .................................... 341
26.1.4. Mode 3: Two 8-Bit Counter/Timers (Timer 0 Only) ............................... 342
26.2. Timer 2 .......................................................................................................... 348
26.2.1. 16-Bit Timer with Auto-Reload .............................................................. 348
26.2.2. 8-Bit Timers with Auto-Reload .............................................................. 349
26.2.3. Comparator 0/SmaRTClock Capture Mode .......................................... 350
26.3. Timer 3 .......................................................................................................... 354
26.3.1. 16-Bit Timer with Auto-Reload .............................................................. 354
26.3.2. 8-Bit Timers with Auto-Reload .............................................................. 355
26.3.3. Comparator 1/External Oscillator Capture Mode .................................. 356
27. Programmable Counter Array............................................................................. 360
27.1. PCA Counter/Timer ....................................................................................... 361
27.2. PCA0 Interrupt Sources................................................................................. 362
27.3. Capture/Compare Modules ........................................................................... 363
27.3.1. Edge-triggered Capture Mode............................................................... 364
27.3.2. Software Timer (Compare) Mode.......................................................... 365
27.3.3. High-Speed Output Mode ..................................................................... 366
27.3.4. Frequency Output Mode ....................................................................... 366
27.3.5. 8-Bit, 9-Bit, 10-Bit and 11-Bit Pulse Width Modulator Modes................ 367
27.3.6. 16-Bit Pulse Width Modulator Mode...................................................... 369
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27.4. Watchdog Timer Mode .................................................................................. 370
27.4.1. Watchdog Timer Operation ................................................................... 370
27.4.2. Watchdog Timer Usage ........................................................................ 371
27.5. Register Descriptions for PCA0..................................................................... 373
28. C2 Interface .......................................................................................................... 379
28.1. C2 Interface Registers................................................................................... 379
28.2. C2 Pin Sharing .............................................................................................. 382
Document Change List.............................................................................................. 383
Contact Information................................................................................................... 384
9
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List of Figures
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Figure 1.1. Si1010 Block Diagram ........................................................................... 21
Figure 1.2. Si1011 Block Diagram ........................................................................... 21
Figure 1.3. Si1012 Block Diagram ........................................................................... 22
Figure 1.4. Si1013 Block Diagram ........................................................................... 22
Figure 1.5. Si1014 Block Diagram ........................................................................... 23
Figure 1.6. Si1015 Block Diagram ........................................................................... 23
Figure 1.7. Si1012/3 RX/TX Direct-Tie Application Example .................................. 24
Figure 1.8. Si1010/1 Antenna Diversity Application Example ................................. 24
Figure 1.9. Port I/O Functional Block Diagram ........................................................ 26
Figure 1.10. PCA Block Diagram ............................................................................. 27
Figure 1.11. ADC0 Functional Block Diagram ......................................................... 28
Figure 1.12. ADC0 Multiplexer Block Diagram ........................................................ 29
Figure 1.13. Comparator 0 Functional Block Diagram ............................................ 30
Figure 1.14. Comparator 1 Functional Block Diagram ............................................ 30
Figure 3.1. Si1010/1/2/3-C-GM2 Pinout Diagram (Top View) ................................. 36
Figure 3.2. Si1014/5-C-GM2 Pinout Diagram (Top View) ....................................... 37
Figure 3.3. LGA-42 Package Drawing (Si1010/1/2/3/4/5-C-GM2) .......................... 38
Figure 3.4. LGA-42 PCB Land Pattern (Si1010/1/2/3/4/5-C-GM2) .......................... 40
Figure 3.5. LGA-42 PCB Stencil and Via Placement (Si1010/1/2/3/4/5-C-GM2) .... 42
Figure 4.1. Active Mode Current (External CMOS Clock) ....................................... 48
Figure 4.2. Idle Mode Current (External CMOS Clock) ........................................... 49
Figure 4.3. Typical DC-DC Converter Efficiency
(High Current, VDD/DC+ = 2 V) ............................................................ 50
Figure 4.4. Typical DC-DC Converter Efficiency
(High Current, VDD/DC+ = 3 V) ............................................................ 51
Figure 4.5. Typical DC-DC Converter Efficiency
(Low Current, VDD/DC+ = 2 V) ............................................................. 52
Figure 4.6. Typical One-Cell Suspend Mode Current .............................................. 53
Figure 4.7. Typical VOH Curves, 1.8–3.6 V ............................................................ 55
Figure 4.8. Typical VOH Curves, 0.9–1.8 V ............................................................ 56
Figure 4.9. Typical VOL Curves, 1.8–3.6 V ............................................................. 57
Figure 4.10. Typical VOL Curves, 0.9–1.8 V ........................................................... 58
Figure 5.1. ADC0 Functional Block Diagram ........................................................... 76
Figure 5.2. 10-Bit ADC Track and Conversion Example Timing
(BURSTEN = 0) ..................................................................................... 79
Figure 5.3. Burst Mode Tracking Example with Repeat Count Set to 4 .................. 81
Figure 5.4. ADC0 Equivalent Input Circuits ............................................................. 82
Figure 5.5. ADC Window Compare Example: Right-Justified
Single-Ended Data ................................................................................ 93
Figure 5.6. ADC Window Compare Example: Left-Justified
Single-Ended Data ................................................................................ 93
Figure 5.7. ADC0 Multiplexer Block Diagram .......................................................... 94
Figure 5.8. Temperature Sensor Transfer Function ................................................ 96
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Figure 5.9. Temperature Sensor Error with 1-Point Calibration (VREF = 1.68 V) .... 97
Figure 5.10. Voltage Reference Functional Block Diagram ..................................... 99
Figure 7.1. Comparator 0 Functional Block Diagram ............................................ 104
Figure 7.2. Comparator 1 Functional Block Diagram ............................................ 105
Figure 7.3. Comparator Hysteresis Plot ................................................................ 106
Figure 7.4. CPn Multiplexer Block Diagram ........................................................... 111
Figure 8.1. CIP-51 Block Diagram ......................................................................... 114
Figure 9.1. Si1010/1/2/3/4/5 Memory Map ............................................................ 123
Figure 9.2. Flash Program Memory Map ............................................................... 124
Figure 13.1. Flash Program Memory Map (16 kB and 8 kB devices) .................... 148
Figure 14.1. Si1010/1/2/3/4/5 Power Distribution .................................................. 158
Figure 15.1. CRC0 Block Diagram ........................................................................ 166
Figure 15.2. Bit Reverse Register ......................................................................... 174
Figure 16.1. DC-DC Converter Block Diagram ...................................................... 175
Figure 16.2. DC-DC Converter Configuration Options .......................................... 178
Figure 18.1. Reset Sources ................................................................................... 187
Figure 18.2. Power-Fail Reset Timing Diagram .................................................... 188
Figure 18.3. Power-Fail Reset Timing Diagram .................................................... 189
Figure 19.1. Clocking Sources Block Diagram ...................................................... 195
Figure 19.2. 25 MHz External Crystal Example ..................................................... 197
Figure 20.1. SmaRTClock Block Diagram ............................................................. 204
Figure 20.2. Interpreting Oscillation Robustness (Duty Cycle) Test Results ......... 213
Figure 21.1. Port I/O Functional Block Diagram .................................................... 220
Figure 21.2. Port I/O Cell Block Diagram .............................................................. 221
Figure 21.3. Crossbar Priority Decoder with No Pins Skipped .............................. 225
Figure 21.4. Crossbar Priority Decoder with Crystal Pins Skipped ....................... 226
Figure 22.1. EZRadioPRO Serial Interface Block Diagram ................................... 240
Figure 22.2. SPI Timing ......................................................................................... 242
Figure 22.3. SPI Timing—READ Mode ................................................................. 242
Figure 22.4. SPI Timing—Burst Write Mode ......................................................... 243
Figure 22.5. SPI Timing—Burst Read Mode ......................................................... 243
Figure 22.6. Master Mode Data/Clock Timing ....................................................... 244
Figure 22.7. SPI Master Timing ............................................................................. 249
Figure 23.1. State Machine Diagram ..................................................................... 252
Figure 23.2. TX Timing .......................................................................................... 255
Figure 23.3. RX Timing .......................................................................................... 256
Figure 23.4. Frequency Deviation ......................................................................... 259
Figure 23.5. Sensitivity at 1% PER vs. Carrier Frequency Offset ......................... 261
Figure 23.6. FSK vs. GFSK Spectrums ................................................................. 263
Figure 23.7. Direct Synchronous Mode Example .................................................. 266
Figure 23.8. Direct Asynchronous Mode Example ................................................ 266
Figure 23.9. Microcontroller Connections .............................................................. 267
Figure 23.10. PLL Synthesizer Block Diagram ...................................................... 269
Figure 23.11. FIFO Thresholds ............................................................................. 272
Figure 23.12. Packet Structure .............................................................................. 273
11
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Figure 23.13. Multiple Packets in TX Packet Handler ........................................... 274
Figure 23.14. Required RX Packet Structure with Packet Handler Disabled ........ 274
Figure 23.15. Multiple Packets in RX Packet Handler ........................................... 275
Figure 23.16. Multiple Packets in RX with CRC or Header Error .......................... 275
Figure 23.17. Operation of Data Whitening, Manchester Encoding, and CRC ..... 277
Figure 23.18. Manchester Coding Example .......................................................... 277
Figure 23.19. Header ............................................................................................. 279
Figure 23.20. POR Glitch Parameters ................................................................... 280
Figure 23.21. General Purpose ADC Architecture ................................................ 283
Figure 23.22. Temperature Ranges using ADC8 .................................................. 285
Figure 23.23. WUT Interrupt and WUT Operation ................................................. 287
Figure 23.24. Low Duty Cycle Mode ..................................................................... 288
Figure 23.25. RSSI Value vs. Input Power ............................................................ 290
Figure 23.26. Si1012 Split RF TX/RX Direct-Tie Reference Design—Schematic . 291
Figure 23.27. Si1010 Switch Matching Reference Design—Schematic ................ 292
Figure 23.1. SMBus Block Diagram ...................................................................... 297
Figure 23.2. Typical SMBus Configuration ............................................................ 298
Figure 23.3. SMBus Transaction ........................................................................... 299
Figure 23.4. Typical SMBus SCL Generation ........................................................ 301
Figure 23.5. Typical Master Write Sequence ........................................................ 310
Figure 23.6. Typical Master Read Sequence ........................................................ 311
Figure 23.7. Typical Slave Write Sequence .......................................................... 312
Figure 23.8. Typical Slave Read Sequence .......................................................... 313
Figure 24.1. UART0 Block Diagram ...................................................................... 318
Figure 24.2. UART0 Baud Rate Logic ................................................................... 319
Figure 24.3. UART Interconnect Diagram ............................................................. 320
Figure 24.4. 8-Bit UART Timing Diagram .............................................................. 320
Figure 24.5. 9-Bit UART Timing Diagram .............................................................. 321
Figure 24.6. UART Multi-Processor Mode Interconnect Diagram ......................... 321
Figure 25.1. SPI Block Diagram ............................................................................ 325
Figure 25.2. Multiple-Master Mode Connection Diagram ...................................... 327
Figure 25.3. 3-Wire Single Master and 3-Wire Single Slave Mode
Connection Diagram ......................................................................... 327
Figure 25.4. 4-Wire Single Master Mode and 4-Wire Slave Mode
Connection Diagram ......................................................................... 328
Figure 25.5. Master Mode Data/Clock Timing ....................................................... 330
Figure 25.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 330
Figure 25.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 331
Figure 25.8. SPI Master Timing (CKPHA = 0) ....................................................... 335
Figure 25.9. SPI Master Timing (CKPHA = 1) ....................................................... 335
Figure 25.10. SPI Slave Timing (CKPHA = 0) ....................................................... 336
Figure 25.11. SPI Slave Timing (CKPHA = 1) ....................................................... 336
Figure 26.1. T0 Mode 0 Block Diagram ................................................................. 341
Figure 26.2. T0 Mode 2 Block Diagram ................................................................. 342
Figure 26.3. T0 Mode 3 Block Diagram ................................................................. 343
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Figure 26.4. Timer 2 16-Bit Mode Block Diagram ................................................. 348
Figure 26.5. Timer 2 8-Bit Mode Block Diagram ................................................... 349
Figure 26.6. Timer 2 Capture Mode Block Diagram .............................................. 350
Figure 26.7. Timer 3 16-Bit Mode Block Diagram ................................................. 354
Figure 26.8. Timer 3 8-Bit Mode Block Diagram ................................................... 355
Figure 26.9. Timer 3 Capture Mode Block Diagram .............................................. 356
Figure 27.1. PCA Block Diagram ........................................................................... 360
Figure 27.2. PCA Counter/Timer Block Diagram ................................................... 362
Figure 27.3. PCA Interrupt Block Diagram ............................................................ 363
Figure 27.4. PCA Capture Mode Diagram ............................................................. 365
Figure 27.5. PCA Software Timer Mode Diagram ................................................. 365
Figure 27.6. PCA High-Speed Output Mode Diagram ........................................... 366
Figure 27.7. PCA Frequency Output Mode ........................................................... 367
Figure 27.8. PCA 8-Bit PWM Mode Diagram ........................................................ 368
Figure 27.9. PCA 9, 10 and 11-Bit PWM Mode Diagram ...................................... 369
Figure 27.10. PCA 16-Bit PWM Mode ................................................................... 370
Figure 27.11. PCA Module 5 with Watchdog Timer Enabled ................................ 371
Figure 28.1. Typical C2 Pin Sharing ...................................................................... 382
13
Rev. 1.2
Si1010/1/2/3/4/5
List of Tables
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Table 2.1. Product Selection Guide ......................................................................... 31
Table 3.1. Pin Definitions for the Si1010/1/2/3/4/5 .................................................. 32
Table 3.2. LGA-42 Package Dimensions (Si1010/1/2/3/4/5-C-GM2) ...................... 39
Table 3.3. LGA-42 PCB Land Pattern Dimensions (Si1010/1/2/3/4/5-C-GM2) ....... 41
Table 4.1. Absolute Maximum Ratings .................................................................... 43
Table 4.2. Global Electrical Characteristics ............................................................. 44
Table 4.3. Port I/O DC Electrical Characteristics ..................................................... 54
Table 4.4. Reset Electrical Characteristics .............................................................. 59
Table 4.5. Power Management Electrical Specifications ......................................... 60
Table 4.6. Flash Electrical Characteristics .............................................................. 60
Table 4.7. Internal Precision Oscillator Electrical Characteristics ........................... 60
Table 4.8. Internal Low-Power Oscillator Electrical Characteristics ........................ 60
Table 4.9. SmaRTClock Characteristics .................................................................. 61
Table 4.10. ADC0 Electrical Characteristics ............................................................ 61
Table 4.11. Temperature Sensor Electrical Characteristics .................................... 62
Table 4.12. Voltage Reference Electrical Characteristics ....................................... 63
Table 4.13. IREF0 Electrical Characteristics ........................................................... 64
Table 4.14. Comparator Electrical Characteristics .................................................. 65
Table 4.15. VREG0 Electrical Characteristics ......................................................... 66
Table 4.16. DC-DC Converter (DC0) Electrical Characteristics .............................. 67
Table 4.17. DC Characteristics ................................................................................ 68
Table 4.18. Synthesizer AC Electrical Characteristics ............................................ 69
Table 4.19. Receiver AC Electrical Characteristics ................................................. 70
Table 4.20. Transmitter AC Electrical Characteristics ............................................. 71
Table 4.21. Auxiliary Block Specifications ............................................................... 72
Table 4.22. Digital IO Specifications (nIRQ) ............................................................ 73
Table 4.23. GPIO Specifications (GPIO_0, GPIO_1, and GPIO_2) ........................ 73
Table 4.24. Absolute Maximum Ratings .................................................................. 74
Table 5.1. Representative Conversion Times and Energy Consumption
for the SAR ADC with 1.65 V High-Speed VREF ................................... 84
Table 8.1. CIP-51 Instruction Set Summary .......................................................... 116
Table 11.1. Special Function Register (SFR) Memory Map (Page 0x0) ............... 128
Table 11.2. Special Function Register (SFR) Memory Map (Page 0xF) ............... 129
Table 11.3. Special Function Registers ................................................................. 130
Table 12.1. Interrupt Summary .............................................................................. 136
Table 13.1. Flash Security Summary .................................................................... 149
Table 14.1. Power Modes ...................................................................................... 157
Table 15.1. Example 16-Bit CRC Outputs ............................................................. 167
Table 15.2. Example 32-bit CRC Outputs ............................................................. 169
Table 16.1. IPeak Inductor Current Limit Settings ................................................. 176
Table 19.1. Recommended XFCN Settings for Crystal Mode ............................... 197
Table 19.2. Recommended XFCN Settings for RC and C modes ......................... 198
Table 20.1. SmaRTClock Internal Registers ......................................................... 205
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Table 20.2. SmaRTClock Load Capacitance Settings .......................................... 212
Table 20.3. SmaRTClock Bias Settings ................................................................ 213
Table 21.1. Port I/O Assignment for Analog Functions ......................................... 222
Table 21.2. Port I/O Assignment for Digital Functions ........................................... 223
Table 21.3. Port I/O Assignment for External Digital Event Capture Functions .... 223
Table 22.1. Serial Interface Timing Parameters .................................................... 242
Table 22.2. SPI Timing Parameters ...................................................................... 249
Table 23.1. EZRadioPRO Operating Modes ......................................................... 251
Table 23.2. EZRadioPRO Operating Modes Response Time ............................... 252
Table 23.3. Frequency Band Selection ................................................................. 257
Table 23.4. Packet Handler Registers ................................................................... 276
Table 23.5. Minimum Receiver Settling Time ........................................................ 278
Table 23.6. POR Parameters ................................................................................ 281
Table 23.7. Temperature Sensor Range ............................................................... 284
Table 23.8. Antenna Diversity Control ................................................................... 289
Table 23.9. EZRadioPRO Internal Register Descriptions ...................................... 294
Table 23.1. SMBus Clock Source Selection .......................................................... 301
Table 23.2. Minimum SDA Setup and Hold Times ................................................ 302
Table 23.3. Sources for Hardware Changes to SMB0CN ..................................... 306
Table 23.4. Hardware Address Recognition Examples (EHACK = 1) ................... 307
Table 23.5. SMBus Status Decoding with Hardware ACK Generation Disabled
(EHACK = 0) ....................................................................................... 314
Table 23.6. SMBus Status Decoding With Hardware ACK Generation Enabled
(EHACK = 1) ....................................................................................... 316
Table 24.1. Timer Settings for Standard Baud Rates
Using The Internal 24.5 MHz Oscillator .............................................. 324
Table 24.2. Timer Settings for Standard Baud Rates
Using an External 22.1184 MHz Oscillator ......................................... 324
Table 25.1. SPI Slave Timing Parameters ............................................................ 337
Table 26.1. Timer 0 Running Modes ..................................................................... 340
Table 27.1. PCA Timebase Input Options ............................................................. 361
Table 27.2. PCA0CPM and PCA0PWM Bit Settings for PCA
Capture/Compare Modules ................................................................ 364
Table 27.3. Watchdog Timer Timeout Intervals1 ................................................... 372
15
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Si1010/1/2/3/4/5
List of Registers
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SFR Definition 5.1. ADC0CN: ADC0 Control ................................................................ 85
SFR Definition 5.2. ADC0CF: ADC0 Configuration ...................................................... 86
SFR Definition 5.3. ADC0AC: ADC0 Accumulator Configuration ................................. 87
SFR Definition 5.4. ADC0PWR: ADC0 Burst Mode Power-Up Time ............................ 88
SFR Definition 5.5. ADC0TK: ADC0 Burst Mode Track Time ....................................... 89
SFR Definition 5.6. ADC0H: ADC0 Data Word High Byte ............................................ 90
SFR Definition 5.7. ADC0L: ADC0 Data Word Low Byte .............................................. 90
SFR Definition 5.8. ADC0GTH: ADC0 Greater-Than High Byte ................................... 91
SFR Definition 5.9. ADC0GTL: ADC0 Greater-Than Low Byte .................................... 91
SFR Definition 5.10. ADC0LTH: ADC0 Less-Than High Byte ...................................... 92
SFR Definition 5.11. ADC0LTL: ADC0 Less-Than Low Byte ........................................ 92
SFR Definition 5.12. ADC0MX: ADC0 Input Channel Select ........................................ 95
SFR Definition 5.13. TOFFH: ADC0 Data Word High Byte .......................................... 98
SFR Definition 5.14. TOFFL: ADC0 Data Word Low Byte ............................................ 98
SFR Definition 5.15. REF0CN: Voltage Reference Control ........................................ 101
SFR Definition 6.1. IREF0CN: Current Reference Control ......................................... 102
SFR Definition 6.2. IREF0CF: Current Reference Configuration ................................ 103
SFR Definition 7.1. CPT0CN: Comparator 0 Control .................................................. 107
SFR Definition 7.2. CPT0MD: Comparator 0 Mode Selection .................................... 108
SFR Definition 7.3. CPT1CN: Comparator 1 Control .................................................. 109
SFR Definition 7.4. CPT1MD: Comparator 1 Mode Selection .................................... 110
SFR Definition 7.5. CPT0MX: Comparator0 Input Channel Select ............................. 112
SFR Definition 7.6. CPT1MX: Comparator1 Input Channel Select ............................. 113
SFR Definition 8.1. DPL: Data Pointer Low Byte ........................................................ 120
SFR Definition 8.2. DPH: Data Pointer High Byte ....................................................... 120
SFR Definition 8.3. SP: Stack Pointer ......................................................................... 121
SFR Definition 8.4. ACC: Accumulator ....................................................................... 121
SFR Definition 8.5. B: B Register ................................................................................ 121
SFR Definition 8.6. PSW: Program Status Word ........................................................ 122
SFR Definition 10.1. EMI0CN: External Memory Interface Control ............................ 127
SFR Definition 11.1. SFR Page: SFR Page ................................................................ 130
SFR Definition 12.1. IE: Interrupt Enable .................................................................... 138
SFR Definition 12.2. IP: Interrupt Priority .................................................................... 139
SFR Definition 12.3. EIE1: Extended Interrupt Enable 1 ............................................ 140
SFR Definition 12.4. EIP1: Extended Interrupt Priority 1 ............................................ 141
SFR Definition 12.5. EIE2: Extended Interrupt Enable 2 ............................................ 142
SFR Definition 12.6. EIP2: Extended Interrupt Priority 2 ............................................ 143
SFR Definition 12.7. IT01CF: INT0/INT1 Configuration .............................................. 145
SFR Definition 13.1. PSCTL: Program Store R/W Control ......................................... 154
SFR Definition 13.2. FLKEY: Flash Lock and Key ...................................................... 155
SFR Definition 13.3. FLSCL: Flash Scale ................................................................... 156
SFR Definition 13.4. FLWR: Flash Write Only ............................................................ 156
SFR Definition 14.1. PMU0CF: Power Management Unit Configuration .................... 163
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SFR Definition 14.2. PMU0MD: Power Management Unit Mode ................................ 164
SFR Definition 14.3. PCON: Power Management Control Register ........................... 165
SFR Definition 15.1. CRC0CN: CRC0 Control ........................................................... 170
SFR Definition 15.2. CRC0IN: CRC0 Data Input ........................................................ 171
SFR Definition 15.3. CRC0DAT: CRC0 Data Output .................................................. 171
SFR Definition 15.4. CRC0AUTO: CRC0 Automatic Control ...................................... 172
SFR Definition 15.5. CRC0CNT: CRC0 Automatic Flash Sector Count ..................... 173
SFR Definition 15.6. CRC0FLIP: CRC0 Bit Flip .......................................................... 174
SFR Definition 16.1. DC0CN: DC-DC Converter Control ........................................... 182
SFR Definition 16.2. DC0CF: DC-DC Converter Configuration .................................. 183
SFR Definition 16.3. DC0MD: DC-DC Mode .............................................................. 184
SFR Definition 17.1. REG0CN: Voltage Regulator Control ........................................ 185
SFR Definition 18.1. VDM0CN: VDD_MCU/DC+ Supply Monitor Control .................. 191
SFR Definition 18.2. RSTSRC: Reset Source ............................................................ 194
SFR Definition 19.1. CLKSEL: Clock Select ............................................................... 201
SFR Definition 19.2. OSCICN: Internal Oscillator Control .......................................... 202
SFR Definition 19.3. OSCICL: Internal Oscillator Calibration ..................................... 202
SFR Definition 19.4. OSCXCN: External Oscillator Control ........................................ 203
SFR Definition 20.1. RTC0KEY: SmaRTClock Lock and Key .................................... 208
SFR Definition 20.2. RTC0ADR: SmaRTClock Address ............................................ 209
SFR Definition 20.3. RTC0DAT: SmaRTClock Data .................................................. 210
Internal Register Definition 20.4. RTC0CN: SmaRTClock Control ............................. 216
Internal Register Definition 20.5. RTC0XCN: SmaRTClock
Oscillator Control ............................................................. 217
Internal Register Definition 20.6. RTC0XCF: SmaRTClock
Oscillator Configuration ................................................... 218
Internal Register Definition 20.7. RTC0PIN: SmaRTClock Pin Configuration ............ 218
Internal Register Definition 20.8. CAPTUREn: SmaRTClock Timer Capture ............. 219
Internal Register Definition 20.9. ALARMn: SmaRTClock Alarm
Programmed Value .......................................................... 219
SFR Definition 21.1. XBR0: Port I/O Crossbar Register 0 .......................................... 227
SFR Definition 21.2. XBR1: Port I/O Crossbar Register 1 .......................................... 228
SFR Definition 21.3. XBR2: Port I/O Crossbar Register 2 .......................................... 229
SFR Definition 21.4. P0MASK: Port0 Mask Register .................................................. 230
SFR Definition 21.5. P0MAT: Port0 Match Register ................................................... 230
SFR Definition 21.6. P1MASK: Port1 Mask Register .................................................. 231
SFR Definition 21.7. P1MAT: Port1 Match Register ................................................... 231
SFR Definition 21.8. P0: Port0 .................................................................................... 233
SFR Definition 21.9. P0SKIP: Port0 Skip .................................................................... 233
SFR Definition 21.10. P0MDIN: Port0 Input Mode ...................................................... 234
SFR Definition 21.11. P0MDOUT: Port0 Output Mode ............................................... 234
SFR Definition 21.12. P0DRV: Port0 Drive Strength .................................................. 235
SFR Definition 21.13. P1: Port1 .................................................................................. 236
SFR Definition 21.14. P1SKIP: Port1 Skip .................................................................. 236
SFR Definition 21.15. P1MDIN: Port1 Input Mode ...................................................... 237
17
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SFR Definition 21.16. P1MDOUT: Port1 Output Mode ............................................... 237
SFR Definition 21.17. P1DRV: Port1 Drive Strength .................................................. 238
SFR Definition 21.18. P2: Port2 .................................................................................. 238
SFR Definition 21.19. P2MDOUT: Port2 Output Mode ............................................... 239
SFR Definition 21.20. P2DRV: Port2 Drive Strength .................................................. 239
SFR Definition 22.1. SPI1CFG: SPI Configuration ..................................................... 245
SFR Definition 22.2. SPI1CN: SPI Control ................................................................. 246
SFR Definition 22.3. SPI1CKR: SPI Clock Rate ......................................................... 247
SFR Definition 22.4. SPI1DAT: SPI Data ................................................................... 248
SFR Definition 23.1. SMB0CF: SMBus Clock/Configuration ...................................... 303
SFR Definition 23.2. SMB0CN: SMBus Control .......................................................... 305
SFR Definition 23.3. SMB0ADR: SMBus Slave Address ............................................ 308
SFR Definition 23.4. SMB0ADM: SMBus Slave Address Mask .................................. 308
SFR Definition 23.5. SMB0DAT: SMBus Data ............................................................ 309
SFR Definition 24.1. SCON0: Serial Port 0 Control .................................................... 322
SFR Definition 24.2. SBUF0: Serial (UART0) Port Data Buffer .................................. 323
SFR Definition 25.7. SPI0CFG: SPI0 Configuration ................................................... 332
SFR Definition 25.8. SPI0CN: SPI0 Control ............................................................... 333
SFR Definition 25.9. SPI0CKR: SPI0 Clock Rate ....................................................... 334
SFR Definition 25.10. SPI0DAT: SPI0 Data ............................................................... 334
SFR Definition 26.1. CKCON: Clock Control .............................................................. 339
SFR Definition 26.2. TCON: Timer Control ................................................................. 344
SFR Definition 26.3. TMOD: Timer Mode ................................................................... 345
SFR Definition 26.4. TL0: Timer 0 Low Byte ............................................................... 346
SFR Definition 26.5. TL1: Timer 1 Low Byte ............................................................... 346
SFR Definition 26.6. TH0: Timer 0 High Byte ............................................................. 347
SFR Definition 26.7. TH1: Timer 1 High Byte ............................................................. 347
SFR Definition 26.8. TMR2CN: Timer 2 Control ......................................................... 351
SFR Definition 26.9. TMR2RLL: Timer 2 Reload Register Low Byte .......................... 352
SFR Definition 26.10. TMR2RLH: Timer 2 Reload Register High Byte ...................... 352
SFR Definition 26.11. TMR2L: Timer 2 Low Byte ....................................................... 353
SFR Definition 26.12. TMR2H Timer 2 High Byte ....................................................... 353
SFR Definition 26.13. TMR3CN: Timer 3 Control ....................................................... 357
SFR Definition 26.14. TMR3RLL: Timer 3 Reload Register Low Byte ........................ 358
SFR Definition 26.15. TMR3RLH: Timer 3 Reload Register High Byte ...................... 358
SFR Definition 26.16. TMR3L: Timer 3 Low Byte ....................................................... 359
SFR Definition 26.17. TMR3H Timer 3 High Byte ....................................................... 359
SFR Definition 27.1. PCA0CN: PCA Control .............................................................. 373
SFR Definition 27.2. PCA0MD: PCA Mode ................................................................ 374
SFR Definition 27.3. PCA0PWM: PCA PWM Configuration ....................................... 375
SFR Definition 27.4. PCA0CPMn: PCA Capture/Compare Mode .............................. 376
SFR Definition 27.5. PCA0L: PCA Counter/Timer Low Byte ...................................... 377
SFR Definition 27.6. PCA0H: PCA Counter/Timer High Byte ..................................... 377
SFR Definition 27.7. PCA0CPLn: PCA Capture Module Low Byte ............................. 378
SFR Definition 27.8. PCA0CPHn: PCA Capture Module High Byte ........................... 378
Rev. 1.2
18
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C2 Register Definition 28.1. C2ADD: C2 Address ...................................................... 379
C2 Register Definition 28.2. DEVICEID: C2 Device ID ............................................... 380
C2 Register Definition 28.3. REVID: C2 Revision ID .................................................. 380
C2 Register Definition 28.4. FPCTL: C2 Flash Programming Control ........................ 381
C2 Register Definition 28.5. FPDAT: C2 Flash Programming Data ............................ 381
19
Rev. 1.2
Si1010/1/2/3/4/5
1. System Overview
D
240–960 MHz EZRadioPRO® transceiver
Single/Dual Battery operation with on-chip dc-dc boost converter.
High-speed pipelined 8051-compatible microcontroller core (up to 25 MIPS)
In-system, full-speed, non-intrusive debug interface (on-chip)
10-bit 300 ksps or 12-bit 75 ksps single-ended ADC with analog multiplexer
6-Bit Programmable Current Reference. Resolution can be increased with PWM.
Precision programmable 24.5 MHz internal oscillator with spread spectrum technology.
16 kB or 8 kB of on-chip Flash memory
768 bytes of on-chip RAM
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Si1010/1/2/3/4/5 devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features
are listed below. Refer to Table 2.1 for specific product feature selection and part ordering numbers.
SMBus/I2C, Enhanced UART, and two Enhanced SPI serial interfaces implemented in hardware
Four general-purpose 16-bit timers
Programmable Counter/Timer Array (PCA) with six capture/compare modules and Watchdog Timer
function
On-chip Power-On Reset, VDD Monitor, and Temperature Sensor
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Two On-chip Voltage Comparators with 11 Capacitive Touch Sense inputs.
15 Port I/O (5 V tolerant except for GPIO_0, GPIO_1, and GPIO_2)
With on-chip Power-On Reset, VDD monitor, Watchdog Timer, and clock oscillator, the Si1010/1/2/3/4/5
devices are truly stand-alone System-on-a-Chip solutions. The Flash memory can be reprogrammed even
in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. User
software has complete control of all peripherals, and may individually shut down any or all peripherals for
power savings.
m
en
de
d
om
The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip
resources), full speed, in-circuit debugging using the production MCU installed in the final application. This
debug logic supports inspection and modification of memory and registers, setting breakpoints, single
stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging
using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging without occupying package pins.
ec
Each device is specified for 0.9 to 1.8 V, 0.9 to 3.6 V or 1.8 to 3.6 V operation over the industrial temperature range (–40 to +85 °C). The Port I/O and RST pins are tolerant of input signals up to 5 V. The
Si1010/1/2/3/4/5 devices are available in a 42-pin LGA package which is lead-free and RoHS compliant.
See Table 2.1 for ordering information. Block diagrams are included in Figure 1.1 through Figure 1.4.
N
ot
R
The transceiver's extremely low receive sensitivity (–121 dBm) coupled with industry leading +20 dBm output power ensures extended range and improved link performance. Built-in antenna diversity and support
for frequency hopping can be used to further extend range and enhance performance. The advanced radio
features including continuous frequency coverage from 240–960 MHz in 156 Hz or 312 Hz steps allow precise tuning control. Additional system features such as an automatic wake-up timer, low battery detector,
64 byte TX/RX FIFOs, automatic packet handling, and preamble detection reduce overall current consumption. The transceivers digital receive architecture features a high-performance ADC and DSP-based
modem which performs demodulation, filtering, and packet handling for increased flexibility and performance. The direct digital transmit modulation and automatic PA power ramping ensure precise transmit
modulation and reduced spectral spreading, ensuring compliance with global regulations including FCC,
ETSI, ARIB, and 802.15.4d regulations. An easy-to-use calculator is provided to quickly configure the radio
settings, simplifying customer's system design and reducing time to market.
Rev. 1.2
20
Si1010/1/2/3/4/5
Debug /
Programming
Hardware
16k Byte ISP Flash
Program Memory
6-bit
IREF
256 Byte SRAM
512 Byte XRAM
C2D
VDD
External
VREF
VREF
CP1, CP1A
XTAL3
XTAL4
AGC
LNA
RXp
RXn
Mixer
PGA
ADC
+
-
+
-
Digital
Modem
Digital Peripherals
Transceiver Control Interface
Delta
Sigma
Modulator
Digital
Logic
UART
External
Oscillator
Circuit
Timers 0,
1, 2, 3
SmaRTClock
Oscillator
PCA/
WDT
System Clock
Configuration
XIN
XOUT
OSC
Priority
Crossbar
Decoder
SMBus
fo
r
XTAL2
VDD
VREF
Temp
Sensor
A
M
U
X
Comparators
Low Power
20 MHz
Oscillator
XTAL1
TX
CP0, CP0A
SFR
Bus
Precision
24.5 MHz
Oscillator
PA
Internal
GND
SYSCLK
GND
IREF0
12/10-bit
75/300 ksps
ADC
CRC
Engine
VREG
RF XCVR
(240-960 MHz)
es
ig
ns
C2CK/RST
Analog Peripherals
D
Wake
Reset
CIP-51 8051
Controller Core
N
ew
Power On
Reset/PMU
SPI 0
Port I/O
Config
15
ANALOG &
DIGITAL I/O
m
en
de
d
Figure 1.1. Si1010 Block Diagram
Power On
Reset/PMU
Wake
Reset
C2CK/RST
Debug /
Programming
Hardware
CIP-51 8051
Controller Core
8k Byte ISP Flash
Program Memory
512 Byte XRAM
om
VREG
N
ot
R
ec
GND
XTAL3
XTAL4
XTAL1
XTAL2
PA
Internal
External
VREF
VREF
VDD
VREF
Temp
Sensor
+
-
Digital Peripherals
Transceiver Control Interface
PGA
ADC
Digital
Modem
Delta
Sigma
Modulator
Digital
Logic
UART
External
Oscillator
Circuit
Timers 0,
1, 2, 3
SmaRTClock
Oscillator
PCA/
WDT
SMBus
System Clock
Configuration
SPI 0
Rev. 1.2
XIN
XOUT
OSC
Priority
Crossbar
Decoder
Figure 1.2. Si1011 Block Diagram
21
RXp
RXn
LNA
+
-
Comparators
Low Power
20 MHz
Oscillator
AGC
Mixer
GND
CP1, CP1A
SFR
Bus
TX
A
M
U
X
CP0, CP0A
SYSCLK
Precision
24.5 MHz
Oscillator
IREF0
12/10-bit
75/300 ksps
ADC
CRC
Engine
RF XCVR
(240-960 MHz)
6-bit
IREF
256 Byte SRAM
C2D
VDD
Analog Peripherals
Port I/O
Config
15
ANALOG &
DIGITAL I/O
Si1010/1/2/3/4/5
16k Byte ISP Flash
Program Memory
6-bit
IREF
256 Byte SRAM
Debug /
Programming
Hardware
512 Byte XRAM
C2D
External
VREF
VREF
CP1, CP1A
XTAL4
RXp
RXn
LNA
PGA
ADC
+
-
+
-
Transceiver Control Interface
Digital
Modem
Delta
Sigma
Modulator
Digital
Logic
UART
Timers 0,
1, 2, 3
SmaRTClock
Oscillator
PCA/
WDT
System Clock
Configuration
XIN
XOUT
OSC
Priority
Crossbar
Decoder
SMBus
fo
r
XTAL3
AGC
Mixer
Digital Peripherals
External
Oscillator
Circuit
XTAL2
VDD
VREF
Temp
Sensor
Comparators
Low Power
20 MHz
Oscillator
XTAL1
TX
A
M
U
X
CP0, CP0A
SFR
Bus
Precision
24.5 MHz
Oscillator
PA
Internal
GND
SYSCLK
GND
IREF0
12/10-bit
75/300 ksps
ADC
CRC
Engine
VREG
VDD
RF XCVR
(240-960 MHz)
es
ig
ns
C2CK/RST
Analog Peripherals
D
Wake
Reset
CIP-51 8051
Controller Core
N
ew
Power On
Reset/PMU
SPI 0
Port I/O
Config
15
ANALOG &
DIGITAL I/O
m
en
de
d
Figure 1.3. Si1012 Block Diagram
CIP-51 8051
Controller Core
Power On
Reset/PMU
8k Byte ISP Flash
Program Memory
Wake
Reset
C2CK/RST
om
512 Byte XRAM
VDD
N
ot
R
ec
GND
XTAL3
XTAL4
XTAL1
XTAL2
PA
Internal
External
VREF
VREF
VDD
VREF
Temp
Sensor
+
-
RXp
RXn
LNA
PGA
ADC
+
-
Comparators
Digital Peripherals
Low Power
20 MHz
Oscillator
AGC
Mixer
GND
CP1, CP1A
SFR
Bus
TX
A
M
U
X
CP0, CP0A
SYSCLK
Precision
24.5 MHz
Oscillator
IREF0
12/10-bit
75/300 ksps
ADC
CRC
Engine
VREG
RF XCVR
(240-960 MHz)
6-bit
IREF
256 Byte SRAM
Debug /
Programming
Hardware
C2D
Analog Peripherals
Transceiver Control Interface
Digital
Modem
Delta
Sigma
Modulator
Digital
Logic
UART
External
Oscillator
Circuit
Timers 0,
1, 2, 3
SmaRTClock
Oscillator
PCA/
WDT
SMBus
System Clock
Configuration
XIN
XOUT
OSC
Priority
Crossbar
Decoder
SPI 0
Port I/O
Config
15
ANALOG &
DIGITAL I/O
Figure 1.4. Si1013 Block Diagram
Rev. 1.2
22
Si1010/1/2/3/4/5
16k Byte ISP Flash
Program Memory
6-bit
IREF
256 Byte SRAM
Debug /
Programming
Hardware
512 Byte XRAM
C2D
VREG
Analog
Power
GND/DC-
VBAT
DC/DC
Converter
External
VREF
VREF
CP1, CP1A
SFR
Bus
XTAL3
XTAL4
RXp
RXn
LNA
PGA
ADC
+
-
+
-
Digital Peripherals
Transceiver Control Interface
Digital
Modem
Delta
Sigma
Modulator
Digital
Logic
UART
Timers 0,
1, 2, 3
SmaRTClock
Oscillator
PCA/
WDT
XTAL2
AGC
Mixer
Comparators
External
Oscillator
Circuit
XTAL1
VDD
VREF
Temp
Sensor
A
M
U
X
CP0, CP0A
Low Power
20 MHz
Oscillator
GND
TX
GND
SYSCLK
Precision
24.5 MHz
Oscillator
PA
Internal
12/10-bit
75/300 ksps
ADC
CRC
Engine
Digital
Power
IREF0
N
ew
VDD/DC+
Power Net
RF XCVR
(240-960 MHz)
System Clock
Configuration
XIN
XOUT
OSC
Priority
Crossbar
Decoder
SMBus
fo
r
C2CK/RST
Analog Peripherals
es
ig
ns
Wake
Reset
CIP-51 8051
Controller Core
D
Power On
Reset/PMU
Port I/O
Config
SPI 0
15
ANALOG &
DIGITAL I/O
m
en
de
d
Figure 1.5. Si1014 Block Diagram
CIP-51 8051
Controller Core
Power On
Reset/PMU
8k Byte ISP Flash
Program Memory
Wake
Reset
C2CK/RST
512 Byte XRAM
C2D
om
VDD/DC+
Analog
Power
ec
GND/DC-
VBAT
DC/DC
Converter
N
ot
R
GND
XTAL3
XTAL4
XTAL1
XTAL2
VREG
Digital
Power
PA
Internal
External
VREF
VREF
Low Power
20 MHz
Oscillator
VDD
VREF
Temp
Sensor
+
-
RXp
RXn
LNA
PGA
ADC
+
-
Comparators
Digital Peripherals
Transceiver Control Interface
Digital
Modem
Delta
Sigma
Modulator
Digital
Logic
UART
External
Oscillator
Circuit
Timers 0,
1, 2, 3
SmaRTClock
Oscillator
PCA/
WDT
SMBus
System Clock
Configuration
SPI 0
Rev. 1.2
XIN
XOUT
OSC
Priority
Crossbar
Decoder
Figure 1.6. Si1015 Block Diagram
23
AGC
Mixer
GND
CP1, CP1A
SFR
Bus
TX
A
M
U
X
CP0, CP0A
SYSCLK
Precision
24.5 MHz
Oscillator
IREF0
12/10-bit
75/300 ksps
ADC
CRC
Engine
RF XCVR
(240-960 MHz)
6-bit
IREF
256 Byte SRAM
Debug /
Programming
Hardware
Power Net
Analog Peripherals
Port I/O
Config
15
ANALOG &
DIGITAL I/O
Si1010/1/2/3/4/5
1.1. Typical Connection Diagram
es
ig
ns
The application shown in Figure 1.7 is designed for a system with a TX/RX direct-tie configuration without
the use of a TX/RX switch. Most lower power applications will use this configuration. A complete direct-tie
reference design is available from Silicon Laboratories applications support.
supply voltage
1u
L1
VDD_RF
L2
VDD_M CU
VDD_DIG
Px.x
TX
L3
C1
RFp
C2
Si101x
RXn
GPIO2
GPIO1
L5
GPIO0
ANT_A
L6
fo
r
C4
VR_DIG
L4
C3
N
ew
100n
nIRQ
100p
X1
30MHz
XIN
C8
XOUT
C7
SDN
C6
D
For applications seeking improved performance in the presence of multipath fading, antenna diversity can
be used. Antenna diversity support is integrated into the EZRadioPRO transceiver and can improve the
system link budget by 8–10 dB in the presence of these fading conditions, resulting in substantial range
increases. A complete Antenna Diversity reference design is available from Silicon Laboratories applications support.
0.1 uF
0.1 uF
C9
1u
m
en
de
d
C5
Program mable load capacitors for X1 are integrated.
L1-L6 and C1-C5 values depend on frequency band, antenna
impedance, output power and supply voltage range.
Figure 1.7. Si1012/3 RX/TX Direct-Tie Application Example
4
L1
C3
C2
nIRQ
XIN
XOUT
VDD_RF
VDD_MCU
VDD_DIG
Px.x
TX
C1
RXp
Si101x
RXn
C4
L4
GPIO2
3
L2
X1
30MHz
0.1 uF
VR_DIG
5
ec
2
L3
0.1 uF
C9
C5
1u
N
ot
R
6
C8
1u
GPIO1
1
C7
100 n
GPIO0
TR & ANT-DIV
Switch
C6
100 p
SDN
om
Supply Voltage
Programmable load capacitors for X1 are
integrated.
L1–L4 and C1–C5 values depend on frequency
band, antenna impedance, output power, and
supply voltage range.
Figure 1.8. Si1010/1 Antenna Diversity Application Example
Rev. 1.2
24
Si1010/1/2/3/4/5
1.2. CIP-51™ Microcontroller Core
1.2.1. Fully 8051 Compatible
es
ig
ns
The Si1010/1/2/3/4/5 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is
fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be
used to develop software. The CIP-51 core offers all the peripherals included with a standard 8052.
1.2.2. Improved Throughput
D
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than
four system clock cycles.
Clocks to Execute
1
2
2/3
3
Number of Instructions
26
50
5
14
N
ew
The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that
require each execution time.
3/4
4
4/5
5
8
7
3
1
2
1
1.2.3. Additional Features
fo
r
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS.
m
en
de
d
The Si1010/1/2/3/4/5 SoC family includes several key enhancements to the CIP-51 core and peripherals to
improve performance and ease of use in end applications.
The extended interrupt handler provides multiple interrupt sources into the CIP-51 allowing numerous analog and digital peripherals to interrupt the controller. An interrupt driven system requires less intervention
by the MCU, giving it more effective throughput. The extra interrupt sources are very useful when building
multi-tasking, real-time systems.
om
Eight reset sources are available: power-on reset circuitry (POR), an on-chip VDD monitor (forces reset
when power supply voltage drops below safe levels), a Watchdog Timer, a Missing Clock Detector,
SmaRTClock oscillator fail or alarm, a voltage level detection from Comparator0, a forced software reset,
an external reset pin, and an illegal Flash access protection circuit. Each reset source except for the POR,
Reset Input Pin, or Flash error may be disabled by the user in software. The WDT may be permanently disabled in software after a power-on reset during MCU initialization.
N
ot
R
ec
The internal oscillator factory calibrated to 24.5 MHz and is accurate to ±2% over the full temperature and
supply range. The internal oscillator period can also be adjusted by user firmware. An additional 20 MHz
low power oscillator is also available which facilitates low-power operation. An external oscillator drive circuit is included, allowing an external crystal, ceramic resonator, capacitor, RC, or CMOS clock source to
generate the system clock. If desired, the system clock source may be switched on-the-fly between both
internal and external oscillator circuits. An external oscillator can also be extremely useful in low power
applications, allowing the MCU to run from a slow (power saving) source, while periodically switching to
the fast (up to 25 MHz) internal oscillator as needed.
25
Rev. 1.2
Si1010/1/2/3/4/5
1.3. Port Input/Output
es
ig
ns
Digital and analog resources are available through 12 I/O pins. Port pins are organized as three byte-wide
ports. Port pins P0.0–P1.6 can be defined as digital or analog I/O. Digital I/O pins can be assigned to one
of the internal digital resources or used as general purpose I/O (GPIO). Analog I/O pins are used by the
internal analog resources. P1.0, P1.1, P1.2, and P1.3 are dedicated for communication with the EZRadioPRO peripheral. P2.7 can be used as GPIO and is shared with the C2 Interface Data signal (C2D). See
description in Section 28 on page 379.
D
The designer has complete control over which digital and analog functions are assigned to individual Port
pins, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved
through the use of a Priority Crossbar Decoder. See Section “21.3. Priority Crossbar Decoder” on
page 224 for more information on the Crossbar.
Port Match
P0MASK, P0MAT
P1MASK, P1MAT
fo
r
XBR0, XBR1,
XBR2, PnSKIP
Registers
N
ew
All Px.x Port I/Os are 5 V tolerant when used as digital inputs or open-drain outputs. For Port I/Os configured as push-pull outputs, current is sourced from the VDD/DC+ supply. Port I/Os used for analog functions can operate up to the VDD/DC+ supply voltage. See Section “21.1. Port I/O Modes of Operation” on
page 221 for more information on Port I/O operating modes and the electrical specifications chapter for
detailed electrical specifications.
External Interrupts
EX0 and EX1
Highest
Priority
m
en
de
d
Priority
Decoder
4
Digital
Crossbar
CP0
CP1
Outputs
SYSCLK
T0, T1
ec
(Port Latches)
R
8
4
PCA
N
ot
P0.0
2
SMBus
om
(Internal Digital Signals)
SPI0
SPI1
Lowest
Priority
PnMDOUT,
PnMDIN Registers
2
UART
P0.7
7
7
P1.4
P1
I/O
Cells
2
P1.5
P1.6
8
P0
(P0.0-P0.7)
P1
(P1.0-P1.6)
1
7
1
P2
P0
I/O
Cells
(P2.7)
P2
I/O
Cell
To Analog Peripherals
(ADC0, CP0, and CP1 inputs,
VREF, IREF0, AGND)
P2.7
No analog functionality
available on P2.7
Note: P1.0, P1.1, P1.2, and P1.3 are internally
connected to the EZRadioPRO peripheral.
Figure 1.9. Port I/O Functional Block Diagram
Rev. 1.2
26
Si1010/1/2/3/4/5
1.4. Serial Ports
es
ig
ns
The Si1010/1/2/3/4/5 Family includes an SMBus/I2C interface, a full-duplex UART with enhanced baud
rate configuration, and two Enhanced SPI interfaces. Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention.
1.5. Programmable Counter Array
D
An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit general purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with six programmable capture/compare modules. The PCA clock is derived from one of six sources: the system clock divided
by 12, the system clock divided by 4, Timer 0 overflows, an External Clock Input (ECI), the system clock,
the external oscillator clock source divided by 8, or the SmaRTClock divided by 8.
N
ew
Each capture/compare module can be configured to operate in a variety of modes: edge-triggered capture,
software timer, high-speed output, pulse width modulator (8, 9, 10, 11, or 16-bit), or frequency output. Additionally, Capture/Compare Module 5 offers watchdog timer (WDT) capabilities. Following a system reset,
Module 5 is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O and External
Clock Input may be routed to Port I/O via the Digital Crossbar.
SYSCLK/12
ECI
SYSCLK
PCA
CLOCK
MUX
fo
r
SYSCLK/4
Timer 0 Overflow
16-Bit Counter/Timer
m
en
de
d
External Clock/8
SmaRTClock/8
Capture/Compare
Module 0
Capture/Compare
Module 2
Capture/Compare
Module 3
ec
R
N
ot
Port I/O
Figure 1.10. PCA Block Diagram
27
Rev. 1.2
Capture/Compare
Module 5 / WDT
CEX5
Crossbar
Capture/Compare
Module 4
CEX4
CEX3
CEX2
CEX1
CEX0
ECI
om
Capture/Compare
Module 1
Si1010/1/2/3/4/5
1.6. SAR ADC with 16-Bit Auto-Averaging Accumulator and Autonomous Low
Power Burst Mode
es
ig
ns
Si1010/1/2/3/4/5 devices have a 300 ksps, 10-bit or 75 ksps 12-bit successive-approximation-register
(SAR) ADC with integrated track-and-hold and programmable window detector. ADC0 also has an autonomous low power Burst Mode which can automatically enable ADC0, capture and accumulate samples,
then place ADC0 in a low power shutdown mode without CPU intervention. It also has a 16-bit accumulator
that can automatically average the ADC results, providing an effective 11, 12, or 13 bit ADC result without
any additional CPU intervention.
D
The ADC can sample the voltage at any of the GPIO pins (with the exception of P2.7) and has an on-chip
attenuator that allows it to measure voltages up to twice the voltage reference. Additional ADC inputs
include an on-chip temperature sensor, the VDD/DC+ supply voltage, the VBAT supply voltage, and the
internal digital supply voltage.
AIN+
N
ot
AD0TM
AMP0GN
AD08BE
AD0SC0
AD0SC1
AD0SC2
AD0SC3
AD0SC4
R
ec
AD0CM0
AD0CM1
AD0CM2
N
ew
010
011
100
Timer 2 Overflow
Timer 3 Overflow
CNVSTR Input
16-Bit Accumulator
REF
om
SYSCLK
ADC
ADC0CF
AD0WINT
AD0INT
AD0BUSY
10/12-Bit
SAR
AD0BUSY (W)
Timer 0 Overflow
ADC0L
From
AMUX0
Burst Mode Logic
000
001
ADC0LTH
ADC0H
ADC0PWR
Start
Conversion
m
en
de
d
ADC0TK
fo
r
VDD
BURSTEN
AD0EN
ADC0CN
AD0WINT
ADC0LTL
32
Window
Compare
Logic
ADC0GTH ADC0GTL
Figure 1.11. ADC0 Functional Block Diagram
Rev. 1.2
28
Si1010/1/2/3/4/5
es
ig
ns
AD0MX1
AM0MX0
AD0MX2
AD0MX3
AD0MX4
ADC0MX
P0.0
D
Programmable
Attenuator
N
ew
AIN+
P1.6*
AMUX
Temp
Sensor
Gain = 0. 5 or 1
VDD_MCU/DC+
fo
r
VBAT
Digital Supply
ADC0
m
en
de
d
*P1.0 – P1.3 are not
available as device pins
Figure 1.12. ADC0 Multiplexer Block Diagram
1.7. Programmable Current Reference (IREF0)
Si1010/1/2/3/4/5 devices include an on-chip programmable current reference (source or sink) with two output current settings: low power mode and high current mode. The maximum current output in low power
mode is 63 µA (1 µA steps) and the maximum current output in high current mode is 504 µA (8 µA steps).
om
1.8. Comparators
ec
Si1010/1/2/3/4/5 devices include two on-chip programmable voltage comparators: Comparator 0 (CPT0)
which is shown in Figure 1.13; Comparator 1 (CPT1) which is shown in Figure 1.14. The two comparators
operate identically but may differ in their ability to be used as reset or wake-up sources. See Section
“18. Reset Sources” on page 186 and the Section “14. Power Management” on page 157 for details on
reset sources and low power mode wake-up sources, respectively.
N
ot
R
The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an
asynchronous “raw” output (CP0A, CP1A). The asynchronous CP0A signal is available even when the
system clock is not active. This allows the Comparator to operate and generate an output when the device
is in some low power modes.
The comparator inputs may be connected to Port I/O pins or to other internal signals. Port pins may also be
used to directly sense capacitive touch switches.
29
Rev. 1.2
CP0EN
CP0OUT
CP0RIF
CP0FIF
VDD
es
ig
ns
CPT0CN
Si1010/1/2/3/4/5
CP0HYP1
CP0HYP0
CP0HYN1
CP0
Interrupt
CP0HYN0
CPT0MD
Analog Input Multiplexer
CP0
Rising-edge
CP0
Falling-edge
D
CP0FIE
CP0RIE
CP0MD1
CP0MD0
Px.x
CP0 +
Interrupt
Logic
CP0
N
ew
Px.x
+
SET
D
-
CLR
Px.x
D
Q
Q
SET
CLR
Q
Q
Crossbar
(SYNCHRONIZER)
GND
CP0 -
CP0A
(ASYNCHRONOUS)
fo
r
Reset
Decision
Tree
Px.x
m
en
de
d
Figure 1.13. Comparator 0 Functional Block Diagram
CPT0CN
CP1EN
CP1OUT
CP1RIF
VDD
CP1FIF
CP1HYP1
CP1HYN0
CPT0MD
CP1FIE
CP1RIE
Px.x
CP1MD1
CP1MD0
om
Analog Input Multiplexer
ec
CP1
Interrupt
CP1HYP0
CP1HYN1
CP1
Rising-edge
CP1 +
Interrupt
Logic
Px.x
CP1
+
R
N
ot
CP1
Falling-edge
D
-
SET
CLR
Q
Q
D
SET
CLR
Q
Q
Px.x
Crossbar
(SYNCHRONIZER)
CP1 -
GND
(ASYNCHRONOUS)
CP1A
Reset
Decision
Tree
Px.x
Figure 1.14. Comparator 1 Functional Block Diagram
Rev. 1.2
30
Si1010/1/2/3/4/5
2. Ordering Information
es
ig
ns
‘F9xx Plus Features*
Package
Lead-free (RoHS Compliant)
D
Minimum Operating Voltage (Volts)
P 15 P
P
P +20 dBm 1.8 P
P
LGA-42
Si1011-C-GM2 25
768
P
1
1
1
4
P 15 P
P
P +20 dBm 1.8 P
P
LGA-42
Si1012-C-GM2 25 16 768
P
1
1
1
4
P 15 P
P
P +13 dBm 1.8 P
P
LGA-42
Si1013-C-GM2 25
768
P
1
1
1
4
P 15 P
P
P +13 dBm 1.8 P
P
LGA-42
Si1014-C-GM2 25 16 768
P
1
1
1
4
P 15 P
P
P +13 dBm 0.9 P
P
LGA-42
Si1015-C-GM2 25
P
1
1
1
4
P 15 P
P
P +13 dBm 0.9 P
P
LGA-42
8
768
Maximum Transmit Power
fo
r
om
8
10-bit 300ksps ADC
MIPS (Peak)
m
en
de
d
8
N
ew
Temperature Sensor
4
Timers (16-bit)
1
UART
1
SMBus/I2C
1
RAM (bytes)
P
Flash Memory (kB)
Si1010-C-GM2 25 16 768
Ordering Part Number*
Internal Voltage Reference
Digital Port I/Os (Includes EZRadioPRO GPIOs)
Programmable Counter Array
Enhanced SPI (available for external communication)
SmaRTClock Real Time Clock
Table 2.1. Product Selection Guide
N
ot
R
ec
*The ‘F9xx Plus features are a set of enhancements that allow greater power efficiency and increased
functionality. They include 12-bit ADC mode, PWM Enhanced IREF, ultra-low power SmaRTClock LFO,
VBAT input voltage from 0.9 to 3.6 V, and VBAT battery low indicator. The ‘F9xx Plus features are
described in detail in “AN431: F93x-F90x Software Porting Guide.”
Rev. 1.2
31
Si1010/1/2/3/4/5
3. Pinout and Package Definitions
Name
Pin Number
Type
Description
Si1010/1
Si1014/5
Si1012/3
es
ig
ns
Table 3.1. Pin Definitions for the Si1010/1/2/3/4/5
VDD_MCU
38
—
P In
GND
37
—
G
VBAT
—
41
P In
Battery Supply Voltage. Must be 0.9 to 1.8 V in single-cell
battery mode and 1.8 to 3.6 V in dual-cell battery mode.
GND
—
38
P In
In dual-cell battery mode, this pin must be connected
directly to ground.
In one-cell applications, this pin should be connected
directly to the negative battery terminal, which is not
connected to the ground plane.
DCEN
—
40
P In
VDD_MCU /
DC+
—
39
P In
P Out
—
om
GND
D
DC-DC Enable Pin. In single-cell battery mode, this pin
must be connected to VBAT through a 0.68 µH inductor.
In dual-cell battery mode, this pin must be connected
directly to ground.
m
en
de
d
G
N
ew
G
Required Ground for the entire MCU except for the
EZRadioPRO peripheral.
fo
r
VBAT-
Power Supply Voltage for the entire MCU except for the
EZRadioPRO peripheral. Must be 1.8 to 3.6 V.
37
DC–
G
G
Power Supply Voltage for the entire MCU except for the
EZRadioPRO peripheral. Must be 1.8 to 3.6 V. This supply
voltage is not required in low power sleep mode. This
voltage must always be > VBAT.
Positive output of the dc-dc converter. In single-cell battery
mode, a 1 µF ceramic capacitor is required between dc+
and dc–. This pin can supply power to external devices
when operating in single-cell battery mode.
In dual-cell battery mode, this pin must be connected
directly to ground.
DC-DC converter return current path. In one-cell mode, this
pin must be connected to the ground plane.
16
16
P In
Power Supply Voltage for the analog portion of the
EZRadioPRO peripheral. Must be 1.8 to 3.6 V.
VDD_DIG
28
28
P In
Power Supply Voltage for the digital portion of the
EZRadioPRO peripheral. Must be 1.8 to 3.6 V.
27
27
P Out
23
23
G
R
ec
VDD_RF
N
ot
VR_DIG
GND
Regulated Output Voltage of the digital 1.7 V regulator for
the EZRadioPRO peripheral. A 1 µF decoupling capacitor is
required.
Required Ground for the digital and analog portions of the
EZRadioPRO peripheral.
Rev. 1.2
32
Si1010/1/2/3/4/5
Table 3.1. Pin Definitions for the Si1010/1/2/3/4/5 (Continued)
Name
Pin Number
Type
Description
42
C2CK
P2.7/
40
1
C2D
Device Reset. Open-drain output of internal POR or VDD
monitor. An external source can initiate a system reset by
driving this pin low for at least 15 µs. A 1–5 k pullup to
VDD_MCU is recommended. See Reset Sources section
for a complete description.
D I/O
Clock signal for the C2 Debug Interface.
D I/O
Port 2.7. This pin can only be used as GPIO. The Crossbar
cannot route signals to this pin and it cannot be configured
as an analog input. See Port I/O section for a complete
description.
D I/O
Bi-directional data signal for the C2 Debug Interface.
1
3
A In
SmaRTClock Oscillator Crystal Input.
See Section 20 for a complete description.
XTAL4
42
2
A Out
SmaRTClock Oscillator Crystal Output.
See Section 20 for a complete description.
P0.0
36
36
A In
A Out
35
P0.2
35
34
34
ec
R
P0.3
N
ot
XTAL2
33
33
Optional Analog Ground. See VREF chapter.
D I/O or Port 0.2. See Port I/O Section for a complete description.
A In
A In
XTAL1
External VREF Input.
Internal VREF Output. External VREF decoupling capacitors
are recommended. See Voltage Reference section.
D I/O or Port 0.1. See Port I/O Section for a complete description.
A In
G
om
AGND
D I/O or Port 0.0. See Port I/O section for a complete description.
A In
m
en
de
d
P0.1
fo
r
XTAL3
VREF
33
D I/O
D
39
N
ew
RST/
es
ig
ns
Si1010/1
Si1014/5
Si1012/3
External Clock Input. This pin is the external oscillator
return for a crystal or resonator. See Oscillator section.
D I/O or Port 0.3. See Port I/O Section for a complete description.
A In
A Out
D In
A In
External Clock Output. This pin is the excitation driver for an
external crystal or resonator.
External Clock Input. This pin is the external clock input in
external CMOS clock mode.
External Clock Input. This pin is the external clock input in
capacitor or RC oscillator configurations.
See Oscillator section for complete details.
Rev. 1.2
Si1010/1/2/3/4/5
Table 3.1. Pin Definitions for the Si1010/1/2/3/4/5 (Continued)
Pin Number
Type
Description
Si1010/1
Si1014/5
Si1012/3
32
D I/O or Port 0.4. See Port I/O section for a complete description.
A In
D Out
TX
P0.5
31
31
D I/O or Port 0.5. See Port I/O section for a complete description.
A In
D In
RX
P0.6
30
30
UART RX Pin. See Port I/O section.
D I/O or Port 0.6. See Port I/O section for a complete description.
A In
D In
CNVSTR
UART TX Pin. See Port I/O section.
D
32
N
ew
P0.4
es
ig
ns
Name
External Convert Start Input for ADC0. See ADC0 section
for a complete description.
29
D I/O or Port 0.7. See Port I/O section for a complete description.
A In
A Out IREF0 Output. See IREF section for complete description.
P1.4
6
6
D I/O or Port 1.4. See Port I/O section for a complete description.
A In
P1.5
5
5
D I/O or Port 1.5. See Port I/O section for a complete description.
A In
P1.6
4
4
D I/O or Port 1.6. See Port I/O section for a complete description.
A In
GPIO_0
24
24
GPIO_1
25
25
D I/O or General Purpose I/O controlled by the EZRadioPRO periphA I/O eral. May be configured through the EZRadioPRO registers
to perform various functions including: Clock Output, FIFO
D I/O or
status, POR, Wake-Up Timer, Low Battery Detect, TRSW,
A I/O
AntDiversity control, etc. See the EZRadioPRO GPIO ConD I/O or figuration Registers for more information.
A I/O
26
26
nIRQ
11
11
DO
EZRadioPRO peripheral interrupt status pin. Will be set low
to indicate a pending EZRadioPRO interrupt event. See the
EZRadioPRO Control Logic Registers for more details. This
pin is an open-drain output with a 220 k internal pullup
resistor. An external pull-up resistor is recommended.
12
12
AO
EZRadioPRO peripheral crystal oscillator output. Connect
to an external 30 MHz crystal or to an external clock source.
If using an external clock source with no crystal, dc coupling
with a nominal 0.8 VDC level is recommended with a minimum ac amplitude of 700 mVpp. Refer to AN417 for more
details about using an external clock source.
ec
GPIO_2
R
om
m
en
de
d
IREF0
fo
r
29
P0.7
N
ot
XOUT
Rev. 1.2
34
Si1010/1/2/3/4/5
Table 3.1. Pin Definitions for the Si1010/1/2/3/4/5 (Continued)
Name
Pin Number
Type
Description
AI
EZRadioPRO peripheral crystal oscillator input. Connect to
an external 30 MHz crystal or leave floating if driving the
XOUT pin with an external signal source.
es
ig
ns
Si1010/1
Si1014/5
Si1012/3
XIN
13
13
NC
14, 20,
22
14, 20,
22
SDN
15
15
DI
EZRadioPRO peripheral shutdown pin. When driven to
logic HIGH, the EZRadioPRO peripheral will be completely
shut down and the contents of the EZRadioPRO registers
will be lost. This pin should be driven to logic LOW during all
other times; this pin should never be left floating.
TX
17
17
AO
EZRadioPRO peripheral transmit RF output pin. The PA
output is an open-drain connection so the L-C match must
supply (1.8 to 3.6 VDC) to this pin.
RXp
18
18
AI
RXn
19
19
AI
EZRadioPRO peripheral differential RF input pins of the
LNA. See application schematic for example matching network.
ANT_A
21
21
DO
fo
r
N
ew
D
No Connect. May be left floating or tied to power or ground.
N
ot
R
ec
om
m
en
de
d
EZRadioPRO antenna diversity GPIO Ant1 signal direct
digital output. Refer to the description of GPIO Ant1 in the
Function and Control 2 register. A complete description may
be found in “AN440: EZRadioPRO Detailed Transceiver
Register Descriptions.”
35
Rev. 1.2
1
35
N.C.
2
34
N.C.
3
P1.6
4
P1.5
5
P1.4
6
N.C.
7
N.C.
8
N.C.
9
N.C.
10
nIRQ
11
XOUT
12
XIN
N.C.
P0.1/AGND
N
ew
D
XTAL3
es
ig
ns
36
37
38
39
40
41
42
Si1010/1/2/3/4/5
P0.2/XTAL1
33
P0.3/XTAL2
32
P0.4/TX
31
P0.5/RX
30
P0.6/CNVSTR
29
P0.7/IREF0
28
VDD_DIG
27
VR_DIG
26
GPIO_2
25
GPIO_1
24
GPIO_0
13
23
GND
14
22
N.C.
m
en
de
d
fo
r
GND
N
ot
21
20
19
18
17
16
15
R
ec
om
(Top View)
Figure 3.1. Si1010/1/2/3-C-GM2 Pinout Diagram (Top View)
Rev. 1.2
36
35
XTAL4
2
34
XTAL3
3
P1.6
4
P1.5
5
P1.4
6
N.C.
7
N.C.
8
31
P0.5/RX
30
P0.6/CNVSTR
29
P0.7/IREF0
28
VDD_DIG
9
27
VR_DIG
10
26
GPIO_2
11
25
GPIO_1
12
24
GPIO_0
13
23
GND
22
N.C.
om
fo
r
GND
(Top View)
21
20
19
14
N
ot
R
ec
N.C.
18
XIN
P0.4/TX
17
XOUT
32
16
nIRQ
P0.2/XTAL1
P0.3/XTAL2
15
N.C.
P0.1/AGND
33
m
en
de
d
N.C.
es
ig
ns
1
N
ew
P2.7/C2D
D
36
37
38
39
40
41
42
Si1010/1/2/3/4/5
37
Figure 3.2. Si1014/5-C-GM2 Pinout Diagram (Top View)
Rev. 1.2
m
en
de
d
fo
r
N
ew
D
es
ig
ns
Si1010/1/2/3/4/5
N
ot
R
ec
om
Figure 3.3. LGA-42 Package Drawing (Si1010/1/2/3/4/5-C-GM2)
Rev. 1.2
38
Si1010/1/2/3/4/5
Table 3.2. LGA-42 Package Dimensions (Si1010/1/2/3/4/5-C-GM2)
Min
Nom
Max
A
0.85
0.90
0.95
b
0.20
0.25
0.30
D1
3.15
D2
3.00
D3
4.40
e
0.50 BSC.
E
7.00 BSC.
E1
5.40
E2
6.40
E3
6.50
L1
0.05
aaa
—
bbb
—
0.40
fo
r
0.35
m
en
de
d
L
ccc
D
5.00 BSC.
N
ew
D
es
ig
ns
Dimension
—
0.45
0.10
0.15
—
0.10
—
0.10
—
0.08
N
ot
R
ec
om
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C
specification for Small Body Components.
39
Rev. 1.2
Si1010/1/2/3/4/5
D1
es
ig
ns
D
E2
E1
N
ew
E3
Y
(1.675)
1
E
fo
r
X
m
en
de
d
D2
D3
N
ot
R
ec
om
Figure 3.4. LGA-42 PCB Land Pattern (Si1010/1/2/3/4/5-C-GM2)
Rev. 1.2
40
Si1010/1/2/3/4/5
mm
D1
3.20
D2
3.00
D3
4.40
E
0.50
E1
5.45
E2
6.40
N
ew
D
Dimension
es
ig
ns
Table 3.3. LGA-42 PCB Land Pattern Dimensions (Si1010/1/2/3/4/5-C-GM2)
E3
6.50
X
0.25
Y
0.50
N
ot
R
ec
om
m
en
de
d
fo
r
Notes:
General
1. All dimensions shown are in millimeters (mm).
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition
(LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
to assure good solder paste release.
6. The stencil thickness should be 0.125 mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
8. A 4 x 2 array of 1.1 mm square openings on 1.4 mm pitch should be used for the center
ground pad.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for
Small Body Components.
41
Rev. 1.2
N
ew
D
es
ig
ns
Si1010/1/2/3/4/5
2.420
Ø0.250
0.075
1.350
1.200
R
ec
om
m
en
de
d
fo
r
1.210
Center pad paste detail:
R 0.25
N
ot
1.11
1.11
Figure 3.5. LGA-42 PCB Stencil and Via Placement (Si1010/1/2/3/4/5-C-GM2)
Rev. 1.2
42
Si1010/1/2/3/4/5
4. Electrical Characteristics
es
ig
ns
In Section 4.1 and Section 4.2, “VDD” refers to the VDD_MCU supply voltage on Si1010/1/2/3 devices and
to the VDD_MCU/DC+ supply voltage on Si1014/5 devices. The ADC, Comparator, and Port I/O specifications in these two sections do not apply to the EZRadioPRO peripheral.
In Section 4.3 and Section 4.4, “VDD” refers to the VDD_RF and VDD_DIG Supply Voltage. All specifications in these sections pertain to the EZRadioPRO peripheral.
4.1. Absolute Maximum Specifications
Test Condition
Min
Typ
Max
Unit
–55
—
125
°C
–65
—
150
°C
–0.3
–0.3
—
—
5.8
VDD + 3.6
V
–0.3
–0.3
—
—
4.0
4.0
V
–0.3
—
4.0
V
Maximum Total Current through
VBAT, DCEN, VDD_MCU/DC+ or
GND
—
—
500
mA
Maximum Output Current Sunk
by RST or any Px.x Pin
—
—
100
mA
Maximum Total Current through
all Px.x Pins
—
—
200
mA
—
—
110
mW
All pins except TX, RXp,
and RXn
—
—
2
kV
TX, RXp, and RXn
—
—
1
kV
All pins except TX, RXp,
and RXn
—
—
150
V
TX, RXp, and RXn
—
—
45
V
Ambient temperature under bias
Storage Temperature
Voltage on VBAT with respect to
GND
One-Cell Mode
Two-Cell Mode
om
m
en
de
d
Voltage on VDD_MCU or
VDD_MCU/DC+ with respect to
GND
VDD > 2.2 V
VDD < 2.2 V
fo
r
Voltage on any Px.x I/O Pin or
RST with Respect to GND
DC-DC Converter Output Power
ec
ESD (Human Body Model)
N
ot
R
ESD (Machine Model)
N
ew
Parameter
D
Table 4.1. Absolute Maximum Ratings
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the devices at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Rev. 1.2
43
Si1010/1/2/3/4/5
4.2. Electrical Characteristics
Table 4.2. Global Electrical Characteristics
Min
Typ
Max
Unit
Battery Supply Voltage
(VBAT)
One-Cell Mode
Two-Cell Mode
0.9
1.8
1.2
2.4
3.6
3.6
V
Supply Voltage
(VDD_MCU/DC+)
One-Cell Mode
Two-Cell Mode
1.8
1.8
1.9
2.4
3.6
3.6
V
VDD (not in Sleep Mode)
VBAT (in Sleep Mode)
—
—
1.4
0.3
—
0.5
V
0
—
25
MHz
18
—
—
ns
18
—
—
ns
–40
—
+85
°C
Minimum RAM Data
Retention Voltage1
SYSCLK (System Clock)2
TSYSH (SYSCLK High Time)
TSYSL (SYSCLK Low Time)
N
ot
R
ec
om
m
en
de
d
fo
r
Specified Operating
Temperature Range
44
D
Test Condition
N
ew
Parameter
es
ig
ns
–40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the
‘F9xx" for details on how to achieve the supply current specifications listed in this table. All supply current specs are for
the EZRadioPRO peripheral placed in shutdown mode.
Rev. 1.2
Si1010/1/2/3/4/5
Table 4.2. Global Electrical Characteristics (Continued)
Parameter
Test Condition
Min
es
ig
ns
–40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the
‘F9xx" for details on how to achieve the supply current specifications listed in this table. All supply current specs are for
the EZRadioPRO peripheral placed in shutdown mode.
Typ
Max
Unit
IDD Frequency Sensitivity3,
—
4.0
5.0
mA
VDD = 1.8–3.6 V, F = 20 MHz
(includes low power oscillator current)
—
3.4
—
mA
VDD = 1.8 V, F = 1 MHz
VDD = 3.6 V, F = 1 MHz
(includes external oscillator/GPIO current)
—
—
—
—
µA
µA
VDD = 1.8–3.6 V, F = 32.768 kHz
(includes SmaRTClock oscillator current)
—
84
—
µA
VDD = 1.8–3.6 V, T = 25 °C, F < 14 MHz
(Flash oneshot active, see Section 13.6)
—
191
—
µA/MHz
VDD = 1.8–3.6 V, T = 25 °C, F > 14 MHz
(Flash oneshot bypassed, see Section
13.6)
—
102
—
µA/MHz
265
305
fo
r
5, 6
VDD = 1.8–3.6 V, F = 24.5 MHz
(includes precision oscillator current)
N
ew
IDD 3, 4, 5, 6
D
Digital Supply Current—CPU Active (Normal Mode, fetching instructions from Flash)
Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from Flash)
VDD = 1.8–3.6 V, F = 24.5 MHz
(includes precision oscillator current)
—
2.1
3.0
mA
VDD = 1.8–3.6 V, F = 20 MHz
(includes low power oscillator current)
—
1.6
—
mA
VDD = 1.8 V, F = 1 MHz
VDD = 3.6 V, F = 1 MHz
(includes external oscillator/GPIO current)
—
—
160
185
—
—
µA
µA
VDD = 1.8–3.6 V, F = 32.768 kHz
(includes SmaRTClock oscillator current)
—
82
—
µA
VDD = 1.8–3.6 V, T = 25 °C
—
79
—
µA/MHz
m
en
de
d
IDD4, 6, 7
N
ot
R
ec
om
IDD Frequency Sensitivity1,6,7
Rev. 1.2
45
Si1010/1/2/3/4/5
Table 4.2. Global Electrical Characteristics (Continued)
Test Condition
Min
Typ
Max
Unit
—
77
—
µA
Digital Supply Current
1.8 V, T = 25 °C
(Sleep Mode, SmaRTClock 3.0 V, T = 25 °C
running, 32.768 kHz crystal) 3.6 V, T = 25 °C
1.8 V, T = 85 °C
3.0 V, T = 85 °C
3.6 V, T = 85 °C
(includes SmaRTClock oscillator and
VBAT Supply Monitor)
—
—
—
—
—
—
0.61
0.76
0.87
1.32
1.62
1.93
—
—
—
—
—
—
µA
Digital Supply Current
(Sleep Mode, SmaRTClock
running, internal LFO)
1.8 V, T = 25 °C
(includes SmaRTClock oscillator and
VBAT Supply Monitor)
—
0.31
—
µA
Digital Supply Current
(Sleep Mode)
1.8 V, T = 25 °C
3.0 V, T = 25 °C
3.6 V, T = 25 °C
1.8 V, T = 85 °C
3.0 V, T = 85 °C
3.6 V, T = 85 °C
(includes VBAT supply monitor)
—
—
—
—
—
—
0.06
0.09
0.14
0.77
0.92
1.23
—
—
—
—
—
—
µA
1.8 V, T = 25 °C
—
0.02
—
µA
Digital Supply Current—Suspend and Sleep Mode
fo
r
N
ew
VDD = 1.8–3.6 V, two-cell mode
m
en
de
d
Digital Supply Current6
(Suspend Mode)
N
ot
R
ec
om
Digital Supply Current
(Sleep Mode, VBAT Supply
Monitor Disabled)
46
D
Parameter
es
ig
ns
–40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the
‘F9xx" for details on how to achieve the supply current specifications listed in this table. All supply current specs are for
the EZRadioPRO peripheral placed in shutdown mode.
Rev. 1.2
Si1010/1/2/3/4/5
Table 4.2. Global Electrical Characteristics (Continued)
Parameter
Test Condition
Min
es
ig
ns
–40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the
‘F9xx" for details on how to achieve the supply current specifications listed in this table. All supply current specs are for
the EZRadioPRO peripheral placed in shutdown mode.
Typ
Max
Unit
m
en
de
d
fo
r
N
ew
D
Notes:
1. Based on device characterization data; Not production tested.
2. SYSCLK must be at least 32 kHz to enable debugging.
3. Digital Supply Current depends upon the particular code being executed. The values in this table are obtained
with the CPU executing an “sjmp $” loop, which is the compiled form of a while(1) loop in C. One iteration
requires 3 CPU clock cycles, and the Flash memory is read on each cycle. The supply current will vary slightly
based on the physical location of the sjmp instruction and the number of Flash address lines that toggle as a
result. In the worst case, current can increase by up to 30% if the sjmp loop straddles a 64-byte Flash address
boundary (e.g., 0x007F to 0x0080). Real-world code with larger loops and longer linear sequences will have
few transitions across the 64-byte address boundaries.
4. Includes oscillator and regulator supply current.
5. IDD can be estimated for frequencies 14 MHz, the estimate should be the current at 25 MHz minus the difference in current
indicated by the frequency sensitivity number. For example: VDD = 3.0 V; F = 20 MHz, IDD = 4 mA –
(25 MHz – 20 MHz) x 0.102 mA/MHz = 3.5 mA assuming the same oscillator setting.
6. The supply current specifications in Table 4.2 are for two cell mode. The VBAT current in one-cell mode can
be estimated using the following equation:
Supply Voltage Supply Current (two-cell mode)
VBAT Current (one-cell mode) = ----------------------------------------------------------------------------------------------------------------------------------DC-DC Converter Efficiency VBAT Voltage
N
ot
R
ec
om
The VBAT Voltage is the voltage at the VBAT pin, typically 0.9 to 1.8 V.
The Supply Current (two-cell mode) is the data sheet specification for supply current.
The Supply Voltage is the voltage at the VDD/DC+ pin, typically 1.8 to 3.3 V (default = 1.9 V).
The DC-DC Converter Efficiency can be estimated using Figure 4.3–Figure 4.5.
7. Idle IDD can be estimated by taking the current at 25 MHz minus the difference in current indicated by the
frequency sensitivity number. For example: VDD = 3.0 V; F = 5 MHz, Idle IDD = 2.1 mA – (25 MHz –
5 MHz) x 0.079 mA/MHz = 0.52 mA.
Rev. 1.2
47
Si1010/1/2/3/4/5
4200
4000
F > 14 MHz
Oneshot Bypassed
es
ig
ns
F < 14 MHz
Oneshot Enabled
4100
3900
3800
3700
3600
3500
< 160 uA/MHz
3400
D
3300
3200
3100
185 uA/MHz
N
ew
3000
2900
2800
2700
2600
200 uA/MHz
2400
fo
r
2300
2200
2100
2000
1900
m
en
de
d
Supply Current (uA)
2500
1800
1700
1600
1500
1400
1300
215 uA/MHz
1200
1100
1000
900
om
800
700
600
500
ec
400
300
300 uA/MHz
200
R
100
0
N
ot
0
48
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Frequency (MHz)
Figure 4.1. Active Mode Current (External CMOS Clock)
Rev. 1.2
22
23
24
25
Si1010/1/2/3/4/5
4200
es
ig
ns
4100
4000
3900
3800
3700
3600
3500
3400
D
3300
3200
3100
N
ew
3000
2900
2800
2700
2600
fo
r
2400
2300
2200
2100
2000
m
en
de
d
Supply Current (uA)
2500
1900
1800
1700
1600
1500
1400
1300
1200
1100
900
800
700
ec
600
om
1000
500
400
R
300
200
N
ot
100
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Frequency (MHz)
Figure 4.2. Idle Mode Current (External CMOS Clock)
Rev. 1.2
49
6:6(/
es
ig
ns
Si1010/1/2/3/4/5
6:6(/
D
N
ew
fo
r
9%$7 9
m
en
de
d
Efficiency (%)
9%$7 9
9%$7 9
9%$7 9
9%$7 9
9%$7 9
9%$7 9
X+,QGXFWRUSDFNDJH(65 2KPV
9'''& 90LQLPXP3XOVH:LGWK QV 3XOVH6NLSSLQJ'LVDEOHG
om
1RWH (IILFLHQF\DWKLJKFXUUHQWVPD\EHLPSURYHGE\FKRRVLQJDQ
LQGXFWRUZLWKDORZHU(65
ec
R
N
ot
Load Current (mA)
Figure 4.3. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 2 V)
50
Rev. 1.2
Si1010/1/2/3/4/5
6:6(/
6:6(/
es
ig
ns
D
N
ew
9%$7 9
fo
r
9%$7 9
9%$7 9
9%$7 9
9%$7 9
ec
om
9%$7 9
X+,QGXFWRUSDFNDJH(65 2KPV
9'''& 90LQLPXP3XOVH:LGWK QV
3XOVH6NLSSLQJ'LVDEOHG
1RWH (IILFLHQF\DWKLJKFXUUHQWVPD\EHLPSURYHGE\
FKRRVLQJDQLQGXFWRUZLWKDORZHU(65
9%$7 9
m
en
de
d
Efficiency (%)
R
N
ot
Figure 4.4. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 3 V)
Rev. 1.2
51
Si1010/1/2/3/4/5
es
ig
ns
D
N
ew
9%$7 9
9%$7 9
9%$7 9
fo
r
9%$7 9
9%$7 9
9%$7 9
9%$7 9
m
en
de
d
Efficiency (%)
X+,QGXFWRUSDFNDJH(65 2KPV
6:6(/ 9'''& 90LQLPXP3XOVH:LGWK QV
om
ec
N
ot
R
52
Load current (mA)
Figure 4.5. Typical DC-DC Converter Efficiency (Low Current, VDD/DC+ = 2 V)
Rev. 1.2
X+,QGXFWRUSDFNDJH(65 2KPV
6:6(/ 9'''& 9/RDG&XUUHQW X$
D
es
ig
ns
Si1010/1/2/3/4/5
0LQ3XOVH:LGWK QV
N
ew
0LQ3XOVH:LGWK QV
0LQ3XOVH:LGWK QV
0LQ3XOVH:LGWK QV
fo
r
m
en
de
d
9%$7&XUUHQW X$
om
ec
N
ot
R
9%$7 9
Figure 4.6. Typical One-Cell Suspend Mode Current
Rev. 1.2
53
Si1010/1/2/3/4/5
Table 4.3. Port I/O DC Electrical Characteristics
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Min
Output High Voltage
High Drive Strength, PnDRV.n = 1
IOH = –3 mA, Port I/O push-pull
IOH = –10 µA, Port I/O push-pull
IOH = –10 mA, Port I/O push-pull
VDD – 0.7
VDD – 0.1
—
—
See Chart
—
—
—
VDD – 0.7
VDD – 0.1
—
—
See Chart
—
—
—
—
—
See Chart
0.6
0.1
—
—
—
—
—
—
See Chart
0.6
0.1
—
VDD = 2.0 to 3.6 V
VDD – 0.6
—
—
High Drive Strength, PnDRV.n = 1
IOL = 8.5 mA
IOL = 10 µA
IOL = 25 mA
V
VDD = 0.9 to 2.0 V
0.7 x VDD
—
—
V
—
—
0.6
V
VDD = 0.9 to 2.0 V
—
—
0.3 x VDD
V
Weak Pullup Off
Weak Pullup On, VIN = 0 V, VDD = 1.8 V
Weak Pullup On, Vin = 0 V, VDD = 3.6 V
—
—
—
—
4
20
±1
—
35
µA
ec
R
N
ot
54
V
VDD = 2.0 to 3.6 V
om
Input Leakage
Current
m
en
de
d
Input Low Voltage
Unit
D
—
—
—
fo
r
Low Drive Strength, PnDRV.n = 0
IOL = 1.4 mA
IOL = 10 µA
IOL = 4 mA
Input High Voltage
Max
V
Low Drive Strength, PnDRV.n = 0
IOH = –1 mA, Port I/O push-pull
IOH = –10 µA, Port I/O push-pull
IOH = –3 mA, Port I/O push-pull
Output Low Voltage
Typ
es
ig
ns
Test Condition
N
ew
Parameters
Rev. 1.2
Si1010/1/2/3/4/5
3.6
VDD = 3.6V
3
VDD = 3.0V
2.7
VDD = 2.4V
2.4
VDD = 1.8V
2.1
D
Voltage
3.3
es
ig
ns
Typical VOH (High Drive Mode)
1.5
1.2
0.9
0
5
10
15
20
25
30
35
40
45
50
fo
r
Load Current (mA)
N
ew
1.8
Typical VOH (Low Drive Mode)
3.6
VDD = 3.6V
3
VDD = 3.0V
2.7
VDD = 2.4V
Voltage
m
en
de
d
3.3
2.4
VDD = 1.8V
2.1
1.8
om
1.5
1.2
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Load Current (mA)
Figure 4.7. Typical VOH Curves, 1.8–3.6 V
N
ot
R
ec
0.9
Rev. 1.2
55
Si1010/1/2/3/4/5
1.8
1.7
VDD = 1.8V
1.6
VDD = 1.5V
1.5
1.4
VDD = 1.2V
VDD = 0.9V
1.2
1.1
D
Voltage
1.3
1
0.8
0.7
0.6
0.5
0
1
2
3
4
5
6
7
8
9
10
11
12
fo
r
Load Current (mA)
N
ew
0.9
Typical VOH (Low Drive Mode)
1.8
1.7
m
en
de
d
VDD = 1.8V
1.6
VDD = 1.5V
1.5
1.4
VDD = 1.2V
Voltage
1.3
1.2
VDD = 0.9V
1.1
1
0.9
om
0.8
0.7
0.6
0
1
2
3
Load Current (mA)
Figure 4.8. Typical VOH Curves, 0.9–1.8 V
N
ot
R
ec
0.5
56
es
ig
ns
Typical VOH (High Drive Mode)
Rev. 1.2
Si1010/1/2/3/4/5
1.8
VDD = 3.6V
1.5
VDD = 3.0V
VDD = 2.4V
VDD = 1.8V
0.9
D
Voltage
1.2
es
ig
ns
Typical VOL (High Drive Mode)
0.3
0
-80
-70
-60
-50
-40
-30
N
ew
0.6
-20
-10
0
fo
r
Load Current (mA)
Typical VOL (Low Drive Mode)
m
en
de
d
1.8
VDD = 3.6V
1.5
VDD = 3.0V
Voltage
1.2
VDD = 2.4V
VDD = 1.8V
0.9
om
0.6
0.3
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
Load Current (mA)
Figure 4.9. Typical VOL Curves, 1.8–3.6 V
N
ot
R
ec
0
Rev. 1.2
57
Si1010/1/2/3/4/5
Typical VOL (High Drive Mode)
es
ig
ns
0.5
VDD = 1.8V
VDD = 1.5V
VDD = 1.2V
0.3
VDD = 0.9V
D
Voltage
0.4
N
ew
0.2
0.1
0
-5
-4
-3
-2
-1
0
fo
r
Load Current (mA)
Typical VOL (Low Drive Mode)
m
en
de
d
0.5
0.3
VDD = 1.8V
0.2
VDD = 1.5V
om
Voltage
0.4
VDD = 1.2V
0.1
VDD = 0.9V
-3
-2
-1
58
0
Load Current (mA)
Figure 4.10. Typical VOL Curves, 0.9–1.8 V
N
ot
R
ec
0
Rev. 1.2
Si1010/1/2/3/4/5
Table 4.4. Reset Electrical Characteristics
Min
Typ
Max
Unit
RST Output Low Voltage
IOL = 1.4 mA,
—
—
0.6
V
RST Input High Voltage
VDD = 2.0 to 3.6 V
VDD – 0.6
—
—
V
VDD = 0.9 to 2.0 V
0.7 x VDD
—
—
V
VDD = 2.0 to 3.6 V
—
—
0.6
V
VDD = 0.9 to 2.0 V
—
—
0.3 x VDD
V
RST Input Pullup Current
RST = 0.0 V, VDD = 1.8 V
RST = 0.0 V, VDD = 3.6 V
—
—
4
20
—
35
µA
VDD/DC+ Monitor Threshold (VRST)
Early Warning
Reset Trigger
(all power modes except Sleep)
1.8
1.7
1.85
1.75
1.9
1.8
V
One-cell mode: VBAT ramp 0–0.9 V
Two-cell mode: VBAT ramp 0–1.8 V
—
—
3
ms
Initial Power-On (VBAT Rising)
Early Warning
Brownout Condition (VBAT Falling)
Recovery from Brownout (VBAT Rising)
—
0.9
0.7
—
0.75
1.0
0.8
0.95
—
1.1
0.9
—
V
Missing Clock Detector
Timeout
Time from last system clock rising edge
to reset initiation
100
525
1000
µs
Minimum System Clock w/
Missing Clock Detector
Enabled
System clock frequency which triggers
a missing clock detector timeout
—
2
10
kHz
Delay between release of any reset
source and code
execution at location 0x0000
—
10
—
µs
Minimum RST Low Time to
Generate a System Reset
15
—
—
µs
VDD Monitor Turn-on Time
—
300
—
ns
VDD Monitor Supply
Current
—
10
—
µA
VBAT Ramp Time for
Power On
N
ot
R
ec
om
Reset Time Delay
m
en
de
d
VBAT Monitor Threshold
(VPOR)
N
ew
RST Input Low Voltage
D
Test Condition
fo
r
Parameter
es
ig
ns
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Rev. 1.2
59
Si1010/1/2/3/4/5
Table 4.5. Power Management Electrical Specifications
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Min
Typ
2
—
Low power oscillator
—
400
Precision oscillator
—
400
Two-cell mode
—
2
One-cell mode
—
10
Suspend Mode Wake-up Time
Sleep Mode Wake-up Time
Table 4.6. Flash Electrical Characteristics
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameter
Test Condition
Flash Size
Si1010/2/4
Si1011/3/5
m
en
de
d
Erase Cycle Time
Write Cycle Time
3
SYSCLKs
—
ns
—
ns
—
µs
—
µs
Min
Typ
Max
Unit
16384*
8192
512
1k
—
—
—
90 k
—
—
512
—
28
57
32
64
36
71
bytes
bytes
bytes
Erase/Write
Cycles
ms
µs
fo
r
Scratchpad Size
Endurance
Unit
N
ew
Idle Mode Wake-up Time
Max
es
ig
ns
Test Condition
D
Parameter
Note: On 16 kB devices, 1024 bytes at addresses 0x3C00 to 0x3FFF are reserved.
Table 4.7. Internal Precision Oscillator Electrical Characteristics
VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings.
Parameter
Oscillator Frequency
om
Oscillator Supply Current
(from VDD)
Test Condition
Min
Typ
Max
Unit
–40 to +85 °C,
VDD = 1.8–3.6 V
25 °C; includes bias current
of 90–100 µA
24
24.5
25
MHz
—
300*
—
µA
ec
Note: Does not include clock divider or clock tree supply current.
Table 4.8. Internal Low-Power Oscillator Electrical Characteristics
VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings.
R
Parameter
N
ot
Oscillator Frequency
Oscillator Supply Current
(from VDD)
Test Condition
–40 to +85 °C,
VDD = 1.8–3.6 V
25 °C
No separate bias current
required.
Note: Does not include clock divider or clock tree supply current.
60
Rev. 1.2
Min
Typ
Max
Unit
18
20
22
MHz
—
100*
—
µA
Si1010/1/2/3/4/5
Table 4.9. SmaRTClock Characteristics
VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings.
Test Condition
Oscillator Frequency (LFO)
Min
Typ
13.1
16.4
Table 4.10. ADC0 Electrical Characteristics
Max
Unit
19.7
kHz
es
ig
ns
Parameter
VDD = 1.8 to 3.6V V, VREF = 1.65 V (REFSL[1:0] = 11), –40 to +85 °C unless otherwise specified.
Parameter
Test Condition
Min
Typ
—
—
—
—
—
—
—
—
12
10
±1
±0.5
±0.8
±0.5
±
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