SI2401

Si2401/Si3008 V. 22 B I S I S O M O D E M ® W I T H L O W - C O S T D A A Features Data modem formats 2400 bps: V.22bis 1200 bps: V.22, V.23, Bell 212A 300 bps: V.21, Bell 103 Fast connect and V.23 reversing SIA and other security protocols Integrated DAA Over 6000 V capacitive isolation Parallel phone detection Compliant with FCC, China, JATE, and 31 other PTTs Line-in-use detection 27 MHz CLKIN support Caller ID detection and decode UART with flow control AT command set support Call progress support 3.3 V Power Lead-free and RoHS-compliant packages Ordering Information See page 66. Applications Set-top boxes Point-of-sale ATM terminals Security systems Medical monitoring Power meters Pin Assignments Si2401 CLKIN/XTALI 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 GPIO1/EOFR GPIO2/CD GPIO3/ESC VA GND GPIO4/INT/AOUT C1A C2A XTALO Description The Si2401 ISOmodem is a complete, two-chip, 2400 bps modem integrating Silicon Laboratories’ fourth-generation direct access arrangement (DAA), which provides a globally-programmable telephone line interface with an unprecedented level of integration. Available in two small packages, this compact solution eliminates the need for a separate DSP data pump, modem controller, codec, isolation transformer, relay, opto-isolators, and 2–4 wire hybrid. The Si2401 provides conventional data formats at connect rates of up to 2400 bps with full-duplex operation over the Public Switched Telephone Network (PSTN). This device is ideal for embedded modem applications due to its small size, minimal external component count, and low power consumption. ® GPIO5/RI VD RXD TXD CTS RESET Si3008 C1B C2B VREG CID 1 2 3 4 8 7 IGND 6 5 9 RX DCT QB QE Functional Block Diagram Si2401 RXD TXD CTS RESET U.S. Patent #5,870,046 U.S. Patent #6,061,009 Other patents pending UART µ Controller (AT Decoder, Call Progress) Isolation Interface CD/GPIO2 INT/GPIO4 RI/GPIO5 XTALI XOUT Control Interface DSP (Data Pump) To phone line Clock Interface Rev. 1.1 2/06 Copyright© 2006 by Silicon Laboratories Si3008 Si2401-Si3008 S i2401/Si3008 2 Rev. 1.1 S i2401/Si3008 TA B L E O F C O N T E N TS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3. Bill of Materials: Si2401/08 Chipset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2. Configurations and Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3. Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4. Parallel Phone Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.5. Interrupt Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.6. V.23 Operation/V.23 Reversing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.7. V.42 HDLC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.8. Fast Connect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 4.9. Clock Generation Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5. AT Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 5.1. Command Line Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2. End-Of-Line Character . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.3. AT Command Set Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 5.4. Alarm Industry AT Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.5. Modem Result Codes and Call Progress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6. Low Level DSP Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 6.1. DSP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.2. Call Progress Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7. S Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8. Pin Descriptions: Si2401 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 9. Pin Descriptions: Si3008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 10. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11. Package Outline: 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 12. Package Outline: 8-Pin Exposed Pad SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Rev. 1.1 3 S i2401/Si3008 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter1 Ambient Temperature Si2401 Supply Voltage, Digital3 Symbol TA VD Test Condition F-Grade Min2 0 3.0 Typ 25 3.3 Max2 70 3.6 Unit °C V Notes: 1. The Si2401 specifications are guaranteed when the typical application circuit (including component tolerance) and Si2401 and Si3008 are used. See "2. Typical Application Schematic" on page 9. 2. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. 3. The digital supply, VD, operates from 3.0 to 3.6 V. The Si2401 interface supports 5 V logic (CLKIN/XTALI supports 3.3 V logic only). Table 2. Loop Characteristics (VD = 3.0 to 3.6 V, TA = 0 to 70 °C, see Figure 1) Parameter DC Termination Voltage DC Termination Voltage On-Hook Leakage Current Operating Loop Current DC Ring Current Symbol VTR VTR ILK ILP Test Condition IL = 20 mA IL = 120 mA VTR = –100 V Min — 9 — 15 Typ — — — — 1.5 Max 7.5 — 12 120 3 Unit V V µA mA µA dc current flowing through ring detection circuitry VRD FR REN — Ring Detect Voltage* Ring Frequency Ringer Equivalence Number 10 15 — 15 — — 35 68 0.2 Vrms Hz *Note: The ring signal is guaranteed to be undetected below the minimum. The ring signal is guaranteed to be detected above the maximum. 4 Rev. 1.1 S i2401/Si3008 Table 3. DC Characteristics* (VD = 3.0 to 3.6 V, TA = 0 to 70°C for F-Grade) Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Low Level Output Voltage, GPIO1–4 Input Leakage Current Pullup Resistance Pins 5,7,11,14 Power Supply Current, Digital Power Supply Current, DSP Powerdown Power Supply Current, Wake-On-Ring Power Supply Current, Total Powerdown Symbol VIH VIL VOH VOL VOL IL RPU ID ID ID ID Test Condition Min 2.0 — Typ — — — — — — 100 10 8 7 100 Max — 0.8 — 0.35 0.6 10 200 15 12 10 — Unit V V V V V µA kΩ mA mA mA µA IO = –2 mA IO = 1 mA IO = 10 mA 2.4 — — –10 50 VD pin SEB[3] = 1 ATZ SF1[5] =1, SF1[6] =1 — — — — *Note: Measurements are taken with inputs at rails and no loads on outputs. TIP + 600 Ω IL 10 μ F Si3008 VTR – RING Figure 1. Test Circuit for Loop Characteristics Rev. 1.1 5 S i2401/Si3008 Table 4. AC Characteristics (VD = 3.0 to 3.6 V, TA = 0 to 70 °C for K-Grade, Fs = 8 kHz) Parameter Sample Rate Clock Input Frequency Clock Input Frequency Receive Frequency Response Transmit Full Scale Level Dynamic Range3,4,5 1 Symbol Fs FXTL FXTL Test Condition default DCL then ACL = LCS(t) If (ACL – LCS[t – 40 ms x DGSR]) > DCL) and (ACL – LCS[t]) > DCL), an intrusion is sent to the host. The very first sample of LCS the algorithm uses after going off-hook does not have any previous samples for comparison. If LCS was measured during a previous call, this value of LCS may be used as an initial reference. ACL may be written by the host with this known value of LCS. If ACL is non-zero, the ISOmodem chipset uses ACL as the first valid LCS sample in the off-hook intrusion algorithm. If ACL is 0 (default after reset), the ISOmodem chipset ignores the register and does not begin operating the algorithm until two LCS samples have been received. Additionally, immediately after a modem call, ACL is updated automatically with the last valid LCS value before a parallel phone detection (PPD) intrusion or going back on-hook. The off-hook intrusion algorithm does not begin to operate immediately after going off-hook. This is to avoid triggering an interrupt due to transients resulting from the ISOmodem chipset itself going from on-hook to off-hook. The time that elapses between the ISOmodem chipset going off-hook and the intrusion algorithm starting defaults to one second and may be adjusted via the IST register (S82, bits 7:4). If ACL is written to a non-zero value before going off-hook, a parallel phone intrusion that occurs during this IST interval and sustains through the end of the interval triggers an interrupt.7 The off-hook intrusion algorithm may, additionally, be disabled for a period of time after dialing begins via the IB register (S82, bits 2:1). This avoids triggering an interrupt due to pulse dialing, open-switch intervals, or line transients from central office switching. Intrusion may be disabled from the start of dialing to the end of dialing (IB = Dlb), from the start of dialing to the timeout of the IS (S29, bits 7:0) by setting IB = 10b(IB = 2) or from the start of dial to carrier detect by setting IB = 11. The off-hook intrusion algorithm is only suspended (not disabled) during this IB interval. Therefore, any intrusion that occurs during the IB interval and sustains through the end of the interval triggers a PPD interrupt. 4.5. Interrupt Detection The INT interrupt pin can be programmed to alert the host of loss-of-carrier, loss-of-phone-line voltage/ current, parallel phone detection, and other interrupts listed in the interrupt status mask (S08). After the host receives an interrupt via the INT pin, the host should issue the AT:I command. This command causes a readclear of the WOR, PPD, NLD, RI, OCD, and REV bits of the S09 register and raises (deactivates) the INT pin. All the interrupt status bits in register S09 remain high after being set until cleared by the AT:I command. 4.5.1. Loop Current Detection In addition to monitoring parallel phone intrusion, it is possible to monitor the loss of loop current. This feature can be enabled by setting S08[4] (NLDM) = 1. This feature is disabled by default. If the loop current is too low for normal DAA operation, S09[4] (NLD) is set. During this event, if the NLR result code is enabled by setting S62[1](NLR) = 1, the “l” result code is sent. Once the loop current returns to a normal current state, the “L” Rev. 1.1 15 S i2401/Si3008 result code is sent. The INT pin is also asserted if enabled. 4.5.2. Loss-of-Carrier Detection The Si2401 has two methods of implementing a loss-ofcarrier function. If GPIO4 is programmed as INT and if S08[7](CDM) = 1, INT asserts in data mode when a loss-of-carrier is detected. The carrier detect function may also be implemented on GPIO2 by setting SE2[3:2] (GPIO2) = 01 and SOC[7](CDE) = 1. 4.5.3. Caller ID Decoding Operation The Si2401 supports full caller ID detection and decode for US Bellcore and UK standards. To use the caller ID decoding feature, the following configuration is necessary: 1. Set SE0[3] (ND) = 0b (set modem to 8N1 configuration). 2. Set S0C[6:5] (CIDM) = 01 (set modem to Bellcore type caller ID) or S13[2] (CIDB) = 1 (set modem to UK type caller ID). 4.5.4. Caller ID Monitor/Bellcore Caller ID The Si2401 continuously monitors the phone line for the caller ID mark signals. This can be useful in systems that require detection of caller ID data before the ring signal, voice mail indicator signals, and Type II caller ID monitor support. To force the Si2401 into caller ID monitor mode, set SOC[6:5] (CIDM) = 11. Note: CIDM should be disabled before going off-hook. is made with the modem transmitting at 1200/600 bps and receiving at 75 bps. The modem responds with a “v” character if a V.23 connection is established with the modem transmitting at 75 bps and receiving at 1200/ 600 bps. The Si2401 supports the V.23 turnaround procedure. This allows a modem that is transmitting at 75 bps to initiate a “turnaround” procedure so that it can begin transmitting data at 1200/600 bps and receiving data at 75 bps. The modem is defined as being in V.23 master mode if it is transmitting at 75 bps, and it is defined as being in slave mode if the modem is transmitting at 1200/600 bps. The following paragraphs give a detailed description of the V.23 turnaround procedure. 4.6.1. Modem in Master Mode To perform a direct turnaround once a modem connection is established, the master host goes into online command mode by sending an escape command (Escape pin activation, TIES, or ninth bit escape) to the master modem. Note: The host can initiate a turnaround only if the Si2401 is the master. 4.5.5. UK Caller ID Operation The Si2401 starts searching for the Idle State Tone Alert Signal. When this signal has been detected, the Si2401 transmits an “a” to the host. After the Idle State Tone Alert Signal is completed, the Si2401 applies the wetting pulse for the required 15 ms by quickly going off-hook and on-hook. From this point on, the algorithm is identical to that of Bellcore in that it searches for the channel seizure signal and the marks before echoing an “m” and then reports the decoded caller ID data. The host then sends the ATRO command to the Si2401 to initiate a V.23 turnaround and return to the online (data) mode. The Si2401 then changes its carrier frequency (from 390 Hz to 1300 Hz) and waits to detect a 390 Hz carrier for 440 ms. If the modem detects more than 40 ms of a 390 Hz carrier in a time window of 440 ms, it echoes the “c” response character. If the modem does not detect more than 40 ms of a 390 Hz carrier in a time window of 440 ms, it hangs up and echoes the “N” (no carrier) character as a response. 4.6.2. Modem in Slave Mode Configure GPIO4 as INT (SE2[7:6] [GPIO4] = 11). The Si2401 performs a reverse turnaround when it detects a carrier drop longer than 20 ms. The Si2401 then reverses (changes its carrier from 1300 Hz to 390 Hz) and waits to detect a 1300 Hz carrier for 400 ms. If the Si2401 detects more than 40 ms of a 1300 Hz carrier in a time window of 400 ms, it sets the S09[7] bit, and the next character echoed by the Si2401 is a “v”. If the Si2401 does not detect more than 40 ms of the 1300 Hz carrier in a time window of 400 ms, it reverses again and waits to detect a 390 Hz carrier for 440 ms. Then, if the Si2401 detects more than 40 ms of a 390 Hz carrier in a time window of 220 ms, it sets the S09[7] bit, and the next character echoed by the Si2401 is a “c”. At this point, if the Si2401 does not detect more than 40 ms of the 390 Hz carrier in a time window of 440 ms, it hangs up, sets the S09[7] bit, and the next character 4.6. V.23 Operation/V.23 Reversing The Si2401 supports full V.23 operation including the V.23 reversing procedure. V.23 operation is enabled by setting S07 (MF1) = xx10xx00b or xx01xx00b. If S07[5] (V23R) = 1, the Si2401 transmits data at 75 bps and receives data at 600 or 1200 bps. If S07[4] (V23T) = 1, the Si2401 receives data at 75 bps and transmits data at 600 or 1200 bps. S07[2] (BAUD) is the 1200 or 600 bps indicator. BAUD = 1 enables the 1200/600 V.23 channel to run at 1200 bps, while BAUD = 0b enables 600 bps operation. When a V.23 connection is successfully established, the modem responds with a “c” character if the connection 16 Rev. 1.1 S i2401/Si3008 echoed by the Si2401 is an “N” (no carrier). Successful completion of a turnaround procedure in master or slave mode automatically updates S07[4] (V23T) and S07[5] (V23R) to indicate the new status of the V.23 connection. To avoid using the INT pin, the host may also be notified of the INT condition by using 9-bit data mode. Setting S15[0] (NBE) = 1 and S0C[3] (9BF) = 0b configures the ninth bit on the Si2401 TXD path to function exactly as the INT pin has been described. 1. After the call is connected, the host should begin sending the frame data to the Si2401 using the CTS flow control to ensure data synchronicity. 2. When the frame is complete, the host should simply stop sending data to the Si2401. Since the Si2401 does not yet recognize the end-of-frame, it expects an extra byte and assert CTS as shown in Figure 4A. If CTS is used to cause a host interrupt, this final interrupt should be ignored by the host. 3. When the Si2401 is ready to send the next byte, if it has not yet received any data from the host, it recognizes this as an end-of-frame, raise CTS, calculates the final CRC code, transmits the code, and begins transmitting stop flags. 4. After transmitting the first stop flag, the Si2401 lowers CTS, indicating that it is ready to receive the next frame from the host. At this point, the process repeats as in Step 1. The method of receiving HDLC frames is as follows: 1. After the call is connected, the Si2401 searches for flag data. Then, once the first non-flag word is detected, the CRC is continuously computed, and the data is sent across the UART (8-bit data or 9-bit data mode) to the host after removing the HDLC zero-bit insertion. The DTE rate of the host must be at least as high as that of data transmission. HDLC mode only works with 8-bit data words; the ninth bit is used only for escape on TXD and end-of-frame received (EOFR) on RXD. 2. When the Si2401 detects the stop flag, it sends the last data word in the frame as well as the two CRC bytes and determines if the CRC checksum matches. Thus, the last two bytes are not frame data but are the CRC bytes, which can be discarded by the host. If the checksum matches, the Si2401 echoes “G” (good). If the checksum does not match, the Si2401 echoes “e” (error). Additionally, if the Si2401 detects an abort (seven or more contiguous ones), it echoes an “A”. When the “G”, “e”, or “A” (referred to as a frame result word) is sent, the Si2401 raises the EOFR (end of frame receive) pin (see Figure 4B). The GPIO1 pin must be configured as EOFR by setting SE4[3] (GPE) = 1. In addition to using the EOFR pin to indicate that the byte is a frame result word, if in 9bit data mode (set S15[0] (NBE) = 1), the ninth bit is raised if the byte is a frame result word. To program this mode, set S0C[3] (9BF) = 1 and SE0[3] (ND) = 1. 3. When the next frame of data is detected, EOFR is lowered, and the process repeats at Step 1. 4.7. V.42 HDLC Mode The Si2401 supports V.42 through hardware HDLC framing in all modem data modes. Frame packing and unpacking including opening and closing flag generation and detection, CRC computation and checking, zero insertion and deletion, and modem data transmission and reception are all performed by the Si2401. V.42 error correction and V.42bis data compression must be performed by the host. The digital link interface in this mode uses the same UART interface (8-bit data and 9-bit data formats) as in the asynchronous modes, and the ninth data bit may be used as an escape by setting S15[0] (NBE) = 1. When using HDLC in 9-bit data mode, if the ninth bit is not used as an escape, it is ignored. To use the HDLC feature on the Si2401, the host must enable HDLC operation by setting S13[1] (HDEN) = 1. The host may initiate the call or answer the call using either the “ATDT#”, the “ATA” command or the autoanswer mode. (The auto-answer mode is implemented by setting register S00 (NR) to a non-zero value.) When the call is connected, a “c”, “d”, or “v” is echoed to the host controller. The host may now send/receive data across the UART using either the 8-bit or 9-bit data formats with flow control. At this point, the Si2401 begins framing data into the HDLC format. On the transmit side, if no data is available from the host, the HDLC flag pattern is sent repeatedly. When data is available, the Si2401 computes the CRC code throughout the frame, and the data is sent with the HDLC zero-bit insertion algorithm. HDLC flow control operates in a manner similar to normal asynchronous flow control across the UART and is shown in Figure 4. To operate flow control (using the CTS pin to indicate when the Si2401 is ready to accept a character), a DTE rate higher than the line rate should be selected. The method of transmitting HDLC frames is as follows: Rev. 1.1 17 S i2401/Si3008 To summarize, when receiving HDLC frames, the host begins receiving data asynchronously from the Si2401. When each byte is received, the host should check the EOFR pin (or the ninth bit). If the EOFR pin (or the ninth bit) is low, the data is valid frame data. If the EOFR pin (or the ninth bit) is high, the data is a frame result word. 4.9. Clock Generation Subsystem The Si2401 contains an on-chip clock generator. Using a single master clock input, the Si2401 can generate all modem sample rates necessary to support V.22bis, V.22/Bell212A, and V.21/Bell103 standards and a 9.6 kHz rate for audio playback. Either a 27 MHz or 4.9152 MHz clock on XTALI or a 4.9152 MHz crystal across XTALI and XTALO form the master clock for the Si2401. This clock source is sent to an internal phaselocked loop (PLL) that generates all necessary internal system clocks. The PLL has a settling time of ~1 ms. Data on RXD should not be sent to the device prior to settling of the PLL. By default, the Si2401 assumes a 4.9152 MHz clock input. If a 27 MHz clock on XTALI is used, a pulldown resistor B? TDET Filter A Energy Detect 20log10(4096/CPDL) –43 dBm Figure 5. Programmable Call Progress Filter Architecture 30 Rev. 1.1 S i2401/Si3008 7. S Registers Any register not documented here is reserved and should not be written. Bold selection in bit-mapped registers indicates default values. Table 21. S-Register Summary “S” Register S00 S01 S02 S03 S04 S05 S06 S07 S08 S09 S0C S0D S0E S0F S10 S11 S12 Register Address (hex) 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 Name Function Reset NR DW CW CLW TD OFFPD ONPD MF1 INTM INTS MF2 MF3 DIT TEC TDT OFHI ACL Number of rings before answer; 0 suppresses auto answer. Number of seconds modem waits before dialing after going off-hook (maximum of 109 seconds). Number of seconds modem waits for a dial tone before hang-up added to time specified by DW (maximum of 109 seconds). Duration that the modem waits (53.33 ms units) after loss of carrier before hanging up. Both duration and spacing (5/3 ms units) of DTMF dialed tones. Duration of off-hook time (5/3 ms units) for pulse dialing. Duration of on-hook time (5/3 ms units) for pulse dialing. This is a bit-mapped register.* This is a bit-mapped register.* This is a bit-mapped register.* This is a bit-mapped register.* This is a bit-mapped register.* Pulse dialing Interdigit time (10 ms units added to a minimum time of 64 ms). TIES escape character. Default = +. TIES delay time (53.33 ms units). This is a bit-mapped register.* Absolute Current Level. When S13[4] (OFHD) = 0b, ACL represents the absolute current threshold used by the off-hook intrusion algorithm (1 mA units.) This is a bit-mapped register.* This is a bit-mapped register. * 0x00 0x02 0x03 0x0E 0x30 0x18 0x24 0x06 0x00 0x00 0x00 0x00 0x46 0x2B 0x13 0x04 0x00 S13 S15 S16 S17 0x13 0x15 0x16 0x17 MF4 MLC BTON BTOF 0x10 0x04 0x32 0x32 Busy tone on. Time that the busy tone must be on (10 ms units) for busy tone detector. Busy tone off. Time that the busy tone must be off (10 ms units) for busy tone detector. *Note: These registers are explained in detail in the following section. Rev. 1.1 31 S i2401/Si3008 Table 21. S-Register Summary (Continued) “S” Register S18 Register Address (hex) 0x18 Name Function Reset BTOD Busy tone delta time (10 ms units). A busy tone is detected to be valid if (BTON – BTOD < on time < BTON + BTOD) and (BTOF – BTOD < off time < BTOF + BTOD). Ringback tone on. Time that the ringback tone must be on (53.333 ms units) for ringback tone detector. Ringback tone off. Time that the ringback tone must be off (53.333 ms units) for ringback tone detector. Detector time delta (53.333 ms units). A ringback tone is determined to be valid if (RTON – RTOD < on time < RTON + RTOD) and (RTOF – RTOD < off time < RTOF + RTOD). Dial tone detect time. The time that the dial tone must be valid before being detected (10 ms units). Transmit answer tone length. Answer tone length in seconds when answering a call (1 s units). Answer tone to transmit delay. Delay between answer tone end and transmit data start (5/3 ms units). Unscrambled ones length. Minimum length of time required for detection of unscrambled binary ones during V.22 handshaking by a calling modem (5/3 ms units). Transmit scrambled ones delay. Time between unscrambled binary one detection and scrambled binary one transmission by a call mode V.22 modem (53.3 ms units). Transmit scrambled ones length. Length of time scrambled ones are sent by a call mode V.22 modem (5/3 ms units). V.22X data delay low. Delay between handshake complete and data connection for a V.22X call mode modem (5/3 ms units added to the time specified by VDDH). V.22X data delay high. Delay between handshake complete and data connection for a V.22X call mode modem (256 x 5/3 ms units added to the time specified by VDDL). S1 pattern time length. Amount of time the unscrambled S1 pattern is sent by a call mode V.22bis modem (5/3 ms units). V.22bis 1200 bps scrambled ones length. Minimum length of time for transmission of 1200 bps scrambled binary ones by a call mode V.22bis modem after the end of pattern S1 detection (53.3 ms). V.22bis 2400 bps scrambled ones length low. Minimum length of time for transmission of 2400 bps scrambled binary ones by a call mode V.22bis modem (5/3 ms units). 0x0F S19 S1A S1B 0x19 0x1A 0x1B RTON RTOF RTOD 0x26 0x4B 0x07 S1C 0x1C DTT 0x0A S1E S1F S20 0x1E 0x1F 0x20 TATL ARM3 UNL 0x03 0x2D 0x5D S21 0x21 TSOD 0x09 S22 S23 0x22 0x23 TSOL VDDL 0xA2 0xCB S24 0x24 VDDH 0x08 S25 S26 0x25 0x26 SPTL VTSO 0x3C 0x0C S27 0x27 VTSOL 0x78 *Note: These registers are explained in detail in the following section. 32 Rev. 1.1 S i2401/Si3008 Table 21. S-Register Summary (Continued) “S” Register S28 Register Address (hex) 0x28 Name Function Reset VTSOH V.22bis 2400 bps scrambled ones length high. Minimum length of time for transmission of 2400 bps scrambled binary ones by a call mode V.22bis modem (256 x 5/3 ms units added to the time specified by VTSOL). Intrusion suspend. When S82[2:1] (IB) = 10b, this register sets the length of time from when dialing begins that the off-hook intrusion algorithm is blocked (suspended) (500 ms units). Receive scrambled ones V.22bis (2400 bps) length. Minimum length of time required for detection of scrambled binary ones during V.22bis handshaking by the answering modem after S1 pattern conclusion (5/3 ms units). V.23 direct turnaround carrier length. Minimum length of time that a master mode V.23 modem must detect carrier when searching for a direct turnaround sequence (5/3 ms units). V.23 direct turnaround timeout. Length of time that the modem searches for a direct turnaround carrier (5/3 ms units added to a minimum time of 426.66 ms). V.23 slave carrier detect loss. Minimum length of time that a slave mode V.23 modem must lose carrier before searching for a reverse turnaround sequence (5/3 ms units). V.23 reverse turnaround carrier timeout. Amount of time a slave mode V.23 modem searches for carriers during potential reverse turnaround sequences (5/3 ms units). FSK connection delay low. Amount of time delay added between end of answer tone handshake and actual modem connection for FSK modem connections (5/3 ms units). FSK connection delay high. Amount of time delay added between end of answer tone handshake and actual modem connection for FSK modem connections (256 x 5/3 ms units). Receive answer tone length. Minimum length of time required for detection of a CCITT answer tone (5/3 ms units). The time after going off-hook when the loop current sense bits are checked for overcurrent status (5/3 ms units). Answer tone length when answering a call (5/3 ms units). This register is only used if TATL (1E) has a value of zero. Receive scrambled ones V.22 length (5/3 ms units). Minimum length of time that an originating V.22 (1200 bps) modem must detect 1200 bps scrambled ones during a V.22 handshake. Second kissoff tone detector length. The security modes, A1 and !1, echo a “k” if a kissoff tone longer than the value stored in SKDTL is detected (10 ms units). 0x08 S29 0x29 IS 0x00 S2A 0x2A RSO 0xD2 S2B 0x2B DTL 0x18 S2C 0x2C DTTO 0x08 S2D 0x2D SDL 0x0C S2E 0x2E RTCT 0xF0 S2F 0x2F FCD 0x3C S30 0x30 FCDH 0x00 S31 S32 S34 S35 0x31 0x32 0x34 0x35 RATL OCDT TASL RSOL 0x3C 0x0C 0x5A 0xA2 S36 0x36 ARM1 0x30 *Note: These registers are explained in detail in the following section. Rev. 1.1 33 S i2401/Si3008 Table 21. S-Register Summary (Continued) “S” Register S37 Register Address (hex) 0x37 Name Function Reset CDR Carrier detect return. Minimum length of time that a carrier must return and be detected in order to be recognized after a carrier loss is detected (5/3 ms units). Carrier detect timeout. Amount of time modem waits for carrier detect before aborting call (1 second units). Delay between going off-hook and answer tone generation when in answer mode (53.33 ms units). Minimum number of consecutive ring pulses per ring burst. This is a bit mapped register. This is a bit mapped register. This is a bit mapped * * 0x20 S39 S3A S3B S3C S62 S82 SDB 0x39 0x3A 0x3B 0x3C 0x62 0x82 0xDB CDT ATD RP CIDG RC IST LVS 0x3C 0x29 0x03 0x01 0x41 0x08 register.* Line Voltage Status. Eight bit signed, 2s complement number representing the tip-ring voltage. Each bit represents 1 volt. Polarity of the voltage is represented by the MSB (sign bit). 0000_0000 = Measured voltage is < 3 V. This is a bit mapped register.* This is a bit mapped register.* This is a bit mapped register.* This is a bit mapped register.* This is a bit mapped register.* This is a bit mapped register.* (SE8 = 0x00) Write only definition. DSP register address lower bits [7:0].* (SE8 = 0x01) Write only definition. DSP data word lower bits [7:0].* (SE8 = 0x02) Read only definition. This is a bit mapped register.1 (SE8 = 0x02) Write only definition. This is a bit mapped register.1 (SE8 = 0x00) Write only definition. DSP register address upper bits [15:8]. (SE8 = 0x01) Write only definition. DSP data word upper bits [13:8] (SE8 = 0x02) Write only definition. This is a bit mapped register.1 Set the mode to define E5 and E6 for low level DSP control. 0x0C 0x22 0x04 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 SDF SE0 SE1 SE2 SE3 SE4 SE5 SE5 SE5 SE5 SE6 SE6 SE6 SE8 0xDF 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE5 0xE5 0xE5 0xE6 0xE6 0xE6 0xE8 DGSR CF1 GPIO1 GPIO2 GPD CF5 DADL DDL DSP1 DSP2 DADH DDH DSP3 DSPR4 *Note: These registers are explained in detail in the following section. 34 Rev. 1.1 S i2401/Si3008 Table 21. S-Register Summary (Continued) “S” Register SEB SEC SED SEE SF0 SF1 SF2 SF3 Register Address (hex) 0xEB 0xEC 0xED 0xEE 0xF0 0xF1 0xF2 0xF3 Name Function Reset TPD RVC1 RVC2 RVC3 DAA0 DAA1 DAA2 DAA3 This is a bit mapped register.* This is a bit mapped register. This is a bit mapped register. This is a bit mapped * * 0x00 0x88 0x19 0x16 0x40 0x0C 0x00 0x00 register.* * * This is a bit mapped register. This is a bit mapped register. This is a bit mapped register.* Line Current Status. Eight-bit value returning the loop current. Each bit represents 1.1 mA of loop current. Accuracy is not guaranteed if the loop current is less than required for normal operation. This is a bit mapped register.* This is a bit mapped register.* This is a bit mapped register.* This is a bit mapped register.* This is a bit mapped register.* This is a bit mapped register.* SF4 SF5 SF6 SF7 SF8 SF9 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 DAA4 DAA5 DAA6 DAA7 DAA8 DAA9 0x0F 0x00 0xF0 0x00 — 0x20 *Note: These registers are explained in detail in the following section. Rev. 1.1 35 S i2401/Si3008 Table 22. Bit Mapped Register Summary “S” Register Register Register Address Name (hex) S07 S08 S09 S0C S0D S11 S13 S15 S3C S62 S82 SDF SE0 SE1 SE2 SE3 SE4 SE5 SE5 SE6 SEB SEC SED SEE SF0 SF1 SF2 0x07 0x08 0x09 0x0C 0x0D 0x11 0x13 0x15 0x3C 0x62 0x82 0xDF 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE5 0xE6 0xEB 0xEC 0xED 0xEE 0xF0 0xF1 0xF2 MF1 INTM INTS MF2 MF3 OFHI MF4 MLC CIDG RC IST DGSR CF1 GPIO1 GPIO2 GPD CF5 DSP1 DSP2 DSP3 TPD RVC1 RVC2 RVC3 DAA0 DAA1 DAA2 RTO[3:0] FOH[1:0] PDN PDL LVFD FDT HBE RNGV RDLY[2:0] CPSQ CPCD NBCK DDAV SBCK TDET DTM[3:0] USEN2 USEN1 PDDE RCC[2:0] RAS[5:0] RMX[3:0] LM[1:0] V23E DRT GPIO4[1:0] GPIO3[1:0] GPIO2[1:0] GPD4 GPE TONE[4:0] TONC[2:0] GPD3 ICTS OCR IST[3:0] LCLD DGSR[6:0] ND SD[2:0] GPD5 GPIO5 IR ATPRE BTID VCTE FHGE OFHD EHGE STB CDM CD CDE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Binary 0000_0110 0000_0000 0000_0000 0000_0000 EHE 0000_0000 0000_0100 0001_0000 NBE 0000_0100 0000_0001 RR 0100_0001 0000_1000 0000_1100 0010_0010 0000_0000 0000_0000 0000_0000 0000_0000 0000_0000 0000_0000 BD V23R V23T NVDM NVD RIM RI 9BF RBTS EHR BAUD CCITT CIDM CID BDL EHB MLB EHI FSK REVM REV WORM PPDM WOR PPD CIDM[1:0] RI INTP DCL[3:0] CIDB HDEN BDA[1:0] CIDG[2:0] NLR IB[1:0] GPIO1[1:0] GPD2 GPD1 ANSE DTMFE 0000_0000 0000_0000 1000_1000 0001_1001 0001_0110 0100_0000 0000_1100 0000_0000 36 Rev. 1.1 S i2401/Si3008 Table 22. Bit Mapped Register Summary (Continued) “S” Register Register Register Address Name (hex) SF4 SF5 SF8 SF9 SFC 0xF4 0xF5 0xF8 0xF9 0xFC DAA4 DAA5 DAA8 DAA9 DAAFC CTSM LRV[3:0] OVL ROV Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Binary 0000_1111 0000_0000 — 0010_0000 0000_0000 ARL[1:0] ATL[1:0] RT Rev. 1.1 37 S i2401/Si3008 S07 (MF1). Modem Functions 1 Bit Name Type D7 D6 BD R/W D5 V23R R/W D4 V23T R/W D3 D2 BAUD R/W D1 CCITT R/W D0 FSK R/W Reset settings = 0000_0110 (0x06) Bit 7 6 Name Reserved BD Read returns zero. Blind Dialing. 0 = Disable. 1 = Enable (Blind dialing occurs immediately after “ATDT#” command). 5 V23R V.23 Receive.* V.23 75 bps send/600 (BAUD = 0) or 1200 (BAUD = 1) bps receive. 0 = Disable. 1 = Enable. 4 V23T V.23 Transmit.* V.23 600 (BAUD = 0) or 1200 (BAUD = 1) bps send/75 bps receive. 0 = Disable. 1 = Enable. 3 2 Reserved BAUD Read returns zero. 2400/1200 Baud Select.* 2400/1200 baud select (V23R = 0 and V23T = 0). 0 = 1200 1 = 2400 600/1200 baud select (V23R = 1 and V23T = 1). 0 = 600 1 = 1200 1 CCITT CCITT/Bell Mode.* 0 = Bell. 1 = CCITT. 0 FSK 300 bps FSK.* 0 = Disable. 1 = Enable. *Note: See Table 10 on page 13 for proper setting of modem protocols. Function 38 Rev. 1.1 S i2401/Si3008 S08 (INTM). Interrupt Mask Bit Name Type D7 CDM R/W D6 WORM R/W D5 PPDM R/W D4 NVDM R/W D3 RIM R/W D2 CIDM R/W R/W D1 D0 REVM R/W Reset settings = 0000_0000 (0x00) Bit 7 Name CDM Function Carrier Detect Mask. 0 = Change in CD does not affect INT. 1 = A high to low transition in CD (S09, bit 7), which indicates loss of carrier, activates INT. Wake-on-Ring Mask. 0 = Change in CD does not affect INT. 1 = A low to high transition in WOR (S09, bit 6) activatesINT. Parallel Phone Detect Mask. 0 = Change in PPD does not affect INT. 1 = A low to high transition in PPD (S09, bit 5) activates INT. No Phone Line Detect Mask. 0 = Change in NLD does not affect INT. 1 = A low to high transition in NLD (S09, bit 4) activates INT. Ring Indicator Mask. 0 = Change in RI does not affect INT. 1 = A low to high transition in RI (S09, bit 3) activates INT. Caller ID Mask. 0 = Change in CID does not affect INT. 1 = A low to high transition in CID (S09, bit 2) activates INT. Read returns zero. V.23 Reversal Detect Mask. 0 = Change in REV does not affect INT. 1 = A low to high transition in REV (S09, bit 0) activates INT. 6 WORM 5 PPDM 4 NVDM 3 RIM 2 CIDM 1 0 Reserved REVM Rev. 1.1 39 S i2401/Si3008 S09 (INTS). Interrupt Status Bit Name Type D7 CD R/W D6 WOR R/W D5 PPD R/W D4 NVD R/W D3 RI R/W D2 CID R/W R/W D1 D0 REV R/W Reset settings = 0000_0000 (0x00) Bit 7 Name CD Function Carrier Detect (sticky). Active high bit indicates carrier detected (equivalent to inverse of CD pin). Clears on :1 read. Wake-on-Ring (sticky). Wake-on-ring has occurred. Clears on :I read. Parallel Phone Detect (sticky). Parallel phone detected since last off-hook event. Clears on :I read. No Phone Line Detect (sticky). No line phone detected. Clears on :I read. Ring Indicator (sticky). Active high bit when the Si2401 is on-hook, indicates ring event has occurred. Clears on :I read. Caller ID (sticky). Caller ID preamble has been detected; data soon follows. Clears on :I read. Read returns zero. V.23 Reversal Detect (sticky). V.23 reversal condition has occurred. Clears on :I read. 6 5 4 3 WOR PPD NVD RI 2 1 0 CID Reserved REV 40 Rev. 1.1 S i2401/Si3008 S0C (MF2). Modem Functions 2 Bit Name Type D7 CDE R/W D6 D5 D4 D3 9BF R/W D2 BDL R/W D1 MLB R/W D0 CIDM[1:0] R/W Reset settings = 0000_0000 (0x00) Bit 7 Name CDE Carrier Detect Enable. 0 = Disable. 1 = Enable GPI02 as an active low carrier detect pin (must also set SE2[3:2] [GPIO2] = 01). 6:5 CIDM[1:0] Caller ID Monitor. 00 = Caller ID monitor disabled. 01 = Caller ID monitor enabled. Si2401 must detect channel seizure signal followed by marks in order to report caller ID data. (Normal Bellcore caller ID) 10 = Reserved. 11 = Caller ID monitor enabled. Si2401 must only detect marks in order to report caller ID data. 4 3 Reserved 9BF Read returns zero. Ninth Bit Function. Only valid if the ninth bit escape is set S15[0] (NBE). 0 = Ninth bit equivalent to ALERT. 1 = Ninth bit equivalent to HDLC EOFR. 2 BDL Blind Dialing. 0 = Blind dialing disabled. 1 = Enables blind dialing after dial timeout register S02 (CW) expires. 1 MLB Modem Loopback. 0 = Not swapped. 1 = Swaps frequency bands in modem algorithm to do a loopback in a test mode. 0 Reserved Read returns zero. Function Rev. 1.1 41 S i2401/Si3008 SOD (MF3). Modem Functions 3 Bit Name Type D7 D6 RI R/W D5 INTP R/W D4 RBTS R/W D3 EHR R/W D2 EHB R/W D1 EHI R/W D0 EHE R/W Reset settings = 0000_0000 (0x00) Bit 7 6 Name Reserved RI Read returns zero. Ring Indicator Control. Specifies the functionality of pin3. 0 = Pin 3 functions as GPIO5 controlled by register SE1. 1 = Pin 3 functions as RI. RI asserts during a ring and negates when no ring is present. INT Polarity. Specifies the polarity of the INT function on pin 11. 0 = An interrupt forces pin 11 low. 1 = An interrupt forces pin 11 high. Ringback Tone Selector. Controls the unit step size for registers S19, S1A and S1B. 0 = 53.33 ms units. Necessary for detecting a ringback tone. 1 = 10 ms units. Necessary for detecting a reorder tone. Enable Hangup on Reorder. Modem is placed on-hook if a ringback or reorder tone is detected. See S0D[4]. 0 = Disable. 1 = Enable. Enable Hangup on Busy. Modem is placed on-hook if a busy signal is detected. 0 = Disable. 1 = Enable. Enable Hangup on Intrusion. Modem is placed on-hook if parallel intrusion is detected. 0 = Disable. 1 = Enable. Enable Hangup on Escape. Modem is placed on-hook if a ESC signal is detected. 0 = Disable. 1 = Enable. Function 5 INTP 4 RBTS 3 EHR 2 EHB 1 EHI 0 EHE 42 Rev. 1.1 S i2401/Si3008 S11 (OFHI). Off-Hook Intrusion Bit Name Type Reset settings = 0000_0100 (0x04) Bit 7:4 3:0 Name Reserved DCL[3:0] Read returns zero. Differential Current Level. Differential current level to detect intrusion event (1 mA units). Function D7 D6 D5 D4 D3 D2 D1 DCL[3:0] R/W D0 S13 (MF4). Modem Functions 4 Bit Name Type D7 D6 BTID R/W R/W D5 D4 OFHD R/W D3 D2 CIDB R/W D1 HDEN R/W D0 Reset settings = 0001_0000 (0x10) Bit 7 6 Name Reserved BTID Read returns zero. BT Caller ID Wetting Pulse. 0 = Enable. 1 = Disable. 5 4 Reserved OFHD Read returns zero. Off-Hook Intrusion Detect Method. 0 = Absolute. 1 = Differential. 3 2 Reserved CIDB Read returns zero. British Telecom Caller ID Decode. 0 = Disable. 1 = Enable. When set, SOC[6:5] is overwritten by the modem, as needed. 1 HDEN HDLC Framing. 0 = Disable. 1 = Enable. 0 Reserved Read returns zero. Function Rev. 1.1 43 S i2401/Si3008 S15 (MLC). Modem Link Control Bit Name Type D7 ATPRE R/W D6 VCTE R/W D5 FHGE R/W D4 EHGE R/W D3 STB R/W D2 D1 D0 NBE R/W BDA[1:0] R/W Reset settings = 0000_0100 (0x04) Bit 7 Name ATPRE Answer Tone Phase Reversal. 0 = Disable. 1 = Enable answer tone phase reversal. 6 VCTE V.25 Calling Tone. 0 = Disable. 1 = Enable V.25 calling tone. 5 FHGE 550 Hz Guardtone. 0 = Disable. 1 = Enable 550 Hz guardtone. 4 EHGE 1800 Hz Guardtone. 0 = Disable. 1 = Enable 1800 Hz guardtone. 3 STB Stop Bits. 0 = 1 stop bit. 1 = 2 stop bits. 2:1 BDA[1:0] Bit Data. 00 = 6 bit data. 01 = 7 bit data. 10 = 8 bit data. 11 = 9 bit data. 0 NBE Ninth Bit Enable. 0 = Disable. 1 = Enable ninth bit as Escape and ninth bit function (register C). Function 44 Rev. 1.1 S i2401/Si3008 S3C (CIDG). Caller ID Gain Bit Name Type Reset settings = 0000_0001 (0x01) Bit 7:3 2:0 Name Reserved CIDG[2:0] Read returns 0. Caller ID Gain. The Si2401 dynamically sets the On-Hook Analog Receive Gain SF4[6:4] (ARG) to CIDG during a caller ID event (or continuously if S0C[6:5] (CIDM = 11). This field should be set prior to caller ID operation. 000 = 0 dB 001 = 3 dB 010 = 6 dB 011 = 9 dB 100 = 12 dB Function D7 D6 D5 D4 D3 D2 D1 CIDG[2:0] R/W D0 Rev. 1.1 45 S i2401/Si3008 S62 (RC). Result Codes Override Bit Name Type D7 D6 OCR R/W D5 D4 D3 D2 IR R/W D1 NLR R/W D0 RR R/W Reset settings = 0100_0001 (0x41) Bit 7 6 Name Reserved OCR Read returns zero. Overcurrent Result Code (“x”). 0 = Enable. 1 = Disable. 5:3 2 Reserved IR Read returns zero. Intrusion Result Code (“I” and “i”). 0 = Disable. 1 = Enable. 1 NLR No Phone Line Result Code (“L” and “l”). 0 = Disable. 1 = Enable. 0 RR Ring Result Code (“R”). 0 = Disable. 1 = Enable. Function 46 Rev. 1.1 S i2401/Si3008 S82 (IST). Intrusion Bit Name Type D7 D6 IST[3:0] R/W D5 D4 D3 LCLD R/W D2 IB[1:0] R/W D1 D0 Reset settings = 0000_1000 (0x08) Bit 7:4 Name IST[3:0] Intrusion Settling Time. 0000 = IST equals 1 second. Delay between when the ISOmodem® chipset goes off-hook and the off-hook intrusion algorithm begins (250 ms units). 3 LCLD Loop Current Loss Detect. 0 = Disable. 1 = Enables the reporting of “I” and “L” result codes while off-hook. Asserts INT if GPIO4 (SE2[7:6]) is enabled as INT. 2:1 IB[1:0] Intrusion Blocking. This feature only works when SDF ≠ 0x00. Defines the method used to block the off-hook intrusion algorithm from operating after dialing has begun. 00 = No intrusion blocking. 01 = Intrusion disabled from start of dial to end of dial. 10 = Intrusion disabled from start of dial to register S29 time out. 11 = Intrusion disabled from start of dial to carrier detect or to “N” or “n” result code. 0 Reserved Read returns zero. Function Rev. 1.1 47 S i2401/Si3008 SDF (DGSR). Intrusion Deglitch Bit Name Type Reset settings = 0000_1100 (0x0C) Bit 7 6:0 Name Reserved DGSR[6:0] Read returns zero. Deglitch Sample Rate. Sets the sample rate for the deglitch algorithm and the off-hook intrusion algorithm (40 ms units). 0000000 = Disables the deglitch algorithm, and sets the off-hook intrusion sample rate to 200 ms and delay between compared samples to 800 ms. Function D7 D6 D5 D4 D3 DGSR[6:0] R/W D2 D1 D0 SE0 (CF1). Chip Functions 1 Bit Name Type Reset settings = 0010_0010 (0x22) Bit 7:6 5 Name Reserved ICTS Read returns zero. Invert CTS pin. 0 = Inverted (CTS). 1 = Normal (CTS). 4 3 2:0 Reserved ND SD[2:0] Read returns zero. 0 = 8N1. 1 = 9N1 (hardware UART only). Serial Dividers. 000 = 300 bps serial link. 001 = 1200 bps serial link. 010 = 2400 bps serial link. 011 = 9600 bps serial link. 100 = 19200 bps serial link. 101 = 38400 bps serial link 110 = 115200 bps serial link. 111 = 307200 bps serial link. Function D7 D6 D5 ICTS R/W D4 D3 ND R/W D2 D1 SD[2:0] R/W D0 48 Rev. 1.1 S i2401/Si3008 SE1 (GPIO1). General Purpose Input/Output 1 Bit Name Type Reset settings = 0000_0000 (0x04) Bit 7:2 1 Name Reserved GPD5 Function Read returns zero. GPIO5 Data. Data = 0. Data = 1. GPIO5. 0 = Digital input. 1 = Digital output (relay drive). D7 D6 D5 D4 D3 D2 D1 GPD5 R/W D0 GPIO5 R/W 0 GPIO5 SE2 (GPIO2). General Purpose Input/Output 2 Bit Name Type D7 R/W D6 D5 R/W D4 D3 R/W D2 D1 R/W D0 GPIO4[1:0] GPIO3[1:0] GPIO2[1:0] GPIO1[1:0] Reset settings = 0000_0000 (0x00) Bit 7:6 Name GPIO4[1:0] GPIO4. 00 = Digital input. 01 = Digital output (relay drive). 10 = AOUT. 11 = INT function defined by S08. GPIO3[1:0] GPIO3. 00 = Digital input. 01 = Digital output (relay drive). 10 = Reserved. 11 = ESC function (digital input). GPIO2[1:0] GPIO2. 00 = Digital input. 01 = Digital output (relay drive; also used for CD function). 10 = Reserved. 11 = Digital input. GPIO1[1:0] GPIO1*. 00 = Digital input. 01 = Digital output (relay drive). 10 = Reserved. 11 = Reserved. *Note: To be used as a GPIO pin; SE4[3] (GPE) must equal zero. Function 5:4 3:2 1:0 Rev. 1.1 49 S i2401/Si3008 SE3 (GPD). GPIO Data Bit Name Type Reset settings = 0000_0000 (0x00) Bit 7:4 3 Name Reserved GPD4 Read returns zero. GPIO4 Data. Data = 0 Data = 1 2 GPD3 GPIO3 Data. Data = 0 Data = 1 1 GPD2 GPIO2 Data. Data = 0 Data = 1 GPIO1 Data. Data = 0 Data = 1 Function D7 D6 D5 D4 D3 GPD4 R/W D2 GPD3 R/W D1 GPD2 R/W D0 GPD1 R/W 0 GPD1 SE4 (CF5). Chip Functions 5 Bit Name Type D7 NBCK R D6 SBCK R D5 DRT R/W D4 D3 GPE R/W D2 D1 D0 Reset settings = 0000_0000 (0x00) Bit 7 6 5 Name NBCK SBCK DRT Function 9600 Baud Clock (Read Only). 600 Baud Clock (Read Only). Data Routing. 0 = Data mode, DSP output transmitted to line, line received by DSP input. 1 = Loopback mode, TXD through microcontroller (DSP) to RXD. Read returns zero. GPIO1 Enable. 0 = Disable. 1 = Enable GPIO1 to be HDLC end-of-frame flag. Read returns zero. 4 3 Reserved GPE 2:0 Reserved 50 Rev. 1.1 S i2401/Si3008 SE5 (DSP1). (SE8 = 0x02) Read Only Definition Bit Name Type D7 DDAV R D6 TDET R D5 D4 D3 D2 TONE[4:0] R D1 D0 Reset settings = 0000_0000 (0x00) Bit 7 6 Name DDAV TDET DSP Data Available. Tone Detected. Indicates a TONE (any of type 0–25 below) has been detected. 0 = Not detected. 1 = Detected. Read returns zero. Tone Type Detected. When TDET goes high, TONE indicates which tone has been detected from the following: TONE Tone Type Priority 00000–01111 DTMF 0–15 (DTMFE = 1)1 See Table 17 on page 26. 1 10000 Answer tone detected 2100 Hz (ANSE = 1)2 2 10001 Bell 103 answer tone detected 2225 Hz (ANSE = 1) 2 10010 V.23 forward channel mark 1300 Hz (V23E = 1)3 3 10011 V.23 backward channel mark 390 Hz (V23E = 1) 3 10100 User defined frequency 1 (USEN1 = 1)4 4 10101 User defined frequency 2 (USEN1 = 1) 4 10110 Call progress filter A detected 6 10111 User defined frequency 3 (USEN2 = 1)5 5 11000 User defined frequency 4 (USEN2 = 1) 5 11001 Call progress filter B detected 6 Notes: 1. SE6[0] (DTMFE) SE8 = 0x02. 2. SE6[1] (ANSE) SE8 = 0x02. 3. SE6[2] (V23E) SE8 = 0x02. 4. SE6[3] (USEN1) SE8 = 0x02. 5. SE6[4] (USEN2) SE8 = 0x02. Function 5 4:0 Reserved TONE[4:0] Rev. 1.1 51 S i2401/Si3008 SE5 (DSP2). (SE8 = 0x02) Write Only Definition Bit Name Type Reset settings = 0000_0000 (0x00) Bit 7 6:3 2:0 Name Reserved DTM[3:0] TONC[2:0] Function Always write this bit to zero. Tone Type Generated. DTMF tone (0–15) to transmit when selected by TONC = 001. See Table 17 on page 26. DTMF Tone Selector. Tone 000 001 010 011 100 101 110 111 Tone Type Mute DTMF 2225 Hz Bell mode answer tone with phase reversal 2100 Hz CCITT mode answer tone with phase reversal 2225 Hz Bell mode answer tone without phase reversal 2100 Hz CCITT mode answer tone without phase reversal User-defined programmable frequency tone (UFRQ) (see Table 18 on page 28, default = 1700 Hz) 1300 Hz V.25 calling tone D7 D6 D5 DTM[3:0] W D4 D3 D2 D1 TONC[2:0] W D0 52 Rev. 1.1 S i2401/Si3008 SE6 (DSP3). (SE8 = 0x02) Write Only Definition Bit Name Type D7 CPSQ W D6 CPCD W D5 D4 USEN2 W D3 USEN1 W D2 V23E W D1 ANSE W D0 DTMFE W Reset settings = 0000_0000 (0x00) Bit 7 Name CPSQ Function Call Progress Squaring Filter. 0 = Disable. 1 = Enables a squaring function on the output of filter B before the input to A (cascade only). Call Progress Cascade Disable. 0 = Call progress filter B output is input into call progress filter A. Output from filter A is used in the detector. 1 = Cascade disabled. Two independent fourth order filters available (A and B). The largest output of the two is used in the detector. Do not modify. User Tone Reporting Enable 2. 0 = Disable. 1 = Enable the reporting of user defined frequency tones 3 and 4 through TONE. User Tone Reporting Enable 1. 0 = Disable. 1 = Enable the reporting of user defined frequency tones 1 and 2. V.23 Tone Reporting Enable. 0 = Disable. 1 = Enable the reporting of V.23 tones, 390 Hz and 1300 Hz. Answering Tone Reporting Enable. 0 = Disable. 1 = Enable the reporting of answer tones. DTMF Tone Reporting Enable. 0 = Disable. 1 = Enable the reporting of DTMF tones. 6 CPCD 5 4 Reserved USEN2 3 USEN1 2 V23E 1 ANSE 0 DTMFE Rev. 1.1 53 S i2401/Si3008 SEB (TPD). Timer and Powerdown Bit Name Type Reset settings = 0000_0000 (0x00) Bit 7:4 3 Name Reserved PDDE Read returns zero. Powerdown DSP Engine. 0 = Power on. 1 = Powerdown. 2:0 Reserved Read returns zero. Function D7 D6 D5 D4 D3 PDDE R/W D2 D1 D0 54 Rev. 1.1 S i2401/Si3008 SEC (RVC1). Ring Validation Control 1 Bit Name Type D7 RNGV R/W D6 D5 RDLY[2:0] R/W D4 D3 D2 RCC[2:0] R/W D1 D0 Reset settings = 1000_1000 (0x88) Bit 7 Name RNGV Ring Validation Enable. 0 = Ring validation feature is disabled. 1 = Ring validation feature is enabled in both normal operating mode and lowpower mode. 6:4 RDLY[2:0] Ring Delay. These bits set the amount of time between when a ring signal is validated and when a valid ring signal is indicated. RDLY[2:0] Delay 000 0 ms 001 256 ms 010 512 ms . . . 111 1792 ms Ring Confirmation Count. These bits set the amount of time that the ring frequency must be within the tolerances set by the RAS[5:0] bits and the RMX[3:0] bits to be classified as a valid ring signal. RCC[2:0] Ring Confirmation Count Time 000 100 ms 001 150 ms 010 200 ms 011 256 ms 100 384 ms 101 512 ms 110 640 ms 111 1024 ms This bit must always be written to zero. Function 3:1 RCC[2:0] 0 Reserved Rev. 1.1 55 S i2401/Si3008 SED (RVC2). Ring Validation Control 2 Bit Name Type Reset settings = 0001_1001 (0x19) Bit 7:6 5:0 Name Reserved RAS[5:0] Read returns zero. Ring Assertion Time. These bits set the minimum ring frequency for a valid ring signal. During ring qualification, a timer is loaded with the RAS[5:0] field upon a TIP/RING event and decrements at a regular rate. If a second or subsequent TIP/RING event occurs after the timer has timed out, the frequency of the ring is too low, and the ring is invalidated. The difference between RAS[5:0] and RMX[5:0] identifies the minimum duration between TIP/RING events to qualify as a ring, in binary-coded increments of 2.0 ms (nominal). A TIP/RING event typically occurs twice per ring tone period. At 20 Hz, TIP/RING events would occur every 1/(2 x 20 Hz) = 25 ms. To calculate the correct RAS[5:0] value for a frequency range [f_min, f_max], the following equation should be used: RAS[5:0] = 1 / (2 x f_min). Function D7 D6 D5 D4 D3 RAS[5:0] R/W D2 D1 D0 56 Rev. 1.1 S i2401/Si3008 SEE (RVC3). Ring Validation Control 3 Bit Name Type Reset settings = 0001_0110 (0x16) Bit 7:4 Name RTO[3:0] Function Ring Timeout. These bits set when a ring signal is determined to be over after the most recent ring threshold crossing. RTO[3:0] Ring Timeout 0000 80 ms 0001 128 ms 0010 256 ms . . . 1111 1920 ms Ring Assertion Maximum Count. These bits set the maximum ring frequency for a valid ring signal. During ring qualification, a timer is loaded with the RAS[5:0] field upon a TIP/RING event and decrements at a regular rate. When a subsequent TIP/RING event occurs, the timer value is compared to the RMX[3:0] field, and if it exceeds the value in RMX[3:0], the frequency of the ring is too high, and the ring is invalidated. The difference between RAS[5:0] and RMX[3:0] identifies the minimum duration between TIP/RING events to qualify as a ring, in binary-coded increments of 2.0 ms (nominal). A TIP/RING event typically occurs twice per ring tone period. At 20 Hz, TIP/RING events would occur every 1/(2 x 20 Hz) = 25 ms. To calculate the correct RMX[3:0] value for a frequency range [f_min, f_max], the following equation should be used: RMX[3:0] x 2 ms = RAS[5:0] – 2 ms – (1/(2 x f_max)). D7 D6 RTO[3:0] D5 D4 D3 D2 RMX[3:0] R/W D1 D0 R/W 3:0 RMX[3:0] Rev. 1.1 57 S i2401/Si3008 SF0 (DAA0). DAA Low Level Functions 0 Bit Name Type D7 FOH[1:0] R/W R/W D6 D5 D4 D3 D2 D1 LM[1:0] R/W D0 Reset settings = 0100_0000 (0x40) Bit 7:6 Name FOH[1:0] Function Fast Off-Hook Selection. These bits determine the length of the off-hook counter. The default setting is 128 ms. 00 = 512 ms 01 = 128 ms 10 = 64 ms 11 = 8 ms Read returns zero. Line Mode. These bits determine the line status of the Si2401.* 00 = On-hook 01 = Off-hook 10 = On-hook line monitor mode 11 = Reserved 5:2 1:0 Reserved LM[1:0] *Note: Under normal operation, the Si2401 internal microcontroller automatically sets these bits appropriately. 58 Rev. 1.1 S i2401/Si3008 SF1 (DAA1). DAA Low Level Functions 1 Bit Name Type D7 D6 PDN R/W D5 PDL R/W D4 LVFD R/W D3 D2 HBE R/W D1 D0 Reset settings = 0000_1100 (0x0C) Bit 7 6 Name Reserved PDN Read returns zero. Powerdown. 0 = Normal operation. 1 = Powers down the Si2401. 5 PDL Powerdown Line-Side Chip (typically only used for board level debug.) 0 = Normal operation. Program the clock generator before clearing this bit. 1 = Places the line-side device in lower power mode. 4 LVFD Line Voltage Force Disable. 0 = Normal operation. 1 = The circuitry that forces the LVS register to all 0s at 3 V or less is disabled. This register may display unpredictable values at voltages between 0 to 2 V. All 0s are displayed if the line voltage is 0 V. Do not modify. Hybrid Transmit Path Connect. 0 = Disable. 1 = Enable. 1:0 Reserved Do not modify. Function 3 2 Reserved HBE Rev. 1.1 59 S i2401/Si3008 SF2 (DAA2). DAA Low Level Functions 2 Bit Name Type Reset settings = 0000_0000 (0x00) Bit 7:4 3 Name Reserved FDT Read only. Frame Detect (Typically only used for board-level debug). 1 = Indicates isolation capacitor frame lock has been established. 0 = Indicates isolation capacitor frame lock has not been established. 2:0 Reserved Reserved Function D7 D6 D5 D4 D3 FDT R D2 D1 D0 SF4 (DAA4). DAA Low Level Functions 4 Bit Name Type Reset settings = 0000_1111 (0x0F) Bit 7:4 3:2 Name Reserved ARL[1:0] Read returns zero. AOUT Receive—Path Level. DAA receive path signal AOUT gain. 00 = 0 dB 01 = –6 dB 10 = –12 dB 11 = Mute 1:0 ATL[1:0] AOUT Transmit—Path Level. DAA transmit path signal AOUT gain. 00 = –18 dB 01 = –24 dB 10 = –30 dB 11 = Mute Function D7 D6 D5 D4 D3 ARL[1:0] R/W D2 D1 ATL[1:0] R/W D0 60 Rev. 1.1 S i2401/Si3008 SF5 (DAA5). DAA Low Level Functions 5 Bit Name Type Reset settings = 0000_0000 (0x00) Bit 7:1 0 Name Reserved RT Read returns zero. Ringer Threshold Select. Used to satisfy country requirements on ring detection. Signals below the lower level do not generate a ring detection; Signals above the upper level are guaranteed to generated a ring detection. 0 = 13.5 to 16.5 VRMS 1 = 19.35 to 23.65 VRMS Function D7 D6 D5 D4 D3 D2 D1 D0 RT R/W SF8 (DAA8). DAA Low Level Functions 8 Bit Name Type D7 D6 LRV[3:0] R D5 D4 D3 D2 D1 D0 Reset settings vary with line-side revision Bit 7:4 3:0 Name LRV[3:0] Reserved Function Line-Side Device Revision Number. 1001 = Si3008 Rev B Do not modify. Rev. 1.1 61 S i2401/Si3008 SF9 (DAA9). DAA Low Level Functions 9 Read Only Bit Name Type Reset settings = 0010_0000 (0x20) Bit 7:3 2 1 Name Reserved OVL ROV Do not modify. Receive overload. Same as ROV, except not sticky. Receive Overload (sticky). 0 = No excessive level detected. 1 = Excessive input level detected. 0 Reserved Do not modify. Function D7 D6 D5 D4 D3 D2 OVL R D1 ROV R/W D0 SFC (DAAFC). DAA Low Level Functions Bit Name Type D7 CTSM R/W D6 D5 D4 D3 D2 D1 D0 Reset settings = 0000_0000 (0x00) Bit 7 Name CTSM Clear-to-Send (CTS) Mode. 0 = CTS pin is negated as soon as a start bit is detected and reasserted when the transmit FIFO is empty. 1 = CTS pin is negated when the FIFO is > 70% full and reasserted when the FIFO is < 30% full. 6:0 Reserved Read returns zero. Function 62 Rev. 1.1 S i2401/Si3008 8. Pin Descriptions: Si2401 CLKIN/XTALI XTALO GPIO5/RI VD RXD TXD CTS RESET 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 GPIO1/EOFR GPIO2/CD GPIO3/ESC VA GND GPIO4/INT/AOUT C1A C2A Pin # 1 Pin Name CLKIN/XTALI Description XTALI—Crystal Oscillator Pin. These pins provide support for parallel resonant AT cut crystals. XTALI also acts as an input in the event that an external clock source is used in place of a crystal. A 4.9152 MHz crystal is required or a 4.9152 or 27 MHz clock on XTALI. XTALO—Crystal Oscillator Pin. Serves as the output of the crystal amplifier. General Purpose Input/RI. This pin can be either a GPIO pin (digital in, digital out) or the RI pin. Default is digital in. When programmed as RI, it indicates the presence of an ON segment of a ring signal on the telephone line. Supply Voltage. Provides the 3.3 V supply voltage to the Si2401. Receive Data. Serial communication data from the Si2401. Transmit Data. Serial communication data to the Si2401. Clear to Send. Clear to send output used by the Si2401 to signal that the device is ready to receive more digital data on the TXD pin. Reset Input. An active low input that is used to reset all control registers to a defined, initialized state. Also used to bring the Si2401 out of sleep mode. Isolation Capacitor 2A. Connects to one side of the isolation capacitor C2. Isolation Capacitor 1A. Connects to one side of the isolation capacitor C1. 2 3 XTALO GPI05/RI 4 5 6 7 VD RXD TXD CTS 8 RESET 9 10 C2A C1A Rev. 1.1 63 S i2401/Si3008 Pin # 11 Pin Name GPIO4/INT/ AOUT Description General Purpose Input/INT. This pin can be either a GPIO pin (digital in, digital out) or the INT pin. Default is digital in. When programmed as INT, this pin provides five functions. While the modem is connected, it asserts if the carrier is lost, a wake-on ring (using the “ATZ” command) event is detected, a loss of loop current event is detected, V.23 reversal is detected, or if an intrusion event has been detected. The INT pin is sticky and stays asserted until the host clears it by writing to the correct S register. (See register SE2[7:6].) Ground. Connects to the system digital ground. Regulator Voltage Reference. This pin connects to an external capacitor and serves as the reference for the internal voltage regulator. General Purpose Input/Escape. This pin can be either a GPIO pin (digital in, digital out) or the ESC pin. Default is digital in. When programmed as ESC, a positive edge on this pin causes the modem to go from online (connected) mode to the offline (command) mode. General Purpose Input/CD. This pin can be either a GPIO pin (digital in, digital out) or the CD pin. Default is digital in. When programmed as CD, it is the active low carrier detect pin. General Purpose Input/EOFR. This pin can be either a GPIO pin (digital in, digital out) or the EOFR pin. Default is digital in. This pin can also be programmed to function as the EOFR (end-of-frame receive) signal for HDLC framing. 12 13 GND VA 14 GPIO3/ESC 15 GPIO2/CD 16 GPIO1/EOFR 64 Rev. 1.1 S i2401/Si3008 9. Pin Descriptions: Si3008 Si3008 C1B C2B VREG CID 1 2 3 4 8 7 IGND 6 5 9 RX DCT QB QE Pin # 1 2 3 4 5 6 7 8 9 Pin Name C1B C2B VREG CID QE QB DCT RX IGND Description Isolation Capacitor 1B. Connects to one side of isolation capacitor C1 and communicates with the Si2401. Isolation Capacitor 2B. Connects to one side of isolation capacitor C2 and communicates with the Si2401. Voltage regulator. Connects to an external capacitor to provide bypassing for an internal power supply. Caller ID. Caller ID input. Transistor Emitter. Connects to the emitter of Q3. Transistor Base. Connects to the base of transistor Q3. Used to go on- and off-hook. DC Termination. Provides dc termination to the telephone network. Receive Input. Serves as the receive side input from the telephone network. Isolated Ground (exposed pad). Connects to ground on the line-side interface. Rev. 1.1 65 S i2401/Si3008 10. Ordering Guide Chipset Si2401 Description Commercial lead-free Power Supply 3.3 V Digital Si2401-FS Line Si3008-B-FS Temperature 0 to 70 °C 66 Rev. 1.1 S i2401/Si3008 11. Package Outline: 16-Pin SOIC Figure 6 illustrates the package details for the Si3054 and Si3018. Table 23 lists the values for the dimensions shown in the illustration. 16 9 h E -BH bbb B θ L Detail F 1 B 8 aaa C A B -A- D -Ce A1 A C See Detail F Seating Plane γ Figure 6. 16-pin Small Outline Integrated Circuit (SOIC) Package Table 23. Package Diagram Dimensions Symbol A A1 B C D E e H h L γ θ aaa bbb Millimeters Min Max 1.35 1.75 .10 .25 .33 .51 .19 .25 9.80 10.00 3.80 4.00 1.27 BSC 5.80 6.20 .25 .50 .40 1.27 0.10 0º 8º 0.25 0.25 Rev. 1.1 67 S i2401/Si3008 12. Package Outline: 8-Pin Exposed Pad SOIC Figure 7 illustrates the package details for the Si3008. Table 24 lists the values for the dimensions shown in the illustration. α Figure 7. 8-pin Exposed Pad Small Outline Integrated Circuit (SOIC) Package 68 Rev. 1.1 S i2401/Si3008 Table 24. Package Diagram Dimensions Dimension A A1 A2 B C D D1 E E1 e H h L ∝ 5.80 0.25 0.40 0° Millimeters Min 1.35 0.00 1.40 REF 0.33 0.19 4.80 2.14 3.80 2.14 1.27 BSC 6.20 0.50 1.27 8° Max 1.75 0.15 1.55 REF 0.51 0.25 5.00 2.44 4.00 2.44 Notes: 1. All dimensions shown are in millimeters (mm). 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Recommended card reflow profile is per the JEDEC/IPC J-STD020C specification for Small Body Components. Rev. 1.1 69 S i2401/Si3008 DOCUMENT CHANGE LIST Revision 0.5 to Revision 1.0 Updated Table 2, “Loop Characteristics,” on page 4. Updated Table 4, “AC Characteristics,” on page 6. Updated Table 7, “Country-Specific PTT Specifications,” on page 11. Updated "12. Package Outline: 8-Pin Exposed Pad SOIC" on page 68. Revision 1.0 to Revision 1.1 Updated Table 7, “Country-Specific PTT Specifications,” on page 11. Removed Brazil listing. 70 Rev. 1.1 S i2401/Si3008 NOTES: Rev. 1.1 71 S i2401/Si3008 CONTACT INFORMATION Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: ISOinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. 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Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders 72 Rev. 1.1