Si 2401
V.22 B I S ISO MODEM ®
WITH
I NTEGRATED G LOBAL D AA
Features
Data modem formats
Integrated third-generation DAA
2400 bps: V.22bis
Fewer external components required
1200 bps: V.22, V.23, Bell 212A
Over 5000 V capacitive isolation
300 bps: V.21, Bell 103
Parallel phone detect
Fast connect and V.23 reversing
Globally-compliant line interface
SIA and other security protocols
27 MHz CLKIN support
Caller ID detection and decoding
UART with flow control
AT command set support
Call progress support
3.3 V Power
Lead-free, RoHS-compliant
packages
Applications
Set-top boxes
Point-of-sale
ATM terminals
Security systems
Medical monitoring
Power meters
Description
The Si2401 ISOmodem® is a complete, two-chip 2400 bps modem integrating
Skyworks Solutions’ third-generation direct access arrangement (DAA), which
provides a globally-programmable telephone line interface with an unprecedented
level of integration. Available in two 16-pin SOIC packages, this compact solution
eliminates the need for a separate DSP data pump, modem controller, codec,
isolation transformer, relay, opto-isolators, and 2–4 wire hybrid. The Si2401
provides conventional data formats at connect rates of up to 2400 bps with fullduplex operation over the Public Switched Telephone Network (PSTN).
Additionally, the Si2401 is fully-programmable to meet global standards with a
single design. Other features include fast connect times for electronic point-ofsale (EPOS) applications and alarm protocols for security systems. The device is
ideal for embedded modem applications due to its small size, low external
component count, and low power consumption.
Functional Block Diagram
Si2401
µ Controller
(AT Decoder,
Call Progress)
RESET
EOFR/GPIO1
CD/GPIO2
ESC/GPIO3
INT/GPIO4
Control
Interface
RI/GPIO5
XTALI
XOUT
DSP
(Data Pump)
Isolation Interface
CTS
See page 72.
Pin Assignments
Si2401
CLKIN/XTALI
1
16
GPIO1/EOFR
XTALO
2
3
15
14
GPIO2/CD
GPIO3/ESC
4
5
13
VA
GND
GPIO5/RI
VD
RXD
TXD
CTS
RESET
6
7
8
12
11
GPIO4/INT/AOUT
10
C1A
9
C2A
Si3010
QE
1
16
DCT2
DCT
2
3
15
14
IGND
DCT3
4
5
13
12
QB
QE2
6
11
SC
7
10
8
9
RX
IB
C1B
C2B
VREG
RNG1
VREG2
RNG2
RX
UART
RXD
TXD
Si3010
Ordering Information
Hybrid, AC
and DC
Terminations
Isolation
Interface
Ring Detect
Clock
Interface
Off-Hook
IB
SC
DCT
VREG
VREG2
DCT2
DCT3
U.S. Patent #5,870,046
U.S. Patent #6,061,009
Other patents pending
RNG1
RNG2
QB
QE
QE2
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Si 2401
2
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Si2401
TABLE
Section
OF
C ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3. Bill of Materials: Si2401/10 Chipset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2. Configurations and Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3. Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.4. Global DAA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.5. Parallel Phone Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.6. Interrupt Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.7. V.23 Operation/V.23 Reversing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.8. V.42 HDLC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.9. Fast Connect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.10. Clock Generation Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5. AT Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1. Command Line Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2. End-Of-Line Character . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.3. AT Command Set Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.4. Alarm Industry AT Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.5. Modem Result Codes and Call Progress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6. Low Level DSP Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.1. DSP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.2. Call Progress Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7. S Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
8. Pin Descriptions: Si2401 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
9. Pin Descriptions: Si3010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
10. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
11. Package Outline: 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
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Si 2401
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter1
Ambient Temperature
Si2401 Supply Voltage, Digital3
Symbol
Test Condition
TA
VD
F-Grade
Min2
0
3.0
Typ
25
3.3
Max2
70
3.6
Unit
°C
V
Notes:
1. The Si2401 specifications are guaranteed when the typical application circuit (including component tolerance) and Si2401
and Si3010 are used. See "2. Typical Application Schematic" on page 10.
2. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical
values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
3. The digital supply, VD, operates from 3.0 to 3.6 V. The Si2401 interface supports 5 V logic (CLKIN/XTALI supports 3.3 V
logic only).
4
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Si2401
Table 2. Loop Characteristics
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C for F-Grade, see Figure 1 on page 6)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
DC Termination Voltage
VTR
IL = 20 mA, ILIM = 0
DCV = 00, MINI = 11, DCR = 0
—
—
6.0
V
DC Termination Voltage
VTR
IL = 120 mA, ILIM = 0
DCV = 00, MINI = 11, DCR = 0
9
—
—
V
DC Termination Voltage
VTR
IL = 20 mA, ILIM = 0
DCV = 11, MINI = 00, DCR = 0
—
—
7.5
V
DC Termination Voltage
VTR
IL = 120 mA, ILIM = 0
DCV = 11, MINI = 00, DCR = 0
9
—
—
V
DC Termination Voltage
VTR
IL = 20 mA, ILIM = 1
DCV = 11, MINI = 00, DCR = 0
—
—
7.5
V
DC Termination Voltage
VTR
IL = 60 mA, ILIM = 1
DCV = 11, MINI = 00, DCR = 0
40
—
—
V
DC Termination Voltage
VTR
IL = 50 mA, ILIM = 1
DCV = 11, MINI = 00, DCR = 0
—
—
40
V
On-Hook Leakage Current
ILK
VTR = –48 V
—
—
5
µA
MINI = 00, ILIM = 0
10
—
120
mA
ILP
MINI = 00, ILIM = 1
dc current flowing through ring
detection circuitry
10
—
—
1.5
60
3
mA
µA
VRD
RT = 0
12
15
18
RT = 1
18
21
25
VRMS
15
—
—
—
68
0.2
Operating Loop Current
Operating Loop Current
DC Ring Current
Ring Detect Voltage*
*
Ring Detect Voltage
Ring Frequency
Ringer Equivalence Number
ILP
VRD
FR
REN
VRMS
Hz
*Note: The ring signal is guaranteed to not be detected below the minimum. The ring signal is guaranteed to be detected
above the maximum.
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Si 2401
Table 3. DC Characteristics*
(VD = 3.0 to 3.6 V, TA = 0 to 70°C for F-Grade)
Parameter
Symbol
High Level Input Voltage
Test Condition
VIH
Low Level Input Voltage
VIL
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Power Supply Current, DSP Powerdown
Power Supply Current, Total Powerdown
2.0
—
—
V
—
—
0.8
V
—
—
V
—
—
0.35
V
VOL
IO = 10 mA
—
—
0.6
V
IO = 1 mA
–10
—
10
µA
50
100
200
k
ID
VD pin
—
10
15
mA
—
8
12
mA
ID
VD pin
VD pin
—
7
10
mA
VD pin
—
100
—
µA
ID
Power Supply Current, Wake-On-Ring
Unit
2.4
RPU
Power Supply Current, Digital
Max
IO = –2 mA
IL
Pullup Resistance Pins 5, 7, 11, 14
Typ
VOH
VOL
Low Level Output Voltage, GPIO1–4
Min
ID
*Note: Measurements are taken with inputs at rails and no loads on outputs.
TIP
+
600
Si3010
V TR
IL
10 µF
RING
–
Figure 1. Test Circuit for Loop Characteristics
6
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Si2401
Table 4. AC Characteristics
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C for F-Grade, Fs = 8 kHz)
Parameter
Symbol
Sample Rate
Test Condition
Fs
Min
Typ
Max
Unit
—
8
—
kHz
Clock Input Frequency
FXTL
default
—
4.9152
—
MHz
Clock Input Frequency
FXTL
—
27
—
MHz
Receive Frequency Response
350 and IF > 225 mA, e.g., part
number HD04-T in a MiniDIP package by Diodes, Inc., two MMBD3004S-7-F diode pairs by Diodes, Inc. in an SOT-23
package, or four 1N4004 diodes.
3. Murata BLM21AG601SN1 may be substituted for R15–R16 (0 ) to decrease emissions.
4. To ensure compliance with ITU specifications, frequency tolerance must be less than 100 ppm including initial
accuracy, 5-year aging, 0 to 70 °C, and capacitive loading. 50 ppm initial accuracy crystals typically satisfy this
requirement.
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Si 2401
4. Functional Description
The Si2401 is a complete modem chipset with
integrated direct access arrangement (DAA) that
provides a programmable line interface to meet global
telephone line requirements. Available in two 16-pin
small-outline packages, this solution includes a DSP
data pump, modem controller, codec, and DAA.
The modem accepts simple modem AT commands and
provides connect rates up to 2400 bps full-duplex over
the Public Switched Telephone Network (PSTN) with
V.42 hardware support through HDLC framing. To
minimize handshake times, the Si2401 can implement a
V.22-based fast connect. The modem also supports the
V.23 reversing protocol and standard alarm formats
including SIA.
This device is ideal for embedded modem applications
due to its small board space, low power consumption,
and global compliance. The Si2401 solution integrates a
silicon DAA using Skyworks Solutions’ proprietary thirdgeneration DAA technology. This highly-integrated DAA
can be programmed using the Si3010 to meet
worldwide PTT specifications for ac termination, dc
termination, ringer impedance, and ringer threshold.
The DAA can also monitor line status for parallel
handset detection and overcurrent conditions.
The Si2401 is designed for rapid assimilation into
existing modem applications. The device interfaces
directly through a UART to a microcontroller. The
Si2401URT-EVB evaluation board connects directly to a
standard RS-232 interface. This allows for evaluation of
the modem immediately upon powerup via
HyperTerminal or any standard terminal software.
The chipset can be fully programmed to meet
international telephone line interface requirements with
full compliance to FCC, TBR21, JATE, and other
country-specific PTT specifications. In addition, the
Si2401 has been designed to meet the most stringent
worldwide requirements for out-of-band energy, billingtone immunity, high-voltage surges, and safety
requirements.
Table 7. Selectable Configurations
Configuration
V.21
V.22*
V.22bis*
V.23
V.23
Bell 103
Bell 212A
Security
SIA—Pulse
SIA Format
Modulation
Carrier
Frequency (Hz)
Data Rate
(bps)
Standard
Compliance
FSK
1080/1750
300
Full
DPSK
1200/2400
1200
Full
QAM
FSK
1200/2400
1300/2100
1300/1700
1170/2125
1200/2400
—
—
1170/2125
2400
1200/75
600/75
300
1200
40
Low
300 half-duplex
No retrain
Full; plus reversing
(Europe)
FSK
DPSK
DTMF
Pulse
FSK
Full
Full
Full
Full
300 bps only
*Note: The Si2401 only adjusts its DCE rate from 2400 bps to 1200 bps if it is connecting to a V.22-only (1200 bps only)
modem. Because the V.22bis specification does not outline a fallback procedure, the host should implement a
fallback mechanism consisting of hanging up and connecting at a lower baud rate. Retraining to accommodate
changes in line conditions that occur during a call must be implemented by terminating the call and redialing.
12
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Si2401
4.1. Serial Interface
The
Si2401 has a universal asynchronous
receiver/transmitter (UART) serial interface compatible
with standard microcontroller serial interfaces. After
powerup or reset, the speed of the serial (Data Terminal
Equipment—DTE) interface is set by default to
2400 bps with the 8-bit, no parity, and one-stop bit (8N1)
format described below.
The serial interface DTE rate can be modified by writing
SE0[2:0] (SD) with the value corresponding to the
desired DTE rate. (See Table 8.) This is accomplished
with the command, ATSE0=xx, where xx is the
hexadecimal value of the SE0 register.
Table 8. DTE Rates
DTE Rate (bps)
300
1200
2400
9600
19200
38400
115200
307200
SE0[2:0] (SD)
000
001
010
011
100
101
110
111
Immediately after the ATSE0=xx string is sent, the host
UART must be reprogrammed to the new DTE rate in
order to communicate with the Si2401.
The carriage return character following the ATSE0=xx
string must be sent at the new DTE rate to observe the
“O” response code. See Table 12 on page 24 for the
response code summary.
4.2. Configurations and Data Rates
The Si2401 can be configured to any of the Bell and
CCITT operation modes listed in Table 9. When
configured for V.22bis, the modem connects at
1200 bps if the far end modem is configured for V.22.
This device also supports SIA and other protocols for
the security industry. Table 7 provides the modulation
method, carrier frequencies, data rate, baud rate, and
notes on standard compliance for each modem
configuration of the Si2401. Table 9 shows example
register settings (S07) for some of the modem
configurations.
Table 9. Modem Configuration Examples
(S07[7] (HDEN) = 0, S07[6] (BD) = 0)
Modem Protocol
V.22bis
V.22
V.21
Bell 212A
Bell 103
V.23 (1200 tx, 75 rx)
V.23 (75 tx, 1200 rx)
V.23 (600 tx, 75 rx)
V.23 (75 tx, 600 rx)
Register S07 Values
0x06
0x02
0x03
0x00
0x01
0x16
0x26
0x10
0x20
As shown in Figure 3, 8-bit and 9-bit data modes refer to
the DTE format over the UART. Line data formats are
configured through registers S07 (MF1) and S15 (MLC).
If the number of bits specified by the format differs from
the number of bits specified by the DCE data
communications equipment or line (DTE) format, the
MSBs are either dropped or bit-stuffed, as appropriate.
For example, if the DTE format is 9 data bits (9N1), and
the line data format is 8 data bits (8N1), the MSB from
the DTE is dropped as the 9-bit word is passed from the
DTE side to the DCE (line) side. In this case, the
dropped ninth bit can then be used as an escape
mechanism. However, if the DTE format is 8N1, and the
line data format is 9N1, an MSB equal to 0 is added to
the 8-bit word as it is passed from the DTE side to the
DCE side.
The Si2401 UART does not continuously check for stop
bits on the incoming digital data. Therefore, if the TXD
pin is not high, the RXD pin may echo meaningless
characters to the host UART. This requires the host
UART to flush its receiver FIFO upon initialization.
TXD
Si2401
Si3010
RJ11
RXD
DTE Interface
DCE (Line) Interface
Data Rate: SE0[2:0] (SD)
Data Format: SE0[3] (ND)
Data Rate: S07 (MF1)
Data Format: S15 (MLC)
Figure 3. Link and Line Data Formats
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Si 2401
4.2.1. Command/Data Mode
Upon reset, the modem is in command mode and
accepts AT-style commands. An outgoing modem call
can be made using the “ATDT#” (tone dial) or “ATDP#”
(pulse dial) command after the device is configured. If
the handshake is successful, the modem responds with
the “c”, “d”, or “v” string and enters data mode. (The
byte following the “c”, “d”, or “v” is the first data byte.) At
this point, AT-style commands are not accepted. There
are three methods that may be used to return the
Si2401 to command mode:
Use the ESC pin—To program the GPIO3 pin to
function as an ESCAPE input, set GPIO3
SE2[5:4] = 11. In this setting, a positive edge
detected on this pin returns the modem to command
mode. The “ATO” string can be used to reenter data
mode.
Use 9-bit data mode—If 9-bit data format with
escape is programmed, a 1 detected on bit 9 returns
the modem to command mode. (See Figure 2 on
page 9.) This is enabled by setting SE0[3] (ND) = 1
and S15[0] (NBE) = 1. The ATO string can be used
to reenter data mode. Ninth bit escape does not
work in the security modes.
Use “+++”—The escape sequence is a sequence of
three escape characters that are set in S-register
S0F (“+” characters by default). If the ISOmodem®
chipset detects the “+++” sequence and detects no
activity on the UART before or after the “+++”
sequence for a time period set by S-register S10, it
returns to command mode. To disable this escape
sequence, set S-register S10 = FF. To remove the
time-dependent behavior, set S-register S10 = 00.
Whether using an escape method or not, when the
carrier is lost, the modem automatically returns to
command mode and reports “N”.
4.2.2. 8-Bit Data Mode (8N1)
The 8-bit data mode is the default mode after powerup
or reset and is set by SE0[3] (ND) = 0b. It is
asynchronous, full duplex, and uses a total of 10 bits
including a start bit (logic 0), eight data bits, and a stop
bit (logic 1). Data received from the remote modem is
transferred from the Si2401 to the host on the RXD pin.
Data transfer to the host begins when the Si2401
asserts a logic 0 start bit on RXD. Data is shifted out of
the Si2401 LSB first at the DTE rate determined by the
SE0[2:0] (SD) setting and terminates with a stop bit.
Data from the host for transmission to the remote
modem is shifted to the Si2401 on TXD beginning with a
start bit, LSB, first at the DTE rate determined by the
SE0[2:0] setting, and terminates with a stop bit.
After the middle of the stop bit time, the Si2401 begins
looking for a logic 1 to logic 0 transition signaling the
start of the next character on TXD to be sent to the line
(remote modem).
4.2.3. 9-Bit Data Mode (9N1)
The 9-bit data mode is set by SE0[3] (ND) = 1. It is
asynchronous, full duplex, and uses a total of 11 bits
including a start bit (logic 0), 9 data bits, and a stop bit
(logic 1). Data received from the line (remote modem) is
transferred from the Si2401 to the host on the RXD pin.
Data transfer to the host begins when the Si2401
asserts a logic 0 start bit on RXD. Data is shifted out of
the Si2401 LSB first at the DTE rate determined by the
SE0[2:0] (SD) setting and terminates with a stop bit.
Data from the host for transmission to the line (remote
modem) is shifted to the Si2401 on TXD beginning with
a start bit, LSB, first at the DTE rate determined by the
S-Register SE0[2:0] (SD) setting, and terminates with a
stop bit. After the middle of the stop bit time, the Si2401
begins looking for a logic 1 to logic 0 transition signaling
the start of the next character on TXD to be sent to the
line (remote modem).
The ninth data bit may be used to indicate an escape by
setting S15[0] (NBE) = 1. In this mode, the ninth data bit
is normally set to 0 when the modem is online. When
the ninth data bit is set to 1, the modem goes offline into
command mode, and the next frame is interpreted as an
AT command. Data mode can be reentered using the
ATO command.
4.2.4. Flow Control
No flow control is needed if the DTE rate and DCE rate
are the same. If the serial link (DTE) data rate is set
higher than the line (DCE) rate of the modem, flow
control is required to prevent loss of data to the
transmitter.
To control data flow, the clear-to-send (CTS) pin is used.
When CTS is asserted, the Si2401 is ready to accept a
character. While CTS is negated, no data should be
sent to the Si2401 on TXD. To simplify flow control, the
Si2401 has an integrated ten character transmit FIFO
and allows for two different CTS reporting methods. By
default, the CTS pin is negated as soon as a start bit is
detected on the TXD pin and remains negated until the
modem is ready to accept another character (see
Figure 2 on page 9.) By setting SFC7[7] = 1 (CTSM),
CTS is negated when the FIFO is 70% full and is
reasserted when the FIFO is 30% full.
14
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Si2401
4.3. Low Power Modes
The Si2401 has three low-power modes:
DSP Powerdown. The DSP processor can be
powered down by setting register
SEB[3] (PDDE) = 1.
In this mode, the serial interface still functions, and
the modem detects ringing and intrusion. However,
no modem modes or tone detection features
function.
Wake-Up-On-Ring. By issuing the ATz command,
the Si2401 goes into a low-power mode where both
the microcontroller and DSP are powered down.
Only an incoming ring, a low TXD signal, or a total
reset will power up the chip again. Return from
wake-on-ring triggers the INT pin if S09[6]
(WOR) = 1 (WOR = 0b by default).
Total Powerdown. Setting SF1[5] = 1 and SF1[6] = 1
places the Si2401 into a total powerdown mode. All
logic is powered down including the crystal oscillator
and clock-out pin. Only a hardware reset can restart
the Si2401.
4.4. Global DAA Operation
The Si2401 chipset contains an integrated silicon direct
access arrangement (silicon DAA) that provides a
programmable line interface to meet international
telephone line requirements. Table 10 gives the DAA
register settings required to meet various country PTT
standards.
Table 10. Country-Specific Register Settings
Si2401 Register
SF5
SF6
Country
OHS
ILIM
RZ
RT
MINI[1:0] DCV[1:0] ACT[3:0]
AT Command
String
Algeria
10
1
0
0
00
10
0011
ATSF5=28SF6=23
Argentina
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Armenia
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Australia
01
0
0
0
10
01
0011
ATSF5=10SF6=93
Austria (EU)
10
1
0
0
00
10
0011
ATSF5=28SF6=23
Bahamas
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Bahrain
10
1
0
0
00
10
0011
ATSF5=28SF6=23
Belarus
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Belgium (EU)
10
1
0
0
00
10
0011
ATSF5=28SF6=23
Bermuda
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Brazil
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Brunei
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Bulgaria
10
1
0
0
00
10
0011
ATSF5=28SF6=23
Canada
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Caribbean
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Chile
00
0
0
0
00
10
0000
ATSF5=00SF6=20
China - People's Republic
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Colombia
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Costa Rica
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Croatia
10
1
0
0
00
10
0011
ATSF5=28SF6=23
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Si 2401
Table 10. Country-Specific Register Settings
Si2401 Register
SF5
SF6
Country
OHS
ILIM
RZ
RT
MINI[1:0] DCV[1:0] ACT[3:0]
AT Command
String
Cyprus (EU)
10
1
0
0
00
10
0011
ATSF5=28SF6=23
Czech Republic (EU)
10
1
0
0
00
10
0011
ATSF5=28SF6=23
Denmark (EU)
10
1
0
0
00
10
0011
ATSF5=28SF6=23
Dominican Republic
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Dubai
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Equador
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Egypt
10
1
0
0
00
10
0011
ATSF5=28SF6=23
El Salvador
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Estonia (EU)
10
1
0
0
00
10
0011
ATSF5=28SF6=23
Finland (EU)
10
1
0
0
00
10
0011
ATSF5=28SF6=23
France (EU)
10
1
0
0
00
10
0011
ATSF5=28SF6=23
Georgia
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Germany (EU)
10
1
0
0
00
10
0011
ATSF5=28SF6=23
Ghana
10
1
0
0
00
10
0011
ATSF5=28SF6=23
Greece (EU)
10
1
0
0
00
10
0011
ATSF5=28SF6=23
Guadeloupe
10
1
0
0
00
10
0011
ATSF5=28SF6=23
Guam
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Hong Kong
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Hungary (EU)
10
1
0
0
00
10
0011
ATSF5=28SF6=23
Iceland (CTR-21)
10
1
0
0
00
10
0011
ATSF5=28SF6=23
India
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Indonesia
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Ireland (EU)
10
1
0
0
00
10
0011
ATSF5=28SF6=23
Israel
10
0
0
0
01
01
0011
ATSF5=20SF6=53
Italy (EU)
10
1
0
0
00
10
0011
ATSF5=28SF6=23
Japan
00
0
0
0
10
01
0000
ATSF5=00SF6=90
Jordan
00
0
0
0
10
01
0000
ATSF5=00SF6=90
Kazakhstan
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Korea
00
0
1
0
00
10
0000
ATSF5=04SF6=20
Kuwait
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Kyrgyzstan
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Latvia (EU)
10
1
0
0
00
10
0011
ATSF5=28SF6=23
Lebanon
10
1
0
0
00
10
0011
ATSF5=28SF6=23
Lesotho
00
0
1
0
00
10
0011
ATSF5=04SF6=23
16
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Si2401
Table 10. Country-Specific Register Settings
Si2401 Register
SF5
SF6
Country
OHS
ILIM
RZ
RT
MINI[1:0] DCV[1:0] ACT[3:0]
AT Command
String
Liechtenstein (CTR-21)
10
1
0
0
00
10
0011
ATSF5=28SF6=23
Lithuania (EU)
10
1
0
0
00
10
0011
ATSF5=28SF6=23
Luxembourg (EU)
10
1
0
0
00
10
0011
ATSF5=28SF6=23
Macao
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Malaysia
00
0
0
0
10
01
0000
ATSF5=00SF6=90
Malta (EU)
10
1
0
0
00
10
0011
ATSF5=28SF6=23
Martinique
10
1
0
0
00
10
0011
ATSF5=28SF6=23
Mexico
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Moldova
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Morocco
10
1
0
0
00
10
0011
ATSF5=28SF6=23
Netherlands (EU)
10
1
0
0
00
10
0011
ATSF5=28SF6=23
New Zealand
00
0
0
0
00
10
0100
ATSF5=00SF6=24
Nigeria
10
1
0
0
00
10
0011
ATSF5=28SF6=23
Norway (CTR-21)
10
1
0
0
00
10
0011
ATSF5=28SF6=23
Oman
00
0
0
0
10
01
0000
ATSF5=00SF6=90
Pakistan
00
0
0
0
10
01
0000
ATSF5=00SF6=90
Paraguay
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Peru
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Philippines
00
0
0
0
10
01
0000
ATSF5=00SF6=90
Poland (EU)
10
1
0
0
00
10
0011
ATSF5=28SF6=23
Polynesia (French)
10
1
0
0
00
10
0011
ATSF5=28SF6=23
Portugal (EU)
10
1
0
0
00
10
0011
ATSF5=28SF6=23
Puerto Rico
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Qatar
00
0
0
0
10
01
0000
ATSF5=00SF6=90
Reunion
10
1
0
0
00
10
0011
ATSF5=28SF6=23
Romania
10
1
0
0
00
10
0011
ATSF5=28SF6=23
Russia
00
0
0
0
00
01
0000
ATSF5=00SF6=10
Saudi Arabia
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Singapore
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Slovakia (EU)
10
1
0
0
00
10
0011
ATSF5=28SF6=23
Slovenia (EU)
10
1
0
0
00
10
0011
ATSF5=28SF6=23
South Africa
00
0
1
0
00
10
0011
ATSF5=04SF6=23
Spain (EU)
10
1
0
0
00
10
0011
ATSF5=28SF6=23
Sri Lanka
00
0
0
0
00
10
0000
ATSF5=00SF6=20
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Si 2401
Table 10. Country-Specific Register Settings
Si2401 Register
SF5
SF6
Country
OHS
ILIM
RZ
RT
MINI[1:0] DCV[1:0] ACT[3:0]
AT Command
String
Sweden (EU)
10
1
0
0
00
10
0011
ATSF5=28SF6=23
Switzerland (CTR-21)
10
1
0
0
00
10
0011
ATSF5=28SF6=23
Taiwan
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Thailand
00
0
0
0
00
01
0000
ATSF5=00SF6=10
Tunisia
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Turkey
10
1
0
0
00
10
0011
ATSF5=28SF6=23
UAE
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Ukraine
00
0
0
0
00
10
0000
ATSF5=00SF6=20
United Kingdom (EU)
10
1
0
0
00
10
0011
ATSF5=28SF6=23
Uruguay
00
0
0
0
00
10
0000
ATSF5=00SF6=20
USA
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Uzbekistan
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Venezuela
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Yemen
00
0
0
0
00
10
0000
ATSF5=00SF6=20
Zambia
10
1
0
0
00
10
0011
ATSF5=28SF6=23
18
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Si2401
4.5. Parallel Phone Detection
The ISOmodem® chipset is able to detect when another
telephone, modem, or other device is using the phone
line. This allows the host to avoid interrupting another
phone call when the phone line is already in use and to
intelligently handle an interruption when the ISOmodem
chipset is using the phone line.
4.5.1. On-Hook Intrusion Detection
When the ISOmodem chipset is sharing the telephone
line with other devices, it is important that it not interrupt
a call in progress. To detect when another device is
using the shared telephone line, the host can use the
ISOmodem chipset to monitor the TIP-RING dc voltage
with the LVS[7:0] bits (SDB). The LVS[7:0] bits have a
resolution of 1 V per bit with an accuracy of
approximately ±10%. Bits 0 through 6 of this 8-bit
signed 2s complement number indicate the value of the
line voltage, and the sign bit (bit 7) indicates the polarity
of TIP and RING.
When all devices on a particular telephone line are onhook, there is no loop current flowing through TIP and
RING. Therefore, the voltage across TIP and RING is at
a maximum. (On most telephone lines, this on-hook
voltage is a minimum of 40 V.) Once a device goes offhook, current flows through TIP and RING on that
device, and the TIP-RING voltage drops appreciably.
(On most telephone lines, this off-hook voltage is a
maximum of 20 V.)
If the host checks the TIP-RING voltage via LVS before
causing the ISOmodem chipset to dial out or go offhook, the host can determine if another device is using
the telephone line. One way to do this is to verify that
the voltage represented in LVS is above some fixed
threshold, such as 30 V.
4.5.2. Off-Hook Intrusion Detection
After it has been determined that it is safe to use the
phone line without interrupting a call, the host can
instruct the ISOmodem chipset to begin a call or go offhook. However, once the call has begun and the
ISOmodem chipset is in data mode, the serial port is
used for modem data making it difficult for the host to
monitor registers. Therefore, when the ISOmodem
chipset is off-hook, an algorithm is implemented to
automatically monitor the TIP-RING loop current via the
LCS register (SF3). Because the TIP-RING voltage
drops significantly when off-hook, TIP-RING current is a
better indicator of another device using the phone line.
The LCS[7:0] bits have a resolution of 1.1 mA per bit.
An LCS register value of 0x00 indicates less than the
required loop current is present, and a value of 0xFF
indicates excessive current draw (>120 mA if ILIM = 0
or >60 mA if ILIM = 1). The user can read these bits
directly through the LCS register. Upon detecting an
intrusion, an "i" result code is sent to the host if it is in
the call negotiation stage or command mode.
Otherwise, the modem can be programmed to generate
an interrupt to notify the host of the intrusion.
The off-hook intrusion algorithm monitors the value of
LCS (SF3) at a sample rate determined by the DGSR
(SDF, bits 6:0) register (40 ms units). The algorithm
compares each LCS sample to the reference value in
the ACL register (S12). If LCS is lower than ACL by an
amount greater than DCL (S11, bits 4:0), the algorithm
waits for another LCS sample, and if the next LCS
sample is also lower than ACL by an amount greater
than DCL, an interrupt occurs. This helps the
ISOmodem chipset avoid a false parallel phone
detection (PPD) interrupt due to glitches on the phone
line. The ACL is continually updated with the value of
LCS as outlined below. The algorithm can be outlined
as follows:
If LCS(t) = LCS(t – 40 ms x DGSR)
and
LCS(t) – ACL > DCL
then ACL = LCS(t)
If (ACL – LCS[t – 40 ms x DGSR]) > DCL)
and
(ACL – LCS[t]) > DCL)
Then, an intrusion is sent to the host.
The very first sample of LCS the algorithm uses after
going off-hook does not have any previous samples for
comparison. If LCS was measured during a previous
call, this value of LCS may be used as an initial
reference. ACL may be written by the host with this
known value of LCS. If ACL is non-zero, the ISOmodem
chipset uses ACL as the first valid LCS sample in the
off-hook intrusion algorithm. If ACL is 0 (default after
reset), the ISOmodem chipset ignores the register and
does not begin operating the algorithm until two LCS
samples have been received. Additionally, immediately
after a modem call, ACL is updated automatically with
the last valid LCS value before a parallel phone
detection (PPD) intrusion or going back on-hook.
The off-hook intrusion algorithm does not begin to
operate immediately after going off-hook. This is to
avoid triggering an interrupt due to transients resulting
from the ISOmodem chipset itself going from on-hook to
off-hook. The time that elapses between the ISOmodem
chipset going off-hook and the intrusion algorithm
starting defaults to one second and may be adjusted via
the IST register (S82, bits 7:4). If ACL is written to a
non-zero value before going off-hook, a parallel phone
intrusion that occurs during this IST interval and
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Si 2401
sustains through the end of the interval triggers an
interrupt.
The off-hook intrusion algorithm may additionally be
disabled for a period of time after dialing begins via the
IB register (S82, bits 2:1). This avoids triggering an
interrupt due to pulse dialing, open-switch intervals, or
line transients from central office switching. Intrusion
may be disabled from the start of dialing to the end of
dialing (IB = 01b), from the start of dialing to the timeout
of the IS (S29, bits 7:0) by setting IB = 10b(IB = 2), or
from the start of dialing to carrier detect by setting
IB = 11b. The off-hook intrusion algorithm is only
suspended (not disabled) during this IB interval.
Therefore, any intrusion that occurs during the IB
interval and sustains through the end of the interval
triggers a PPD interrupt.
4.6. Interrupt Detection
The INT interrupt pin can be programmed to alert the
host of loss of carrier, loss of phone line voltage/current,
parallel phone detection, and other interrupts listed in
the interrupt status mask (S08). After the host receives
an interrupt via the INT pin, the host should issue the
AT:I command. This command causes a read-clear of
the WOR, PPD, NLD, RI, OCD, and REV bits of the S09
register and raises (deactivates) the INT pin. All the
interrupt status bits in register S09 remain high after
being set until cleared by the AT:I command.
4.6.1. Loop Current Detection
In addition to monitoring parallel phone intrusion, it is
possible to monitor the loss of loop current. This feature
can be enabled by setting S08[4] (NLDM) = 1. This
feature is disabled by default. If the loop current is too
low for normal DAA operation, S09[4] (NLD) is set.
During this event, if the NLR result code is enabled by
setting S62[1](NLR) = 1, the “l” result code is sent. Once
the loop current returns to a normal current state, the “L”
result code is sent. The INT pin is also asserted if
enabled.
4.6.2. Loss-of-Carrier Detection
The Si2401 has two methods of implementing a loss-ofcarrier function. If GPIO4 is programmed as INT, and if
S08[7](CDM) = 1, INT asserts in data mode when a
loss-of-carrier is detected. The carrier detect function
may also be implemented on GPIO2 by setting SE2[3:2]
(GPIO2) = 01 and SOC[7](CDE) = 1.
4.6.3. Overcurrent Detection
The Si2401 has an integrated overcurrent detection
feature. The Si2401 begins monitoring for an
overcurrent condition at a programmable time set by
S32 (OCDT) after going off-hook (default = 20 ms). If an
overcurrent condition is detected, the Si2401 sets
S09[1] interrupt status. As long as GPIO4 is
programmed as INT and the overcurrent mask bit is
enabled by setting S08[1](OCDM) = 1, INT asserts
during an overcurrent situation. The host may then
check S09[1] (OCD) via the AT:I command to confirm
that an overcurrent condition occurred.
4.6.4. Caller ID Decoding Operation
The Si2401 supports full caller ID detection and decode
for US Bellcore and UK standards. To use the caller ID
decoding feature, the following configuration is
necessary:
1. Set SE0[3] (ND) = 0b (set modem to 8N1
configuration).
2. Set S0C[6:5] (CIDM) = 01 (set modem to Bellcore
type caller ID) or S13[2] (CIDB) = 1 (set modem to
UK type caller ID).
4.6.5. Caller ID Monitor/Bellcore Caller ID
The Si2401 continuously monitors the phone line for the
caller ID mark signals. This can be useful in systems
that require detection of caller ID data before the ring
signal, voice mail indicator signals, and Type II caller ID
monitor support. To force the Si2401 into caller ID
monitor mode, set SOC[6:5] (CIDM) = 11.
Note: CIDM should be disabled before going off-hook.
4.6.6. UK Caller ID Operation
The Si2401 starts searching for the Idle State Tone Alert
Signal. When this signal has been detected, the Si2401
transmits an “a” to the host. After the Idle State Tone
Alert Signal is completed, the Si2401 applies the
wetting pulse for the required 15 ms by quickly going
off-hook and on-hook. From this point on, the algorithm
is identical to that of Bellcore in that it searches for the
channel seizure signal and the marks before echoing an
“m” and then reports the decoded caller ID data.
4.7. V.23 Operation/V.23 Reversing
The Si2401 supports full V.23 operation including the
V.23 reversing procedure. V.23 operation is enabled by
setting S07 (MF1) = xx10x110b or xx01x110b. If
S07[5] (V23R) = 1b, the Si2401 transmits data at 75 bps
and receives data at 600 or 1200 bps. If
S07[4] (V23T) = 1b, the Si2401 receives data at 75 bps
and transmits data at 600 or 1200 bps. S07[2] (BAUD)
is the 1200 or 600 bps indicator. BAUD = 1b enables the
1200/600 V.23 channel to run at 1200 bps, while
BAUD = 0b enables 600 bps operation.
When a V.23 connection is successfully established, the
modem responds with a “c” character if the connection
is made with the modem transmitting at 1200/600 bps
and receiving at 75 bps. The modem responds with a
“v” character if a V.23 connection is established with the
20
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Si2401
modem transmitting at 75 bps and receiving at
1200/600 bps.
The Si2401 supports the V.23 turnaround procedure.
This allows a modem that is transmitting at 75 bps to
initiate a “turnaround” procedure so that it can begin
transmitting data at 1200/600 bps and receiving data at
75 bps. The modem is defined as being in V.23 master
mode if it is transmitting at 75 bps, and it is defined as
being in slave mode if the modem is transmitting at
1200/600 bps. The following paragraphs give a detailed
description of the V.23 turnaround procedure.
4.7.1. Modem in Master Mode
To perform a direct turnaround once a modem
connection is established, the master host goes into
online-command-mode by sending an escape
command (Escape pin activation, TIES, or ninth bit
escape) to the master modem.
Note: The host can initiate a turnaround only if the Si2401 is
the master.
The host then sends the ATRO command to the Si2401
to initiate a V.23 turnaround and return to the online
(data) mode.
The Si2401 then changes its carrier frequency (from
390 Hz to 1300 Hz) and waits to detect a 390 Hz carrier
for 440 ms. If the modem detects more than 40 ms of a
390 Hz carrier in a time window of 440 ms, it echoes the
“c” response character. If the modem does not detect
more than 40 ms of a 390 Hz carrier in a time window of
440 ms, it hangs up and echoes the “N” (no carrier)
character as a response.
4.7.2. Modem in Slave Mode
Configure GPIO4 as INT (SE2[7:6] [GPIO4] = 11b). The
Si2401 performs a reverse turnaround when it detects a
carrier drop longer than 20 ms. The Si2401 then
reverses (changes its carrier from 1300 Hz to 390 Hz)
and waits to detect a 1300 Hz carrier for 400 ms. If the
Si2401 detects more than 40 ms of a 1300 Hz carrier in
a time window of 400 ms, it sets the S09[7] bit, and the
next character echoed by the Si2401 is a “v”.
If the Si2401 does not detect more than 40 ms of the
1300 Hz carrier in a time window of 400 ms, it reverses
again and waits to detect a 390 Hz carrier for 440 ms.
Then, if the Si2401 detects more than 40 ms of a
390 Hz carrier in a time window of 220 ms, it sets the
S09[7] bit, and the next character echoed by the Si2401
is a “c”.
At this point, if the Si2401 does not detect more than
40 ms of the 390 Hz carrier in a time window of 440 ms,
it hangs up, sets the S09[7] bit, and the next character
echoed by the Si2401 is an “N” (no carrier).
Successful completion of a turnaround procedure in
master or slave mode automatically updates
S07[4] (V23T) and S07[5] (V23R) to indicate the new
status of the V.23 connection.
To avoid using the INT pin, the host may also be notified
of the INT condition by using 9-bit data mode. Setting
S15[0] (NBE) = 1b and S0C[3] (9BF) = 0b configures
the ninth bit on the Si2401 TXD path to function exactly
as the INT pin has been described.
4.8. V.42 HDLC Mode
The Si2401 supports V.42 through hardware HDLC
framing in all modem data modes. Frame packing and
unpacking including opening and closing flag generation
and detection, CRC computation and checking, zero
insertion and deletion, and modem data transmission
and reception are all performed by the Si2401. V.42
error correction and V.42bis data compression must be
performed by the host.
The digital link interface in this mode uses the same
UART interface (8-bit data and 9-bit data formats) as in
the asynchronous modes, and the ninth data bit may be
used as an escape by setting S15[0] (NBE) = 1b. When
using HDLC in 9-bit data mode, if the ninth bit is not
used as an escape, it is ignored.
To use the HDLC feature on the Si2401, the host must
enable HDLC operation by setting S13[1] (HDEN) = 1b.
The host may initiate the call or answer the call using
either the “ATDT#”, the “ATA” command or the autoanswer mode. (The auto-answer mode is implemented
by setting register S00 (NR) to a non-zero value.) When
the call is connected, a “c”, “d”, or “v” is echoed to the
host controller. The host may now send/receive data
across the UART using either the 8-bit data or 9-bit data
formats with flow control.
At this point, the Si2401 begins framing data into the
HDLC format. On the transmit side, if no data is
available from the host, the HDLC flag pattern is sent
repeatedly. When data is available, the Si2401
computes the CRC code throughout the frame, and the
data is sent with the HDLC zero-bit insertion algorithm.
HDLC flow control operates in a similar manner to
normal asynchronous flow control across the UART and
is shown in Figure 4. To operate flow control (using the
CTS pin to indicate when the Si2401 is ready to accept
a character), a DTE rate higher than the line rate should
be selected.
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Si 2401
The method of transmitting HDLC frames is as follows:
1. After the call is connected, the host should begin
sending the frame data to the Si2401 using the CTS
flow control to ensure data synchronicity.
2. When the frame is complete, the host should simply
stop sending data to the Si2401. Since the Si2401
does not yet recognize the end-of-frame, it expects
an extra byte and asserts CTS as shown in
Figure 4A. If CTS is used to cause a host interrupt,
this final interrupt should be ignored by the host.
3. When the Si2401 is ready to send the next byte, if it
has not yet received any data from the host, it
recognizes this as an end-of-frame, raises CTS,
calculates the final CRC code, transmits the code,
and begins transmitting stop flags.
4. After transmitting the first stop flag, the Si2401
lowers CTS indicating that it is ready to receive the
next frame from the host. At this point, the process
repeats as in Step 1.
The method of receiving HDLC frames is as follows:
1. After the call is connected, the Si2401 searches for
flag data. Then, once the first non-flag word is
detected, the CRC is continuously computed, and
the data is sent across the UART (8-bit data or 9-bit
data mode) to the host after removing the HDLC
zero-bit insertion. The DTE rate of the host must be
at least as high as that of data transmission. HDLC
mode only works with 8-bit data words; the ninth bit
is used only for escape on TXD and end-of-frame
received (EOFR) on RXD.
2. When the Si2401 detects the stop flag, it sends the
last data word in the frame as well as the two CRC
bytes and determines if the CRC checksum
matches. Thus, the last two bytes are not frame data
but are the CRC bytes, which can be discarded by
the host. If the checksum matches, the Si2401
echoes “G” (good). If the checksum does not match,
the Si2401 echoes “e” (error). Additionally, if the
Si2401 detects an abort (seven or more contiguous
ones), it echoes an “A”.
When the “G”, “e”, or “A” (referred to as a frame
result word) is sent, the Si2401 raises the EOFR
(end of frame receive) pin (see Figure 4B). The
GPIO1 pin must be configured as EOFR by setting
SE4[3] (GPE) = 1b. In addition to using the EOFR
pin to indicate that the byte is a frame result word, if
in 9-bit data mode (set S15[0] (NBE) = 1b), the ninth
bit is raised if the byte is a frame result word. To
program this mode, set S0C[3] (9BF) = 1b and
SE0[3] (ND) = 1.
3. When the next frame of data is detected, EOFR is
lowered, and the process repeats at Step 1b.
To summarize, when receiving HDLC frames, the host
begins receiving data asynchronously from the Si2401.
When each byte is received, the host should check the
EOFR pin (or the ninth bit). If the EOFR pin (or the ninth
bit) is low, the data is valid frame data. If the EOFR pin
(or the ninth bit) is high, the data is a frame result word.
Host finished sending frame N
Host begins frame N
TXD
Start
Frame N
Si2400 ready for byte 1 of frame N
Host begins frame N + 1
Stop
Start
Frame N + 1
Si2401 detects end of frame N.
(CTS used as normal flow control.)
Si2401 ready for byte 1
of frame N + 1.
CTS
Note: Figure not to scale.
A. Frame Transmit
RXD
EOFR
(or bit 9)
Start
Receive Data
Stop
Start
CRC Byte 1
Stop
Start
CRC Byte 2
Stop
Start
Frame Result Word
Stop
B. Frame Receive
Figure 4. HDLC Timing
22
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Si2401
4.9. Fast Connect
4.10. Clock Generation Subsystem
In modem applications that require fast connection
times, it is possible to reduce the length of the
handshake.
Additional modem handshaking control can be adjusted
through the registers shown in Table 11. These registers
are most useful if the user has control of both the
originating and answering modems.
When the fast connect settings are used, there may be
unintended data received initially. The host must
tolerate these bytes.
The Si2401 contains an on-chip clock generator. Using
a single master clock input, the Si2401 can generate all
modem sample rates necessary to support V.22bis,
V.22/Bell212A, and V.21/Bell103 standards and a
9.6 kHz rate for audio playback. Either a 27 MHz or
4.9152 MHz clock on XTALI or a 4.9152 MHz crystal
across XTALI and XTALO form the master clock for the
Si2401. This clock source is sent to an internal phaselocked loop (PLL) that generates all necessary internal
system clocks. The PLL has a settling time of ~1 ms.
Data on RXD should not be sent to the device prior to
settling of the PLL. By default, the Si2401 assumes a
4.9152 MHz clock input. If a 27 MHz clock on XTALI is
used, a pulldown resistor B? TDET
CPSQ
Filter A
Energy
Detect
20log10 (4096/CPDL) –43 dBm
Figure 5. Programmable Call Progress Filter Architecture
34
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Si2401
7. S Registers
Any register not documented here is reserved and should not be written. Bold selection in bit-mapped registers
indicates default values.
Table 21. S-Register Summary
“S”
Register
Register
Address
(hex)
Name
Function
Reset
S00
0x00
NR
Number of rings before answer; 0 suppresses auto answer.
0x00
S01
0x01
DW
Number of seconds modem waits before dialing after going offhook (maximum of 109 seconds).
0x02
S02
0x02
CW
Number of seconds modem waits for a dial tone before hang-up
added to time specified by DW (maximum of 109 seconds).
0x03
S03
0x03
CLW
Duration that the modem waits (53.33 ms units) after loss of carrier before hanging up.
0x0E
S04
0x04
TD
Both duration and spacing (5/3 ms units) of DTMF dialed tones.
0x30
S05
0x05
OFFPD
Duration of off-hook time (5/3 ms units) for pulse dialing.
0x18
S06
0x06
ONPD
Duration of on-hook time (5/3 ms units) for pulse dialing.
0x24
S07
S08
S09
S0C
0x07
0x08
0x09
0x0C
MF1
INTM
INTS
MF2
This is a bit-mapped
register.*
0x06
This is a bit-mapped
register.*
0x00
This is a bit-mapped
register.*
0x00
This is a bit-mapped
register.*
0x00
register.*
0x00
S0D
0x0D
MF3
This is a bit-mapped
S0E
0x0E
DIT
Pulse dialing Interdigit time (10 ms units added to a minimum
time of 64 ms).
0x46
S0F
0x0F
TEC
TIES escape character. Default = +.
0x2B
S10
0x10
TDT
TIES delay time (53.33 ms units).
0x13
register.*
S11
0x11
OFHI
This is a bit-mapped
S12
0x12
ACL
Absolute Current Level. When S13[4] (OFHD) = 0b, ACL
represents the absolute current threshold used by the off-hook
intrusion algorithm (1 mA units.)
0x00
S13
0x13
MF4
This is a bit-mapped register.*
0x10
register.*
0x04
This is a bit-mapped
0x04
S15
0x15
MLC
S16
0x16
BTON
Busy tone on. Time that the busy tone must be on (10 ms units)
for busy tone detector.
0x32
S17
0x17
BTOF
Busy tone off. Time that the busy tone must be off (10 ms units)
for busy tone detector.
0x32
S18
0x18
BTOD
Busy tone delta time (10 ms units). A busy tone is detected to be
valid if (BTON – BTOD < on time < BTON + BTOD) and (BTOF –
BTOD < off time < BTOF + BTOD).
0x0F
S19
0x19
RTON
Ringback tone on. Time that the ringback tone must be on
(53.333 ms units) for ringback tone detector.
0x26
*Note: These registers are explained in detail in the following section.
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Si 2401
Table 21. S-Register Summary (Continued)
“S”
Register
Register
Address
(hex)
Name
Function
Reset
S1A
0x1A
RTOF
Ringback tone off. Time that the ringback tone must be off
(53.333 ms units) for ringback tone detector.
0x4B
S1B
0x1B
RTOD
Detector time delta (53.333 ms units). A ringback tone is determined to be valid if (RTON – RTOD < on time < RTON + RTOD)
and (RTOF – RTOD < off time < RTOF + RTOD).
0x07
S1C
0x1C
DTT
Dial tone detect time. The time that the dial tone must be valid
before being detected
(10 ms units).
0x0A
S1E
0x1E
TATL
Transmit answer tone length. Answer tone length in seconds
when answering a call (1 s units).
0x03
S1F
0x1F
ARM3
Answer tone to transmit delay. Delay between answer tone end
and transmit data start (5/3 ms units).
0x2D
S20
0x20
UNL
Unscrambled ones length. Minimum length of time required for
detection of unscrambled binary ones during V.22 handshaking
by a calling modem (5/3 ms units).
0x5D
S21
0x21
TSOD
Transmit scrambled ones delay. Time between unscrambled
binary one detection and scrambled binary one transmission by
a call mode V.22 modem (53.3 ms units).
0x09
S22
0x22
TSOL
Transmit scrambled ones length. Length of time scrambled ones
are sent by a call mode V.22 modem (5/3 ms units).
0xA2
S23
0x23
VDDL
V.22X data delay low. Delay between handshake complete and
data connection for a V.22X call mode modem (5/3 ms units
added to the time specified by VDDH).
0xCB
S24
0x24
VDDH
V.22X data delay high. Delay between handshake complete and
data connection for a V.22X call mode modem (256 x 5/3 ms
units added to the time specified by VDDL).
0x08
S25
0x25
SPTL
S1 pattern time length. Amount of time the unscrambled S1 pattern is sent by a call mode V.22bis modem (5/3 ms units).
0x3C
S26
0x26
VTSO
V.22bis 1200 bps scrambled ones length. Minimum length of
time for transmission of 1200 bps scrambled binary ones by a
call mode V.22bis modem after the end of pattern S1 detection
(53.3 ms).
0x0C
S27
0x27
VTSOL
V.22bis 2400 bps scrambled ones length low. Minimum length of
time for transmission of 2400 bps scrambled binary ones by a
call mode V.22bis modem (5/3 ms units).
0x78
S28
0x28
VTSOH
V.22bis 2400 bps scrambled ones length high. Minimum length
of time for transmission of 2400 bps scrambled binary ones by a
call mode V.22bis modem (256 x 5/3 ms units added to the time
specified by VTSOL).
0x08
S29
0x29
IS
Intrusion suspend. When S82[2:1] (IB) = 10b, this register sets
the length of time from when dialing begins that the off-hook
intrusion algorithm is blocked (suspended) (500 ms units).
0x00
*Note: These registers are explained in detail in the following section.
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Si2401
Table 21. S-Register Summary (Continued)
“S”
Register
Register
Address
(hex)
Name
Function
Reset
S2A
0x2A
RSO
Receive scrambled ones V.22bis (2400 bps) length.
Minimum length of time required for detection of scrambled
binary ones during V.22bis handshaking by the answering
modem after S1 pattern conclusion (5/3 ms units).
0xD2
S2B
0x2B
DTL
V.23 direct turnaround carrier length. Minimum length of time that
a master mode V.23 modem must detect carrier when searching
for a direct turnaround sequence (5/3 ms units).
0x18
S2C
0x2C
DTTO
V.23 direct turnaround timeout. Length of time that the modem
searches for a direct turnaround carrier (5/3 ms units added to a
minimum time of 426.66 ms).
0x08
S2D
0x2D
SDL
V.23 slave carrier detect loss. Minimum length of time that a
slave mode V.23 modem must lose carrier before searching
for a reverse turnaround sequence (5/3 ms units).
0x0C
S2E
0x2E
RTCT
V.23 reverse turnaround carrier timeout. Amount of time a slave
mode V.23 modem searches for carriers during potential reverse
turnaround sequences (5/3 ms units).
0xF0
S2F
0x2F
FCD
FSK connection delay low. Amount of time delay added
between end of answer tone handshake and actual modem
connection for FSK modem connections (5/3 ms units).
0x3C
S30
0x30
FCDH
FSK connection delay high. Amount of time delay added
between end of answer tone handshake and actual modem connection for FSK modem connections (256 x 5/3 ms units).
0x00
S31
0x31
RATL
Receive answer tone length. Minimum length of time required
for detection of a CCITT answer tone (5/3 ms units).
0x3C
S32
0x32
OCDT
The time after going off-hook when the loop current sense bits
are checked for overcurrent status (5/3 ms units).
0x0C
S34
0x34
TASL
Answer tone length when answering a call (5/3 ms units). This
register is only used if TATL (1E) has a value of zero.
0x5A
S35
0x35
RSOL
Receive scrambled ones V.22 length (5/3 ms units). Minimum
length of time that an originating V.22 (1200 bps) modem must
detect 1200 bps scrambled ones during a V.22 handshake.
0xA2
S36
0x36
ARM1
Second kissoff tone detector length. The security modes, A1 and
!1, echo a “k” if a kissoff tone longer than the value stored in
SKDTL is detected (10 ms units).
0x30
S37
0x37
CDR
Carrier detect return. Minimum length of time that a carrier must
return and be detected in order to be recognized after a carrier
loss is detected
(5/3 ms units).
0x20
S39
0x39
CDT
Carrier detect timeout. Amount of time modem waits for carrier
detect before aborting call (1 second units).
0x3C
S3A
0x3A
ATD
Delay between going off-hook and answer tone generation when
in answer mode (53.33 ms units).
0x29
*Note: These registers are explained in detail in the following section.
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Si 2401
Table 21. S-Register Summary (Continued)
“S”
Register
Register
Address
(hex)
Name
Function
S3C
0x3C
CIDG
This is a bit-mapped register.*
0x01
This is a bit-mapped
register.*
0x41
register.*
0x08
S62
0x62
RC
Reset
S82
0x82
IST
This is a bit-mapped
SDB
0xDB
LVS
Line Voltage Status. Eight bit signed, 2s complement number
representing the tip-ring voltage. Each bit represents 1 volt.
Polarity of the voltage is represented by the MSB (sign bit).
0000_0000 = Measured voltage is < 3 V.
SDF
0xDF
DGSR
SE0
SE1
SE2
0xE0
0xE1
0xE2
CF1
GPIO1
GPIO2
This is a bit-mapped register.*
0x0C
This is a bit-mapped
register.*
0x22
This is a bit-mapped
register.*
0x0E
This is a bit-mapped
register.*
0x00
register.*
SE3
0xE3
GPD
This is a bit-mapped
SE4
0xE4
CF5
This is a bit-mapped register.*
SE5
0xE5
DADL
SE5
0xE5
DDL
SE5
0xE5
DSP1
(SE8 = 0x02) Read only definition. This is a bit-mapped register.1
SE5
0xE5
DSP2
(SE8 = 0x02) Write only definition. This is a bit-mapped register.1
SE6
0xE6
DADH
(SE8 = 0x00) Write only definition. DSP register address upper
bits [15:8].
SE6
0xE6
DDH
(SE8 = 0x01) Write only definition. DSP data word upper bits
[13:8]
SE6
0xE6
DSP3
(SE8 = 0x02) Write only definition. This is a bit-mapped register.1
SE8
0xE8
DSPR4
SEB
0xEB
TPD
This is a bit-mapped register.*
0x00
RV1
This is a bit-mapped
register.*
0x88
This is a bit-mapped
register.*
0x19
This is a bit-mapped
register.*
0x16
This is a bit-mapped
register.*
0x40
This is a bit-mapped
register.*
0x0C
register.*
SEC
SED
SEE
SF0
SF1
0xEC
0xED
0xEE
0xF0
0xF1
RV2
RV3
DAA0
DAA1
0x00
(SE8 = 0x00) Write only definition. DSP register address lower
bits [7:0].*
(SE8 = 0x01) Write only definition. DSP data word lower bits
[7:0].*
Set the mode to define E5 and E6 for low-level DSP control.
SF2
0xF2
DAA2
This is a bit-mapped
SF3
0xF3
DAA3
Line Current Status. Eight-bit value returning the loop current.
Each bit represents 1.1 mA of loop current.
Accuracy is not guaranteed if the loop current is less than
required for normal operation.
0x00
SF4
0xF4
DAA4
This is a bit-mapped register.*
0x0F
*Note: These registers are explained in detail in the following section.
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Si2401
Table 21. S-Register Summary (Continued)
“S”
Register
Register
Address
(hex)
Name
Function
SF5
0xF5
DAA5
This is a bit-mapped register.*
0x00
DAA6
This is a bit-mapped
register.*
0xF0
This is a bit-mapped
register.*
0x00
This is a bit-mapped
register.*
—
This is a bit-mapped
register.*
0x20
SF6
SF7
SF8
SF9
0xF6
0xF7
0xF8
0xF9
DAA7
DAA8
DAA9
Reset
*Note: These registers are explained in detail in the following section.
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Si 2401
Table 22. Bit-Mapped Register Summary
“S”
Register Register
Register Address Name
(hex)
Bit 7
Bit 6
Bit 5
Bit 4
BD
V23R
V23T
WORM PPDM
NVDM
NVD
S07
0x07
MF1
S08
0x08
INTM
CDM
S09
0x09
INTS
CD
S0C
0x0C
MF2
CDE
S0D
0x0D
MF3
S11
0x11
OFHI
S13
0x13
MF4
S15
0x15
MLC
S3C
0x3C
CIDG
S62
0x62
RC
S82
0x82
IST
SDF
0xDF
DGSR
SE0
0xE0
CF1
SE1
0xE1
GPIO1
SE2
0xE2
GPIO2
SE3
0xE3
GPD
SE4
0xE4
CF5
NBCK
SBCK
SE5
0xE5
DSP1
DDAV
TDET
SE5
0xE5
DSP2
SE6
0xE6
DSP3
SEB
0xEB
TPD
SEC
0xEC
RVC1
SED
0xED
RVC2
SEE
0xEE
RVC3
SF0
0xF0
DAA0
SF1
0xF1
DAA1
SF2
0xF2
DAA2
SF4
0xF4
DAA4
WOR
PPD
CIDM[1:0]
RI
INTP
RBTS
Bit 3
Bit 2
Bit 1
Bit 0
Default
Binary
BAUD
CCITT
FSK
0000_0110
RIM
CIDM
OCDM
REVM
0000_0000
RI
CID
OCD
REV
0000_0000
9BF
BDL
MLB
EHR
EHB
EHI
0000_0000
EHE
DCL[3:0]
BTID
ATPRE
VCTE
OFHD
FHGE
EHGE
CIDB
STB
0000_0100
HDEN
0001_0000
BDA[1:0]
NBE
CIDG[2:0]
OCR
IR
IST[3:0]
LCLD
NLR
RR
IB[1:0]
0000_1100
ND
GPIO3[1:0]
SD[2:0]
GPIO2[1:0]
GPD4
DRT
0010_0010
GPIO5 0000_1110
GPIO1[1:0]
GPD3
GPD2
GPD1
GPE
TONE[4:0]
CPCD
TONC[2:0]
USEN2 USEN1
RDLY[2:0]
V23E
ANSE
0000_0000
RCC[2:0]
RTO[3:0]
1000_1000
0001_1001
RMX[3:0]
FOH[1:0]
PDN
0001_0110
LM[1:0]
PDL
LVFD
N/A
DTMFE 0000_0000
RAS[5:0]
BTE
N/A
N/A
PDDE
RNGV
0000_0000
xx00_0000
DTM[3:0]
CPSQ
0100_0001
0000_1000
GPD5
GPIO4[1:0]
0000_0100
0000_0001
DGSR[6:0]
ICTS
0000_0000
HBE
0000_1100
FDT
ARL[1:0]
0100_0000
xxxx_1xxx
ATL[1:0]
0000_1111
40
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Si2401
Table 22. Bit-Mapped Register Summary (Continued)
“S”
Register Register
Register Address Name
(hex)
SF5
0xF5
DAA5
SF6
0xF6
DAA6
SF8
0xF8
DAA8
SF9
0xF9
DAA9
SFC
0xFC
DAAFC
Bit 7
Bit 6
Bit 5
Bit 4
OHS[1:0]
MINI[1:0]
Bit 3
Bit 2
ILIM
RZ
DCV[1:0]
ACT[3:0]
LRV[3:0]
BTD
CTSM
Bit 1
OVL
Bit 0
Default
Binary
RT
0000_0000
1111_0000
DCR
N/A
ROV
0010_0000
N/A
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Si 2401
S07 (MF1). Modem Functions 1
Bit
D7
D6
D5
D4
Name
BD
V23R
Type
R/W
R/W
D3
D2
D1
D0
V23T
BAUD
CCITT
FSK
R/W
R/W
R/W
R/W
Reset settings = 0000_0110 (0x06)
Bit
Name
7
Reserved
6
BD
5
V23R
4
V23T
3
Reserved
2
BAUD
1
CCITT
0
FSK
Function
Read returns zero.
Blind Dialing.
0 = Disable.
1 = Enable (Blind dialing occurs immediately after “ATDT#” command).
V.23 Receive.*
V.23 75 bps send/600 (BAUD = 0) or 1200 (BAUD = 1) bps receive.
0 = Disable.
1 = Enable.
V.23 Transmit.*
V.23 600 (BAUD = 0) or 1200 (BAUD = 1) bps send/75 bps receive.
0 = Disable.
1 = Enable.
Read returns zero.
2400/1200 Baud Select.*
2400/1200 baud select (V23R = 0 and V23T = 0).
0 = 1200
1 = 2400
600/1200 baud select (V23R = 1 and V23T = 1).
0 = 600
1 = 1200
CCITT/Bell Mode.*
0 = Bell.
1 = CCITT.
300 bps FSK.*
0 = Disable.
1 = Enable.
*Note: See Table 9 on page 13 for proper setting of modem protocols.
42
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Si2401
S08 (INTM). Interrupt Mask
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
CDM
WORM
PPDM
NVDM
RIM
CIDM
OCDM
REVM
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset settings = 0000_0000 (0x00)
Bit
Name
7
CDM
6
WORM
5
PPDM
4
NVDM
3
RIM
2
CIDM
1
OCDM
0
REVM
Function
Carrier Detect Mask.
0 = Change in CD does not affect INT.
1 = A high to low transition in CD (S09, bit 7), which indicates loss of carrier, activates
INT.
Wake-on-Ring Mask.
0 = Change in CD does not affect INT.
1 = A low to high transition in WOR (S09, bit 6) activatesINT.
Parallel Phone Detect Mask.
0 = Change in PPD does not affect INT.
1 = A low to high transition in PPD (S09, bit 5) activates INT.
No Phone Line Detect Mask.
0 = Change in NLD does not affect INT.
1 = A low to high transition in NLD (S09, bit 4) activates INT.
Ring Indicator Mask.
0 = Change in RI does not affect INT.
1 = A low to high transition in RI (S09, bit 3) activates INT.
Caller ID Mask.
0 = Change in CID does not affect INT.
1 = A low to high transition in CID (S09, bit 2) activates INT.
Overcurrent Detect Mask.
0 = Change in OCD does not affect INT.
1 = A low to high transition in OCD (S09, bit 1) activates INT.
V.23 Reversal Detect Mask.
0 = Change in REV does not affect INT.
1 = A low to high transition in REV (S09, bit 0) activates INT.
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Si 2401
S09 (INTS). Interrupt Status
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
CD
WOR
PPD
NVD
RI
CID
OCD
REV
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset settings = 0000_0000 (0x00)
Bit
Name
Function
7
CD
6
WOR
5
PPD
4
NVD
3
RI
2
CID
1
OCD
0
REV
Carrier Detect (sticky).
Active high bit indicates carrier detected (equivalent to inverse of CD pin). Clears on :1
read.
Wake-on-Ring (sticky).
Wake-on-ring has occurred. Clears on :I read.
Parallel Phone Detect (sticky).
Parallel phone detected since last off-hook event. Clears on :I read.
No Phone Line Detect (sticky).
No line phone detected. Clears on :I read.
Ring Indicator (sticky).
Active high bit when the Si2403 is on-hook, indicates ring event has occurred. Clears on
:I read.
Caller ID (sticky).
Caller ID preamble has been detected; data soon follows. Clears on :I read.
Overcurrent Detect (sticky).
Overcurrent condition has occurred. Clears on :I read.
V.23 Reversal Detect (sticky).
V.23 reversal condition has occurred. Clears on :I read.
44
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Si2401
S0C (MF2). Modem Functions 2
Bit
D7
Name
CDE
Type
R/W
D6
D5
D4
D3
D2
D1
CIDM[1:0]
9BF
BDL
MLB
R/W
R/W
R/W
R/W
D0
Reset settings = 0000_0000 (0x00)
Bit
Name
Function
7
CDE
6:5
CIDM[1:0]
4
3
Reserved
9BF
2
BDL
1
MLB
0
Reserved
Carrier Detect Enable.
0 = Disable.
1 = Enable GPI02 as an active low carrier detect pin (must also set SE2[3:2]
[GPIO2] = 01).
Caller ID Monitor.
00 = Caller ID monitor disabled.
01 = Caller ID monitor enabled. Si2401 must detect channel seizure signal followed by
marks in order to report caller ID data. (Normal Bellcore caller ID)
10 = Reserved.
11 = Caller ID monitor enabled. Si2401 must only detect marks in order to report caller ID
data.
Read returns zero.
Ninth Bit Function.
Only valid if the ninth bit escape is set S15[0] (NBE).
0 = Ninth bit equivalent to ALERT.
1 = Ninth bit equivalent to HDLC EOFR.
Blind Dialing.
0 = Blind dialing disabled.
1 = Enables blind dialing after dial timeout register S02 (CW) expires.
Modem Loopback.
0 = Not swapped.
1 = Swaps frequency bands in modem algorithm to do a loopback in a test mode.
Read returns zero.
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Si 2401
S0D (MF3). Modem Functions 3
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
RI
INTP
RBTS
EHR
EHB
EHI
EHE
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset settings = 0000_0000 (0x00)
Bit
7
6
Name
Reserved
RI
5
INTP
INT Polarity.
Specifies the polarity of the INT function on pin 11.
0 = An interrupt forces pin 11 low.
1 = An interrupt forces pin 11 high.
4
RBTS
Ringback Tone Selector
Controls the unit step size for registers S19, S1A and S1B.
0 = 53.33 ms units. Necessary for detecting a ringback tone.
1 = 10 ms units. Necessary for detecting a reorder tone.
3
EHR
Enable Hangup on Reorder.
Modem is placed on-hook if a ringback or reorder tone is detected. See S0D[4].
0 = Disable.
1 = Enable.
2
EHB
Enable Hangup on Busy.
Modem is placed on-hook if a busy signal is detected.
0 = Disable.
1 = Enable.
1
EHI
Enable Hangup on Intrusion.
Modem is placed on-hook if parallel intrusion is detected.
0 = Disable.
1 = Enable.
0
EHE
Enable Hangup on Escape.
Modem is placed on-hook if a ESC signal is detected.
0 = Disable.
1 = Enable.
Read returns zero.
Function
Ring Indicator.
Specifies the functionality of pin3.
0 = Pin 3 functions as GPIO5 controlled by register SE1.
1 = Pin 3 functions as RI. RI asserts during a ring and negates when no
ring is present.
46
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Si2401
S11 (OFHI). Off-Hook Intrusion
Bit
D7
D6
D5
D4
D3
D2
D1
Name
DCL[3:0]
Type
R/W
D0
Reset settings = 0000_0100 (0x04)
Bit
Name
Function
7:4
Reserved
Read returns zero.
3:0
DCL[3:0]
Differential Current Level.
Differential current level to detect intrusion event (1 mA units).
S13 (MF4). Modem Functions 4
Bit
D7
D6
Name
BTID
Type
R/W
D5
D4
D2
D1
OFHD
CIDB
HDEN
R/W
R/W
R/W
R/W
D3
D0
Reset settings = 0001_0000 (0x10)
Bit
Name
7
Reserved
6
BTID
5
Reserved
4
OFHD
3
Reserved
2
CIDB
1
HDEN
0
Reserved
Function
Read returns zero.
BT Caller ID Wetting Pulse.
0 = Enable.
1 = Disable.
Read returns zero.
Off-Hook Intrusion Detect Method.
0 = Absolute.
1 = Differential.
Read returns zero.
British Telecom Caller ID Decode.
0 = Disable.
1 = Enable.
When set, SOC[6:5] is overwritten by the modem, as needed.
HDLC Framing.
0 = Disable.
1 = Enable.
Read returns zero.
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Si 2401
S15 (MLC). Modem Link Control
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
ATPRE
VCTE
FHGE
EHGE
STB
BDA[1:0]
NBE
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset settings = 0000_0100 (0x04)
Bit
Name
7
ATPRE
6
VCTE
5
FHGE
4
EHGE
3
STB
2:1
BDA[1:0]
0
NBE
Function
Answer Tone Phase Reversal.
0 = Disable.
1 = Enable answer tone phase reversal.
V.25 Calling Tone.
0 = Disable.
1 = Enable V.25 calling tone.
550 Hz Guardtone.
0 = Disable.
1 = Enable 550 Hz guardtone.
1800 Hz Guardtone.
0 = Disable.
1 = Enable 1800 Hz guardtone.
Stop Bits.
0 = 1 stop bit.
1 = 2 stop bits.
Bit Data.
00 = 6 bit data.
01 = 7 bit data.
10 = 8 bit data.
11 = 9 bit data.
Ninth Bit Enable.
0 = Disable.
1 = Enable ninth bit as Escape and ninth bit function (register C).
48
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Si2401
S3C (CIDG). Caller ID Gain
Bit
D7
D6
D5
D4
D3
D2
D1
Name
CIDG[2:0]
Type
R/W
D0
Reset settings = 0000_0001 (0x01)
Bit
Name
Function
7:3
Reserved
Read returns 0.
2:0
CIDG[2:0]
Caller ID Gain.
The Si2400 dynamically sets the On-Hook Analog Receive Gain SF4[6:4] (ARG) to
CIDG during a caller ID event (or continuously if S0C[6:5] (CIDM = 11b). This field should
be set prior to caller ID operation.
000 = 0 dB
001 = 3 dB
010 = 6 dB
011 = 9 dB
100 = 12 dB
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Si 2401
S62 (RC). Result Codes Override
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
OCR
IR
NLR
RR
Type
R/W
R/W
R/W
R/W
Reset settings = 0100_0001 (0x41)
Bit
Name
7
6
Reserved
OCR
5:3
2
Reserved
IR
1
NLR
0
RR
Function
Read returns zero.
Overcurrent Result Code (“x”).
0 = Enable.
1 = Disable.
Read returns zero.
Intrusion Result Code (“I” and “i”).
0 = Disable.
1 = Enable.
No Phone Line Result Code (“L” and “l”).
0 = Disable.
1 = Enable.
Ring Result Code (“R”).
0 = Disable.
1 = Enable.
50
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Si2401
S82 (IST). Intrusion
Bit
D7
D6
D5
D4
D3
D2
D1
Name
IST[3:0]
LCLD
IB[1:0]
Type
R/W
R/W
R/W
D0
Reset settings = 0000_1000 (0x08)
Bit
Name
Function
7:4
IST[3:0]
3
LCLD
2:1
IB[1:0]
0
Reserved
Intrusion Settling Time.
0000 = IST equals 1 second.
Delay between when the ISOmodem® chipset goes off-hook and the off-hook intrusion
algorithm begins (250 ms units).
Loop Current Loss Detect.
0 = Disable.
1 = Enables the reporting of “I” and “L” result codes while off-hook. Asserts INT if
GPIO4 (SE2[7:6]) is enabled as INT.
Intrusion Blocking.
This feature only works when SDF 0x00. Defines the method used to block the off-hook
intrusion algorithm from operating after dialing has begun.
00 = No intrusion blocking.
01 = Intrusion disabled from start of dial to end of dial.
10 = Intrusion disabled from start of dial to register S29 time out.
11 = Intrusion disabled from start of dial to carrier detect or to “N” or “n” result code.
Read returns zero.
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Si 2401
SDF (DGSR). Intrusion Deglitch
Bit
D7
D6
D5
D4
D3
D2
Name
DGSR[6:0]
Type
R/W
D1
D0
Reset settings = 0000_1100 (0x0C)
Bit
Name
Function
7
Reserved
Read returns zero.
6:0
DGSR[6:0]
Deglitch Sample Rate.
Sets the sample rate for the deglitch algorithm and the off-hook intrusion algorithm
(40 ms units).
0000000 = Disables the deglitch algorithm, and sets the off-hook intrusion sample rate to
200 ms and delay between compared samples to 800 ms.
SE0 (CF1). Chip Functions 1
Bit
D7
D6
D5
D4
D3
D2
D1
Name
ICTS
ND
SD[2:0]
Type
R/W
R/W
R/W
D0
Reset settings = 0010_0010 (0x22)
Bit
Name
Function
7:6
Read returns zero.
5
Reserved
ITCS
4
Reserved
Read returns zero.
3
ND
2:0
SD[2:0]
Invert CTS pin.
0 = Inverted (CTS).
1 = Normal (CTS).
0 = 8N1.
1 = 9N1 (hardware UART only).
Serial Dividers.
000 = 300 bps serial link.
001 = 1200 bps serial link.
010 = 2400 bps serial link.
011 = 9600 bps serial link.
100 = 19200 bps serial link.
101 = 38400 bps serial link
110 = 115200 bps serial link.
111 = 307200 bps serial link.
52
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Si2401
SE1 (GPIO1). General Purpose Input/Output 1
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
GPD5
GPIO5
Type
R/W
R/W
D1
D0
Reset settings = 0000_1110 (0x0E)
Bit
7:2
1
Name
Reserved
GPD5
0
GPIO5
Function
Read returns zero.
GPIO5 Data.
Data = 0.
Data = 1.
GPIO5.
0 = Digital input.
1 = Digital output (relay drive).
SE2 (GPIO2). General Purpose Input/Output 2
Bit
D7
D6
D5
D4
D3
D2
Name
GPIO4[1:0]
GPIO3[1:0]
GPIO2[1:0]
GPIO1[1:0]
Type
R/W
R/W
R/W
R/W
Reset settings = 0000_0000 (0x00)
Bit
7:6
5:4
3:2
1:0
Name
Function
GPIO4[1:0] GPIO4.
00 = Digital input.
01 = Digital output (relay drive).
10 = AOUT.
11 = INT function defined by S08.
GPIO3[1:0] GPIO3.
00 = Digital input.
01 = Digital output (relay drive).
10 = Reserved.
11 = ESC function (digital input).
GPIO2[1:0] GPIO2.
00 = Digital input.
01 = Digital output (relay drive; also used for CD function).
10 = Reserved.
11 = Digital input.
GPIO1[1:0] GPIO1*.
00 = Digital input.
01 = Digital output (relay drive).
10 = Reserved.
11 = Reserved.
*Note: To be used as a GPIO pin; SE4[3] (GPE) must equal zero.
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Si 2401
SE3 (GPD). GPIO Data
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
GPD4
GPD3
GPD2
GPD1
Type
R/W
R/W
R/W
R/W
D2
D1
D0
Reset settings N/A
Bit
Name
7:4
Reserved
3
GPD4
2
GPD3
1
GPD2
0
GPD1
Function
Read returns zero.
GPIO4 Data.
Data = 0
Data = 1
GPIO3 Data.
Data = 0
Data = 1
GPIO2 Data.
Data = 0
Data = 1
GPIO1 Data.
Data = 0
Data = 1
SE4 (CF5). Chip Functions 5
Bit
D7
D6
D5
D4
D3
Name
NBCK
SBCK
DRT
GPE
Type
R
R
R/W
R/W
Reset settings = xx00_0000 (0x00)
Bit
7
6
5
Name
NBCK
SBCK
DRT
4
3
Reserved
GPE
2:0
Reserved
Function
9600 Baud Clock (Read Only).
600 Baud Clock (Read Only).
Data Routing.
0 = Data mode, DSP output transmitted to line, line received by DSP input.
1 = Loopback mode, TXD through microcontroller (DSP) to RXD.
Read returns zero.
GPIO1 Enable.
0 = Disable.
1 = Enable GPIO1 to be HDLC end-of-frame flag.
Read returns zero.
54
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Si2401
SE5 (DSP1). (SE8 = 0x02) Read Only Definition
Bit
D7
D6
D5
D4
D3
D2
Name
DDAV
TDET
TONE[4:0]
Type
R
R
R
D1
D0
Reset settings N/A
Bit
Name
Function
7
6
DDAV
TDET
5
Reserved
Read returns zero.
4:0
TONE[4:0]
Tone Type Detected.
When TDET goes high, TONE indicates which tone has been detected from the following:
TONE
Tone Type
Priority
00000–01111 DTMF 0–15 (DTMFE = 1)1 See Table 17 on page 31.
1
10000
Answer tone detected 2100 Hz (ANSE = 1)2
2
10001
Bell 103 answer tone detected 2225 Hz (ANSE = 1)
2
10010
V.23 forward channel mark 1300 Hz (V23E = 1)3
3
10011
V.23 backward channel mark 390 Hz (V23E = 1)
3
10100
User defined frequency 1 (USEN1 = 1)4
4
10101
User defined frequency 2 (USEN1 = 1)
4
10110
Call progress filter A detected
6
10111
User defined frequency 3 (USEN2 = 1)5
5
11000
User defined frequency 4 (USEN2 = 1)
5
11001
Call progress filter B detected
6
DSP Data Available.
Tone Detected.
Indicates a TONE (any of type 0–25 below) has been detected.
0 = Not detected.
1 = Detected.
Notes:
1. SE6[0] (DTMFE) SE8 = 0x02.
2. SE6[1] (ANSE) SE8 = 0x02.
3. SE6[2] (V23E) SE8 = 0x02.
4. SE6[3] (USEN1) SE8 = 0x02.
5. SE6[4] (USEN2) SE8 = 0x02.
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Si 2401
SE5 (DSP2). (SE8 = 0x02) Write Only Definition
Bit
D7
D6
D5
D4
D3
D2
D1
Name
DTM[3:0]
TONC[2:0]
Type
W
W
D0
Reset settings N/A
Bit
Name
Function
7
6:3
Reserved
DTM[3:0]
2:0
TONC[2:0]
Always write zero.
Tone Type Generated.
DTMF tone (0–15) to transmit when selected by TONC = 001. See Table 17 on page 31.
DTMF Tone Selector.
ToneTone Type
000
Mute
001
DTMF
010
2225 Hz Bell mode answer tone with phase reversal
011
2100 Hz CCITT mode answer tone with phase reversal
100
2225 Hz Bell mode answer tone without phase reversal
101
2100 Hz CCITT mode answer tone without phase reversal
110
User-defined programmable frequency tone (UFRQ)
(see Table 18 on page 32, default = 1700 Hz)
111
1300 Hz V.25 calling tone
56
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Si2401
SE6 (DSP3). (SE8 = 0x02) Write Only Definition
Bit
D7
D6
Name
CPSQ
Type
W
D5
D4
D3
D2
D1
D0
CPCD
USEN2
USEN1
V23E
ANSE
DTMFE
W
W
W
W
W
W
Reset settings = 0000_0000 (0x00)
Bit
Name
Function
7
CPSQ
Call Progress Squaring Filter.
0 = Disable.
1 = Enables a squaring function on the output of filter B before the input to A (cascade
only).
6
CPCD
Call Progress Cascade Disable.
0 = Call progress filter B output is input into call progress filter A. Output from filter A is used in the detector.
1 = Cascade disabled. Two independent fourth order filters available (A and B). The
largest output of the two is used in the detector.
5
Reserved
4
USEN2
User Tone Reporting Enable 2.
0 = Disable.
1 = Enable the reporting of user defined frequency tones 3 and 4 through TONE.
3
USEN1
User Tone Reporting Enable 1.
0 = Disable.
1 = Enable the reporting of user defined frequency tones 1 and 2.
2
V23E
V.23 Tone Reporting Enable.
0 = Disable.
1 = Enable the reporting of V.23 tones, 390 Hz and 1300 Hz.
1
ANSE
Answering Tone Reporting Enable.
0 = Disable.
1 = Enable the reporting of answer tones.
0
DTMFE
DTMF Tone Reporting Enable.
0 = Disable.
1 = Enable the reporting of DTMF tones.
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Si 2401
SEB (TPD). Timer and Powerdown
Bit
D7
D6
D5
D4
D3
Name
PDDE
Type
R/W
D2
D1
D0
Reset settings = 0000_0000 (0x00)
Bit
Name
7:4
Reserved
3
PDDE
2:0
Reserved
Function
Read returns zero.
Powerdown DSP Engine.
0 = Power on.
1 = Powerdown.
Read returns zero.
58
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Si2401
SEC (RVC1). Ring Validation Control 1
Bit
D7
D6
D5
D4
D3
D2
Name
RNGV
RDLY[2:0]
RCC[2:0]
Type
R/W
R/W
R/W
D1
D0
Reset settings = 1000_1000 (0x88)
Bit
Name
Function
7
RNGV
6:4
RDLY[2:0]
3:1
RCC[2:0]
Ring Confirmation Count.
These bits set the amount of time that the ring frequency must be within the tolerances
set by the RAS[5:0] bits and the RMX[3:0] bits to be classified as a valid ring signal.
RCC[2:0]
Ring Confirmation Count Time
000
100 ms
001
150 ms
010
200 ms
011
256 ms
100
384 ms
101
512 ms
110
640 ms
111
1024 ms
0
Reserved
This bit must always be written to zero.
Ring Validation Enable.
0 = Ring validation feature is disabled.
1 = Ring validation feature is enabled in both normal operating mode and lowpower mode.
Ring Delay.
These bits set the amount of time between when a ring signal is validated and when a
valid ring signal is indicated.
RDLY[2:0]
Delay
000
0 ms
001
256 ms
010
512 ms
.
.
.
111
1792 ms
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Si 2401
SED (RVC2). Ring Validation Control 2
Bit
D7
D6
D5
D4
D3
D2
Name
RAS[5:0]
Type
R/W
D1
D0
Reset settings = 0001_1001 (0x19)
Bit
7:6
5:0
Name
Reserved
RAS[5:0]
Function
Read returns zero.
Ring Assertion Time.
These bits set the minimum ring frequency for a valid ring signal. During ring qualification,
a timer is loaded with the RAS[5:0] field upon a TIP/RING event and decrements at a regular rate. If a second or subsequent TIP/RING event occurs after the timer has timed out,
the frequency of the ring is too low, and the ring is invalidated. The difference between
RAS[5:0] and RMX[5:0] identifies the minimum duration between TIP/RING events to qualify as a ring, in binary-coded increments of 2.0 ms (nominal). A TIP/RING event typically
occurs twice per ring tone period. At 20 Hz, TIP/RING events would occur every
1/(2 x 20 Hz) = 25 ms. To calculate the correct RAS[5:0] value for a frequency range
[f_min, f_max], the following equation should be used: RAS[5:0] = 1 / (2 x f_min).
60
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Si2401
SEE (RVC3). Ring Validation Control 3
Bit
D7
Name
D6
D5
D4
D3
D1
D0
RMX[3:0]
RTO[3:0]
Type
D2
R/W
R/W
Reset settings = 0001_0110 (0x16)
Bit
Name
Function
7:4
RTO[3:0]
3:0
RMX[3:0]
Ring Timeout.
These bits set when a ring signal is determined to be over after the most recent ring
threshold crossing.
RTO[3:0]
Ring Timeout
0000
80 ms
0001
128 ms
0010
256 ms
.
.
.
1111
1920 ms
Ring Assertion Maximum Count.
These bits set the maximum ring frequency for a valid ring signal. During ring qualification,
a timer is loaded with the RAS[5:0] field upon a TIP/RING event and decrements at a regular rate. When a subsequent TIP/RING event occurs, the timer value is compared to the
RMX[3:0] field, and if it exceeds the value in RMX[3:0], the frequency of the ring is too
high, and the ring is invalidated. The difference between RAS[5:0] and RMX[3:0] identifies
the minimum duration between TIP/RING events to qualify as a ring, in binary-coded increments of 2.0 ms (nominal). A TIP/RING event typically occurs twice per ring tone period.
At 20 Hz, TIP/RING events would occur every 1/(2 x 20 Hz) = 25 ms. To calculate the correct RMX[3:0] value for a frequency range [f_min, f_max], the following equation should be
used: RMX[3:0] x 2 ms = RAS[5:0] – 2 ms – (1/(2 x f_max)).
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Si 2401
SF0 (DAA0). DAA Low Level Functions 0
Bit
D7
D6
Name
FOH[1:0]
Type
R/W
D5
D4
D3
D2
D1
D0
LM[1:0]
R/W
R/W
Reset settings = 0100_0000 (0x40)
Bit
Name
Function
7:6
FOH[1:0]
Fast Off-Hook Selection.
These bits determine the length of the off-hook counter. The default setting is 128 ms.
00 = 512 ms
01 = 128 ms
10 = 64 ms
11 = 8 ms
5:2
Reserved
Read returns zero.
1:0
LM[1:0]
Line Mode.
These bits determine the line status of the Si2401.*
00 = On-hook
01 = Off-hook
10 = On-hook line monitor mode
11 = Reserved
*Note: Under normal operation, the Si2401 internal microcontroller automatically sets these bits appropriately.
62
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Si2401
SF1 (DAA1). DAA Low Level Functions 1
Bit
D7
D6
D5
D4
D3
D2
Name
BTE
PDN
PDL
LVFD
HBE
Type
R/W
R/W
R/W
R/W
R/W
D1
D0
Reset settings = 0000_1100 (0x0C)
Bit
Name
Function
7
BTE
6
PDN
5
PDL
4
LVFD
Billing Tone Enable.
When the line-side device detects a billing tone, SF9[3] (BTD) is set.
0 = Disable.
1 = Enable.
Powerdown.
0 = Normal operation.
1 = Powers down the Si2401.
Powerdown Line-Side Chip (typically only used for board level debug.)
0 = Normal operation. Program the clock generator before clearing this bit.
1 = Places the line-side device in lower power mode.
Line Voltage Force Disable.
0 = Normal operation.
1 = The circuitry that forces the LVS register to all 0s at 3 V or less is disabled. This register may display unpredictable values at voltages between 0 to 2 V. All 0s are displayed
if the line voltage is 0 V.
3
Reserved
2
HBE
1:0
Reserved
Do not modify.
Hybrid Transmit Path Connect.
0 = Disable.
1 = Enable.
Do not modify.
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Si 2401
SF2 (DAA2). DAA Low Level Functions 2
Bit
D7
D6
D5
D4
D3
D2
Name
FDT
Type
R
D1
D0
Reset settings = xxxx_1xxx
Bit
Name
7:4
Reserved
3
FDT
2:0
Reserved
Function
Read only.
Frame Detect (Typically only used for board-level debug).
1 = Indicates isolation capacitor frame lock has been established.
0 = Indicates isolation capacitor frame lock has not been established.
Reserved
SF4 (DAA4). DAA Low Level Functions 4
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
ARL[1:0]
ATL[1:0]
Type
R/W
R/W
Reset settings = 0000_1111 (0x0F)
Bit
Name
Function
7:4
Reserved
Read returns zero.
3:2
ARL[1:0]
1:0
ATL[1:0]
AOUT Receive—Path Level.
DAA receive path signal AOUT gain.
00 = 0 dB
01 = –6 dB
10 = –12 dB
11 = Mute
AOUT Transmit—Path Level.
DAA transmit path signal AOUT gain.
00 = –18 dB
01 = –24 dB
10 = –30 dB
11 = Mute
64
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Si2401
SF5 (DAA5). DAA Low Level Functions 5
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
OHS[1:0]
ILIM
RZ
RT
Type
R/W
R/W
R/W
R/W
Reset settings = 0000_0000 (0x00)
Bit
Name
Function
7:6
Reserved
Read returns zero.
5:4
OHS[1:0]
On-Hook Speed.
These bits set the amount of time for the line-side device to go on-hook. The on-hook
speeds specified are measured from the time the register is written until loop current
equals zero.
OHS[1:0]
Mean On-Hook Speed
00
Less than 0.5 ms
01
3 ms ±10% (Meets ETSI standard)
1X
20 ms ±10% (Meets Australian spark quenching spec)
3
ILIM
Current Limiting Enable.
0 = Current limiting mode disabled.
1 = Current limiting mode enabled. This mode limits loop current to a maximum of 60 mA
per the TBR21 standard.
2
RZ
Ringer Impedance.
0 = Maximum (high) ringer impedance.
1 = Synthesized ringer impedance used to satisfy a maximum ringer impedance specification in countries, such as Poland, South Africa, and Slovenia.
1
0
Reserved
RT
Do not modify.
Ringer Threshold Select.
Used to satisfy country requirements on ring detection. Signals below the lower level do
not generate a ring detection; Signals above the upper level are guaranteed to generated
a ring detection.
0 = 13.5 to 16.5 VRMS
1 = 19.35 to 23.65 VRMS
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Si 2401
SF6 (DAA6). DAA Low Level Functions 6
Bit
D7
D6
D5
D4
D3
D2
D1
Name
MINI[1:0]
DCV[1:0]
ACT[3:0]
Type
R/W
R/W
R/W
D0
Reset settings = 1111_0000 (0xF0)
Bit
Name
Function
7:6
MINI[1:0]
Minimum Operational Loop Current.
Adjusts the minimum loop current at which the DAA can operate. Increasing the minimum operational loop current can improve signal headroom at a lower TIP/RING voltage.
MINI[1:0] Min Loop Current
00
10 mA
01
12 mA
10
14 mA
11
16 mA
5:4
DCV[1:0]
TIP/RING Voltage Adjust.
These bits adjust the voltage on the DCT pin of the line-side device, which affects the
TIP/RING voltage on the line. Low voltage countries should use a lower TIP/RING voltage. Raising the TIP/RING voltage can improve signal headroom.
DCV[1:0] DCT Pin Voltage
00
3.1 V
01
3.2 V
10
3.35 V
11
3.5 V
3:0
ACT[3:0]
AC Termination Select.
ACT[3:0] AC Termination
0000
Real 600 termination that satisfies the impedance requirements
of FCC part 68, JATE, and other countries.
0011
Global complex impedance. Complex impedance that satisfies global
impedance requirements EXCEPT New Zealand. May achieve higher
return loss for countries requiring complex ac termination.
[220 + (820 || 120 nF) and 220 + (820 || 115 nF)].
0100
Complex impedance for use in New Zealand.
[370 + (620 || 310 nF)]
1111
Complex impedance that satisfies global impedance requirements.
66
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Si2401
SF8 (DAA8). DAA Low Level Functions 8
Bit
D7
D6
D5
D4
D3
D2
D1
Name
LRV[3:0]
DCR
Type
R
R/W
D0
Reset settings vary with line-side vision
Bit
7:4
Name
LRV[3:0]
3:2
1
Reserved
DCR
0
Reserved
Function
Line-Side Device Revision Number.
0011 = Si3010 Rev C
0100 = Si3010 Rev D
0101 = Si3010 Rev E
0110 = Si3010 Rev F
Read returns an indeterministic value.
DC Impedance Selection.
0 = 50 dc termination is selected. This mode should be used for all standard
applications.
1 = 800 dc termination is selected.
Do not modify.
SF9 (DAA9). DAA Low Level Functions 9 Read Only
Bit
D7
D6
D5
D4
D3
D2
D1
Name
BTD
OVL
ROV
Type
R/W
R
R/W
D0
Reset settings = 0010_0000 (0x20)
Bit
7:4
3
Name
Reserved
BTD
2
OVL
1
ROV
0
Reserved
Function
Do not modify.
Billing Tone Detect (sticky).
0 = No billing tone detected.
1 = Billing tone detected.
Receive overload.
Same as ROV, except not sticky.
Receive Overload (sticky).
0 = No excessive level detected.
1 = Excessive input level detected.
Do not modify.
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Si 2401
SFC (DAAFC). DAA Low Level Functions
Bit
D7
Name
CTSM
Type
R/W
D6
D5
D4
D3
D2
D1
D0
Reset settings N/A
Bit
Name
Function
7
CTSM
6:0
Reserved
Clear-to-Send (CTS) Mode.
0 = CTS pin is negated as soon as a start bit is detected and reasserted when the
transmit FIFO is empty.
1 = CTS pin is negated when the FIFO is > 70% full and reasserted when the FIFO is <
30% full.
Read value indeterminate.
68
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Si2401
8. Pin Descriptions: Si2401
CLKIN/XTALI
1
16
GPIO1/EOFR
XTALO
2
3
15
14
GPIO2/CD
4
5
13
12
VA
GND
GPIO5/RI
VD
RXD
TXD
GPIO3/ESC
6
11
GPIO4/INT/AOUT
CTS
7
10
C1A
RESET
8
9
C2A
Pin #
Pin Name
Description
1
CLKIN/XTALI
XTALI—Crystal Oscillator Pin.
These pins provide support for parallel resonant AT cut crystals. XTALI also acts as an
input in the event that an external clock source is used in place of a crystal. A
4.9152 MHz crystal is required or a 4.9152 or 27 MHz clock on XTALI.
2
XTALO
3
GPI05/RI
4
VD
5
RXD
Receive Data.
Serial communication data from the Si2401.
6
TXD
Transmit Data.
Serial communication data to the Si2401.
7
CTS
Clear to Send.
Clear to send output used by the Si2401 to signal that the device is ready to receive
more digital data on the TXD pin.
8
RESET
9
C2A
Isolation Capacitor 2A.
Connects to one side of the isolation capacitor C2.
10
C1A
Isolation Capacitor 1A.
Connects to one side of the isolation capacitor C1.
XTALO—Crystal Oscillator Pin.
Serves as the output of the crystal amplifier.
General Purpose Input/RI.
This pin can be either a GPIO pin (digital in, digital out) or the RI pin. Default is digital
in. When programmed as RI, it indicates the presence of an ON segment of a ring
signal on the telephone line.
Supply Voltage.
Provides the 3.3 V supply voltage to the Si2401.
Reset Input.
An active low input that is used to reset all control registers to a defined, initialized
state. Also used to bring the Si2401 out of sleep mode.
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Si 2401
Pin #
11
Pin Name
Description
GPIO4/INT/AO General Purpose Input/INT.
UT
This pin can be either a GPIO pin (digital in, digital out) or the INT pin. Default is digital
in. When programmed as INT, this pin provides five functions. While the modem is
connected, it asserts if the carrier is lost, a wake-on ring (using the “ATZ” command)
event is detected, a loss of loop current event is detected, V.23 reversal is detected, or
if an intrusion event has been detected. The INT pin is sticky and stays asserted until
the host clears it by writing to the correct S register. (See register SE2[7:6].)
12
GND
13
VA
Regulator Voltage Reference.
This pin connects to an external capacitor and serves as the reference for the internal
voltage regulator.
14
GPIO3/ESC
General Purpose Input/Escape.
This pin can be either a GPIO pin (digital in, digital out) or the ESC pin. Default is digital in. When programmed as ESC, a positive edge on this pin causes the modem to go
from online (connected) mode to the offline (command) mode.
15
GPIO2/CD
General Purpose Input/CD.
This pin can be either a GPIO pin (digital in, digital out) or the CD pin. Default is digital
in. When programmed as CD, it is the active low carrier detect pin.
16
GPIO1/EOFR
Ground.
Connects to the system digital ground.
General Purpose Input/EOFR.
This pin can be either a GPIO pin (digital in, digital out) or the EOFR pin. Default is
digital in. This pin can also be programmed to function as the EOFR (end-of-frame
receive) signal for HDLC framing.
70
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Si2401
9. Pin Descriptions: Si3010
QE
1
16
DCT2
DCT
2
3
15
14
IGND
DCT3
4
5
13
12
QB
QE2
6
11
SC
7
8
10
RX
IB
C1B
C2B
VREG
RNG1
9
VREG2
RNG2
Table 23. Si3010 Pin Descriptions
Pin #
1
Pin Name
QE
2
DCT
3
RX
4
IB
5
C1B
6
C2B
7
VREG
8
RNG1
9
RNG2
10
VREG2
11
SC
12
QE2
13
QB
14
DCT3
15
IGND
16
DCT2
Description
Transistor Emitter.
Connects to the emitter of Q3.
DC Termination.
Provides dc termination to the telephone network.
Receive Input.
Serves as the receive side input from the telephone network.
Internal Bias 1.
Provides Internal Bias.
Isolation Capacitor 1B.
Connects to one side of isolation capacitor C1 and communicates with the Si2401.
Isolation Capacitor 2B.
Connects to one side of isolation capacitor C2 and communicates with the Si2401.
Voltage Regulator.
Connects to an external capacitor to provide bypassing for an internal power supply.
Ring 1.
Connects through a capacitor to the RING lead of the telephone line. Provides the ring
and caller ID signals to the Si2401.
Ring 2.
Connects through a capacitor to the TIP lead of the telephone line. Provides the ring
and caller ID signals to the Si2401.
Voltage Regulator 2.
Connects to an external capacitor to provide bypassing for an internal power supply.
Circuit Enable.
Enables transistor network.
Transistor Emitter 2.
Connects to the emitter of Q4.
Transistor Base.
Connects to the base of transistor Q3. Used to go on- and off-hook.
DC Termination 3.
Provides the dc termination to the telephone network.
Isolated Ground.
Connects to ground on the line-side interface.
DC Termination 2.
Provides dc termination to the telephone network.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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Si 2401
10. Ordering Guide
Chipset
Region
Digital
Line
Lead-Free
Temperature
Si2401
Global
Si2401-FS
Si3010-F-FS
Yes
0 to 70 °C
72
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.01 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 2, 2021
Si2401
11. Package Outline: 16-Pin SOIC
Figure 6 illustrates the package details for the Si2401 and Si3010. Table 24 lists the values for the dimensions
shown in the illustration.
16
9
h
E
bbb B
H
-B-
1
8
B
L
aaa C A B
-A-
Detail F
D
-C-
C
A
A1
e
See Detail F
Seating Plane
Figure 6. 16-pin Small Outline Integrated Circuit (SOIC) Package
Table 24. Package Diagram Dimensions
Symbol
A
A1
B
C
D
E
e
H
h
L
aaa
bbb
Millimeters
Min
Max
1.35
1.75
.10
.25
.33
.51
.19
.25
9.80
10.00
3.80
4.00
1.27 BSC
5.80
6.20
.25
.50
.40
1.27
0.10
0º
8º
0.25
0.25
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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Si 2401
DOCUMENT CHANGE LIST
Revision 0.7 to Revision 0.9
Updated Table 5, “Absolute Maximum Ratings,” on
page 8.
Updated "3. Bill of Materials: Si2401/10 Chipset" on
page 11.
Updated SF3 description in Table 21, “S-Register
Summary,” on page 35.
Updated SE4 description in Register SE4 (CF5).,
“Chip Functions 5,” on page 54.
Updated "8. Pin Descriptions: Si2401" on page 69.
Removed Appendix A and Appendix B. This
information can be found in “AN94: Si2401 Modem
Designer’s Guide”.
Revision 0.9 to Revision 1.0
Updated features list to include lead-free, RoHS
compliant packages.
Updated ring detect voltage values in Table 2 on
page 5.
Updated transmit and receive values in Table 4 on
page 7.
Updated "3. Bill of Materials: Si2401/10 Chipset" on
page 11.
Updated country-specific register settings in
Table 10 on page 15.
Updated reset values in Table 21 on page 35.
Updated default binary values in Table 22 on page
40.
Updated "10. Ordering Guide" on page 72.
Updated "11. Package Outline: 16-Pin SOIC" on
page 73.
Revision 1.0 to Revision 1.01
Updated Table 3, “Bill of Materials: Si2401/10
Chipset,” on page 11.
Updated Table 10, “Country-Specific Register
Settings,” on page 15.
74
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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Connecting Everyone
and Everything,
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