SI2456-FTR

Si2456/33/14 V. 9 0 , V. 3 4 , V. 3 2 B I S I SO M O D E M ® C H I PS E T WITH I N T E G R A T E D G L O B A L DAA Features Data modem formats Integrated DAA ITU-T, Bell 300 bps up to 56 kbps V.42, V.42bis, MNP2-5 Automatic rate negotiation Over 5000 V capacitive isolation Parallel phone detect Globally-compliant line interface Caller ID decode 3.3 V power No external ROM or RAM required UART with flow control AT command set support Overcurrent detection Fast connect Parallel interface Call progress support Firmware upgradeable Applications Set-top boxes E-mail terminals Point-of-sale terminals Digital video recorders Security systems Remote monitoring Ordering Information This data sheet is valid only for those chipset combinations listed on page 69. Pin Assignments Description Si2456/33/14 The Si2456 is a complete, ITU-V.90-compliant, 56 kbps modem chipset with integrated direct access arrangement (DAA) that provides a programmable line interface to meet global telephone line requirements with a single design. Available in two small packages, it eliminates the need for a separate DSP data pump, external RAM and ROM, modem controller, codec, isolation transformer, relays, opto-isolators, and 2- to 4wire hybrid. The ISOmodem® chipset is ideal for embedded modem applications due to its small board space, low power consumption, and global compliance. The Si2433 and Si2414 products offer all the same features as the Si2456 with connect rates of up to 33.6 kbps and 14.4 kbps, respectively. CLKIN/XTALI 1 24 XTALO 2 23 DCD/D4 CLKOUT/EECS/A0 3 22 ESC/D3 EECLK/D5 D6 4 21 C1A VD3.3 5 ISOB GND 6 20 19 VDA 7 18 GND RTS/D7 8 17 VDB RXD/RD 9 16 EESD/D2 TXD/WR 10 15 RI/D1 CTS/CS 11 14 INT/D0 RESET 12 13 AOUT/INT VD3.3 Functional Block Diagram Si3015 CLKIN/XTALI RXD TXD CTS RTS DCD ESC RI PLL Clocking RAM/ROM RNG1 RNG2 Data Bus QB QE Serial Interface C1A Microcontroller DSP INT CS WR RD A0 D0-D7 IGND C1B DAA Interface Si3015 CLKOUT QE2 DCT XTALO 4 5 6 7 8 16 15 FILT2 FILT 14 13 RX REXT 12 11 REF 10 9 VREG2 VREG REXT2 To Phone Line AOUT Parallel Interface 1 2 3 Patents pending ISOB RESET Rev. 1.2 8/06 Copyright © 2006 by Silicon Laboratories Si2456/33/14 Si2456/33/14 2 Rev. 1.2 Si2456/33/14 TA B L E O F C O N T E N TS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3. Bill of Materials: Si2456/33/14 Chipset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1. Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3. Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 4.4. Command Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 4.5. Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.6. Fast Connect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 4.7. V.29 Fast Connect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.8. Clocking/Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.9. Data Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.10. Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.11. Wire Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.12. Caller ID Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.13. Parallel Phone Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.14. Overcurrent Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.15. Global Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.16. Firmware Upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 4.17. EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.18. AT Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 4.19. Extended AT Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5. S-Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6. User-Access Registers (U-Registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1. Bit-Mapped U-Register Detail (defaults in bold) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7. Parallel Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 8. Pin Descriptions: Si2456/33/14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9. Pin Descriptions: Si3015 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 10. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 11. Package Outline: 24-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 12. Package Outline: 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Rev. 1.2 3 Si2456/33/14 1. Electrical Specifications Table 1. Recommended Operating Conditions Symbol Test Condition Min2 Typ Max2 Unit Ambient Temperature TA K-Grade, F-Grade 0 25 70 °C Ambient Temperature TA B-Grade –40 25 85 °C Si2456/33/14 Supply Voltage, Digital3 VD 3.0 3.3 3.6 V Parameter1 Notes: 1. The Si2456/33/14 specifications are guaranteed when the typical application circuit (including component tolerance) and any Si2456/33/14 and any Si3015 are used. See "Typical Application Schematic" on page 11. 2. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. 3. The digital supply, VD, operates from 3.0 to 3.6 V. The Si2456/33/14 interface supports 5 V logic (CLKIN/XTALI supports 3.3 V logic only). 4 Rev. 1.2 Si2456/33/14 Table 2. DAA Loop Characteristics (VD = 3.0 to 3.6 V, TA = 0 to 70 °C for K-Grade) Parameter Symbol Test Condition Min Typ Max Unit DC Termination Voltage VTR IL = 20 mA, ACT1 = 1 DCT = 11 (CTR21) — — 7.5 V DC Termination Voltage VTR IL = 42 mA, ACT = 1 DCT = 11 (CTR21) — — 14.5 V DC Termination Voltage VTR IL = 50 mA, ACT = 1 DCT = 11 (CTR21) — — 40 V DC Termination Voltage VTR IL = 60 mA, ACT = 1 DCT = 11 (CTR21) 40 — — V DC Termination Voltage VTR IL = 20 mA, ACT = 0 DCT = 01 (Japan) — — 6.0 V DC Termination Voltage VTR IL = 100 mA, ACT = 0 DCT = 01 (Japan) 9 — — V DC Termination Voltage VTR IL = 20 mA, ACT = 0 DCT = 10 (FCC) — — 7.5 V DC Termination Voltage VTR IL = 100 mA, ACT = 0 DCT = 10 (FCC) 9 — — V On-Hook Leakage Current ILK VTR = –48 V — — 7 μA Operating Loop Current ILP FCC/Japan Modes 13 — 120 mA Operating Loop Current ILP CTR21 13 — 60 mA DC flowing through ring detection circuitry — — 7 µA DC Ring Current2 Ring Detect Voltage3 VRD RT = 0 11 — 22 Vrms 3 VRD RT = 1 17 — 33 Vrms FR 15 — 68 Hz REN — — 0.2 Ring Detect Voltage Ring Frequency Ringer Equivalence Number4 Notes: 1. ACT = U67, bit 5; DCT = U67, bits 3:2; RT = U67, bit 0; RZ = U67, bit 1. 2. R25 and R26 installed. 3. The ring signal is guaranteed to not be detected below the minimum. The ring signal is guaranteed to be detected above the maximum. 4. C15, R14, Z2, and Z3 not installed. RZ = 0. Rev. 1.2 5 Si2456/33/14 TIP + 600 Ω Si3015 IL VTR 10 µF – RING Figure 1. Test Circuit for Loop Characteristics Table 3. DC Characteristics, VD = 3.3 V (VD = 3.0 to 3.6 V, TA = 0 to 70 °C for K-Grade) Parameter Symbol Test Condition Min Typ Max Unit High Level Input Voltage VIH 2.0 — — V Low Level Input Voltage VIL — — 0.8 V High Level Output Voltage VOH IO = –2 mA 2.4 — — V Low Level Output Voltage VOL IO = 2 mA — — 0.35 V IL –10 — 10 µA RPU 50 100 200 kΩ Input Leakage Current Pullup Resistance Pins 3,4,9,11, 13,14,16,23,24 Total Supply Current* Total Supply Current, Powerdown * ID VD33 pin — 26 35 mA ID PDN = 1 — 80 — μA *Note: All inputs at 0 or VD. All inputs held static except clock, and all outputs unloaded (Static IOUT = 0 mA). 6 Rev. 1.2 Si2456/33/14 Table 4. DAA AC Characteristics (VD = 3.0 to 3.6 V, TA = 0 to 70 °C for K-Grade) Parameter Symbol Sample Rate Crystal Oscillator Frequency Test Condition Min Typ Max Unit Fs — 9.6 — kHz FXTL — 4.9152 — MHz Transmit Frequency Response Low –3 dBFS Corner — 5 — Hz Receive Frequency Response Low –3 dBFS Corner — 5 — Hz — 1 — VPEAK Transmit Full Scale Level 1 1 Receive Full Scale Level VFS — 1 — VPEAK DR ACT5 DCT5 = 0, = 10 (FCC) IL=100 mA — 82 — dB Dynamic Range2,3,6 DR ACT = 0, DCT = 01 (Japan) IL = 20 mA — 83 — dB Dynamic Range2,3,4 DR ACT = 1, DCT = 11(CTR21) IL = 60 mA — 84 — dB Transmit Total Harmonic Distortion4,7 THD ACT = 0, DCT = 10 (FCC) IL = 100 mA — –85 — dB Transmit Total Harmonic Distortion5,7 THD ACT = 0, DCT = 01 (Japan) IL = 20 mA — –76 — dB Receive Total Harmonic Distortion6,7 THD ACT = 0, DCT = 01 (Japan) IL = 20 mA — –74 — dB Receive Total Harmonic Distortion4,7 THD ACT = 1, DCT = 11 (CTR21) IL = 60 mA — –82 — dB AOUT Dynamic Range VIN = 1 kHz — 40 — dB AOUT THD VIN = 1 kHz — 40 — dB AOUT Full-Scale Level — 0.7VDD — VPP AOUT Mute Level — 60 — dB Dynamic Range2,3,4 VFS Notes: 1. Measured at TIP and RING with 600 Ω termination at 1 kHz. 2. DR = 20 x log |Vin| + 20 x log (RMS signal/RMS noise). 3. Measurement is 300 to 3400 Hz. Applies to transmit and receive paths. 4. Vin = 1 kHz, –3 dBFS, Fs = 10300 Hz. 5. ACT = U67, bit 5; DCT = U67, bits 3:2. 6. Vin = 1 kHz, –6 dBFS, Fs = 10300 Hz. 7. THD = 20 x log (RMS distortion/RMS signal). Rev. 1.2 7 Si2456/33/14 Table 5. Absolute Maximum Ratings Parameter Symbol Value Unit DC Supply Voltage VD 4.1 V Input Current, Si2456/33/14 Digital Input Pins IIN ±10 µA Digital Input Voltage VIND –0.3 to 5.3 V CLKIN/XTALI Input Voltage VXIND –0.3 to (VD + 0.3) V TA –10 to 100 °C TSTG –40 to 150 °C Operating Temperature Range Storage Temperature Range Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 6. Switching Characteristics (VD = 3.0 to 3.6 V, TA = 0 to 70 °C for K-Grade) Parameter Symbol CLKOUT Output Clock Frequency Min Typ Max Unit 2.4576 — 39.3216 MHz Baud Rate Accuracy tBD –1 — 1 % CTS or RTS ↑ High to Start Bit↓ tRTS 10 — — ns RESET ↓ to RESET ↑ tRS 5.0 — — ms RESET ↑ to 1st AT Command tAT 300 — — ms Address Setup tAS 15 — — ns Address Hold tAH 0 — — ns WR Low Pulse Width tWL 50 — — ns tWDSU 20 — — ns Write Cycle Time tWC 120 — — ns Chip Select Setup tCSS 10 — — ns Chip Select Hold tCSH 0 — — ns tRL 50 — — ns tRLDD — — 20 ns Data Hold tDH 10 — — ns RD High to Hi-Z Time tDZ — — 30 ns Read Cycle Time tRC 120 — — ns Write Data Setup Time RD Low Pulse Width RD Low to Data Driven Time Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VD – 0.4 V, VIL = 0.4 V 8 Rev. 1.2 Si2456/33/14 UART Time for Modem Receive Path (8N1 Mode) 8-B it Data M ode RX S tart tR TS D0 D1 D2 D3 D4 D5 D6 D7 S top t R TH RTS UART Timing for Modem Transmit Path (9N1 Mode with 9th Bit Escape) 9-B it Data M ode TX S tart D0 D1 D2 D3 D4 D5 D6 D7 t R TS ESC S top t CTH CTS Figure 2. Asynchronous UART Serial Interface Timing Diagram Rev. 1.2 9 Si2456/33/14 t CSS t CSH t AS t AH CS ADDRESS = 0 or 1 A0 t RC t RL RD t DZ t RLDD t DH D[7:0] VALID DATA VALID DATA t RLDD Figure 3. Parallel Interface Read Timing t CSS t CSH t AS t AH CS A0 ADDRESS = 0 or 1 tW L tW C WR t W DSU t DH D[7:0] VALID DATA VALID DATA Figure 4. Parallel Interface Write Timing 10 Rev. 1.2 Y1 1 C26 C35 RTSb/D7 RXD/RDb TXD/WRb CTSb/CSb RESETb CLKOUT/EECS/A0 D6 2 C27 1 2 3 4 5 6 7 8 9 10 11 12 AOUT/INTb INTb/D0 RIb/D1 EESD/D2 CLKIN/XTALI EECLK/D5 XTALO DCD/D4 CLKOUT/EECS/A0 ESC/D3 D6 C1A VD3.3 ISOB GND VD 3.3 VDA GND RTS/D7 VDB RXD/RD EESD/D2 TXD/WR RI/D1 CTS/CS INT/D0 RESET AOUT/INT Si2456/33/14 U1 ESC/D3 DCDb/D4 EECLK/D5 24 23 22 21 20 19 18 17 16 15 14 13 C37 Decoupling caps for U1 VD C36 C3 Z4 R27 C30 D3 Rev. 1.2 R28 C9 R7 R8 1 2 3 4 5 6 7 8 U2 C18 C19 D4 Si3015 C7 C8 Z5 TSTA/QE2 TX/FILT2 TSTB/DCT NC/FILT IGND RX C1B REXT RNG1 DCT/REXT2 RNG2 NC/REF QB NC/VREG2 QE VREG C6 16 15 14 13 12 11 10 9 C13 R9 R10 C16 C12 + R11 D1 RV2 D2 C14 + R12 R13 R2 + C5 Note 5: L1,L2, C38, C39, R31, R32 are for EN55022/CISPR-22 Conduc ted Disturbance compliance. Note 4: R27, R28, D3, D4, Z4, Z5, RV2 may be populated for enhanced lightning option. Note 3: S ee "Billing Tone Immunity" section for optional billing tone filter (Germany, Switzerland, South Africa). Note 2: See "Ringer Impedance" section for optional Czech Republic support. Note 1: R12, R13 and C14 are only required if complex AC termination is used (ACT bit = 1). C4 C1 R15 C10 R25 R26 C22 R18 Z1 C25 R24 Q4 C24 R5 R19 Refer to AN48 for Layout Guidelines Please submit layout to Silicon Labs for review prior to PCB fabrication. C38 C39 Q2 R31 R32 L1 L2 Q1 R16 VCC Q3 C20 R6 FB1 FB2 RV1 TIP RING Si2456/33/14 2. Typical Application Schematic 11 R17 Si2456/33/14 3. Bill of Materials: Si2456/33/14 Chipset Component Value Supplier(s) C1,C41 150 pF, 3 kV, X7R, ±20% Novacap, Venkel, Johanson, Murata, Panasonic C3,C13,C35,C36 0.22 µF, 16 V, X7R, ±20% Novacap, Venkel, Johanson, Murata, Panasonic 0.1 µF, 50 V, Elec/Tant, ±20% Venkel, Johanson, Murata, Panasonic 0.1 µF, 16 V, X7R, ±20% Novacap, Venkel, Johanson, Murata C7,C8 560 pF, 250 V, X7R, ±20% Novacap, Venkel, Johanson, Murata, Panasonic C9 22 nF, 250 V, X7R, ±20% Novacap, Venkel, Johanson, Murata, Panasonic 1.0 µF, 16 V, Tant, ±20% Venkel, Panasonic 0.68 µF, 16 V, X7R/Elec/Tant, ±20% Novacap, Venkel, AUX, Murata, Panasonic C18,C193 3.9 nF, 16 V, X7R, ±20% Novacap, Venkel, Johanson, Murata C20 0.01 µF, 16 V, X7R, ±20% Novacap, Venkel, Johanson, Murata 1800 pF, 50 V, X7R, ±20% Not installed 1000 pF, 3 kV, X7R, ±10% Novacap, Venkel, Johanson, Murata, Panasonic 33 pF, 16 V, NPO, ±5% Novacap, Venkel, Johanson, Murata 10 pF, 16 V, NPO, ±10% Not Installed 47 pF, 16 V, X7R, ±10% Venkel Dual Diode, 300 V, 225 mA Central Semiconductor D3,D4 BAV99 Dual Diode, 70 V, 350 mW Diodes Inc., OnSemiconductor, Fairchild FB1,FB2 Ferrite Bead, 600 Ω, ±25%, 200 mA Murata L1,L22,5 68 μH, 120 mA, 4 Ω max, ±10% Murata, Panasonic Q1,Q3 A42, NPN, 300 V OnSemiconductor, Fairchild, Zetex Q2 A92, PNP, 300 V OnSemiconductor, Fairchild, Zetex BCP56, NPN, 60 V, 1/2 W OnSemiconductor, Fairchild C5 2 C6,C10,C16,C37 3 C12 C14 C22 2 4 C24,C25 1 C26,C27 C30 4 2,5 C38,C39 D1,D26 1 7 Q4 Notes: 1. The Si2456/33/14 design survives up to 3500 V longitudinal surges without R27, R28, D3, D4, Z4, and Z5. Adding the R27, R28, D3, D4, Z4, and Z5 enhanced lightning options increases longitudinal surge survival to greater than 6600 V. The isolation capacitors, C1, C4, C24, and C25, must also be rated to greater than the surge voltage. Y-class capacitors are recommended for highest surge survival. 2. For FCC-only designs, C14, C38, C39, R12, R13, R31, and R32 are not required (leave Si3015 pin 12 unconnected); L1 and L2 may be replaced with a short; R2 may be ±5%; with Z1 rated at 18 V, C5 may be rated at 16 V; also see Note 9. 3. If the auto answer, ring detect, and caller ID features are not used, R9, R10, C7, and C8 may be removed. 4. C22 and C30 may provide an additional improvement in emissions/immunity, depending on design and layout. Population option recommended. See “AN70: Si2456/Si2433/Si2414/Si2403 Modem Designer’s Guide” for details. 5. Compliance with EN55022 and/or CISPR-22 conductance disturbance tests requires the following: L1, L2, C38, C39, R31, and R32; D1 and D2 must be 400 V rated, and RV2 must be populated. See also “EN55022 and CISPR-22 Compliance” in “AN70: Si2456/ Si2433/Si2414/Si2403 Modem Designer’s Guide”. 6. Several diode bridge configurations are acceptable (suppliers include General Semi., Diodes Inc.) 7. Q4 may require copper on board to meet 1/2 W power requirement. (Contact manufacturer for details.) 8. RV2 can be installed to improve performance for multiple longitudinal surges. 9. The R7, R8, R15, and R16, R17, R19 resistors may each be replaced with a single resistor of 1.78 kΩ, 3/4 W, ±1%. For FCC-only designs, 1.78 kΩ, 1/16 W, ±5% resistors may be used. 10. If the parallel phone detection feature is not used, R25 and R26 may be removed. 11. To ensure compliance with ITU specifications, frequency tolerance must be less than 100 ppm including initial accuracy, 5-year aging, 0 to 70 °C, and capacitive loading. Crystals with 50 ppm initial accuracy typically satisfy this requirement. 12 Rev. 1.2 Si2456/33/14 Component Value Supplier(s) RV1 Sidactor, 275 V, 100 A Teccor, ST Microelectronics, Microsemi, TI RV25,8 270 V, MOV Not Installed 402 Ω, 1/16 W, ±1% Venkel, Panasonic 100 kΩ, 1/16 W, ±1% Venkel, Panasonic 120 kΩ, 1/16 W, ±5% Venkel, Panasonic 5.36 kΩ, 1/4 W, ±1% Venkel, Panasonic 56 kΩ, 1/10 W, ±5% Venkel, Panasonic R2 2 R5 R6 9 R7,R8,R15,R16,R17,R19 R9,R10 3 R11 9.31 kΩ, 1/16 W, ±1% Venkel, Panasonic R12 2 78.7 Ω, 1/16 W, ±1% Venkel, Panasonic R13 2 215 Ω, 1/16 W, ±1% Venkel, Panasonic R18 2.2 kΩ, 1/10 W, ±5% Venkel, Panasonic 150 Ω, 1/16 W, ±5% Venkel, Panasonic 10 MΩ, 1/16 W, ±5% Venkel, Panasonic 10 Ω, 1/10 W, ±5% Venkel, Panasonic 470 Ω, 1/16 W, ±5% Venkel, Panasonic U1 Si2456/33/14 Silicon Labs U2 Si3015 R24 10 R25,R26 R27,R281 2,5 R31,R32 Silicon Labs 11 Y1 4.9152 MHz, 20 pF, 100 ppm , 150 ESR Not Installed Z11 Zener Diode, 43 V, 1/2 W Vishay, OnSemiconductor, Rohm Z4,Z51 Zener Diode, 5.6 V, 1/2 W Vishay, OnSemiconductor, Rohm Notes: 1. The Si2456/33/14 design survives up to 3500 V longitudinal surges without R27, R28, D3, D4, Z4, and Z5. Adding the R27, R28, D3, D4, Z4, and Z5 enhanced lightning options increases longitudinal surge survival to greater than 6600 V. The isolation capacitors, C1, C4, C24, and C25, must also be rated to greater than the surge voltage. Y-class capacitors are recommended for highest surge survival. 2. For FCC-only designs, C14, C38, C39, R12, R13, R31, and R32 are not required (leave Si3015 pin 12 unconnected); L1 and L2 may be replaced with a short; R2 may be ±5%; with Z1 rated at 18 V, C5 may be rated at 16 V; also see Note 9. 3. If the auto answer, ring detect, and caller ID features are not used, R9, R10, C7, and C8 may be removed. 4. C22 and C30 may provide an additional improvement in emissions/immunity, depending on design and layout. Population option recommended. See “AN70: Si2456/Si2433/Si2414/Si2403 Modem Designer’s Guide” for details. 5. Compliance with EN55022 and/or CISPR-22 conductance disturbance tests requires the following: L1, L2, C38, C39, R31, and R32; D1 and D2 must be 400 V rated, and RV2 must be populated. See also “EN55022 and CISPR-22 Compliance” in “AN70: Si2456/ Si2433/Si2414/Si2403 Modem Designer’s Guide”. 6. Several diode bridge configurations are acceptable (suppliers include General Semi., Diodes Inc.) 7. Q4 may require copper on board to meet 1/2 W power requirement. (Contact manufacturer for details.) 8. RV2 can be installed to improve performance for multiple longitudinal surges. 9. The R7, R8, R15, and R16, R17, R19 resistors may each be replaced with a single resistor of 1.78 kΩ, 3/4 W, ±1%. For FCC-only designs, 1.78 kΩ, 1/16 W, ±5% resistors may be used. 10. If the parallel phone detection feature is not used, R25 and R26 may be removed. 11. To ensure compliance with ITU specifications, frequency tolerance must be less than 100 ppm including initial accuracy, 5-year aging, 0 to 70 °C, and capacitive loading. Crystals with 50 ppm initial accuracy typically satisfy this requirement. Rev. 1.2 13 Si2456/33/14 Table 7. Protocol Characteristics Item Specification Data Rate 56 kbps1 54.666 kbps1 53.333 kbps1 52 kbps1 50.666 kbps1 49.333 kbps1 48 kbps1 46.666 kbps1 45.333 kbps1 44 kbps1 42.666 kbps1 41.333 kbps1 40 kbps1 38.666 kbps1 37.333 kbps1 36 kbps1 34.666 kbps1 33.333 kbps1 32 kbps1 30.666 kbps1 29.333 kbps1 28 kbps1 33.6 kbps2 31.2 kbps2 28.8 kbps2 26.4 kbps2 24.0 kbps2 21.6 kbps2 19.2 kbps2 16.8 kbps2 14.4 kbps 12.0 kbps 9600 bps 7200 bps 4800 bps 2400 bps 1200 bps 300 bps 300 bps ITU-T V.901 ITU-T V.901 ITU-T V.901 ITU-T V.901 ITU-T V.901 ITU-T V.901 ITU-T V.901 ITU-T V.901 ITU-T V.901 ITU-T V.901 ITU-T V.901 ITU-T V.901 ITU-T V.901 ITU-T V.901 ITU-T V.901 ITU-T V.901 ITU-T V.901 ITU-T V.901 ITU-T V.901 ITU-T V.901 ITU-T V.901 ITU-T V.901 ITU-T V.342 ITU-T V.342 ITU-T V.342 ITU-T V.342 ITU-T V.342 ITU-T V.342 ITU-T V.342 ITU-T V.342 ITU-T V.34 or V.32bis ITU-T V.34 or V.32bis ITU-T V.34, V.32bis, or V.29 ITU-T V.34 or V.32bis ITU-T V.34 or V.32bis ITU-T V.34 or V.22bis ITU-T V.22bis, V.23, or Bell 212A ITU-T V.21 Bell 103 Notes: 1. Supported on Si2456 only. 2. Supported on Si2456 and Si2433 only. 14 Rev. 1.2 Si2456/33/14 Table 7. Protocol Characteristics (Continued) Item Data Format Bit asynchronous Compatibility Specification Selectable 8, 9, 10, or 11 bits per character ITU-T V.901, V.342, V.32bis, V.32, V.23, V.22bis, V.22, V.21, Bell 212A, and Bell 103 Operating Mode Switched network Two-wire full duplex Data Modulation 28 to 56 kbps1 2.4 to 33.6 kbps2 14.4 kbps 12.0 kbps 9600 bps 9600 bps 9600 bps 7200 bps 4800 bps 2400 bps 1200 bps 0 to 300 bps V.90 as specified by ITU-T V.34 as specified by ITU-T 128-level TCM/2400 Baud ±0.01% 64-level TCM/2400 Baud ±0.01% 32-level TCM/2400 Baud ±0.01% 16-level QAM/2400 Baud ±0.01% V.29 QAM as specified by ITU-T 16-level TCM/2400 Baud ±0.01% 4-level QAM/2400 Baud ±0.01% 16-level QAM/600 Baud ±0.01% 4-level PSK/600 Baud ±0.01% FSK 0–300 Baud ±0.01% Answer Tone ITU-T V.32bis, V.32, V.22bis, V.22, and V.21 modes Bell 212A and 103 modes Transmit Carrier V.901 V.342 ITU-T V.32bis ITU-T V.32 ITU-T V.22, V.22bis/Bell 212A Originate mode Answer mode ITU-T V.21 Originate mode Answer mode Bell 103 Originate mode Answer mode 2100 Hz ±3 Hz 2225 Hz ±3 Hz As specified by ITU-T As specified by ITU-T 1800 Hz ±0.01% 1800 Hz ±0.01% 1200 Hz ±0.5 Hz 2400 Hz ±1 Hz Mark (980 Hz ±12 Hz) Space (1180 Hz ±12 Hz) Mark (1650 Hz ±12 Hz) Space (1850 Hz ±12 Hz) Mark (1270 Hz ±12 Hz) Space (1070 Hz ±12 Hz) Mark (2225 Hz ±12 Hz) Space (2025 Hz ±12 Hz) Output Level Permissive—Switched network –9 dBm maximum Notes: 1. Supported on Si2456 only. 2. Supported on Si2456 and Si2433 only. Rev. 1.2 15 Si2456/33/14 Table 7. Protocol Characteristics (Continued) Item Receive Carrier ITU-T V.901 ITU-T V.342 ITU-T V.32bis ITU-T V.32 ITU-T V.22, V.22bis/Bell 212A Originate mode Answer mode ITU-T V.21 Originate mode Answer mode Bell 103 Originate mode Answer mode Specification As specified by ITU-T As specified by ITU-T 1800 Hz ±7 Hz 1800 Hz ±7 Hz 2400 Hz ±7 Hz 1200 Hz ±7 Hz Mark (980 Hz ±12 Hz) Space (1180 Hz ±12 Hz) Mark (1650 Hz ±12 Hz) Space (1850 Hz ±12 Hz) Mark (2225 Hz ±12 Hz) Space (2025 Hz ±12 Hz) Mark (1270 Hz ±12 Hz) Space (1070 Hz ±12 Hz) Carrier Detect (level for ITU-T V.22bis, V.22, V.21, 212, 103) in Switched Network Acquisition (–43 dBm) Release (–48 dBm) Hysteresis 2 dBm minimum Note: ITU-T V.901, V.342, V.32/V.32bis are echo-canceling protocols that use signal quality as criteria for maintaining connection. They also provide for self-training detection to force disconnect. DTE Interface EIA/TIA-232-E (ITU-T V.24/V.28/ISO 2110) Line Equalization Connection Options Automatic Adaptive Loss of Carrier in ITU-T V.22bis and lower Phone Types 500 (rotary dial), 2500 (DTMF dial) Dialing Pulse and Tone DTMF Output Level Per Part 68 Pulse Dial Ratio Make/Break: 39/61% Ring Cadence On 2 seconds; Off 4 seconds Call Progress Monitor BUSY CONNECT (rate) NO CARRIER NO DIALTONE OK RING RINGING Notes: 1. Supported on Si2456 only. 2. Supported on Si2456 and Si2433 only. 16 Rev. 1.2 Si2456/33/14 4. Functional Description 4.1. Digital Interface The ISOmodem® chipset is a complete embeddedmodem chipset with integrated direct-access arrangement (DAA) that provides a programmable line interface to meet global telephone line requirements. Available in two small packages, this solution includes a DSP data pump, a modem controller, on-chip RAM and ROM, an analog front end (AFE), a DAA, and analog output. The ISOmodem chipset digital I/O can be configured as either a serial UART interface with flow control or as a parallel 8-bit interface. The Si2456/33/14 accepts standard modem AT commands and provides connect rates up to 56/33.6/ 14.4 kbps full-duplex over the Public Switched Telephone Network (PSTN). The Si2456/33/14 features a complete set of modem protocols including all ITU-T standard formats up to 56 kbps. The Si2456/33/14 provides numerous additional features for embedded modem applications. The modem includes full caller ID detection and decoding for global standards. Call progress is supported through echoing result codes and is also programmable to meet global settings. Because the Si2456/33/14 integrates the DAA, analog features, such as parallel phone detect, overcurrent detection, and global PTT compliance with a single design, are included. This device is ideal for embedded modem applications due to its small board space, low power consumption, and global compliance. The Si2456/33/14 solution includes a silicon DAA using Silicon Laboratories’ proprietary capacitive isolation technology. This highlyintegrated DAA can be programmed to meet worldwide PTT specifications for ac termination, dc termination, ringer impedance, and ringer threshold. In addition, the Si2456/33/14 has been designed to meet the most stringent worldwide requirements for out-of-band energy, billing-tone immunity, lightning surges, and safety requirements. The Si2456/33/14 is designed to be rapidly incorporated into existing modem applications. The device interfaces directly through either a serial UART to a microcontroller or to a PC through a standard RS-232 transceiver. This interface allows for PC evaluation of the modem immediately upon powerup via the AT commands using standard terminal software. The Si2456/33/14 also provides an 8-bit parallel port. The Si2456/33/14 solution requires only a few low-cost discrete components to achieve global compliance. See the "Typical Application Schematic" on page 11. Selection of a serial or parallel I/O interface is determined by the state of AOUT/INT (Si2456/33/14, pin 13) during the rising edge of RESET. An internal pullup resistor forces the default state to serial mode operation. An external 10 kΩ pulldown resistor can be connected to AOUT/INT to force selection of parallel mode. Additionally, when selecting parallel mode, CS should remain high until after the rising edge of RESET. Configuration of pins 3, 4, 8–11, 13–16, and 22–24 is determined by this interface selection. 4.2. Serial Interface The ISOmodem chipset supports Data Terminal Equipment (DTE) rates up to 307.2 kbps with the standard serial UART format. Upon powerup, the UART defaults to a 19.2 kbps baud rate. If a pulldown resistor ≤ 10 kΩ is placed between D2 (Si2456/33/14, pin 16) and GND (Si2456/33/14, pin 6), the DTE rate is set by the autobaud feature after reset. The serial interface also provides a hardware pin, DCD (data carrier detect), which remains low as long as the Si2456/33/14 is connected. The INT interrupt pin can be programmed to alert the host of changes to the interrupts listed in I/O Control 0 (U70). 4.2.1. Autobaud The ISOmodem chipset includes an automatic baud rate detection feature that allows the host to start transmitting data at any standard DTE rate from 300 bps to 307.2 kbps. This feature is enabled by placing a pulldown resistor 140 mA in all modes except CTR21 Overload > 54 mA in CTR21 mode Rev. 1.2 59 Si2456/33/14 U7A GENA Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 Name DOP ADD Type R/W R/W D5 D4 D3 D2 D1 D0 HDLC FAST R/W R/W Reset settings = 0x0000 Bit Name Function 15:8 Reserved 7 DOP Dial or Pulse. 0 = Normal ATDTW operation 1 = Use ATDTW for Pulse/Tone Dial Detection (see also ATDW command) 6 ADD Adaptive Dialing 1 = Enable 0 = Disable Attempt DTMF dial, then fall back to pulse dialing if unsuccessful. First digit is dialed as DTMF. If a dialtone is still present after two seconds, the Si2456/33/14 will redial the first digit and remaining digits as pulse. If a dialtone is not present after two seconds, the Si2456/33/14 will dial the remaining digits as DTMF. 5:2 Reserved 1 HDLC Synchronous Mode.* 0 = Normal asynchronous mode. 1 = Transparent HDLC mode. 0 FAST Fast Connect.* 0 = Normal modem handshake timing per ITU/Bellcore standards. 1 = Fast connect modem handshake timing. Read returns to zero. Read returns to zero. *Note: When V22HD, HDLC, or FAST bits are set, \N0 (wire mode) must be used. 60 Rev. 1.2 Si2456/33/14 U7C GENC Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name RIGPO RIGPOEN Type R R/W Reset settings = 0x0000 Bit 15:5 4 3:1 0 Name Reserved RIGPO Function Reads returns to zero. RI. RI (pin 15), follows this bit when RIGPIOEN = 1b. Reserved Reads returns to zero. RIGPOEN 0 = RI indicates valid ring signal (Normal ring-indicator mode). 1 = RI (Pin 15) can be used as a general-purpose output and follows U7C[4] (RIGPO). Rev. 1.2 61 Si2456/33/14 U7D GEND Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name LVFE LLV AUSDC ATZD FDP Type R/W R/W R/W R/W R/W Reset settings = 0x0000 Bit 15:14 13 Name Reserved LVFE 12:11 10 Reserved LLV 9 AUSDC 8:2 1 Reserved ATZD 0 FDP Function Reads returns to zero. LVCS Filter Enable. 0 = Normal operation 1 = Enables optional filtering on LVCS to mitigate the effect of 50/60 Hz noise on tip/ring voltage. Read returns zero. 0 = Normal operation. 1 = Enables an optional algorithm for countries, such as Japan and Malaysia, with low loop voltage. Also set U67[3:2] (DCT) = 00b, U69[4] VOL = 1b, and U52 = 0x0002 before going offhook. When the modem goes off-hook, it samples LVCS and changes DCT and VOL as necessary to maximize transmit levels and optimize distortion. 0 = Normal operation. 1 = Causes the modem to go off-hook in Japan mode and then revert to FCC mode after 500 ms. This allows the modem to meet the Australian line seizure requirements while allowing the maximum transmit power (optional for Australia and when DCT = 01b). Reads returns to zero. ATZ Disable. 0 = ATZ functions normally. 1 = Disable ATZ command. This may be used to ensure modem settings are not lost in some systems. FSK Data Processing. 0 = FSK data processing stops when carrier is lost. 1 = FSK data processing continued for 2 bytes after carrier is lost. UAA V.29 Mode Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 Name V29EMA Type R/W Reset settings = 0x0000 Bit 15:2 1 Name Reserved V29ENA 0 Reserved 62 Function Read returns zero. 0 disables V.29. 1 enables V.29 Read returns zero. Rev. 1.2 D0 Si2456/33/14 7. Parallel Interface Registers Parallel Interface 0 (0x00) Bit D7 D6 D5 D4 D3 Name TX/RX Type R/W D2 D1 D0 Reset settings = 0x00 Bit Name Function 7:0 TX/RX Parallel Interface Transmit/Receive. This register functions similarly to the serial port TX pin on writes to the parallel port, and similarly to the serial port RX pin on reads from the parallel port. Rev. 1.2 63 Si2456/33/14 Parallel Interface 1 (0x01) Bit D7 D6 D5 D4 D3 D2 D1 D0 Name RXF TXE REM INTM INT ESC RTS CTS Type R R R R/W R R/W R/W R Reset settings = 0110_0011 Bit Name Function 7 RXF Receive FIFO Almost Full (status). 0 = Receive FIFO (12 deep) contains three or more empty locations (RXF ≤ 9). The host can clear the RXF interrupt without emptying the RX FIFO by writing a 0 to the RXF bit. This will disable the RXF interrupt until the host has emptied the FIFO. 1 = Receive FIFO contains two or less empty locations (RXF ≥ 10). 6 TXE Transmit FIFO Almost Empty (status). 0 = Transmit FIFO (14 deep) contains three or more characters (TXF ≥ 3). 1 = Transmit FIFO contains two or less characters (TXF ≤ 2). TXE interrupt will not trigger if the CTS bit is inactive. Therefore, the host does not need to poll CTS while waiting for transmit FIFO to empty. TXE can be cleared by writing it to 0. 5 REM Receive FIFO Empty. 0 = Receive FIFO has valid data. 1 = Receive FIFO empty. Note: If the interim timer (see PTMR - U6F, bits 7:0) set by PTMR expires, it will cause an interrupt. This interrupt will not set RXF, TXE, or INT. The interrupt handler on the host should then verify that REM = 0 and begin to empty the receive FIFO (Parallel Interface 0 register) until REM = 1. 64 4 INTM Interrupt Mask. 0 = In parallel mode, the INT pin is triggered by a rising edge on RXF or TXE only (default). 1 = In parallel mode, the INT pin is triggered by a rising edge on RXF, TXE, or INT. 3 INT Interrupt. 0 = No interrupt has occurred. 1 = Indicates that an interrupt (CID, OCD, PPD, RI, or DCD from U70) has occurred. This bit is cleared via the AT:I command. 2 ESC Escape. Operation of this bit in parallel mode is functionally-equivalent to the ESC pin in serial mode. 1 RTS Request-to-Send. Operation of this bit in parallel mode is functionally equivalent to the RTS pin in serial mode. Use of the CTS and RTS bits (as opposed to the TXE and RXF bits) allows the flow control between the host and the Si2456/33/14 to operate 1 byte at a time rather than in blocks. 0 CTS Clear-to-Send. Operation of this bit in parallel mode is functionally-equivalent to the CTS pin in serial mode. Use of the CTS and RTS bits (as opposed to the TXE and RXF bits) allows the flow control between the host and the Si2456/33/14 to operate 1 byte at a time, rather than in blocks. Rev. 1.2 Si2456/33/14 8. Pin Descriptions: Si2456/33/14 CLKIN/XTALI 1 24 EECLK/D5 XTALO 2 23 DCD/D4 CLKOUT/EECS/AO 3 22 ESC/D3 D6 4 21 C1A VD3.3 5 6 20 19 ISOB GND VDA 7 18 GND RTS/D7 8 17 VDB RXD/RD 9 16 EESD/D2 TXD/WR 10 15 RI/D1 CTS/CS 11 14 INT/DO 12 13 AOUT/INT RESET VD3.3 Pin # Pin Name Description 1 CLKIN/XTALI Clock Input/Crystal Oscillator Pin. This pin provides support for parallel-resonant, AT-cut crystals. XTALI also acts as an input in the event that an external clock source is used in place of a crystal. A 4.9152 MHz crystal or 4.9152 MHz clock is required. 2 XTALO Crystal Oscillator Pin. This pin provides support for parallel-resonant AT-cut crystals. XTALO serves as the output of the crystal amplifier. 3 CLKOUT/EECS/A0 Clock Output/EEPROM Chip Select/Address Bit 0. Clock output in serial mode. Active low read/write enable for SPI EEPROM in serial mode when pin 4 is pulled low during powerup. Address Enable in parallel mode. 4 D6 Data Bit. Bidirectional parallel bus data bit 6 in parallel mode. 5, 19 VD3.3 Digital Supply Voltage. Provides the 3.3 V digital supply voltage to the Si2456/33/14. 6, 18 GND Ground. Connects to the system digital ground. 7,17 VDA, VDB 8 RTS/D7 Request-to-Send/Data Bit. Request-to-send (for flow control) in serial mode. Bidirectional parallel bus data bit 7 in parallel mode. 9 RXD/RD Receive Data/Read Enable. Data output to DTE RXD pin in serial mode. Active low read enable pin in parallel mode. Digital Rail. Pin provides decoupling for the internal power supplies. Rev. 1.2 65 Si2456/33/14 Pin # Pin Name Description 10 TXD/WR Transmit Data/Write Enable. Data input from DTE TXD pin in serial mode. Active low write-enable pin in parallel mode. 11 CTS/CS Clear-to-Send/Chip Select. Active low clear-to-send (for flow control) in serial mode. Active low chip select in parallel mode. 12 RESET Reset Input. An active low input that is used to reset all control registers to a defined initialized state. 13 AOUT/INT 14 INT/D0 Interrupt Output/Data Bit. Active low interrupt output in serial mode. Bidirectional parallel bus data bit 0 in parallel mode. 15 RI/D1 Ring Indicator/Data Bit. The RI on (active low) indicates the presence of an ON segment of a ring signal on the telephone line. Bidirectional parallel bus data bit 1 in parallel mode. 16 EESD/D2 EEPROM Serial Data Input/Output/Data Bit. Bidirectional Input/Output to SPI EEPROM in serial mode. Bidirectional parallel bus data bit 2 in parallel mode. 20 ISOB Bias Voltage. This pin provides decoupling for the power supply. 21 C1A Isolation Capacitor 1A. Connects to one side of the isolation capacitor, C1. 22 ESC/D3 Escape/Data Bit. Hardware escape in serial mode. Bidirectional parallel bus data bit 3 in parallel mode. 23 DCD/D4 Carrier Detect/Data Bit. Active low-carrier detect in serial mode. Bidirectional parallel bus data bit 4 in parallel mode. 24 EECLK/D5 EEPROM Clock/Data Bit. Clock output for SPI EEPROM in serial mode. Bidirectional parallel bus data bit 5 in parallel mode. 66 Analog Output/Interrupt Output. Analog output in serial mode. Active low interrupt output in parallel mode. Rev. 1.2 Si2456/33/14 9. Pin Descriptions: Si3015 QE2 DCT IGND C1B RNG1 RNG2 QB QE 1 2 3 4 5 6 7 8 16 15 FILT2 FILT 14 13 RX REXT 12 11 REF 10 9 VREG2 VREG REXT2 Pin # Pin Name Description 1 QE2 Transistor Emitter 2. Connects to the emitter of Q4. 2 DCT DC Termination. Provides dc termination to the telephone network. 3 IGND Isolated Ground. Connects to ground on the line-side interface. Also connects to capacitor C2. 4 C1B Isolation Capacitor 1B. Connects to one side of isolation capacitor C1. 5 RNG1 Ring 1. Connects through a capacitor to the TIP lead of the telephone line. Provides the ring and caller ID signals to the modem. 6 RNG2 Ring 2. Connects through a capacitor to the RING lead of the telephone line. Provides the ring and caller ID signals to the modem. 7 QB Transistor Base. Connects to the base of transistor Q3. 8 QE Transistor Emitter. Connects to the emitter of transistor Q3. 9 VREG Voltage Regulator. Connects to an external capacitor to provide bypassing for an internal power supply. 10 VREG2 Voltage Regulator 2. Connects to an external capacitor to provide bypassing for an internal power supply. 11 REF 12 REXT2 External Resistor 2. Sets the complex ac termination impedance. 13 REXT External Resistor. Sets the real ac termination impedance. Reference. Connects to an external resistor to provide a high-accuracy reference current. Rev. 1.2 67 Si2456/33/14 Pin # Pin Name 14 RX Receive Input. Serves as the receive side input from the telephone network. 15 FILT Filter. Provides filtering for the dc termination circuits. 16 FILT2 Filter 2. Provides filtering for the bias circuits. 68 Description Rev. 1.2 Si2456/33/14 10. Ordering Guide Chipset Description System-Side Line-Side Temperature Si2456 Commercial Si2456-KT Si3015-KS 0 to 70 °C Si2456 Commercial lead-free Si2456-FT Si3015-F-FS 0 to 70 °C Si2456 Industrial Si2456-BT Si3015-BS –40 to 85 °C Si2433 Commercial Si2433-KT Si3015-KS 0 to 70 °C Si2433 Commercial lead-free Si2433-FT Si3015-F-FS 0 to 70 °C Si2433 Industrial Si2433-BT Si3015-BS –40 to 85 °C Si2414 Commercial Si2414-KT Si3015-KS 0 to 70 °C Si2414 Commercial lead-free Si2414-FT Si3015-F-FS 0 to 70 °C Si2414 Industrial Si2414-BT Si3015-BS –40 to 85 °C Rev. 1.2 69 Si2456/33/14 11. Package Outline: 24-Pin TSSOP Figure 8 illustrates the package details for the Si2456/33/14. Table 16 lists the values for the dimensions shown in the illustration. E H θ L B D A e A1 γ C Approximate device weight is 115.7 mg. Figure 8. 24-Pin Thin Shrink Small Outline Package (TSSOP) Table 16. Package Diagram Dimensions Millimeters Symbol Min Max Typical* A — 1.20 3 A1 0.05 0.15 3 B 0.19 0.30 C 0.09 0.20 D 7.70 7.90 E 4.30 4.50 e 0.65 BSC H 6.40 BSC L 0.45 0.75 θ 0° 8° γ 3 3 0.10 *Note: To guarantee coplanarity (γ), the parameters marked “Typical” may be exceeded. 70 Rev. 1.2 Si2456/33/14 12. Package Outline: 16-Pin SOIC Figure 9 illustrates the package details for the Si3015. Table 17 lists the values for the dimensions shown in the illustration. 16 9 h E H 0.010 θ 1 8 B GAUGE PLANE L Detail F D C A e A1 See Detail F γ Seating Plane Figure 9. 16-pin Small Outline Integrated Circuit (SOIC) Package Table 17. Package Diagram Dimensions A Millimeters Min Max 1.35 1.75 A1 .10 .25 B .33 .51 C .19 .25 D 9.80 10.00 E 3.80 4.00 e 1.27 BSC — H 5.80 6.20 Symbol h .25 .50 L .40 1.27 γ — 0.10 θ 0º 8º Typical* 3 3 3 3 *Note: Typical parameters are for information purposes only. Rev. 1.2 71 Si2456/33/14 DOCUMENT CHANGE LIST Revision 1.0 to Revision 1.1 Updated "Functional Block Diagram" on page 1. Updated Table 6 on page 8. Expanded +GCI country codes in Table 8 on page 22. Updated S-registers S43 and S44 in Table 14 on page 41. Added U-register “UAA V.29 Mode” on page 62. Updated default register values for U66. Updated U-register U7D. Revision 1.1 to Revision 1.2 Updated "Ordering Guide" on page 69. 72 Rev. 1.2 Si2456/33/14 NOTES: Rev. 1.2 73 Si2456/33/14 CONTACT INFORMATION Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: ISOinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and ISOmodem are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 74 Rev. 1.2