Si3056
Si 3 0 1 8 / 1 9 /10
G LO BAL S E R I A L I N T E R FA C E D IR EC T A C C E S S A R R A N G E M E N T
Features
Complete DAA includes the following:
Programmable line interface
AC termination
DC termination
Ring detect threshold
Ringer impedance
80 dB dynamic range TX/RX paths
Integrated codec and 2- to 4-wire
hybrid
Integrated ring detector
Type I and II caller ID support
Line voltage monitor
Loop current monitor
Polarity reversal detection
Programmable digital gain
Clock generation
Pulse dialing support
Overload detection
3.3 V power supply
Direct interface to DSPs
Serial interface control for up to eight
devices
>5000 V isolation
Proprietary isolation technology
Parallel handset detection
+3.2 dBm TX/RX level mode
Programmable digital hybrid for nearend echo reduction
Low-profile SOIC packages
Lead-free/RoHS-compliant packages
available
Applications
V.92 modems
Set-top boxes
Voice mail systems
Fax machines
Multi-function printers
Internet appliances
Personal digital
assistants
Description
The Si3056 is an integrated direct access arrangement (DAA) with a
programmable line interface to meet global telephone line requirements. Available
in two 16-pin small outline packages, it eliminates the need for an analog front end
(AFE), isolation transformer, relays, opto-isolators, and a 2- to 4-wire hybrid. The
Si3056 dramatically reduces the number of discrete components and cost
required to achieve compliance with global regulatory requirements. The Si3056
interfaces directly to standard modem DSPs.
Functional Block Diagram
Si3056
MCLK
SCLK
FSYNC
SDI
SDO
FC/RGDT
Si3018/19/10
RX
Digital
Interface
Hybrid and
dc
Termination
Isolation
Interface
RGDT/FSD/M1
OFHK
M0
RESET
AOUT/INT
Control
Interface
Isolation
Interface
Ring Detect
Off-Hook
IB
SC
DCT
VREG
VREG2
DCT2
DCT3
Ordering Information
See page 87.
Pin Assignments
Si3056
MCLK
1
16
OFHK
FSYNC
2
15
SCLK
3
4
14
13
RGDT/FSD/M1
M0
12
SDI
5
6
11
AOUT/INT
FC/RGDT
RESET
7
8
10
9
C1A
C2A
VD
SDO
VA
GND
Si3018/19/10
QE
1
16
DCT2
DCT
RX
IB
2
15
IGND
3
4
14
13
DCT3
C1B
C2B
5
6
12
QB
QE2
11
SC
VREG
7
8
10
9
VREG2
RNG2
RNG1
US Patent # 5,870,046
US Patent # 6,061,009
Other Patents Pending
RNG1
RNG2
QB
QE
QE2
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TA B L E O F C O N T E N T S
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4. AOUT PWM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1. Upgrading from the Si3034/35/44 to Si3056 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2. Line-Side Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.3. Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.4. Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
5.5. Isolation Barrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.6. Transmit/Receive Full Scale Level (Si3019 Line-Side Only) . . . . . . . . . . . . . . . . . . . 25
5.7. Parallel Handset Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.8. Line Voltage/Loop Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.9. Off-Hook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.10. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.11. DC Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.12. AC Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.13. Transhybrid Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.14. Ring Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.15. Ring Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
5.16. Ringer Impedance and Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.17. Pulse Dialing and Spark Quenching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.18. Billing Tone Protection and Receive Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.19. Billing Tone Filter (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.20. On-Hook Line Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.21. Caller ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.22. Overload Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
5.23. Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
5.24. Filter Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
5.25. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.26. Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
5.27. Multiple Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
5.28. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.29. Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
5.30. In-Circuit Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.31. Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
5.32. Revision Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
7. Pin Descriptions: Si3056 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
8. Pin Descriptions: Si3018/19/10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
9. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
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10. Evaluation Board Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11. Package Outline: 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Appendix—UL1950 3rd Edition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Silicon Laboratories Si3056 Support Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
4
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Si3056 Si3018/19/10
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter1
Symbol
Test Condition
Min2
Typ
Max2
Unit
Ambient Temperature
TA
F and K-Grade
0
25
70
°C
Si3056 Supply Voltage, Digital3
VD
3.0
3.3
3.6
V
Notes:
1. The Si3056 specifications are guaranteed when the typical application circuit (including component tolerance) and the
Si3056 and any Si3018 or Si3019 are used. See Figure 17 on page 18 for typical application schematic.
2. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
3. 3.3 V applies to both the digital and serial interface and the digital signals RGDT/FSD, OFHK, RESET, M0, and M.
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Table 2. Loop Characteristics
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C, see Figure 1)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
DC Termination Voltage
VTR
IL = 20 mA, MINI = 11,
ILIM = 0, DCV = 00, DCR = 0
—
—
6.0
V
DC Termination Voltage
VTR
IL = 120 mA, MINI = 11,
ILIM = 0, DCV = 00, DCR = 0
9
—
—
V
DC Termination Voltage
VTR
IL = 20 mA, MINI = 00,
ILIM = 0, DCV = 11, DCR = 0
—
—
7.5
V
DC Termination Voltage
VTR
IL = 120 mA, MINI = 00,
ILIM = 0, DCV = 11, DCR = 0
9
—
—
V
DC Termination Voltage
VTR
IL = 20 mA, MINI = 00,
ILIM = 1, DCV = 11, DCR = 0
—
—
7.5
V
DC Termination Voltage
VTR
IL = 60 mA, MINI = 00,
ILIM = 1, DCV = 11, DCR = 0
40
—
—
V
DC Termination Voltage
VTR
IL = 50 mA, MINI = 00,
ILIM = 1, DCV = 11, DCR = 0
—
—
40
V
On Hook Leakage Current
ILK
VTR = –48 V
—
—
5
µA
Operating Loop Current
ILP
MINI = 00, ILIM = 0
10
—
120
mA
Operating Loop Current
ILP
MINI = 00, ILIM = 1
10
—
60
mA
DC current flowing through ring
detection circuitry
—
1.5
3
µA
DC Ring Current
Ring Detect Voltage*
VRD
RT = 0
13.5
15
16.5
Vrms
Ring Detect Voltage*
VRD
RT = 1
19.35
21.5
23.65
Vrms
FR
13
—
68
Hz
REN
—
—
0.2
Ring Frequency
Ringer Equivalence Number
*Note: The ring signal is guaranteed to not be detected below the minimum. The ring signal is guaranteed to be detected
above the maximum.
TIP
+
600
Si3018
IL
VTR
10 F
RING
–
Figure 1. Test Circuit for Loop Characteristics
6
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Table 3. DC Characteristics, VD = 3.3 V
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
High Level Input Voltage
VIH
2.4
—
—
V
Low Level Input Voltage
VIL
—
—
0.8
V
High Level Output Voltage
VOH
IO = –2 mA
2.4
—
—
V
Low Level Output Voltage
VOL
IO = 2 mA
—
—
0.35
V
–10
—
10
µA
Input Leakage Current
IL
Power Supply Current, Digital1
ID
VD pin
—
15
—
mA
ID
PDN = 1, PDL = 0
—
9
—
mA
ID
PDN = 1, PDL = 1
—
1
—
mA
Total Supply Current, Sleep Mode1
Total Supply Current, Deep Sleep
1,2
Notes:
1. All inputs at 0.4 or VD – 0.4 (CMOS levels). All inputs are held static except clock and all outputs unloaded
(Static IOUT = 0 mA).
2. RGDT is not functional in this state.
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Table 4. AC Characteristics
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C; see Figure 17 on page 18)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Fs
Fs = FPLL2/5120
7.2
—
16
kHz
FPLL1
FPLL1 = (FMCLK x M)/N
—
98.304
—
MHz
Transmit Frequency Response
Low –3 dBFS Corner
—
0
—
Hz
Receive Frequency Response
Low –3 dBFS Corner,
FILT = 0
—
5
—
Hz
Receive Frequency Response
Low –3 dBFS Corner,
FILT = 111
—
200
—
Hz
FULL = 0 (0 dBm)
—
1.1
—
VPEAK
FULL = 111(3.2 dBm)
—
1.58
—
VPEAK
FULL2 = 1 (6.0 dBm)
—
2.16
—
VPEAK
Sample Rate1
PLL Output Clock
Frequency1
Transmit Full Scale Level2,3
Receive Full Scale Level2,4
VFS
VFS
FULL = 0 (0 dBm)
1.1
VPEAK
11
FULL = 1 (3.2 dBm)
—
1.58
—
VPEAK
FULL2 = 1 (6.0 dBm)
—
2.16
—
VPEAK
5,6,7
DR
ILIM = 0, DCV = 11, DCR = 0,
IL = 100 mA, MINI = 00
—
80
—
dB
Dynamic Range5,6,7
DR
ILIM = 0, DCV = 00, DCR = 0,
IL = 20 mA, MINI = 11
—
80
—
dB
Dynamic Range5,6,7
DR
ILIM = 1, DCV = 11, DCR = 0,
IL = 50 mA, MINI = 00
—
80
—
dB
Transmit Total Harmonic Distortion8,9
THD
ILIM = 0, DCV = 11, DCR = 0,
IL = 100 mA, MINI = 00
—
–72
—
dB
Transmit Total Harmonic Distortion8,9
THD
ILIM = 0, DCV = 00, DCR = 0,
IL = 20 mA, MINI = 11
—
–78
—
dB
Dynamic Range
Notes:
1. See Figure 26 on page 37.
2. Measured at TIP and RING with 600 termination at 1 kHz, as shown in Figure 1.
3. With FULL = 1, the transmit and receive full scale level of +3.2 dBm can be achieved with a 600 ac termination, while
the transmit and receive level in dBm varies with reference impedance, the DAA will transmit and receive 1 dBV into all
reference impedances in “FULL” mode. With FULL2 = 1, the transmit and receive full scale level of +6.0 dBm can be
achieved with a 600 ac termination. In “FULL2” mode, the DAA will transmit and receive +1.5 dBV into all reference
impedances.
4. Receive full scale level produces –0.9 dBFS at SDO.
5. DR = 20 x log (RMS VFS/RMS VIN).+ 20 x log (RMS VIN/RMS noise). The RMS noise measurement excludes
harmonics. VFS is the 0 dBm full-scale level.
6. Measurement is 300 to 3400 Hz. Applies to both transmit and receive paths. VIN = 1 kHz, –3 dBFS, Fs = 10300 Hz.
7. When using the Si3010 line-side, the typical DR values will be approximately 10 dB lower.
8. THD = 20 x log (RMS distortion/RMS signal). VIN = 1 kHz, –3 dBFS, Fs = 10300 Hz.
9. When using the Si3010 line-side, the typical THD values will be approximately 10 dB higher.
10. DRCID = 20 x log (RMS VCID/RMS VIN) + 20 x log(RMS VIN/RMS noise). VCID is the 6 V full-scale level for the typical
application circuit in Figure 17. With the enhanced CID circuit, the VCID full-scale level is 1.5 V peak, and DRCID
increases to 62 dB.
11. Available on the Si3019 line-side device only.
8
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Table 4. AC Characteristics (Continued)
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C; see Figure 17 on page 18)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Receive Total Harmonic Distortion8,9
THD
ILIM = 0, DCV = 00, DCR = 0,
IL = 20 mA, MINI = 11
—
–78
—
dB
Receive Total Harmonic Distortion8,9
THD
ILIM = 1, DCV = 11, DCR = 0,
IL = 50 mA, MINI = 00
—
–78
—
dB
DRCID
VIN = 1 kHz, –13 dBFS
—
50
—
dB
—
6
—
VPEAK
AOUT Low Level Current
—
—
10
mA
AOUT High Level Current
—
—
10
mA
Dynamic Range (caller ID
mode)10,7
Caller ID Full Scale Level10
VCID
Notes:
1. See Figure 26 on page 37.
2. Measured at TIP and RING with 600 termination at 1 kHz, as shown in Figure 1.
3. With FULL = 1, the transmit and receive full scale level of +3.2 dBm can be achieved with a 600 ac termination, while
the transmit and receive level in dBm varies with reference impedance, the DAA will transmit and receive 1 dBV into all
reference impedances in “FULL” mode. With FULL2 = 1, the transmit and receive full scale level of +6.0 dBm can be
achieved with a 600 ac termination. In “FULL2” mode, the DAA will transmit and receive +1.5 dBV into all reference
impedances.
4. Receive full scale level produces –0.9 dBFS at SDO.
5. DR = 20 x log (RMS VFS/RMS VIN).+ 20 x log (RMS VIN/RMS noise). The RMS noise measurement excludes
harmonics. VFS is the 0 dBm full-scale level.
6. Measurement is 300 to 3400 Hz. Applies to both transmit and receive paths. VIN = 1 kHz, –3 dBFS, Fs = 10300 Hz.
7. When using the Si3010 line-side, the typical DR values will be approximately 10 dB lower.
8. THD = 20 x log (RMS distortion/RMS signal). VIN = 1 kHz, –3 dBFS, Fs = 10300 Hz.
9. When using the Si3010 line-side, the typical THD values will be approximately 10 dB higher.
10. DRCID = 20 x log (RMS VCID/RMS VIN) + 20 x log(RMS VIN/RMS noise). VCID is the 6 V full-scale level for the typical
application circuit in Figure 17. With the enhanced CID circuit, the VCID full-scale level is 1.5 V peak, and DRCID
increases to 62 dB.
11. Available on the Si3019 line-side device only.
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Table 5. Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
DC Supply Voltage
VD
–0.5 to 3.6
V
Input Current, Si3056 Digital Input Pins
IIN
±10
mA
VIND
–0.3 to (VD + 0.3)
V
TA
–40 to 100
°C
TSTG
–65 to 150
°C
Digital Input Voltage
Operating Temperature Range
Storage Temperature Range
Note: Permanent device damage can occur if the above absolute maximum ratings are exceeded. Restrict functional
operation to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods might affect device reliability.
Table 6. Switching Characteristics—General Inputs
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C, CL = 20 pF)
Symbol
Min
Typ
Max
Unit
Cycle Time, MCLK
tmc
16.67
—
1000
ns
MCLK Duty Cycle
tdty
40
50
60
%
MCLK Jitter Tolerance
tjitter
—
—
±2
ns
Rise Time, MCLK
tr
—
—
5
ns
Fall Time, MCLK
tf
—
—
5
ns
tmr
10
—
—
cycles
trl
250
—
—
ns
tmxr
20
—
—
ns
Parameter1
MCLK Before RESET
RESET Pulse
Width2
M0, M Before RESET3
Notes:
1. All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are
VIH = VD – 0.4 V, VIL = 0.4 V. Rise and fall times are referenced to the 20% and 80% levels of the waveform.
2. The minimum RESET pulse width is the greater of 250 ns or 10 MCLK cycle times.
3. M0 and M are typically connected to VD or GND and should not be changed during normal operation.
tm c
tr
M CLK
tf
V IH
V IL
tm r
RESET
t rl
M 0, M1
t m xr
Figure 2. General Inputs Timing Diagram
10
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Table 7. Switching Characteristics—Serial Interface (Master Mode, DCE = 0)
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C, CL = 20 pF)
Parameter
Symbol
Min
Typ
Max
Unit
Cycle time, SCLK
tc
244
1/256 Fs
—
ns
SCLK Duty Cycle
tdty
—
50
—
%
Delay Time, SCLKto FSYNC
td1
—
—
20
ns
Delay Time, SCLK to SDO Valid
td2
—
—
20
ns
Delay Time, SCLKto FSYNC
td3
—
—
20
ns
Setup Time, SDI Before SCLK
tsu
25
—
—
ns
Hold Time, SDI After SCLK
th
20
—
—
ns
Setup Time, FC Before SCLK
tsfc
40
—
—
ns
Hold time, FC After SCLK
thfc
40
—
—
ns
Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VD – 0.4 V, VIL = 0.4 V.
SCLK
tc
VOH
VOL
td1
td3
FSYNC
(mode 0)
FSYNC
(mode 1)
16-Bit
SDO
td3
td2
D15
D14
tsu
16-Bit
SDI
D15
D1
D0
D0
D1
D0
th
D14
tsfc
thfc
FC
Figure 3. Serial Interface Timing Diagram (DCE = 0)
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Table 8. Switching Characteristics—Serial Interface (Master Mode, DCE = 1, FSD = 0)
(VA = Charge Pump, VD = 3.0 to 3.6 V, TA = 0 to 70 °C, CL = 20 pF)
Symbol
Min
Typ
Max
Unit
Cycle Time, SCLK
tc
244
1/256 Fs
—
ns
SCLK Duty Cycle
tdty
—
50
—
%
Delay Time, SCLKto FSYNC
td1
—
—
20
ns
Delay Time, SCLKto FSYNC
td2
—
—
20
ns
Delay Time, SCLK to SDO valid
td3
—
—
20
ns
Delay Time, SCLK to SDO Hi-Z
td4
—
—
20
ns
Delay Time, SCLK to FSD
td5
—
—
20
ns
Delay Time, SCLK to FSD
td6
—
—
20
ns
Setup Time, SDO Before SCLK
tsu
25
—
—
ns
Hold Time, SDO After SCLK
th
20
—
—
ns
Parameter1,2
Notes:
1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VD – 0.4 V, VIL = 0.4 V.
2. See "5.27.Multiple Device Support" on page 38 for functional details.
32 SCLKs
16 SCLKs
tc
16 SCLKs
SCLK
td1
td2
td2
FSYNC
(mode 1)
td2
td6
td2
FSYNC
(mode 0)
td3
SDO
(master)
tsu
D15
th
D14
td4
D13
D0
td3
SDO
(slave 1)
D15
td5
FSYNC
(Mode 0)
td5
FSYNC
(Mode 1)
tsu
SDI
D15
th
D14
D13
D0
Figure 4. Serial Interface Timing Diagram (DCE = 1, FSD = 0)
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Table 9. Switching Characteristics—Serial Interface (Master Mode, DCE = 1, FSD = 1)
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C, CL = 20 pF)
Symbol
Min
Typ
Max
Unit
Cycle Time, SCLK
tc
244
1/256 Fs
—
ns
SCLK Duty Cycle
tdty
—
50
—
%
Delay Time, SCLKto FSYNC
td1
—
—
20
ns
Delay Time, SCLKto FSYNC
td2
—
—
20
ns
Delay Time, SCLK to SDO Valid
td3
—
—
20
ns
Delay Time, SCLK to SDO Hi-Z
td4
—
—
20
ns
Delay Time, SCLK to FSD
td5
—
—
20
ns
Setup Time, SDO Before SCLK
tsu
25
—
—
ns
Hold Time, SDO After SCLK
th
20
—
—
ns
Parameter1, 2
Notes:
1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VD – 0.4 V, VIL = 0.4 V.
2. See "5.27.Multiple Device Support" on page 38 for functional details.
tc
SCLK
td1
td2
FSYNC
(mode 1)
SDO
(master)
td3
tsu
th
D15
D14
td4
D13
D0
td3
SDO
(slave 1)
D15
td5
FSD
tsu
SDI
D15
th
D14
D1
D0
Figure 5. Serial Interface Timing Diagram (DCE = 1, FSD = 1)
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Table 10. Switching Characteristics—Serial Interface (Slave Mode, DCE = 1, FSD = 1)
(VA = Charge Pump, VD = 3.0 to 3.6 V, TA = 0 to 70 °C, CL = 20 pF)
Parameter
Symbol
Min
Typ
Max
Unit
tc
244
1/256 Fs
—
ns
Setup Time, FSYNC before MCLK*
tsu1
—
—
20
ns
Delay Time, FSYNC after MCLK*
td1
—
—
20
ns
Setup Time, SDI before MCLK
tsu3
—
—
20
ns
Hold Time, SDI After MCLK
th2
—
—
20
ns
Delay Time, MCLK to SDO
td3
—
—
20
ns
Delay Time, MCLK to FSYNC
td1
—
—
20
ns
Delay Time, MCLK to FSYNC
td2
—
—
20
ns
Cycle Time, MCLK
*Note: Tsu1 and Th1 are listed for applications where the controller drives the MCLK and FSYNC instead of a master DAA.
tC
MCLK
td1
tSU1
th1
td1
FSYNC
(mode 1)
FSYNC
(mode 0)
td2
tsu3 th2
SDI
D15
D14
D0
D15
D14
D0
td3
SDO
Figure 6. Serial Interface Timing Diagram (Slave Mode, DCE = 1, FSD = 1)
14
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Table 11. Digital FIR Filter Characteristics—Transmit and Receive
(VD = 3.0 to 3.6 V, Sample Rate = 8 kHz, TA = 0 to 70 °C)
Parameter
Symbol
Min
Typ
Max
Unit
Passband (0.1 dB)
F(0.1 dB)
0
—
3.3
kHz
F(3 dB)
0
—
3.6
kHz
–0.1
—
0.1
dB
—
4.4
—
kHz
–74
—
—
dB
—
12/Fs
—
s
Passband (3 dB)
Passband Ripple Peak-to-Peak
Stopband
Stopband Attenuation
Group Delay
tgd
Note: Typical FIR filter characteristics for Fs = 8000 Hz are shown in Figures 7, 8, 9, and 10.
Table 12. Digital IIR Filter Characteristics—Transmit and Receive
(VD = 3.0 to 3.6 V, Sample Rate = 8 kHz, TA = 0 to 70 °C)
Parameter
Passband (3 dB)
Symbol
Min
Typ
Max
Unit
F(3 dB)
0
—
3.6
kHz
–0.2
—
0.2
dB
—
4.4
—
kHz
–40
—
—
dB
—
1.6/Fs
—
s
Passband Ripple Peak-to-Peak
Stopband
Stopband Attenuation
Group Delay
tgd
Note: Typical IIR filter characteristics for Fs = 8000 Hz are shown in Figures 11, 12, 13, and 14. Figures 15 and 16 show
group delay versus input frequency.
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Figure 7. FIR Receive Filter Response
Figure 9. FIR Transmit Filter Response
Figure 8. FIR Receive Filter Passband Ripple
Figure 10. FIR Transmit Filter Passband Ripple
For Figures 7–10, all filter plots apply to a sample rate of Fs = 8 kHz.
16
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Figure 11. IIR Receive Filter Response
Figure 14. IIR Transmit Filter Passband Ripple
Figure 12. IIR Receive Filter Passband Ripple
Figure 15. IIR Receive Group Delay
Figure 13. IIR Transmit Filter Response
Figure 16. IIR Transmit Group Delay
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AOUT
SDO
SDI
FC
RESETb
MCLK
FSYNCb
SCLK
M0
RGDTb
OFHKb
C50
Decoupling cap for
U1 VD
VD
R53
VD
1
2
3
4
5
6
7
8
R51
U1
MCLK
FSYNC
SCLK
VD
SDO
SDI
FC/RGDT
RESET
R52
Si3056
16
15
14
13
12
11
10
9
C51
R13
R12
C2
C1
R9
C5
R1
1
2
3
4
5
6
7
8
Si3018/19/10
Si3018/19
QE
DCT2
DCT
IGND
RX
DCT3
IB
QB
C1B
QE2
C2B
SC
VREG VREG2
RNG1 RNG2
U2
R33
R8
C6
R2
R31
R7
Optional CID Enhancement
16
15
14
13
12
11
10
9
R3
R30
C30
C31
R32
Q5
R11
Q4
R4
D1
D2
C3
C7
R5
Z1
Q1
Figure 17. Typical Application Circuit for the Si3056 and Si3018/19/10
(Refer to AN67 for recommended layout guidelines)
Decoupling cap for
U1 VA
OFHK
RGDT/FSD/M1
M0
VA
GND
AOUT/INT
C1A
C2A
C4
+
R10
No Ground Plane In DAA Section
FB1
FB2
Q2
Q3
R6
C10
C8
C9
R15
R16
RV1
TIP
RING
Si3056 Si3018/19/10
2. Typical Application Schematic
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3. Bill of Materials
Component(s)
C1, C2
C31
C4
C5, C6, C50, C51
C7
C8, C9
C10
C30, C312
D1, D23
FB1, FB2
Q1, Q3
Q2
Q4, Q5
RV1
R1
R2
R3
R4
R5, R6
R7, R83
R9
R10
R11
R12, R13
R15, R164
R30, R322
R31, R332
R51, R52
U1
U2
Z1
Value
33 pF, Y2, X7R, 20%
10 nF, 250 V, X7R, ±10%
1.0 µF, 50 V, Elec/Tant, ±20%
0.1 µF, 16 V, X7R, ±20%
2.7 nF, 50 V, X7R, 20%
680 pF, Y2, X7R, ±10%
0.01 µF, 16 V, X7R, ±20%
Not installed, 120 pF, 250V, X7R, ±10%
MMBD3004S-7-T
(VRRM = 350 V and IF = 0.225 mA)
Ferrite Bead, BLM18AG601SN1B
NPN, 300 V, MMBTA42
PNP, 300 V, MMBTA92
NPN, 60 V, 330 mW, MMBTA06
Sidactor, 275 V, 100 A
1.07 k, 1/2 W, 1%
150 , 1/16 W, 5%
3.65 k, 1/2 W, 1%
2.49 k, 1/2 W, 1%
100 k, 1/16 W, 5%
20 M, 1/16 W, 5%
1 M, 1/16 W, 1%
536 , 1/4 W, 1%
73.2 , 1/2 W, 1%
56.2 , 1/16 W, 1%
0 , 1/16 W
Not installed, 15 M, 1/8 W, 5%
Not installed, 5.1 M, 1/8 W, 5%
4.7 k, 1/10 W, 5%
Si3056
Si3018/19/10
Zener Diode, 43 V, 1/2 W, ZMM43
Supplier(s)
Panasonic, Murata, Vishay
Venkel, SMEC
Panasonic
Venkel, SMEC
Venkel, SMEC
Panasonic, Murata, Vishay
Venkel, SMEC
Venkel, SMEC
Diodes, Inc.
Murata
OnSemi, Fairchild
OnSemi, Fairchild
OnSemi, Fairchild
Teccor, Protek, ST Micro
Venkel, SMEC, Panasonic
Venkel, SMEC, Panasonic
Venkel, SMEC, Panasonic
Venkel, SMEC, Panasonic
Venkel, SMEC, Panasonic
Venkel, SMEC, Panasonic
Venkel, SMEC, Panasonic
Venkel, SMEC, Panasonic
Venkel, SMEC, Panasonic
Venkel, SMEC, Panasonic
Venkel, SMEC, Panasonic
Venkel, SMEC, Panasonic
Venkel, SMEC, Panasonic
Venkel, SMEC, Panasonic
Skyworks Solutions
Skyworks Solutions
General Semiconductor
Notes:
1. Value for C3 above is recommended for use with the Si3018. In voice appliations, a C3 value of 3.9 nF (250 V, X7R,
20%) is recommended to improve return loss performance.
2. C30-31 and R30-33 can be substitued for R7-8 to implent the enhanced caller ID circuit.
3. Several diode configurations are acceptable, with the main requirement being VRRM > 350 and IF > 225 mA, e.g., part
number HD04-T in a MiniDIP package by Diodes, Inc., two MMBD3004S-7-F diode pairs by Diodes, Inc. in an SOT-23
package, or four 1N4004 diodes.
4. Murata BLM18AG601SN1B may be substituted for R15-R16 (0 ) to decrease emissions.
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4. AOUT PWM Output
Figure 18 illustrates an optional circuit to support the pulse width modulation (PWM) output capability of the Si3056
for call progress monitoring purposes. Set the PWME bit (Register 1, bit 3) to enable this mode.
+5 VA
LS1
Q6
NPN
R41
AOUT
C41
Figure 18. AOUT PWM Circuit for Call Progress
Table 13. Component Values—AOUT PWM
Component
Value
Supplier
LS1
Speaker BRT1209PF-06
Intervox
Q6
NPN KSP13
Fairchild
C41
0.1 µF, 16 V, X7R, ±20%
Venkel, SMEC
R41
150 1/16 W, ±5%
Venkel, SMEC, Panasonic
Registers 20 and 21 allow the receive and transmit paths to be attenuated linearly. When these registers are set to
all 0s, the receive and transmit paths are muted. These registers affect the call progress output only and do not
affect transmit and receive operations on the telephone line.
The PWMM[1:0] bits (Register 1, bits 5:4) select one of the three different PWM output modes for the AOUT signal,
including a delta-sigma data stream, a conventional 32 kHz return to zero PWM output, and balanced 32 kHz PWM
output.
20
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5. Functional Description
The Si3056 is an integrated direct access arrangement
(DAA) that provides a programmable line interface to
meet global telephone line interface requirements. The
Si3056 implements Skyworks Solutions® patented
isolation technology and offers the highest level of
integration by replacing an analog front end (AFE), an
isolation transformer, relays, opto-isolators, and a 2- to
4-wire hybrid with two 16-pin packages.
The Si3056 DAA is software programmable to meet
global requirements and is compliant with FCC, TBR21,
JATE, and other country-specific PTT specifications as
shown in Table 16 on page 26. In addition, the Si3056
meets the most stringent worldwide requirements for
out-of-band energy, emissions, immunity, high-voltage
surges, and safety, including FCC Part 15 and 68,
EN55022, EN55024, and many other standards.
5.1. Upgrading from the Si3034/35/44 to
Si3056
The Si3056 offers Skyworks Solutions® customers
currently using Si3034/35/44 standard serial interface
DAA chipsets with an upgrade path for use in new
designs. The Si3056 digital interface is similar to the
Si3034/35/44 DAAs, thus the Si3056 retains the ability
to connect to many widely available DSPs. This also
allows customers to leverage software developed for
existing Si3034/35/44 designs. More importantly, the
Si3056 also offers a number of new features not
provided in the Si3034/35/44 DAAs. An overview of the
feature differences between the Si3044 and the Si3056
is presented in Table 14. Finally, the globally-compliant
Si3056 can be implemented with roughly half the
external components required in the already highly
integrated Si3034/35/44 DAA application circuits. The
following items have changed in the Si3056 as
compared to the Si3034/35/44 DAAs:
The pinout, the application circuit, and the bill of
materials. The Si3056 is not pin compatible with
Si3034/35/44 DAA chipsets.
New features have been added to the Si3056
including more ac terminations, a programmable
hybrid, finer gain/attenuation step resolution, finer
resolution loop current monitoring capability, ring
validation, more HW interrupts, a 200 Hz low
frequency filter pole. (See the appropriate functional
descriptions.)
The secondary communication data format (see
"5.26.Digital Interface" on page 37).
The low-power sleep mode, and system
requirements to support wake-on-ring. (See
"5.28.Power Management" on page 39.)
5.2. Line-Side Device Support
Three different line-side devices can be used with the
Si3056 system-side device:
Globally-compliant line-side device—Targets global
DAA requirements. Use the Si3018 global line-side
device for this configuration. This line-side device
supports both FCC-compliant countries and nonFCC-compliant countries.
Globally-compliant, enhanced features line-side
device—Targets embedded and voice applications
with global DAA requirements. Use the Si3019 lineside device for this configuration. The Si3019
contains all the features available on the Si3018,
plus the following additional features/enhancements:
Sixteen
selectable ac terminations to increase return
loss and trans-hybrid loss performance.
Higher transmit and receive level mode.
Selectable 200 Hz low frequency pole.
–16 to 13.5 dB digital gain/attenuation adjustment in
0.1 dB increments for the transmit and receive paths.
Programmable line current/voltage threshold interrupt.
Globally-compliant, low-speed only line-side
device—Targets embedded 2400 bps soft modem
applications. Use the Si3010 line-side device for this
configuration. The Si3010 contains all the features
available on the Si3018, except the transmit and
receive paths are optimized and tested only for
modem connect rates up to 2400 bps.
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Table 14. New Si3056 Features
Chipset
Si3044
System-Side Part #
Si3021
Line-Side Part #
Si3015
Si3010
Si3018
Si3019
Global DAA
Yes
Yes
Yes
Yes
Digital Interface
SSI
SSI
SSI
SSI
3.3 V or 5 V
3.3 V
3.3 V
3.3 V
56 kbps
2400 bps
56 kbps
56 kbps
Data Bus Width
16-bit
16-bit
16-bit
16-bit
Control Register Addressing
6-bit
8-bit
8-bit
8-bit
11.025 kHz
16 kHz
16 kHz
16 kHz
2
4
4
16
3 dB steps
3 dB steps
3 dB steps
0.1 dB steps
Loop Current Monitoring
3 mA/bit
1.1 mA/bit
1.1 mA/bit
1.1 mA/bit
Line Voltage Monitoring
2.75 V per bit
1 V per bit
1 V per bit
1 V per bit
Power Supply
Max Modem Connect Rate
Max Sampling Frequency
AC Terminations
Programmable Gain
Si3056
Polarity Reversal Detection
Yes (SW polling)
Yes (HW interrupt) Yes (HW interrupt) Yes (HW interrupt)
Line I/V Threshold Detection
No
No
No
Yes
Ring Qualification
No
Yes
Yes
Yes
Wake-on-Ring Support
Yes
Yes (MCLK active) Yes (MCLK active) Yes (MCLK active)
Ring detect only
7 HW interrupts
7 HW interrupts
8 HW interrupts
Integrated Fixed Analog
Hybrid
Yes
Yes
Yes
Yes
Programmable Digital Hybrid
No
Yes
Yes
Yes
+3.2 dBm
0 dBm
0 dBm
+3.2 dBm
HW Interrupts
Full Scale Transmit/Receive
Level
22
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Table 15. Country Specific Register Settings
Register
Country
Argentina
Australia4
Austria
Bahrain
Belgium
Brazil
Bulgaria
Canada
Chile
China5
Colombia
Croatia
Cyprus
Czech Republic
Denmark
Ecuador
Egypt
El Salvador
Finland
France
Germany
Greece
Guam
Hong Kong
Hungary
Iceland
India
Indonesia
Ireland
Israel
Italy
Japan
Jordan
Kazakhstan
Kuwait
Latvia
Note:
1.
2.
3.
4.
5.
6.
16
31
16
16
26
OHS
OHS2
RZ
RT
ILIM
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
0
0
0
0
1
1
1
1
0
1
0
1
1
1
1
0
0
1
1
0
0
1
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
0
0
0
0
1
1
1
1
0
1
0
1
1
1
1
0
0
1
1
0
0
1
1
1
0
0
0
0
1
26
26
DCV[1:0] MINI[1:0]
11
01
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
01
01
11
11
11
00
01
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
01
01
00
00
00
302
163
ACIM[3:0]
ACT
ACT2
0000
0011
0010
0010
0010
0000
0011
0000
0000
0000/1010
0000
0010
0010
0010
0010
0000
0010
0000
0010
0010
0010
0010
0000
0000
0010
0010
0000
0000
0010
0010
0010
0000
0000
0000
0000
0010
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
0
0
0
0
1
1
1
1
0
1
0
1
1
1
1
0
0
1
1
0
0
1
1
1
0
0
0
0
1
Supported for loop current 20 mA.
Available with Si3019 line-side only.
Available with Si3018 and Si3010 line-sides only.
See "5.11.DC Termination" on page 27 for DCV and MINI settings.
ACIM is 0000 for data applications and 1010 for voice applications.
For South Korea, set the TB3 bit in conjunction with the RZ bit. (See Register 59 description.)
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Table 15. Country Specific Register Settings (Continued)
Register
Country
Lebanon
Luxembourg
Macao
Malaysia1
Malta
Mexico
Morocco
Netherlands
New Zealand
Nigeria
Norway
Oman
Pakistan
Peru
Philippines
Poland
Portugal
Romania
Russia
Saudi Arabia
Singapore
Slovakia
Slovenia
South Africa
South Korea6
Spain
Sweden
Switzerland
Taiwan
TBR21
Thailand
UAE
United Kingdom
USA
Yemen
Note:
1.
2.
3.
4.
5.
6.
16
31
16
16
26
OHS
OHS2
RZ
RT
ILIM
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
1
1
0
1
1
0
0
0
0
1
1
1
0
0
0
1
1
0
0
1
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
1
1
0
1
1
0
0
0
0
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
0
1
0
0
26
26
DCV[1:0] MINI[1:0]
11
11
11
01
11
11
11
11
11
11
11
01
01
11
01
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
01
11
11
11
11
00
00
00
01
00
00
00
00
00
00
00
01
01
00
01
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
01
00
00
00
00
302
163
ACIM[3:0]
ACT
ACT2
0010
0010
0000
0000
0010
0000
0010
0010
0100
0010
0010
0000
0000
0000
0000
0010
0010
0010
0000
0000
0000
0010
0010
0011
0000
0010
0010
0010
0000
0010
0000
0000
0101
0000
0000
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
1
1
1
1
1
0
0
0
0
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
0
1
0
0
Supported for loop current 20 mA.
Available with Si3019 line-side only.
Available with Si3018 and Si3010 line-sides only.
See "5.11.DC Termination" on page 27 for DCV and MINI settings.
ACIM is 0000 for data applications and 1010 for voice applications.
For South Korea, set the TB3 bit in conjunction with the RZ bit. (See Register 59 description.)
24
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5.3. Power Supplies
The Si3056 system-side device operates from a 3.0–
3.6 V power supply. The Si3056 input pins are 5 V
tolerant. The Si3056 output pins only drive 3.3 V. The
line-side device derives its power from two sources: The
Si3056 and the telephone line. The Si3056 supplies
power over the patented isolation link between the two
devices, allowing the line-side device to communicate
with the Si3056 while on-hook and perform other onhook functions such as line voltage monitoring. When
off-hook, the line-side device also derives power from
the line current supplied from the telephone line. This
feature is exclusive to DAAs from Skyworks Solutions®
and allows the most cost-effective implementation for a
DAA while still maintaining robust performance over all
line conditions.
5.4. Initialization
When the Si3056 is powered up, assert the RESET pin.
When the RESET pin is deasserted, the registers have
default values. This reset condition guarantees the lineside device is powered down without the possibility of
loading the line (i.e., off-hook). An example initialization
procedure is outlined in the following list:
1. Program the PLL with registers 8 and 9 (N[7:0],
M[7:0]) to the appropriate divider ratios for the
supplied MCLK frequency and the sample rate in
register 7 (SRC), as defined in "5.25.Clock
Generation" on page 36.
2. Wait 1 ms until the PLL is locked.
3. Write a 00H into Register 6 to power up the line-side
device.
4. Set the required line interface parameters (i.e.,
DCV[1:0], MINI[1:0], ILIM, DCR, ACT and ACT2 or
ACIM[3:0], OHS, RT, RZ, ATX[2:0] or TGA2 and
TXG2) as defined by “Country Specific Register
Settings” shown in Table 15.
When this procedure is complete, the Si3056 is ready
for ring detection and off-hook.
5.5. Isolation Barrier
The Si3056 achieves an isolation barrier through lowcost, high-voltage capacitors in conjunction with
Skyworks Solutions® proprietary signal processing
techniques. These techniques eliminate signal
degradation from capacitor mismatches, common mode
interference, or noise coupling. As shown in Figure 17 on
page 18, the C1, C2, C8, and C9 capacitors isolate the
Si3056 (system-side) from the line-side device. Transmit,
receive, control, ring detect, and caller ID data are
passed across this barrier. Y2 class capacitors can be
used to achieve surge performance of 5 kV or greater.
The capacitive communications link is disabled by
default. To enable it, the PDL bit (Register 6, bit 4) must
be cleared. No communication between the systemside and line-side can occur until this bit is cleared. The
clock generator must be programmed to an acceptable
sample rate before clearing the PDL bit.
5.6. Transmit/Receive Full Scale Level
(Si3019 Line-Side Only)
The Si3056 supports programmable maximum transmit
and receive levels. The default signal level supported by
the Si3056 is 0 dBm into a 600 load. Two additional
modes of operation offer increased transmit and receive
level capability to enable use of the DAA in applications
that require higher signal levels. The full scale mode is
enabled by setting the FULL bit in Register 31. With
FULL = 1, the full scale signal level increases to
+3.2 dBm into a 600 load, or 1 dBV into all reference
impedances. The enhanced full scale mode (or 2X full
scale) is enabled by setting the FULL2 bit in Register
30. Will FULL2 = 1, the full scale signal level increases
to +6.0 dBm into a 600 load, or 1.5 dBV into all
reference impedances. The full scale and enhanced full
scale modes provide the ability to trade off TX power
and TX distortion for a peak signal. By using the
programmable digital gain registers in conjunction with
the enhanced full scale signal level mode, a specific
power level (+3.2 dBm for example) could be achieved
across all ACT settings.
5.7. Parallel Handset Detection
The Si3056 can detect a parallel handset going offhook. When the Si3056 is off-hook, the loop current can
be monitored with the LCS bits. A significant drop in
loop current signals that a parallel handset is going offhook. If a parallel handset causes the LCS bits to read
all 0s, the Drop-Out Detect (DOD) bit can be checked to
verify a valid line exists.
The LVS bits can be read to determine the line voltage
when on-hook and off-hook. Significant drops in line
voltage can signal a parallel handset. For the Si3056 to
operate in parallel with another handset, the parallel
handset must have a sufficiently high dc termination to
support two off-hook DAAs on the same line. Improved
parallel handset operation can be achieved by changing
the dc impedance from 50 to 800 and reducing the
DCT pin voltage with the DVC[1:0] bits.
5.8. Line Voltage/Loop Current Sensing
The Si3056 can measure loop current and line voltage
with the Si3010, Si3018, and the Si3019 line-side
devices. The 8-bit LCS2[7:0] and LCS[4:0] registers
report loop current. The 8-bit LVS[7:0] register reports
line voltage.
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These registers can help determine the following:
When on-hook, detect if a line is connected.
When on-hook, detect if a parallel phone is off-hook.
When off-hook, detect if a parallel phone goes on or
off-hook.
Detect if enough loop current is available to operate.
When used in conjunction with the OPD bit, detect if
an overcurrent condition exists. (See "5.22.Overload
Detection" on page 35.)
5.8.1. Line Voltage Measurement
The Si3056 device reports line voltage with the LVS[7:0]
bits (Register 29) in both on- and off-hook states with a
resolution of 1 V per bit. The accuracy of these bits is
approximately ±10%. Bits 0 through 6 of this register
indicate the value of the line voltage in 2s compliment
format. Bit 7 of this register indicates the polarity of the
tip/ring voltage.
If the INTE bit (Register 2) and the POLM bit (Register
3) are set, a hardware interrupt is generated on the
AOUT/INT pin when bit 7 of the LVS register changes
state. The edge-triggered interrupt is cleared by writing
0 to the POLI bit (Register 4). The POLI bit is set each
time bit 7 of the LVS register changes state and must be
written to 0 to clear it.
The default state of the LVS register forces the LVS bits
to 0 when the line voltage is 3 V or less. The LVFD bit
(Register 31, bit 0) disables the force-to-zero function
and allows the LVS register to display non-zero values
of 3 V and below. This register might display
unpredictable values at line voltages between 0 to 2 V.
At 0 V, the LVS register displays all 0s.
5.8.2. Loop Current Measurement
When the Si3056 is off-hook, the LCS2[7:0] and
LCS[4:0] bits measure loop current in 1.1 mA/bit and
3.3 mA/bit resolution respectively. These bits enable
detection of another phone going off-hook by monitoring
the dc loop current. The LCS bits are decoded from
LCS2; so, both are available at the same time. The line
current sense transfer function is shown in Figure 19
and detailed in Table 16. The LCS and LCS2 bits report
loop current down to the minimum operating loop
current for the DAA. Below this threshold, the reported
value of loop current is unpredictable.
Table 16. Loop Current Transfer Function
LCS[4:0]
Condition
00000
Insufficient line current for normal
operation. Use the DOD bit (Register 19,
bit 1) to determine if a line is connected.
00100
Minimum line current for normal operation.
11111
Loop current is greater than 127 mA. An
overcurrent situation may exist.
5.9. Off-Hook
The communication system generates an off-hook
command by applying a logic 0 to the OFHK pin or by
setting the OH bit (Register 5, bit 0).The OFHK pin must
be enabled by setting the OHE bit (Register 5, bit 1).
The polarity of the OFHK pin is selected by the OPOL
bit (Register 5, bit 4). With OFHK asserted, the system
is in an off-hook state.
The off-hook state seizes the line for incoming/outgoing
calls and also can be used for pulse dialing. With OFHK
deasserted, negligible dc current flows through the
hookswitch. When the OFHK pin is asserted, the
hookswitch transistor pair, Q1 and Q2, turn on. This
applies a termination impedance across TIP and RING
and causes dc loop current to flow. The termination
impedance has an ac and dc component.
Possible Overload
30
25
20
LCS
BITS
15
10
5
0
0
3.3
6.6
9.9 13.2 16.5 19.8 23.1 26.4 29.7
33
36.3 39.6 42.9 46.2 49.5 52.8 56.1 59.1 62.7 66
Loop Current (mA)
69.3 72.6 75.9 79.2 82.5 85.8 89.1 92.4 95.7
99 102.3
127
Figure 19. Typical Loop Current LCS Transfer Function
26
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After the off-hook counter has expired, a resistor
calibration is performed for 17 ms. This allows circuitry
internal to the DAA to adjust to the exact conditions
present at the time of going off-hook. This resistor
calibration can be disabled by setting the RCALD bit
(Register 25, bit 5).
After the resistor calibration is performed, an ADC
calibration is performed for 256 ms. This calibration
helps to remove offset in the A/D sampling the
telephone line. This ADC calibration can be disabled by
setting the CALD bit (Register 17, bit 5). See
“5.29.Calibration” on page 39. for more information on
automatic and manual calibration.
Skyworks Solutions® recommends that the resistor and
the ADC calibrations not be disabled except when a fast
response is needed after going off-hook, such as when
responding to a Type II caller-ID signal. See “5.21.Caller
ID” on page 32.
To calculate the total time required to go off-hook and
start transmission or reception, the digital filter delay
(typically 1.5 ms with the FIR filter) should be included
in the calculation.
5.10. Interrupts
The AOUT/INT pin can be used as a hardware interrupt
pin by setting the INTE bit (Register 2, bit 7). When this
bit is set, the call progress output function (AOUT) is not
available. The default state of this interrupt output pin is
active low, but active high operation can be enabled by
setting the INTP bit (Register 2, bit 6). This pin is an
open-drain output when the INTE bit is set, and requires
a 4.7 k pullup or pulldown for correct operation. If
multiple INT pins are connected to a single input, the
combined pullup or pulldown resistance should equal
4.7 k. Bits 7–2, and 0 in Register 3 and bit 1 in
Register 44 can be set to enable hardware interrupt
sources. When one or more of these bits are set, the
AOUT/INT pin becomes active and stays active until the
interrupts are serviced. If more than one hardware
interrupt is enabled in Register 3, software polling
determines the cause of the interrupts. Register 4 and
bit 3 of Register 44 contain sticky interrupt flag bits.
Clear these bits after being set to service the interrupt.
Registers 43 and 44 contain the line current/voltage
threshold interrupt. This interrupt will trigger when either
the measured line voltage or current in the LVS or LCS2
registers, as selected by the CVS bit (Register 44, bit 2),
crosses the threshold programmed into the CVT[7:0]
bits. An interrupt can be programmed to occur when the
measured value rises above or falls below the
threshold. Only the magnitude of the measured value is
used to compare to the threshold programmed into the
CVT[7:0] bits, and thus only positive numbers should be
used as a threshold. This line current/voltage threshold
interrupt is only available with the Si3019 line-side
device.
5.11. DC Termination
The DAA has programmable settings for dc impedance,
minimum operational loop current, and TIP/RING
voltage. The dc impedance of the DAA is normally
represented with a 50 slope as shown in Figure 20,
but can be changed to an 800 slope by setting the
DCR bit. This higher dc termination presents a higher
resistance to the line as loop current increases.
.
12
Voltage Across DAA (V)
Several events occur in the DAA when the OFHK pin is
asserted or the OH bit is set. There is a 250 s latency
to allow the off-hook command to be communicated to
the line-side device. Once the line-side device goes offhook, an off-hook counter forces a delay for line
transients to settle before transmission or reception
occurs. This off-hook counter time is controlled by the
FOH[1:0] bits (Register 31, bits 6:5). The default setting
for the off-hook counter time is 128 ms, but can be
adjusted up to 512 ms or down to either 64 or 8 ms.
FCC DCT Mode
11
10
9
8
7
6
.01 .02 .03 .04 .05 .06 .07 .08 .09 .1 .11
Loop Current (A)
Figure 20. FCC Mode I/V Characteristics,
DCV[1:0] = 11, MINI[1:0] = 00, ILIM = 0
For applications that require current limiting per the
TBR21 standard, the ILIM bit can be set to select this
mode. In the current limiting mode, the dc I/V curve is
changed to a 2000 slope above 40 mA, as shown in
Figure 21. The DAA operates with a 50 V, 230 feed,
which is the maximum line feed specified in the TBR21
standard.
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Si3056 Si3018/19/10
Voltage Across DAA (V)
45
TBR21 DCT Mode
Table 17. AC Termination Settings for the Si3010
and Si3018 Line-Side Devices
40
35
30
ACT
ACT2
0
0
Real, nominal 600 termination that satisfies the impedance requirements of
FCC part 68, JATE, and other countries.
1
0
Complex impedance that satisfies global
impedance requirements.
0
1
Complex impedance that satisfies global
impedance requirements EXCEPT New
Zealand. Achieves higher return loss for
countries requiring complex ac termination. [220 + (820 || 120 nF) and
220 + (820 || 115 nF)]
25
20
15
10
5
.015 .02 .025 .03 .035 .04 .045 .05 .055 .06
Loop Current (A)
Figure 21. TBR21 Mode I/V Characteristics,
DCV[1:0] = 11, MINI[1:0] = 00, ILIM = 1
AC Termination
The MINI[1:0] bits select the minimum operational loop 1
1
Complex impedance for use in New Zeacurrent for the DAA, and the DCV[1:0] bits adjust the
land. [370 + (620 || 310 nF)]
DCT pin voltage, which affects the TIP/RING voltage of
the DAA. These bits permit important trade-offs for the
Table 18. AC Termination Settings for the
system designer. Increasing the TIP/RING voltage
Si3019 Line-Side Device
provides more signal headroom, while decreasing the
TIP/RING voltage allows compliance to PTT standards
ACIM[3:0]
AC Termination
in low-voltage countries such as Japan. Increasing the
minimum operational loop current above 10 mA also
0000
600
increases signal headroom and prevents degradation of
the signal level in low-voltage countries.
0001
900
Finally, Australia has separate dc termination
0010
270 + (750 || 150 nF) and 275
requirements for line seizure versus line hold. Japan
+ (780 || 150 nF)
mode may be used to satisfy both requirements.
However, if a higher transmit level for modem operation 0011
220 + (820 || 120 nF) and
is desired, switch to FCC mode 500 ms after the initial
220 + (820 || 115 nF)
off-hook. This satisfies the Australian dc termination
0100
370 + (620 || 310 nF)
requirements.
0101
320 + (1050 || 230 nF)
5.12. AC Termination
The Si3056 has four ac termination impedances with
the Si3018 line-side device and sixteen ac termination
impedances with the Si3019 line-side device. The ACT
and ACT2 bits select the ac impedance on the Si3018
line-side device. The ACIM[3:0] bits select the ac
impedance on the Si3019. The available ac termination
settings are listed for the line-side devices in Tables 17
and 18.
The most widely used ac terminations are available as
register options to satisfy various global PTT
requirements. The real 600 impedance satisfies the
requirements of FCC part 68, JATE, and many other
countries. The 270 + (750 || 150 nF) satisfies the
requirements of TBR21 (ACT = 0, ACT = 1, or ACIM
[3:0] = 0010).
0110
370 + (820 || 110 nF)
0111
275 + (780 || 115 nF)
1000
120 + (820 || 110 nF)
1001
350 + (1000 || 210 nF)
1010
200 + (680 || 100 nF)
1011
600 + 2.16 µF
1100
900 + 1 µF
1101
900 + 2.16 µF
1110
600 + 1 µF
1111
Global complex impedance
28
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There are two selections that are useful for satisfying
non-standard ac termination requirements. The 350 +
(1000 || 210 nF) impedance selection is the
ANSI/EIA/TIA 464 compromise impedance network for
trunks.
The
last
ac
termination
selection,
ACIM[3:0] = 1111, is designed to satisfy minimum return
loss requirements for every country in the world that
requires a complex termination. For any of the ac
termination settings, the programmable hybrid can be
used to further reduce near-end echo. See
“5.13.Transhybrid Balance” for more details.
setting the RPOL bit (Register 14, bit 1). This pin is a
standard CMOS output. If multiple RGDT pins are
connected to a single input, the combined pullup or
pulldown resistance should equal 4.7 k
5.13. Transhybrid Balance
The second method to monitor ring detection uses the
ring detect bits (RDTP, RDTN, and RDT). The RDTP
and RDTN behavior is based on the RNG1-RNG2
voltage. When the signal on RNG1-RNG2 is above the
positive ring threshold, the RDTP bit is set. When the
signal on RNG1-RNG2 is below the negative ring
threshold, the RDTN bit is set. When the signal on
RNG1-RNG2 is between these thresholds, neither bit is
set.
The Si3056 contains an on-chip analog hybrid that
performs the 2- to 4-wire conversion and near-end echo
cancellation. This hybrid circuit is adjusted for each ac
termination setting selected.
The Si3056 also offers a digital filter stage for additional
near-end echo cancellation. For each ac termination
setting selected, the eight programmable hybrid
registers (Registers 45-52) can be programmed with
coefficients to provide increased cancellation of realworld line anomalies. This digital filter can produce
10 dB or greater of near-end echo cancellation in
addition to the echo cancellation provided by the analog
hybrid circuitry.
5.14. Ring Detection
The ring signal is resistively coupled from TIP and RING
to the RNG1 and RNG2 pins. The Si3056 supports
either full- or half-wave ring detection. With full-wave
ring detection, the designer can detect a polarity
reversal of the ring signal. See “5.21.Caller ID” on
page 32. The ring detection threshold is programmable
with the RT bit (Register 16, bit 0). The ring detector
output can be monitored in three ways. The first method
uses the RGDT pin. The second method uses the
register bits, RDTP, RDTN, and RDT (Register 5). The
final method uses the DTX output.
The ring detector mode is controlled by the RFWE bit
(Register 18, bit 1). When the RFWE bit is 0 (default
mode), the ring detector operates in half-wave rectifier
mode. In this mode, only positive ring signals are
detected. A positive ring signal is defined as a voltage
greater than the ring threshold across RNG1-RNG2.
Conversely, a negative ring signal is defined as a
voltage less than the negative ring threshold across
RNG1-RNG2. When the RFWE bit is 1, the ring detector
operates in full-wave rectifier mode. In this mode, both
positive and negative ring signals are detected.
The first method to monitor ring detection output uses
the RGDT pin. When the RGDT pin is used, it defaults
to active low, but can be changed to active high by
When the RFWE bit is 0, the RGDT pin is asserted
when the ring signal is positive, which results in an
output signal frequency equal to the actual ring
frequency. When the RFWE bit is 1, the RGDT pin is
asserted when the ring signal is positive or negative.
The output then appears to be twice the frequency of
the ring waveform.
The RDT behavior is also based on the RNG1-RNG2
voltage. When the RFWE bit is 0, a positive ring signal
sets the RDT bit for a period of time. When the RFWE
bit is 1, a positive or negative ring signal sets the RDT
bit.
The RDT bit acts like a one shot. When a new ring
signal is detected, the one shot is reset. If no new ring
signals are detected prior to the one shot counter
reaching 0, then the RDT bit clears. The length of this
count is approximately 5 seconds. The RDT bit is reset
to 0 by an off-hook event. If the RDTM bit
(Register 3, bit 7) is set, a hardware interrupt occurs on
the AOUT/INT pin when RDT is triggered. This interrupt
can be cleared by writing to the RDTI bit
(Register 4, bit 7). When the RDI bit (Register 2, bit 2) is
set, an interrupt occurs on both the beginning and end
of the ring pulse. Ring validation may be enabled when
using the RDI bit.
The third method to monitor detection uses the DTX
data samples to transmit ring data. If the
communications link is active (PDL = 0) and the device
is not off-hook or in on-hook line monitor mode, the ring
data is presented on DTX. The waveform on DTX
depends on the state of the RFWE bit.
When RFWE is 0, DTX is –32768 (0x8000) while the
RNG1-RNG2 voltage is between the thresholds. When
a ring is detected, DTX transitions to +32767 when the
ring signal is positive, then goes back to –32768 when
the ring is near 0 and negative. Thus a near square
wave is presented on DTX that swings from –32768 to
+32767 in cadence with the ring signal.
When RFWE is 1, DTX sits at approximately +1228
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while the RNG1-RNG2 voltage is between the
thresholds. When the ring becomes positive, DTX
transitions to +32767. When the ring signal goes near 0,
DTX remains near 1228. As the ring becomes negative,
the DTX transitions to –32768. This repeats in cadence
with the ring signal.
Delay period between when the ring signal is
validated and when a valid ring signal is indicated to
accommodate distinctive ringing.
The RNGV bit (Register 24, bit 7) enables or disables
the ring validation feature in normal operating mode and
low-power sleep mode.
To observe the ring signal on DTX, watch the MSB of
the data. The MSB toggles at the same frequency as
the ring signal independent of the ring detector mode.
This method is adequate for determining the ring
frequency.
Ring validation affects the behavior of the RDT status
bit, the RDTI interrupt, the INT pin, and the RGDT pin.
5.15. Ring Validation
This feature prevents false triggering of a ring detection
by validating the ring frequency. Invalid signals, such as
a line voltage change when a parallel handset goes offhook, pulse dialing, or a high-voltage line test are
ignored. Ring validation can be enabled during normal
operation and in low power sleep mode. The external
MCLK signal is required in low power sleep mode for
ring validation.
1. When ring validation is enabled, the status bit seen
in the RDT read-only bit (r5.2), represents the
detected envelope of the ring. The ring validation
parameters are configurable so that this envelope
may remain high throughout a distinctive-ring
sequence.
2. The RDTI interrupt fires when a validated ring
occurs. If RDI is zero (default), the interrupt occurs
on the rising edge of RDT. If RDI is set, the interrupt
occurs on both rising and falling edges of RDT.
3. The INT pin follows the RDTI bit with configurable
polarity.
The ring validation circuit operates by calculating the
time between alternating crossings of positive and
negative ring thresholds to validate that the ring
frequency is within tolerance. High and low frequency
tolerances are programmable in the RAS[5:0] and
RMX[5:0] fields. The RCC[2:0] bits define how long the
ring signal must be within tolerance.
The RGDT pin can be configured to follow the ringing
signal envelope detected by the ring validation circuit by
setting RFWE to 0. If RFWE is set to 1, the RGDT pin
follows an unqualified ring detect one-shot signal
initiated by a ring-threshold crossing and terminated by
a fixed counter timeout of approximately 5 seconds.
(This information is shown in Register 18).
Once the duration of the ring frequency is validated by
the RCC bits, the circuitry stops checking for frequency
tolerance and begins checking for the end of the ring
signal, which is defined by a lack of additional threshold
crossings for a period of time configured by the
RTO[3:0] bits. When the ring frequency is first validated,
a timer defined by the RDLY[2:0] bits is started. If the
RDLY[2:0] timer expires before the ring timeout, then
the ring is validated and a valid ring is indicated. If the
ring timeout expires before the RDLY[2:0] timer, a valid
ring is not indicated.
5.16. Ringer Impedance and Threshold
Ring validation requires five parameters:
Timeout parameter to place a lower limit on the
frequency of the ring signal on the RAS[5:0] bits
(Register 24). This is measured by calculating the
time between crossings of positive and negative ring
thresholds.
Minimum count to place an upper limit on the
frequency on the RMX[5:0] bits (Register 22).
Time interval over which the ring signal must be the
correct frequency on the RCC[2:0] bits (Register 23).
Timeout period that defines when the ring pulse has
ended based on the most recent ring threshold
crossing.
The ring detector in many DAAs is ac coupled to the line
with a large 1 µF, 250 V decoupling capacitor. The ring
detector on the Si3056 is resistively coupled to the line.
This produces a high ringer impedance to the line of
approximately 20 M to meet the majority of country
PTT specifications, including FCC and TBR21.
Several countries including Poland, and South Africa,
may require a maximum ringer impedance that can be
met with an internally synthesized impedance by setting
the RZ bit (Register 16, bit 1).
Some countries also specify ringer thresholds
differently. The RT bit (Register 16, bit 0) selects
between two different ringer thresholds: 15 V ±10% and
21.5 V ±10%. These two settings satisfy ringer
threshold requirements worldwide. The thresholds are
set so that a ring signal is guaranteed to not be detected
below the minimum, and a ring signal is guaranteed to
be detected above the maximum.
30
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5.17. Pulse Dialing and Spark Quenching
Pulse dialing results from going off- and on-hook to
generate make and break pulses. The nominal rate is
10 pulses per second. Some countries have strict
specifications for pulse fidelity that include make and
break times, make resistance, and rise and fall times. In
a traditional solid-state dc holding circuit, there are
many problems in meeting these requirements.
The Si3056 dc holding circuit actively controls the onhook and off-hook transients to maintain pulse dialing
fidelity.
Spark quenching requirements in countries such as
Italy, the Netherlands, South Africa, and Australia deal
with the on-hook transition during pulse dialing. These
tests provide an inductive dc feed resulting in a large
voltage spike. This spike is caused by the line
inductance and the sudden decrease in current through
the loop when going on-hook. The traditional solution to
the problem is to put a parallel resistive capacitor (RC)
shunt across the hookswitch relay. However, the
capacitor required is large (~1 F, 250 V) and relatively
expensive. In the Si3056, loop current can be controlled
to achieve three distinct on-hook speeds to pass spark
quenching tests without additional BOM components.
Through settings of four bits in three registers, OHS
(Register 16), OHS2 (Register 31), SQ1 and SQ0
(Register 59), a slow ramp down of loop current can be
achieved which induces a delay between the time OH
bit is cleared and the time the DAA actually goes onhook.
To ensure proper operation of the DAA during pulse
dialing, disable the automatic resistor calibration that is
performed each time the DAA enters the off-hook state
by setting the RCALD bit (Register 25, bit 5).
5.18. Billing Tone Protection and Receive
Overload
“Billing tones” or “metering pulses” generated by the
Central Office can cause modem connection difficulties.
The billing tone is typically either a 12 or 16 kHz signal
and is sometimes used in Germany, Switzerland, and
South Africa. Depending on line conditions, the billing
tone might be large enough to cause major errors in the
line data. The Si3056 chipset can provide feedback
indicating the beginning and end of a billing tone.
Billing tone detection is enabled with the BTE bit
(Register 17, bit 2). Billing tones less than 1.1 VPK on
the line are filtered out by the low pass digital filter on
the Si3056. The ROV bit is set when a line signal is
greater than 1.1 VPK, indicating a receive overload
condition. The BTD bit is set when a billing tone is large
enough to excessively reduce the line-derived power
supply of the line-side device.
The OVL bit (Register 19) can be polled following a
billing tone detection. The OVL bit indicates that the
billing tone has passed when it returns to 0. The BTD
and ROV bits are sticky, and must be written to 0 to be
reset. After the billing tone passes, the DAA initiates an
auto-calibration sequence that must complete before
data can be transmitted or received.
Certain line events, such as an off-hook event on a
parallel phone or a polarity reversal, can trigger the ROV
or the BTD bits. Look for multiple events before
qualifying if billing tones are present. After the billing
tone passes, the DAA initiates an auto-calibration
sequence that must complete before data can be
transmitted or received.
Although the DAA remains off-hook during a billing tone
event, the received data from the line is corrupted when
a large billing tone occurs. If the user wishes to receive
data through a billing tone, an external LC filter must be
added. A manufacturer can provide this filter to users in
the form of a dongle that connects on the phone line
before the DAA. This prevents the manufacturer from
having to include a costly LC filter to support multiple
countries and customers.
Alternatively, when a billing tone is detected, the system
software notifies the user that a billing tone has
occurred. Notification prompts the user to contact the
telephone company to disable billing tones or to
purchase an external LC filter.
Disturbance on the line other than billing tones can also
cause a receive overload. Some conditions may result in
a loop current collapse to a level below the minimum
required operating current of the DAA. When this occurs,
the dropout detect bit (DOD) is set, and an interrupt will
be generated if the dropout detect interrupt mask bit
(DODM) is set.
5.19. Billing Tone Filter (Optional)
To operate without degradation during billing tones in
Germany, Switzerland, and South Africa, requires an
external LC notch filter. The Si3056 can remain off-hook
during a billing tone event, but line data is lost in the
presence of large billing tone signals. The notch filter
design requires two notches, one at 12 kHz and one at
16 kHz. Because these components are expensive and
few countries utilize billing tones, this filter is typically
placed in an external dongle or added as a population
option for these countries. Figure 22 shows an example
billing tone filter.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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Si3056 Si3018/19/10
5.21. Caller ID
C1
The Si3056 can pass caller ID data from the phone line
to a caller ID decoder connected to the serial port.
C2
5.21.1. Type I Caller ID
Type I Caller ID sends the CID data while the phone is
on-hook.
L1
TIP
From
Line
L2
To
DAA
C3
RING
Figure 22. Billing Tone Filter
L1 must carry the entire loop current. The series
resistance of the inductors is important to achieve a
narrow and deep notch. This design has more than
25 dB of attenuation at both 12 kHz and 16 kHz.
Table 19. Component Values—Optional Billing
Tone Filters
Symbol
Value
C1,C2
0.027 µF, 50 V, ±10%
C3
0.01 µF, 250 V, ±10%
L1
3.3 mH, >120 mA, 40 mA,
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