Si3406x Family Data Sheet
Fully-Integrated IEEE 802.3-Compliant POE+ PD Interface and
High-Efficiency Switching Regulators with Sleep, Wake, and LED
Drive
The Si3406x family integrates all power management and control functions required in
a Power-over-Ethernet Plus (PoE+) powered device (PD) application. These devices
convert the high voltage supplied over the 10/100/1000BASE-T Ethernet connection to
a regulated, low-voltage output supply. The optimized architecture of this device family
minimizes the solution footprint and external BOM cost and enables the use of low-cost
external components while maintaining high performance. The Si3406x family integrates the required diode bridges and transient surge suppressor, thus enabling direct
connection of the IC to the Ethernet RJ-45 connector. The switching power FET and
all associated functions are also integrated. The integrated, current mode controlled
switching regulator supports isolated or non-isolated flyback and buck converter topologies. The switching frequency for the regulator is tunable with a simple external resistor
value to help avoid unwanted harmonics for better emissions control. A synchronous
driver is provided to optionally drive a secondary side FET to improve efficiency of
power conversion. Connection to the PSE switch is maintained during sleep by an
optional automated maintain-power-signature (MPS) signal.
These devices fully support the IEEE 802.3at specification for the cases of single or
two event classification. Standard external resistors provide the proper IEEE 802.3
signatures for the detection function and programming of the classification mode, and
internal startup circuits ensure well-controlled soft-start initial operation of both the
hotswap switch and the voltage regulator.
The Si34061 and Si34062 add main transformer bias winding support for ultra-high-efficiency operation.
The Si34062 includes support for sleep modes with wake function, as well as LED drive
capability. These features can be utilized to minimize standby current, control sleep and
wake states, and provide application status information using an LED.
KEY FEATURES
• Type 1 (PoE) or Type 2 (PoE+) power
• Full IEEE 802.3at compliance
• Synchronous secondary FET driver
• Current mode dc-dc converter
• Tunable switching frequency
• Auxiliary transformer winding support
• Auxiliary wall adapter support (12 V to 57 V)
• Internal hotswap and switching FET bypass
support
• Automated maintain-power-signature (MPS)
support
• Sleep mode augmented with wake pin,
mode control, and LED driver
• 120 V Absolute Max voltage performance
• Extended –40 to +85 °C temperature
• Compact ROHS-compliant 5 mm x 5 mm
QFN Package
APPLICATIONS
• Voice over IP telephones
• Wireless access points
• Security and surveillance IP cameras
• Lighting luminaires
• Point-of-sale terminals
• Internet appliances
• Network devices
The Si3406 is available in a low-profile, 20-pin, 5 x 5 mm QFN package, and the
Si34061 and Si34062 are available in low-profile, 24-pin, 5 x 5 mm QFN packages.
1
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1
Si3406x Family Data Sheet • Ordering Guide
1. Ordering Guide
Table 1.1. Si3406x Ordering Guide
Ordering Part Number
Si3406-A-GM
Si34061-A-GM
Si34062-A-GM
2
Package
5 x 5 mm 20-QFN
Pb-free, RoHS-compliant
5 x 5 mm 24-QFN
Pb-free, RoHS-compliant
5 x 5 mm 24-QFN
Pb-free, RoHS-compliant
Temperature Range (Ambient)
Applications
–40 to 85 °C Extended
All Purposes
–40 to 85 °C Extended
Any high-power, high-efficiency
uses, such as Wireless Access
Points and IP Cameras
–40 to 85 °C Extended
IP Phones with manual sleep
mode
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2
Table of Contents
1. Ordering Guide
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2. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Block Diagrams.
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. 4
2.2 Power over Ethernet (PoE) Line-Side Interface
2.2.1 Surge Protection . . . . . . . . .
2.2.2 Telephony Protection . . . . . . .
2.2.3 Detection and Classification . . . . .
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2.3 Hotswap Switch
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2.4 HSSW State Machine . . . .
2.4.1 External HSSW FET Driver .
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2.5 DC to DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.1 Average Current Sensing, Overcurrent, Low-Current Detection, and Output Short Protection .
2.5.2 Sync FET Driver . . . . . . . . . . . . . . . . . . . . . . . . . . .
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2.6 Tunable Oscillator .
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. 9
2.7 Regulators .
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2.8 Sleep Mode .
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2.9 Special Sleep Mode .
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.10
2.10 External Wall Adapter Support .
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.11
3. Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . .
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4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . .
14
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
6. Packaging
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5.1 Detailed Pin Descriptions
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6.1 Package Outline: Si3406
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.26
6.2 Land Pattern: Si3406 .
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.28
6.3 Package Outline: Si34061/62 .
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.29
6.4 Land Pattern: Si34061/62 .
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.31
7. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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7.1 Si3406 Top Marking .
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.32
7.2 Si34061 Top Marking .
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.33
7.3 Si34062 Top Marking .
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.34
8. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
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3
Si3406x Family Data Sheet • System Overview
2. System Overview
The following Block Diagrams will give the designer a sense for the internal arrangement of functional blocks, plus their relationships to
external pins. The Block Diagrams are followed by a description of the features of these integrated circuits.
2.1 Block Diagrams
RFREQ
RDET
V11
VPOS
11V
REGULATOR
IBIAS
CT1
CT2
DETECTION
SP1
THERMAL
PROTECTION
FBH
VSS+1.32V
FBL
EROUT
DC/DC
SW
CURRENT
MODE
PWM
CONTROLLER
THERMAL
PROTECTION
HOT-SWAP
CONTROLLER
100V
VPOS-1.32V
Start
250kHz
TVS
5V
REGULATOR
250kHz
OSCs
fixed: 250kHz
adjustable: 100...500kHz
PoE
CONTROLLER
CLASS
&
MPS
SP2
VDD
SWO
VSS
VNEG
HSSW
ISNS
IAVG
HSO
V11
SYNCL
DRV
RCL
nSLEEP
nT2P
Figure 2.1. Si3406 Block Diagram
RFREQ
RDET
VT15
AUX
WINDING
SUPPORT
VPOS
IBIAS
CT1
V11
VDD
11V
REGULATOR
5V
REGULATOR
250kHz
OSCs
fixed: 250kHz
adjustable: 100...500kHz
THERMAL
PROTECTION
VSS+1.32V
CT2
DETECTION
SP1
PoE
CONTROLLER
CURRENT
MODE
PWM
CONTROLLER
THERMAL
PROTECTION
HOT-SWAP
CONTROLLER
TVS
100V
DC/DC
SW
HSSW
V11
IPK
VEHSSW
DRV
IAVG
EXTGD
SWISNS
ISNS
HSO
V11
DRV
EXTHSW
SWO
VSS
DRV
VNEG
RCL
FBL
EROUT
250kHz
CLASS
&
MPS
SP2
Start
ASUP
nT2P
SYNCL
nSLEEP
Figure 2.2. Si34061 Block Diagram
4
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Si3406x Family Data Sheet • System Overview
RFREQ
RDET
VT15
AUX
WINDING
SUPPORT
VPOS
IBIAS
CT1
V11
VDD
11V
REGULATOR
5V
REGULATOR
250kHz
OSCs
fixed: 250kHz
adjustable: 100...500kHz
THERMAL
PROTECTION
FBH
VPOS-1.32V
FBL
VSS+1.32V
CT2
DETECTION
SP1
PoE
CONTROLLER
EROUT
250kHz
CLASS
&
MPS
SP2
Start
CURRENT
MODE
PWM
CONTROLLER
THERMAL
PROTECTION
HOT-SWAP
CONTROLLER
TVS
100V
DC/DC
SW
SWO
VSS
VNEG
HSSW
IAVG
ISNS
HSO
V11
DRV
RCL
WAKE
MODE
LED
nT2P
SYNCL
nSLEEP
Figure 2.3. Si34062 Block Diagram
2.2 Power over Ethernet (PoE) Line-Side Interface
The PoE line interface consists of diode bridges, internal surge protection, and the protocol interface support for detection and
classification.
Internal diode bridge maximum current is given by the specification, IRECT. For Class 1 and Class 2 applications, the internal diode
bridge can be used. For Class 3 and Class 4, an external diode bridge needs to be installed.
The external bridge should be connected in parallel to the internal bridge and the designer must ensure that the internal bridge will not
conduct significant current by using low-voltage-drop external diodes. For higher efficiency, Schottky diodes are recommended.
Instead of a diode bridge, a Mosfet based bridge can be used as well to further improve the overall efficiency.
The chip features active protection against surge transients and accidentally applied telephony voltages.
2.2.1 Surge Protection
The surge protection circuit is activated if the VPOS-VNEG voltage exceeds VPROT and the hotswap switch is off (dc-dc is not
powered). If the hotswap switch is on, the surge power is sunk in the dc-dc input capacitance.
The internal surge protection can be overridden with an external TVS if higher than specified surge conditions need be tolerated. The
external surge device must be connected between VPOS an VNEG in parallel to the internal one; therefore, the designer must ensure
that the external surge protection will activate prior to the internal surge protection.
2.2.2 Telephony Protection
The Si3406x provides protection against telephony ringing voltage. The telephony ringing is much longer than the surge pulse but it
has less energy, therefore, the Si3406x has a switch parallel with the supply (between VPOS and VNEG). When the protection circuit is
activated, it turns ON the protection switch; the ringing energy then dissipates on this switch and ringing generator resistance (> 400 Ω).
5
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Si3406x Family Data Sheet • System Overview
2.2.3 Detection and Classification
When the Si3406x is connected via Ethernet cable to a PSE-enabled Ethernet switch, it must provide a characteristic resistance (~25
kΩ) to the PSE in a given voltage range (2.7–10.1 V). This is called detection. After the PSE detects the PD, the PSE increases the
voltage above the classification threshold 14.5 V. Then, the PD provides the classification current to inform the PSE about its required
power class (Class 1, 2, 3, or 4). Type 1 PSEs will recognize the Class 4 PD as Class 0, providing 15.4 W to the PD. Therefore, the
optimal Class 4 PD application is designed with two power modes: Low-Power mode (for Type 1 PSE) and High-Power mode (for Type
2 PSE). Type 2 PSEs have additional voltage steps before switching on the PD. After an initial classification voltage pulse, the Type 2
PSE reduces the voltage below the mark threshold level (10 V). At that point, the PD should provide a non-valid detection resistance.
Then, the PSE raises a voltage up again to the Class event range (Class 2). Last, before turning ON the dc-dc, the PSE reduces the
voltage again (Mark2). This sequence is recognized by the si3406x, and it pulls down its nT2P pin to inform the application about the
higher available power; otherwise, the application will need to operate in a reduced power consumption state (Type 1) if the PSE is
incapable of delivering Class 4 power.
Voltage
57 V
IEEE 802.3afstartup
42 V
37 V
42.5 V – 57 V (at)
37 V - 57 V (af)
20.5 V
Class2
Class1
IEEE 802.3atstartup
14.5 V
10.1 V
Mark1
6.9 V
Mark2
2.7 V
Time
Reset
Detection
Classification/Mark
PD turned ON
Figure 2.4. Powered Device Voltages
2.3 Hotswap Switch
The hotswap switch is a high-voltage device that separates the PoE inerface from the dc-dc converter domain. The internal hotswap
switch (HSSW) is turned on (conducting) when the PoE interface voltage goes above VUVLO_R. It provides limited inrush current until
the dc-dc side capacitor is charged. The hotswap switch turns off (open) if voltage on the HSSW switch (HSO-VNEG) is greater than
VHSSW_OFF.
In overload, the hotswap switch goes into current-limiting mode with a current limit of IOVL. It will turn back ON after TWAITHSSW elapses
and the dc-dc input capacitor is recharged, meaning the HSO-VNEG voltage is less than VHSSW_ON.
The hotswap switch (if it is in the on state and conducting) can detect if the current is lower than IMPSth. If automatic sleep mode is
enabled, the chip turns on MPS pulse generation, which ensures that the PSE will not disconnect.
With the Si34061, an external hotswap switch can be used to improve efficiency and reduce thermal stress in high current applications.
For Class 3 applications, using an external hotswap switch is recommended; for Class 4, it is mandatory because the internal hotswap
switch otherwise generates significant heat. When an external hotswap switch is used, intelligent switch control ensures that inrush
current limiting and automatic MPS request of the internal switch are still supported.
6
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Si3406x Family Data Sheet • System Overview
2.4 HSSW State Machine
The HSSW operates as simple 4-state state machine:
2
S3
S2
ON
3
INRUSH
1
170 mA
S4
S1
5
5
4
OVERLOAD
OFF
10 mA
5
Figure 2.5. Hotswap Switch 4-State Machine
OFF State
HSSW turn-on is controlled by UVLO, the undervoltage lockout feature. When UVLO is engaged, the HSSW is OFF. In this state,
the HSSW is in idle mode, VNEG and HSO pins are disconnected. In normal operation, a complete detect/classification procedure
precedes the HSSW turn-on, and the control of this sequence is implemented in the state machine logic of the chip.
INRUSH State
After the controller enables the HSSW, the block starts operation in the INRUSH state. In this state the switch itself is not directly turned
on, but operating in a closed-loop current limit mode to avoid high current peaks during the charging of the input capacitor of the dc-dc
converter.
If the VHSSW voltage drops below 380 mV (meaning the bypass cap is 99% charged), the HSSW will change state to ON either in
Type1 classification immediately, or in Type2 classification if the HSSW has been in the INRUSH state for at least 80 ms.
ON State
In ON state, the HSSW switch is completely turned on. The HSSW circuit continuously monitors VHSSW. HSSW will change to
OVERLOAD state if VHSSW voltage increases over 3.5 V for at least 140 µs.
OVERLOAD State
In OVERLOAD state the HSSW operates in closed-loop low current limit mode. If the VHSSW voltage drops below 380 mV again, and
the HSSW has been in the OVERLOAD state for at least 80 ms, the HSSW will change back to the ON state.
2.4.1 External HSSW FET Driver
An external HSSW FET may be used to improve thermal operation of an Si34061 at very high power loading levels (the top end of
Class 4).
With the Si34061, the chip automatically detects if the EXTHSW pin is connected to VNEG or to a FET gate at startup. If the external
hotswap FET driver will not be used, the EXTHSW pin must be tied to VNEG.
For further information on using an external HSSW FET, please refer to "AN1130: Using the Si3406/Si34061/Si34062 PoE+ and Si3404
PoE PD Controller In Isolated and Non-Isolated Designs".
7
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Si3406x Family Data Sheet • System Overview
2.5 DC to DC Converter
The dc-dc converter is current-controlled for easier compensation and more robust protection of circuit magnetics. The controller has
the following features:
• High- and low-side error amplifier (supports Buck and Flyback topologies).
• 681 Ω)
0
—
4
mA
Class 1 (RCLASS = 140 Ω @ 1%)
9
—
12
mA
Class 2 (RCLASS = 75 Ω @ 1%)
17
—
20
mA
Class 3 (RCLASS = 48.7 Ω @ 1%)
26
—
30
mA
Class 4 (RCLASS = 33.2 Ω @ 1 %)
36
—
44
mA
VMARK
Mark event voltage (at VPORT)
6.9
—
10.1
V
IMARK
Mark event current
0.25
—
4
mA
VUVLO_R
Hotswap closed and converter on
34
37
40
V
VUVLO_F
Hotswap open and converter off
30
32
34
V
3.5
4.5
6
V
PoE PROTOCOL
Detection
VDET
Classification
VRESET
VCLASS
IPortCLASS
Type 2 Classification
Power On and UVLO
VUVLO_HYST
Thermal Characteristics
TSHD
Thermal shutdown
—
160
—
°C
THYST
Thermal shutdown hysteresis
—
20
—
°C
TVS protection activation voltage (VPOSVNEG)
100
—
—
V
Iinrush
Inrush current
100
170
200
mA
IMAXHSSW
Maximum continuous operating current
—
—
600
mA
VHSSW_ON
Switch ON voltage
—
380
—
mV
VHSSW_OFF
Switch OFF voltage, HSSW goes to overload
cycle
—
3.5
—
V
On-Chip Transient Voltage Suppression/Protection
VPROT
Hotswap Switch
16
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16
Si3406x Family Data Sheet • Electrical Specifications
Symbol
Parameter (Condition)
Min
Typ
Max
Unit
IOVL
Switch current limit in OVERLOAD State
—
10.5
—
mA
IMPSth
MPS signal request current level threshold
14
20
26
mA
IEXT_DRV
External hotswap driver peak current on
EXTHSW pin
—
—
10
mA
VEXT_DRV
External hotswap driver voltage on EXTHSW
pin
9
11
13
V
TWAITHSSW
Wait time in OVERLOAD and type 2 inrush
80
96
116
ms
RONHSSW
Internal hotswap drain-source resistance while
ON
0.65
1.5
2.9
Ω
ISWOPEAK
Peak current limit of internal FET (SWO pin)
2.1
—
2.7
A
VEXTGD
External FET driver voltage (EXTGD pin)
9
11
13
V
IEXTGD
External FET driver peak current (EXTGD pin)
—
—
500
mA
FOSCINT
Using internal Oscillator
215
250
290
kHz
Using external Oscillator,
RFREQ = 215 kΩ
75
95
115
kHz
Using external Oscillator,
RFREQ = 39 kΩ
420
470
520
kHz
DUC
Output duty cycle of PWM
—
—
75
%
VDCDCUVLO
DCDC UVLO level (Minimum adapter voltageASUP mode)
10.75
11.3
11.85
V
VFBREF
FBH (referenced to VPOS) and FBL (referenced to VSS) reference voltage
1.28
1.32
1.36
V
VEROUT
Operating voltage range of error input
1
—
4
V
THICCUP
Output short protection if EROUT is max
—
1
—
ms
VISNS_OVC
Overcurrent limit voltage on ISNS (ref. to VSS)
–305
–270
–255
mV
VISNS_LC
Low current limit voltage on ISNS (ref. to VSS)
–45
–30
–15
mV
VSWISNSMAX
External FET peak current sense
—
240
—
mV
TSOFTSTART
Startup time1
—
15
—
ms
RONDCDC
Internal DCDC switching FET drain-source resistance while ON
—
0.9
1.2
Ω
DC-DC
FOSCEXT
Regulators
17
VT15
Override internal regulator with transformer
winding
12.5
—
16.5
V
VDD
5 V regulated output
4.9
5.2
5.5
V
VDDILIM
DC current limit of VDD
9.7
11.2
—
mA
CREG
Filter capacitor on VDD and V11
82
100
220
nF
IMAXLED
LED pin max current, reduces VDDILIM
—
5
—
mA
IMAXDO
Digital output max current (NT2P), reduces
VDDILIM
2
2.5
—
mA
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Si3406x Family Data Sheet • Electrical Specifications
Symbol
Parameter (Condition)
Min
Typ
Max
Unit
PINTMAX
DC-DC max power internal FET
—
0.2
0.9
W
PMAX
Total chip power
—
0.5
—
W
IPortOP
Operating current (VPORT 57 V; 250 kHz)
—
3
5
mA
Power Dissipation2
Package Thermal Characteristics2
θJA
QFN20
—
44
—
C°/W
θJA
QFN24
—
38.5
—
C°/W
Note:
1. Depends on output load.
2. Assumes 4-Layer PCB with adequate layout.
18
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Si3406x Family Data Sheet • Pin Descriptions
5. Pin Descriptions
SYNCL
19
VDD 4
14 VPOS
LED 5
15 CT2
14 VPOS
13 SP1
7
8
9
10
11
12
SP2
WAKE 6
RCL
12
16 CT1
RFREQ
SP2
20
VNEG
(ePad)
HSO
RFREQ
11
SP2
RCL
10
RFREQ
HSO
9
RCL
RDET
8
HSO
nSLEEP
7
RDET
10
15 CT2
13 SP1
nSLEEP
9
FBL 3
RDET
VDD 4
EXTHSW 5
16 CT1
nSLEEP
VNEG
(ePad)
ASUP 6
8
21
17 nT2P
12 VPOS
7
22
EROUT 2
FBL 3
6
23
17 nT2P
EROUT 2
5
24
18 VT15
13 CT2
11 SP1
19
FBH 1
14 CT1
FBL 3
20
18 VT15
EROUT 2
VDD 4
21
ISNS 1
FBH 1
VNEG
(ePad)
22
MODE
23
V11
24
SWO
VSS
15
ISNS
SWISNS
16
VSS
nT2P
17
V11
SYNCL
18
Si34062 Pinout
(Top View)
SYNCL
V11
19
SWO
SWO
20
EXTGD
VSS
Si34061 Pinout
(Top View)
ISNS
Si3406 Pinout
(Top View)
Table 5.1. Pin Descriptions
'06
Pins
'061
Pins
'062
Pins
Name
Ref
Dir.
Vrange
SWISNS
VSS
I
0–1
External FET peak current sense resistor voltage input
24
ISNS
VSS
I
-1–0
Chip average current sense resistor input
1
FBH
VPOS
I
0–5.5
High side (VPOS referred) dc-dc feedback (Buck converter)
24
20
1
1
2
2
2
EROUT
VSS
IO
0–5.5
Error amplifier current output, compensation impedance input
3
3
3
FBL
VSS
I
0–5.5
Low side (VSS referenced) dc-dc feedback (Flyback converter)
4
4
4
VDD
VSS
O
0–5.5
5 V regulator output
5
LED
VSS
O
0–5.5
Output to drive sleep LED
EXTHSW
VNEG
O
0–11
External hotswap switch drive
WAKE
VSS
I
0–5.5
Wakeup from sleep mode
ASUP
VSS
I
0–5.5
AUX auxiliary adapter present
5
6
6
19
Description
5
7
7
nSLEEP
VSS
I
0–5.5
Sleep, with pull-up, driven by open drain
6
8
8
RDET
VPOS
IO
0–100
Detection resistor
7
9
9
HSO
VNEG
IO
0–100
Hotswap switch output
8
10
10
RCL
VNEG
IO
0–5.5
Classification resistor
9
11
11
RFREQ
VPOS
IO
0–5.5
Oscillator frequency tuning resistor, tie to VPOS to select default frequency
10
12
12
SP2
SP1
I
0 - 100 High-voltage supply input from spare pair; polarity-insensitive
11
13
13
SP1
SP2
I
0–100
High-voltage supply input from spare pair; polarity-insensitive
12
14
14
VPOS
—
IO
0–100
Rectified high-voltage supply positive rail
13
15
15
CT2
CT1
I
0–100
High-voltage supply input from main pair; polarity-insensitive
14
16
16
CT1
CT2
I
0 - 100 High-voltage supply input from main pair; polarity-insensitive
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Si3406x Family Data Sheet • Pin Descriptions
'06
Pins
'061
Pins
'062
Pins
Name
Ref
Dir.
Vrange
15
17
17
nT2P
VSS
O
0–5.5
18
18
VT15
VSS
I
0–16.5 dc-dc transformer bias winding input
16
19
19
SYNCL
VSS
O
0–11
Gate driver for synchronous rectification FET
17
20
20
V11
VSS
IO
0–11
11 V regulator output for filter cap.
EXTGD
VSS
O
0–11
External FET gate drive.
When internal switching FET is in use, tie to VSS.
21
MODE
VSS
I
0–5.5
Controls MPS and LED switch behavior
Internal dc-dc switch output (NMOS drain)
21
Description
Type II classification was successful
18
22
22
SWO
VSS
O
0–120
19
23
23
VSS
—
IO
0
dc-dc converter primary ground
ePad
ePad
ePad
VNEG
—
IO
0
Rectified high voltage supply ground
20
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Si3406x Family Data Sheet • Pin Descriptions
5.1 Detailed Pin Descriptions
Table 5.2. Circuit Equivalent and Description of Die Pads
Pin Name
Detailed Description
Circuit Detail
VDD
SWISNS
External dc-dc switching FET peak current sense resistor input. The maximum current of the switching FET should correspond to voltage VSWISNSMAX.
SWISNS
RSWISNS
VSS
VSS
ISNS
Average current sense resistor input. The resistor value will set the maximum allowed average current for the application. The overcurrent threshold
voltage VISNS_OVC. Note that this pin voltage goes below VSS.
ISNS
VPOS
FBH
High side dc-dc feedback input. Need to be tied to VPOS when not used.
See VFBREF.
FBH
VDD
dc-dc converter error output; current out, voltage sense. Loop compensating impedance should be connected here.
EROUT
EROUT
IEROUT = (VFBH – VFBREF) x 50 μA or
IEROUT = (VFBL – VFBREF) x 50 μA
VSS
VDD
FBL
Low side dc-dc feedback input. Need to be tied to VSS when not used. See
VFBREF
FBL
VSS
21
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Si3406x Family Data Sheet • Pin Descriptions
Pin Name
Detailed Description
Circuit Detail
VDD
VDD
Regulated 5 V relative to VSS. There is no foldback characteristic, reaching
VDDILIM the output voltage decreases.
The regulator needs CREG external capacitance.
VSS
VDD
LED
LED
LED driver output Max current is IMAXLED
VSS
VDD
WAKE
Wake-up input pin for sleep mode, used only in Si34062.
WAKE
VSS
VDD
ASUP
Auxiliary supply adapter is present. Enables the operation of the dc-dc
controller without PoE supply being present (used only in Si34061).
ASUP
VSS
VDD
nSLEEP
Sleep function input, see description in Sleep mode section.
nSLEEP
VSS
22
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Si3406x Family Data Sheet • Pin Descriptions
Pin Name
Detailed Description
Circuit Detail
ICLASS
RCL
Classification resistor input. For class 0 this pin can be left floating. Pin is
active only at time of classification.
RCL
+
-
REXT
VNEG
VPOS
Used for adjusting the oscillator frequency.
RFREQ
The frequency is inversely proportional to the value of the connected resistor.
REXT
+
-
RFREQ
IFREQ
VPOS
SP1, SP2
CT1, CT2
Main power inputs, goes to diode bridge producing VPOS and VNEG. Can
be used up to Class 1 and Class 2. For higher power classes, external
bridge is required.
CT1,CT2
SP1,SP2
VNEG
VPOS
VPOS,
VNEG
Main chip power output generated by the diode bridge. Note that VNEG
(the ePad on the bottom of the chip) also provides thermal relief.
CT1,CT2
SP1,SP2
VNEG
VDD
nT2P
23
Pin main function is digital output; it is low if Type 2 classification was
successful and the application is allowed to draw class 4 current.
nT2P
Output current is IMAXDO, but the load (e.g. an LED) should connected to
VDD not VSS; otherwise, it can cause false operation.
VSS
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Si3406x Family Data Sheet • Pin Descriptions
Pin Name
Detailed Description
Circuit Detail
HSO
HSO
Hotswap Switch Output. The switch shorts the VNEG and HSO pins, and
includes several other functions. See hotswap switch section for details.
100V
VNEG
V11
6V
EXTGD,
SYNCL
EXTGD: Optional external switch driver of the dc-dc converter. When the
internal switch is used this pin should be tied to VSS. This driver controls
the external switch with 10 V logic level, relative to VSS.
VCASP
SYNCL: Optional synchronous rectifier switch driver of the dc-dc converter.
When not used the pin must be left floating. This driver controls the external
synchronous switch with 10 V logic level, relative to VSS.
VCASN
6V
EXTGD/
SYNCL
6V
6V
VSS
11V internal supply
6V
EXTHSW
Optional external hotswap switch driver output. The maximum current of the
internal hotswap switch is IMAXHSSW, for higher currents an external NMOS
FET should be used in parallel with the internal HSSW (VNEG-HSO). When VCAS
EXTGD is not used the pin should be tied to VNEG. This driver controls the
external switch with 10 V logic level, relative to VNEG.
6V
EXTHSW
6V
6V
VNEG
VPOS
RDET
24
The user has to tie the RDET resistor between this pin and VPOS. During
detection, a high voltage switch pulls down RDET to VNEG. After detection,
the reference block uses RDET as absolute chip current reference, forcing
–750 mV relative to VPOS, creating 30 µA for the internal blocks.
100V
RDET
RDET
100V
VNEG
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Si3406x Family Data Sheet • Pin Descriptions
Pin Name
Detailed Description
Circuit Detail
VPOS
VT15,
V11
VT15
VT15 is input for an optional 15 V supply generated by an auxiliary transformer bias winding. If the bias winding voltage is lower than VT15_MIN, the
internal 15 V coarse regulator will provide the current for the 11 V regulator.
6V
The V11 pin is for filtering capacitor for the 11 V regulator. A capacitor of
value CREG is required.
6V
V11
6V
VSS
VDD
MODE
MODE
MPS mode control, used in Si34062.
VSS
SWO
SWO
dc-dc converter switching transistor drain output, Vmax = 120 V.
VSS
VPOS
VSS
dc-dc converter ground.
120V
ESD
CLAMP
VSS
25
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Si3406x Family Data Sheet • Packaging
6. Packaging
6.1 Package Outline: Si3406
The figure below illustrates the package details for the Si3406. The table lists the values for the dimensions shown in the illustration.
Figure 6.1. 20-Pin, QFN Package
Table 6.1. Package Diagram Dimensions
Dimension
Min
Nom
Max
A
0.80
0.85
0.90
A1
0.00
0.02
0.05
b
0.25
0.30
0.35
D
D2
26
5.00 BSC.
2.60
2.70
e
0.80 BSC.
E
5.00 BSC.
2.80
E2
2.60
2.70
2.80
L
0.50
0.55
0.60
L1
0.00
—
0.10
aaa
—
—
0.10
bbb
—
—
0.10
ccc
—
—
0.08
ddd
—
—
0.10
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Si3406x Family Data Sheet • Packaging
Dimension
Min
Nom
Max
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VHHB-1.
27
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Si3406x Family Data Sheet • Packaging
6.2 Land Pattern: Si3406
The figure below illustrates the land pattern details for the Si3406. The table lists the values for the dimensions shown in the illustration.
Figure 6.2. 20-Pin, QFN Land Pattern
Table 6.2. Land Pattern Dimensions
Dimension
Max
C1
4.70
C2
4.70
X1
0.35
X2
2.80
Y1
1.00
Y2
2.80
e
0.80
Note:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This land pattern design is based on the IPC-7351 guidelines.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
28
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Si3406x Family Data Sheet • Packaging
6.3 Package Outline: Si34061/62
The figure below illustrates the package details for the Si34061/62. The table lists the values for the dimensions shown in the
illustration.
Figure 6.3. 24-Pin, QFN Package
Table 6.3. Package Diagram Dimensions
29
Symbol
Min
Nom
Max
A
0.80
0.85
0.90
A1
0.00
0.02
0.05
b
0.25
0.30
0.35
A3
0.20 REF
D
5.00 BSC.
e
0.65 BSC.
E
5.00 BSC.
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Si3406x Family Data Sheet • Packaging
Symbol
Min
Nom
Max
D2
2.90
3.00
3.10
E2
2.90
3.00
3.10
L
0.35
0.40
0.45
K
0.20
—
—
aaa
0.15
bbb
0.10
ccc
0.10
ddd
0.05
eee
0.08
fff
0.10
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
30
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Si3406x Family Data Sheet • Packaging
6.4 Land Pattern: Si34061/62
The figure below illustrates the land pattern details for the Si34061/62. The table lists the values for the dimensions shown in the
illustration.
Figure 6.4. 24-Pin, QFN Land Pattern
Table 6.4. Land Pattern Dimensions
Dimension
mm
C1
4.90
C2
4.90
X1
0.35
X2
3.10
Y1
0.85
Y2
3.10
e
0.65
Note:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted
2. This land pattern design is based on the IPC-7351 guidelines
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release
2. The stencil thickness should be 0.125 mm (5 mils)
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
31
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Si3406x Family Data Sheet • Top Markings
7. Top Markings
7.1 Si3406 Top Marking
Figure 7.1. Si3406 Top Marking
Table 7.1. Si3406 Top Marking Explanation
Mark Method:
Laser
Pin 1 Mark:
Circle = 0.50 mm Diameter (Lower-Left Corner)
Font Size:
2.0 Point (28 mils)
Line 1 Mark Format:
Device Part Number
Si3406
Line 2 Mark Format:
Device Type
A = Device Revision A
G = Extended temperature range
M = QFN package
Line 3 Mark Format:
TTTTTT
Manufacturing Trace Code (assigned at assembly)
Line 4 Mark Format:
YY = Year
Assembly Year
WW = Work Week
Assembly Week
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Si3406x Family Data Sheet • Top Markings
7.2 Si34061 Top Marking
Figure 7.2. Si34061 Top Marking
Table 7.2. Si34061 Top Marking Explanation
Mark Method:
Laser
Pin 1 Mark:
Circle = 0.50 mm Diameter (Lower-Left Corner)
Font Size:
2.0 Point (28 mils)
Line 1 Mark Format:
Device Part Number
Si34061
Line 2 Mark Format:
Device Type
A = Device Revision A
G = Extended temperature range
M = QFN package
Line 3 Mark Format:
TTTTTT
Manufacturing Trace Code (assigned at assembly)
Line 4 Mark Format:
YY = Year
Assembly Year
WW = Work Week
Assembly Week
33
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Si3406x Family Data Sheet • Top Markings
7.3 Si34062 Top Marking
Figure 7.3. Si34062 Top Marking
Table 7.3. Si34062 Top Marking Explanation
Mark Method:
Laser
Pin 1 Mark:
Circle = 0.50 mm Diameter (Lower-Left Corner)
Font Size:
2.0 Point (28 mils)
Line 1 Mark Format:
Device Part Number
Si34062
Line 2 Mark Format:
Device Type
A = Device Revision A
G = Extended temperature range
M = QFN package
Line 3 Mark Format:
TTTTTT
Manufacturing Trace Code (assigned at assembly)
Line 4 Mark Format:
YY = Year
Assembly Year
WW = Work Week
Assembly Week
34
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Si3406x Family Data Sheet • Revision History
8. Revision History
Revision 1.1
July, 2022
• Updated Table 5.1 Pin Descriptions on page 19.
Revision 1.0
December, 2018
•
•
•
•
•
Renamed and reordered sections 2.6, 2.7, 2.8, 2.9, and 2.10. Removed section V0.5 section 2.6 and merged with 2.4.1.
Replaced Figure 2.4 Powered Device Voltages on page 6 with revised version.
Replaced Figure 2.5 Hotswap Switch 4-State Machine on page 7 with new version.
Replaced Figure 2.6 Si3406x DC-DC Converter Block Diagram on page 8 with new version.
Updated 2.10 External Wall Adapter Support with further detail on external wall adapter support.
• Updated Figure 2.9 Auxiliary Wall Adapter Connection Example on page 11.
• Updated 4. Electrical Specifications,
• Added min and max current to Peak Current spec.
• Updated Table 4.1 Absolute Maximum Ratings1 on page 14.
• Added junction temperature.
• Updated Table 4.2 Recommended Operating Conditions on page 15.
• Added VPOS-VNEG to VHV_OP spec and updated min voltage based on final characterization data
• Added note on transition voltages for digital input pins.
• Updated Table 4.3 Electrical Characteristics on page 16.
• Reworded and corrected VDET spec.
• Reworded and corrected VCLASS spec.
• Removed IMARK typ spec.
• Added min and max specs to VUVLO_R, VUVLO_F, and VUVLO_HYST based on final characterization data.
• Removed IOVL max and min specs.
• Added max voltage spec to VEXT_DRV based on final characterization data.
• Added min and max frequency to FOSCINT based on final characterization data.
• Removed TBD on DUC.
• Added min and max spec to VFBREF based on final characterization data.
• Added THICCUP spec.
• Added min and max specs to VISNS_OVC and VISNS_LC based on final characterization data.
• Updated TSOFTSTART based on application data and added note.
• Updated all Regulators specs based on final characterization data.
• Updated package thermal characteristics based on final characterization data.
• Added electrical and junction temperature conditions.
• PINTMAX specification typical value corrected to 0.2 W.
• Updated Table 5.1 Pin Descriptions on page 19.
• Updated Vrange.
• Updated Table 5.2 Circuit Equivalent and Description of Die Pads on page 21.
• Updated V15 and V11 descriptions.
35
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Si3406x Family Data Sheet • Revision History
Revision 0.5
February, 2018
• Updated 2. System Overview and 3. Application Examples.
• Added theory of operation and application content.
• Updated Table 4.1 Absolute Maximum Ratings1 on page 14, Table 4.2 Recommended Operating Conditions on page 15, and Table
4.3 Electrical Characteristics on page 16.
• Clarified multiple parameters.
• Added 5.1 Detailed Pin Descriptions.
• Added 6. Packaging including outline and land pattern.
Revision 0.1
August, 2016
• Initial release.
36
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