Si3452
Q UAD H IGH - VO L TAG E P ORT C O N T R O L L E R
FOR P O E AND P O E+ PSE S
Features
INT
VOUT1
RST
DET1
AD1
GND12
AD0
DET2
VOUT2
VEE2
40
39
38
37
36
35
34
33
32
31
DGND
VREF
3
28
AD0
AIN
4
27
AD1
AOUT
5
26
AD2
AGND
6
25
AD2
RBIAS
7
24
AD3
AGND
8
23
RST
NC
9
22
VEE3
VEE4
10
21
AD3
16
17
18
19
20
NC
DET3
VDD
VOUT3
Si3452
(Top View)
SCL
Copyright © 2015 by Silicon Laboratories
VDD
29
15
Rev. 1.5 1/15
Industrial automation systems
Networked audio
IP Phone Systems and iPBXs
Metropolitan area networked WAPs,
cameras, and sensors
WiMAX ASN/BTS and CPE/ODU
systems
30
2
GND34
1
VEE
14
Power over Ethernet Endpoint
switches and Midspans for IEEE Std
802.3af and 802.3at
Supports high-power PDs, such as:
Pan/Tilt/Zoom security cameras
802.11n WAPs
Multi-band, multi-radio WAPs
Security and RFID systems
VEE1
SDA
40-Pin QFN
13
Applications
Pin Assignments
DET4
See page 31.
12
Ordering Information:
11
NC
Programmable architecture supports
IEEE 802.3af (PoE) and IEEE
802.3at (PoE+) PSEs
Programmable current limits for
PoE (350 mA) and PoE+
(600 mA), and custom limits to
850 mA
Per-port current and voltage
monitoring for sophisticated power
management and control
Power policing mode
Robust multi-point detection
Supports 1-Event and 2-Event
classification algorithms
Comprehensive, robust, faultprotection circuitry
Supply undervoltage lockout
(UVLO)
Output current limit and shortcircuit protection
Foldback current limiting
Dual-threshold thermal overload
protection
Fault source reporting for
intelligent port management
VOUT4
Each Si3452 high-voltage port
controller supports four PSE power
interfaces
Programmable current limits for PoE
(15.4 W), PoE+ (30 W), and
proprietary systems (up to 40 W) per
port
I2C interface requires no external
MCU for easy, low-cost management
of 4 to 48 ports by the host system
Unique mixed-signal IC high-voltage
component integration simplifies
design, lowers power dissipation,
minimizes external BOM, and
reduces PCB footprint
Internal low-RON power FETs with
current-sense circuitry
Integrated transient voltage surge
suppressors
Proprietary dV/dt disconnect
sensing methods
Industrial (–40 to 85 °C) operating
temperature
Compact, 6×6 mm2, 40-pin QFN
RoHS-compliant package
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See "9. Pin Descriptions" on page 28.
Si3452
Si3452
Description
When connected directly to the host system or configured in Auto mode, each Si3452 high-voltage port controller
provides all of the critical circuitry and sophisticated power measurement functionality for the high-voltage
interfaces of four complete PSE ports. The Si3452 fully integrates robust, low-RON (0.3 typical) power MOSFET
switches, low-power dissipation current sensing circuitry, and transient voltage surge suppression devices.
The on-chip current sense circuitry and power MOSFETs provide programmable scaling of current limits to match
either PoE (350 mA, 15.4 W), PoE+ (600 mA, 30 W), and extended (800 mA, 40 W) power requirements on a perport basis. Designed for use in Endpoint PSE (e.g., Ethernet switches) or Midspan PSE (e.g., inline power
injectors) applications, each Si3452 also performs the IEEE-required powered device (PD) detection, classification,
and disconnect functionality.
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The flexible architecture enables powered device disconnect detection using Silicon Laboratories' proprietary dV/dt
disconnect sensing algorithm. dV/dt disconnect is an alternative to dc disconnect that requires no additional BOM
components, does not dissipate extra device power, and fully interoperates with all powered devices. Also provided
are multi-point detection algorithms and per-port current and voltage monitoring.
Intelligent protection circuitry includes power supply undervoltage lockout (UVLO), port output current limiting and
short-circuit protection, thermal overload sensing and port shutdown, and transient voltage surge suppressors
capable of protecting the Si3452 from a variety of harsh surge events seen on the RJ-45 interface.
To maximize system design flexibility and minimize cost, each Si3452 connects directly to a system host controller
through an I2C serial interface, eliminating the need for an external MCU. The Si3452 can be set to one of 12
unique addresses, allowing control of up to 48 ports on a single I2C bus.
PER PORT ANALOG
Detection
&
Classification
256 Byte SRAM
MEAS.
MUX
Temp
Sensor
2
Rev. 1.5
Thermal
Prot.
Current
Sense
DET4
DET3
DET2
DET1
VOUT4
VOUT3
VOUT2
VEE4
VOUT1
VEE3
VEE
DGND
VDD
VREF
RBIAS
AOUT
dV/dt
Disconnect
Gate Control,
Current Limit
& Foldback
VREF & Central Bias
AIN
SCL
SDA
INT
I2C
VDD
Voltage
Regulator
& Monitor
AGND
WDT
AMUX
PGA
10b
ADC
AGND
PLL
POR
Channel
Mode
&
Limit
Control
VEE1
8 kByte EPROM
GND12
GND34
AD0
AD1
AD2
AD3
RST
AD1
AD0
HV SPI
&
Port
Control
LV SPI
VEE2
MCU Core
& PSE FSM
AD2
AD3
RST
Functional Block Diagram
Si3452
TABLE O F C ONTENTS
Section
Page
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1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. PSE System-Level Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3. PSE Application Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1. Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2. Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3. Port Turn-On and Power FETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4. Disconnect Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.5. Transient Voltage Surge Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.6. Temperature Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.7. Port Measurement and Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4.8. SMBus/I2C Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5. Register Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
5.1. Interrupt (Registers 0x00–0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2. Port Event (Registers 0x02–0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
5.3. Port Status (Registers 0x06–0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.4. Port Configuration (Registers 0x0A–0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.5. Command and Return Registers (Registers 0x12–0x1C) . . . . . . . . . . . . . . . . . . . . .19
5.6. Device Status Register (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6. Operational Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1. Port Turn On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
6.2. Changing the Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.3. Port Voltage and Current Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7. PCB Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
8. Firmware Release Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.1. I2C Address ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.2. “Sifos” Tester Vtrans_min Issue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.3. PSE-to-PSE Cross Powering Possibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
10. Package Outline: 40-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
11. Recommended PCB Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
12. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
12.1. Evaluation Kits and Reference Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
13. Device Marking Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Rev. 1.5
3
Si3452
1. Electrical Specifications
Unless noted otherwise, specifications apply over the operating temperature range with VDD = +3.3 V and
VEE = –48 V relative to GND.
VDD pins should be electrically shorted. AGND pins, DGND, GND12, and GND34 should be electrically shorted
(“GND”). VEE, VEE1, VEE2, VEE3, and VEE4 should be electrically shorted (“VEE”).
VPort for any port is measured from GND to the respective VOUTn.
Table 1. Absolute Maximum Ratings1
Description
Rating
Unit
VEE to GND
–62 to +0.3
V
VDD to GND
–0.3 to +3.6
V
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Type
VDD1 to VDD2
–0.3 to +0.3
V
Any VEE to any other VEE
–0.3 to +0.3
V
Any GND to any other GND
–0.3 to +0.3
V
SDA, SCL, ADn, RST, INT
(GND – 0.3) to (VDD + 0.3)
V
VREF, AIN, AOUT, RBIAS, OSC
(GND – 0.3) to (VDD + 0.3)
V
VOUTn, DETn
(VEE – 0.3) to (GND + 0.3)
V
DETn Peak Currents During Surge Events2
±5
A
Maximum Continuous Power Dissipation3
1.2
W
Maximum Junction Temperature
125
°C
–55 to 150
°C
260
°C
Supply Voltages
Voltage on Digital Pins
Voltage on Analog Pins
Ambient Storage Temperature
Lead Temperature (Soldering, 10 seconds Maximum)
Notes:
1. Functional operation should be restricted to those conditions specified in Table 2. Functional operation or specification
compliance is not implied at these conditions. Stresses beyond those listed in absolute maximum ratings may cause
permanent damage to the device.
2. See IEEE Std 802.3-2005, clause 33.4, for a description of surge events.
3. If all ports are on with 600 mA load, the power dissipation is 25 °C, –35 V over the full temperature range.
2. 1x mode current limit is enforced during the 60 ms TSTART time.
3. In auto mode, class policing is automatically enabled. In manual mode, ICUT must be programmed manually.
See "5.4. Port Configuration (Registers 0x0A–0x11)" on page 18 for more information.
4. 600 mA is consistent with the IEEE 802.3at draft standard. ICUT is user-programmable in 3.2 mA increments to over
800 mA for non-standard applications.
5. For 2x mode and extreme overload or short-circuit events, TOVLD will dynamically decrease to prevent excessive FET
heating. This is consistent with the 802.3at draft.
Table 7. dV/dt Disconnect Specifications
Description
Symbol
Test Condition
Min
Typ
Max
Unit
10
—
—
mA
Load Current to Prevent
Disconnect
ION
Load Current to
Guarantee Disconnect
IOFF
dV/dt disconnect
—
—
2
mA
TDCDV_DLY
Time from IOFF load current to port
turn off
300
—
400
ms
Disconnect Delay
Rev. 1.5
7
Si3452
Table 8. Port Measurement and Monitoring Specifications
Description
Symbol
Test Condition
Min
Typ
Max
Unit
Port Current Measurement
Offset
IOFFSET
–5
—
5
mA
Port Current Measurement
Tolerance
%TOL
20 mA ≤ IPORT ≤ ICUT. For final
IPORT reading, add offset to% of
reading tolerance.
–4
—
4
%
Min
Typ
Max
Unit
Table 9. SMBus (I2C) Electrical Specifications
VDD = 3.0 to 3.6 V
Symbol
Test Condition
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Description
Input Low Voltage
VIL
SCL, SDA pins
—
—
0.8*
V
Input High Voltage
VIH
SCL, SDA pins
2.2
—
—
V
Output Low Voltage
VOL
SCL, SDA pins,
driving ≤ 8.5 mA
—
—
0.6
V
IL
SCL, SDA pins
—
—
40
µA
Input Leakage Current
*Note: 0.85 V for Tj >–10 °C. This ensures compatibility with Si840x isolators with 3 k pull up. For isolator compatibility over
the full temperature range, use Si860x isolators.
Table 10. Address Pin Electrical Specifications*
VDD = 3.0 to 3.6 V
Description
Symbol
Test Condition
Min
Typ
Max
Unit
Input Low Voltage
VIL
AD0, AD1, AD2, AD3 pins
—
—
0.8
V
Input High Voltage
VIH
AD0, AD1, AD2, AD3 pins
0.7 x VDD
—
—
V
IH , I L
AD0, AD1, AD2, AD3 pins
–10
—
10
µA
Input Leakage Current
*Note: At power-up, these pins are logic inputs. A 10 k pull up or pull down resistor is used for address selection. After
address recognition, the pins are used for internal communications.
8
Rev. 1.5
Si3452
Table 11. SMBus (I2C) Timing Specifications (see Figure 1)
VDD = 3.0 to 3.6 V
Description
Symbol
Test Condition
Min
Typ
Max
Unit
Serial Bus Clock
Frequency
fSCL
0
—
400
kHz
SCL High Time
tSKH
600
—
—
ns
SCL Low Time
tSKL
1.3
—
—
μs
SCL, SDA Rise Time
tR_SCL
20
—
300
ns
SCL, SDA Fall Time
tF_SCL
20
—
150
ns
tBUF
Between START and STOP
conditions.
1.3
—
—
μs
Start Hold Time
tSTH
Between START and first low SCL.
600
—
—
ns
Start Setup Time
tSTS
Between SCL high and START
condition.
600
—
—
ns
Stop Setup Time
tSPS
Between SCL high and STOP
condition.
600
—
—
ns
Data Hold Time
tDH
200
—
—
ns
Data Setup Time
tDS
200
—
—
ns
—
—
100
ms
—
—
5
ms
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Bus Free Time
Time from Hardware or
Software Reset until Start
of I2C Traffic
tRESET
Delay from Event to INT
Pin Low or from Clear-OnRead to INT Pin High
tINT
Reset to start condition
Notes:
1. Not production tested (guaranteed by design).
2. All timing references measured at VIL and VIH.
3. The Si3452 will stretch (pull down on) SCK during the ACK time period if required. The maximum SCL stretching is
10 µsec; so, SCL only needs to be bidirectional for I2C bus speeds over 50 kHz.
t R_SCL
fSC L
t F_SC L
t SKH
tSKL
SCL
tBU F
tST H
SDA
t DS
D7
D6
tD H
D5
D4
Start Bit
tSPS
D3
D0
Stop Bit
Figure 1. I2C Timing Diagram
Rev. 1.5
9
Si3452
Table 12. Interrupt (INT) Specifications
Description
Symbol
Test Condition
Min
Typ
Max
Unit
VOL
INT pin driving ≤ 8.5 mA
—
—
0.6
V
Min
Typ
Max
Unit
Nominal VREF Input
—
1.1
—
V
Reference Tolerance
—
—
1
%
–10
—
+10
µA
Output Low Voltage
Table 13. Input Voltage Reference Specifications
Description
Test Condition
Input current
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VREF Loading
Symbol
10
Rev. 1.5
Si3452
I2C
SCL
Host
Controller
I2C
INT
Si8405 Digital
Isolator
OTP
RST
RAM
PSE State
Machines
and
Measurement
Subsystem
Mixed Signal
Resources
High Voltage Interface
SDA
4 Ports of PoE+
2. PSE System-Level Diagrams
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Si3452
Figure 2. 4-Port System with Direct Host Connection
3. PSE Application Diagrams
+3.3 V
Host / Switch
Tie high
or low to
select
address
Si8405
Bidirectional
Isolator
AD0
AD1
AD2
AD3
AD0
AD1
AD2
AD3
4x10 k
VDD
AGND DGND
GND12/34
SCL
SDA
INT
DET4
Si3452
RST
DET3
DET2
DET1
RBIAS
44.2 k
1%
VEE VEE[4:1] VOUT4 VOUT3 VOUT2 VOUT1
–54 V
To Magnetics
VREF
1.1 V
(e.g. TLV431)
PORT1
PORT2
PORT3
PORT4
Figure 3. 4-Port Application Diagram Using dV/dt Disconnect and I2C Host Interface
Rev. 1.5
11
Si3452
4. Functional Description
Integrating four independent, high-voltage PSE port interfaces, the Si3452 high-voltage port controller enables an
extremely flexible solution for virtually any PoE or PoE+ PSE application. The Si3452 provides all of the highvoltage Power over Ethernet PSE functions.
Each port of the Si3452 integrates all high-voltage PSE controller functions needed for a quad-port PoE design,
including the power MOSFET, efficient current-sensing circuitry, transient voltage surge suppressor, and multiple
detect and disconnect circuits. The external BOM is typically only a single filter capacitor on each high-voltage port.
When a PD device has been properly detected and classified, the port is powered by a –54 V nominal supply with
continuous monitoring of voltage and current for feedback to the host system.
In addition to the required IEEE features, the Si3452 includes many additional features:
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Per port current / voltage monitoring and measurement
Support for 1-Event and 2-Event classification algorithms
Start up in shutdown or auto mode
Alternative A (typically used for endpoint systems) or Alternative B (typically used for midspan systems)
detection timing
4.1. Detection
The Si3452 has per-port signature detection that satisfies the IEEE Std 802.3™-2005 specifications. However, by
utilizing a 3-point voltage-forced detection method, the Si3452 yields robust recognition of valid and invalid
powered device (PD) signatures, properly identifying signatures often mischaracterized by other detection
techniques.
3 point
detection
2 event
classification
Port powerup
Figure 4. PSE Sequencing (3-Point Detection Followed by 2-Event Classification and Powerup)
Vport Relative to GND
The detection circuitry performs the function of setting the output voltage on any channel to the proper value for
detection or classification and then measuring the resulting line current.
A typical detection cycle consists of applying 4 V, then 8 V, then 4 V again with the current limit set to 3 mA. The
current is measured after an appropriate settling time. For a valid PD, the detection signature must be compliant
with the detection voltage both increasing and decreasing.
12
Rev. 1.5
Si3452
4.2. Classification
Following a successful PD detection, the classification phase will be automatically initiated in all operational
modes. During this phase, a single measurement will be made at 18 V to determine how much power the PD
device will draw under maximum loads per the IEEE 802.3af and 802.3at standards. The current limit during this
test mode is 60 mA nominal.
The Si3452 supports 1-Event and 2-Event classification. When operating in PoE (15.4 W) mode results in 2-Event classification probes. The 1-Event
classification is compliant to IEEE standard 802.3-2005. 2-Event classification is compliant to draft IEEE P802.3at.
4.3. Port Turn-On and Power FETs
The FET is turned on with a gate drive that results in a very low-noise turn-on waveform with a slew rate of less
than 1 V/µsec (See Figure 5).
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The power FET switch on each port has been sized to have a typical ON resistance of approximately 0.3 . The
shunt resistor for current measurement has also been set to 0.1 . Including interconnection and process variation,
the total resistance to VEE for a port that is on is 0.6 (max). This limits the maximum power dissipation per
channel to < 250 mW when the operating current is 600 mA, the maximum current allowed by the IEEE 802.3at
PoE+ standard.
The FET has a programmable operating current limit. Each channel can be set to support output currents of
400 mA or 800 mA minimum.
In addition to the normal current limit, there is a short circuit current shutdown approximately 25% greater than the
nominal current limit. If there is a transient current surge where the current ramps up faster than the programmed
current limit can respond, the gate drive voltage is clamped immediately to VEE. The clamp is enabled for at least
10 µs, which allows the normal current circuitry to respond.
Another important protection feature is foldback current limiting. When VOUT is near VEE, the current limit is at
maximum. As the VDS of the driver switch increases (and VOUT is closer to ground), the current limit goes to its
lowest level. The amount of the foldback current is scaled proportionally with the programmed current limit.
Figure 5. Turn-On Waveform—Vport Relative to GND
Rev. 1.5
13
Si3452
4.4. Disconnect Detection
The dV/dt disconnect function can be used to detect a disconnected device without using dc disconnect or ac
disconnect.
In dV/dt disconnect mode, the FET current limit is switched to 7.5 mA. If the voltage across the FET increases, a
load is assumed to be present, and the FET current limit is automatically switched back to its pre-selected value. If,
after 350 ms, the FET voltage has not increased, there is no load present, and the FET is turned off.
In addition to operating in a manner functionally distinct from DC disconnect, dV/dt disconnect requires no
additional external components and fully interoperates with all powered device DC Maintain Power Signatures. For
more information, see “AN399: dV/dt Disconnect and the IEEE 802.3 PoE Standard”.
4.5. Transient Voltage Surge Suppression
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The Si3452 features robust on-chip surge protectors on each port; this is an industry first. This unique protection
circuitry acts as an active device that can withstand lightning-induced transients as well as large ESD transient
events. When the port voltage exceeds its protection limit and the current reaches a triggering threshold, current is
shunted from the port to the ground pins.
Internal circuitry is provided to protect the line outputs from externally-coupled fault currents. These are transient
currents of up to 5 A peak.
The operation of the protection circuits depends on the operating mode of the channel switch and the direction of
the fault current. The clamping operation is performed on the detect pin.
The switch itself will also be protected by the current limit. If the transient lasts long enough to heat up the die, then
the temperature sense circuit will shut off the switch, and all the fault current will flow through the clamp diode.
4.6. Temperature Sense
A temperature sense signal is used in conjunction with the current limit status signals from the gate drive blocks.
Any channel that is generating excess heat is assumed to be operating in current limit mode, with both high voltage
drop and high current.
If the port is in PoE mode, an overload will generally not result in thermal shutdown before the 60 ms ICUT period. If
the port is in PoE+ mode, an overload may cause the port to shut down prior to the 60 ms ICUT period. In either
case, the event is reported as ICUT. The faster shutdown in PoE+ mode is consistent with and specifically allowed
by the 802.3at draft and provides much more robust overload protection than is possible with external FETs.
In addition, there is a thermal shutdown if the package temperature exceeds 120 °C. If this threshold is reached, all
output drivers are turned off and detection modes are disabled. This secondary threshold limit guards against the
possibility that the overheating is not caused by a driver operating in current limit.
4.7. Port Measurement and Monitoring
VEE monitoring in conjunction with port current monitoring allows measurement of port power. Port power
monitoring, dynamic power allocation via LLDP*, and port power policing allow efficient power supply sizing.
The Si3452 is factory-calibrated and temperature-compensated for the following measurements:
Port current measurement. These measurements are auto-ranged and scaled to a 16 bit number at 100 µA per
bit. Port current accuracy is ±4% ± 2 mA.
VEE is measured with a scale of 64 V. The measurement is reported as a 16-bit number scaled at 1 mV per bit.
VEE measurement accuracy is ±4% over the valid VEE range.
*Note: LLDP = Link Layer Discovery Protocol. Refer to IEEE 802.3at (draft) and IEEE 802.1AB for more information.
14
Rev. 1.5
Si3452
4.8. SMBus/I2C Interface Description
The I2C interface is a two-wire, bidirectional serial bus. The I2C is compliant with the System Management Bus
Specification (SMBus), version 1.1 and compatible with the I2C serial bus. Reads and writes to the interface by the
system controller are byte-oriented with the I2C interface autonomously controlling the serial transfer of the data. A
method of extending the clock-low duration is available to accommodate devices with different speed capabilities
on the same bus. The I2C provides control of SDA (serial data), SCL (serial clock) generation and synchronization,
arbitration logic, and START/STOP control and generation.
A typical I2C transaction consists of a START condition followed by an address byte (Bits7–1: 7-bit slave address;
Bit0: R/W direction bit), one or more bytes of data, and a STOP condition. Each byte that is received (by a master
or slave) must be acknowledged (ACK) with a low SDA during a high SCL (see Figure 6). If the receiving device
does not ACK, the transmitting device will read a NACK (not acknowledge), which is a high SDA during a high
SCL.
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The direction bit (R/W) occupies the least-significant bit position of the address byte. The direction bit is set to logic
1 to indicate a “READ” operation and cleared to logic 0 to indicate a “WRITE” operation. All transactions are
initiated by a master, with one or more addressed slave devices as the target. The master generates the START
condition and then transmits the slave address and direction bit. If the transaction is a WRITE operation from the
master to the slave, the master transmits the data one byte at a time, waiting for an ACK from the slave at the end
of each byte.
For READ operations, the slave transmits the data waiting for an ACK from the master at the end of each byte. At
the end of the data transfer, the master generates a STOP condition to terminate the transaction and free the bus.
Figure 6 illustrates a typical SMBus/I2C transaction.
Silicon Laboratories recommends the use of bidirectional digital isolators, such as the Si840x, to isolate the I2C
communications interface between the Si3452 high-voltage port controllers and the system host controller.
Slave Addr ess
0
ST ART
1
0
A3
A2 A1
Register Address
A0 R/W#
A7
A6 A5
A4 A3 A2
ACK by IC
F ixed IC
Address
Write Data
A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
ACK by IC
ACK by IC
Write Sequence
Pin Set IC
Address
Setup Register Addr ess
0
1
0
A3 A2
A1 A0 R/W#
ACK by IC
Fixed IC
Addr ess
Pin Set IC
Addr ess
Transfer Data to Setup Address
Register Address
Slave Address
START
ST OP by Master
A7 A6
A5 A4
Slave Address
A3 A2 A1
A0
0
1
0
A3
A2 A1
ACK by IC
START
A0 R/W#
ACK by IC
F ixed IC
Address
Read Sequence
Register Data
D7 D6 D5 D4 D3 D2 D1 D0
Not ACK by Master
STOP by Master
Pin Set IC
Addr ess
Figure 6. Typical I2C Bus Transactions
The Si3452 does not support the alert response address (ARA) protocol. Polling is used to determine which
controller is interrupting in an interrupt-driven system.
Rev. 1.5
15
Si3452
4.8.1. Address Pins
Table 14. Address Pin Assignments
Pin #
Pin Name
21
AD3
24
AD3
25
AD2
26
AD2
27
AD1
28
AD0
34
AD0
36
AD1
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Pins with the same name must be externally connected and then tied high or low via a weak (10 k) pull up or pull
down to establish the device address at power up. The Si3452 powers up in either Auto mode or Shutdown mode
depending on the ordering part number. For more information, see "12. Ordering Guide" on page 33.
4.8.2. Address Format
The address byte of the I2C communication protocol has the following format:
Table 15. I2C Address Byte Protocol
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
0
AD3
AD2
AD1
AD0
R/W
AD3, AD2, AD1, and AD0 are the pin-selected address bits (pull up = 1; pull down = 0). For the R/W bit, see
Figure 6. The device will also respond to the global address, 0x30. The Si3452 does not support bus arbitration;
so, a global read command will generally give an invalid result. Global writes can be useful for initialization as well
as for shutting down low-priority ports. Table 16 lists the valid device addresses:
Table 16. Address Selection
16
AD3
AD2
AD1
AD0
Address
Valid
0
0
0
0
0x20
Y
0
0
0
1
0x21
Y
0
0
1
0
—
N
0
0
1
1
—
N
0
1
0
0
0x24
Y
0
1
0
1
0x25
Y
0
1
1
0
—
N
0
1
1
1
—
N
1
0
0
0
0x28
Y
1
0
0
1
0x29
Y
1
0
1
0
0x2A
Y
1
0
1
1
0x2B
Y
1
1
0
0
0x2C
Y
1
1
0
1
0x2D
Y
1
1
1
0
0x2E
Y
1
1
1
1
0x2F
Y
Rev. 1.5
Si3452
5. Register Interface
The register types are described in the following sections. Refer to Table 19 on page 20 for a complete map of the
registers.
5.1. Interrupt (Registers 0x00–0x01)
An interrupt (INT pin low) is generated if any bit of the Interrupt register (register 0x00) is true. The Interrupt register
contains the information about which port is generating the interrupt or if the interrupt is due to a global event.
The port interrupt is generated by the port event register masked by the interrupt mask register.
Port event = (tSTART Event AND tSTART mask) OR (tICUT Event AND tICUT mask) OR (Rgood_CLS_event AND
Rgood_CLS_mask) OR (DET_COMPL_EVENT AND DET_COMPL_MASK) OR (PwrGood_change AND
Pwrgood_change_MASK) OR (Penable_event AND Penable_mask)
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The device event bit of the interrupt register is set if there is a change in the VEE or temperature status in register
0x1D. Reading 0x1D clears the event.
5.2. Port Event (Registers 0x02–0x05)
This register contains bits that become true if the event has occurred. The registers are Clear On Read (COR) so
that reading these registers will clear the INT pin if the INT pin is being held low due to a port event.
tSTART is an event bit indicating an overload occurred for all but 5 ms of the initial 60 ms start up time.
tICUT is an event bit indicating that an overload condition has existed for greater than 60 ms after the first 60 ms.
tICUT has a 16:1 up/down counter so that, if the overload is present at less than a 6.66% cycle, the port will not
shut down. Overload is defined as I>ICUT or port voltage not within 2 V of VEE. The port is turned off on this
event. A tICUT event is also generated if the port is shutdown due to an overload or due to the protection clamp
turning on. If the port is set to auto mode, it will attempt to re-power after >750 ms if there is a good detection
signature.
Rgood CLS indicates classification has been completed. Classification is only attempted after an Rgood; so, if
this bit is set, it indicates that detection gave an Rgood and classification is complete.
DET compl indicates the completion of a detection cycle. Normally, this bit will be masked. The DET complete
bit is used for legacy detection via modified link pulses. If the link pulse is returned indicating a PD is present,
then, normally, a detection is done, and the port is powered only if the result is not a short. In some cases, it
may be desirable to deny power to a port where an overload has been detected until the port is unplugged. In
this case, the Ropen result will be used to indicate the port has been unplugged and detection and classification
can resume.
Disconnect event indicates a disconnect has occurred. DC power was removed due to the dV/dt disconnect.
Overload conditions or loss of VEE turns off ports but does not generate a disconnect event.
Pgood indicates the port has been turned on and did not shut down during the Tstart time.
Penable indicates a port has been turned on.
5.3. Port Status (Registers 0x06–0x09)
These registers specify the port status. They are read-only registers.
Pwr good indicates that the port has been turned on and the port voltage is within 2 V of VEE.
Pwr Enable indicates the port has been turned on.
The three class status bits indicate the last classification result for that port. If a classification has not been done or
if the port is shut down with no new classification result, the class status is reported as unknown.
The three detect status bits indicate the last detection result for that port. If a detection has not been done or if the
port is shut down with no new detection result, the detection status is reported as unknown.
Rev. 1.5
17
Si3452
5.4. Port Configuration (Registers 0x0A–0x11)
These registers indicate the port configuration and are read/write registers.
The port priority bit is set if the port is not high priority. Low-priority ports are shut down when the shutdown lowpriority ports command is issued.
The “PoE+” bit specifies the dc current limit at either 425 mA or 850 mA nominal*.
*Note: The PoE+ mode should be set correctly according to the electrical design of the PSE circuit (transformer and conductor
current carrying capacity). The PoE+ port mode can safely be changed prior to port turn-on, but changes after port turnon do not have an immediate effect and are not recommended.
“Disconnect enable” must be set for power to be removed if there is a disconnect. “Port mode” is set according to
Table 17.
Table 17. Port Mode Selection
Mode
Description
00b
Shutdown
01b
Manual
10b
Semiauto
Detection is done and classification is done for Rgood, but the port does
not power.
11b
Auto
Detection classification and port powering are all automatic with no host
intervention required. ICUT and ILIM are automatically set according to
the PoE+ mode and classification result.
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Port Mode Setting
B1, B0
The power is shut down with no detection pulses.
A command to manually power the port is ignored.
The port can be powered by the manual power command.
ICUT is the nominal current level at which the port will automatically power down if ICUT is exceeded for 60 ms. It
can be set with 3.2 mA resolution. The accuracy of current measurement is approximately 5%; so, ICUT is normally
set 7% higher than the supported current level. ICUT is automatically set based on the classification result and
PoE+ mode. The automatically-set ICUT level is appropriate for a 45 V minimum system power supply for classes
0–3 and for a 51 V minimum power supply for PoE+ mode. This feature is classification policing.
If the Si3452 is in the semi-auto mode, ICUT will not be updated according to the classification result. This means
that if it is desired to set ICUT at port turn-on, this should be done before the port is turned on.
Once a port is turned on, ICUT can be changed dynamically. It is often undesirable to use a low value of ICUT during
port turn-on because inrush can trigger the ICUT event. For this reason, it is normal to allow the port to turn on with
the automatic ICUT setting and then later change this value after port current has stabilized and also if the PD and
PSE have negotiated for a different ICUT value based on the PoE L2 power negotiation protocol (LLDP).
The Si3452 supports 2-Event classification as defined in the IEEE 802.3at draft. 2-event classification is an
alternative to L2 power management where the PSE advertises it is capable of PoE powering by generating two
classification pulses. 2-Event classification is only supported for auto mode. If the Si3452 is in auto mode and the
first event classification result is Class 4, the mark, second event, and second mark are performed. Power is
applied only if the second event is also Class 4. If the second event is not Class 4, the classification error is
reported, and the port will not power. If the port is in manual mode, classification is done prior to turning on the port.
18
Rev. 1.5
Si3452
5.5. Command and Return Registers (Registers 0x12–0x1C)
The global command register enables manual port turn-on or turn-off, chip reset, port reset, and measurement of
port current and VEE. Register 0x12 is a Write only register. See Table 24 on page 24 for a list of all available
commands.
Consecutive writes to the global command register require delay to be inserted between some commands. Refer to
Table 24 on page 24 for the delay requirements.
If the command results in a numerical return value, that value is stored in the measurement registers, which are
read-only. Each of the five possible measurements results in a 2 byte return value, and that value is stored in a
unique register. VEE is encoded in mV units; so, the full scale is 65.535 V. Iport is encoded in 100 µA units; so, the
full scale is 6.5535 A.
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The output data is updated by the proper command register write operation (see Table 23). This means that the
numerical value of the port current or VEE voltage in the measurement register will be the value at the time the
command was issued. If the port turns off due to an overload or disconnect, the port current register contents will
not be set to zero. If a command to read port current is issued and the port is off, the return value will be zero.
5.6. Device Status Register (0x1D)
The device event bits are listed in Table 18.
Table 18. Device Status Bits
Bit
Description
B6—OverTemp
The Si3452 has per-port thermal shutdown sensors as well a global thermal shutdown
at a slightly higher temperature. The global thermal shutdown bit of the device event
register is set if this occurs.
B5—VEE UVLO
VEE UVLO. The part is put in its reset state if VEE is not in a valid range.
The Device status register is RO. The VEE, UVLO, and overtemp bits reflect the device status. They are set if VEE
or temperature is out of range and reset if the VEE or temperature is in range. Bit 6 of the Interrupt register is set if
there is a change in the overtemp status (bit 6 of 0x1D), and bit 5 of the Interrupt register is set if there is a change
in the VEE UVLO status (bit 5 of 0x1D). Reading register 0x1D clears these bits of the Interrupt register but does
not clear the device status register.
In addition, bit B0 indicates whether or not detection back-off is used. For PSEs that are wired as Alternative B
(power on the spare pair–typically used for midspans), the time between detection pulses is increased to slightly
over two seconds to avoid interference with Alternative A (power on the data pair–typically used for endpoints). Bit
B0 can be toggled using the 0x10 command code.
Rev. 1.5
19
Si3452
Table 19. Si3452 Register Map
Address Register Name
Type
B3
B2
B1
B0
Register
Content at
Power Up
Port 4 event
Port 3 event
Port 2 event
Port 1 event
0x00
Disconnect
mask
PwrGood mask
PwrEn mask
0x85
DET compl
Disconnect Ev
PwrGood
Change
PwrEn
Change
0x00
Rgood CLS
DET compl
Disconnect Ev
PwrGood
Change
PwrEn
Change
0x00
tICUT Event
Rgood CLS
DET compl
Disconnect Ev
PwrGood
Change
PwrEn
Change
0x00
tSTART Event
tICUT Event
Rgood CLS
DET compl
Disconnect Ev
PwrGood
Change
PwrEn
Change
0x00
PwrGood
Status
PwrEnable
Status
CLS Stat B2
CLS Stat B1
CLS Stat B0
DET Stat B2
DET Stat B1
DET Stat B0
0x00
PwrGood
Status
PwrEnable
Status
CLS Stat B2
CLS Stat B1
CLS Stat B0
DET Stat B2
DET Stat B1
DET Stat B0
0x00
PwrGood
Status
PwrEnable
Status
CLS Stat B2
CLS Stat B1
CLS Stat B0
DET Stat B2
DET Stat B1
DET Stat B0
0x00
PwrGood
Status
PwrEnable
Status
CLS Stat B2
CLS Stat B1
CLS Stat B0
DET Stat B2
DET Stat B1
DET Stat B0
0x00
Port priority
PoE+
Discon En
Port Mode B1
Port Mode B0
00000100b
Port priority
PoE+
Discon En
Port Mode B1
Port Mode B0
00000100b
Port priority
PoE+
Discon En
Port Mode B1
Port Mode B0
00000100b
Port priority
PoE+
Discon En
Port Mode B1
Port Mode B0
00000100b
B4
B3
B2
B1
B0
0x75
B7
B6
B5
B4
Overtemp
change
VEE UVLO
change
tSTART mask
tICUT mask
tSTART Event
tICUT Event
Rgood CLS
tSTART Event
tICUT Event
tSTART Event
0x00
Interrupt Reg 1
RO
0x01
Interrupt Mask 1
RW
Port Events
0x02
Port 1 Events
COR
0x03
Port 2 Events
COR
0x04
Port 3 Events
COR
0x05
Port 4 Events
COR
0x06
Port 1 Status
RO
0x07
Port 2 Status
RO
0x08
Port 3 Status
RO
0x09
Port 4 Status
RO
Status
Configuration1
0x0A
Port 1 Config
RW
0x0B
Port 2 Config
RW
0x0C
Port 3 Config
RW
0x0D
Port 4 Config
RW
0x0E
Port 1 ICUT
RW
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Interrupts
Device status mask
B7
B6
B5
Rgood CLS mask DET compl mask
Notes:
1. Register content at Power Up is shown for the Si3452 Shutdown Mode part. Refer to "12. Ordering Guide" on page 33 to order Auto Mode parts with different default settings. This
register can be changed via the host. Refer to Table 17 on page 18 for register variations.
2. B0 Alternative B timing is set to 0x01 if using Alternative B detect timing. Refer to "5.6. Device Status Register (0x1D)" on page 19 and "12. Ordering Guide" on page 33.
20
Rev. 1.5
Si3452
Table 19. Si3452 Register Map (Continued)
Type
B7
B6
B5
B4
B3
B2
B1
B0
Register
Content at
Power Up
Port 2 ICUT
RW
B7
B6
B5
B4
B3
B2
B1
B0
0x75
0x10
Port 3 ICUT
RW
B7
B6
B5
B4
B3
B2
0x11
Port 4 ICUT
RW
0x0F
Global Device
0x12
Command Register
WO
0x13
VEE MSB
RO
0x14
VEE LSB
RO
0x15
Current P1
MSB
RO
0x16
Current P1 LSB
RO
0x17
Current P2
MSB
RO
0x18
Current P2 LSB
RO
0x19
Current P3
MSB
RO
0x1A
Current P3 LSB
RO
0x1B
Current P4
MSB
RO
0x1C
Current P4 LSB
RO
0x1D
Device Status2
RO
0x60
Hardware
Revision
RO
0x61
Firmware Revision
RO
Revision
B1
B0
0x75
B5
B4
B3
B2
B1
B0
0x75
CMD Code B5
CMD Code B4
CMD Code B3
CMD Code B2
CMD Param
B1
CMD Param
B0
0x00
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Address Register Name
B7
B6
OverTemp
VEE UVLO
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Alternative B
Timing
0x00
Notes:
1. Register content at Power Up is shown for the Si3452 Shutdown Mode part. Refer to "12. Ordering Guide" on page 33 to order Auto Mode parts with different default settings. This
register can be changed via the host. Refer to Table 17 on page 18 for register variations.
2. B0 Alternative B timing is set to 0x01 if using Alternative B detect timing. Refer to "5.6. Device Status Register (0x1D)" on page 19 and "12. Ordering Guide" on page 33.
Rev. 1.5
21
Si3452
Table 19. Si3452 Register Map (Continued)
Type
0x62
Firmware Revision
RO
0x63
Firmware Revision
RO
B7
B6
B5
B4
B3
B2
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Address Register Name
B1
B0
Register
Content at
Power Up
Notes:
1. Register content at Power Up is shown for the Si3452 Shutdown Mode part. Refer to "12. Ordering Guide" on page 33 to order Auto Mode parts with different default settings. This
register can be changed via the host. Refer to Table 17 on page 18 for register variations.
2. B0 Alternative B timing is set to 0x01 if using Alternative B detect timing. Refer to "5.6. Device Status Register (0x1D)" on page 19 and "12. Ordering Guide" on page 33.
22
Rev. 1.5
Si3452
Table 20. Si3452 Detect Encoding
Condition
000b
Unknown
001b
Short
010b
Reserved
011b
Rlow
100b
Good
101b
Rhigh
110b
Ropen
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Value
111b
Reserved
Table 21. Si3452 Class Encoding
Value
Condition
000b
Unknown
001b
Class 1
010b
Class 2
011b
Class 3
100b
Class 4
101b
Probes Not Equal
110b
Class 0
111b
Class Overload
Table 22. Si3452 Port Mode Encoding
Value
Condition
00b
Shutdown
01b
Manual
10b
Semiauto
11b
Auto
Rev. 1.5
23
Si3452
Table 23. Si3452 Port Configuration
Class
Auto Mode Setting of
ICUT Register
ICUT Nominal
Ilim Nominal*
0 or 1 don’t care
1
0x1E
97 mA
425 mA
0 or 1 don’t care
2
0x35
170 mA
425 mA
0 or 1 don’t care
0/3
0x75
375 mA
425 mA
0
4
0x75
375 mA
425 mA
1
4
0xC9
640 mA
850 mA
PoE+ bit
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*Note: During initial port turn-on (TSTART time of 60 ms), the current limit is set to 425 mA, even in PoE+ mode.
Table 24. Si3452 Command Codes
CMD Register
[B5..B2]
[B1..B0] Command
Parameter
2 Byte Return
Value
Command
Delay1
Power on port
0x04 | port no
0001b
2 bit port number2
—
15 ms
Power off port
0x08 | port no
0010b
2 bit port number
—
15 ms
Reset port
0x0C | port no
0011b
2 bit port number
—
15 ms
Toggle detection
back-off timing3
0x10
0100b
NA
—
15 ms
Reset chip
0x14
0101b
NA
—
100 ms
Get VEE
0x18
0110b
NA
VEE in mV units
0 ms
0x1C | port no
0111b
2 bit port number
Port current in
100 µA units
0 ms
0x20
1000b
NA
—
15 ms
Command
Read port current
Shut down
low-priority ports
Notes:
1. The host should delay for at least these specified times before writing to the command register again.
2. Port 1 has 2 bit port number 0x00; port 2 is 0x01, etc.
3. This command toggles bit 0 of Register 0x1D. When bit zero is set, the detection back-off of 2 seconds is implemented
(alternative B or “midspan” mode).
24
Rev. 1.5
Si3452
6. Operational Notes
6.1. Port Turn On
If the port is turned on by putting it in auto mode, the Si3452 will take care of all specified timing, and it will take
care of the two-event classification if the first event result is Class 4 and PoE+ mode is enabled. However, if
automatic mode operation is not desired after port turn-on, the port should be set to semi-auto or manual mode
once it has powered. In automatic mode, ICUT is set according to the classification result.
The port turn-on command is used to turn on a port in semi-auto or manual mode. If the port is turned on in semiauto mode, turn-on is delayed until the next detection and classification. If the detection or classification result is
not valid, the port will not power. If the classification is Class 4 and PoE+ mode is enabled, a 2-event classification
is given. ICUT setting is not automatic for port turn-on in semi-auto or manual mode.
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If the port is turned on by putting it in manual mode, the normal sequence is to start with the port in semi-auto mode
and interrupt on a classification complete, which indicates that there is a valid PD signature and that a classification
result is available. Based on the classification result, the host can make a decision to apply power or not. The IEEE
standard requires that a port be powered within 400 ms of a valid detect complete. It is also desirable to power the
port prior to the start of the next detection pulse, which can occur in as little as 300 ms. Therefore, it is
recommended that ports be powered in under 250 ms from the class complete interrupt when using the manual
mode turn-on command.
Using manual mode turn-on, detection is not done prior to port turn on, but classification is always performed just
prior to port turn on. Ports are turned on in manual mode regardless of the classification result. 2-event
classification is performed if the first event result is Class 4 and the port is enabled for PoE+ mode. The manual
mode classification step does not generate a classification complete flag because it is assumed that the
classification was already done in semi-auto mode and the host has already made the decision to grant power.
During the initial 60 ms (Tstart) time of port turn-on, 1x current limit and ICUT = 375 mA (nominal) is enforced. After
Tstart, if the port is not overloaded, Pgood is set to true, and ICUT and 1x or 2x current limit will follow the I2C
register settings. In auto mode, the I2C registers are set according to the classification result, but, if desired, they
can be overwritten after Pgood becomes true. After Tstart, 2x current limit is always allowed if PoE+ mode is
enabled.
6.2. Changing the Interrupt Mask
The INT register and INT pin are always synchronized. However, there can be up to a 5 ms delay between an
event that causes or clears an interrupt and the update of the register and pin.
Thus, if the INT mask register is changed to clear an interrupt or to block an interrupt source, there can be up to a
5 ms delay between the change of the INT mask register and the resultant change in the INT register and INT pin.
Generally, use of the mask register to clear interrupts is not recommended; it is better to clear an interrupt by
reading the appropriate COR register.
6.3. Port Voltage and Current Measurements
Port current voltage and current are reported as of the time the measurement command is written to register 0x12.
Spikes of current or other momentary current changes are not filtered. It may be desirable to add a ~1 second
averaging filter to reported current when using port current information for power management decisions.
Rev. 1.5
25
Si3452
7. PCB Layout Guidelines
Following are some PCB layout considerations. See also "12.1. Evaluation Kits and Reference Designs" on page
33 for reference design information. Please visit the Silicon Labs technical support web page at
www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to request support for your design,
particularly if you are not closely following the recommended reference design.
Due to the high current of up to 800 mA per port, the following board layout guidelines apply. In addition, contact
Silicon Laboratories for access to complete PSE reference design databases including recommended layouts.
The VEE1, VEE2, VEE3, and VEE4 pins can carry up to 800 mA and are connected to a VEE bus. The VEE bus for
a 24 port PCB layout can thus carry as much as 20 A current. With 2 oz. copper on an outer layer, a bus of 0.4
inches is needed. For an inner layer, this increases to a 1 inch wide bus. Use of large or multiple vias is required for
properly supporting the 800 mA per channel operating current. The VEE pin does not carry high current and can be
connected directly to the bus as well. The best practice is to devote an entire inner layer for VEE power routing.
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Similarly, GND1/2 and GND3/4 pins can carry up to 1.6 A per pin, and the GND return bus should be at least as
wide as the VEE bus described above. The best practice is to devote an entire inner layer for ground power routing.
The ground power plane does not generally have a high frequency content (other than external faults); so, it is
generally acceptable to use the ground power plane as a ground signal plane and tie AGND and GND12, GND34
to this plane as well.
The VOUTn pins carry up to 800 mA dc and up to 5 A in faults; so, a 20 mil trace with wide or multiple vias is also
recommended. The VDETn pins also carry fault current; so, this pin connection to VOUTn needs to use 20 mil
traces and wide or multiple vias where needed.
The VDD currents are not large; so, it is acceptable to route the VDD nodes on one of the outer layers.
If care is taken to avoid disruption of the high current paths, VDD can be globally routed on one of the power planes
and then locally routed on an inner or outer layer.
To avoid coupling between surge events and logic signals, it is recommended that VOUTn traces be routed on the
side opposite the I2C interface pins.
The thermal pad of the Si3452 is connected to VEE. At full IEEE 802.3at current of 600 mA on each port, the
dissipation of the Si3452 is up to 1.2 W; so, multiple vias are required to conduct the heat from the thermal pad to
the VEE plane. As many as 36 small vias provide the best thermal conduction.
26
Rev. 1.5
Si3452
8. Firmware Release Notes
Devices marked with Revision 02 (see "13. Device Marking Diagram" on page 34) have the firmware revision
registers set as 0x61 = 0x00; 0x62 = 0x02, and 0x63 = 0x51 (0.2.81).
The following are known issues:
8.1. I2C Address ACK
Issue: Very rarely, the Si3452 may not ACK the I2C address byte.
Impact: This is allowed in the I2C specification.
Workaround: Retransmit the address byte if there is an ACK failure.
8.2. “Sifos” Tester Vtrans_min Issue
Issue: The Si3452 may occasionally fail the “Vtrans_min” test as applied by Sifos PoE test equipment.
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Impact: A small transient excursion beyond the minimum voltage specified in this test is a function of filter
capacitance on the port output. Normally, this small remaining voltage transient is completely filtered by the
minimum input capacitance of an attached powered device.
Mitigation/Workaround: The voltage transient may be filtered by adding capacitance to the output port within the
PoE specification maximum of 0.5 µF.
8.3. PSE-to-PSE Cross Powering Possibility
Issue: If ports on two Si3452 PSE devices operating in Auto mode are directly connected PSE-to-PSE, their
relative detect cycles may, on rare occasions, coincide so that one PSE port detects the other PSE port as having
a valid PD signature and then applies PoE power to the other.
Impact: If there is a voltage difference between the PSE power supplies and there are other PD loads connected to
the PSEs, there is a possibility for significant power to flow from one PSE port to the other, up to the class current
level of the supplying port. Power is coupled into the receiving device through the body diode of its port MOSFET.
The energy dissipated in the forward bias of this diode causes heating in the receiving device, possibly leading to
damage. The receiving device is not aware of the power flow into it from its port and has no means to control it.
Mitigation/Workaround: Prevention of damage is not guaranteed. Therefore, it is strongly advised not to connect
Si3452 PSE ports together in this manner.
Rev. 1.5
27
Si3452
INT
VOUT1
RST
DET1
AD1
GND12
AD0
DET2
VOUT2
VEE2
40
39
38
37
36
35
34
33
32
31
9. Pin Descriptions
VEE1
1
30
VDD
VEE
2
29
DGND
VREF
3
28
AD0
AIN
4
27
AD1
AOUT
5
26
AD2
AGND
6
25
AD2
RBIAS
7
24
AD3
AGND
8
23
RST
NC
9
22
VEE3
VEE4
10
21
AD3
11
12
13
14
15
16
17
18
19
20
NC
VOUT4
DET4
SDA
GND34
SCL
NC
DET3
VDD
VOUT3
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Si3452
(Top View)
Table 25. Si3452 Pin Descriptions
Pin #
Name
Type
VEE1
Supply
Driver 1 VEE supply. Short to VEE, VEE2/3/4.
VEE
Supply
Global PoE (–48 V nom.) or PoE+ (–54 V nom.) supply. Short to VEE1/2/3/4.
VREF
Analog input
1.1 V nom. voltage reference from reference generator (for example, TLV431 or
power management unit).
AIN
Analog input
Measurement data converter input. Short to AOUT.
AOUT
Analog output
Measurement multiplexer subsystem output. Short to AIN.
AGND
Ground
Analog ground reference. Short to AGND pin 8, GND12/34, DGND.
RBIAS
Analog input
External 44.2 kΩ (±1%) resistor to ground sets internal bias currents.
8
AGND
Ground
Analog ground reference. Short to AGND pin 6, GND12/34, DGND.
9
NC
No connect
10
VEE4
Supply
11
NC
No connect
Do not connect (float).
12
VOUT4
Analog I/O
Port 4 power FET switch output. When on, provides a low impedance path to
VEE4.
1
2
3
4
5
6
7
28
Description
Do not connect (float).
Driver 4 VEE supply. Short to VEE, VEE1/2/3.
Rev. 1.5
Si3452
Table 25. Si3452 Pin Descriptions (Continued)
Pin #
Name
Type
Description
13
DET4
Analog I/O
Connection for port 4 detection, classification, and transient surge protection. This
pin is tied to VOUT4.
14
SDA
Digital I/O
I2C data pin
15
GND34
Ground
16
SCL
Digital I/O
17
NC
No connect
Do not connect (float).
18
DET3
Analog I/O
Connection for port 3 detection and classification. See DET4 for detailed description.
I2C clock pin
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19
Ground supply for protection clamps. Short to AGND, GND12, DGND.
VDD
Supply
VOUT3
Analog I/O
Port 3 power FET switch output. When on, provides a low impedance path to
VEE3.
AD3
Digital I/O
Chip address bit 3 pin, read after reset. Address set with defined resistor dividers.
Pin also used for internal communications. Short to AD3 pin 24.
VEE3
Supply
RST
Digital input
AD3
Digital I/O
Chip address bit 3 pin, read after reset. Address set with a 10 kpull-up or pulldown resistor. Also used for internal communications. Short to AD3 pin 21.
AD2
Digital I/O
Chip address bit 2 pin, read after reset. Address set with a 10 kpull-up or pulldown resistor. Also used for internal communications. Short to AD2 pin 26.
AD2
Digital I/O
Chip address bit 2 pin, read after reset. Address set with a 10 kpull-up or pulldown resistor. Also used for internal communications. Short to AD2 pin 25.
AD1
Digital I/O
Chip address bit 1 pin, read after reset. Address set with a 10 kpull-up or pulldown resistor. Also used for internal communications. Short to AD1 pin 36.
AD0
Digital I/O
Chip address bit 0 pin, read after reset. Address set with a 10 kpull-up or pulldown resistor. Also used for internal communications. Short to AD0 pin 34.
DGND
Ground
Digital ground reference. Short to AGND, GND12/34
VDD
Supply
+3.3 V isolated supply. Short to VDD pin 19.
31
VEE2
Supply
Driver 2 VEE supply. Short to VEE, VEE1/3/4.
32
VOUT2
Analog I/O
Port 2 power FET switch output. When on, provides a low impedance path to
VEE2.
33
DET2
Analog I/O
Connection for port 2 detection and classification. See DET4 for detailed description.
34
AD0
Digital I/O
Chip address bit 0 pin. See description for- and short to AD0 pin 28.
35
GND12
Ground
36
AD1
Digital I/O
20
21
22
23
24
25
26
27
28
29
30
+3.3 V (±10%) isolated supply. Short to VDD pin 30.
Driver 3 VEE supply. Short to VEE, VEE1/2/4.
Active low digital reset. Short to RST pin 38.
Ground supply for protection clamps. Short to AGND, GND34, DGND.
Chip address bit 1 pin. See description for- and short to AD1 pin 27.
Rev. 1.5
29
Si3452
Table 25. Si3452 Pin Descriptions (Continued)
Pin #
Name
Type
Description
37
DET1
Analog I/O
Connection for port 1 detection and classification. See DET4 for detailed description.
38
RST
Digital input
Active low digital reset. Short to RST pin 23.
39
VOUT1
Analog I/O
Port 1 power FET switch output. When on, provides a low impedance path to
VEE1.
40
INT
Digital output
ePAD
Vee
Supply
Active low interrupt output pin.
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Connect the thermal pad to a plane which connects to Vee. For best results, use a
5 x 5 or larger via array for best thermal conductivity with 1 square inch or larger
of plane area per device.
30
Rev. 1.5
Si3452
10. Package Outline: 40-Pin QFN
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The Si3452 is packaged in an industry-standard, RoHS compliant 6 x 6 mm2, 40-pin QFN package.
Figure 7. 40-Pin QFN Mechanical Diagram
Table 26. Package Diagram Dimensions
Dimension
Min
Nom
Max
A
0.80
0.85
0.90
A1
0.00
0.02
0.05
b
0.18
0.25
0.30
D
D2
6.00 BSC.
3.95
4.10
e
0.50 BSC.
E
6.00 BSC.
4.25
E2
3.95
4.10
4.25
L
0.30
0.40
0.50
aaa
0.10
bbb
0.10
ccc
0.08
ddd
0.10
eee
0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, Variation VJJD-2
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for
Small Body Components.
Rev. 1.5
31
Si3452
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11. Recommended PCB Footprint
Figure 8. PCB Land Pattern
Table 27. PCB Land Pattern Dimensions
Dimension
Min
Max
Dimension
Min
Max
C1
5.80
5.90
X2
4.10
4.20
C2
5.80
5.90
Y1
0.75
0.85
Y2
4.10
4.20
e
X1
0.50 BSC
0.15
0.25
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimension and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-SM-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is
calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the
metal pad is to be 60 m minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure
good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
9. A 4x4 array of 0.80 mm square openings on a 1.05 mm pitch should be used for the center ground pad.
Card Assembly
10. A No-Clean, Type-3 solder paste is recommended.
11. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
32
Rev. 1.5
Si3452
12. Ordering Guide
Ordering Part Number1
Detect
Timing
Powerup Mode2,3,4,5
2,5
Si3452-B02-GM
Alt A
Si3452A-B02-GM
Alt A
Si3452B-B02-GM
Alt B
Si3452C-B02-GM
Alt A
Si3452D-B02-GM
Alt B
PoE7
Firmware
Revision
Package6
Temp. Range
0.2.81
–40 to 85 °C
ambient
Shutdown
PoE (15.4 W)
Auto
PoE+ (30 W)
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Notes:
1. Add “R” to the end of the ordering part number to denote tape-and-reel option. E.g., Si3452-B02-GMR.
2. For alternative A, power is applied to wire pairs 1,2 and 3,6. For alternative B, power is applied to wire pairs 4,5 and 7,8
(the spare pairs in the case of 10/100 Ethernet). Conventionally, alternative B is used for midspan power injectors. For
alternative B, detection is done with over 2 seconds between detection pulses so as to avoid interfering with end-point
equipment trying to provide power using alternative A.
3. Devices powering up into shutdown mode are intended for use with a system host that provides run-time configuration
or power-management.
4. The maximum PoE or PoE+ power applies to all ports on Auto mode devices.
5. Detect Timing and Powerup Modes (PoE vs. PoE+, Shutdown vs. Auto) are pre-configured in firmware but can be
reconfigured at any time via a host connection.
6. All devices are packaged in RoHS-compliant, 40-pin, 6x6 mm QFN.
7. The Si3452-B02-GM is PoE+ capable. The part defaults to PoE mode at powerup but can be reconfigured to PoE+ via
register settings.
12.1. Evaluation Kits and Reference Designs
Part Number
Description
Related Ethernet Chipset
Type
Si3452MS8-KIT
PoE+ 8-port Midspan PSE evaluation kit.
Includes PC-control interface, PD loads,
and cables.
None
Evaluation Kit
Si3452V1-RD*
PoE/PoE+ 24-port daughtercard
Vitesse E-StaX (VSC7407)
Reference Design
Si3452V2-RD*
PoE+ 8-port Gb-Ethernet switch
Vitesse SparX-G8e (VSC7398)
Reference Design
Si3452M1-RD*
PoE/PoE+ 24-port daughtercard
Marvell Prestera-DX, xCAT
Reference Design
*Note: Due to unique high-voltage and high-power design considerations, Silicon Laboratories recommends that the
reference designs be followed very closely for both bill of materials and layout. Please visit the Silicon Labs technical
support web page at www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to request support for
your design, particularly if you are not closely following the recommended reference design.
Rev. 1.5
33
Si3452
13. Device Marking Diagram
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Figure 9. Device Marking Diagram
Table 28. Device Marking Table
Line #
1
2
2
3
4
34
Text Value
Description
Si3452
Base part number. This is not the “Ordering Part Number” since it does not contain a
specific revision. Refer to "12. Ordering Guide" on page 33 for complete ordering
information.
XZZ
X = Device revision.
ZZ = Firmware revision.
GM
G = Industrial temperature range.
M = QFN package.
TTTTTT
Trace code (assigned by the assembly subcontractor).
O
Pin 1 identifier.
YY
Assembly year.
WW
Assembly week.
Rev. 1.5
Si3452
DOCUMENT CHANGE LIST
Revision 1.0 to Revision 1.1
Updated “GM” parts temperature range to –40 to
+85 °C, eliminating the need for the -IM ordering part
numbers. Contact Silicon Labs for date code
information if needed.
Revision 1.1 to Revision 1.2
Removed references to Si3453 throughout.
Updated Figure 9, “Device Marking Diagram,” on
page 34.
Updated typical VDD reset threshold in Table 3 on
page 5.
Clarified notes in Table 19, “Si3452 Register Map,”
on page 20.
Updated Table 28, “Device Marking Table,” on
page 34.
Clarified notes in "12. Ordering Guide" on page 33.
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Revision 1.2 to Revision 1.3
Updated "8. Firmware Release Notes" on page 27.
Updated "11. Recommended PCB Footprint" on
page 32.
Updated Table 27, “PCB Land Pattern Dimensions,”
on page 32.
Updated "12. Ordering Guide" on page 33.
Updated "12.1. Evaluation Kits and Reference
Designs" on page 33.
Revision 1.3 to Revision 1.4
Added “Not Recommended for New Designs”
watermark.
Added guidance on I2C register command write
delays.
Updated "8. Firmware Release Notes" on page 27
regarding Sifos "Vtrans_min" test.
Revision 1.4 to Revision 1.5
Updated "8. Firmware Release Notes" on page 27
regarding PSE-to-PSE Cross Powering Possibility.
Rev. 1.5
35
Si3452
CONTACT INFORMATION
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Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
https://www.siliconlabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
Patent Notice
Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analogintensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where
personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized
application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
36
Rev. 1.5
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